imx6: backport ahci support
[openwrt.git] / target / linux / imx6 / patches-3.10 / 0007-ARM-dtsi-enable-ahci-sata-on-imx6q-platforms.patch
1 From 0fb1f804269e549b556b475c8655bc862c220622 Mon Sep 17 00:00:00 2001
2 From: Richard Zhu <r65037@freescale.com>
3 Date: Tue, 16 Jul 2013 11:28:46 +0800
4 Subject: [PATCH] ARM: dtsi: enable ahci sata on imx6q platforms
5
6 Only imx6q has the ahci sata controller, enable
7 it on imx6q platforms.
8
9 Signed-off-by: Richard Zhu <r65037@freescale.com>
10 Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
11 ---
12  arch/arm/boot/dts/imx6q-sabreauto.dts | 4 ++++
13  arch/arm/boot/dts/imx6q-sabrelite.dts | 4 ++++
14  arch/arm/boot/dts/imx6q-sabresd.dts   | 4 ++++
15  arch/arm/boot/dts/imx6q.dtsi          | 9 +++++++++
16  4 files changed, 21 insertions(+)
17
18 --- a/arch/arm/boot/dts/imx6q-sabreauto.dts
19 +++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
20 @@ -33,3 +33,7 @@
21                 };
22         };
23  };
24 +
25 +&sata {
26 +       status = "okay";
27 +};
28 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts
29 +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
30 @@ -65,6 +65,10 @@
31         };
32  };
33  
34 +&sata {
35 +       status = "okay";
36 +};
37 +
38  &ecspi1 {
39         fsl,spi-num-chipselects = <1>;
40         cs-gpios = <&gpio3 19 0>;
41 --- a/arch/arm/boot/dts/imx6q-sabresd.dts
42 +++ b/arch/arm/boot/dts/imx6q-sabresd.dts
43 @@ -37,3 +37,7 @@
44                 };
45         };
46  };
47 +
48 +&sata {
49 +       status = "okay";
50 +};
51 --- a/arch/arm/boot/dts/imx6q.dtsi
52 +++ b/arch/arm/boot/dts/imx6q.dtsi
53 @@ -332,6 +332,15 @@
54                         };
55                 };
56  
57 +               sata: sata@02200000 {
58 +                       compatible = "fsl,imx6q-ahci";
59 +                       reg = <0x02200000 0x4000>;
60 +                       interrupts = <0 39 0x04>;
61 +                       clocks =  <&clks 154>, <&clks 187>, <&clks 105>;
62 +                       clock-names = "sata", "sata_ref", "ahb";
63 +                       status = "disabled";
64 +               };
65 +
66                 ipu2: ipu@02800000 {
67                         #crtc-cells = <1>;
68                         compatible = "fsl,imx6q-ipu";