1 From 9e54eae23bc9cca0d8a955018c35b1250e09a73a Mon Sep 17 00:00:00 2001
2 From: Richard Zhu <r65037@freescale.com>
3 Date: Wed, 24 Jul 2013 14:15:29 +0800
4 Subject: [PATCH] ahci_imx: add ahci sata support on imx platforms
6 imx6q contains one Synopsys AHCI SATA controller, But it can't share
7 ahci_platform driver with other controllers because there are some
8 misalignments of the generic AHCI controller - the bits definitions of
9 the HBA registers, the Vendor Specific registers, the AHCI PHY clock
10 and the AHCI signals adjustment window(GPR13 register).
12 - CAP_SSS(bit20) of the HOST_CAP is writable, default value is '0',
13 should be configured to be '1'
15 - bit0 (only one AHCI SATA port on imx6q) of the HOST_PORTS_IMPL
16 should be set to be '1'.(default 0)
18 - One Vendor Specific register HOST_TIMER1MS(offset:0xe0) should be
19 configured regarding to the frequency of AHB bus clock.
21 - Configurations of the AHCI PHY clock, and the signal parameters of
24 Setup its own ahci sata driver, contained the imx6q specific
25 initialized codes, re-use the generic ahci_platform driver, and keep
26 the generic ahci_platform driver clean as much as possible.
28 tj: patch description reformatted
30 Signed-off-by: Richard Zhu <r65037@freescale.com>
31 Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
32 Signed-off-by: Tejun Heo <tj@kernel.org>
34 drivers/ata/Kconfig | 9 ++
35 drivers/ata/Makefile | 1 +
36 drivers/ata/ahci_imx.c | 236 +++++++++++++++++++++++++++++++++++++++++++++++++
37 3 files changed, 246 insertions(+)
38 create mode 100644 drivers/ata/ahci_imx.c
40 --- a/drivers/ata/Kconfig
41 +++ b/drivers/ata/Kconfig
42 @@ -97,6 +97,15 @@ config SATA_AHCI_PLATFORM
47 + tristate "Freescale i.MX AHCI SATA support"
48 + depends on SATA_AHCI_PLATFORM
50 + This option enables support for the Freescale i.MX SoC's
56 tristate "Freescale 3.0Gbps SATA support"
58 --- a/drivers/ata/Makefile
59 +++ b/drivers/ata/Makefile
60 @@ -10,6 +10,7 @@ obj-$(CONFIG_SATA_INIC162X) += sata_inic
61 obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
62 obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
63 obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
64 +obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
67 obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
69 +++ b/drivers/ata/ahci_imx.c
72 + * Freescale IMX AHCI SATA platform driver
73 + * Copyright 2013 Freescale Semiconductor, Inc.
75 + * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
77 + * This program is free software; you can redistribute it and/or modify it
78 + * under the terms and conditions of the GNU General Public License,
79 + * version 2, as published by the Free Software Foundation.
81 + * This program is distributed in the hope it will be useful, but WITHOUT
82 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
83 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
86 + * You should have received a copy of the GNU General Public License along with
87 + * this program. If not, see <http://www.gnu.org/licenses/>.
90 +#include <linux/kernel.h>
91 +#include <linux/module.h>
92 +#include <linux/platform_device.h>
93 +#include <linux/regmap.h>
94 +#include <linux/ahci_platform.h>
95 +#include <linux/of_device.h>
96 +#include <linux/mfd/syscon.h>
97 +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
101 + HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
104 +struct imx_ahci_priv {
105 + struct platform_device *ahci_pdev;
106 + struct clk *sata_ref_clk;
107 + struct clk *ahb_clk;
108 + struct regmap *gpr;
111 +static int imx6q_sata_init(struct device *dev, void __iomem *mmio)
114 + unsigned int reg_val;
115 + struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
118 + syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
119 + if (IS_ERR(imxpriv->gpr)) {
120 + dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
121 + return PTR_ERR(imxpriv->gpr);
124 + ret = clk_prepare_enable(imxpriv->sata_ref_clk);
126 + dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret);
131 + * set PHY Paremeters, two steps to configure the GPR13,
132 + * one write for rest of parameters, mask of first write
133 + * is 0x07fffffd, and the other one write for setting
136 + regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
137 + | IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
138 + | IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
139 + | IMX6Q_GPR13_SATA_SPD_MODE_MASK
140 + | IMX6Q_GPR13_SATA_MPLL_SS_EN
141 + | IMX6Q_GPR13_SATA_TX_ATTEN_MASK
142 + | IMX6Q_GPR13_SATA_TX_BOOST_MASK
143 + | IMX6Q_GPR13_SATA_TX_LVL_MASK
144 + | IMX6Q_GPR13_SATA_TX_EDGE_RATE
145 + , IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
146 + | IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
147 + | IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
148 + | IMX6Q_GPR13_SATA_SPD_MODE_3P0G
149 + | IMX6Q_GPR13_SATA_MPLL_SS_EN
150 + | IMX6Q_GPR13_SATA_TX_ATTEN_9_16
151 + | IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
152 + | IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
153 + regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
154 + IMX6Q_GPR13_SATA_MPLL_CLK_EN);
155 + usleep_range(100, 200);
158 + * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
159 + * and IP vendor specific register HOST_TIMER1MS.
160 + * Configure CAP_SSS (support stagered spin up).
161 + * Implement the port0.
162 + * Get the ahb clock rate, and configure the TIMER1MS register.
164 + reg_val = readl(mmio + HOST_CAP);
165 + if (!(reg_val & HOST_CAP_SSS)) {
166 + reg_val |= HOST_CAP_SSS;
167 + writel(reg_val, mmio + HOST_CAP);
169 + reg_val = readl(mmio + HOST_PORTS_IMPL);
170 + if (!(reg_val & 0x1)) {
172 + writel(reg_val, mmio + HOST_PORTS_IMPL);
175 + reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
176 + writel(reg_val, mmio + HOST_TIMER1MS);
181 +static void imx6q_sata_exit(struct device *dev)
183 + struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
185 + regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
186 + !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
187 + clk_disable_unprepare(imxpriv->sata_ref_clk);
190 +static struct ahci_platform_data imx6q_sata_pdata = {
191 + .init = imx6q_sata_init,
192 + .exit = imx6q_sata_exit,
195 +static const struct of_device_id imx_ahci_of_match[] = {
196 + { .compatible = "fsl,imx6q-ahci", .data = &imx6q_sata_pdata},
199 +MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
201 +static int imx_ahci_probe(struct platform_device *pdev)
203 + struct device *dev = &pdev->dev;
204 + struct resource *mem, *irq, res[2];
205 + const struct of_device_id *of_id;
206 + const struct ahci_platform_data *pdata = NULL;
207 + struct imx_ahci_priv *imxpriv;
208 + struct device *ahci_dev;
209 + struct platform_device *ahci_pdev;
212 + imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
214 + dev_err(dev, "can't alloc ahci_host_priv\n");
218 + ahci_pdev = platform_device_alloc("ahci", -1);
222 + ahci_dev = &ahci_pdev->dev;
223 + ahci_dev->parent = dev;
225 + imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
226 + if (IS_ERR(imxpriv->ahb_clk)) {
227 + dev_err(dev, "can't get ahb clock.\n");
228 + ret = PTR_ERR(imxpriv->ahb_clk);
232 + imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
233 + if (IS_ERR(imxpriv->sata_ref_clk)) {
234 + dev_err(dev, "can't get sata_ref clock.\n");
235 + ret = PTR_ERR(imxpriv->sata_ref_clk);
239 + imxpriv->ahci_pdev = ahci_pdev;
240 + platform_set_drvdata(pdev, imxpriv);
242 + of_id = of_match_device(imx_ahci_of_match, dev);
244 + pdata = of_id->data;
250 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
251 + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
252 + if (!mem || !irq) {
253 + dev_err(dev, "no mmio/irq resource\n");
261 + ahci_dev->coherent_dma_mask = DMA_BIT_MASK(32);
262 + ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
263 + ahci_dev->of_node = dev->of_node;
265 + ret = platform_device_add_resources(ahci_pdev, res, 2);
269 + ret = platform_device_add_data(ahci_pdev, pdata, sizeof(*pdata));
273 + ret = platform_device_add(ahci_pdev);
276 + platform_device_put(ahci_pdev);
283 +static int imx_ahci_remove(struct platform_device *pdev)
285 + struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
286 + struct platform_device *ahci_pdev = imxpriv->ahci_pdev;
288 + platform_device_unregister(ahci_pdev);
292 +static struct platform_driver imx_ahci_driver = {
293 + .probe = imx_ahci_probe,
294 + .remove = imx_ahci_remove,
296 + .name = "ahci-imx",
297 + .owner = THIS_MODULE,
298 + .of_match_table = imx_ahci_of_match,
301 +module_platform_driver(imx_ahci_driver);
303 +MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
304 +MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
305 +MODULE_LICENSE("GPL");
306 +MODULE_ALIAS("ahci:imx");