target/linux/ifxmips/files/arch/mips/danube/interrupt.c

   1 /*
   2  *   arch/mips/danube/interrupt.c
   3  *
   4  *   This program is free software; you can redistribute it and/or modify
   5  *   it under the terms of the GNU General Public License as published by
   6  *   the Free Software Foundation; either version 2 of the License, or
   7  *   (at your option) any later version.
   8  *
   9  *   This program is distributed in the hope that it will be useful,
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *   GNU General Public License for more details.
  13  *
  14  *   You should have received a copy of the GNU General Public License
  15  *   along with this program; if not, write to the Free Software
  16  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  17  *
  18  *   Copyright (C) 2005 Wu Qi Ming infineon
  19  *
  20  *   Rewrite of Infineon Danube code, thanks to infineon for the support,
  21  *   software and hardware
  22  *
  23  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
  24  *
  25  */
  26
  27 #include <linux/init.h>
  28 #include <linux/sched.h>
  29 #include <linux/slab.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/kernel_stat.h>
  32 #include <linux/module.h>
  33
  34 #include <asm/bootinfo.h>
  35 #include <asm/irq.h>
  36 #include <asm/danube/danube.h>
  37 #include <asm/danube/danube_irq.h>
  38 #include <asm/irq_cpu.h>
  39
  40
  41 void
  42 disable_danube_irq (unsigned int irq_nr)
  43 {
  44         int i;
  45         u32 *danube_ier = IFXMIPS_ICU_IM0_IER;
  46
  47         irq_nr -= INT_NUM_IRQ0;
  48         for (i = 0; i <= 4; i++)
  49         {
  50                 if (irq_nr < INT_NUM_IM_OFFSET){
  51                         writel(readl(danube_ier) & ~(1 << irq_nr ), danube_ier);
  52                         return;
  53                 }
  54                 danube_ier += IFXMIPS_ICU_OFFSET;
  55                 irq_nr -= INT_NUM_IM_OFFSET;
  56         }
  57 }
  58 EXPORT_SYMBOL (disable_danube_irq);
  59
  60 void
  61 mask_and_ack_danube_irq (unsigned int irq_nr)
  62 {
  63         int i;
  64         u32 *danube_ier = IFXMIPS_ICU_IM0_IER;
  65         u32 *danube_isr = IFXMIPS_ICU_IM0_ISR;
  66
  67         irq_nr -= INT_NUM_IRQ0;
  68         for (i = 0; i <= 4; i++)
  69         {
  70                 if (irq_nr < INT_NUM_IM_OFFSET)
  71                 {
  72                         writel(readl(danube_ier) & ~(1 << irq_nr ), danube_ier);
  73                         writel((1 << irq_nr ), danube_isr);
  74                         return;
  75                 }
  76                 danube_ier += IFXMIPS_ICU_OFFSET;
  77                 danube_isr += IFXMIPS_ICU_OFFSET;
  78                 irq_nr -= INT_NUM_IM_OFFSET;
  79         }
  80 }
  81 EXPORT_SYMBOL (mask_and_ack_danube_irq);
  82
  83 void
  84 enable_danube_irq (unsigned int irq_nr)
  85 {
  86         int i;
  87         u32 *danube_ier = IFXMIPS_ICU_IM0_IER;
  88
  89         irq_nr -= INT_NUM_IRQ0;
  90         for (i = 0; i <= 4; i++)
  91         {
  92                 if (irq_nr < INT_NUM_IM_OFFSET)
  93                 {
  94                         writel(readl(danube_ier) | (1 << irq_nr ), danube_ier);
  95                         return;
  96                 }
  97                 danube_ier += IFXMIPS_ICU_OFFSET;
  98                 irq_nr -= INT_NUM_IM_OFFSET;
  99         }
 100 }
 101 EXPORT_SYMBOL (enable_danube_irq);
 102
 103 static unsigned int
 104 startup_danube_irq (unsigned int irq)
 105 {
 106         enable_danube_irq (irq);
 107         return 0;
 108 }
 109
 110 static void
 111 end_danube_irq (unsigned int irq)
 112 {
 113         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 114                 enable_danube_irq (irq);
 115 }
 116
 117 static struct hw_interrupt_type danube_irq_type = {
 118         "IFXMIPS",
 119         .startup = startup_danube_irq,
 120         .enable = enable_danube_irq,
 121         .disable = disable_danube_irq,
 122         .unmask = enable_danube_irq,
 123         .ack = end_danube_irq,
 124         .mask = disable_danube_irq,
 125         .mask_ack = mask_and_ack_danube_irq,
 126         .end = end_danube_irq,
 127 };
 128
 129 static inline int
 130 ls1bit32(unsigned long x)
 131 {
 132         __asm__ (
 133                 "       .set    push                                    \n"
 134                 "       .set    mips32                                  \n"
 135                 "       clz     %0, %1                                  \n"
 136                 "       .set    pop                                     \n"
 137                 : "=r" (x)
 138                 : "r" (x));
 139
 140                 return 31 - x;
 141 }
 142
 143 void
 144 danube_hw_irqdispatch (int module)
 145 {
 146         u32 irq;
 147
 148         irq = readl(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
 149         if (irq == 0)
 150                 return;
 151
 152         irq = ls1bit32 (irq);
 153         do_IRQ ((int) irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
 154
 155         if ((irq == 22) && (module == 0)){
 156                 writel(readl(IFXMIPS_EBU_PCC_ISTAT) | 0x10, IFXMIPS_EBU_PCC_ISTAT);
 157         }
 158 }
 159
 160 asmlinkage void
 161 plat_irq_dispatch (void)
 162 {
 163         unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 164         unsigned int i;
 165
 166         if (pending & CAUSEF_IP7){
 167                 do_IRQ(MIPS_CPU_TIMER_IRQ);
 168                 goto out;
 169         } else {
 170                 for (i = 0; i < 5; i++)
 171                 {
 172                         if (pending & (CAUSEF_IP2 << i))
 173                         {
 174                                 danube_hw_irqdispatch(i);
 175                                 goto out;
 176                         }
 177                 }
 178         }
 179         printk("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
 180
 181 out:
 182         return;
 183 }
 184
 185 static struct irqaction cascade = {
 186         .handler = no_action,
 187         .flags = IRQF_DISABLED,
 188         .name = "cascade",
 189 };
 190
 191 void __init
 192 arch_init_irq(void)
 193 {
 194         int i;
 195
 196         for (i = 0; i < 5; i++)
 197         {
 198                 writel(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
 199         }
 200
 201         mips_cpu_irq_init();
 202
 203         for (i = 2; i <= 6; i++)
 204         {
 205                 setup_irq(i, &cascade);
 206         }
 207
 208         for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
 209         {
 210 #if 0
 211                 irq_desc[i].status = IRQ_DISABLED;
 212                 irq_desc[i].action = NULL;
 213                 irq_desc[i].depth = 1;
 214 #endif
 215                 set_irq_chip_and_handler(i, &danube_irq_type, handle_level_irq);
 216         }
 217
 218         set_c0_status (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
 219 }