target/linux/generic/patches-3.3/020-ssb_update.patch

   1 --- a/drivers/ssb/b43_pci_bridge.c
   2 +++ b/drivers/ssb/b43_pci_bridge.c
   3 @@ -29,11 +29,14 @@ static const struct pci_device_id b43_pc
   4         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
   5         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
   6         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
   7 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4322) },
   8 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43222) },
   9         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
  10         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
  11         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
  12         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
  13         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
  14 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
  15         { 0, },
  16  };
  17  MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
  18 --- a/drivers/ssb/driver_chipcommon_pmu.c
  19 +++ b/drivers/ssb/driver_chipcommon_pmu.c
  20 @@ -13,6 +13,9 @@
  21  #include <linux/ssb/ssb_driver_chipcommon.h>
  22  #include <linux/delay.h>
  23  #include <linux/export.h>
  24 +#ifdef CONFIG_BCM47XX
  25 +#include <asm/mach-bcm47xx/nvram.h>
  26 +#endif
  27
  28  #include "ssb_private.h"
  29
  30 @@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct s
  31         u32 pmuctl, tmp, pllctl;
  32         unsigned int i;
  33
  34 -       if ((bus->chip_id == 0x5354) && !crystalfreq) {
  35 -               /* The 5354 crystal freq is 25MHz */
  36 -               crystalfreq = 25000;
  37 -       }
  38         if (crystalfreq)
  39                 e = pmu0_plltab_find_entry(crystalfreq);
  40         if (!e)
  41 @@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_
  42         u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
  43
  44         if (bus->bustype == SSB_BUSTYPE_SSB) {
  45 -               /* TODO: The user may override the crystal frequency. */
  46 +#ifdef CONFIG_BCM47XX
  47 +               char buf[20];
  48 +               if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
  49 +                       crystalfreq = simple_strtoul(buf, NULL, 0);
  50 +#endif
  51         }
  52
  53         switch (bus->chip_id) {
  54 @@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_
  55                 ssb_pmu1_pllinit_r0(cc, crystalfreq);
  56                 break;
  57         case 0x4328:
  58 +               ssb_pmu0_pllinit_r0(cc, crystalfreq);
  59 +               break;
  60         case 0x5354:
  61 +               if (crystalfreq == 0)
  62 +                       crystalfreq = 25000;
  63                 ssb_pmu0_pllinit_r0(cc, crystalfreq);
  64                 break;
  65         case 0x4322:
  66 @@ -607,3 +614,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
  67
  68  EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
  69  EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
  70 +
  71 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
  72 +{
  73 +       struct ssb_bus *bus = cc->dev->bus;
  74 +
  75 +       switch (bus->chip_id) {
  76 +       case 0x5354:
  77 +               /* 5354 chip uses a non programmable PLL of frequency 240MHz */
  78 +               return 240000000;
  79 +       default:
  80 +               ssb_printk(KERN_ERR PFX
  81 +                          "ERROR: PMU cpu clock unknown for device %04X\n",
  82 +                          bus->chip_id);
  83 +               return 0;
  84 +       }
  85 +}
  86 +
  87 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
  88 +{
  89 +       struct ssb_bus *bus = cc->dev->bus;
  90 +
  91 +       switch (bus->chip_id) {
  92 +       case 0x5354:
  93 +               return 120000000;
  94 +       default:
  95 +               ssb_printk(KERN_ERR PFX
  96 +                          "ERROR: PMU controlclock unknown for device %04X\n",
  97 +                          bus->chip_id);
  98 +               return 0;
  99 +       }
 100 +}
 101 --- a/drivers/ssb/driver_mipscore.c
 102 +++ b/drivers/ssb/driver_mipscore.c
 103 @@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
 104         struct ssb_bus *bus = mcore->dev->bus;
 105         u32 pll_type, n, m, rate = 0;
 106
 107 +       if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
 108 +               return ssb_pmu_get_cpu_clock(&bus->chipco);
 109 +
 110         if (bus->extif.dev) {
 111                 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
 112         } else if (bus->chipco.dev) {
 113 --- a/drivers/ssb/main.c
 114 +++ b/drivers/ssb/main.c
 115 @@ -140,19 +140,6 @@ static void ssb_device_put(struct ssb_de
 116                 put_device(dev->dev);
 117  }
 118
 119 -static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
 120 -{
 121 -       if (drv)
 122 -               get_driver(&drv->drv);
 123 -       return drv;
 124 -}
 125 -
 126 -static inline void ssb_driver_put(struct ssb_driver *drv)
 127 -{
 128 -       if (drv)
 129 -               put_driver(&drv->drv);
 130 -}
 131 -
 132  static int ssb_device_resume(struct device *dev)
 133  {
 134         struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
 135 @@ -250,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
 136                         ssb_device_put(sdev);
 137                         continue;
 138                 }
 139 -               sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
 140 -               if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
 141 -                       ssb_device_put(sdev);
 142 +               sdrv = drv_to_ssb_drv(sdev->dev->driver);
 143 +               if (SSB_WARN_ON(!sdrv->remove))
 144                         continue;
 145 -               }
 146                 sdrv->remove(sdev);
 147                 ctx->device_frozen[i] = 1;
 148         }
 149 @@ -293,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
 150                                    dev_name(sdev->dev));
 151                         result = err;
 152                 }
 153 -               ssb_driver_put(sdrv);
 154                 ssb_device_put(sdev);
 155         }
 156
 157 @@ -1094,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
 158         u32 plltype;
 159         u32 clkctl_n, clkctl_m;
 160
 161 +       if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
 162 +               return ssb_pmu_get_controlclock(&bus->chipco);
 163 +
 164         if (ssb_extif_available(&bus->extif))
 165                 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
 166                                            &clkctl_n, &clkctl_m);
 167 --- a/drivers/ssb/pci.c
 168 +++ b/drivers/ssb/pci.c
 169 @@ -178,6 +178,18 @@ err_pci:
 170  #define SPEX(_outvar, _offset, _mask, _shift) \
 171         SPEX16(_outvar, _offset, _mask, _shift)
 172
 173 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift)    \
 174 +       do {    \
 175 +               SPEX(_field[0], _offset +  0, _mask, _shift);   \
 176 +               SPEX(_field[1], _offset +  2, _mask, _shift);   \
 177 +               SPEX(_field[2], _offset +  4, _mask, _shift);   \
 178 +               SPEX(_field[3], _offset +  6, _mask, _shift);   \
 179 +               SPEX(_field[4], _offset +  8, _mask, _shift);   \
 180 +               SPEX(_field[5], _offset + 10, _mask, _shift);   \
 181 +               SPEX(_field[6], _offset + 12, _mask, _shift);   \
 182 +               SPEX(_field[7], _offset + 14, _mask, _shift);   \
 183 +       } while (0)
 184 +
 185
 186  static inline u8 ssb_crc8(u8 crc, u8 data)
 187  {
 188 @@ -331,7 +343,6 @@ static void sprom_extract_r123(struct ss
 189  {
 190         int i;
 191         u16 v;
 192 -       s8 gain;
 193         u16 loc[3];
 194
 195         if (out->revision == 3)                 /* rev 3 moved MAC */
 196 @@ -361,8 +372,9 @@ static void sprom_extract_r123(struct ss
 197         SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
 198         SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
 199         SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
 200 -       SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
 201 -            SSB_SPROM1_BINF_CCODE_SHIFT);
 202 +       if (out->revision == 1)
 203 +               SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
 204 +                    SSB_SPROM1_BINF_CCODE_SHIFT);
 205         SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
 206              SSB_SPROM1_BINF_ANTA_SHIFT);
 207         SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
 208 @@ -388,22 +400,16 @@ static void sprom_extract_r123(struct ss
 209         SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
 210         if (out->revision >= 2)
 211                 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
 212 +       SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
 213 +       SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
 214
 215         /* Extract the antenna gain values. */
 216 -       gain = r123_extract_antgain(out->revision, in,
 217 -                                   SSB_SPROM1_AGAIN_BG,
 218 -                                   SSB_SPROM1_AGAIN_BG_SHIFT);
 219 -       out->antenna_gain.ghz24.a0 = gain;
 220 -       out->antenna_gain.ghz24.a1 = gain;
 221 -       out->antenna_gain.ghz24.a2 = gain;
 222 -       out->antenna_gain.ghz24.a3 = gain;
 223 -       gain = r123_extract_antgain(out->revision, in,
 224 -                                   SSB_SPROM1_AGAIN_A,
 225 -                                   SSB_SPROM1_AGAIN_A_SHIFT);
 226 -       out->antenna_gain.ghz5.a0 = gain;
 227 -       out->antenna_gain.ghz5.a1 = gain;
 228 -       out->antenna_gain.ghz5.a2 = gain;
 229 -       out->antenna_gain.ghz5.a3 = gain;
 230 +       out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
 231 +                                                   SSB_SPROM1_AGAIN_BG,
 232 +                                                   SSB_SPROM1_AGAIN_BG_SHIFT);
 233 +       out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
 234 +                                                   SSB_SPROM1_AGAIN_A,
 235 +                                                   SSB_SPROM1_AGAIN_A_SHIFT);
 236  }
 237
 238  /* Revs 4 5 and 8 have partially shared layout */
 239 @@ -464,14 +470,17 @@ static void sprom_extract_r45(struct ssb
 240         SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
 241         SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
 242              SSB_SPROM4_ETHPHY_ET1A_SHIFT);
 243 +       SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
 244         if (out->revision == 4) {
 245 -               SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
 246 +               SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
 247 +               SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
 248                 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
 249                 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
 250                 SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
 251                 SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
 252         } else {
 253 -               SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
 254 +               SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
 255 +               SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
 256                 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
 257                 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
 258                 SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
 259 @@ -504,16 +513,14 @@ static void sprom_extract_r45(struct ssb
 260         }
 261
 262         /* Extract the antenna gain values. */
 263 -       SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
 264 +       SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
 265              SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
 266 -       SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
 267 +       SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
 268              SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
 269 -       SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
 270 +       SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
 271              SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
 272 -       SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
 273 +       SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
 274              SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
 275 -       memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
 276 -              sizeof(out->antenna_gain.ghz5));
 277
 278         sprom_extract_r458(out, in);
 279
 280 @@ -523,14 +530,22 @@ static void sprom_extract_r45(struct ssb
 281  static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
 282  {
 283         int i;
 284 -       u16 v;
 285 +       u16 v, o;
 286 +       u16 pwr_info_offset[] = {
 287 +               SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
 288 +               SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
 289 +       };
 290 +       BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
 291 +                       ARRAY_SIZE(out->core_pwr_info));
 292
 293         /* extract the MAC address */
 294         for (i = 0; i < 3; i++) {
 295                 v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
 296                 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
 297         }
 298 -       SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
 299 +       SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
 300 +       SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
 301 +       SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
 302         SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
 303         SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
 304         SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
 305 @@ -596,16 +611,46 @@ static void sprom_extract_r8(struct ssb_
 306         SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
 307
 308         /* Extract the antenna gain values. */
 309 -       SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
 310 +       SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
 311              SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
 312 -       SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
 313 +       SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
 314              SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
 315 -       SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
 316 +       SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
 317              SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
 318 -       SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
 319 +       SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
 320              SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
 321 -       memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
 322 -              sizeof(out->antenna_gain.ghz5));
 323 +
 324 +       /* Extract cores power info info */
 325 +       for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
 326 +               o = pwr_info_offset[i];
 327 +               SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
 328 +                       SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
 329 +               SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
 330 +                       SSB_SPROM8_2G_MAXP, 0);
 331 +
 332 +               SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
 333 +               SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
 334 +               SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
 335 +
 336 +               SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
 337 +                       SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
 338 +               SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
 339 +                       SSB_SPROM8_5G_MAXP, 0);
 340 +               SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
 341 +                       SSB_SPROM8_5GH_MAXP, 0);
 342 +               SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
 343 +                       SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
 344 +
 345 +               SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
 346 +               SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
 347 +               SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
 348 +               SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
 349 +               SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
 350 +               SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
 351 +               SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
 352 +               SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
 353 +               SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
 354 +       }
 355
 356         /* Extract FEM info */
 357         SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
 358 @@ -630,6 +675,63 @@ static void sprom_extract_r8(struct ssb_
 359         SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
 360                 SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
 361
 362 +       SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
 363 +            SSB_SPROM8_LEDDC_ON_SHIFT);
 364 +       SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
 365 +            SSB_SPROM8_LEDDC_OFF_SHIFT);
 366 +
 367 +       SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
 368 +            SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
 369 +       SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
 370 +            SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
 371 +       SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
 372 +            SSB_SPROM8_TXRXC_SWITCH_SHIFT);
 373 +
 374 +       SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
 375 +
 376 +       SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
 377 +       SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
 378 +       SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
 379 +       SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
 380 +
 381 +       SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
 382 +            SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
 383 +       SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
 384 +            SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
 385 +       SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
 386 +            SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
 387 +            SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
 388 +       SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
 389 +            SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
 390 +       SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
 391 +            SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
 392 +            SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
 393 +       SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
 394 +            SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
 395 +            SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
 396 +       SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
 397 +            SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
 398 +            SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
 399 +       SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
 400 +            SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
 401 +
 402 +       SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
 403 +       SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
 404 +       SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
 405 +       SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
 406 +
 407 +       SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
 408 +            SSB_SPROM8_THERMAL_TRESH_SHIFT);
 409 +       SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
 410 +            SSB_SPROM8_THERMAL_OFFSET_SHIFT);
 411 +       SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
 412 +            SSB_SPROM8_TEMPDELTA_PHYCAL,
 413 +            SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
 414 +       SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
 415 +            SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
 416 +       SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
 417 +            SSB_SPROM8_TEMPDELTA_HYSTERESIS,
 418 +            SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
 419         sprom_extract_r458(out, in);
 420
 421         /* TODO - get remaining rev 8 stuff needed */
 422 @@ -759,7 +861,6 @@ static void ssb_pci_get_boardinfo(struct
 423  {
 424         bi->vendor = bus->host_pci->subsystem_vendor;
 425         bi->type = bus->host_pci->subsystem_device;
 426 -       bi->rev = bus->host_pci->revision;
 427  }
 428
 429  int ssb_pci_get_invariants(struct ssb_bus *bus,
 430 --- a/drivers/ssb/pcmcia.c
 431 +++ b/drivers/ssb/pcmcia.c
 432 @@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
 433         case SSB_PCMCIA_CIS_ANTGAIN:
 434                 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
 435                         "antg tpl size");
 436 -               sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
 437 -               sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
 438 -               sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
 439 -               sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
 440 -               sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
 441 -               sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
 442 -               sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
 443 -               sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
 444 +               sprom->antenna_gain.a0 = tuple->TupleData[1];
 445 +               sprom->antenna_gain.a1 = tuple->TupleData[1];
 446 +               sprom->antenna_gain.a2 = tuple->TupleData[1];
 447 +               sprom->antenna_gain.a3 = tuple->TupleData[1];
 448                 break;
 449         case SSB_PCMCIA_CIS_BFLAGS:
 450                 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
 451 --- a/drivers/ssb/scan.c
 452 +++ b/drivers/ssb/scan.c
 453 @@ -90,6 +90,8 @@ const char *ssb_core_name(u16 coreid)
 454                 return "ARM 1176";
 455         case SSB_DEV_ARM_7TDMI:
 456                 return "ARM 7TDMI";
 457 +       case SSB_DEV_ARM_CM3:
 458 +               return "ARM Cortex M3";
 459         }
 460         return "UNKNOWN";
 461  }
 462 @@ -318,6 +320,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
 463                         bus->chip_package = 0;
 464                 }
 465         }
 466 +       ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
 467 +                  "package 0x%02X\n", bus->chip_id, bus->chip_rev,
 468 +                  bus->chip_package);
 469         if (!bus->nr_devices)
 470                 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
 471         if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
 472 --- a/drivers/ssb/sdio.c
 473 +++ b/drivers/ssb/sdio.c
 474 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
 475                         case SSB_SDIO_CIS_ANTGAIN:
 476                                 GOTO_ERROR_ON(tuple->size != 2,
 477                                               "antg tpl size");
 478 -                               sprom->antenna_gain.ghz24.a0 = tuple->data[1];
 479 -                               sprom->antenna_gain.ghz24.a1 = tuple->data[1];
 480 -                               sprom->antenna_gain.ghz24.a2 = tuple->data[1];
 481 -                               sprom->antenna_gain.ghz24.a3 = tuple->data[1];
 482 -                               sprom->antenna_gain.ghz5.a0 = tuple->data[1];
 483 -                               sprom->antenna_gain.ghz5.a1 = tuple->data[1];
 484 -                               sprom->antenna_gain.ghz5.a2 = tuple->data[1];
 485 -                               sprom->antenna_gain.ghz5.a3 = tuple->data[1];
 486 +                               sprom->antenna_gain.a0 = tuple->data[1];
 487 +                               sprom->antenna_gain.a1 = tuple->data[1];
 488 +                               sprom->antenna_gain.a2 = tuple->data[1];
 489 +                               sprom->antenna_gain.a3 = tuple->data[1];
 490                                 break;
 491                         case SSB_SDIO_CIS_BFLAGS:
 492                                 GOTO_ERROR_ON((tuple->size != 3) &&
 493 --- a/drivers/ssb/ssb_private.h
 494 +++ b/drivers/ssb/ssb_private.h
 495 @@ -207,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
 496  }
 497  #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
 498
 499 +/* driver_chipcommon_pmu.c */
 500 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
 501 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
 502 +
 503  #endif /* LINUX_SSB_PRIVATE_H_ */
 504 --- a/include/linux/ssb/ssb.h
 505 +++ b/include/linux/ssb/ssb.h
 506 @@ -16,6 +16,12 @@ struct pcmcia_device;
 507  struct ssb_bus;
 508  struct ssb_driver;
 509
 510 +struct ssb_sprom_core_pwr_info {
 511 +       u8 itssi_2g, itssi_5g;
 512 +       u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
 513 +       u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
 514 +};
 515 +
 516  struct ssb_sprom {
 517         u8 revision;
 518         u8 il0mac[6];           /* MAC address for 802.11b/g */
 519 @@ -26,9 +32,12 @@ struct ssb_sprom {
 520         u8 et0mdcport;          /* MDIO for enet0 */
 521         u8 et1mdcport;          /* MDIO for enet1 */
 522         u16 board_rev;          /* Board revision number from SPROM. */
 523 +       u16 board_num;          /* Board number from SPROM. */
 524 +       u16 board_type;         /* Board type from SPROM. */
 525         u8 country_code;        /* Country Code */
 526 -       u16 leddc_on_time;      /* LED Powersave Duty Cycle On Count */
 527 -       u16 leddc_off_time;     /* LED Powersave Duty Cycle Off Count */
 528 +       char alpha2[2];         /* Country Code as two chars like EU or US */
 529 +       u8 leddc_on_time;       /* LED Powersave Duty Cycle On Count */
 530 +       u8 leddc_off_time;      /* LED Powersave Duty Cycle Off Count */
 531         u8 ant_available_a;     /* 2GHz antenna available bits (up to 4) */
 532         u8 ant_available_bg;    /* 5GHz antenna available bits (up to 4) */
 533         u16 pa0b0;
 534 @@ -47,10 +56,10 @@ struct ssb_sprom {
 535         u8 gpio1;               /* GPIO pin 1 */
 536         u8 gpio2;               /* GPIO pin 2 */
 537         u8 gpio3;               /* GPIO pin 3 */
 538 -       u16 maxpwr_bg;          /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
 539 -       u16 maxpwr_al;          /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
 540 -       u16 maxpwr_a;           /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
 541 -       u16 maxpwr_ah;          /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
 542 +       u8 maxpwr_bg;           /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
 543 +       u8 maxpwr_al;           /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
 544 +       u8 maxpwr_a;            /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
 545 +       u8 maxpwr_ah;           /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
 546         u8 itssi_a;             /* Idle TSSI Target for A-PHY */
 547         u8 itssi_bg;            /* Idle TSSI Target for B/G-PHY */
 548         u8 tri2g;               /* 2.4GHz TX isolation */
 549 @@ -61,8 +70,8 @@ struct ssb_sprom {
 550         u8 txpid5gl[4];         /* 4.9 - 5.1GHz TX power index */
 551         u8 txpid5g[4];          /* 5.1 - 5.5GHz TX power index */
 552         u8 txpid5gh[4];         /* 5.5 - ...GHz TX power index */
 553 -       u8 rxpo2g;              /* 2GHz RX power offset */
 554 -       u8 rxpo5g;              /* 5GHz RX power offset */
 555 +       s8 rxpo2g;              /* 2GHz RX power offset */
 556 +       s8 rxpo5g;              /* 5GHz RX power offset */
 557         u8 rssisav2g;           /* 2GHz RSSI params */
 558         u8 rssismc2g;
 559         u8 rssismf2g;
 560 @@ -82,16 +91,13 @@ struct ssb_sprom {
 561         u16 boardflags2_hi;     /* Board flags (bits 48-63) */
 562         /* TODO store board flags in a single u64 */
 563
 564 +       struct ssb_sprom_core_pwr_info core_pwr_info[4];
 565 +
 566         /* Antenna gain values for up to 4 antennas
 567          * on each band. Values in dBm/4 (Q5.2). Negative gain means the
 568          * loss in the connectors is bigger than the gain. */
 569         struct {
 570 -               struct {
 571 -                       s8 a0, a1, a2, a3;
 572 -               } ghz24;        /* 2.4GHz band */
 573 -               struct {
 574 -                       s8 a0, a1, a2, a3;
 575 -               } ghz5;         /* 5GHz band */
 576 +               s8 a0, a1, a2, a3;
 577         } antenna_gain;
 578
 579         struct {
 580 @@ -103,14 +109,85 @@ struct ssb_sprom {
 581                 } ghz5;
 582         } fem;
 583
 584 -       /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
 585 +       u16 mcs2gpo[8];
 586 +       u16 mcs5gpo[8];
 587 +       u16 mcs5glpo[8];
 588 +       u16 mcs5ghpo[8];
 589 +       u8 opo;
 590 +
 591 +       u8 rxgainerr2ga[3];
 592 +       u8 rxgainerr5gla[3];
 593 +       u8 rxgainerr5gma[3];
 594 +       u8 rxgainerr5gha[3];
 595 +       u8 rxgainerr5gua[3];
 596 +
 597 +       u8 noiselvl2ga[3];
 598 +       u8 noiselvl5gla[3];
 599 +       u8 noiselvl5gma[3];
 600 +       u8 noiselvl5gha[3];
 601 +       u8 noiselvl5gua[3];
 602 +
 603 +       u8 regrev;
 604 +       u8 txchain;
 605 +       u8 rxchain;
 606 +       u8 antswitch;
 607 +       u16 cddpo;
 608 +       u16 stbcpo;
 609 +       u16 bw40po;
 610 +       u16 bwduppo;
 611 +
 612 +       u8 tempthresh;
 613 +       u8 tempoffset;
 614 +       u16 rawtempsense;
 615 +       u8 measpower;
 616 +       u8 tempsense_slope;
 617 +       u8 tempcorrx;
 618 +       u8 tempsense_option;
 619 +       u8 freqoffset_corr;
 620 +       u8 iqcal_swp_dis;
 621 +       u8 hw_iqcal_en;
 622 +       u8 elna2g;
 623 +       u8 elna5g;
 624 +       u8 phycal_tempdelta;
 625 +       u8 temps_period;
 626 +       u8 temps_hysteresis;
 627 +       u8 measpower1;
 628 +       u8 measpower2;
 629 +       u8 pcieingress_war;
 630 +
 631 +       /* power per rate from sromrev 9 */
 632 +       u16 cckbw202gpo;
 633 +       u16 cckbw20ul2gpo;
 634 +       u32 legofdmbw202gpo;
 635 +       u32 legofdmbw20ul2gpo;
 636 +       u32 legofdmbw205glpo;
 637 +       u32 legofdmbw20ul5glpo;
 638 +       u32 legofdmbw205gmpo;
 639 +       u32 legofdmbw20ul5gmpo;
 640 +       u32 legofdmbw205ghpo;
 641 +       u32 legofdmbw20ul5ghpo;
 642 +       u32 mcsbw202gpo;
 643 +       u32 mcsbw20ul2gpo;
 644 +       u32 mcsbw402gpo;
 645 +       u32 mcsbw205glpo;
 646 +       u32 mcsbw20ul5glpo;
 647 +       u32 mcsbw405glpo;
 648 +       u32 mcsbw205gmpo;
 649 +       u32 mcsbw20ul5gmpo;
 650 +       u32 mcsbw405gmpo;
 651 +       u32 mcsbw205ghpo;
 652 +       u32 mcsbw20ul5ghpo;
 653 +       u32 mcsbw405ghpo;
 654 +       u16 mcs32po;
 655 +       u16 legofdm40duppo;
 656 +       u8 sar2g;
 657 +       u8 sar5g;
 658  };
 659
 660  /* Information about the PCB the circuitry is soldered on. */
 661  struct ssb_boardinfo {
 662         u16 vendor;
 663         u16 type;
 664 -       u8  rev;
 665  };
 666
 667
 668 @@ -166,6 +243,7 @@ struct ssb_bus_ops {
 669  #define SSB_DEV_MINI_MACPHY    0x823
 670  #define SSB_DEV_ARM_1176       0x824
 671  #define SSB_DEV_ARM_7TDMI      0x825
 672 +#define SSB_DEV_ARM_CM3                0x82A
 673
 674  /* Vendor-ID values */
 675  #define SSB_VENDOR_BROADCOM    0x4243
 676 --- a/include/linux/ssb/ssb_driver_gige.h
 677 +++ b/include/linux/ssb/ssb_driver_gige.h
 678 @@ -2,6 +2,7 @@
 679  #define LINUX_SSB_DRIVER_GIGE_H_
 680
 681  #include <linux/ssb/ssb.h>
 682 +#include <linux/bug.h>
 683  #include <linux/pci.h>
 684  #include <linux/spinlock.h>
 685
 686 --- a/include/linux/ssb/ssb_regs.h
 687 +++ b/include/linux/ssb/ssb_regs.h
 688 @@ -228,6 +228,7 @@
 689  #define  SSB_SPROM1_AGAIN_BG_SHIFT     0
 690  #define  SSB_SPROM1_AGAIN_A            0xFF00  /* A-PHY */
 691  #define  SSB_SPROM1_AGAIN_A_SHIFT      8
 692 +#define SSB_SPROM1_CCODE               0x0076
 693
 694  /* SPROM Revision 2 (inherits from rev 1) */
 695  #define SSB_SPROM2_BFLHI               0x0038  /* Boardflags (high 16 bits) */
 696 @@ -267,6 +268,7 @@
 697  #define  SSB_SPROM3_OFDMGPO            0x107A  /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
 698
 699  /* SPROM Revision 4 */
 700 +#define SSB_SPROM4_BOARDREV            0x0042  /* Board revision */
 701  #define SSB_SPROM4_BFLLO               0x0044  /* Boardflags (low 16 bits) */
 702  #define SSB_SPROM4_BFLHI               0x0046  /* Board Flags Hi */
 703  #define SSB_SPROM4_BFL2LO              0x0048  /* Board flags 2 (low 16 bits) */
 704 @@ -389,6 +391,11 @@
 705  #define  SSB_SPROM8_GPIOB_P2           0x00FF  /* Pin 2 */
 706  #define  SSB_SPROM8_GPIOB_P3           0xFF00  /* Pin 3 */
 707  #define  SSB_SPROM8_GPIOB_P3_SHIFT     8
 708 +#define SSB_SPROM8_LEDDC               0x009A
 709 +#define  SSB_SPROM8_LEDDC_ON           0xFF00  /* oncount */
 710 +#define  SSB_SPROM8_LEDDC_ON_SHIFT     8
 711 +#define  SSB_SPROM8_LEDDC_OFF          0x00FF  /* offcount */
 712 +#define  SSB_SPROM8_LEDDC_OFF_SHIFT    0
 713  #define SSB_SPROM8_ANTAVAIL            0x009C  /* Antenna available bitfields*/
 714  #define  SSB_SPROM8_ANTAVAIL_A         0xFF00  /* A-PHY bitfield */
 715  #define  SSB_SPROM8_ANTAVAIL_A_SHIFT   8
 716 @@ -404,6 +411,13 @@
 717  #define  SSB_SPROM8_AGAIN2_SHIFT       0
 718  #define  SSB_SPROM8_AGAIN3             0xFF00  /* Antenna 3 */
 719  #define  SSB_SPROM8_AGAIN3_SHIFT       8
 720 +#define SSB_SPROM8_TXRXC               0x00A2
 721 +#define  SSB_SPROM8_TXRXC_TXCHAIN      0x000f
 722 +#define  SSB_SPROM8_TXRXC_TXCHAIN_SHIFT        0
 723 +#define  SSB_SPROM8_TXRXC_RXCHAIN      0x00f0
 724 +#define  SSB_SPROM8_TXRXC_RXCHAIN_SHIFT        4
 725 +#define  SSB_SPROM8_TXRXC_SWITCH       0xff00
 726 +#define  SSB_SPROM8_TXRXC_SWITCH_SHIFT 8
 727  #define SSB_SPROM8_RSSIPARM2G          0x00A4  /* RSSI params for 2GHz */
 728  #define  SSB_SPROM8_RSSISMF2G          0x000F
 729  #define  SSB_SPROM8_RSSISMC2G          0x00F0
 730 @@ -430,6 +444,7 @@
 731  #define  SSB_SPROM8_TRI5GH_SHIFT       8
 732  #define SSB_SPROM8_RXPO                        0x00AC  /* RX power offsets */
 733  #define  SSB_SPROM8_RXPO2G             0x00FF  /* 2GHz RX power offset */
 734 +#define  SSB_SPROM8_RXPO2G_SHIFT       0
 735  #define  SSB_SPROM8_RXPO5G             0xFF00  /* 5GHz RX power offset */
 736  #define  SSB_SPROM8_RXPO5G_SHIFT       8
 737  #define SSB_SPROM8_FEM2G               0x00AE
 738 @@ -445,10 +460,71 @@
 739  #define  SSB_SROM8_FEM_ANTSWLUT                0xF800
 740  #define  SSB_SROM8_FEM_ANTSWLUT_SHIFT  11
 741  #define SSB_SPROM8_THERMAL             0x00B2
 742 -#define SSB_SPROM8_MPWR_RAWTS          0x00B4
 743 -#define SSB_SPROM8_TS_SLP_OPT_CORRX    0x00B6
 744 -#define SSB_SPROM8_FOC_HWIQ_IQSWP      0x00B8
 745 -#define SSB_SPROM8_PHYCAL_TEMPDELTA    0x00BA
 746 +#define  SSB_SPROM8_THERMAL_OFFSET     0x00ff
 747 +#define  SSB_SPROM8_THERMAL_OFFSET_SHIFT       0
 748 +#define  SSB_SPROM8_THERMAL_TRESH      0xff00
 749 +#define  SSB_SPROM8_THERMAL_TRESH_SHIFT        8
 750 +/* Temp sense related entries */
 751 +#define SSB_SPROM8_RAWTS               0x00B4
 752 +#define  SSB_SPROM8_RAWTS_RAWTEMP      0x01ff
 753 +#define  SSB_SPROM8_RAWTS_RAWTEMP_SHIFT        0
 754 +#define  SSB_SPROM8_RAWTS_MEASPOWER    0xfe00
 755 +#define  SSB_SPROM8_RAWTS_MEASPOWER_SHIFT      9
 756 +#define SSB_SPROM8_OPT_CORRX           0x00B6
 757 +#define  SSB_SPROM8_OPT_CORRX_TEMP_SLOPE       0x00ff
 758 +#define  SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT 0
 759 +#define  SSB_SPROM8_OPT_CORRX_TEMPCORRX        0xfc00
 760 +#define  SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT  10
 761 +#define  SSB_SPROM8_OPT_CORRX_TEMP_OPTION      0x0300
 762 +#define  SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT        8
 763 +/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
 764 +#define SSB_SPROM8_HWIQ_IQSWP          0x00B8
 765 +#define  SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR       0x000f
 766 +#define  SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT 0
 767 +#define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP       0x0010
 768 +#define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
 769 +#define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL        0x0020
 770 +#define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT  5
 771 +#define SSB_SPROM8_TEMPDELTA           0x00BA
 772 +#define  SSB_SPROM8_TEMPDELTA_PHYCAL   0x00ff
 773 +#define  SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT     0
 774 +#define  SSB_SPROM8_TEMPDELTA_PERIOD   0x0f00
 775 +#define  SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT     8
 776 +#define  SSB_SPROM8_TEMPDELTA_HYSTERESIS       0xf000
 777 +#define  SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT 12
 778 +
 779 +/* There are 4 blocks with power info sharing the same layout */
 780 +#define SSB_SROM8_PWR_INFO_CORE0       0x00C0
 781 +#define SSB_SROM8_PWR_INFO_CORE1       0x00E0
 782 +#define SSB_SROM8_PWR_INFO_CORE2       0x0100
 783 +#define SSB_SROM8_PWR_INFO_CORE3       0x0120
 784 +
 785 +#define SSB_SROM8_2G_MAXP_ITSSI                0x00
 786 +#define  SSB_SPROM8_2G_MAXP            0x00FF
 787 +#define  SSB_SPROM8_2G_ITSSI           0xFF00
 788 +#define  SSB_SPROM8_2G_ITSSI_SHIFT     8
 789 +#define SSB_SROM8_2G_PA_0              0x02    /* 2GHz power amp settings */
 790 +#define SSB_SROM8_2G_PA_1              0x04
 791 +#define SSB_SROM8_2G_PA_2              0x06
 792 +#define SSB_SROM8_5G_MAXP_ITSSI                0x08    /* 5GHz ITSSI and 5.3GHz Max Power */
 793 +#define  SSB_SPROM8_5G_MAXP            0x00FF
 794 +#define  SSB_SPROM8_5G_ITSSI           0xFF00
 795 +#define  SSB_SPROM8_5G_ITSSI_SHIFT     8
 796 +#define SSB_SPROM8_5GHL_MAXP           0x0A    /* 5.2GHz and 5.8GHz Max Power */
 797 +#define  SSB_SPROM8_5GH_MAXP           0x00FF
 798 +#define  SSB_SPROM8_5GL_MAXP           0xFF00
 799 +#define  SSB_SPROM8_5GL_MAXP_SHIFT     8
 800 +#define SSB_SROM8_5G_PA_0              0x0C    /* 5.3GHz power amp settings */
 801 +#define SSB_SROM8_5G_PA_1              0x0E
 802 +#define SSB_SROM8_5G_PA_2              0x10
 803 +#define SSB_SROM8_5GL_PA_0             0x12    /* 5.2GHz power amp settings */
 804 +#define SSB_SROM8_5GL_PA_1             0x14
 805 +#define SSB_SROM8_5GL_PA_2             0x16
 806 +#define SSB_SROM8_5GH_PA_0             0x18    /* 5.8GHz power amp settings */
 807 +#define SSB_SROM8_5GH_PA_1             0x1A
 808 +#define SSB_SROM8_5GH_PA_2             0x1C
 809 +
 810 +/* TODO: Make it deprecated */
 811  #define SSB_SPROM8_MAXP_BG             0x00C0  /* Max Power 2GHz in path 1 */
 812  #define  SSB_SPROM8_MAXP_BG_MASK       0x00FF  /* Mask for Max Power 2GHz */
 813  #define  SSB_SPROM8_ITSSI_BG           0xFF00  /* Mask for path 1 itssi_bg */
 814 @@ -473,12 +549,23 @@
 815  #define SSB_SPROM8_PA1HIB0             0x00D8  /* 5.8GHz power amp settings */
 816  #define SSB_SPROM8_PA1HIB1             0x00DA
 817  #define SSB_SPROM8_PA1HIB2             0x00DC
 818 +
 819  #define SSB_SPROM8_CCK2GPO             0x0140  /* CCK power offset */
 820  #define SSB_SPROM8_OFDM2GPO            0x0142  /* 2.4GHz OFDM power offset */
 821  #define SSB_SPROM8_OFDM5GPO            0x0146  /* 5.3GHz OFDM power offset */
 822  #define SSB_SPROM8_OFDM5GLPO           0x014A  /* 5.2GHz OFDM power offset */
 823  #define SSB_SPROM8_OFDM5GHPO           0x014E  /* 5.8GHz OFDM power offset */
 824
 825 +#define SSB_SPROM8_2G_MCSPO            0x0152
 826 +#define SSB_SPROM8_5G_MCSPO            0x0162
 827 +#define SSB_SPROM8_5GL_MCSPO           0x0172
 828 +#define SSB_SPROM8_5GH_MCSPO           0x0182
 829 +
 830 +#define SSB_SPROM8_CDDPO               0x0192
 831 +#define SSB_SPROM8_STBCPO              0x0194
 832 +#define SSB_SPROM8_BW40PO              0x0196
 833 +#define SSB_SPROM8_BWDUPPO             0x0198
 834 +
 835  /* Values for boardflags_lo read from SPROM */
 836  #define SSB_BFL_BTCOEXIST              0x0001  /* implements Bluetooth coexistance */
 837  #define SSB_BFL_PACTRL                 0x0002  /* GPIO 9 controlling the PA */