target/linux/generic/patches-3.3/020-ssb_update.patch

   1 --- a/arch/mips/bcm47xx/nvram.c
   2 +++ b/arch/mips/bcm47xx/nvram.c
   3 @@ -43,8 +43,8 @@ static void early_nvram_init(void)
   4  #ifdef CONFIG_BCM47XX_SSB
   5         case BCM47XX_BUS_TYPE_SSB:
   6                 mcore_ssb = &bcm47xx_bus.ssb.mipscore;
   7 -               base = mcore_ssb->flash_window;
   8 -               lim = mcore_ssb->flash_window_size;
   9 +               base = mcore_ssb->pflash.window;
  10 +               lim = mcore_ssb->pflash.window_size;
  11                 break;
  12  #endif
  13  #ifdef CONFIG_BCM47XX_BCMA
  14 --- a/arch/mips/bcm47xx/wgt634u.c
  15 +++ b/arch/mips/bcm47xx/wgt634u.c
  16 @@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
  17                                             SSB_CHIPCO_IRQ_GPIO);
  18                 }
  19
  20 -               wgt634u_flash_data.width = mcore->flash_buswidth;
  21 -               wgt634u_flash_resource.start = mcore->flash_window;
  22 -               wgt634u_flash_resource.end = mcore->flash_window
  23 -                                          + mcore->flash_window_size
  24 +               wgt634u_flash_data.width = mcore->pflash.buswidth;
  25 +               wgt634u_flash_resource.start = mcore->pflash.window;
  26 +               wgt634u_flash_resource.end = mcore->pflash.window
  27 +                                          + mcore->pflash.window_size
  28                                            - 1;
  29                 return platform_add_devices(wgt634u_devices,
  30                                             ARRAY_SIZE(wgt634u_devices));
  31 --- a/drivers/ssb/Kconfig
  32 +++ b/drivers/ssb/Kconfig
  33 @@ -136,10 +136,15 @@ config SSB_DRIVER_MIPS
  34
  35           If unsure, say N
  36
  37 +config SSB_SFLASH
  38 +       bool "SSB serial flash support"
  39 +       depends on SSB_DRIVER_MIPS
  40 +       default y
  41 +
  42  # Assumption: We are on embedded, if we compile the MIPS core.
  43  config SSB_EMBEDDED
  44         bool
  45 -       depends on SSB_DRIVER_MIPS
  46 +       depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE
  47         default y
  48
  49  config SSB_DRIVER_EXTIF
  50 @@ -160,4 +165,12 @@ config SSB_DRIVER_GIGE
  51
  52           If unsure, say N
  53
  54 +config SSB_DRIVER_GPIO
  55 +       bool "SSB GPIO driver"
  56 +       depends on SSB && GPIOLIB
  57 +       help
  58 +         Driver to provide access to the GPIO pins on the bus.
  59 +
  60 +         If unsure, say N
  61 +
  62  endmenu
  63 --- a/drivers/ssb/Makefile
  64 +++ b/drivers/ssb/Makefile
  65 @@ -11,10 +11,12 @@ ssb-$(CONFIG_SSB_SDIOHOST)          += sdio.o
  66  # built-in drivers
  67  ssb-y                                  += driver_chipcommon.o
  68  ssb-y                                  += driver_chipcommon_pmu.o
  69 +ssb-$(CONFIG_SSB_SFLASH)               += driver_chipcommon_sflash.o
  70  ssb-$(CONFIG_SSB_DRIVER_MIPS)          += driver_mipscore.o
  71  ssb-$(CONFIG_SSB_DRIVER_EXTIF)         += driver_extif.o
  72  ssb-$(CONFIG_SSB_DRIVER_PCICORE)       += driver_pcicore.o
  73  ssb-$(CONFIG_SSB_DRIVER_GIGE)          += driver_gige.o
  74 +ssb-$(CONFIG_SSB_DRIVER_GPIO)          += driver_gpio.o
  75
  76  # b43 pci-ssb-bridge driver
  77  # Not strictly a part of SSB, but kept here for convenience
  78 --- a/drivers/ssb/b43_pci_bridge.c
  79 +++ b/drivers/ssb/b43_pci_bridge.c
  80 @@ -29,11 +29,15 @@ static const struct pci_device_id b43_pc
  81         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
  82         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
  83         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
  84 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4322) },
  85 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43222) },
  86         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
  87         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
  88         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
  89         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
  90         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
  91 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
  92 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
  93         { 0, },
  94  };
  95  MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
  96 --- a/drivers/ssb/driver_chipcommon.c
  97 +++ b/drivers/ssb/driver_chipcommon.c
  98 @@ -4,6 +4,7 @@
  99   *
 100   * Copyright 2005, Broadcom Corporation
 101   * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
 102 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
 103   *
 104   * Licensed under the GNU/GPL. See COPYING for details.
 105   */
 106 @@ -12,6 +13,7 @@
 107  #include <linux/ssb/ssb_regs.h>
 108  #include <linux/export.h>
 109  #include <linux/pci.h>
 110 +#include <linux/bcm47xx_wdt.h>
 111
 112  #include "ssb_private.h"
 113
 114 @@ -280,13 +282,79 @@ static void calc_fast_powerup_delay(stru
 115         cc->fast_pwrup_delay = tmp;
 116  }
 117
 118 +static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
 119 +{
 120 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
 121 +               return ssb_pmu_get_alp_clock(cc);
 122 +
 123 +       return 20000000;
 124 +}
 125 +
 126 +static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
 127 +{
 128 +       u32 nb;
 129 +
 130 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 131 +               if (cc->dev->id.revision < 26)
 132 +                       nb = 16;
 133 +               else
 134 +                       nb = (cc->dev->id.revision >= 37) ? 32 : 24;
 135 +       } else {
 136 +               nb = 28;
 137 +       }
 138 +       if (nb == 32)
 139 +               return 0xffffffff;
 140 +       else
 141 +               return (1 << nb) - 1;
 142 +}
 143 +
 144 +u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
 145 +{
 146 +       struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
 147 +
 148 +       if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
 149 +               return 0;
 150 +
 151 +       return ssb_chipco_watchdog_timer_set(cc, ticks);
 152 +}
 153 +
 154 +u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
 155 +{
 156 +       struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
 157 +       u32 ticks;
 158 +
 159 +       if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
 160 +               return 0;
 161 +
 162 +       ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
 163 +       return ticks / cc->ticks_per_ms;
 164 +}
 165 +
 166 +static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
 167 +{
 168 +       struct ssb_bus *bus = cc->dev->bus;
 169 +
 170 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 171 +                       /* based on 32KHz ILP clock */
 172 +                       return 32;
 173 +       } else {
 174 +               if (cc->dev->id.revision < 18)
 175 +                       return ssb_clockspeed(bus) / 1000;
 176 +               else
 177 +                       return ssb_chipco_alp_clock(cc) / 1000;
 178 +       }
 179 +}
 180 +
 181  void ssb_chipcommon_init(struct ssb_chipcommon *cc)
 182  {
 183         if (!cc->dev)
 184                 return; /* We don't have a ChipCommon */
 185 +
 186 +       spin_lock_init(&cc->gpio_lock);
 187 +
 188         if (cc->dev->id.revision >= 11)
 189                 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
 190 -       ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
 191 +       ssb_dbg("chipcommon status is 0x%x\n", cc->status);
 192
 193         if (cc->dev->id.revision >= 20) {
 194                 chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
 195 @@ -297,6 +365,11 @@ void ssb_chipcommon_init(struct ssb_chip
 196         chipco_powercontrol_init(cc);
 197         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
 198         calc_fast_powerup_delay(cc);
 199 +
 200 +       if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
 201 +               cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
 202 +               cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
 203 +       }
 204  }
 205
 206  void ssb_chipco_suspend(struct ssb_chipcommon *cc)
 207 @@ -395,10 +468,27 @@ void ssb_chipco_timing_init(struct ssb_c
 208  }
 209
 210  /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
 211 -void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
 212 +u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
 213  {
 214 -       /* instant NMI */
 215 -       chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
 216 +       u32 maxt;
 217 +       enum ssb_clkmode clkmode;
 218 +
 219 +       maxt = ssb_chipco_watchdog_get_max_timer(cc);
 220 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 221 +               if (ticks == 1)
 222 +                       ticks = 2;
 223 +               else if (ticks > maxt)
 224 +                       ticks = maxt;
 225 +               chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
 226 +       } else {
 227 +               clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
 228 +               ssb_chipco_set_clockmode(cc, clkmode);
 229 +               if (ticks > maxt)
 230 +                       ticks = maxt;
 231 +               /* instant NMI */
 232 +               chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
 233 +       }
 234 +       return ticks;
 235  }
 236
 237  void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 238 @@ -418,28 +508,93 @@ u32 ssb_chipco_gpio_in(struct ssb_chipco
 239
 240  u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
 241  {
 242 -       return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
 243 +       unsigned long flags;
 244 +       u32 res = 0;
 245 +
 246 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 247 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
 248 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 249 +
 250 +       return res;
 251  }
 252
 253  u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
 254  {
 255 -       return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
 256 +       unsigned long flags;
 257 +       u32 res = 0;
 258 +
 259 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 260 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
 261 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 262 +
 263 +       return res;
 264  }
 265
 266  u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
 267  {
 268 -       return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
 269 +       unsigned long flags;
 270 +       u32 res = 0;
 271 +
 272 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 273 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
 274 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 275 +
 276 +       return res;
 277  }
 278  EXPORT_SYMBOL(ssb_chipco_gpio_control);
 279
 280  u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 281  {
 282 -       return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
 283 +       unsigned long flags;
 284 +       u32 res = 0;
 285 +
 286 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 287 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
 288 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 289 +
 290 +       return res;
 291  }
 292
 293  u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
 294  {
 295 -       return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
 296 +       unsigned long flags;
 297 +       u32 res = 0;
 298 +
 299 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 300 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
 301 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 302 +
 303 +       return res;
 304 +}
 305 +
 306 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value)
 307 +{
 308 +       unsigned long flags;
 309 +       u32 res = 0;
 310 +
 311 +       if (cc->dev->id.revision < 20)
 312 +               return 0xffffffff;
 313 +
 314 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 315 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value);
 316 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 317 +
 318 +       return res;
 319 +}
 320 +
 321 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value)
 322 +{
 323 +       unsigned long flags;
 324 +       u32 res = 0;
 325 +
 326 +       if (cc->dev->id.revision < 20)
 327 +               return 0xffffffff;
 328 +
 329 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 330 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value);
 331 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 332 +
 333 +       return res;
 334  }
 335
 336  #ifdef CONFIG_SSB_SERIAL
 337 @@ -473,12 +628,7 @@ int ssb_chipco_serial_init(struct ssb_ch
 338                                        chipco_read32(cc, SSB_CHIPCO_CORECTL)
 339                                        | SSB_CHIPCO_CORECTL_UARTCLK0);
 340                 } else if ((ccrev >= 11) && (ccrev != 15)) {
 341 -                       /* Fixed ALP clock */
 342 -                       baud_base = 20000000;
 343 -                       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 344 -                               /* FIXME: baud_base is different for devices with a PMU */
 345 -                               SSB_WARN_ON(1);
 346 -                       }
 347 +                       baud_base = ssb_chipco_alp_clock(cc);
 348                         div = 1;
 349                         if (ccrev >= 21) {
 350                                 /* Turn off UART clock before switching clocksource. */
 351 --- a/drivers/ssb/driver_chipcommon_pmu.c
 352 +++ b/drivers/ssb/driver_chipcommon_pmu.c
 353 @@ -13,6 +13,9 @@
 354  #include <linux/ssb/ssb_driver_chipcommon.h>
 355  #include <linux/delay.h>
 356  #include <linux/export.h>
 357 +#ifdef CONFIG_BCM47XX
 358 +#include <asm/mach-bcm47xx/nvram.h>
 359 +#endif
 360
 361  #include "ssb_private.h"
 362
 363 @@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct s
 364         u32 pmuctl, tmp, pllctl;
 365         unsigned int i;
 366
 367 -       if ((bus->chip_id == 0x5354) && !crystalfreq) {
 368 -               /* The 5354 crystal freq is 25MHz */
 369 -               crystalfreq = 25000;
 370 -       }
 371         if (crystalfreq)
 372                 e = pmu0_plltab_find_entry(crystalfreq);
 373         if (!e)
 374 @@ -111,8 +110,8 @@ static void ssb_pmu0_pllinit_r0(struct s
 375                 return;
 376         }
 377
 378 -       ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
 379 -                  (crystalfreq / 1000), (crystalfreq % 1000));
 380 +       ssb_info("Programming PLL to %u.%03u MHz\n",
 381 +                crystalfreq / 1000, crystalfreq % 1000);
 382
 383         /* First turn the PLL off. */
 384         switch (bus->chip_id) {
 385 @@ -139,7 +138,7 @@ static void ssb_pmu0_pllinit_r0(struct s
 386         }
 387         tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
 388         if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
 389 -               ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
 390 +               ssb_emerg("Failed to turn the PLL off!\n");
 391
 392         /* Set PDIV in PLL control 0. */
 393         pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
 394 @@ -250,8 +249,8 @@ static void ssb_pmu1_pllinit_r0(struct s
 395                 return;
 396         }
 397
 398 -       ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
 399 -                  (crystalfreq / 1000), (crystalfreq % 1000));
 400 +       ssb_info("Programming PLL to %u.%03u MHz\n",
 401 +                crystalfreq / 1000, crystalfreq % 1000);
 402
 403         /* First turn the PLL off. */
 404         switch (bus->chip_id) {
 405 @@ -276,7 +275,7 @@ static void ssb_pmu1_pllinit_r0(struct s
 406         }
 407         tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
 408         if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
 409 -               ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
 410 +               ssb_emerg("Failed to turn the PLL off!\n");
 411
 412         /* Set p1div and p2div. */
 413         pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
 414 @@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_
 415         u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
 416
 417         if (bus->bustype == SSB_BUSTYPE_SSB) {
 418 -               /* TODO: The user may override the crystal frequency. */
 419 +#ifdef CONFIG_BCM47XX
 420 +               char buf[20];
 421 +               if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
 422 +                       crystalfreq = simple_strtoul(buf, NULL, 0);
 423 +#endif
 424         }
 425
 426         switch (bus->chip_id) {
 427 @@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_
 428                 ssb_pmu1_pllinit_r0(cc, crystalfreq);
 429                 break;
 430         case 0x4328:
 431 +               ssb_pmu0_pllinit_r0(cc, crystalfreq);
 432 +               break;
 433         case 0x5354:
 434 +               if (crystalfreq == 0)
 435 +                       crystalfreq = 25000;
 436                 ssb_pmu0_pllinit_r0(cc, crystalfreq);
 437                 break;
 438         case 0x4322:
 439 @@ -339,10 +346,11 @@ static void ssb_pmu_pll_init(struct ssb_
 440                         chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
 441                 }
 442                 break;
 443 +       case 43222:
 444 +               break;
 445         default:
 446 -               ssb_printk(KERN_ERR PFX
 447 -                          "ERROR: PLL init unknown for device %04X\n",
 448 -                          bus->chip_id);
 449 +               ssb_err("ERROR: PLL init unknown for device %04X\n",
 450 +                       bus->chip_id);
 451         }
 452  }
 453
 454 @@ -427,6 +435,7 @@ static void ssb_pmu_resources_init(struc
 455                  min_msk = 0xCBB;
 456                  break;
 457         case 0x4322:
 458 +       case 43222:
 459                 /* We keep the default settings:
 460                  * min_msk = 0xCBB
 461                  * max_msk = 0x7FFFF
 462 @@ -462,9 +471,8 @@ static void ssb_pmu_resources_init(struc
 463                 max_msk = 0xFFFFF;
 464                 break;
 465         default:
 466 -               ssb_printk(KERN_ERR PFX
 467 -                          "ERROR: PMU resource config unknown for device %04X\n",
 468 -                          bus->chip_id);
 469 +               ssb_err("ERROR: PMU resource config unknown for device %04X\n",
 470 +                       bus->chip_id);
 471         }
 472
 473         if (updown_tab) {
 474 @@ -516,8 +524,8 @@ void ssb_pmu_init(struct ssb_chipcommon
 475         pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
 476         cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
 477
 478 -       ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
 479 -                   cc->pmu.rev, pmucap);
 480 +       ssb_dbg("Found rev %u PMU (capabilities 0x%08X)\n",
 481 +               cc->pmu.rev, pmucap);
 482
 483         if (cc->pmu.rev == 1)
 484                 chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
 485 @@ -607,3 +615,102 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
 486
 487  EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
 488  EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
 489 +
 490 +static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
 491 +{
 492 +       u32 crystalfreq;
 493 +       const struct pmu0_plltab_entry *e = NULL;
 494 +
 495 +       crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
 496 +                     SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
 497 +       e = pmu0_plltab_find_entry(crystalfreq);
 498 +       BUG_ON(!e);
 499 +       return e->freq * 1000;
 500 +}
 501 +
 502 +u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
 503 +{
 504 +       struct ssb_bus *bus = cc->dev->bus;
 505 +
 506 +       switch (bus->chip_id) {
 507 +       case 0x5354:
 508 +               ssb_pmu_get_alp_clock_clk0(cc);
 509 +       default:
 510 +               ssb_err("ERROR: PMU alp clock unknown for device %04X\n",
 511 +                       bus->chip_id);
 512 +               return 0;
 513 +       }
 514 +}
 515 +
 516 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
 517 +{
 518 +       struct ssb_bus *bus = cc->dev->bus;
 519 +
 520 +       switch (bus->chip_id) {
 521 +       case 0x5354:
 522 +               /* 5354 chip uses a non programmable PLL of frequency 240MHz */
 523 +               return 240000000;
 524 +       default:
 525 +               ssb_err("ERROR: PMU cpu clock unknown for device %04X\n",
 526 +                       bus->chip_id);
 527 +               return 0;
 528 +       }
 529 +}
 530 +
 531 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
 532 +{
 533 +       struct ssb_bus *bus = cc->dev->bus;
 534 +
 535 +       switch (bus->chip_id) {
 536 +       case 0x5354:
 537 +               return 120000000;
 538 +       default:
 539 +               ssb_err("ERROR: PMU controlclock unknown for device %04X\n",
 540 +                       bus->chip_id);
 541 +               return 0;
 542 +       }
 543 +}
 544 +
 545 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
 546 +{
 547 +       u32 pmu_ctl = 0;
 548 +
 549 +       switch (cc->dev->bus->chip_id) {
 550 +       case 0x4322:
 551 +               ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
 552 +               ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
 553 +               ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
 554 +               if (spuravoid == 1)
 555 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
 556 +               else
 557 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
 558 +               pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
 559 +               break;
 560 +       case 43222:
 561 +               if (spuravoid == 1) {
 562 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008);
 563 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06);
 564 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08);
 565 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
 566 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920);
 567 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815);
 568 +               } else {
 569 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008);
 570 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06);
 571 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08);
 572 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
 573 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0);
 574 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855);
 575 +               }
 576 +               pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
 577 +               break;
 578 +       default:
 579 +               ssb_printk(KERN_ERR PFX
 580 +                          "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
 581 +                          cc->dev->bus->chip_id);
 582 +               return;
 583 +       }
 584 +
 585 +       chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);
 586 +}
 587 +EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
 588 --- /dev/null
 589 +++ b/drivers/ssb/driver_chipcommon_sflash.c
 590 @@ -0,0 +1,164 @@
 591 +/*
 592 + * Sonics Silicon Backplane
 593 + * ChipCommon serial flash interface
 594 + *
 595 + * Licensed under the GNU/GPL. See COPYING for details.
 596 + */
 597 +
 598 +#include <linux/ssb/ssb.h>
 599 +
 600 +#include "ssb_private.h"
 601 +
 602 +static struct resource ssb_sflash_resource = {
 603 +       .name   = "ssb_sflash",
 604 +       .start  = SSB_FLASH2,
 605 +       .end    = 0,
 606 +       .flags  = IORESOURCE_MEM | IORESOURCE_READONLY,
 607 +};
 608 +
 609 +struct platform_device ssb_sflash_dev = {
 610 +       .name           = "ssb_sflash",
 611 +       .resource       = &ssb_sflash_resource,
 612 +       .num_resources  = 1,
 613 +};
 614 +
 615 +struct ssb_sflash_tbl_e {
 616 +       char *name;
 617 +       u32 id;
 618 +       u32 blocksize;
 619 +       u16 numblocks;
 620 +};
 621 +
 622 +static const struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
 623 +       { "M25P20", 0x11, 0x10000, 4, },
 624 +       { "M25P40", 0x12, 0x10000, 8, },
 625 +
 626 +       { "M25P16", 0x14, 0x10000, 32, },
 627 +       { "M25P32", 0x15, 0x10000, 64, },
 628 +       { "M25P64", 0x16, 0x10000, 128, },
 629 +       { "M25FL128", 0x17, 0x10000, 256, },
 630 +       { 0 },
 631 +};
 632 +
 633 +static const struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
 634 +       { "SST25WF512", 1, 0x1000, 16, },
 635 +       { "SST25VF512", 0x48, 0x1000, 16, },
 636 +       { "SST25WF010", 2, 0x1000, 32, },
 637 +       { "SST25VF010", 0x49, 0x1000, 32, },
 638 +       { "SST25WF020", 3, 0x1000, 64, },
 639 +       { "SST25VF020", 0x43, 0x1000, 64, },
 640 +       { "SST25WF040", 4, 0x1000, 128, },
 641 +       { "SST25VF040", 0x44, 0x1000, 128, },
 642 +       { "SST25VF040B", 0x8d, 0x1000, 128, },
 643 +       { "SST25WF080", 5, 0x1000, 256, },
 644 +       { "SST25VF080B", 0x8e, 0x1000, 256, },
 645 +       { "SST25VF016", 0x41, 0x1000, 512, },
 646 +       { "SST25VF032", 0x4a, 0x1000, 1024, },
 647 +       { "SST25VF064", 0x4b, 0x1000, 2048, },
 648 +       { 0 },
 649 +};
 650 +
 651 +static const struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
 652 +       { "AT45DB011", 0xc, 256, 512, },
 653 +       { "AT45DB021", 0x14, 256, 1024, },
 654 +       { "AT45DB041", 0x1c, 256, 2048, },
 655 +       { "AT45DB081", 0x24, 256, 4096, },
 656 +       { "AT45DB161", 0x2c, 512, 4096, },
 657 +       { "AT45DB321", 0x34, 512, 8192, },
 658 +       { "AT45DB642", 0x3c, 1024, 8192, },
 659 +       { 0 },
 660 +};
 661 +
 662 +static void ssb_sflash_cmd(struct ssb_chipcommon *cc, u32 opcode)
 663 +{
 664 +       int i;
 665 +       chipco_write32(cc, SSB_CHIPCO_FLASHCTL,
 666 +                      SSB_CHIPCO_FLASHCTL_START | opcode);
 667 +       for (i = 0; i < 1000; i++) {
 668 +               if (!(chipco_read32(cc, SSB_CHIPCO_FLASHCTL) &
 669 +                     SSB_CHIPCO_FLASHCTL_BUSY))
 670 +                       return;
 671 +               cpu_relax();
 672 +       }
 673 +       pr_err("SFLASH control command failed (timeout)!\n");
 674 +}
 675 +
 676 +/* Initialize serial flash access */
 677 +int ssb_sflash_init(struct ssb_chipcommon *cc)
 678 +{
 679 +       struct ssb_sflash *sflash = &cc->dev->bus->mipscore.sflash;
 680 +       const struct ssb_sflash_tbl_e *e;
 681 +       u32 id, id2;
 682 +
 683 +       switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
 684 +       case SSB_CHIPCO_FLASHT_STSER:
 685 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_DP);
 686 +
 687 +               chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 0);
 688 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
 689 +               id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
 690 +
 691 +               chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 1);
 692 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
 693 +               id2 = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
 694 +
 695 +               switch (id) {
 696 +               case 0xbf:
 697 +                       for (e = ssb_sflash_sst_tbl; e->name; e++) {
 698 +                               if (e->id == id2)
 699 +                                       break;
 700 +                       }
 701 +                       break;
 702 +               case 0x13:
 703 +                       return -ENOTSUPP;
 704 +               default:
 705 +                       for (e = ssb_sflash_st_tbl; e->name; e++) {
 706 +                               if (e->id == id)
 707 +                                       break;
 708 +                       }
 709 +                       break;
 710 +               }
 711 +               if (!e->name) {
 712 +                       pr_err("Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n",
 713 +                              id, id2);
 714 +                       return -ENOTSUPP;
 715 +               }
 716 +
 717 +               break;
 718 +       case SSB_CHIPCO_FLASHT_ATSER:
 719 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_STATUS);
 720 +               id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA) & 0x3c;
 721 +
 722 +               for (e = ssb_sflash_at_tbl; e->name; e++) {
 723 +                       if (e->id == id)
 724 +                               break;
 725 +               }
 726 +               if (!e->name) {
 727 +                       pr_err("Unsupported Atmel serial flash (id: 0x%X)\n",
 728 +                              id);
 729 +                       return -ENOTSUPP;
 730 +               }
 731 +
 732 +               break;
 733 +       default:
 734 +               pr_err("Unsupported flash type\n");
 735 +               return -ENOTSUPP;
 736 +       }
 737 +
 738 +       sflash->window = SSB_FLASH2;
 739 +       sflash->blocksize = e->blocksize;
 740 +       sflash->numblocks = e->numblocks;
 741 +       sflash->size = sflash->blocksize * sflash->numblocks;
 742 +       sflash->present = true;
 743 +
 744 +       pr_info("Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
 745 +               e->name, sflash->size / 1024, e->blocksize, e->numblocks);
 746 +
 747 +       /* Prepare platform device, but don't register it yet. It's too early,
 748 +        * malloc (required by device_private_init) is not available yet. */
 749 +       ssb_sflash_dev.resource[0].end = ssb_sflash_dev.resource[0].start +
 750 +                                        sflash->size;
 751 +       ssb_sflash_dev.dev.platform_data = sflash;
 752 +
 753 +       return 0;
 754 +}
 755 --- a/drivers/ssb/driver_extif.c
 756 +++ b/drivers/ssb/driver_extif.c
 757 @@ -112,10 +112,37 @@ void ssb_extif_get_clockcontrol(struct s
 758         *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
 759  }
 760
 761 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
 762 -                                 u32 ticks)
 763 +u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
 764  {
 765 +       struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
 766 +
 767 +       return ssb_extif_watchdog_timer_set(extif, ticks);
 768 +}
 769 +
 770 +u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
 771 +{
 772 +       struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
 773 +       u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
 774 +
 775 +       ticks = ssb_extif_watchdog_timer_set(extif, ticks);
 776 +
 777 +       return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
 778 +}
 779 +
 780 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
 781 +{
 782 +       if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
 783 +               ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
 784         extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
 785 +
 786 +       return ticks;
 787 +}
 788 +
 789 +void ssb_extif_init(struct ssb_extif *extif)
 790 +{
 791 +       if (!extif->dev)
 792 +               return; /* We don't have a Extif core */
 793 +       spin_lock_init(&extif->gpio_lock);
 794  }
 795
 796  u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
 797 @@ -125,22 +152,50 @@ u32 ssb_extif_gpio_in(struct ssb_extif *
 798
 799  u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
 800  {
 801 -       return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
 802 +       unsigned long flags;
 803 +       u32 res = 0;
 804 +
 805 +       spin_lock_irqsave(&extif->gpio_lock, flags);
 806 +       res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
 807                                    mask, value);
 808 +       spin_unlock_irqrestore(&extif->gpio_lock, flags);
 809 +
 810 +       return res;
 811  }
 812
 813  u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
 814  {
 815 -       return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
 816 +       unsigned long flags;
 817 +       u32 res = 0;
 818 +
 819 +       spin_lock_irqsave(&extif->gpio_lock, flags);
 820 +       res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
 821                                    mask, value);
 822 +       spin_unlock_irqrestore(&extif->gpio_lock, flags);
 823 +
 824 +       return res;
 825  }
 826
 827  u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
 828  {
 829 -       return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
 830 +       unsigned long flags;
 831 +       u32 res = 0;
 832 +
 833 +       spin_lock_irqsave(&extif->gpio_lock, flags);
 834 +       res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
 835 +       spin_unlock_irqrestore(&extif->gpio_lock, flags);
 836 +
 837 +       return res;
 838  }
 839
 840  u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
 841  {
 842 -       return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
 843 +       unsigned long flags;
 844 +       u32 res = 0;
 845 +
 846 +       spin_lock_irqsave(&extif->gpio_lock, flags);
 847 +       res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
 848 +       spin_unlock_irqrestore(&extif->gpio_lock, flags);
 849 +
 850 +       return res;
 851  }
 852 --- /dev/null
 853 +++ b/drivers/ssb/driver_gpio.c
 854 @@ -0,0 +1,210 @@
 855 +/*
 856 + * Sonics Silicon Backplane
 857 + * GPIO driver
 858 + *
 859 + * Copyright 2011, Broadcom Corporation
 860 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
 861 + *
 862 + * Licensed under the GNU/GPL. See COPYING for details.
 863 + */
 864 +
 865 +#include <linux/gpio.h>
 866 +#include <linux/export.h>
 867 +#include <linux/ssb/ssb.h>
 868 +
 869 +#include "ssb_private.h"
 870 +
 871 +static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip)
 872 +{
 873 +       return container_of(chip, struct ssb_bus, gpio);
 874 +}
 875 +
 876 +static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio)
 877 +{
 878 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 879 +
 880 +       return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio);
 881 +}
 882 +
 883 +static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned gpio,
 884 +                                     int value)
 885 +{
 886 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 887 +
 888 +       ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
 889 +}
 890 +
 891 +static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip,
 892 +                                          unsigned gpio)
 893 +{
 894 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 895 +
 896 +       ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0);
 897 +       return 0;
 898 +}
 899 +
 900 +static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip,
 901 +                                           unsigned gpio, int value)
 902 +{
 903 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 904 +
 905 +       ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio);
 906 +       ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
 907 +       return 0;
 908 +}
 909 +
 910 +static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned gpio)
 911 +{
 912 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 913 +
 914 +       ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0);
 915 +       /* clear pulldown */
 916 +       ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0);
 917 +       /* Set pullup */
 918 +       ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio);
 919 +
 920 +       return 0;
 921 +}
 922 +
 923 +static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio)
 924 +{
 925 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 926 +
 927 +       /* clear pullup */
 928 +       ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
 929 +}
 930 +
 931 +static int ssb_gpio_chipco_to_irq(struct gpio_chip *chip, unsigned gpio)
 932 +{
 933 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 934 +
 935 +       if (bus->bustype == SSB_BUSTYPE_SSB)
 936 +               return ssb_mips_irq(bus->chipco.dev) + 2;
 937 +       else
 938 +               return -EINVAL;
 939 +}
 940 +
 941 +static int ssb_gpio_chipco_init(struct ssb_bus *bus)
 942 +{
 943 +       struct gpio_chip *chip = &bus->gpio;
 944 +
 945 +       chip->label             = "ssb_chipco_gpio";
 946 +       chip->owner             = THIS_MODULE;
 947 +       chip->request           = ssb_gpio_chipco_request;
 948 +       chip->free              = ssb_gpio_chipco_free;
 949 +       chip->get               = ssb_gpio_chipco_get_value;
 950 +       chip->set               = ssb_gpio_chipco_set_value;
 951 +       chip->direction_input   = ssb_gpio_chipco_direction_input;
 952 +       chip->direction_output  = ssb_gpio_chipco_direction_output;
 953 +       chip->to_irq            = ssb_gpio_chipco_to_irq;
 954 +       chip->ngpio             = 16;
 955 +       /* There is just one SoC in one device and its GPIO addresses should be
 956 +        * deterministic to address them more easily. The other buses could get
 957 +        * a random base number. */
 958 +       if (bus->bustype == SSB_BUSTYPE_SSB)
 959 +               chip->base              = 0;
 960 +       else
 961 +               chip->base              = -1;
 962 +
 963 +       return gpiochip_add(chip);
 964 +}
 965 +
 966 +#ifdef CONFIG_SSB_DRIVER_EXTIF
 967 +
 968 +static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio)
 969 +{
 970 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 971 +
 972 +       return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio);
 973 +}
 974 +
 975 +static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned gpio,
 976 +                                    int value)
 977 +{
 978 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 979 +
 980 +       ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
 981 +}
 982 +
 983 +static int ssb_gpio_extif_direction_input(struct gpio_chip *chip,
 984 +                                         unsigned gpio)
 985 +{
 986 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 987 +
 988 +       ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0);
 989 +       return 0;
 990 +}
 991 +
 992 +static int ssb_gpio_extif_direction_output(struct gpio_chip *chip,
 993 +                                          unsigned gpio, int value)
 994 +{
 995 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 996 +
 997 +       ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio);
 998 +       ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
 999 +       return 0;
1000 +}
1001 +
1002 +static int ssb_gpio_extif_to_irq(struct gpio_chip *chip, unsigned gpio)
1003 +{
1004 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
1005 +
1006 +       if (bus->bustype == SSB_BUSTYPE_SSB)
1007 +               return ssb_mips_irq(bus->extif.dev) + 2;
1008 +       else
1009 +               return -EINVAL;
1010 +}
1011 +
1012 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
1013 +{
1014 +       struct gpio_chip *chip = &bus->gpio;
1015 +
1016 +       chip->label             = "ssb_extif_gpio";
1017 +       chip->owner             = THIS_MODULE;
1018 +       chip->get               = ssb_gpio_extif_get_value;
1019 +       chip->set               = ssb_gpio_extif_set_value;
1020 +       chip->direction_input   = ssb_gpio_extif_direction_input;
1021 +       chip->direction_output  = ssb_gpio_extif_direction_output;
1022 +       chip->to_irq            = ssb_gpio_extif_to_irq;
1023 +       chip->ngpio             = 5;
1024 +       /* There is just one SoC in one device and its GPIO addresses should be
1025 +        * deterministic to address them more easily. The other buses could get
1026 +        * a random base number. */
1027 +       if (bus->bustype == SSB_BUSTYPE_SSB)
1028 +               chip->base              = 0;
1029 +       else
1030 +               chip->base              = -1;
1031 +
1032 +       return gpiochip_add(chip);
1033 +}
1034 +
1035 +#else
1036 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
1037 +{
1038 +       return -ENOTSUPP;
1039 +}
1040 +#endif
1041 +
1042 +int ssb_gpio_init(struct ssb_bus *bus)
1043 +{
1044 +       if (ssb_chipco_available(&bus->chipco))
1045 +               return ssb_gpio_chipco_init(bus);
1046 +       else if (ssb_extif_available(&bus->extif))
1047 +               return ssb_gpio_extif_init(bus);
1048 +       else
1049 +               SSB_WARN_ON(1);
1050 +
1051 +       return -1;
1052 +}
1053 +
1054 +int ssb_gpio_unregister(struct ssb_bus *bus)
1055 +{
1056 +       if (ssb_chipco_available(&bus->chipco) ||
1057 +           ssb_extif_available(&bus->extif)) {
1058 +               return gpiochip_remove(&bus->gpio);
1059 +       } else {
1060 +               SSB_WARN_ON(1);
1061 +       }
1062 +
1063 +       return -1;
1064 +}
1065 --- a/drivers/ssb/driver_mipscore.c
1066 +++ b/drivers/ssb/driver_mipscore.c
1067 @@ -10,6 +10,7 @@
1068
1069  #include <linux/ssb/ssb.h>
1070
1071 +#include <linux/mtd/physmap.h>
1072  #include <linux/serial.h>
1073  #include <linux/serial_core.h>
1074  #include <linux/serial_reg.h>
1075 @@ -17,6 +18,25 @@
1076
1077  #include "ssb_private.h"
1078
1079 +static const char * const part_probes[] = { "bcm47xxpart", NULL };
1080 +
1081 +static struct physmap_flash_data ssb_pflash_data = {
1082 +       .part_probe_types       = part_probes,
1083 +};
1084 +
1085 +static struct resource ssb_pflash_resource = {
1086 +       .name   = "ssb_pflash",
1087 +       .flags  = IORESOURCE_MEM,
1088 +};
1089 +
1090 +struct platform_device ssb_pflash_dev = {
1091 +       .name           = "physmap-flash",
1092 +       .dev            = {
1093 +               .platform_data  = &ssb_pflash_data,
1094 +       },
1095 +       .resource       = &ssb_pflash_resource,
1096 +       .num_resources  = 1,
1097 +};
1098
1099  static inline u32 mips_read32(struct ssb_mipscore *mcore,
1100                               u16 offset)
1101 @@ -147,21 +167,22 @@ static void set_irq(struct ssb_device *d
1102                 irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
1103                 ssb_write32(mdev, SSB_IPSFLAG, irqflag);
1104         }
1105 -       ssb_dprintk(KERN_INFO PFX
1106 -                   "set_irq: core 0x%04x, irq %d => %d\n",
1107 -                   dev->id.coreid, oldirq+2, irq+2);
1108 +       ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n",
1109 +               dev->id.coreid, oldirq+2, irq+2);
1110  }
1111
1112  static void print_irq(struct ssb_device *dev, unsigned int irq)
1113  {
1114 -       int i;
1115         static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
1116 -       ssb_dprintk(KERN_INFO PFX
1117 -               "core 0x%04x, irq :", dev->id.coreid);
1118 -       for (i = 0; i <= 6; i++) {
1119 -               ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
1120 -       }
1121 -       ssb_dprintk("\n");
1122 +       ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n",
1123 +               dev->id.coreid,
1124 +               irq_name[0], irq == 0 ? "*" : " ",
1125 +               irq_name[1], irq == 1 ? "*" : " ",
1126 +               irq_name[2], irq == 2 ? "*" : " ",
1127 +               irq_name[3], irq == 3 ? "*" : " ",
1128 +               irq_name[4], irq == 4 ? "*" : " ",
1129 +               irq_name[5], irq == 5 ? "*" : " ",
1130 +               irq_name[6], irq == 6 ? "*" : " ");
1131  }
1132
1133  static void dump_irq(struct ssb_bus *bus)
1134 @@ -178,9 +199,9 @@ static void ssb_mips_serial_init(struct
1135  {
1136         struct ssb_bus *bus = mcore->dev->bus;
1137
1138 -       if (bus->extif.dev)
1139 +       if (ssb_extif_available(&bus->extif))
1140                 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
1141 -       else if (bus->chipco.dev)
1142 +       else if (ssb_chipco_available(&bus->chipco))
1143                 mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
1144         else
1145                 mcore->nr_serial_ports = 0;
1146 @@ -189,17 +210,42 @@ static void ssb_mips_serial_init(struct
1147  static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
1148  {
1149         struct ssb_bus *bus = mcore->dev->bus;
1150 +       struct ssb_pflash *pflash = &mcore->pflash;
1151
1152 -       mcore->flash_buswidth = 2;
1153 -       if (bus->chipco.dev) {
1154 -               mcore->flash_window = 0x1c000000;
1155 -               mcore->flash_window_size = 0x02000000;
1156 +       /* When there is no chipcommon on the bus there is 4MB flash */
1157 +       if (!ssb_chipco_available(&bus->chipco)) {
1158 +               pflash->present = true;
1159 +               pflash->buswidth = 2;
1160 +               pflash->window = SSB_FLASH1;
1161 +               pflash->window_size = SSB_FLASH1_SZ;
1162 +               goto ssb_pflash;
1163 +       }
1164 +
1165 +       /* There is ChipCommon, so use it to read info about flash */
1166 +       switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
1167 +       case SSB_CHIPCO_FLASHT_STSER:
1168 +       case SSB_CHIPCO_FLASHT_ATSER:
1169 +               pr_debug("Found serial flash\n");
1170 +               ssb_sflash_init(&bus->chipco);
1171 +               break;
1172 +       case SSB_CHIPCO_FLASHT_PARA:
1173 +               pr_debug("Found parallel flash\n");
1174 +               pflash->present = true;
1175 +               pflash->window = SSB_FLASH2;
1176 +               pflash->window_size = SSB_FLASH2_SZ;
1177                 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
1178                                & SSB_CHIPCO_CFG_DS16) == 0)
1179 -                       mcore->flash_buswidth = 1;
1180 -       } else {
1181 -               mcore->flash_window = 0x1fc00000;
1182 -               mcore->flash_window_size = 0x00400000;
1183 +                       pflash->buswidth = 1;
1184 +               else
1185 +                       pflash->buswidth = 2;
1186 +               break;
1187 +       }
1188 +
1189 +ssb_pflash:
1190 +       if (pflash->present) {
1191 +               ssb_pflash_data.width = pflash->buswidth;
1192 +               ssb_pflash_resource.start = pflash->window;
1193 +               ssb_pflash_resource.end = pflash->window + pflash->window_size;
1194         }
1195  }
1196
1197 @@ -208,9 +254,12 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
1198         struct ssb_bus *bus = mcore->dev->bus;
1199         u32 pll_type, n, m, rate = 0;
1200
1201 -       if (bus->extif.dev) {
1202 +       if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1203 +               return ssb_pmu_get_cpu_clock(&bus->chipco);
1204 +
1205 +       if (ssb_extif_available(&bus->extif)) {
1206                 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
1207 -       } else if (bus->chipco.dev) {
1208 +       } else if (ssb_chipco_available(&bus->chipco)) {
1209                 ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
1210         } else
1211                 return 0;
1212 @@ -238,7 +287,7 @@ void ssb_mipscore_init(struct ssb_mipsco
1213         if (!mcore->dev)
1214                 return; /* We don't have a MIPS core */
1215
1216 -       ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
1217 +       ssb_dbg("Initializing MIPS core...\n");
1218
1219         bus = mcore->dev->bus;
1220         hz = ssb_clockspeed(bus);
1221 @@ -246,9 +295,9 @@ void ssb_mipscore_init(struct ssb_mipsco
1222                 hz = 100000000;
1223         ns = 1000000000 / hz;
1224
1225 -       if (bus->extif.dev)
1226 +       if (ssb_extif_available(&bus->extif))
1227                 ssb_extif_timing_init(&bus->extif, ns);
1228 -       else if (bus->chipco.dev)
1229 +       else if (ssb_chipco_available(&bus->chipco))
1230                 ssb_chipco_timing_init(&bus->chipco, ns);
1231
1232         /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
1233 @@ -286,7 +335,7 @@ void ssb_mipscore_init(struct ssb_mipsco
1234                         break;
1235                 }
1236         }
1237 -       ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
1238 +       ssb_dbg("after irq reconfiguration\n");
1239         dump_irq(bus);
1240
1241         ssb_mips_serial_init(mcore);
1242 --- a/drivers/ssb/driver_pcicore.c
1243 +++ b/drivers/ssb/driver_pcicore.c
1244 @@ -263,8 +263,7 @@ int ssb_pcicore_plat_dev_init(struct pci
1245                 return -ENODEV;
1246         }
1247
1248 -       ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
1249 -                  pci_name(d));
1250 +       ssb_info("PCI: Fixing up device %s\n", pci_name(d));
1251
1252         /* Fix up interrupt lines */
1253         d->irq = ssb_mips_irq(extpci_core->dev) + 2;
1254 @@ -285,12 +284,12 @@ static void ssb_pcicore_fixup_pcibridge(
1255         if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
1256                 return;
1257
1258 -       ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
1259 +       ssb_info("PCI: Fixing up bridge %s\n", pci_name(dev));
1260
1261         /* Enable PCI bridge bus mastering and memory space */
1262         pci_set_master(dev);
1263         if (pcibios_enable_device(dev, ~0) < 0) {
1264 -               ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
1265 +               ssb_err("PCI: SSB bridge enable failed\n");
1266                 return;
1267         }
1268
1269 @@ -299,8 +298,8 @@ static void ssb_pcicore_fixup_pcibridge(
1270
1271         /* Make sure our latency is high enough to handle the devices behind us */
1272         lat = 168;
1273 -       ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
1274 -                  pci_name(dev), lat);
1275 +       ssb_info("PCI: Fixing latency timer of device %s to %u\n",
1276 +                pci_name(dev), lat);
1277         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
1278  }
1279  DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
1280 @@ -323,7 +322,7 @@ static void __devinit ssb_pcicore_init_h
1281                 return;
1282         extpci_core = pc;
1283
1284 -       ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
1285 +       ssb_dbg("PCIcore in host mode found\n");
1286         /* Reset devices on the external PCI bus */
1287         val = SSB_PCICORE_CTL_RST_OE;
1288         val |= SSB_PCICORE_CTL_CLK_OE;
1289 @@ -338,7 +337,7 @@ static void __devinit ssb_pcicore_init_h
1290         udelay(1); /* Assertion time demanded by the PCI standard */
1291
1292         if (pc->dev->bus->has_cardbus_slot) {
1293 -               ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
1294 +               ssb_dbg("CardBus slot detected\n");
1295                 pc->cardbusmode = 1;
1296                 /* GPIO 1 resets the bridge */
1297                 ssb_gpio_out(pc->dev->bus, 1, 1);
1298 --- a/drivers/ssb/embedded.c
1299 +++ b/drivers/ssb/embedded.c
1300 @@ -4,11 +4,13 @@
1301   *
1302   * Copyright 2005-2008, Broadcom Corporation
1303   * Copyright 2006-2008, Michael Buesch <m@bues.ch>
1304 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
1305   *
1306   * Licensed under the GNU/GPL. See COPYING for details.
1307   */
1308
1309  #include <linux/export.h>
1310 +#include <linux/platform_device.h>
1311  #include <linux/ssb/ssb.h>
1312  #include <linux/ssb/ssb_embedded.h>
1313  #include <linux/ssb/ssb_driver_pci.h>
1314 @@ -32,6 +34,38 @@ int ssb_watchdog_timer_set(struct ssb_bu
1315  }
1316  EXPORT_SYMBOL(ssb_watchdog_timer_set);
1317
1318 +int ssb_watchdog_register(struct ssb_bus *bus)
1319 +{
1320 +       struct bcm47xx_wdt wdt = {};
1321 +       struct platform_device *pdev;
1322 +
1323 +       if (ssb_chipco_available(&bus->chipco)) {
1324 +               wdt.driver_data = &bus->chipco;
1325 +               wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
1326 +               wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
1327 +               wdt.max_timer_ms = bus->chipco.max_timer_ms;
1328 +       } else if (ssb_extif_available(&bus->extif)) {
1329 +               wdt.driver_data = &bus->extif;
1330 +               wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
1331 +               wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
1332 +               wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
1333 +       } else {
1334 +               return -ENODEV;
1335 +       }
1336 +
1337 +       pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
1338 +                                            bus->busnumber, &wdt,
1339 +                                            sizeof(wdt));
1340 +       if (IS_ERR(pdev)) {
1341 +               ssb_dbg("can not register watchdog device, err: %li\n",
1342 +                       PTR_ERR(pdev));
1343 +               return PTR_ERR(pdev);
1344 +       }
1345 +
1346 +       bus->watchdog = pdev;
1347 +       return 0;
1348 +}
1349 +
1350  u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
1351  {
1352         unsigned long flags;
1353 --- a/drivers/ssb/main.c
1354 +++ b/drivers/ssb/main.c
1355 @@ -13,6 +13,7 @@
1356  #include <linux/delay.h>
1357  #include <linux/io.h>
1358  #include <linux/module.h>
1359 +#include <linux/platform_device.h>
1360  #include <linux/ssb/ssb.h>
1361  #include <linux/ssb/ssb_regs.h>
1362  #include <linux/ssb/ssb_driver_gige.h>
1363 @@ -289,8 +290,8 @@ int ssb_devices_thaw(struct ssb_freeze_c
1364
1365                 err = sdrv->probe(sdev, &sdev->id);
1366                 if (err) {
1367 -                       ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
1368 -                                  dev_name(sdev->dev));
1369 +                       ssb_err("Failed to thaw device %s\n",
1370 +                               dev_name(sdev->dev));
1371                         result = err;
1372                 }
1373                 ssb_driver_put(sdrv);
1374 @@ -449,10 +450,23 @@ static void ssb_devices_unregister(struc
1375                 if (sdev->dev)
1376                         device_unregister(sdev->dev);
1377         }
1378 +
1379 +#ifdef CONFIG_SSB_EMBEDDED
1380 +       if (bus->bustype == SSB_BUSTYPE_SSB)
1381 +               platform_device_unregister(bus->watchdog);
1382 +#endif
1383  }
1384
1385  void ssb_bus_unregister(struct ssb_bus *bus)
1386  {
1387 +       int err;
1388 +
1389 +       err = ssb_gpio_unregister(bus);
1390 +       if (err == -EBUSY)
1391 +               ssb_dbg("Some GPIOs are still in use\n");
1392 +       else if (err)
1393 +               ssb_dbg("Can not unregister GPIO driver: %i\n", err);
1394 +
1395         ssb_buses_lock();
1396         ssb_devices_unregister(bus);
1397         list_del(&bus->list);
1398 @@ -498,8 +512,7 @@ static int ssb_devices_register(struct s
1399
1400                 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
1401                 if (!devwrap) {
1402 -                       ssb_printk(KERN_ERR PFX
1403 -                                  "Could not allocate device\n");
1404 +                       ssb_err("Could not allocate device\n");
1405                         err = -ENOMEM;
1406                         goto error;
1407                 }
1408 @@ -538,9 +551,7 @@ static int ssb_devices_register(struct s
1409                 sdev->dev = dev;
1410                 err = device_register(dev);
1411                 if (err) {
1412 -                       ssb_printk(KERN_ERR PFX
1413 -                                  "Could not register %s\n",
1414 -                                  dev_name(dev));
1415 +                       ssb_err("Could not register %s\n", dev_name(dev));
1416                         /* Set dev to NULL to not unregister
1417                          * dev on error unwinding. */
1418                         sdev->dev = NULL;
1419 @@ -550,6 +561,22 @@ static int ssb_devices_register(struct s
1420                 dev_idx++;
1421         }
1422
1423 +#ifdef CONFIG_SSB_DRIVER_MIPS
1424 +       if (bus->mipscore.pflash.present) {
1425 +               err = platform_device_register(&ssb_pflash_dev);
1426 +               if (err)
1427 +                       pr_err("Error registering parallel flash\n");
1428 +       }
1429 +#endif
1430 +
1431 +#ifdef CONFIG_SSB_SFLASH
1432 +       if (bus->mipscore.sflash.present) {
1433 +               err = platform_device_register(&ssb_sflash_dev);
1434 +               if (err)
1435 +                       pr_err("Error registering serial flash\n");
1436 +       }
1437 +#endif
1438 +
1439         return 0;
1440  error:
1441         /* Unwind the already registered devices. */
1442 @@ -577,6 +604,8 @@ static int __devinit ssb_attach_queued_b
1443                 if (err)
1444                         goto error;
1445                 ssb_pcicore_init(&bus->pcicore);
1446 +               if (bus->bustype == SSB_BUSTYPE_SSB)
1447 +                       ssb_watchdog_register(bus);
1448                 ssb_bus_may_powerdown(bus);
1449
1450                 err = ssb_devices_register(bus);
1451 @@ -812,7 +841,13 @@ static int __devinit ssb_bus_register(st
1452         if (err)
1453                 goto err_pcmcia_exit;
1454         ssb_chipcommon_init(&bus->chipco);
1455 +       ssb_extif_init(&bus->extif);
1456         ssb_mipscore_init(&bus->mipscore);
1457 +       err = ssb_gpio_init(bus);
1458 +       if (err == -ENOTSUPP)
1459 +               ssb_dbg("GPIO driver not activated\n");
1460 +       else if (err)
1461 +               ssb_dbg("Error registering GPIO driver: %i\n", err);
1462         err = ssb_fetch_invariants(bus, get_invariants);
1463         if (err) {
1464                 ssb_bus_may_powerdown(bus);
1465 @@ -863,11 +898,11 @@ int __devinit ssb_bus_pcibus_register(st
1466
1467         err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
1468         if (!err) {
1469 -               ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1470 -                          "PCI device %s\n", dev_name(&host_pci->dev));
1471 +               ssb_info("Sonics Silicon Backplane found on PCI device %s\n",
1472 +                        dev_name(&host_pci->dev));
1473         } else {
1474 -               ssb_printk(KERN_ERR PFX "Failed to register PCI version"
1475 -                          " of SSB with error %d\n", err);
1476 +               ssb_err("Failed to register PCI version of SSB with error %d\n",
1477 +                       err);
1478         }
1479
1480         return err;
1481 @@ -888,8 +923,8 @@ int __devinit ssb_bus_pcmciabus_register
1482
1483         err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
1484         if (!err) {
1485 -               ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1486 -                          "PCMCIA device %s\n", pcmcia_dev->devname);
1487 +               ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n",
1488 +                        pcmcia_dev->devname);
1489         }
1490
1491         return err;
1492 @@ -911,8 +946,8 @@ int __devinit ssb_bus_sdiobus_register(s
1493
1494         err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
1495         if (!err) {
1496 -               ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1497 -                          "SDIO device %s\n", sdio_func_id(func));
1498 +               ssb_info("Sonics Silicon Backplane found on SDIO device %s\n",
1499 +                        sdio_func_id(func));
1500         }
1501
1502         return err;
1503 @@ -931,8 +966,8 @@ int __devinit ssb_bus_ssbbus_register(st
1504
1505         err = ssb_bus_register(bus, get_invariants, baseaddr);
1506         if (!err) {
1507 -               ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
1508 -                          "address 0x%08lX\n", baseaddr);
1509 +               ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n",
1510 +                        baseaddr);
1511         }
1512
1513         return err;
1514 @@ -1094,6 +1129,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
1515         u32 plltype;
1516         u32 clkctl_n, clkctl_m;
1517
1518 +       if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1519 +               return ssb_pmu_get_controlclock(&bus->chipco);
1520 +
1521         if (ssb_extif_available(&bus->extif))
1522                 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
1523                                            &clkctl_n, &clkctl_m);
1524 @@ -1131,8 +1169,7 @@ static u32 ssb_tmslow_reject_bitmask(str
1525         case SSB_IDLOW_SSBREV_27:     /* same here */
1526                 return SSB_TMSLOW_REJECT;       /* this is a guess */
1527         default:
1528 -               printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1529 -               WARN_ON(1);
1530 +               WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1531         }
1532         return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1533  }
1534 @@ -1324,7 +1361,7 @@ out:
1535  #endif
1536         return err;
1537  error:
1538 -       ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
1539 +       ssb_err("Bus powerdown failed\n");
1540         goto out;
1541  }
1542  EXPORT_SYMBOL(ssb_bus_may_powerdown);
1543 @@ -1347,7 +1384,7 @@ int ssb_bus_powerup(struct ssb_bus *bus,
1544
1545         return 0;
1546  error:
1547 -       ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1548 +       ssb_err("Bus powerup failed\n");
1549         return err;
1550  }
1551  EXPORT_SYMBOL(ssb_bus_powerup);
1552 @@ -1455,15 +1492,13 @@ static int __init ssb_modinit(void)
1553
1554         err = b43_pci_ssb_bridge_init();
1555         if (err) {
1556 -               ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
1557 -                          "initialization failed\n");
1558 +               ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n");
1559                 /* don't fail SSB init because of this */
1560                 err = 0;
1561         }
1562         err = ssb_gige_init();
1563         if (err) {
1564 -               ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
1565 -                          "driver initialization failed\n");
1566 +               ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n");
1567                 /* don't fail SSB init because of this */
1568                 err = 0;
1569         }
1570 --- a/drivers/ssb/pci.c
1571 +++ b/drivers/ssb/pci.c
1572 @@ -56,7 +56,7 @@ int ssb_pci_switch_coreidx(struct ssb_bu
1573         }
1574         return 0;
1575  error:
1576 -       ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
1577 +       ssb_err("Failed to switch to core %u\n", coreidx);
1578         return -ENODEV;
1579  }
1580
1581 @@ -67,10 +67,9 @@ int ssb_pci_switch_core(struct ssb_bus *
1582         unsigned long flags;
1583
1584  #if SSB_VERBOSE_PCICORESWITCH_DEBUG
1585 -       ssb_printk(KERN_INFO PFX
1586 -                  "Switching to %s core, index %d\n",
1587 -                  ssb_core_name(dev->id.coreid),
1588 -                  dev->core_index);
1589 +       ssb_info("Switching to %s core, index %d\n",
1590 +                ssb_core_name(dev->id.coreid),
1591 +                dev->core_index);
1592  #endif
1593
1594         spin_lock_irqsave(&bus->bar_lock, flags);
1595 @@ -178,6 +177,18 @@ err_pci:
1596  #define SPEX(_outvar, _offset, _mask, _shift) \
1597         SPEX16(_outvar, _offset, _mask, _shift)
1598
1599 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift)    \
1600 +       do {    \
1601 +               SPEX(_field[0], _offset +  0, _mask, _shift);   \
1602 +               SPEX(_field[1], _offset +  2, _mask, _shift);   \
1603 +               SPEX(_field[2], _offset +  4, _mask, _shift);   \
1604 +               SPEX(_field[3], _offset +  6, _mask, _shift);   \
1605 +               SPEX(_field[4], _offset +  8, _mask, _shift);   \
1606 +               SPEX(_field[5], _offset + 10, _mask, _shift);   \
1607 +               SPEX(_field[6], _offset + 12, _mask, _shift);   \
1608 +               SPEX(_field[7], _offset + 14, _mask, _shift);   \
1609 +       } while (0)
1610 +
1611
1612  static inline u8 ssb_crc8(u8 crc, u8 data)
1613  {
1614 @@ -219,6 +230,15 @@ static inline u8 ssb_crc8(u8 crc, u8 dat
1615         return t[crc ^ data];
1616  }
1617
1618 +static void sprom_get_mac(char *mac, const u16 *in)
1619 +{
1620 +       int i;
1621 +       for (i = 0; i < 3; i++) {
1622 +               *mac++ = in[i] >> 8;
1623 +               *mac++ = in[i];
1624 +       }
1625 +}
1626 +
1627  static u8 ssb_sprom_crc(const u16 *sprom, u16 size)
1628  {
1629         int word;
1630 @@ -266,7 +286,7 @@ static int sprom_do_write(struct ssb_bus
1631         u32 spromctl;
1632         u16 size = bus->sprom_size;
1633
1634 -       ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1635 +       ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1636         err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
1637         if (err)
1638                 goto err_ctlreg;
1639 @@ -274,17 +294,17 @@ static int sprom_do_write(struct ssb_bus
1640         err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
1641         if (err)
1642                 goto err_ctlreg;
1643 -       ssb_printk(KERN_NOTICE PFX "[ 0%%");
1644 +       ssb_notice("[ 0%%");
1645         msleep(500);
1646         for (i = 0; i < size; i++) {
1647                 if (i == size / 4)
1648 -                       ssb_printk("25%%");
1649 +                       ssb_cont("25%%");
1650                 else if (i == size / 2)
1651 -                       ssb_printk("50%%");
1652 +                       ssb_cont("50%%");
1653                 else if (i == (size * 3) / 4)
1654 -                       ssb_printk("75%%");
1655 +                       ssb_cont("75%%");
1656                 else if (i % 2)
1657 -                       ssb_printk(".");
1658 +                       ssb_cont(".");
1659                 writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
1660                 mmiowb();
1661                 msleep(20);
1662 @@ -297,12 +317,12 @@ static int sprom_do_write(struct ssb_bus
1663         if (err)
1664                 goto err_ctlreg;
1665         msleep(500);
1666 -       ssb_printk("100%% ]\n");
1667 -       ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
1668 +       ssb_cont("100%% ]\n");
1669 +       ssb_notice("SPROM written\n");
1670
1671         return 0;
1672  err_ctlreg:
1673 -       ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n");
1674 +       ssb_err("Could not access SPROM control register.\n");
1675         return err;
1676  }
1677
1678 @@ -327,11 +347,23 @@ static s8 r123_extract_antgain(u8 sprom_
1679         return (s8)gain;
1680  }
1681
1682 +static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
1683 +{
1684 +       SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1685 +       SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
1686 +       SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
1687 +       SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
1688 +       SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
1689 +       SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
1690 +       SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
1691 +       SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
1692 +       SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
1693 +       SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
1694 +            SSB_SPROM2_MAXP_A_LO_SHIFT);
1695 +}
1696 +
1697  static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
1698  {
1699 -       int i;
1700 -       u16 v;
1701 -       s8 gain;
1702         u16 loc[3];
1703
1704         if (out->revision == 3)                 /* rev 3 moved MAC */
1705 @@ -341,19 +373,10 @@ static void sprom_extract_r123(struct ss
1706                 loc[1] = SSB_SPROM1_ET0MAC;
1707                 loc[2] = SSB_SPROM1_ET1MAC;
1708         }
1709 -       for (i = 0; i < 3; i++) {
1710 -               v = in[SPOFF(loc[0]) + i];
1711 -               *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1712 -       }
1713 +       sprom_get_mac(out->il0mac, &in[SPOFF(loc[0])]);
1714         if (out->revision < 3) {        /* only rev 1-2 have et0, et1 */
1715 -               for (i = 0; i < 3; i++) {
1716 -                       v = in[SPOFF(loc[1]) + i];
1717 -                       *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
1718 -               }
1719 -               for (i = 0; i < 3; i++) {
1720 -                       v = in[SPOFF(loc[2]) + i];
1721 -                       *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
1722 -               }
1723 +               sprom_get_mac(out->et0mac, &in[SPOFF(loc[1])]);
1724 +               sprom_get_mac(out->et1mac, &in[SPOFF(loc[2])]);
1725         }
1726         SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
1727         SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
1728 @@ -361,8 +384,10 @@ static void sprom_extract_r123(struct ss
1729         SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
1730         SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
1731         SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
1732 -       SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
1733 -            SSB_SPROM1_BINF_CCODE_SHIFT);
1734 +       SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1735 +       if (out->revision == 1)
1736 +               SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
1737 +                    SSB_SPROM1_BINF_CCODE_SHIFT);
1738         SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
1739              SSB_SPROM1_BINF_ANTA_SHIFT);
1740         SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
1741 @@ -386,24 +411,19 @@ static void sprom_extract_r123(struct ss
1742              SSB_SPROM1_ITSSI_A_SHIFT);
1743         SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
1744         SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
1745 -       if (out->revision >= 2)
1746 -               SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1747 +
1748 +       SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
1749 +       SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
1750
1751         /* Extract the antenna gain values. */
1752 -       gain = r123_extract_antgain(out->revision, in,
1753 -                                   SSB_SPROM1_AGAIN_BG,
1754 -                                   SSB_SPROM1_AGAIN_BG_SHIFT);
1755 -       out->antenna_gain.ghz24.a0 = gain;
1756 -       out->antenna_gain.ghz24.a1 = gain;
1757 -       out->antenna_gain.ghz24.a2 = gain;
1758 -       out->antenna_gain.ghz24.a3 = gain;
1759 -       gain = r123_extract_antgain(out->revision, in,
1760 -                                   SSB_SPROM1_AGAIN_A,
1761 -                                   SSB_SPROM1_AGAIN_A_SHIFT);
1762 -       out->antenna_gain.ghz5.a0 = gain;
1763 -       out->antenna_gain.ghz5.a1 = gain;
1764 -       out->antenna_gain.ghz5.a2 = gain;
1765 -       out->antenna_gain.ghz5.a3 = gain;
1766 +       out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
1767 +                                                   SSB_SPROM1_AGAIN_BG,
1768 +                                                   SSB_SPROM1_AGAIN_BG_SHIFT);
1769 +       out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
1770 +                                                   SSB_SPROM1_AGAIN_A,
1771 +                                                   SSB_SPROM1_AGAIN_A_SHIFT);
1772 +       if (out->revision >= 2)
1773 +               sprom_extract_r23(out, in);
1774  }
1775
1776  /* Revs 4 5 and 8 have partially shared layout */
1777 @@ -448,30 +468,30 @@ static void sprom_extract_r458(struct ss
1778
1779  static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
1780  {
1781 -       int i;
1782 -       u16 v;
1783         u16 il0mac_offset;
1784
1785         if (out->revision == 4)
1786                 il0mac_offset = SSB_SPROM4_IL0MAC;
1787         else
1788                 il0mac_offset = SSB_SPROM5_IL0MAC;
1789 -       /* extract the MAC address */
1790 -       for (i = 0; i < 3; i++) {
1791 -               v = in[SPOFF(il0mac_offset) + i];
1792 -               *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1793 -       }
1794 +
1795 +       sprom_get_mac(out->il0mac, &in[SPOFF(il0mac_offset)]);
1796 +
1797         SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
1798         SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
1799              SSB_SPROM4_ETHPHY_ET1A_SHIFT);
1800 +       SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
1801 +       SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1802         if (out->revision == 4) {
1803 -               SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
1804 +               SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
1805 +               SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
1806                 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
1807                 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
1808                 SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
1809                 SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
1810         } else {
1811 -               SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
1812 +               SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
1813 +               SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
1814                 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
1815                 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
1816                 SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
1817 @@ -504,16 +524,14 @@ static void sprom_extract_r45(struct ssb
1818         }
1819
1820         /* Extract the antenna gain values. */
1821 -       SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
1822 +       SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
1823              SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
1824 -       SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
1825 +       SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
1826              SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
1827 -       SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
1828 +       SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
1829              SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
1830 -       SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
1831 +       SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
1832              SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
1833 -       memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1834 -              sizeof(out->antenna_gain.ghz5));
1835
1836         sprom_extract_r458(out, in);
1837
1838 @@ -523,14 +541,21 @@ static void sprom_extract_r45(struct ssb
1839  static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
1840  {
1841         int i;
1842 -       u16 v;
1843 +       u16 o;
1844 +       u16 pwr_info_offset[] = {
1845 +               SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
1846 +               SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
1847 +       };
1848 +       BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1849 +                       ARRAY_SIZE(out->core_pwr_info));
1850
1851         /* extract the MAC address */
1852 -       for (i = 0; i < 3; i++) {
1853 -               v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
1854 -               *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1855 -       }
1856 -       SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
1857 +       sprom_get_mac(out->il0mac, &in[SPOFF(SSB_SPROM8_IL0MAC)]);
1858 +
1859 +       SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
1860 +       SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1861 +       SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
1862 +       SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
1863         SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
1864         SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
1865         SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
1866 @@ -596,16 +621,46 @@ static void sprom_extract_r8(struct ssb_
1867         SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
1868
1869         /* Extract the antenna gain values. */
1870 -       SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
1871 +       SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
1872              SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
1873 -       SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
1874 +       SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
1875              SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
1876 -       SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
1877 +       SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
1878              SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
1879 -       SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
1880 +       SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
1881              SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
1882 -       memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1883 -              sizeof(out->antenna_gain.ghz5));
1884 +
1885 +       /* Extract cores power info info */
1886 +       for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
1887 +               o = pwr_info_offset[i];
1888 +               SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1889 +                       SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
1890 +               SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1891 +                       SSB_SPROM8_2G_MAXP, 0);
1892 +
1893 +               SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
1894 +               SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
1895 +               SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
1896 +
1897 +               SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1898 +                       SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
1899 +               SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1900 +                       SSB_SPROM8_5G_MAXP, 0);
1901 +               SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
1902 +                       SSB_SPROM8_5GH_MAXP, 0);
1903 +               SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
1904 +                       SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
1905 +
1906 +               SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
1907 +               SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
1908 +               SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
1909 +               SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
1910 +               SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
1911 +               SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
1912 +               SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
1913 +               SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
1914 +               SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
1915 +       }
1916
1917         /* Extract FEM info */
1918         SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
1919 @@ -630,6 +685,63 @@ static void sprom_extract_r8(struct ssb_
1920         SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
1921                 SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1922
1923 +       SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
1924 +            SSB_SPROM8_LEDDC_ON_SHIFT);
1925 +       SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
1926 +            SSB_SPROM8_LEDDC_OFF_SHIFT);
1927 +
1928 +       SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
1929 +            SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
1930 +       SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
1931 +            SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
1932 +       SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
1933 +            SSB_SPROM8_TXRXC_SWITCH_SHIFT);
1934 +
1935 +       SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
1936 +
1937 +       SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
1938 +       SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
1939 +       SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
1940 +       SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
1941 +
1942 +       SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
1943 +            SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
1944 +       SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
1945 +            SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
1946 +       SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
1947 +            SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
1948 +            SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
1949 +       SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
1950 +            SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
1951 +       SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
1952 +            SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
1953 +            SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
1954 +       SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
1955 +            SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
1956 +            SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
1957 +       SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
1958 +            SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
1959 +            SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
1960 +       SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
1961 +            SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
1962 +
1963 +       SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
1964 +       SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
1965 +       SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
1966 +       SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
1967 +
1968 +       SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
1969 +            SSB_SPROM8_THERMAL_TRESH_SHIFT);
1970 +       SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
1971 +            SSB_SPROM8_THERMAL_OFFSET_SHIFT);
1972 +       SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
1973 +            SSB_SPROM8_TEMPDELTA_PHYCAL,
1974 +            SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
1975 +       SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
1976 +            SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
1977 +       SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
1978 +            SSB_SPROM8_TEMPDELTA_HYSTERESIS,
1979 +            SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
1980         sprom_extract_r458(out, in);
1981
1982         /* TODO - get remaining rev 8 stuff needed */
1983 @@ -641,7 +753,7 @@ static int sprom_extract(struct ssb_bus
1984         memset(out, 0, sizeof(*out));
1985
1986         out->revision = in[size - 1] & 0x00FF;
1987 -       ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
1988 +       ssb_dbg("SPROM revision %d detected\n", out->revision);
1989         memset(out->et0mac, 0xFF, 6);           /* preset et0 and et1 mac */
1990         memset(out->et1mac, 0xFF, 6);
1991
1992 @@ -650,7 +762,7 @@ static int sprom_extract(struct ssb_bus
1993                  * number stored in the SPROM.
1994                  * Always extract r1. */
1995                 out->revision = 1;
1996 -               ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
1997 +               ssb_dbg("SPROM treated as revision %d\n", out->revision);
1998         }
1999
2000         switch (out->revision) {
2001 @@ -667,9 +779,8 @@ static int sprom_extract(struct ssb_bus
2002                 sprom_extract_r8(out, in);
2003                 break;
2004         default:
2005 -               ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
2006 -                          " revision %d detected. Will extract"
2007 -                          " v1\n", out->revision);
2008 +               ssb_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
2009 +                        out->revision);
2010                 out->revision = 1;
2011                 sprom_extract_r123(out, in);
2012         }
2013 @@ -689,7 +800,7 @@ static int ssb_pci_sprom_get(struct ssb_
2014         u16 *buf;
2015
2016         if (!ssb_is_sprom_available(bus)) {
2017 -               ssb_printk(KERN_ERR PFX "No SPROM available!\n");
2018 +               ssb_err("No SPROM available!\n");
2019                 return -ENODEV;
2020         }
2021         if (bus->chipco.dev) {  /* can be unavailable! */
2022 @@ -708,7 +819,7 @@ static int ssb_pci_sprom_get(struct ssb_
2023         } else {
2024                 bus->sprom_offset = SSB_SPROM_BASE1;
2025         }
2026 -       ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset);
2027 +       ssb_dbg("SPROM offset is 0x%x\n", bus->sprom_offset);
2028
2029         buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
2030         if (!buf)
2031 @@ -733,18 +844,15 @@ static int ssb_pci_sprom_get(struct ssb_
2032                          * available for this device in some other storage */
2033                         err = ssb_fill_sprom_with_fallback(bus, sprom);
2034                         if (err) {
2035 -                               ssb_printk(KERN_WARNING PFX "WARNING: Using"
2036 -                                          " fallback SPROM failed (err %d)\n",
2037 -                                          err);
2038 +                               ssb_warn("WARNING: Using fallback SPROM failed (err %d)\n",
2039 +                                        err);
2040                         } else {
2041 -                               ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
2042 -                                           " revision %d provided by"
2043 -                                           " platform.\n", sprom->revision);
2044 +                               ssb_dbg("Using SPROM revision %d provided by platform\n",
2045 +                                       sprom->revision);
2046                                 err = 0;
2047                                 goto out_free;
2048                         }
2049 -                       ssb_printk(KERN_WARNING PFX "WARNING: Invalid"
2050 -                                  " SPROM CRC (corrupt SPROM)\n");
2051 +                       ssb_warn("WARNING: Invalid SPROM CRC (corrupt SPROM)\n");
2052                 }
2053         }
2054         err = sprom_extract(bus, sprom, buf, bus->sprom_size);
2055 @@ -759,7 +867,6 @@ static void ssb_pci_get_boardinfo(struct
2056  {
2057         bi->vendor = bus->host_pci->subsystem_vendor;
2058         bi->type = bus->host_pci->subsystem_device;
2059 -       bi->rev = bus->host_pci->revision;
2060  }
2061
2062  int ssb_pci_get_invariants(struct ssb_bus *bus,
2063 --- a/drivers/ssb/pcihost_wrapper.c
2064 +++ b/drivers/ssb/pcihost_wrapper.c
2065 @@ -38,7 +38,7 @@ static int ssb_pcihost_resume(struct pci
2066         struct ssb_bus *ssb = pci_get_drvdata(dev);
2067         int err;
2068
2069 -       pci_set_power_state(dev, 0);
2070 +       pci_set_power_state(dev, PCI_D0);
2071         err = pci_enable_device(dev);
2072         if (err)
2073                 return err;
2074 --- a/drivers/ssb/pcmcia.c
2075 +++ b/drivers/ssb/pcmcia.c
2076 @@ -143,7 +143,7 @@ int ssb_pcmcia_switch_coreidx(struct ssb
2077
2078         return 0;
2079  error:
2080 -       ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
2081 +       ssb_err("Failed to switch to core %u\n", coreidx);
2082         return err;
2083  }
2084
2085 @@ -153,10 +153,9 @@ int ssb_pcmcia_switch_core(struct ssb_bu
2086         int err;
2087
2088  #if SSB_VERBOSE_PCMCIACORESWITCH_DEBUG
2089 -       ssb_printk(KERN_INFO PFX
2090 -                  "Switching to %s core, index %d\n",
2091 -                  ssb_core_name(dev->id.coreid),
2092 -                  dev->core_index);
2093 +       ssb_info("Switching to %s core, index %d\n",
2094 +                ssb_core_name(dev->id.coreid),
2095 +                dev->core_index);
2096  #endif
2097
2098         err = ssb_pcmcia_switch_coreidx(bus, dev->core_index);
2099 @@ -192,7 +191,7 @@ int ssb_pcmcia_switch_segment(struct ssb
2100
2101         return 0;
2102  error:
2103 -       ssb_printk(KERN_ERR PFX "Failed to switch pcmcia segment\n");
2104 +       ssb_err("Failed to switch pcmcia segment\n");
2105         return err;
2106  }
2107
2108 @@ -549,44 +548,39 @@ static int ssb_pcmcia_sprom_write_all(st
2109         bool failed = 0;
2110         size_t size = SSB_PCMCIA_SPROM_SIZE;
2111
2112 -       ssb_printk(KERN_NOTICE PFX
2113 -                  "Writing SPROM. Do NOT turn off the power! "
2114 -                  "Please stand by...\n");
2115 +       ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
2116         err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEEN);
2117         if (err) {
2118 -               ssb_printk(KERN_NOTICE PFX
2119 -                          "Could not enable SPROM write access.\n");
2120 +               ssb_notice("Could not enable SPROM write access\n");
2121                 return -EBUSY;
2122         }
2123 -       ssb_printk(KERN_NOTICE PFX "[ 0%%");
2124 +       ssb_notice("[ 0%%");
2125         msleep(500);
2126         for (i = 0; i < size; i++) {
2127                 if (i == size / 4)
2128 -                       ssb_printk("25%%");
2129 +                       ssb_cont("25%%");
2130                 else if (i == size / 2)
2131 -                       ssb_printk("50%%");
2132 +                       ssb_cont("50%%");
2133                 else if (i == (size * 3) / 4)
2134 -                       ssb_printk("75%%");
2135 +                       ssb_cont("75%%");
2136                 else if (i % 2)
2137 -                       ssb_printk(".");
2138 +                       ssb_cont(".");
2139                 err = ssb_pcmcia_sprom_write(bus, i, sprom[i]);
2140                 if (err) {
2141 -                       ssb_printk(KERN_NOTICE PFX
2142 -                                  "Failed to write to SPROM.\n");
2143 +                       ssb_notice("Failed to write to SPROM\n");
2144                         failed = 1;
2145                         break;
2146                 }
2147         }
2148         err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEDIS);
2149         if (err) {
2150 -               ssb_printk(KERN_NOTICE PFX
2151 -                          "Could not disable SPROM write access.\n");
2152 +               ssb_notice("Could not disable SPROM write access\n");
2153                 failed = 1;
2154         }
2155         msleep(500);
2156         if (!failed) {
2157 -               ssb_printk("100%% ]\n");
2158 -               ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
2159 +               ssb_cont("100%% ]\n");
2160 +               ssb_notice("SPROM written\n");
2161         }
2162
2163         return failed ? -EBUSY : 0;
2164 @@ -676,14 +670,10 @@ static int ssb_pcmcia_do_get_invariants(
2165         case SSB_PCMCIA_CIS_ANTGAIN:
2166                 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2167                         "antg tpl size");
2168 -               sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
2169 -               sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
2170 -               sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
2171 -               sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
2172 -               sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
2173 -               sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
2174 -               sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
2175 -               sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
2176 +               sprom->antenna_gain.a0 = tuple->TupleData[1];
2177 +               sprom->antenna_gain.a1 = tuple->TupleData[1];
2178 +               sprom->antenna_gain.a2 = tuple->TupleData[1];
2179 +               sprom->antenna_gain.a3 = tuple->TupleData[1];
2180                 break;
2181         case SSB_PCMCIA_CIS_BFLAGS:
2182                 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
2183 @@ -704,7 +694,7 @@ static int ssb_pcmcia_do_get_invariants(
2184         return -ENOSPC; /* continue with next entry */
2185
2186  error:
2187 -       ssb_printk(KERN_ERR PFX
2188 +       ssb_err(
2189                    "PCMCIA: Failed to fetch device invariants: %s\n",
2190                    error_description);
2191         return -ENODEV;
2192 @@ -726,7 +716,7 @@ int ssb_pcmcia_get_invariants(struct ssb
2193         res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
2194                                 ssb_pcmcia_get_mac, sprom);
2195         if (res != 0) {
2196 -               ssb_printk(KERN_ERR PFX
2197 +               ssb_err(
2198                         "PCMCIA: Failed to fetch MAC address\n");
2199                 return -ENODEV;
2200         }
2201 @@ -737,7 +727,7 @@ int ssb_pcmcia_get_invariants(struct ssb
2202         if ((res == 0) || (res == -ENOSPC))
2203                 return 0;
2204
2205 -       ssb_printk(KERN_ERR PFX
2206 +       ssb_err(
2207                         "PCMCIA: Failed to fetch device invariants\n");
2208         return -ENODEV;
2209  }
2210 @@ -847,6 +837,6 @@ int ssb_pcmcia_init(struct ssb_bus *bus)
2211
2212         return 0;
2213  error:
2214 -       ssb_printk(KERN_ERR PFX "Failed to initialize PCMCIA host device\n");
2215 +       ssb_err("Failed to initialize PCMCIA host device\n");
2216         return err;
2217  }
2218 --- a/drivers/ssb/scan.c
2219 +++ b/drivers/ssb/scan.c
2220 @@ -90,6 +90,8 @@ const char *ssb_core_name(u16 coreid)
2221                 return "ARM 1176";
2222         case SSB_DEV_ARM_7TDMI:
2223                 return "ARM 7TDMI";
2224 +       case SSB_DEV_ARM_CM3:
2225 +               return "ARM Cortex M3";
2226         }
2227         return "UNKNOWN";
2228  }
2229 @@ -123,8 +125,7 @@ static u16 pcidev_to_chipid(struct pci_d
2230                 chipid_fallback = 0x4401;
2231                 break;
2232         default:
2233 -               ssb_printk(KERN_ERR PFX
2234 -                          "PCI-ID not in fallback list\n");
2235 +               ssb_err("PCI-ID not in fallback list\n");
2236         }
2237
2238         return chipid_fallback;
2239 @@ -150,8 +151,7 @@ static u8 chipid_to_nrcores(u16 chipid)
2240         case 0x4704:
2241                 return 9;
2242         default:
2243 -               ssb_printk(KERN_ERR PFX
2244 -                          "CHIPID not in nrcores fallback list\n");
2245 +               ssb_err("CHIPID not in nrcores fallback list\n");
2246         }
2247
2248         return 1;
2249 @@ -318,12 +318,13 @@ int ssb_bus_scan(struct ssb_bus *bus,
2250                         bus->chip_package = 0;
2251                 }
2252         }
2253 +       ssb_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
2254 +                bus->chip_id, bus->chip_rev, bus->chip_package);
2255         if (!bus->nr_devices)
2256                 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
2257         if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
2258 -               ssb_printk(KERN_ERR PFX
2259 -                          "More than %d ssb cores found (%d)\n",
2260 -                          SSB_MAX_NR_CORES, bus->nr_devices);
2261 +               ssb_err("More than %d ssb cores found (%d)\n",
2262 +                       SSB_MAX_NR_CORES, bus->nr_devices);
2263                 goto err_unmap;
2264         }
2265         if (bus->bustype == SSB_BUSTYPE_SSB) {
2266 @@ -365,8 +366,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2267                         nr_80211_cores++;
2268                         if (nr_80211_cores > 1) {
2269                                 if (!we_support_multiple_80211_cores(bus)) {
2270 -                                       ssb_dprintk(KERN_INFO PFX "Ignoring additional "
2271 -                                                   "802.11 core\n");
2272 +                                       ssb_dbg("Ignoring additional 802.11 core\n");
2273                                         continue;
2274                                 }
2275                         }
2276 @@ -374,8 +374,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2277                 case SSB_DEV_EXTIF:
2278  #ifdef CONFIG_SSB_DRIVER_EXTIF
2279                         if (bus->extif.dev) {
2280 -                               ssb_printk(KERN_WARNING PFX
2281 -                                          "WARNING: Multiple EXTIFs found\n");
2282 +                               ssb_warn("WARNING: Multiple EXTIFs found\n");
2283                                 break;
2284                         }
2285                         bus->extif.dev = dev;
2286 @@ -383,8 +382,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2287                         break;
2288                 case SSB_DEV_CHIPCOMMON:
2289                         if (bus->chipco.dev) {
2290 -                               ssb_printk(KERN_WARNING PFX
2291 -                                          "WARNING: Multiple ChipCommon found\n");
2292 +                               ssb_warn("WARNING: Multiple ChipCommon found\n");
2293                                 break;
2294                         }
2295                         bus->chipco.dev = dev;
2296 @@ -393,8 +391,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2297                 case SSB_DEV_MIPS_3302:
2298  #ifdef CONFIG_SSB_DRIVER_MIPS
2299                         if (bus->mipscore.dev) {
2300 -                               ssb_printk(KERN_WARNING PFX
2301 -                                          "WARNING: Multiple MIPS cores found\n");
2302 +                               ssb_warn("WARNING: Multiple MIPS cores found\n");
2303                                 break;
2304                         }
2305                         bus->mipscore.dev = dev;
2306 @@ -415,8 +412,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2307                                 }
2308                         }
2309                         if (bus->pcicore.dev) {
2310 -                               ssb_printk(KERN_WARNING PFX
2311 -                                          "WARNING: Multiple PCI(E) cores found\n");
2312 +                               ssb_warn("WARNING: Multiple PCI(E) cores found\n");
2313                                 break;
2314                         }
2315                         bus->pcicore.dev = dev;
2316 --- a/drivers/ssb/sdio.c
2317 +++ b/drivers/ssb/sdio.c
2318 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
2319                         case SSB_SDIO_CIS_ANTGAIN:
2320                                 GOTO_ERROR_ON(tuple->size != 2,
2321                                               "antg tpl size");
2322 -                               sprom->antenna_gain.ghz24.a0 = tuple->data[1];
2323 -                               sprom->antenna_gain.ghz24.a1 = tuple->data[1];
2324 -                               sprom->antenna_gain.ghz24.a2 = tuple->data[1];
2325 -                               sprom->antenna_gain.ghz24.a3 = tuple->data[1];
2326 -                               sprom->antenna_gain.ghz5.a0 = tuple->data[1];
2327 -                               sprom->antenna_gain.ghz5.a1 = tuple->data[1];
2328 -                               sprom->antenna_gain.ghz5.a2 = tuple->data[1];
2329 -                               sprom->antenna_gain.ghz5.a3 = tuple->data[1];
2330 +                               sprom->antenna_gain.a0 = tuple->data[1];
2331 +                               sprom->antenna_gain.a1 = tuple->data[1];
2332 +                               sprom->antenna_gain.a2 = tuple->data[1];
2333 +                               sprom->antenna_gain.a3 = tuple->data[1];
2334                                 break;
2335                         case SSB_SDIO_CIS_BFLAGS:
2336                                 GOTO_ERROR_ON((tuple->size != 3) &&
2337 --- a/drivers/ssb/sprom.c
2338 +++ b/drivers/ssb/sprom.c
2339 @@ -54,7 +54,7 @@ static int hex2sprom(u16 *sprom, const c
2340         while (cnt < sprom_size_words) {
2341                 memcpy(tmp, dump, 4);
2342                 dump += 4;
2343 -               err = strict_strtoul(tmp, 16, &parsed);
2344 +               err = kstrtoul(tmp, 16, &parsed);
2345                 if (err)
2346                         return err;
2347                 sprom[cnt++] = swab16((u16)parsed);
2348 @@ -127,13 +127,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
2349                 goto out_kfree;
2350         err = ssb_devices_freeze(bus, &freeze);
2351         if (err) {
2352 -               ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
2353 +               ssb_err("SPROM write: Could not freeze all devices\n");
2354                 goto out_unlock;
2355         }
2356         res = sprom_write(bus, sprom);
2357         err = ssb_devices_thaw(&freeze);
2358         if (err)
2359 -               ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
2360 +               ssb_err("SPROM write: Could not thaw all devices\n");
2361  out_unlock:
2362         mutex_unlock(&bus->sprom_mutex);
2363  out_kfree:
2364 --- a/drivers/ssb/ssb_private.h
2365 +++ b/drivers/ssb/ssb_private.h
2366 @@ -3,21 +3,33 @@
2367
2368  #include <linux/ssb/ssb.h>
2369  #include <linux/types.h>
2370 +#include <linux/bcm47xx_wdt.h>
2371
2372
2373  #define PFX    "ssb: "
2374
2375  #ifdef CONFIG_SSB_SILENT
2376 -# define ssb_printk(fmt, x...) do { /* nothing */ } while (0)
2377 +# define ssb_printk(fmt, ...)                                  \
2378 +       do { if (0) printk(fmt, ##__VA_ARGS__); } while (0)
2379  #else
2380 -# define ssb_printk            printk
2381 +# define ssb_printk(fmt, ...)                                  \
2382 +       printk(fmt, ##__VA_ARGS__)
2383  #endif /* CONFIG_SSB_SILENT */
2384
2385 +#define ssb_emerg(fmt, ...)    ssb_printk(KERN_EMERG PFX fmt, ##__VA_ARGS__)
2386 +#define ssb_err(fmt, ...)      ssb_printk(KERN_ERR PFX fmt, ##__VA_ARGS__)
2387 +#define ssb_warn(fmt, ...)     ssb_printk(KERN_WARNING PFX fmt, ##__VA_ARGS__)
2388 +#define ssb_notice(fmt, ...)   ssb_printk(KERN_NOTICE PFX fmt, ##__VA_ARGS__)
2389 +#define ssb_info(fmt, ...)     ssb_printk(KERN_INFO PFX fmt, ##__VA_ARGS__)
2390 +#define ssb_cont(fmt, ...)     ssb_printk(KERN_CONT fmt, ##__VA_ARGS__)
2391 +
2392  /* dprintk: Debugging printk; vanishes for non-debug compilation */
2393  #ifdef CONFIG_SSB_DEBUG
2394 -# define ssb_dprintk(fmt, x...)        ssb_printk(fmt , ##x)
2395 +# define ssb_dbg(fmt, ...)                                     \
2396 +       ssb_printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__)
2397  #else
2398 -# define ssb_dprintk(fmt, x...)        do { /* nothing */ } while (0)
2399 +# define ssb_dbg(fmt, ...)                                     \
2400 +       do { if (0) printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__); } while (0)
2401  #endif
2402
2403  #ifdef CONFIG_SSB_DEBUG
2404 @@ -207,4 +219,79 @@ static inline void b43_pci_ssb_bridge_ex
2405  }
2406  #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
2407
2408 +/* driver_chipcommon_pmu.c */
2409 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
2410 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
2411 +extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
2412 +
2413 +extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
2414 +                                            u32 ticks);
2415 +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
2416 +
2417 +/* driver_chipcommon_sflash.c */
2418 +#ifdef CONFIG_SSB_SFLASH
2419 +int ssb_sflash_init(struct ssb_chipcommon *cc);
2420 +#else
2421 +static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
2422 +{
2423 +       pr_err("Serial flash not supported\n");
2424 +       return 0;
2425 +}
2426 +#endif /* CONFIG_SSB_SFLASH */
2427 +
2428 +#ifdef CONFIG_SSB_DRIVER_MIPS
2429 +extern struct platform_device ssb_pflash_dev;
2430 +#endif
2431 +
2432 +#ifdef CONFIG_SSB_SFLASH
2433 +extern struct platform_device ssb_sflash_dev;
2434 +#endif
2435 +
2436 +#ifdef CONFIG_SSB_DRIVER_EXTIF
2437 +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
2438 +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
2439 +#else
2440 +static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
2441 +                                                  u32 ticks)
2442 +{
2443 +       return 0;
2444 +}
2445 +static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
2446 +                                                 u32 ms)
2447 +{
2448 +       return 0;
2449 +}
2450 +#endif
2451 +
2452 +#ifdef CONFIG_SSB_EMBEDDED
2453 +extern int ssb_watchdog_register(struct ssb_bus *bus);
2454 +#else /* CONFIG_SSB_EMBEDDED */
2455 +static inline int ssb_watchdog_register(struct ssb_bus *bus)
2456 +{
2457 +       return 0;
2458 +}
2459 +#endif /* CONFIG_SSB_EMBEDDED */
2460 +
2461 +#ifdef CONFIG_SSB_DRIVER_EXTIF
2462 +extern void ssb_extif_init(struct ssb_extif *extif);
2463 +#else
2464 +static inline void ssb_extif_init(struct ssb_extif *extif)
2465 +{
2466 +}
2467 +#endif
2468 +
2469 +#ifdef CONFIG_SSB_DRIVER_GPIO
2470 +extern int ssb_gpio_init(struct ssb_bus *bus);
2471 +extern int ssb_gpio_unregister(struct ssb_bus *bus);
2472 +#else /* CONFIG_SSB_DRIVER_GPIO */
2473 +static inline int ssb_gpio_init(struct ssb_bus *bus)
2474 +{
2475 +       return -ENOTSUPP;
2476 +}
2477 +static inline int ssb_gpio_unregister(struct ssb_bus *bus)
2478 +{
2479 +       return 0;
2480 +}
2481 +#endif /* CONFIG_SSB_DRIVER_GPIO */
2482 +
2483  #endif /* LINUX_SSB_PRIVATE_H_ */
2484 --- a/include/linux/ssb/ssb.h
2485 +++ b/include/linux/ssb/ssb.h
2486 @@ -6,8 +6,10 @@
2487  #include <linux/types.h>
2488  #include <linux/spinlock.h>
2489  #include <linux/pci.h>
2490 +#include <linux/gpio.h>
2491  #include <linux/mod_devicetable.h>
2492  #include <linux/dma-mapping.h>
2493 +#include <linux/platform_device.h>
2494
2495  #include <linux/ssb/ssb_regs.h>
2496
2497 @@ -16,19 +18,29 @@ struct pcmcia_device;
2498  struct ssb_bus;
2499  struct ssb_driver;
2500
2501 +struct ssb_sprom_core_pwr_info {
2502 +       u8 itssi_2g, itssi_5g;
2503 +       u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
2504 +       u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
2505 +};
2506 +
2507  struct ssb_sprom {
2508         u8 revision;
2509 -       u8 il0mac[6];           /* MAC address for 802.11b/g */
2510 -       u8 et0mac[6];           /* MAC address for Ethernet */
2511 -       u8 et1mac[6];           /* MAC address for 802.11a */
2512 +       u8 il0mac[6] __aligned(sizeof(u16));    /* MAC address for 802.11b/g */
2513 +       u8 et0mac[6] __aligned(sizeof(u16));    /* MAC address for Ethernet */
2514 +       u8 et1mac[6] __aligned(sizeof(u16));    /* MAC address for 802.11a */
2515         u8 et0phyaddr;          /* MII address for enet0 */
2516         u8 et1phyaddr;          /* MII address for enet1 */
2517         u8 et0mdcport;          /* MDIO for enet0 */
2518         u8 et1mdcport;          /* MDIO for enet1 */
2519 +       u16 dev_id;             /* Device ID overriding e.g. PCI ID */
2520         u16 board_rev;          /* Board revision number from SPROM. */
2521 +       u16 board_num;          /* Board number from SPROM. */
2522 +       u16 board_type;         /* Board type from SPROM. */
2523         u8 country_code;        /* Country Code */
2524 -       u16 leddc_on_time;      /* LED Powersave Duty Cycle On Count */
2525 -       u16 leddc_off_time;     /* LED Powersave Duty Cycle Off Count */
2526 +       char alpha2[2];         /* Country Code as two chars like EU or US */
2527 +       u8 leddc_on_time;       /* LED Powersave Duty Cycle On Count */
2528 +       u8 leddc_off_time;      /* LED Powersave Duty Cycle Off Count */
2529         u8 ant_available_a;     /* 2GHz antenna available bits (up to 4) */
2530         u8 ant_available_bg;    /* 5GHz antenna available bits (up to 4) */
2531         u16 pa0b0;
2532 @@ -47,10 +59,10 @@ struct ssb_sprom {
2533         u8 gpio1;               /* GPIO pin 1 */
2534         u8 gpio2;               /* GPIO pin 2 */
2535         u8 gpio3;               /* GPIO pin 3 */
2536 -       u16 maxpwr_bg;          /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
2537 -       u16 maxpwr_al;          /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
2538 -       u16 maxpwr_a;           /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
2539 -       u16 maxpwr_ah;          /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
2540 +       u8 maxpwr_bg;           /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
2541 +       u8 maxpwr_al;           /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
2542 +       u8 maxpwr_a;            /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
2543 +       u8 maxpwr_ah;           /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
2544         u8 itssi_a;             /* Idle TSSI Target for A-PHY */
2545         u8 itssi_bg;            /* Idle TSSI Target for B/G-PHY */
2546         u8 tri2g;               /* 2.4GHz TX isolation */
2547 @@ -61,8 +73,8 @@ struct ssb_sprom {
2548         u8 txpid5gl[4];         /* 4.9 - 5.1GHz TX power index */
2549         u8 txpid5g[4];          /* 5.1 - 5.5GHz TX power index */
2550         u8 txpid5gh[4];         /* 5.5 - ...GHz TX power index */
2551 -       u8 rxpo2g;              /* 2GHz RX power offset */
2552 -       u8 rxpo5g;              /* 5GHz RX power offset */
2553 +       s8 rxpo2g;              /* 2GHz RX power offset */
2554 +       s8 rxpo5g;              /* 5GHz RX power offset */
2555         u8 rssisav2g;           /* 2GHz RSSI params */
2556         u8 rssismc2g;
2557         u8 rssismf2g;
2558 @@ -82,16 +94,13 @@ struct ssb_sprom {
2559         u16 boardflags2_hi;     /* Board flags (bits 48-63) */
2560         /* TODO store board flags in a single u64 */
2561
2562 +       struct ssb_sprom_core_pwr_info core_pwr_info[4];
2563 +
2564         /* Antenna gain values for up to 4 antennas
2565          * on each band. Values in dBm/4 (Q5.2). Negative gain means the
2566          * loss in the connectors is bigger than the gain. */
2567         struct {
2568 -               struct {
2569 -                       s8 a0, a1, a2, a3;
2570 -               } ghz24;        /* 2.4GHz band */
2571 -               struct {
2572 -                       s8 a0, a1, a2, a3;
2573 -               } ghz5;         /* 5GHz band */
2574 +               s8 a0, a1, a2, a3;
2575         } antenna_gain;
2576
2577         struct {
2578 @@ -103,14 +112,85 @@ struct ssb_sprom {
2579                 } ghz5;
2580         } fem;
2581
2582 -       /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
2583 +       u16 mcs2gpo[8];
2584 +       u16 mcs5gpo[8];
2585 +       u16 mcs5glpo[8];
2586 +       u16 mcs5ghpo[8];
2587 +       u8 opo;
2588 +
2589 +       u8 rxgainerr2ga[3];
2590 +       u8 rxgainerr5gla[3];
2591 +       u8 rxgainerr5gma[3];
2592 +       u8 rxgainerr5gha[3];
2593 +       u8 rxgainerr5gua[3];
2594 +
2595 +       u8 noiselvl2ga[3];
2596 +       u8 noiselvl5gla[3];
2597 +       u8 noiselvl5gma[3];
2598 +       u8 noiselvl5gha[3];
2599 +       u8 noiselvl5gua[3];
2600 +
2601 +       u8 regrev;
2602 +       u8 txchain;
2603 +       u8 rxchain;
2604 +       u8 antswitch;
2605 +       u16 cddpo;
2606 +       u16 stbcpo;
2607 +       u16 bw40po;
2608 +       u16 bwduppo;
2609 +
2610 +       u8 tempthresh;
2611 +       u8 tempoffset;
2612 +       u16 rawtempsense;
2613 +       u8 measpower;
2614 +       u8 tempsense_slope;
2615 +       u8 tempcorrx;
2616 +       u8 tempsense_option;
2617 +       u8 freqoffset_corr;
2618 +       u8 iqcal_swp_dis;
2619 +       u8 hw_iqcal_en;
2620 +       u8 elna2g;
2621 +       u8 elna5g;
2622 +       u8 phycal_tempdelta;
2623 +       u8 temps_period;
2624 +       u8 temps_hysteresis;
2625 +       u8 measpower1;
2626 +       u8 measpower2;
2627 +       u8 pcieingress_war;
2628 +
2629 +       /* power per rate from sromrev 9 */
2630 +       u16 cckbw202gpo;
2631 +       u16 cckbw20ul2gpo;
2632 +       u32 legofdmbw202gpo;
2633 +       u32 legofdmbw20ul2gpo;
2634 +       u32 legofdmbw205glpo;
2635 +       u32 legofdmbw20ul5glpo;
2636 +       u32 legofdmbw205gmpo;
2637 +       u32 legofdmbw20ul5gmpo;
2638 +       u32 legofdmbw205ghpo;
2639 +       u32 legofdmbw20ul5ghpo;
2640 +       u32 mcsbw202gpo;
2641 +       u32 mcsbw20ul2gpo;
2642 +       u32 mcsbw402gpo;
2643 +       u32 mcsbw205glpo;
2644 +       u32 mcsbw20ul5glpo;
2645 +       u32 mcsbw405glpo;
2646 +       u32 mcsbw205gmpo;
2647 +       u32 mcsbw20ul5gmpo;
2648 +       u32 mcsbw405gmpo;
2649 +       u32 mcsbw205ghpo;
2650 +       u32 mcsbw20ul5ghpo;
2651 +       u32 mcsbw405ghpo;
2652 +       u16 mcs32po;
2653 +       u16 legofdm40duppo;
2654 +       u8 sar2g;
2655 +       u8 sar5g;
2656  };
2657
2658  /* Information about the PCB the circuitry is soldered on. */
2659  struct ssb_boardinfo {
2660         u16 vendor;
2661         u16 type;
2662 -       u8  rev;
2663  };
2664
2665
2666 @@ -166,6 +246,7 @@ struct ssb_bus_ops {
2667  #define SSB_DEV_MINI_MACPHY    0x823
2668  #define SSB_DEV_ARM_1176       0x824
2669  #define SSB_DEV_ARM_7TDMI      0x825
2670 +#define SSB_DEV_ARM_CM3                0x82A
2671
2672  /* Vendor-ID values */
2673  #define SSB_VENDOR_BROADCOM    0x4243
2674 @@ -260,13 +341,61 @@ enum ssb_bustype {
2675  #define SSB_BOARDVENDOR_DELL   0x1028  /* Dell */
2676  #define SSB_BOARDVENDOR_HP     0x0E11  /* HP */
2677  /* board_type */
2678 +#define SSB_BOARD_BCM94301CB   0x0406
2679 +#define SSB_BOARD_BCM94301MP   0x0407
2680 +#define SSB_BOARD_BU4309       0x040A
2681 +#define SSB_BOARD_BCM94309CB   0x040B
2682 +#define SSB_BOARD_BCM4309MP    0x040C
2683 +#define SSB_BOARD_BU4306       0x0416
2684  #define SSB_BOARD_BCM94306MP   0x0418
2685  #define SSB_BOARD_BCM4309G     0x0421
2686  #define SSB_BOARD_BCM4306CB    0x0417
2687 -#define SSB_BOARD_BCM4309MP    0x040C
2688 +#define SSB_BOARD_BCM94306PC   0x0425  /* pcmcia 3.3v 4306 card */
2689 +#define SSB_BOARD_BCM94306CBSG 0x042B  /* with SiGe PA */
2690 +#define SSB_BOARD_PCSG94306    0x042D  /* with SiGe PA */
2691 +#define SSB_BOARD_BU4704SD     0x042E  /* with sdram */
2692 +#define SSB_BOARD_BCM94704AGR  0x042F  /* dual 11a/11g Router */
2693 +#define SSB_BOARD_BCM94308MP   0x0430  /* 11a-only minipci */
2694 +#define SSB_BOARD_BU4318       0x0447
2695 +#define SSB_BOARD_CB4318       0x0448
2696 +#define SSB_BOARD_MPG4318      0x0449
2697  #define SSB_BOARD_MP4318       0x044A
2698 -#define SSB_BOARD_BU4306       0x0416
2699 -#define SSB_BOARD_BU4309       0x040A
2700 +#define SSB_BOARD_SD4318       0x044B
2701 +#define SSB_BOARD_BCM94306P    0x044C  /* with SiGe */
2702 +#define SSB_BOARD_BCM94303MP   0x044E
2703 +#define SSB_BOARD_BCM94306MPM  0x0450
2704 +#define SSB_BOARD_BCM94306MPL  0x0453
2705 +#define SSB_BOARD_PC4303       0x0454  /* pcmcia */
2706 +#define SSB_BOARD_BCM94306MPLNA        0x0457
2707 +#define SSB_BOARD_BCM94306MPH  0x045B
2708 +#define SSB_BOARD_BCM94306PCIV 0x045C
2709 +#define SSB_BOARD_BCM94318MPGH 0x0463
2710 +#define SSB_BOARD_BU4311       0x0464
2711 +#define SSB_BOARD_BCM94311MC   0x0465
2712 +#define SSB_BOARD_BCM94311MCAG 0x0466
2713 +/* 4321 boards */
2714 +#define SSB_BOARD_BU4321       0x046B
2715 +#define SSB_BOARD_BU4321E      0x047C
2716 +#define SSB_BOARD_MP4321       0x046C
2717 +#define SSB_BOARD_CB2_4321     0x046D
2718 +#define SSB_BOARD_CB2_4321_AG  0x0066
2719 +#define SSB_BOARD_MC4321       0x046E
2720 +/* 4325 boards */
2721 +#define SSB_BOARD_BCM94325DEVBU        0x0490
2722 +#define SSB_BOARD_BCM94325BGABU        0x0491
2723 +#define SSB_BOARD_BCM94325SDGWB        0x0492
2724 +#define SSB_BOARD_BCM94325SDGMDL       0x04AA
2725 +#define SSB_BOARD_BCM94325SDGMDL2      0x04C6
2726 +#define SSB_BOARD_BCM94325SDGMDL3      0x04C9
2727 +#define SSB_BOARD_BCM94325SDABGWBA     0x04E1
2728 +/* 4322 boards */
2729 +#define SSB_BOARD_BCM94322MC   0x04A4
2730 +#define SSB_BOARD_BCM94322USB  0x04A8  /* dualband */
2731 +#define SSB_BOARD_BCM94322HM   0x04B0
2732 +#define SSB_BOARD_BCM94322USB2D        0x04Bf  /* single band discrete front end */
2733 +/* 4312 boards */
2734 +#define SSB_BOARD_BU4312       0x048A
2735 +#define SSB_BOARD_BCM4312MCGSG 0x04B5
2736  /* chip_package */
2737  #define SSB_CHIPPACK_BCM4712S  1       /* Small 200pin 4712 */
2738  #define SSB_CHIPPACK_BCM4712M  2       /* Medium 225pin 4712 */
2739 @@ -354,7 +483,11 @@ struct ssb_bus {
2740  #ifdef CONFIG_SSB_EMBEDDED
2741         /* Lock for GPIO register access. */
2742         spinlock_t gpio_lock;
2743 +       struct platform_device *watchdog;
2744  #endif /* EMBEDDED */
2745 +#ifdef CONFIG_SSB_DRIVER_GPIO
2746 +       struct gpio_chip gpio;
2747 +#endif /* DRIVER_GPIO */
2748
2749         /* Internal-only stuff follows. Do not touch. */
2750         struct list_head list;
2751 --- a/include/linux/ssb/ssb_driver_chipcommon.h
2752 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
2753 @@ -219,6 +219,7 @@
2754  #define SSB_CHIPCO_PMU_CTL                     0x0600 /* PMU control */
2755  #define  SSB_CHIPCO_PMU_CTL_ILP_DIV            0xFFFF0000 /* ILP div mask */
2756  #define  SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT      16
2757 +#define  SSB_CHIPCO_PMU_CTL_PLL_UPD            0x00000400
2758  #define  SSB_CHIPCO_PMU_CTL_NOILPONW           0x00000200 /* No ILP on wait */
2759  #define  SSB_CHIPCO_PMU_CTL_HTREQEN            0x00000100 /* HT req enable */
2760  #define  SSB_CHIPCO_PMU_CTL_ALPREQEN           0x00000080 /* ALP req enable */
2761 @@ -504,7 +505,9 @@
2762  #define SSB_CHIPCO_FLASHCTL_ST_SE      0x02D8          /* Sector Erase */
2763  #define SSB_CHIPCO_FLASHCTL_ST_BE      0x00C7          /* Bulk Erase */
2764  #define SSB_CHIPCO_FLASHCTL_ST_DP      0x00B9          /* Deep Power-down */
2765 -#define SSB_CHIPCO_FLASHCTL_ST_RSIG    0x03AB          /* Read Electronic Signature */
2766 +#define SSB_CHIPCO_FLASHCTL_ST_RES     0x03AB          /* Read Electronic Signature */
2767 +#define SSB_CHIPCO_FLASHCTL_ST_CSA     0x1000          /* Keep chip select asserted */
2768 +#define SSB_CHIPCO_FLASHCTL_ST_SSE     0x0220          /* Sub-sector Erase */
2769
2770  /* Status register bits for ST flashes */
2771  #define SSB_CHIPCO_FLASHSTA_ST_WIP     0x01            /* Write In Progress */
2772 @@ -588,7 +591,10 @@ struct ssb_chipcommon {
2773         u32 status;
2774         /* Fast Powerup Delay constant */
2775         u16 fast_pwrup_delay;
2776 +       spinlock_t gpio_lock;
2777         struct ssb_chipcommon_pmu pmu;
2778 +       u32 ticks_per_ms;
2779 +       u32 max_timer_ms;
2780  };
2781
2782  static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
2783 @@ -628,8 +634,7 @@ enum ssb_clkmode {
2784  extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
2785                                      enum ssb_clkmode mode);
2786
2787 -extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
2788 -                                         u32 ticks);
2789 +extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
2790
2791  void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
2792
2793 @@ -642,6 +647,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi
2794  u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value);
2795  u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value);
2796  u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value);
2797 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value);
2798 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value);
2799
2800  #ifdef CONFIG_SSB_SERIAL
2801  extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
2802 @@ -661,5 +668,6 @@ enum ssb_pmu_ldo_volt_id {
2803  void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
2804                              enum ssb_pmu_ldo_volt_id id, u32 voltage);
2805  void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
2806 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid);
2807
2808  #endif /* LINUX_SSB_CHIPCO_H_ */
2809 --- a/include/linux/ssb/ssb_driver_extif.h
2810 +++ b/include/linux/ssb/ssb_driver_extif.h
2811 @@ -152,12 +152,16 @@
2812  /* watchdog */
2813  #define SSB_EXTIF_WATCHDOG_CLK         48000000        /* Hz */
2814
2815 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER   ((1 << 28) - 1)
2816 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS        (SSB_EXTIF_WATCHDOG_MAX_TIMER \
2817 +                                        / (SSB_EXTIF_WATCHDOG_CLK / 1000))
2818
2819
2820  #ifdef CONFIG_SSB_DRIVER_EXTIF
2821
2822  struct ssb_extif {
2823         struct ssb_device *dev;
2824 +       spinlock_t gpio_lock;
2825  };
2826
2827  static inline bool ssb_extif_available(struct ssb_extif *extif)
2828 @@ -171,8 +175,7 @@ extern void ssb_extif_get_clockcontrol(s
2829  extern void ssb_extif_timing_init(struct ssb_extif *extif,
2830                                   unsigned long ns);
2831
2832 -extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
2833 -                                        u32 ticks);
2834 +extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
2835
2836  /* Extif GPIO pin access */
2837  u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
2838 @@ -205,10 +208,52 @@ void ssb_extif_get_clockcontrol(struct s
2839  }
2840
2841  static inline
2842 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
2843 -                                 u32 ticks)
2844 +void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
2845  {
2846  }
2847
2848 +static inline
2849 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
2850 +{
2851 +       return 0;
2852 +}
2853 +
2854 +static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
2855 +{
2856 +       return 0;
2857 +}
2858 +
2859 +static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
2860 +                                    u32 value)
2861 +{
2862 +       return 0;
2863 +}
2864 +
2865 +static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
2866 +                                      u32 value)
2867 +{
2868 +       return 0;
2869 +}
2870 +
2871 +static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
2872 +                                         u32 value)
2873 +{
2874 +       return 0;
2875 +}
2876 +
2877 +static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
2878 +                                        u32 value)
2879 +{
2880 +       return 0;
2881 +}
2882 +
2883 +#ifdef CONFIG_SSB_SERIAL
2884 +static inline int ssb_extif_serial_init(struct ssb_extif *extif,
2885 +                                       struct ssb_serial_port *ports)
2886 +{
2887 +       return 0;
2888 +}
2889 +#endif /* CONFIG_SSB_SERIAL */
2890 +
2891  #endif /* CONFIG_SSB_DRIVER_EXTIF */
2892  #endif /* LINUX_SSB_EXTIFCORE_H_ */
2893 --- a/include/linux/ssb/ssb_driver_gige.h
2894 +++ b/include/linux/ssb/ssb_driver_gige.h
2895 @@ -2,6 +2,7 @@
2896  #define LINUX_SSB_DRIVER_GIGE_H_
2897
2898  #include <linux/ssb/ssb.h>
2899 +#include <linux/bug.h>
2900  #include <linux/pci.h>
2901  #include <linux/spinlock.h>
2902
2903 @@ -96,21 +97,16 @@ static inline bool ssb_gige_must_flush_p
2904         return 0;
2905  }
2906
2907 -#ifdef CONFIG_BCM47XX
2908 -#include <asm/mach-bcm47xx/nvram.h>
2909  /* Get the device MAC address */
2910 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2911 -{
2912 -       char buf[20];
2913 -       if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
2914 -               return;
2915 -       nvram_parse_macaddr(buf, macaddr);
2916 -}
2917 -#else
2918 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2919 +static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2920  {
2921 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
2922 +       if (!dev)
2923 +               return -ENODEV;
2924 +
2925 +       memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
2926 +       return 0;
2927  }
2928 -#endif
2929
2930  extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
2931                                           struct pci_dev *pdev);
2932 @@ -174,6 +170,10 @@ static inline bool ssb_gige_must_flush_p
2933  {
2934         return 0;
2935  }
2936 +static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2937 +{
2938 +       return -ENODEV;
2939 +}
2940
2941  #endif /* CONFIG_SSB_DRIVER_GIGE */
2942  #endif /* LINUX_SSB_DRIVER_GIGE_H_ */
2943 --- a/include/linux/ssb/ssb_driver_mips.h
2944 +++ b/include/linux/ssb/ssb_driver_mips.h
2945 @@ -13,6 +13,24 @@ struct ssb_serial_port {
2946         unsigned int reg_shift;
2947  };
2948
2949 +struct ssb_pflash {
2950 +       bool present;
2951 +       u8 buswidth;
2952 +       u32 window;
2953 +       u32 window_size;
2954 +};
2955 +
2956 +#ifdef CONFIG_SSB_SFLASH
2957 +struct ssb_sflash {
2958 +       bool present;
2959 +       u32 window;
2960 +       u32 blocksize;
2961 +       u16 numblocks;
2962 +       u32 size;
2963 +
2964 +       void *priv;
2965 +};
2966 +#endif
2967
2968  struct ssb_mipscore {
2969         struct ssb_device *dev;
2970 @@ -20,9 +38,10 @@ struct ssb_mipscore {
2971         int nr_serial_ports;
2972         struct ssb_serial_port serial_ports[4];
2973
2974 -       u8 flash_buswidth;
2975 -       u32 flash_window;
2976 -       u32 flash_window_size;
2977 +       struct ssb_pflash pflash;
2978 +#ifdef CONFIG_SSB_SFLASH
2979 +       struct ssb_sflash sflash;
2980 +#endif
2981  };
2982
2983  extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
2984 @@ -41,6 +60,11 @@ void ssb_mipscore_init(struct ssb_mipsco
2985  {
2986  }
2987
2988 +static inline unsigned int ssb_mips_irq(struct ssb_device *dev)
2989 +{
2990 +       return 0;
2991 +}
2992 +
2993  #endif /* CONFIG_SSB_DRIVER_MIPS */
2994
2995  #endif /* LINUX_SSB_MIPSCORE_H_ */
2996 --- a/include/linux/ssb/ssb_regs.h
2997 +++ b/include/linux/ssb/ssb_regs.h
2998 @@ -172,6 +172,7 @@
2999  #define SSB_SPROMSIZE_WORDS_R4         220
3000  #define SSB_SPROMSIZE_BYTES_R123       (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
3001  #define SSB_SPROMSIZE_BYTES_R4         (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
3002 +#define SSB_SPROMSIZE_WORDS_R10                230
3003  #define SSB_SPROM_BASE1                        0x1000
3004  #define SSB_SPROM_BASE31               0x0800
3005  #define SSB_SPROM_REVISION             0x007E
3006 @@ -228,6 +229,7 @@
3007  #define  SSB_SPROM1_AGAIN_BG_SHIFT     0
3008  #define  SSB_SPROM1_AGAIN_A            0xFF00  /* A-PHY */
3009  #define  SSB_SPROM1_AGAIN_A_SHIFT      8
3010 +#define SSB_SPROM1_CCODE               0x0076
3011
3012  /* SPROM Revision 2 (inherits from rev 1) */
3013  #define SSB_SPROM2_BFLHI               0x0038  /* Boardflags (high 16 bits) */
3014 @@ -267,6 +269,7 @@
3015  #define  SSB_SPROM3_OFDMGPO            0x107A  /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
3016
3017  /* SPROM Revision 4 */
3018 +#define SSB_SPROM4_BOARDREV            0x0042  /* Board revision */
3019  #define SSB_SPROM4_BFLLO               0x0044  /* Boardflags (low 16 bits) */
3020  #define SSB_SPROM4_BFLHI               0x0046  /* Board Flags Hi */
3021  #define SSB_SPROM4_BFL2LO              0x0048  /* Board flags 2 (low 16 bits) */
3022 @@ -287,11 +290,11 @@
3023  #define  SSB_SPROM4_ETHPHY_ET1A_SHIFT  5
3024  #define  SSB_SPROM4_ETHPHY_ET0M                (1<<14) /* MDIO for enet0 */
3025  #define  SSB_SPROM4_ETHPHY_ET1M                (1<<15) /* MDIO for enet1 */
3026 -#define SSB_SPROM4_ANTAVAIL            0x005D  /* Antenna available bitfields */
3027 -#define  SSB_SPROM4_ANTAVAIL_A         0x00FF  /* A-PHY bitfield */
3028 -#define  SSB_SPROM4_ANTAVAIL_A_SHIFT   0
3029 -#define  SSB_SPROM4_ANTAVAIL_BG                0xFF00  /* B-PHY and G-PHY bitfield */
3030 -#define  SSB_SPROM4_ANTAVAIL_BG_SHIFT  8
3031 +#define SSB_SPROM4_ANTAVAIL            0x005C  /* Antenna available bitfields */
3032 +#define  SSB_SPROM4_ANTAVAIL_BG                0x00FF  /* B-PHY and G-PHY bitfield */
3033 +#define  SSB_SPROM4_ANTAVAIL_BG_SHIFT  0
3034 +#define  SSB_SPROM4_ANTAVAIL_A         0xFF00  /* A-PHY bitfield */
3035 +#define  SSB_SPROM4_ANTAVAIL_A_SHIFT   8
3036  #define SSB_SPROM4_AGAIN01             0x005E  /* Antenna Gain (in dBm Q5.2) */
3037  #define  SSB_SPROM4_AGAIN0             0x00FF  /* Antenna 0 */
3038  #define  SSB_SPROM4_AGAIN0_SHIFT       0
3039 @@ -389,6 +392,11 @@
3040  #define  SSB_SPROM8_GPIOB_P2           0x00FF  /* Pin 2 */
3041  #define  SSB_SPROM8_GPIOB_P3           0xFF00  /* Pin 3 */
3042  #define  SSB_SPROM8_GPIOB_P3_SHIFT     8
3043 +#define SSB_SPROM8_LEDDC               0x009A
3044 +#define  SSB_SPROM8_LEDDC_ON           0xFF00  /* oncount */
3045 +#define  SSB_SPROM8_LEDDC_ON_SHIFT     8
3046 +#define  SSB_SPROM8_LEDDC_OFF          0x00FF  /* offcount */
3047 +#define  SSB_SPROM8_LEDDC_OFF_SHIFT    0
3048  #define SSB_SPROM8_ANTAVAIL            0x009C  /* Antenna available bitfields*/
3049  #define  SSB_SPROM8_ANTAVAIL_A         0xFF00  /* A-PHY bitfield */
3050  #define  SSB_SPROM8_ANTAVAIL_A_SHIFT   8
3051 @@ -404,6 +412,13 @@
3052  #define  SSB_SPROM8_AGAIN2_SHIFT       0
3053  #define  SSB_SPROM8_AGAIN3             0xFF00  /* Antenna 3 */
3054  #define  SSB_SPROM8_AGAIN3_SHIFT       8
3055 +#define SSB_SPROM8_TXRXC               0x00A2
3056 +#define  SSB_SPROM8_TXRXC_TXCHAIN      0x000f
3057 +#define  SSB_SPROM8_TXRXC_TXCHAIN_SHIFT        0
3058 +#define  SSB_SPROM8_TXRXC_RXCHAIN      0x00f0
3059 +#define  SSB_SPROM8_TXRXC_RXCHAIN_SHIFT        4
3060 +#define  SSB_SPROM8_TXRXC_SWITCH       0xff00
3061 +#define  SSB_SPROM8_TXRXC_SWITCH_SHIFT 8
3062  #define SSB_SPROM8_RSSIPARM2G          0x00A4  /* RSSI params for 2GHz */
3063  #define  SSB_SPROM8_RSSISMF2G          0x000F
3064  #define  SSB_SPROM8_RSSISMC2G          0x00F0
3065 @@ -430,6 +445,7 @@
3066  #define  SSB_SPROM8_TRI5GH_SHIFT       8
3067  #define SSB_SPROM8_RXPO                        0x00AC  /* RX power offsets */
3068  #define  SSB_SPROM8_RXPO2G             0x00FF  /* 2GHz RX power offset */
3069 +#define  SSB_SPROM8_RXPO2G_SHIFT       0
3070  #define  SSB_SPROM8_RXPO5G             0xFF00  /* 5GHz RX power offset */
3071  #define  SSB_SPROM8_RXPO5G_SHIFT       8
3072  #define SSB_SPROM8_FEM2G               0x00AE
3073 @@ -445,10 +461,71 @@
3074  #define  SSB_SROM8_FEM_ANTSWLUT                0xF800
3075  #define  SSB_SROM8_FEM_ANTSWLUT_SHIFT  11
3076  #define SSB_SPROM8_THERMAL             0x00B2
3077 -#define SSB_SPROM8_MPWR_RAWTS          0x00B4
3078 -#define SSB_SPROM8_TS_SLP_OPT_CORRX    0x00B6
3079 -#define SSB_SPROM8_FOC_HWIQ_IQSWP      0x00B8
3080 -#define SSB_SPROM8_PHYCAL_TEMPDELTA    0x00BA
3081 +#define  SSB_SPROM8_THERMAL_OFFSET     0x00ff
3082 +#define  SSB_SPROM8_THERMAL_OFFSET_SHIFT       0
3083 +#define  SSB_SPROM8_THERMAL_TRESH      0xff00
3084 +#define  SSB_SPROM8_THERMAL_TRESH_SHIFT        8
3085 +/* Temp sense related entries */
3086 +#define SSB_SPROM8_RAWTS               0x00B4
3087 +#define  SSB_SPROM8_RAWTS_RAWTEMP      0x01ff
3088 +#define  SSB_SPROM8_RAWTS_RAWTEMP_SHIFT        0
3089 +#define  SSB_SPROM8_RAWTS_MEASPOWER    0xfe00
3090 +#define  SSB_SPROM8_RAWTS_MEASPOWER_SHIFT      9
3091 +#define SSB_SPROM8_OPT_CORRX           0x00B6
3092 +#define  SSB_SPROM8_OPT_CORRX_TEMP_SLOPE       0x00ff
3093 +#define  SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT 0
3094 +#define  SSB_SPROM8_OPT_CORRX_TEMPCORRX        0xfc00
3095 +#define  SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT  10
3096 +#define  SSB_SPROM8_OPT_CORRX_TEMP_OPTION      0x0300
3097 +#define  SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT        8
3098 +/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
3099 +#define SSB_SPROM8_HWIQ_IQSWP          0x00B8
3100 +#define  SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR       0x000f
3101 +#define  SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT 0
3102 +#define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP       0x0010
3103 +#define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
3104 +#define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL        0x0020
3105 +#define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT  5
3106 +#define SSB_SPROM8_TEMPDELTA           0x00BC
3107 +#define  SSB_SPROM8_TEMPDELTA_PHYCAL   0x00ff
3108 +#define  SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT     0
3109 +#define  SSB_SPROM8_TEMPDELTA_PERIOD   0x0f00
3110 +#define  SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT     8
3111 +#define  SSB_SPROM8_TEMPDELTA_HYSTERESIS       0xf000
3112 +#define  SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT 12
3113 +
3114 +/* There are 4 blocks with power info sharing the same layout */
3115 +#define SSB_SROM8_PWR_INFO_CORE0       0x00C0
3116 +#define SSB_SROM8_PWR_INFO_CORE1       0x00E0
3117 +#define SSB_SROM8_PWR_INFO_CORE2       0x0100
3118 +#define SSB_SROM8_PWR_INFO_CORE3       0x0120
3119 +
3120 +#define SSB_SROM8_2G_MAXP_ITSSI                0x00
3121 +#define  SSB_SPROM8_2G_MAXP            0x00FF
3122 +#define  SSB_SPROM8_2G_ITSSI           0xFF00
3123 +#define  SSB_SPROM8_2G_ITSSI_SHIFT     8
3124 +#define SSB_SROM8_2G_PA_0              0x02    /* 2GHz power amp settings */
3125 +#define SSB_SROM8_2G_PA_1              0x04
3126 +#define SSB_SROM8_2G_PA_2              0x06
3127 +#define SSB_SROM8_5G_MAXP_ITSSI                0x08    /* 5GHz ITSSI and 5.3GHz Max Power */
3128 +#define  SSB_SPROM8_5G_MAXP            0x00FF
3129 +#define  SSB_SPROM8_5G_ITSSI           0xFF00
3130 +#define  SSB_SPROM8_5G_ITSSI_SHIFT     8
3131 +#define SSB_SPROM8_5GHL_MAXP           0x0A    /* 5.2GHz and 5.8GHz Max Power */
3132 +#define  SSB_SPROM8_5GH_MAXP           0x00FF
3133 +#define  SSB_SPROM8_5GL_MAXP           0xFF00
3134 +#define  SSB_SPROM8_5GL_MAXP_SHIFT     8
3135 +#define SSB_SROM8_5G_PA_0              0x0C    /* 5.3GHz power amp settings */
3136 +#define SSB_SROM8_5G_PA_1              0x0E
3137 +#define SSB_SROM8_5G_PA_2              0x10
3138 +#define SSB_SROM8_5GL_PA_0             0x12    /* 5.2GHz power amp settings */
3139 +#define SSB_SROM8_5GL_PA_1             0x14
3140 +#define SSB_SROM8_5GL_PA_2             0x16
3141 +#define SSB_SROM8_5GH_PA_0             0x18    /* 5.8GHz power amp settings */
3142 +#define SSB_SROM8_5GH_PA_1             0x1A
3143 +#define SSB_SROM8_5GH_PA_2             0x1C
3144 +
3145 +/* TODO: Make it deprecated */
3146  #define SSB_SPROM8_MAXP_BG             0x00C0  /* Max Power 2GHz in path 1 */
3147  #define  SSB_SPROM8_MAXP_BG_MASK       0x00FF  /* Mask for Max Power 2GHz */
3148  #define  SSB_SPROM8_ITSSI_BG           0xFF00  /* Mask for path 1 itssi_bg */
3149 @@ -473,12 +550,23 @@
3150  #define SSB_SPROM8_PA1HIB0             0x00D8  /* 5.8GHz power amp settings */
3151  #define SSB_SPROM8_PA1HIB1             0x00DA
3152  #define SSB_SPROM8_PA1HIB2             0x00DC
3153 +
3154  #define SSB_SPROM8_CCK2GPO             0x0140  /* CCK power offset */
3155  #define SSB_SPROM8_OFDM2GPO            0x0142  /* 2.4GHz OFDM power offset */
3156  #define SSB_SPROM8_OFDM5GPO            0x0146  /* 5.3GHz OFDM power offset */
3157  #define SSB_SPROM8_OFDM5GLPO           0x014A  /* 5.2GHz OFDM power offset */
3158  #define SSB_SPROM8_OFDM5GHPO           0x014E  /* 5.8GHz OFDM power offset */
3159
3160 +#define SSB_SPROM8_2G_MCSPO            0x0152
3161 +#define SSB_SPROM8_5G_MCSPO            0x0162
3162 +#define SSB_SPROM8_5GL_MCSPO           0x0172
3163 +#define SSB_SPROM8_5GH_MCSPO           0x0182
3164 +
3165 +#define SSB_SPROM8_CDDPO               0x0192
3166 +#define SSB_SPROM8_STBCPO              0x0194
3167 +#define SSB_SPROM8_BW40PO              0x0196
3168 +#define SSB_SPROM8_BWDUPPO             0x0198
3169 +
3170  /* Values for boardflags_lo read from SPROM */
3171  #define SSB_BFL_BTCOEXIST              0x0001  /* implements Bluetooth coexistance */
3172  #define SSB_BFL_PACTRL                 0x0002  /* GPIO 9 controlling the PA */
3173 --- /dev/null
3174 +++ b/include/linux/bcm47xx_wdt.h
3175 @@ -0,0 +1,19 @@
3176 +#ifndef LINUX_BCM47XX_WDT_H_
3177 +#define LINUX_BCM47XX_WDT_H_
3178 +
3179 +#include <linux/types.h>
3180 +
3181 +
3182 +struct bcm47xx_wdt {
3183 +       u32 (*timer_set)(struct bcm47xx_wdt *, u32);
3184 +       u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
3185 +       u32 max_timer_ms;
3186 +
3187 +       void *driver_data;
3188 +};
3189 +
3190 +static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
3191 +{
3192 +       return wdt->driver_data;
3193 +}
3194 +#endif /* LINUX_BCM47XX_WDT_H_ */
3195 --- a/drivers/net/wireless/b43/phy_n.c
3196 +++ b/drivers/net/wireless/b43/phy_n.c
3197 @@ -4259,7 +4259,8 @@ static void b43_nphy_pmu_spur_avoid(stru
3198  #endif
3199  #ifdef CONFIG_B43_SSB
3200         case B43_BUS_SSB:
3201 -               /* FIXME */
3202 +               ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
3203 +                                           avoid);
3204                 break;
3205  #endif
3206         }