target/linux/generic/patches-3.1/020-ssb_update.patch

   1 --- a/drivers/ssb/b43_pci_bridge.c
   2 +++ b/drivers/ssb/b43_pci_bridge.c
   3 @@ -11,6 +11,7 @@
   4   */
   5
   6  #include <linux/pci.h>
   7 +#include <linux/module.h>
   8  #include <linux/ssb/ssb.h>
   9
  10  #include "ssb_private.h"
  11 @@ -28,6 +29,8 @@ static const struct pci_device_id b43_pc
  12         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
  13         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
  14         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
  15 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4322) },
  16 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43222) },
  17         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
  18         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
  19         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
  20 --- a/drivers/ssb/driver_chipcommon_pmu.c
  21 +++ b/drivers/ssb/driver_chipcommon_pmu.c
  22 @@ -12,6 +12,9 @@
  23  #include <linux/ssb/ssb_regs.h>
  24  #include <linux/ssb/ssb_driver_chipcommon.h>
  25  #include <linux/delay.h>
  26 +#ifdef CONFIG_BCM47XX
  27 +#include <asm/mach-bcm47xx/nvram.h>
  28 +#endif
  29
  30  #include "ssb_private.h"
  31
  32 @@ -91,10 +94,6 @@ static void ssb_pmu0_pllinit_r0(struct s
  33         u32 pmuctl, tmp, pllctl;
  34         unsigned int i;
  35
  36 -       if ((bus->chip_id == 0x5354) && !crystalfreq) {
  37 -               /* The 5354 crystal freq is 25MHz */
  38 -               crystalfreq = 25000;
  39 -       }
  40         if (crystalfreq)
  41                 e = pmu0_plltab_find_entry(crystalfreq);
  42         if (!e)
  43 @@ -320,7 +319,11 @@ static void ssb_pmu_pll_init(struct ssb_
  44         u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
  45
  46         if (bus->bustype == SSB_BUSTYPE_SSB) {
  47 -               /* TODO: The user may override the crystal frequency. */
  48 +#ifdef CONFIG_BCM47XX
  49 +               char buf[20];
  50 +               if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
  51 +                       crystalfreq = simple_strtoul(buf, NULL, 0);
  52 +#endif
  53         }
  54
  55         switch (bus->chip_id) {
  56 @@ -329,7 +332,11 @@ static void ssb_pmu_pll_init(struct ssb_
  57                 ssb_pmu1_pllinit_r0(cc, crystalfreq);
  58                 break;
  59         case 0x4328:
  60 +               ssb_pmu0_pllinit_r0(cc, crystalfreq);
  61 +               break;
  62         case 0x5354:
  63 +               if (crystalfreq == 0)
  64 +                       crystalfreq = 25000;
  65                 ssb_pmu0_pllinit_r0(cc, crystalfreq);
  66                 break;
  67         case 0x4322:
  68 @@ -606,3 +613,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
  69
  70  EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
  71  EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
  72 +
  73 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
  74 +{
  75 +       struct ssb_bus *bus = cc->dev->bus;
  76 +
  77 +       switch (bus->chip_id) {
  78 +       case 0x5354:
  79 +               /* 5354 chip uses a non programmable PLL of frequency 240MHz */
  80 +               return 240000000;
  81 +       default:
  82 +               ssb_printk(KERN_ERR PFX
  83 +                          "ERROR: PMU cpu clock unknown for device %04X\n",
  84 +                          bus->chip_id);
  85 +               return 0;
  86 +       }
  87 +}
  88 +
  89 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
  90 +{
  91 +       struct ssb_bus *bus = cc->dev->bus;
  92 +
  93 +       switch (bus->chip_id) {
  94 +       case 0x5354:
  95 +               return 120000000;
  96 +       default:
  97 +               ssb_printk(KERN_ERR PFX
  98 +                          "ERROR: PMU controlclock unknown for device %04X\n",
  99 +                          bus->chip_id);
 100 +               return 0;
 101 +       }
 102 +}
 103 --- a/drivers/ssb/driver_mipscore.c
 104 +++ b/drivers/ssb/driver_mipscore.c
 105 @@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
 106         struct ssb_bus *bus = mcore->dev->bus;
 107         u32 pll_type, n, m, rate = 0;
 108
 109 +       if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
 110 +               return ssb_pmu_get_cpu_clock(&bus->chipco);
 111 +
 112         if (bus->extif.dev) {
 113                 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
 114         } else if (bus->chipco.dev) {
 115 --- a/drivers/ssb/driver_pcicore.c
 116 +++ b/drivers/ssb/driver_pcicore.c
 117 @@ -74,7 +74,7 @@ static u32 get_cfgspace_addr(struct ssb_
 118         u32 tmp;
 119
 120         /* We do only have one cardbus device behind the bridge. */
 121 -       if (pc->cardbusmode && (dev >= 1))
 122 +       if (pc->cardbusmode && (dev > 1))
 123                 goto out;
 124
 125         if (bus == 0) {
 126 --- a/drivers/ssb/main.c
 127 +++ b/drivers/ssb/main.c
 128 @@ -12,6 +12,7 @@
 129
 130  #include <linux/delay.h>
 131  #include <linux/io.h>
 132 +#include <linux/module.h>
 133  #include <linux/ssb/ssb.h>
 134  #include <linux/ssb/ssb_regs.h>
 135  #include <linux/ssb/ssb_driver_gige.h>
 136 @@ -139,19 +140,6 @@ static void ssb_device_put(struct ssb_de
 137                 put_device(dev->dev);
 138  }
 139
 140 -static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
 141 -{
 142 -       if (drv)
 143 -               get_driver(&drv->drv);
 144 -       return drv;
 145 -}
 146 -
 147 -static inline void ssb_driver_put(struct ssb_driver *drv)
 148 -{
 149 -       if (drv)
 150 -               put_driver(&drv->drv);
 151 -}
 152 -
 153  static int ssb_device_resume(struct device *dev)
 154  {
 155         struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
 156 @@ -249,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
 157                         ssb_device_put(sdev);
 158                         continue;
 159                 }
 160 -               sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
 161 -               if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
 162 -                       ssb_device_put(sdev);
 163 +               sdrv = drv_to_ssb_drv(sdev->dev->driver);
 164 +               if (SSB_WARN_ON(!sdrv->remove))
 165                         continue;
 166 -               }
 167                 sdrv->remove(sdev);
 168                 ctx->device_frozen[i] = 1;
 169         }
 170 @@ -292,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
 171                                    dev_name(sdev->dev));
 172                         result = err;
 173                 }
 174 -               ssb_driver_put(sdrv);
 175                 ssb_device_put(sdev);
 176         }
 177
 178 @@ -1093,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
 179         u32 plltype;
 180         u32 clkctl_n, clkctl_m;
 181
 182 +       if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
 183 +               return ssb_pmu_get_controlclock(&bus->chipco);
 184 +
 185         if (ssb_extif_available(&bus->extif))
 186                 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
 187                                            &clkctl_n, &clkctl_m);
 188 @@ -1260,16 +1248,34 @@ void ssb_device_disable(struct ssb_devic
 189  }
 190  EXPORT_SYMBOL(ssb_device_disable);
 191
 192 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
 193 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
 194 +{
 195 +       u16 chip_id = dev->bus->chip_id;
 196 +
 197 +       if (dev->id.coreid == SSB_DEV_80211) {
 198 +               return (chip_id == 0x4322 || chip_id == 43221 ||
 199 +                       chip_id == 43231 || chip_id == 43222);
 200 +       }
 201 +
 202 +       return 0;
 203 +}
 204 +
 205  u32 ssb_dma_translation(struct ssb_device *dev)
 206  {
 207         switch (dev->bus->bustype) {
 208         case SSB_BUSTYPE_SSB:
 209                 return 0;
 210         case SSB_BUSTYPE_PCI:
 211 -               if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64)
 212 +               if (pci_is_pcie(dev->bus->host_pci) &&
 213 +                   ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
 214                         return SSB_PCIE_DMA_H32;
 215 -               else
 216 -                       return SSB_PCI_DMA;
 217 +               } else {
 218 +                       if (ssb_dma_translation_special_bit(dev))
 219 +                               return SSB_PCIE_DMA_H32;
 220 +                       else
 221 +                               return SSB_PCI_DMA;
 222 +               }
 223         default:
 224                 __ssb_dma_not_implemented(dev);
 225         }
 226 --- a/drivers/ssb/pci.c
 227 +++ b/drivers/ssb/pci.c
 228 @@ -178,6 +178,18 @@ err_pci:
 229  #define SPEX(_outvar, _offset, _mask, _shift) \
 230         SPEX16(_outvar, _offset, _mask, _shift)
 231
 232 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift)    \
 233 +       do {    \
 234 +               SPEX(_field[0], _offset +  0, _mask, _shift);   \
 235 +               SPEX(_field[1], _offset +  2, _mask, _shift);   \
 236 +               SPEX(_field[2], _offset +  4, _mask, _shift);   \
 237 +               SPEX(_field[3], _offset +  6, _mask, _shift);   \
 238 +               SPEX(_field[4], _offset +  8, _mask, _shift);   \
 239 +               SPEX(_field[5], _offset + 10, _mask, _shift);   \
 240 +               SPEX(_field[6], _offset + 12, _mask, _shift);   \
 241 +               SPEX(_field[7], _offset + 14, _mask, _shift);   \
 242 +       } while (0)
 243 +
 244
 245  static inline u8 ssb_crc8(u8 crc, u8 data)
 246  {
 247 @@ -331,7 +343,6 @@ static void sprom_extract_r123(struct ss
 248  {
 249         int i;
 250         u16 v;
 251 -       s8 gain;
 252         u16 loc[3];
 253
 254         if (out->revision == 3)                 /* rev 3 moved MAC */
 255 @@ -361,8 +372,9 @@ static void sprom_extract_r123(struct ss
 256         SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
 257         SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
 258         SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
 259 -       SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
 260 -            SSB_SPROM1_BINF_CCODE_SHIFT);
 261 +       if (out->revision == 1)
 262 +               SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
 263 +                    SSB_SPROM1_BINF_CCODE_SHIFT);
 264         SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
 265              SSB_SPROM1_BINF_ANTA_SHIFT);
 266         SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
 267 @@ -388,22 +400,16 @@ static void sprom_extract_r123(struct ss
 268         SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
 269         if (out->revision >= 2)
 270                 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
 271 +       SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
 272 +       SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
 273
 274         /* Extract the antenna gain values. */
 275 -       gain = r123_extract_antgain(out->revision, in,
 276 -                                   SSB_SPROM1_AGAIN_BG,
 277 -                                   SSB_SPROM1_AGAIN_BG_SHIFT);
 278 -       out->antenna_gain.ghz24.a0 = gain;
 279 -       out->antenna_gain.ghz24.a1 = gain;
 280 -       out->antenna_gain.ghz24.a2 = gain;
 281 -       out->antenna_gain.ghz24.a3 = gain;
 282 -       gain = r123_extract_antgain(out->revision, in,
 283 -                                   SSB_SPROM1_AGAIN_A,
 284 -                                   SSB_SPROM1_AGAIN_A_SHIFT);
 285 -       out->antenna_gain.ghz5.a0 = gain;
 286 -       out->antenna_gain.ghz5.a1 = gain;
 287 -       out->antenna_gain.ghz5.a2 = gain;
 288 -       out->antenna_gain.ghz5.a3 = gain;
 289 +       out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
 290 +                                                   SSB_SPROM1_AGAIN_BG,
 291 +                                                   SSB_SPROM1_AGAIN_BG_SHIFT);
 292 +       out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
 293 +                                                   SSB_SPROM1_AGAIN_A,
 294 +                                                   SSB_SPROM1_AGAIN_A_SHIFT);
 295  }
 296
 297  /* Revs 4 5 and 8 have partially shared layout */
 298 @@ -464,14 +470,17 @@ static void sprom_extract_r45(struct ssb
 299         SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
 300         SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
 301              SSB_SPROM4_ETHPHY_ET1A_SHIFT);
 302 +       SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
 303         if (out->revision == 4) {
 304 -               SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
 305 +               SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
 306 +               SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
 307                 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
 308                 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
 309                 SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
 310                 SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
 311         } else {
 312 -               SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
 313 +               SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
 314 +               SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
 315                 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
 316                 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
 317                 SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
 318 @@ -504,16 +513,14 @@ static void sprom_extract_r45(struct ssb
 319         }
 320
 321         /* Extract the antenna gain values. */
 322 -       SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
 323 +       SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
 324              SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
 325 -       SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
 326 +       SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
 327              SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
 328 -       SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
 329 +       SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
 330              SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
 331 -       SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
 332 +       SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
 333              SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
 334 -       memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
 335 -              sizeof(out->antenna_gain.ghz5));
 336
 337         sprom_extract_r458(out, in);
 338
 339 @@ -523,14 +530,22 @@ static void sprom_extract_r45(struct ssb
 340  static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
 341  {
 342         int i;
 343 -       u16 v;
 344 +       u16 v, o;
 345 +       u16 pwr_info_offset[] = {
 346 +               SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
 347 +               SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
 348 +       };
 349 +       BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
 350 +                       ARRAY_SIZE(out->core_pwr_info));
 351
 352         /* extract the MAC address */
 353         for (i = 0; i < 3; i++) {
 354                 v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
 355                 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
 356         }
 357 -       SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
 358 +       SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
 359 +       SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
 360 +       SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
 361         SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
 362         SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
 363         SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
 364 @@ -596,17 +611,127 @@ static void sprom_extract_r8(struct ssb_
 365         SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
 366
 367         /* Extract the antenna gain values. */
 368 -       SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
 369 +       SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
 370              SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
 371 -       SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
 372 +       SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
 373              SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
 374 -       SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
 375 +       SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
 376              SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
 377 -       SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
 378 +       SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
 379              SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
 380 -       memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
 381 -              sizeof(out->antenna_gain.ghz5));
 382
 383 +       /* Extract cores power info info */
 384 +       for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
 385 +               o = pwr_info_offset[i];
 386 +               SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
 387 +                       SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
 388 +               SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
 389 +                       SSB_SPROM8_2G_MAXP, 0);
 390 +
 391 +               SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
 392 +               SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
 393 +               SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
 394 +
 395 +               SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
 396 +                       SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
 397 +               SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
 398 +                       SSB_SPROM8_5G_MAXP, 0);
 399 +               SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
 400 +                       SSB_SPROM8_5GH_MAXP, 0);
 401 +               SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
 402 +                       SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
 403 +
 404 +               SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
 405 +               SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
 406 +               SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
 407 +               SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
 408 +               SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
 409 +               SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
 410 +               SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
 411 +               SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
 412 +               SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
 413 +       }
 414 +
 415 +       /* Extract FEM info */
 416 +       SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
 417 +               SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
 418 +       SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
 419 +               SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
 420 +       SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
 421 +               SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
 422 +       SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
 423 +               SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
 424 +       SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
 425 +               SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
 426 +
 427 +       SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
 428 +               SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
 429 +       SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
 430 +               SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
 431 +       SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
 432 +               SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
 433 +       SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
 434 +               SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
 435 +       SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
 436 +               SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
 437 +
 438 +       SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
 439 +            SSB_SPROM8_LEDDC_ON_SHIFT);
 440 +       SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
 441 +            SSB_SPROM8_LEDDC_OFF_SHIFT);
 442 +
 443 +       SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
 444 +            SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
 445 +       SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
 446 +            SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
 447 +       SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
 448 +            SSB_SPROM8_TXRXC_SWITCH_SHIFT);
 449 +
 450 +       SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
 451 +
 452 +       SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
 453 +       SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
 454 +       SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
 455 +       SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
 456 +
 457 +       SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
 458 +            SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
 459 +       SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
 460 +            SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
 461 +       SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
 462 +            SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
 463 +            SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
 464 +       SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
 465 +            SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
 466 +       SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
 467 +            SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
 468 +            SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
 469 +       SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
 470 +            SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
 471 +            SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
 472 +       SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
 473 +            SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
 474 +            SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
 475 +       SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
 476 +            SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
 477 +
 478 +       SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
 479 +       SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
 480 +       SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
 481 +       SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
 482 +
 483 +       SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
 484 +            SSB_SPROM8_THERMAL_TRESH_SHIFT);
 485 +       SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
 486 +            SSB_SPROM8_THERMAL_OFFSET_SHIFT);
 487 +       SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
 488 +            SSB_SPROM8_TEMPDELTA_PHYCAL,
 489 +            SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
 490 +       SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
 491 +            SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
 492 +       SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
 493 +            SSB_SPROM8_TEMPDELTA_HYSTERESIS,
 494 +            SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
 495         sprom_extract_r458(out, in);
 496
 497         /* TODO - get remaining rev 8 stuff needed */
 498 @@ -736,7 +861,6 @@ static void ssb_pci_get_boardinfo(struct
 499  {
 500         bi->vendor = bus->host_pci->subsystem_vendor;
 501         bi->type = bus->host_pci->subsystem_device;
 502 -       bi->rev = bus->host_pci->revision;
 503  }
 504
 505  int ssb_pci_get_invariants(struct ssb_bus *bus,
 506 --- a/drivers/ssb/pcmcia.c
 507 +++ b/drivers/ssb/pcmcia.c
 508 @@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
 509         case SSB_PCMCIA_CIS_ANTGAIN:
 510                 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
 511                         "antg tpl size");
 512 -               sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
 513 -               sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
 514 -               sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
 515 -               sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
 516 -               sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
 517 -               sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
 518 -               sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
 519 -               sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
 520 +               sprom->antenna_gain.a0 = tuple->TupleData[1];
 521 +               sprom->antenna_gain.a1 = tuple->TupleData[1];
 522 +               sprom->antenna_gain.a2 = tuple->TupleData[1];
 523 +               sprom->antenna_gain.a3 = tuple->TupleData[1];
 524                 break;
 525         case SSB_PCMCIA_CIS_BFLAGS:
 526                 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
 527 --- a/drivers/ssb/scan.c
 528 +++ b/drivers/ssb/scan.c
 529 @@ -318,6 +318,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
 530                         bus->chip_package = 0;
 531                 }
 532         }
 533 +       ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
 534 +                  "package 0x%02X\n", bus->chip_id, bus->chip_rev,
 535 +                  bus->chip_package);
 536         if (!bus->nr_devices)
 537                 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
 538         if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
 539 --- a/drivers/ssb/sdio.c
 540 +++ b/drivers/ssb/sdio.c
 541 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
 542                         case SSB_SDIO_CIS_ANTGAIN:
 543                                 GOTO_ERROR_ON(tuple->size != 2,
 544                                               "antg tpl size");
 545 -                               sprom->antenna_gain.ghz24.a0 = tuple->data[1];
 546 -                               sprom->antenna_gain.ghz24.a1 = tuple->data[1];
 547 -                               sprom->antenna_gain.ghz24.a2 = tuple->data[1];
 548 -                               sprom->antenna_gain.ghz24.a3 = tuple->data[1];
 549 -                               sprom->antenna_gain.ghz5.a0 = tuple->data[1];
 550 -                               sprom->antenna_gain.ghz5.a1 = tuple->data[1];
 551 -                               sprom->antenna_gain.ghz5.a2 = tuple->data[1];
 552 -                               sprom->antenna_gain.ghz5.a3 = tuple->data[1];
 553 +                               sprom->antenna_gain.a0 = tuple->data[1];
 554 +                               sprom->antenna_gain.a1 = tuple->data[1];
 555 +                               sprom->antenna_gain.a2 = tuple->data[1];
 556 +                               sprom->antenna_gain.a3 = tuple->data[1];
 557                                 break;
 558                         case SSB_SDIO_CIS_BFLAGS:
 559                                 GOTO_ERROR_ON((tuple->size != 3) &&
 560 --- a/drivers/ssb/ssb_private.h
 561 +++ b/drivers/ssb/ssb_private.h
 562 @@ -207,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
 563  }
 564  #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
 565
 566 +/* driver_chipcommon_pmu.c */
 567 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
 568 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
 569 +
 570  #endif /* LINUX_SSB_PRIVATE_H_ */
 571 --- a/include/linux/ssb/ssb.h
 572 +++ b/include/linux/ssb/ssb.h
 573 @@ -16,6 +16,12 @@ struct pcmcia_device;
 574  struct ssb_bus;
 575  struct ssb_driver;
 576
 577 +struct ssb_sprom_core_pwr_info {
 578 +       u8 itssi_2g, itssi_5g;
 579 +       u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
 580 +       u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
 581 +};
 582 +
 583  struct ssb_sprom {
 584         u8 revision;
 585         u8 il0mac[6];           /* MAC address for 802.11b/g */
 586 @@ -25,10 +31,13 @@ struct ssb_sprom {
 587         u8 et1phyaddr;          /* MII address for enet1 */
 588         u8 et0mdcport;          /* MDIO for enet0 */
 589         u8 et1mdcport;          /* MDIO for enet1 */
 590 -       u8 board_rev;           /* Board revision number from SPROM. */
 591 +       u16 board_rev;          /* Board revision number from SPROM. */
 592 +       u16 board_num;          /* Board number from SPROM. */
 593 +       u16 board_type;         /* Board type from SPROM. */
 594         u8 country_code;        /* Country Code */
 595 -       u16 leddc_on_time;      /* LED Powersave Duty Cycle On Count */
 596 -       u16 leddc_off_time;     /* LED Powersave Duty Cycle Off Count */
 597 +       char alpha2[2];         /* Country Code as two chars like EU or US */
 598 +       u8 leddc_on_time;       /* LED Powersave Duty Cycle On Count */
 599 +       u8 leddc_off_time;      /* LED Powersave Duty Cycle Off Count */
 600         u8 ant_available_a;     /* 2GHz antenna available bits (up to 4) */
 601         u8 ant_available_bg;    /* 5GHz antenna available bits (up to 4) */
 602         u16 pa0b0;
 603 @@ -47,10 +56,10 @@ struct ssb_sprom {
 604         u8 gpio1;               /* GPIO pin 1 */
 605         u8 gpio2;               /* GPIO pin 2 */
 606         u8 gpio3;               /* GPIO pin 3 */
 607 -       u16 maxpwr_bg;          /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
 608 -       u16 maxpwr_al;          /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
 609 -       u16 maxpwr_a;           /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
 610 -       u16 maxpwr_ah;          /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
 611 +       u8 maxpwr_bg;           /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
 612 +       u8 maxpwr_al;           /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
 613 +       u8 maxpwr_a;            /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
 614 +       u8 maxpwr_ah;           /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
 615         u8 itssi_a;             /* Idle TSSI Target for A-PHY */
 616         u8 itssi_bg;            /* Idle TSSI Target for B/G-PHY */
 617         u8 tri2g;               /* 2.4GHz TX isolation */
 618 @@ -61,8 +70,8 @@ struct ssb_sprom {
 619         u8 txpid5gl[4];         /* 4.9 - 5.1GHz TX power index */
 620         u8 txpid5g[4];          /* 5.1 - 5.5GHz TX power index */
 621         u8 txpid5gh[4];         /* 5.5 - ...GHz TX power index */
 622 -       u8 rxpo2g;              /* 2GHz RX power offset */
 623 -       u8 rxpo5g;              /* 5GHz RX power offset */
 624 +       s8 rxpo2g;              /* 2GHz RX power offset */
 625 +       s8 rxpo5g;              /* 5GHz RX power offset */
 626         u8 rssisav2g;           /* 2GHz RSSI params */
 627         u8 rssismc2g;
 628         u8 rssismf2g;
 629 @@ -82,26 +91,103 @@ struct ssb_sprom {
 630         u16 boardflags2_hi;     /* Board flags (bits 48-63) */
 631         /* TODO store board flags in a single u64 */
 632
 633 +       struct ssb_sprom_core_pwr_info core_pwr_info[4];
 634 +
 635         /* Antenna gain values for up to 4 antennas
 636          * on each band. Values in dBm/4 (Q5.2). Negative gain means the
 637          * loss in the connectors is bigger than the gain. */
 638         struct {
 639 -               struct {
 640 -                       s8 a0, a1, a2, a3;
 641 -               } ghz24;        /* 2.4GHz band */
 642 -               struct {
 643 -                       s8 a0, a1, a2, a3;
 644 -               } ghz5;         /* 5GHz band */
 645 +               s8 a0, a1, a2, a3;
 646         } antenna_gain;
 647
 648 -       /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
 649 +       struct {
 650 +               struct {
 651 +                       u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
 652 +               } ghz2;
 653 +               struct {
 654 +                       u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
 655 +               } ghz5;
 656 +       } fem;
 657 +
 658 +       u16 mcs2gpo[8];
 659 +       u16 mcs5gpo[8];
 660 +       u16 mcs5glpo[8];
 661 +       u16 mcs5ghpo[8];
 662 +       u8 opo;
 663 +
 664 +       u8 rxgainerr2ga[3];
 665 +       u8 rxgainerr5gla[3];
 666 +       u8 rxgainerr5gma[3];
 667 +       u8 rxgainerr5gha[3];
 668 +       u8 rxgainerr5gua[3];
 669 +
 670 +       u8 noiselvl2ga[3];
 671 +       u8 noiselvl5gla[3];
 672 +       u8 noiselvl5gma[3];
 673 +       u8 noiselvl5gha[3];
 674 +       u8 noiselvl5gua[3];
 675 +
 676 +       u8 regrev;
 677 +       u8 txchain;
 678 +       u8 rxchain;
 679 +       u8 antswitch;
 680 +       u16 cddpo;
 681 +       u16 stbcpo;
 682 +       u16 bw40po;
 683 +       u16 bwduppo;
 684 +
 685 +       u8 tempthresh;
 686 +       u8 tempoffset;
 687 +       u16 rawtempsense;
 688 +       u8 measpower;
 689 +       u8 tempsense_slope;
 690 +       u8 tempcorrx;
 691 +       u8 tempsense_option;
 692 +       u8 freqoffset_corr;
 693 +       u8 iqcal_swp_dis;
 694 +       u8 hw_iqcal_en;
 695 +       u8 elna2g;
 696 +       u8 elna5g;
 697 +       u8 phycal_tempdelta;
 698 +       u8 temps_period;
 699 +       u8 temps_hysteresis;
 700 +       u8 measpower1;
 701 +       u8 measpower2;
 702 +       u8 pcieingress_war;
 703 +
 704 +       /* power per rate from sromrev 9 */
 705 +       u16 cckbw202gpo;
 706 +       u16 cckbw20ul2gpo;
 707 +       u32 legofdmbw202gpo;
 708 +       u32 legofdmbw20ul2gpo;
 709 +       u32 legofdmbw205glpo;
 710 +       u32 legofdmbw20ul5glpo;
 711 +       u32 legofdmbw205gmpo;
 712 +       u32 legofdmbw20ul5gmpo;
 713 +       u32 legofdmbw205ghpo;
 714 +       u32 legofdmbw20ul5ghpo;
 715 +       u32 mcsbw202gpo;
 716 +       u32 mcsbw20ul2gpo;
 717 +       u32 mcsbw402gpo;
 718 +       u32 mcsbw205glpo;
 719 +       u32 mcsbw20ul5glpo;
 720 +       u32 mcsbw405glpo;
 721 +       u32 mcsbw205gmpo;
 722 +       u32 mcsbw20ul5gmpo;
 723 +       u32 mcsbw405gmpo;
 724 +       u32 mcsbw205ghpo;
 725 +       u32 mcsbw20ul5ghpo;
 726 +       u32 mcsbw405ghpo;
 727 +       u16 mcs32po;
 728 +       u16 legofdm40duppo;
 729 +       u8 sar2g;
 730 +       u8 sar5g;
 731  };
 732
 733  /* Information about the PCB the circuitry is soldered on. */
 734  struct ssb_boardinfo {
 735         u16 vendor;
 736         u16 type;
 737 -       u8  rev;
 738  };
 739
 740
 741 @@ -231,10 +317,9 @@ struct ssb_driver {
 742  #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
 743
 744  extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
 745 -static inline int ssb_driver_register(struct ssb_driver *drv)
 746 -{
 747 -       return __ssb_driver_register(drv, THIS_MODULE);
 748 -}
 749 +#define ssb_driver_register(drv) \
 750 +       __ssb_driver_register(drv, THIS_MODULE)
 751 +
 752  extern void ssb_driver_unregister(struct ssb_driver *drv);
 753
 754
 755 --- a/include/linux/ssb/ssb_driver_gige.h
 756 +++ b/include/linux/ssb/ssb_driver_gige.h
 757 @@ -2,6 +2,7 @@
 758  #define LINUX_SSB_DRIVER_GIGE_H_
 759
 760  #include <linux/ssb/ssb.h>
 761 +#include <linux/bug.h>
 762  #include <linux/pci.h>
 763  #include <linux/spinlock.h>
 764
 765 --- a/include/linux/ssb/ssb_regs.h
 766 +++ b/include/linux/ssb/ssb_regs.h
 767 @@ -228,6 +228,7 @@
 768  #define  SSB_SPROM1_AGAIN_BG_SHIFT     0
 769  #define  SSB_SPROM1_AGAIN_A            0xFF00  /* A-PHY */
 770  #define  SSB_SPROM1_AGAIN_A_SHIFT      8
 771 +#define SSB_SPROM1_CCODE               0x0076
 772
 773  /* SPROM Revision 2 (inherits from rev 1) */
 774  #define SSB_SPROM2_BFLHI               0x0038  /* Boardflags (high 16 bits) */
 775 @@ -267,6 +268,7 @@
 776  #define  SSB_SPROM3_OFDMGPO            0x107A  /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
 777
 778  /* SPROM Revision 4 */
 779 +#define SSB_SPROM4_BOARDREV            0x0042  /* Board revision */
 780  #define SSB_SPROM4_BFLLO               0x0044  /* Boardflags (low 16 bits) */
 781  #define SSB_SPROM4_BFLHI               0x0046  /* Board Flags Hi */
 782  #define SSB_SPROM4_BFL2LO              0x0048  /* Board flags 2 (low 16 bits) */
 783 @@ -389,6 +391,11 @@
 784  #define  SSB_SPROM8_GPIOB_P2           0x00FF  /* Pin 2 */
 785  #define  SSB_SPROM8_GPIOB_P3           0xFF00  /* Pin 3 */
 786  #define  SSB_SPROM8_GPIOB_P3_SHIFT     8
 787 +#define SSB_SPROM8_LEDDC               0x009A
 788 +#define  SSB_SPROM8_LEDDC_ON           0xFF00  /* oncount */
 789 +#define  SSB_SPROM8_LEDDC_ON_SHIFT     8
 790 +#define  SSB_SPROM8_LEDDC_OFF          0x00FF  /* offcount */
 791 +#define  SSB_SPROM8_LEDDC_OFF_SHIFT    0
 792  #define SSB_SPROM8_ANTAVAIL            0x009C  /* Antenna available bitfields*/
 793  #define  SSB_SPROM8_ANTAVAIL_A         0xFF00  /* A-PHY bitfield */
 794  #define  SSB_SPROM8_ANTAVAIL_A_SHIFT   8
 795 @@ -404,6 +411,13 @@
 796  #define  SSB_SPROM8_AGAIN2_SHIFT       0
 797  #define  SSB_SPROM8_AGAIN3             0xFF00  /* Antenna 3 */
 798  #define  SSB_SPROM8_AGAIN3_SHIFT       8
 799 +#define SSB_SPROM8_TXRXC               0x00A2
 800 +#define  SSB_SPROM8_TXRXC_TXCHAIN      0x000f
 801 +#define  SSB_SPROM8_TXRXC_TXCHAIN_SHIFT        0
 802 +#define  SSB_SPROM8_TXRXC_RXCHAIN      0x00f0
 803 +#define  SSB_SPROM8_TXRXC_RXCHAIN_SHIFT        4
 804 +#define  SSB_SPROM8_TXRXC_SWITCH       0xff00
 805 +#define  SSB_SPROM8_TXRXC_SWITCH_SHIFT 8
 806  #define SSB_SPROM8_RSSIPARM2G          0x00A4  /* RSSI params for 2GHz */
 807  #define  SSB_SPROM8_RSSISMF2G          0x000F
 808  #define  SSB_SPROM8_RSSISMC2G          0x00F0
 809 @@ -430,8 +444,87 @@
 810  #define  SSB_SPROM8_TRI5GH_SHIFT       8
 811  #define SSB_SPROM8_RXPO                        0x00AC  /* RX power offsets */
 812  #define  SSB_SPROM8_RXPO2G             0x00FF  /* 2GHz RX power offset */
 813 +#define  SSB_SPROM8_RXPO2G_SHIFT       0
 814  #define  SSB_SPROM8_RXPO5G             0xFF00  /* 5GHz RX power offset */
 815  #define  SSB_SPROM8_RXPO5G_SHIFT       8
 816 +#define SSB_SPROM8_FEM2G               0x00AE
 817 +#define SSB_SPROM8_FEM5G               0x00B0
 818 +#define  SSB_SROM8_FEM_TSSIPOS         0x0001
 819 +#define  SSB_SROM8_FEM_TSSIPOS_SHIFT   0
 820 +#define  SSB_SROM8_FEM_EXTPA_GAIN      0x0006
 821 +#define  SSB_SROM8_FEM_EXTPA_GAIN_SHIFT        1
 822 +#define  SSB_SROM8_FEM_PDET_RANGE      0x00F8
 823 +#define  SSB_SROM8_FEM_PDET_RANGE_SHIFT        3
 824 +#define  SSB_SROM8_FEM_TR_ISO          0x0700
 825 +#define  SSB_SROM8_FEM_TR_ISO_SHIFT    8
 826 +#define  SSB_SROM8_FEM_ANTSWLUT                0xF800
 827 +#define  SSB_SROM8_FEM_ANTSWLUT_SHIFT  11
 828 +#define SSB_SPROM8_THERMAL             0x00B2
 829 +#define  SSB_SPROM8_THERMAL_OFFSET     0x00ff
 830 +#define  SSB_SPROM8_THERMAL_OFFSET_SHIFT       0
 831 +#define  SSB_SPROM8_THERMAL_TRESH      0xff00
 832 +#define  SSB_SPROM8_THERMAL_TRESH_SHIFT        8
 833 +/* Temp sense related entries */
 834 +#define SSB_SPROM8_RAWTS               0x00B4
 835 +#define  SSB_SPROM8_RAWTS_RAWTEMP      0x01ff
 836 +#define  SSB_SPROM8_RAWTS_RAWTEMP_SHIFT        0
 837 +#define  SSB_SPROM8_RAWTS_MEASPOWER    0xfe00
 838 +#define  SSB_SPROM8_RAWTS_MEASPOWER_SHIFT      9
 839 +#define SSB_SPROM8_OPT_CORRX           0x00B6
 840 +#define  SSB_SPROM8_OPT_CORRX_TEMP_SLOPE       0x00ff
 841 +#define  SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT 0
 842 +#define  SSB_SPROM8_OPT_CORRX_TEMPCORRX        0xfc00
 843 +#define  SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT  10
 844 +#define  SSB_SPROM8_OPT_CORRX_TEMP_OPTION      0x0300
 845 +#define  SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT        8
 846 +/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
 847 +#define SSB_SPROM8_HWIQ_IQSWP          0x00B8
 848 +#define  SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR       0x000f
 849 +#define  SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT 0
 850 +#define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP       0x0010
 851 +#define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
 852 +#define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL        0x0020
 853 +#define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT  5
 854 +#define SSB_SPROM8_TEMPDELTA           0x00BA
 855 +#define  SSB_SPROM8_TEMPDELTA_PHYCAL   0x00ff
 856 +#define  SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT     0
 857 +#define  SSB_SPROM8_TEMPDELTA_PERIOD   0x0f00
 858 +#define  SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT     8
 859 +#define  SSB_SPROM8_TEMPDELTA_HYSTERESIS       0xf000
 860 +#define  SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT 12
 861 +
 862 +/* There are 4 blocks with power info sharing the same layout */
 863 +#define SSB_SROM8_PWR_INFO_CORE0       0x00C0
 864 +#define SSB_SROM8_PWR_INFO_CORE1       0x00E0
 865 +#define SSB_SROM8_PWR_INFO_CORE2       0x0100
 866 +#define SSB_SROM8_PWR_INFO_CORE3       0x0120
 867 +
 868 +#define SSB_SROM8_2G_MAXP_ITSSI                0x00
 869 +#define  SSB_SPROM8_2G_MAXP            0x00FF
 870 +#define  SSB_SPROM8_2G_ITSSI           0xFF00
 871 +#define  SSB_SPROM8_2G_ITSSI_SHIFT     8
 872 +#define SSB_SROM8_2G_PA_0              0x02    /* 2GHz power amp settings */
 873 +#define SSB_SROM8_2G_PA_1              0x04
 874 +#define SSB_SROM8_2G_PA_2              0x06
 875 +#define SSB_SROM8_5G_MAXP_ITSSI                0x08    /* 5GHz ITSSI and 5.3GHz Max Power */
 876 +#define  SSB_SPROM8_5G_MAXP            0x00FF
 877 +#define  SSB_SPROM8_5G_ITSSI           0xFF00
 878 +#define  SSB_SPROM8_5G_ITSSI_SHIFT     8
 879 +#define SSB_SPROM8_5GHL_MAXP           0x0A    /* 5.2GHz and 5.8GHz Max Power */
 880 +#define  SSB_SPROM8_5GH_MAXP           0x00FF
 881 +#define  SSB_SPROM8_5GL_MAXP           0xFF00
 882 +#define  SSB_SPROM8_5GL_MAXP_SHIFT     8
 883 +#define SSB_SROM8_5G_PA_0              0x0C    /* 5.3GHz power amp settings */
 884 +#define SSB_SROM8_5G_PA_1              0x0E
 885 +#define SSB_SROM8_5G_PA_2              0x10
 886 +#define SSB_SROM8_5GL_PA_0             0x12    /* 5.2GHz power amp settings */
 887 +#define SSB_SROM8_5GL_PA_1             0x14
 888 +#define SSB_SROM8_5GL_PA_2             0x16
 889 +#define SSB_SROM8_5GH_PA_0             0x18    /* 5.8GHz power amp settings */
 890 +#define SSB_SROM8_5GH_PA_1             0x1A
 891 +#define SSB_SROM8_5GH_PA_2             0x1C
 892 +
 893 +/* TODO: Make it deprecated */
 894  #define SSB_SPROM8_MAXP_BG             0x00C0  /* Max Power 2GHz in path 1 */
 895  #define  SSB_SPROM8_MAXP_BG_MASK       0x00FF  /* Mask for Max Power 2GHz */
 896  #define  SSB_SPROM8_ITSSI_BG           0xFF00  /* Mask for path 1 itssi_bg */
 897 @@ -456,12 +549,63 @@
 898  #define SSB_SPROM8_PA1HIB0             0x00D8  /* 5.8GHz power amp settings */
 899  #define SSB_SPROM8_PA1HIB1             0x00DA
 900  #define SSB_SPROM8_PA1HIB2             0x00DC
 901 +
 902  #define SSB_SPROM8_CCK2GPO             0x0140  /* CCK power offset */
 903  #define SSB_SPROM8_OFDM2GPO            0x0142  /* 2.4GHz OFDM power offset */
 904  #define SSB_SPROM8_OFDM5GPO            0x0146  /* 5.3GHz OFDM power offset */
 905  #define SSB_SPROM8_OFDM5GLPO           0x014A  /* 5.2GHz OFDM power offset */
 906  #define SSB_SPROM8_OFDM5GHPO           0x014E  /* 5.8GHz OFDM power offset */
 907
 908 +#define SSB_SPROM8_2G_MCSPO            0x0152
 909 +#define SSB_SPROM8_5G_MCSPO            0x0162
 910 +#define SSB_SPROM8_5GL_MCSPO           0x0172
 911 +#define SSB_SPROM8_5GH_MCSPO           0x0182
 912 +
 913 +#define SSB_SPROM8_CDDPO               0x0192
 914 +#define SSB_SPROM8_STBCPO              0x0194
 915 +#define SSB_SPROM8_BW40PO              0x0196
 916 +#define SSB_SPROM8_BWDUPPO             0x0198
 917 +
 918 +/* Values for boardflags_lo read from SPROM */
 919 +#define SSB_BFL_BTCOEXIST              0x0001  /* implements Bluetooth coexistance */
 920 +#define SSB_BFL_PACTRL                 0x0002  /* GPIO 9 controlling the PA */
 921 +#define SSB_BFL_AIRLINEMODE            0x0004  /* implements GPIO 13 radio disable indication */
 922 +#define SSB_BFL_RSSI                   0x0008  /* software calculates nrssi slope. */
 923 +#define SSB_BFL_ENETSPI                        0x0010  /* has ephy roboswitch spi */
 924 +#define SSB_BFL_XTAL_NOSLOW            0x0020  /* no slow clock available */
 925 +#define SSB_BFL_CCKHIPWR               0x0040  /* can do high power CCK transmission */
 926 +#define SSB_BFL_ENETADM                        0x0080  /* has ADMtek switch */
 927 +#define SSB_BFL_ENETVLAN               0x0100  /* can do vlan */
 928 +#define SSB_BFL_AFTERBURNER            0x0200  /* supports Afterburner mode */
 929 +#define SSB_BFL_NOPCI                  0x0400  /* board leaves PCI floating */
 930 +#define SSB_BFL_FEM                    0x0800  /* supports the Front End Module */
 931 +#define SSB_BFL_EXTLNA                 0x1000  /* has an external LNA */
 932 +#define SSB_BFL_HGPA                   0x2000  /* had high gain PA */
 933 +#define SSB_BFL_BTCMOD                 0x4000  /* BFL_BTCOEXIST is given in alternate GPIOs */
 934 +#define SSB_BFL_ALTIQ                  0x8000  /* alternate I/Q settings */
 935 +
 936 +/* Values for boardflags_hi read from SPROM */
 937 +#define SSB_BFH_NOPA                   0x0001  /* has no PA */
 938 +#define SSB_BFH_RSSIINV                        0x0002  /* RSSI uses positive slope (not TSSI) */
 939 +#define SSB_BFH_PAREF                  0x0004  /* uses the PARef LDO */
 940 +#define SSB_BFH_3TSWITCH               0x0008  /* uses a triple throw switch shared with bluetooth */
 941 +#define SSB_BFH_PHASESHIFT             0x0010  /* can support phase shifter */
 942 +#define SSB_BFH_BUCKBOOST              0x0020  /* has buck/booster */
 943 +#define SSB_BFH_FEM_BT                 0x0040  /* has FEM and switch to share antenna with bluetooth */
 944 +
 945 +/* Values for boardflags2_lo read from SPROM */
 946 +#define SSB_BFL2_RXBB_INT_REG_DIS      0x0001  /* external RX BB regulator present */
 947 +#define SSB_BFL2_APLL_WAR              0x0002  /* alternative A-band PLL settings implemented */
 948 +#define SSB_BFL2_TXPWRCTRL_EN          0x0004  /* permits enabling TX Power Control */
 949 +#define SSB_BFL2_2X4_DIV               0x0008  /* 2x4 diversity switch */
 950 +#define SSB_BFL2_5G_PWRGAIN            0x0010  /* supports 5G band power gain */
 951 +#define SSB_BFL2_PCIEWAR_OVR           0x0020  /* overrides ASPM and Clkreq settings */
 952 +#define SSB_BFL2_CAESERS_BRD           0x0040  /* is Caesers board (unused) */
 953 +#define SSB_BFL2_BTC3WIRE              0x0080  /* used 3-wire bluetooth coexist */
 954 +#define SSB_BFL2_SKWRKFEM_BRD          0x0100  /* 4321mcm93 uses Skyworks FEM */
 955 +#define SSB_BFL2_SPUR_WAR              0x0200  /* has a workaround for clock-harmonic spurs */
 956 +#define SSB_BFL2_GPLL_WAR              0x0400  /* altenative G-band PLL settings implemented */
 957 +
 958  /* Values for SSB_SPROM1_BINF_CCODE */
 959  enum {
 960         SSB_SPROM1CCODE_WORLD = 0,