target/linux/generic/files/drivers/net/phy/rtl8367b.c

   1 /*
   2  * Platform driver for the Realtek RTL8367R-VB ethernet switches
   3  *
   4  * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/delay.h>
  16 #include <linux/skbuff.h>
  17 #include <linux/rtl8367.h>
  18
  19 #include "rtl8366_smi.h"
  20
  21 #define RTL8367B_RESET_DELAY    1000    /* msecs*/
  22
  23 #define RTL8367B_PHY_ADDR_MAX   8
  24 #define RTL8367B_PHY_REG_MAX    31
  25
  26 #define RTL8367B_VID_MASK       0x3fff
  27 #define RTL8367B_FID_MASK       0xf
  28 #define RTL8367B_UNTAG_MASK     0xff
  29 #define RTL8367B_MEMBER_MASK    0xff
  30
  31 #define RTL8367B_PORT_MISC_CFG_REG(_p)          (0x000e + 0x20 * (_p))
  32 #define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT      4
  33 #define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK       0x3
  34 #define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL   0
  35 #define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_KEEP       1
  36 #define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_PRI        2
  37 #define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_REAL       3
  38
  39 #define RTL8367B_BYPASS_LINE_RATE_REG           0x03f7
  40
  41 #define RTL8367B_TA_CTRL_REG                    0x0500 /*GOOD*/
  42 #define   RTL8367B_TA_CTRL_SPA_SHIFT            8
  43 #define   RTL8367B_TA_CTRL_SPA_MASK             0x7
  44 #define   RTL8367B_TA_CTRL_METHOD               BIT(4)/*GOOD*/
  45 #define   RTL8367B_TA_CTRL_CMD_SHIFT            3
  46 #define   RTL8367B_TA_CTRL_CMD_READ             0
  47 #define   RTL8367B_TA_CTRL_CMD_WRITE            1
  48 #define   RTL8367B_TA_CTRL_TABLE_SHIFT          0 /*GOOD*/
  49 #define   RTL8367B_TA_CTRL_TABLE_ACLRULE        1
  50 #define   RTL8367B_TA_CTRL_TABLE_ACLACT         2
  51 #define   RTL8367B_TA_CTRL_TABLE_CVLAN          3
  52 #define   RTL8367B_TA_CTRL_TABLE_L2             4
  53 #define   RTL8367B_TA_CTRL_CVLAN_READ \
  54                 ((RTL8367B_TA_CTRL_CMD_READ << RTL8367B_TA_CTRL_CMD_SHIFT) | \
  55                  RTL8367B_TA_CTRL_TABLE_CVLAN)
  56 #define   RTL8367B_TA_CTRL_CVLAN_WRITE \
  57                 ((RTL8367B_TA_CTRL_CMD_WRITE << RTL8367B_TA_CTRL_CMD_SHIFT) | \
  58                  RTL8367B_TA_CTRL_TABLE_CVLAN)
  59
  60 #define RTL8367B_TA_ADDR_REG                    0x0501/*GOOD*/
  61 #define   RTL8367B_TA_ADDR_MASK                 0x3fff/*GOOD*/
  62
  63 #define RTL8367B_TA_LUT_REG                     0x0502/*GOOD*/
  64
  65 #define RTL8367B_TA_WRDATA_REG(_x)              (0x0510 + (_x))/*GOOD*/
  66 #define   RTL8367B_TA_VLAN_NUM_WORDS            2
  67 #define   RTL8367B_TA_VLAN_VID_MASK             RTL8367B_VID_MASK
  68 #define   RTL8367B_TA_VLAN0_MEMBER_SHIFT        0
  69 #define   RTL8367B_TA_VLAN0_MEMBER_MASK         RTL8367B_MEMBER_MASK
  70 #define   RTL8367B_TA_VLAN0_UNTAG_SHIFT         8
  71 #define   RTL8367B_TA_VLAN0_UNTAG_MASK          RTL8367B_MEMBER_MASK
  72 #define   RTL8367B_TA_VLAN1_FID_SHIFT           0
  73 #define   RTL8367B_TA_VLAN1_FID_MASK            RTL8367B_FID_MASK
  74
  75 #define RTL8367B_TA_RDDATA_REG(_x)              (0x0520 + (_x))/*GOOD*/
  76
  77 #define RTL8367B_VLAN_PVID_CTRL_REG(_p)         (0x0700 + (_p) / 2) /*GOOD*/
  78 #define RTL8367B_VLAN_PVID_CTRL_MASK            0x1f /*GOOD*/
  79 #define RTL8367B_VLAN_PVID_CTRL_SHIFT(_p)       (8 * ((_p) % 2)) /*GOOD*/
  80
  81 #define RTL8367B_VLAN_MC_BASE(_x)               (0x0728 + (_x) * 4) /*GOOD*/
  82 #define   RTL8367B_VLAN_MC_NUM_WORDS            4 /*GOOD*/
  83 #define   RTL8367B_VLAN_MC0_MEMBER_SHIFT        0/*GOOD*/
  84 #define   RTL8367B_VLAN_MC0_MEMBER_MASK         RTL8367B_MEMBER_MASK/*GOOD*/
  85 #define   RTL8367B_VLAN_MC1_FID_SHIFT           0/*GOOD*/
  86 #define   RTL8367B_VLAN_MC1_FID_MASK            RTL8367B_FID_MASK/*GOOD*/
  87 #define   RTL8367B_VLAN_MC3_EVID_SHIFT          0/*GOOD*/
  88 #define   RTL8367B_VLAN_MC3_EVID_MASK           RTL8367B_VID_MASK/*GOOD*/
  89
  90 #define RTL8367B_VLAN_CTRL_REG                  0x07a8 /*GOOD*/
  91 #define   RTL8367B_VLAN_CTRL_ENABLE             BIT(0)
  92
  93 #define RTL8367B_VLAN_INGRESS_REG               0x07a9 /*GOOD*/
  94
  95 #define RTL8367B_PORT_ISOLATION_REG(_p)         (0x08a2 + (_p)) /*GOOD*/
  96
  97 #define RTL8367B_MIB_COUNTER_REG(_x)            (0x1000 + (_x)) /*GOOD*/
  98 #define RTL8367B_MIB_COUNTER_PORT_OFFSET        0x007c /*GOOD*/
  99
 100 #define RTL8367B_MIB_ADDRESS_REG                0x1004 /*GOOD*/
 101
 102 #define RTL8367B_MIB_CTRL0_REG(_x)              (0x1005 + (_x)) /*GOOD*/
 103 #define   RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK  BIT(11) /*GOOD*/
 104 #define   RTL8367B_MIB_CTRL0_QM_RESET_MASK      BIT(10) /*GOOD*/
 105 #define   RTL8367B_MIB_CTRL0_PORT_RESET_MASK(_p) BIT(2 + (_p)) /*GOOD*/
 106 #define   RTL8367B_MIB_CTRL0_RESET_MASK         BIT(1) /*GOOD*/
 107 #define   RTL8367B_MIB_CTRL0_BUSY_MASK          BIT(0) /*GOOD*/
 108
 109 #define RTL8367B_SWC0_REG                       0x1200/*GOOD*/
 110 #define   RTL8367B_SWC0_MAX_LENGTH_SHIFT        13/*GOOD*/
 111 #define   RTL8367B_SWC0_MAX_LENGTH(_x)          ((_x) << 13) /*GOOD*/
 112 #define   RTL8367B_SWC0_MAX_LENGTH_MASK         RTL8367B_SWC0_MAX_LENGTH(0x3)
 113 #define   RTL8367B_SWC0_MAX_LENGTH_1522         RTL8367B_SWC0_MAX_LENGTH(0)
 114 #define   RTL8367B_SWC0_MAX_LENGTH_1536         RTL8367B_SWC0_MAX_LENGTH(1)
 115 #define   RTL8367B_SWC0_MAX_LENGTH_1552         RTL8367B_SWC0_MAX_LENGTH(2)
 116 #define   RTL8367B_SWC0_MAX_LENGTH_16000        RTL8367B_SWC0_MAX_LENGTH(3)
 117
 118 #define RTL8367B_CHIP_NUMBER_REG                0x1300/*GOOD*/
 119
 120 #define RTL8367B_CHIP_VER_REG                   0x1301/*GOOD*/
 121 #define   RTL8367B_CHIP_VER_RLVID_SHIFT         12/*GOOD*/
 122 #define   RTL8367B_CHIP_VER_RLVID_MASK          0xf/*GOOD*/
 123 #define   RTL8367B_CHIP_VER_MCID_SHIFT          8/*GOOD*/
 124 #define   RTL8367B_CHIP_VER_MCID_MASK           0xf/*GOOD*/
 125 #define   RTL8367B_CHIP_VER_BOID_SHIFT          4/*GOOD*/
 126 #define   RTL8367B_CHIP_VER_BOID_MASK           0xf/*GOOD*/
 127 #define   RTL8367B_CHIP_VER_AFE_SHIFT           0/*GOOD*/
 128 #define   RTL8367B_CHIP_VER_AFE_MASK            0x1/*GOOD*/
 129
 130 #define RTL8367B_CHIP_MODE_REG                  0x1302
 131 #define   RTL8367B_CHIP_MODE_MASK               0x7
 132
 133 #define RTL8367B_CHIP_DEBUG0_REG                0x1303
 134 #define   RTL8367B_CHIP_DEBUG0_DUMMY0(_x)       BIT(8 + (_x))
 135
 136 #define RTL8367B_CHIP_DEBUG1_REG                0x1304
 137
 138 #define RTL8367B_DIS_REG                        0x1305
 139 #define   RTL8367B_DIS_SKIP_MII_RXER(_x)        BIT(12 + (_x))
 140 #define   RTL8367B_DIS_RGMII_SHIFT(_x)          (4 * (_x))
 141 #define   RTL8367B_DIS_RGMII_MASK               0x7
 142
 143 #define RTL8367B_EXT_RGMXF_REG(_x)              (0x1306 + (_x))
 144 #define   RTL8367B_EXT_RGMXF_DUMMY0_SHIFT       5
 145 #define   RTL8367B_EXT_RGMXF_DUMMY0_MASK        0x7ff
 146 #define   RTL8367B_EXT_RGMXF_TXDELAY_SHIFT      3
 147 #define   RTL8367B_EXT_RGMXF_TXDELAY_MASK       1
 148 #define   RTL8367B_EXT_RGMXF_RXDELAY_MASK       0x7
 149
 150 #define RTL8367B_DI_FORCE_REG(_x)               (0x1310 + (_x))
 151 #define   RTL8367B_DI_FORCE_MODE                BIT(12)
 152 #define   RTL8367B_DI_FORCE_NWAY                BIT(7)
 153 #define   RTL8367B_DI_FORCE_TXPAUSE             BIT(6)
 154 #define   RTL8367B_DI_FORCE_RXPAUSE             BIT(5)
 155 #define   RTL8367B_DI_FORCE_LINK                BIT(4)
 156 #define   RTL8367B_DI_FORCE_DUPLEX              BIT(2)
 157 #define   RTL8367B_DI_FORCE_SPEED_MASK          3
 158 #define   RTL8367B_DI_FORCE_SPEED_10            0
 159 #define   RTL8367B_DI_FORCE_SPEED_100           1
 160 #define   RTL8367B_DI_FORCE_SPEED_1000          2
 161
 162 #define RTL8367B_MAC_FORCE_REG(_x)              (0x1312 + (_x))
 163
 164 #define RTL8367B_CHIP_RESET_REG                 0x1322 /*GOOD*/
 165 #define   RTL8367B_CHIP_RESET_SW                BIT(1) /*GOOD*/
 166 #define   RTL8367B_CHIP_RESET_HW                BIT(0) /*GOOD*/
 167
 168 #define RTL8367B_PORT_STATUS_REG(_p)            (0x1352 + (_p)) /*GOOD*/
 169 #define   RTL8367B_PORT_STATUS_EN_1000_SPI      BIT(11) /*GOOD*/
 170 #define   RTL8367B_PORT_STATUS_EN_100_SPI       BIT(10)/*GOOD*/
 171 #define   RTL8367B_PORT_STATUS_NWAY_FAULT       BIT(9)/*GOOD*/
 172 #define   RTL8367B_PORT_STATUS_LINK_MASTER      BIT(8)/*GOOD*/
 173 #define   RTL8367B_PORT_STATUS_NWAY             BIT(7)/*GOOD*/
 174 #define   RTL8367B_PORT_STATUS_TXPAUSE          BIT(6)/*GOOD*/
 175 #define   RTL8367B_PORT_STATUS_RXPAUSE          BIT(5)/*GOOD*/
 176 #define   RTL8367B_PORT_STATUS_LINK             BIT(4)/*GOOD*/
 177 #define   RTL8367B_PORT_STATUS_DUPLEX           BIT(2)/*GOOD*/
 178 #define   RTL8367B_PORT_STATUS_SPEED_MASK       0x0003/*GOOD*/
 179 #define   RTL8367B_PORT_STATUS_SPEED_10         0/*GOOD*/
 180 #define   RTL8367B_PORT_STATUS_SPEED_100        1/*GOOD*/
 181 #define   RTL8367B_PORT_STATUS_SPEED_1000       2/*GOOD*/
 182
 183 #define RTL8367B_RTL_MAGIC_ID_REG               0x13c2
 184 #define   RTL8367B_RTL_MAGIC_ID_VAL             0x0249
 185
 186 #define RTL8367B_IA_CTRL_REG                    0x1f00
 187 #define   RTL8367B_IA_CTRL_RW(_x)               ((_x) << 1)
 188 #define   RTL8367B_IA_CTRL_RW_READ              RTL8367B_IA_CTRL_RW(0)
 189 #define   RTL8367B_IA_CTRL_RW_WRITE             RTL8367B_IA_CTRL_RW(1)
 190 #define   RTL8367B_IA_CTRL_CMD_MASK             BIT(0)
 191
 192 #define RTL8367B_IA_STATUS_REG                  0x1f01
 193 #define   RTL8367B_IA_STATUS_PHY_BUSY           BIT(2)
 194 #define   RTL8367B_IA_STATUS_SDS_BUSY           BIT(1)
 195 #define   RTL8367B_IA_STATUS_MDX_BUSY           BIT(0)
 196
 197 #define RTL8367B_IA_ADDRESS_REG                 0x1f02
 198 #define RTL8367B_IA_WRITE_DATA_REG              0x1f03
 199 #define RTL8367B_IA_READ_DATA_REG               0x1f04
 200
 201 #define RTL8367B_INTERNAL_PHY_REG(_a, _r)       (0x2000 + 32 * (_a) + (_r))
 202
 203 #define RTL8367B_NUM_MIB_COUNTERS       58
 204
 205 #define RTL8367B_CPU_PORT_NUM           5
 206 #define RTL8367B_NUM_PORTS              8
 207 #define RTL8367B_NUM_VLANS              32
 208 #define RTL8367B_NUM_VIDS               4096
 209 #define RTL8367B_PRIORITYMAX            7
 210 #define RTL8367B_FIDMAX                 7
 211
 212 #define RTL8367B_PORT_0                 BIT(0)
 213 #define RTL8367B_PORT_1                 BIT(1)
 214 #define RTL8367B_PORT_2                 BIT(2)
 215 #define RTL8367B_PORT_3                 BIT(3)
 216 #define RTL8367B_PORT_4                 BIT(4)
 217 #define RTL8367B_PORT_E0                BIT(5)  /* External port 0 */
 218 #define RTL8367B_PORT_E1                BIT(6)  /* External port 1 */
 219 #define RTL8367B_PORT_E2                BIT(7)  /* External port 2 */
 220
 221 #define RTL8367B_PORTS_ALL                                      \
 222         (RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 |  \
 223          RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E0 | \
 224          RTL8367B_PORT_E1 | RTL8367B_PORT_E2)
 225
 226 #define RTL8367B_PORTS_ALL_BUT_CPU                              \
 227         (RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 |  \
 228          RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E1 | \
 229          RTL8367B_PORT_E2)
 230
 231 struct rtl8367b_initval {
 232         u16 reg;
 233         u16 val;
 234 };
 235
 236 static struct rtl8366_mib_counter
 237 rtl8367b_mib_counters[RTL8367B_NUM_MIB_COUNTERS] = {
 238         {0,   0, 4, "ifInOctets"                        },
 239         {0,   4, 2, "dot3StatsFCSErrors"                },
 240         {0,   6, 2, "dot3StatsSymbolErrors"             },
 241         {0,   8, 2, "dot3InPauseFrames"                 },
 242         {0,  10, 2, "dot3ControlInUnknownOpcodes"       },
 243         {0,  12, 2, "etherStatsFragments"               },
 244         {0,  14, 2, "etherStatsJabbers"                 },
 245         {0,  16, 2, "ifInUcastPkts"                     },
 246         {0,  18, 2, "etherStatsDropEvents"              },
 247         {0,  20, 2, "ifInMulticastPkts"                 },
 248         {0,  22, 2, "ifInBroadcastPkts"                 },
 249         {0,  24, 2, "inMldChecksumError"                },
 250         {0,  26, 2, "inIgmpChecksumError"               },
 251         {0,  28, 2, "inMldSpecificQuery"                },
 252         {0,  30, 2, "inMldGeneralQuery"                 },
 253         {0,  32, 2, "inIgmpSpecificQuery"               },
 254         {0,  34, 2, "inIgmpGeneralQuery"                },
 255         {0,  36, 2, "inMldLeaves"                       },
 256         {0,  38, 2, "inIgmpLeaves"                      },
 257
 258         {0,  40, 4, "etherStatsOctets"                  },
 259         {0,  44, 2, "etherStatsUnderSizePkts"           },
 260         {0,  46, 2, "etherOversizeStats"                },
 261         {0,  48, 2, "etherStatsPkts64Octets"            },
 262         {0,  50, 2, "etherStatsPkts65to127Octets"       },
 263         {0,  52, 2, "etherStatsPkts128to255Octets"      },
 264         {0,  54, 2, "etherStatsPkts256to511Octets"      },
 265         {0,  56, 2, "etherStatsPkts512to1023Octets"     },
 266         {0,  58, 2, "etherStatsPkts1024to1518Octets"    },
 267
 268         {0,  60, 4, "ifOutOctets"                       },
 269         {0,  64, 2, "dot3StatsSingleCollisionFrames"    },
 270         {0,  66, 2, "dot3StatMultipleCollisionFrames"   },
 271         {0,  68, 2, "dot3sDeferredTransmissions"        },
 272         {0,  70, 2, "dot3StatsLateCollisions"           },
 273         {0,  72, 2, "etherStatsCollisions"              },
 274         {0,  74, 2, "dot3StatsExcessiveCollisions"      },
 275         {0,  76, 2, "dot3OutPauseFrames"                },
 276         {0,  78, 2, "ifOutDiscards"                     },
 277         {0,  80, 2, "dot1dTpPortInDiscards"             },
 278         {0,  82, 2, "ifOutUcastPkts"                    },
 279         {0,  84, 2, "ifOutMulticastPkts"                },
 280         {0,  86, 2, "ifOutBroadcastPkts"                },
 281         {0,  88, 2, "outOampduPkts"                     },
 282         {0,  90, 2, "inOampduPkts"                      },
 283         {0,  92, 2, "inIgmpJoinsSuccess"                },
 284         {0,  94, 2, "inIgmpJoinsFail"                   },
 285         {0,  96, 2, "inMldJoinsSuccess"                 },
 286         {0,  98, 2, "inMldJoinsFail"                    },
 287         {0, 100, 2, "inReportSuppressionDrop"           },
 288         {0, 102, 2, "inLeaveSuppressionDrop"            },
 289         {0, 104, 2, "outIgmpReports"                    },
 290         {0, 106, 2, "outIgmpLeaves"                     },
 291         {0, 108, 2, "outIgmpGeneralQuery"               },
 292         {0, 110, 2, "outIgmpSpecificQuery"              },
 293         {0, 112, 2, "outMldReports"                     },
 294         {0, 114, 2, "outMldLeaves"                      },
 295         {0, 116, 2, "outMldGeneralQuery"                },
 296         {0, 118, 2, "outMldSpecificQuery"               },
 297         {0, 120, 2, "inKnownMulticastPkts"              },
 298 };
 299
 300 #define REG_RD(_smi, _reg, _val)                                        \
 301         do {                                                            \
 302                 err = rtl8366_smi_read_reg(_smi, _reg, _val);           \
 303                 if (err)                                                \
 304                         return err;                                     \
 305         } while (0)
 306
 307 #define REG_WR(_smi, _reg, _val)                                        \
 308         do {                                                            \
 309                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 310                 if (err)                                                \
 311                         return err;                                     \
 312         } while (0)
 313
 314 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 315         do {                                                            \
 316                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 317                 if (err)                                                \
 318                         return err;                                     \
 319         } while (0)
 320
 321 static const struct rtl8367b_initval rtl8367r_vb_initvals_0[] = {
 322         {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x0301, 0x0026}, {0x1722, 0x0E14},
 323         {0x205F, 0x0002}, {0x2059, 0x1A00}, {0x205F, 0x0000}, {0x207F, 0x0002},
 324         {0x2077, 0x0000}, {0x2078, 0x0000}, {0x2079, 0x0000}, {0x207A, 0x0000},
 325         {0x207B, 0x0000}, {0x207F, 0x0000}, {0x205F, 0x0002}, {0x2053, 0x0000},
 326         {0x2054, 0x0000}, {0x2055, 0x0000}, {0x2056, 0x0000}, {0x2057, 0x0000},
 327         {0x205F, 0x0000}, {0x12A4, 0x110A}, {0x12A6, 0x150A}, {0x13F1, 0x0013},
 328         {0x13F4, 0x0010}, {0x13F5, 0x0000}, {0x0018, 0x0F00}, {0x0038, 0x0F00},
 329         {0x0058, 0x0F00}, {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x12B6, 0x0C02},
 330         {0x12B7, 0x030F}, {0x12B8, 0x11FF}, {0x12BC, 0x0004}, {0x1362, 0x0115},
 331         {0x1363, 0x0002}, {0x1363, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E},
 332         {0x221F, 0x0007}, {0x221E, 0x002D}, {0x2218, 0xF030}, {0x221F, 0x0007},
 333         {0x221E, 0x0023}, {0x2216, 0x0005}, {0x2215, 0x00B9}, {0x2219, 0x0044},
 334         {0x2215, 0x00BA}, {0x2219, 0x0020}, {0x2215, 0x00BB}, {0x2219, 0x00C1},
 335         {0x2215, 0x0148}, {0x2219, 0x0096}, {0x2215, 0x016E}, {0x2219, 0x0026},
 336         {0x2216, 0x0000}, {0x2216, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
 337         {0x221F, 0x0007}, {0x221E, 0x0020}, {0x2215, 0x0D00}, {0x221F, 0x0000},
 338         {0x221F, 0x0000}, {0x2217, 0x2160}, {0x221F, 0x0001}, {0x2210, 0xF25E},
 339         {0x221F, 0x0007}, {0x221E, 0x0042}, {0x2215, 0x0F00}, {0x2215, 0x0F00},
 340         {0x2216, 0x7408}, {0x2215, 0x0E00}, {0x2215, 0x0F00}, {0x2215, 0x0F01},
 341         {0x2216, 0x4000}, {0x2215, 0x0E01}, {0x2215, 0x0F01}, {0x2215, 0x0F02},
 342         {0x2216, 0x9400}, {0x2215, 0x0E02}, {0x2215, 0x0F02}, {0x2215, 0x0F03},
 343         {0x2216, 0x7408}, {0x2215, 0x0E03}, {0x2215, 0x0F03}, {0x2215, 0x0F04},
 344         {0x2216, 0x4008}, {0x2215, 0x0E04}, {0x2215, 0x0F04}, {0x2215, 0x0F05},
 345         {0x2216, 0x9400}, {0x2215, 0x0E05}, {0x2215, 0x0F05}, {0x2215, 0x0F06},
 346         {0x2216, 0x0803}, {0x2215, 0x0E06}, {0x2215, 0x0F06}, {0x2215, 0x0D00},
 347         {0x2215, 0x0100}, {0x221F, 0x0001}, {0x2210, 0xF05E}, {0x221F, 0x0000},
 348         {0x2217, 0x2100}, {0x221F, 0x0000}, {0x220D, 0x0003}, {0x220E, 0x0015},
 349         {0x220D, 0x4003}, {0x220E, 0x0006}, {0x221F, 0x0000}, {0x2200, 0x1340},
 350         {0x133F, 0x0010}, {0x12A0, 0x0058}, {0x12A1, 0x0058}, {0x133E, 0x000E},
 351         {0x133F, 0x0030}, {0x221F, 0x0000}, {0x2210, 0x0166}, {0x221F, 0x0000},
 352         {0x133E, 0x000E}, {0x133F, 0x0010}, {0x133F, 0x0030}, {0x133E, 0x000E},
 353         {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8B6E},
 354         {0x2206, 0x0000}, {0x220F, 0x0100}, {0x2205, 0x8000}, {0x2206, 0x0280},
 355         {0x2206, 0x28F7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
 356         {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
 357         {0x2206, 0x6602}, {0x2206, 0x80B9}, {0x2206, 0xE08B}, {0x2206, 0x8CE1},
 358         {0x2206, 0x8B8D}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x8E1E},
 359         {0x2206, 0x01A0}, {0x2206, 0x00E7}, {0x2206, 0xAEDB}, {0x2206, 0xEEE0},
 360         {0x2206, 0x120E}, {0x2206, 0xEEE0}, {0x2206, 0x1300}, {0x2206, 0xEEE0},
 361         {0x2206, 0x2001}, {0x2206, 0xEEE0}, {0x2206, 0x2166}, {0x2206, 0xEEE0},
 362         {0x2206, 0xC463}, {0x2206, 0xEEE0}, {0x2206, 0xC5E8}, {0x2206, 0xEEE0},
 363         {0x2206, 0xC699}, {0x2206, 0xEEE0}, {0x2206, 0xC7C2}, {0x2206, 0xEEE0},
 364         {0x2206, 0xC801}, {0x2206, 0xEEE0}, {0x2206, 0xC913}, {0x2206, 0xEEE0},
 365         {0x2206, 0xCA30}, {0x2206, 0xEEE0}, {0x2206, 0xCB3E}, {0x2206, 0xEEE0},
 366         {0x2206, 0xDCE1}, {0x2206, 0xEEE0}, {0x2206, 0xDD00}, {0x2206, 0xEEE2},
 367         {0x2206, 0x0001}, {0x2206, 0xEEE2}, {0x2206, 0x0100}, {0x2206, 0xEEE4},
 368         {0x2206, 0x8860}, {0x2206, 0xEEE4}, {0x2206, 0x8902}, {0x2206, 0xEEE4},
 369         {0x2206, 0x8C00}, {0x2206, 0xEEE4}, {0x2206, 0x8D30}, {0x2206, 0xEEEA},
 370         {0x2206, 0x1480}, {0x2206, 0xEEEA}, {0x2206, 0x1503}, {0x2206, 0xEEEA},
 371         {0x2206, 0xC600}, {0x2206, 0xEEEA}, {0x2206, 0xC706}, {0x2206, 0xEE85},
 372         {0x2206, 0xEE00}, {0x2206, 0xEE85}, {0x2206, 0xEF00}, {0x2206, 0xEE8B},
 373         {0x2206, 0x6750}, {0x2206, 0xEE8B}, {0x2206, 0x6632}, {0x2206, 0xEE8A},
 374         {0x2206, 0xD448}, {0x2206, 0xEE8A}, {0x2206, 0xD548}, {0x2206, 0xEE8A},
 375         {0x2206, 0xD649}, {0x2206, 0xEE8A}, {0x2206, 0xD7F8}, {0x2206, 0xEE8B},
 376         {0x2206, 0x85E2}, {0x2206, 0xEE8B}, {0x2206, 0x8700}, {0x2206, 0xEEFF},
 377         {0x2206, 0xF600}, {0x2206, 0xEEFF}, {0x2206, 0xF7FC}, {0x2206, 0x04F8},
 378         {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2023}, {0x2206, 0xF620},
 379         {0x2206, 0xE48B}, {0x2206, 0x8E02}, {0x2206, 0x2877}, {0x2206, 0x0225},
 380         {0x2206, 0xC702}, {0x2206, 0x26A1}, {0x2206, 0x0281}, {0x2206, 0xB302},
 381         {0x2206, 0x8496}, {0x2206, 0x0202}, {0x2206, 0xA102}, {0x2206, 0x27F1},
 382         {0x2206, 0x0228}, {0x2206, 0xF902}, {0x2206, 0x2AA0}, {0x2206, 0x0282},
 383         {0x2206, 0xB8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD21}, {0x2206, 0x08F6},
 384         {0x2206, 0x21E4}, {0x2206, 0x8B8E}, {0x2206, 0x0202}, {0x2206, 0x80E0},
 385         {0x2206, 0x8B8E}, {0x2206, 0xAD22}, {0x2206, 0x05F6}, {0x2206, 0x22E4},
 386         {0x2206, 0x8B8E}, {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2305},
 387         {0x2206, 0xF623}, {0x2206, 0xE48B}, {0x2206, 0x8EE0}, {0x2206, 0x8B8E},
 388         {0x2206, 0xAD24}, {0x2206, 0x08F6}, {0x2206, 0x24E4}, {0x2206, 0x8B8E},
 389         {0x2206, 0x0227}, {0x2206, 0x6AE0}, {0x2206, 0x8B8E}, {0x2206, 0xAD25},
 390         {0x2206, 0x05F6}, {0x2206, 0x25E4}, {0x2206, 0x8B8E}, {0x2206, 0xE08B},
 391         {0x2206, 0x8EAD}, {0x2206, 0x260B}, {0x2206, 0xF626}, {0x2206, 0xE48B},
 392         {0x2206, 0x8E02}, {0x2206, 0x830D}, {0x2206, 0x021D}, {0x2206, 0x6BE0},
 393         {0x2206, 0x8B8E}, {0x2206, 0xAD27}, {0x2206, 0x05F6}, {0x2206, 0x27E4},
 394         {0x2206, 0x8B8E}, {0x2206, 0x0281}, {0x2206, 0x4402}, {0x2206, 0x045C},
 395         {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B83}, {0x2206, 0xAD23},
 396         {0x2206, 0x30E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x2359},
 397         {0x2206, 0x02E0}, {0x2206, 0x85EF}, {0x2206, 0xE585}, {0x2206, 0xEFAC},
 398         {0x2206, 0x2907}, {0x2206, 0x1F01}, {0x2206, 0x9E51}, {0x2206, 0xAD29},
 399         {0x2206, 0x20E0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x06E1},
 400         {0x2206, 0x8B84}, {0x2206, 0xAD28}, {0x2206, 0x42E0}, {0x2206, 0x8B85},
 401         {0x2206, 0xAD21}, {0x2206, 0x06E1}, {0x2206, 0x8B84}, {0x2206, 0xAD29},
 402         {0x2206, 0x36BF}, {0x2206, 0x34BF}, {0x2206, 0x022C}, {0x2206, 0x31AE},
 403         {0x2206, 0x2EE0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x10E0},
 404         {0x2206, 0x8B84}, {0x2206, 0xF620}, {0x2206, 0xE48B}, {0x2206, 0x84EE},
 405         {0x2206, 0x8ADA}, {0x2206, 0x00EE}, {0x2206, 0x8ADB}, {0x2206, 0x00E0},
 406         {0x2206, 0x8B85}, {0x2206, 0xAD21}, {0x2206, 0x0CE0}, {0x2206, 0x8B84},
 407         {0x2206, 0xF621}, {0x2206, 0xE48B}, {0x2206, 0x84EE}, {0x2206, 0x8B72},
 408         {0x2206, 0xFFBF}, {0x2206, 0x34C2}, {0x2206, 0x022C}, {0x2206, 0x31FC},
 409         {0x2206, 0x04F8}, {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B85},
 410         {0x2206, 0xAD21}, {0x2206, 0x42E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0},
 411         {0x2206, 0x2358}, {0x2206, 0xC059}, {0x2206, 0x021E}, {0x2206, 0x01E1},
 412         {0x2206, 0x8B72}, {0x2206, 0x1F10}, {0x2206, 0x9E2F}, {0x2206, 0xE48B},
 413         {0x2206, 0x72AD}, {0x2206, 0x2123}, {0x2206, 0xE18B}, {0x2206, 0x84F7},
 414         {0x2206, 0x29E5}, {0x2206, 0x8B84}, {0x2206, 0xAC27}, {0x2206, 0x10AC},
 415         {0x2206, 0x2605}, {0x2206, 0x0205}, {0x2206, 0x23AE}, {0x2206, 0x1602},
 416         {0x2206, 0x0535}, {0x2206, 0x0282}, {0x2206, 0x30AE}, {0x2206, 0x0E02},
 417         {0x2206, 0x056A}, {0x2206, 0x0282}, {0x2206, 0x75AE}, {0x2206, 0x0602},
 418         {0x2206, 0x04DC}, {0x2206, 0x0282}, {0x2206, 0x04EF}, {0x2206, 0x96FE},
 419         {0x2206, 0xFC04}, {0x2206, 0xF8F9}, {0x2206, 0xE08B}, {0x2206, 0x87AD},
 420         {0x2206, 0x2321}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
 421         {0x2206, 0xAD26}, {0x2206, 0x18F6}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
 422         {0x2206, 0xE5EA}, {0x2206, 0x15F6}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
 423         {0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
 424         {0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
 425         {0x2206, 0xE08B}, {0x2206, 0x87AD}, {0x2206, 0x233A}, {0x2206, 0xAD22},
 426         {0x2206, 0x37E0}, {0x2206, 0xE020}, {0x2206, 0xE1E0}, {0x2206, 0x21AC},
 427         {0x2206, 0x212E}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
 428         {0x2206, 0xF627}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
 429         {0x2206, 0xE2EA}, {0x2206, 0x12E3}, {0x2206, 0xEA13}, {0x2206, 0x5A8F},
 430         {0x2206, 0x6A20}, {0x2206, 0xE6EA}, {0x2206, 0x12E7}, {0x2206, 0xEA13},
 431         {0x2206, 0xF726}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
 432         {0x2206, 0xF727}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
 433         {0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B87},
 434         {0x2206, 0xAD23}, {0x2206, 0x38AD}, {0x2206, 0x2135}, {0x2206, 0xE0E0},
 435         {0x2206, 0x20E1}, {0x2206, 0xE021}, {0x2206, 0xAC21}, {0x2206, 0x2CE0},
 436         {0x2206, 0xEA14}, {0x2206, 0xE1EA}, {0x2206, 0x15F6}, {0x2206, 0x27E4},
 437         {0x2206, 0xEA14}, {0x2206, 0xE5EA}, {0x2206, 0x15E2}, {0x2206, 0xEA12},
 438         {0x2206, 0xE3EA}, {0x2206, 0x135A}, {0x2206, 0x8FE6}, {0x2206, 0xEA12},
 439         {0x2206, 0xE7EA}, {0x2206, 0x13F7}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
 440         {0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
 441         {0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
 442         {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2146},
 443         {0x2206, 0xE0E0}, {0x2206, 0x22E1}, {0x2206, 0xE023}, {0x2206, 0x58C0},
 444         {0x2206, 0x5902}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x651F},
 445         {0x2206, 0x109E}, {0x2206, 0x33E4}, {0x2206, 0x8B65}, {0x2206, 0xAD21},
 446         {0x2206, 0x22AD}, {0x2206, 0x272A}, {0x2206, 0xD400}, {0x2206, 0x01BF},
 447         {0x2206, 0x34F2}, {0x2206, 0x022C}, {0x2206, 0xA2BF}, {0x2206, 0x34F5},
 448         {0x2206, 0x022C}, {0x2206, 0xE0E0}, {0x2206, 0x8B67}, {0x2206, 0x1B10},
 449         {0x2206, 0xAA14}, {0x2206, 0xE18B}, {0x2206, 0x660D}, {0x2206, 0x1459},
 450         {0x2206, 0x0FAE}, {0x2206, 0x05E1}, {0x2206, 0x8B66}, {0x2206, 0x590F},
 451         {0x2206, 0xBF85}, {0x2206, 0x6102}, {0x2206, 0x2CA2}, {0x2206, 0xEF96},
 452         {0x2206, 0xFEFC}, {0x2206, 0x04F8}, {0x2206, 0xF9FA}, {0x2206, 0xFBEF},
 453         {0x2206, 0x79E2}, {0x2206, 0x8AD2}, {0x2206, 0xAC19}, {0x2206, 0x2DE0},
 454         {0x2206, 0xE036}, {0x2206, 0xE1E0}, {0x2206, 0x37EF}, {0x2206, 0x311F},
 455         {0x2206, 0x325B}, {0x2206, 0x019E}, {0x2206, 0x1F7A}, {0x2206, 0x0159},
 456         {0x2206, 0x019F}, {0x2206, 0x0ABF}, {0x2206, 0x348E}, {0x2206, 0x022C},
 457         {0x2206, 0x31F6}, {0x2206, 0x06AE}, {0x2206, 0x0FF6}, {0x2206, 0x0302},
 458         {0x2206, 0x0470}, {0x2206, 0xF703}, {0x2206, 0xF706}, {0x2206, 0xBF34},
 459         {0x2206, 0x9302}, {0x2206, 0x2C31}, {0x2206, 0xAC1A}, {0x2206, 0x25E0},
 460         {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x23EF}, {0x2206, 0x300D},
 461         {0x2206, 0x311F}, {0x2206, 0x325B}, {0x2206, 0x029E}, {0x2206, 0x157A},
 462         {0x2206, 0x0258}, {0x2206, 0xC4A0}, {0x2206, 0x0408}, {0x2206, 0xBF34},
 463         {0x2206, 0x9E02}, {0x2206, 0x2C31}, {0x2206, 0xAE06}, {0x2206, 0xBF34},
 464         {0x2206, 0x9C02}, {0x2206, 0x2C31}, {0x2206, 0xAC1B}, {0x2206, 0x4AE0},
 465         {0x2206, 0xE012}, {0x2206, 0xE1E0}, {0x2206, 0x13EF}, {0x2206, 0x300D},
 466         {0x2206, 0x331F}, {0x2206, 0x325B}, {0x2206, 0x1C9E}, {0x2206, 0x3AEF},
 467         {0x2206, 0x325B}, {0x2206, 0x1C9F}, {0x2206, 0x09BF}, {0x2206, 0x3498},
 468         {0x2206, 0x022C}, {0x2206, 0x3102}, {0x2206, 0x83C5}, {0x2206, 0x5A03},
 469         {0x2206, 0x0D03}, {0x2206, 0x581C}, {0x2206, 0x1E20}, {0x2206, 0x0207},
 470         {0x2206, 0xA0A0}, {0x2206, 0x000E}, {0x2206, 0x0284}, {0x2206, 0x17AD},
 471         {0x2206, 0x1817}, {0x2206, 0xBF34}, {0x2206, 0x9A02}, {0x2206, 0x2C31},
 472         {0x2206, 0xAE0F}, {0x2206, 0xBF34}, {0x2206, 0xC802}, {0x2206, 0x2C31},
 473         {0x2206, 0xBF34}, {0x2206, 0xC502}, {0x2206, 0x2C31}, {0x2206, 0x0284},
 474         {0x2206, 0x52E6}, {0x2206, 0x8AD2}, {0x2206, 0xEF97}, {0x2206, 0xFFFE},
 475         {0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xBF34}, {0x2206, 0xDA02},
 476         {0x2206, 0x2CE0}, {0x2206, 0xE58A}, {0x2206, 0xD3BF}, {0x2206, 0x34D4},
 477         {0x2206, 0x022C}, {0x2206, 0xE00C}, {0x2206, 0x1159}, {0x2206, 0x02E0},
 478         {0x2206, 0x8AD3}, {0x2206, 0x1E01}, {0x2206, 0xE48A}, {0x2206, 0xD3D1},
 479         {0x2206, 0x00BF}, {0x2206, 0x34DA}, {0x2206, 0x022C}, {0x2206, 0xA2D1},
 480         {0x2206, 0x01BF}, {0x2206, 0x34D4}, {0x2206, 0x022C}, {0x2206, 0xA2BF},
 481         {0x2206, 0x34CB}, {0x2206, 0x022C}, {0x2206, 0xE0E5}, {0x2206, 0x8ACE},
 482         {0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CE0}, {0x2206, 0xE58A},
 483         {0x2206, 0xCFBF}, {0x2206, 0x8564}, {0x2206, 0x022C}, {0x2206, 0xE0E5},
 484         {0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6A02}, {0x2206, 0x2CE0},
 485         {0x2206, 0xE58A}, {0x2206, 0xD1FC}, {0x2206, 0x04F8}, {0x2206, 0xE18A},
 486         {0x2206, 0xD1BF}, {0x2206, 0x856A}, {0x2206, 0x022C}, {0x2206, 0xA2E1},
 487         {0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
 488         {0x2206, 0xE18A}, {0x2206, 0xCFBF}, {0x2206, 0x8567}, {0x2206, 0x022C},
 489         {0x2206, 0xA2E1}, {0x2206, 0x8ACE}, {0x2206, 0xBF34}, {0x2206, 0xCB02},
 490         {0x2206, 0x2CA2}, {0x2206, 0xE18A}, {0x2206, 0xD3BF}, {0x2206, 0x34DA},
 491         {0x2206, 0x022C}, {0x2206, 0xA2E1}, {0x2206, 0x8AD3}, {0x2206, 0x0D11},
 492         {0x2206, 0xBF34}, {0x2206, 0xD402}, {0x2206, 0x2CA2}, {0x2206, 0xFC04},
 493         {0x2206, 0xF9A0}, {0x2206, 0x0405}, {0x2206, 0xE38A}, {0x2206, 0xD4AE},
 494         {0x2206, 0x13A0}, {0x2206, 0x0805}, {0x2206, 0xE38A}, {0x2206, 0xD5AE},
 495         {0x2206, 0x0BA0}, {0x2206, 0x0C05}, {0x2206, 0xE38A}, {0x2206, 0xD6AE},
 496         {0x2206, 0x03E3}, {0x2206, 0x8AD7}, {0x2206, 0xEF13}, {0x2206, 0xBF34},
 497         {0x2206, 0xCB02}, {0x2206, 0x2CA2}, {0x2206, 0xEF13}, {0x2206, 0x0D11},
 498         {0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CA2}, {0x2206, 0xEF13},
 499         {0x2206, 0x0D14}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
 500         {0x2206, 0xEF13}, {0x2206, 0x0D17}, {0x2206, 0xBF85}, {0x2206, 0x6A02},
 501         {0x2206, 0x2CA2}, {0x2206, 0xFD04}, {0x2206, 0xF8E0}, {0x2206, 0x8B85},
 502         {0x2206, 0xAD27}, {0x2206, 0x2DE0}, {0x2206, 0xE036}, {0x2206, 0xE1E0},
 503         {0x2206, 0x37E1}, {0x2206, 0x8B73}, {0x2206, 0x1F10}, {0x2206, 0x9E20},
 504         {0x2206, 0xE48B}, {0x2206, 0x73AC}, {0x2206, 0x200B}, {0x2206, 0xAC21},
 505         {0x2206, 0x0DAC}, {0x2206, 0x250F}, {0x2206, 0xAC27}, {0x2206, 0x0EAE},
 506         {0x2206, 0x0F02}, {0x2206, 0x84CC}, {0x2206, 0xAE0A}, {0x2206, 0x0284},
 507         {0x2206, 0xD1AE}, {0x2206, 0x05AE}, {0x2206, 0x0302}, {0x2206, 0x84D8},
 508         {0x2206, 0xFC04}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0x0402},
 509         {0x2206, 0x84E5}, {0x2206, 0x0285}, {0x2206, 0x2804}, {0x2206, 0x0285},
 510         {0x2206, 0x4904}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0xEE8B},
 511         {0x2206, 0x6902}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B85},
 512         {0x2206, 0xAD26}, {0x2206, 0x38D0}, {0x2206, 0x0B02}, {0x2206, 0x2B4D},
 513         {0x2206, 0x5882}, {0x2206, 0x7882}, {0x2206, 0x9F2D}, {0x2206, 0xE08B},
 514         {0x2206, 0x68E1}, {0x2206, 0x8B69}, {0x2206, 0x1F10}, {0x2206, 0x9EC8},
 515         {0x2206, 0x10E4}, {0x2206, 0x8B68}, {0x2206, 0xE0E0}, {0x2206, 0x00E1},
 516         {0x2206, 0xE001}, {0x2206, 0xF727}, {0x2206, 0xE4E0}, {0x2206, 0x00E5},
 517         {0x2206, 0xE001}, {0x2206, 0xE2E0}, {0x2206, 0x20E3}, {0x2206, 0xE021},
 518         {0x2206, 0xAD30}, {0x2206, 0xF7F6}, {0x2206, 0x27E4}, {0x2206, 0xE000},
 519         {0x2206, 0xE5E0}, {0x2206, 0x01FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
 520         {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2212},
 521         {0x2206, 0xE0E0}, {0x2206, 0x14E1}, {0x2206, 0xE015}, {0x2206, 0xAD26},
 522         {0x2206, 0x9CE1}, {0x2206, 0x85E0}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
 523         {0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x04F8},
 524         {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B86}, {0x2206, 0xAD22},
 525         {0x2206, 0x09E1}, {0x2206, 0x85E1}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
 526         {0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x0464},
 527         {0x2206, 0xE48C}, {0x2206, 0xFDE4}, {0x2206, 0x80CA}, {0x2206, 0xE480},
 528         {0x2206, 0x66E0}, {0x2206, 0x8E70}, {0x2206, 0xE076}, {0x2205, 0xE142},
 529         {0x2206, 0x0701}, {0x2205, 0xE140}, {0x2206, 0x0405}, {0x220F, 0x0000},
 530         {0x221F, 0x0000}, {0x2200, 0x1340}, {0x133E, 0x000E}, {0x133F, 0x0010},
 531         {0x13EB, 0x11BB}
 532 };
 533
 534 static const struct rtl8367b_initval rtl8367r_vb_initvals_1[] = {
 535         {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x1305, 0xC000}, {0x121E, 0x03CA},
 536         {0x1233, 0x0352}, {0x1234, 0x0064}, {0x1237, 0x0096}, {0x1238, 0x0078},
 537         {0x1239, 0x0084}, {0x123A, 0x0030}, {0x205F, 0x0002}, {0x2059, 0x1A00},
 538         {0x205F, 0x0000}, {0x207F, 0x0002}, {0x2077, 0x0000}, {0x2078, 0x0000},
 539         {0x2079, 0x0000}, {0x207A, 0x0000}, {0x207B, 0x0000}, {0x207F, 0x0000},
 540         {0x205F, 0x0002}, {0x2053, 0x0000}, {0x2054, 0x0000}, {0x2055, 0x0000},
 541         {0x2056, 0x0000}, {0x2057, 0x0000}, {0x205F, 0x0000}, {0x133F, 0x0030},
 542         {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2205, 0x8B86}, {0x2206, 0x800E},
 543         {0x221F, 0x0000}, {0x133F, 0x0010}, {0x12A3, 0x2200}, {0x6107, 0xE58B},
 544         {0x6103, 0xA970}, {0x0018, 0x0F00}, {0x0038, 0x0F00}, {0x0058, 0x0F00},
 545         {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x133F, 0x0030}, {0x133E, 0x000E},
 546         {0x221F, 0x0005}, {0x2205, 0x8B6E}, {0x2206, 0x0000}, {0x220F, 0x0100},
 547         {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8000}, {0x2206, 0x0280},
 548         {0x2206, 0x2BF7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
 549         {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
 550         {0x2206, 0x6602}, {0x2206, 0x8044}, {0x2206, 0x0201}, {0x2206, 0x7CE0},
 551         {0x2206, 0x8B8C}, {0x2206, 0xE18B}, {0x2206, 0x8D1E}, {0x2206, 0x01E1},
 552         {0x2206, 0x8B8E}, {0x2206, 0x1E01}, {0x2206, 0xA000}, {0x2206, 0xE4AE},
 553         {0x2206, 0xD8EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE}, {0x2206, 0x85C1},
 554         {0x2206, 0x00EE}, {0x2206, 0x8AFC}, {0x2206, 0x07EE}, {0x2206, 0x8AFD},
 555         {0x2206, 0x73EE}, {0x2206, 0xFFF6}, {0x2206, 0x00EE}, {0x2206, 0xFFF7},
 556         {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD20},
 557         {0x2206, 0x0302}, {0x2206, 0x8050}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
 558         {0x2206, 0xE08B}, {0x2206, 0x85AD}, {0x2206, 0x2548}, {0x2206, 0xE08A},
 559         {0x2206, 0xE4E1}, {0x2206, 0x8AE5}, {0x2206, 0x7C00}, {0x2206, 0x009E},
 560         {0x2206, 0x35EE}, {0x2206, 0x8AE4}, {0x2206, 0x00EE}, {0x2206, 0x8AE5},
 561         {0x2206, 0x00E0}, {0x2206, 0x8AFC}, {0x2206, 0xE18A}, {0x2206, 0xFDE2},
 562         {0x2206, 0x85C0}, {0x2206, 0xE385}, {0x2206, 0xC102}, {0x2206, 0x2DAC},
 563         {0x2206, 0xAD20}, {0x2206, 0x12EE}, {0x2206, 0x8AE4}, {0x2206, 0x03EE},
 564         {0x2206, 0x8AE5}, {0x2206, 0xB7EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE},
 565         {0x2206, 0x85C1}, {0x2206, 0x00AE}, {0x2206, 0x1115}, {0x2206, 0xE685},
 566         {0x2206, 0xC0E7}, {0x2206, 0x85C1}, {0x2206, 0xAE08}, {0x2206, 0xEE85},
 567         {0x2206, 0xC000}, {0x2206, 0xEE85}, {0x2206, 0xC100}, {0x2206, 0xFDFC},
 568         {0x2206, 0x0400}, {0x2205, 0xE142}, {0x2206, 0x0701}, {0x2205, 0xE140},
 569         {0x2206, 0x0405}, {0x220F, 0x0000}, {0x221F, 0x0000}, {0x133E, 0x000E},
 570         {0x133F, 0x0010}, {0x13EB, 0x11BB}, {0x207F, 0x0002}, {0x2073, 0x1D22},
 571         {0x207F, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x2200, 0x1340},
 572         {0x133E, 0x000E}, {0x133F, 0x0010},
 573 };
 574
 575 static int rtl8367b_write_initvals(struct rtl8366_smi *smi,
 576                                   const struct rtl8367b_initval *initvals,
 577                                   int count)
 578 {
 579         int err;
 580         int i;
 581
 582         for (i = 0; i < count; i++)
 583                 REG_WR(smi, initvals[i].reg, initvals[i].val);
 584
 585         return 0;
 586 }
 587
 588 static int rtl8367b_read_phy_reg(struct rtl8366_smi *smi,
 589                                 u32 phy_addr, u32 phy_reg, u32 *val)
 590 {
 591         int timeout;
 592         u32 data;
 593         int err;
 594
 595         if (phy_addr > RTL8367B_PHY_ADDR_MAX)
 596                 return -EINVAL;
 597
 598         if (phy_reg > RTL8367B_PHY_REG_MAX)
 599                 return -EINVAL;
 600
 601         REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
 602         if (data & RTL8367B_IA_STATUS_PHY_BUSY)
 603                 return -ETIMEDOUT;
 604
 605         /* prepare address */
 606         REG_WR(smi, RTL8367B_IA_ADDRESS_REG,
 607                RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg));
 608
 609         /* send read command */
 610         REG_WR(smi, RTL8367B_IA_CTRL_REG,
 611                RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_READ);
 612
 613         timeout = 5;
 614         do {
 615                 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
 616                 if ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0)
 617                         break;
 618
 619                 if (timeout--) {
 620                         dev_err(smi->parent, "phy read timed out\n");
 621                         return -ETIMEDOUT;
 622                 }
 623
 624                 udelay(1);
 625         } while (1);
 626
 627         /* read data */
 628         REG_RD(smi, RTL8367B_IA_READ_DATA_REG, val);
 629
 630         dev_dbg(smi->parent, "phy_read: addr:%02x, reg:%02x, val:%04x\n",
 631                 phy_addr, phy_reg, *val);
 632         return 0;
 633 }
 634
 635 static int rtl8367b_write_phy_reg(struct rtl8366_smi *smi,
 636                                  u32 phy_addr, u32 phy_reg, u32 val)
 637 {
 638         int timeout;
 639         u32 data;
 640         int err;
 641
 642         dev_dbg(smi->parent, "phy_write: addr:%02x, reg:%02x, val:%04x\n",
 643                 phy_addr, phy_reg, val);
 644
 645         if (phy_addr > RTL8367B_PHY_ADDR_MAX)
 646                 return -EINVAL;
 647
 648         if (phy_reg > RTL8367B_PHY_REG_MAX)
 649                 return -EINVAL;
 650
 651         REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
 652         if (data & RTL8367B_IA_STATUS_PHY_BUSY)
 653                 return -ETIMEDOUT;
 654
 655         /* preapre data */
 656         REG_WR(smi, RTL8367B_IA_WRITE_DATA_REG, val);
 657
 658         /* prepare address */
 659         REG_WR(smi, RTL8367B_IA_ADDRESS_REG,
 660                RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg));
 661
 662         /* send write command */
 663         REG_WR(smi, RTL8367B_IA_CTRL_REG,
 664                RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_WRITE);
 665
 666         timeout = 5;
 667         do {
 668                 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
 669                 if ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0)
 670                         break;
 671
 672                 if (timeout--) {
 673                         dev_err(smi->parent, "phy write timed out\n");
 674                         return -ETIMEDOUT;
 675                 }
 676
 677                 udelay(1);
 678         } while (1);
 679
 680         return 0;
 681 }
 682
 683 static int rtl8367b_init_regs(struct rtl8366_smi *smi)
 684 {
 685         const struct rtl8367b_initval *initvals;
 686         u32 chip_ver;
 687         u32 rlvid;
 688         int count;
 689         int err;
 690
 691         REG_WR(smi, RTL8367B_RTL_MAGIC_ID_REG, RTL8367B_RTL_MAGIC_ID_VAL);
 692         REG_RD(smi, RTL8367B_CHIP_VER_REG, &chip_ver);
 693
 694         rlvid = (chip_ver >> RTL8367B_CHIP_VER_RLVID_SHIFT) &
 695                 RTL8367B_CHIP_VER_RLVID_MASK;
 696
 697         switch (rlvid) {
 698         case 0:
 699                 initvals = rtl8367r_vb_initvals_0;
 700                 count = ARRAY_SIZE(rtl8367r_vb_initvals_0);
 701                 break;
 702
 703         case 1:
 704                 initvals = rtl8367r_vb_initvals_1;
 705                 count = ARRAY_SIZE(rtl8367r_vb_initvals_1);
 706                 break;
 707
 708         default:
 709                 dev_err(smi->parent, "unknow rlvid %u\n", rlvid);
 710                 return -ENODEV;
 711         }
 712
 713         /* TODO: disable RLTP */
 714
 715         return rtl8367b_write_initvals(smi, initvals, count);
 716 }
 717
 718 static int rtl8367b_reset_chip(struct rtl8366_smi *smi)
 719 {
 720         int timeout = 10;
 721         int err;
 722         u32 data;
 723
 724         REG_WR(smi, RTL8367B_CHIP_RESET_REG, RTL8367B_CHIP_RESET_HW);
 725         msleep(RTL8367B_RESET_DELAY);
 726
 727         do {
 728                 REG_RD(smi, RTL8367B_CHIP_RESET_REG, &data);
 729                 if (!(data & RTL8367B_CHIP_RESET_HW))
 730                         break;
 731
 732                 msleep(1);
 733         } while (--timeout);
 734
 735         if (!timeout) {
 736                 dev_err(smi->parent, "chip reset timed out\n");
 737                 return -ETIMEDOUT;
 738         }
 739
 740         return 0;
 741 }
 742
 743 static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
 744                                    enum rtl8367_extif_mode mode)
 745 {
 746         int err;
 747
 748         /* set port mode */
 749         switch (mode) {
 750         case RTL8367_EXTIF_MODE_RGMII:
 751         case RTL8367_EXTIF_MODE_RGMII_33V:
 752                 REG_WR(smi, RTL8367B_CHIP_DEBUG0_REG, 0x0367);
 753                 REG_WR(smi, RTL8367B_CHIP_DEBUG1_REG, 0x7777);
 754                 break;
 755
 756         case RTL8367_EXTIF_MODE_TMII_MAC:
 757         case RTL8367_EXTIF_MODE_TMII_PHY:
 758                 REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG,
 759                         BIT((id + 1) % 2), BIT((id + 1) % 2));
 760                 break;
 761
 762         case RTL8367_EXTIF_MODE_GMII:
 763                 REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
 764                         RTL8367B_CHIP_DEBUG0_DUMMY0(id),
 765                         RTL8367B_CHIP_DEBUG0_DUMMY0(id));
 766                 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), BIT(6));
 767                 break;
 768
 769         case RTL8367_EXTIF_MODE_MII_MAC:
 770         case RTL8367_EXTIF_MODE_MII_PHY:
 771         case RTL8367_EXTIF_MODE_DISABLED:
 772                 REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG,
 773                         BIT((id + 1) % 2), 0);
 774                 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), 0);
 775                 break;
 776
 777         default:
 778                 dev_err(smi->parent,
 779                         "invalid mode for external interface %d\n", id);
 780                 return -EINVAL;
 781         }
 782
 783         REG_RMW(smi, RTL8367B_DIS_REG,
 784                 RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id),
 785                 mode << RTL8367B_DIS_RGMII_SHIFT(id));
 786
 787         return 0;
 788 }
 789
 790 static int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id,
 791                                     struct rtl8367_port_ability *pa)
 792 {
 793         u32 mask;
 794         u32 val;
 795         int err;
 796
 797         mask = (RTL8367B_DI_FORCE_MODE |
 798                 RTL8367B_DI_FORCE_NWAY |
 799                 RTL8367B_DI_FORCE_TXPAUSE |
 800                 RTL8367B_DI_FORCE_RXPAUSE |
 801                 RTL8367B_DI_FORCE_LINK |
 802                 RTL8367B_DI_FORCE_DUPLEX |
 803                 RTL8367B_DI_FORCE_SPEED_MASK);
 804
 805         val = pa->speed;
 806         val |= pa->force_mode ? RTL8367B_DI_FORCE_MODE : 0;
 807         val |= pa->nway ? RTL8367B_DI_FORCE_NWAY : 0;
 808         val |= pa->txpause ? RTL8367B_DI_FORCE_TXPAUSE : 0;
 809         val |= pa->rxpause ? RTL8367B_DI_FORCE_RXPAUSE : 0;
 810         val |= pa->link ? RTL8367B_DI_FORCE_LINK : 0;
 811         val |= pa->duplex ? RTL8367B_DI_FORCE_DUPLEX : 0;
 812
 813         REG_RMW(smi, RTL8367B_DI_FORCE_REG(id), mask, val);
 814
 815         return 0;
 816 }
 817
 818 static int rtl8367b_extif_set_rgmii_delay(struct rtl8366_smi *smi, int id,
 819                                          unsigned txdelay, unsigned rxdelay)
 820 {
 821         u32 mask;
 822         u32 val;
 823         int err;
 824
 825         mask = (RTL8367B_EXT_RGMXF_RXDELAY_MASK |
 826                 (RTL8367B_EXT_RGMXF_TXDELAY_MASK <<
 827                         RTL8367B_EXT_RGMXF_TXDELAY_SHIFT));
 828
 829         val = rxdelay;
 830         val |= txdelay << RTL8367B_EXT_RGMXF_TXDELAY_SHIFT;
 831
 832         REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), mask, val);
 833
 834         return 0;
 835 }
 836
 837 static int rtl8367b_extif_init(struct rtl8366_smi *smi, int id,
 838                                struct rtl8367_extif_config *cfg)
 839 {
 840         enum rtl8367_extif_mode mode;
 841         int err;
 842
 843         mode = (cfg) ? cfg->mode : RTL8367_EXTIF_MODE_DISABLED;
 844
 845         err = rtl8367b_extif_set_mode(smi, id, mode);
 846         if (err)
 847                 return err;
 848
 849         if (mode != RTL8367_EXTIF_MODE_DISABLED) {
 850                 err = rtl8367b_extif_set_force(smi, id, &cfg->ability);
 851                 if (err)
 852                         return err;
 853
 854                 err = rtl8367b_extif_set_rgmii_delay(smi, id, cfg->txdelay,
 855                                                      cfg->rxdelay);
 856                 if (err)
 857                         return err;
 858         }
 859
 860         return 0;
 861 }
 862
 863 static int rtl8367b_setup(struct rtl8366_smi *smi)
 864 {
 865         struct rtl8367_platform_data *pdata;
 866         int err;
 867         int i;
 868
 869         pdata = smi->parent->platform_data;
 870
 871         err = rtl8367b_init_regs(smi);
 872         if (err)
 873                 return err;
 874
 875         /* initialize external interfaces */
 876         err = rtl8367b_extif_init(smi, 0, pdata->extif0_cfg);
 877         if (err)
 878                 return err;
 879
 880         err = rtl8367b_extif_init(smi, 1, pdata->extif1_cfg);
 881         if (err)
 882                 return err;
 883
 884         /* set maximum packet length to 1536 bytes */
 885         REG_RMW(smi, RTL8367B_SWC0_REG, RTL8367B_SWC0_MAX_LENGTH_MASK,
 886                 RTL8367B_SWC0_MAX_LENGTH_1536);
 887
 888         /*
 889          * discard VLAN tagged packets if the port is not a member of
 890          * the VLAN with which the packets is associated.
 891          */
 892         REG_WR(smi, RTL8367B_VLAN_INGRESS_REG, RTL8367B_PORTS_ALL);
 893
 894         /*
 895          * Setup egress tag mode for each port.
 896          */
 897         for (i = 0; i < RTL8367B_NUM_PORTS; i++)
 898                 REG_RMW(smi,
 899                         RTL8367B_PORT_MISC_CFG_REG(i),
 900                         RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK <<
 901                                 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT,
 902                         RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL <<
 903                                 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT);
 904
 905         return 0;
 906 }
 907
 908 static int rtl8367b_get_mib_counter(struct rtl8366_smi *smi, int counter,
 909                                     int port, unsigned long long *val)
 910 {
 911         struct rtl8366_mib_counter *mib;
 912         int offset;
 913         int i;
 914         int err;
 915         u32 addr, data;
 916         u64 mibvalue;
 917
 918         if (port > RTL8367B_NUM_PORTS ||
 919             counter >= RTL8367B_NUM_MIB_COUNTERS)
 920                 return -EINVAL;
 921
 922         mib = &rtl8367b_mib_counters[counter];
 923         addr = RTL8367B_MIB_COUNTER_PORT_OFFSET * port + mib->offset;
 924
 925         /*
 926          * Writing access counter address first
 927          * then ASIC will prepare 64bits counter wait for being retrived
 928          */
 929         REG_WR(smi, RTL8367B_MIB_ADDRESS_REG, addr >> 2);
 930
 931         /* read MIB control register */
 932         REG_RD(smi, RTL8367B_MIB_CTRL0_REG(0), &data);
 933
 934         if (data & RTL8367B_MIB_CTRL0_BUSY_MASK)
 935                 return -EBUSY;
 936
 937         if (data & RTL8367B_MIB_CTRL0_RESET_MASK)
 938                 return -EIO;
 939
 940         if (mib->length == 4)
 941                 offset = 3;
 942         else
 943                 offset = (mib->offset + 1) % 4;
 944
 945         mibvalue = 0;
 946         for (i = 0; i < mib->length; i++) {
 947                 REG_RD(smi, RTL8367B_MIB_COUNTER_REG(offset - i), &data);
 948                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 949         }
 950
 951         *val = mibvalue;
 952         return 0;
 953 }
 954
 955 static int rtl8367b_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 956                                 struct rtl8366_vlan_4k *vlan4k)
 957 {
 958         u32 data[RTL8367B_TA_VLAN_NUM_WORDS];
 959         int err;
 960         int i;
 961
 962         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 963
 964         if (vid >= RTL8367B_NUM_VIDS)
 965                 return -EINVAL;
 966
 967         /* write VID */
 968         REG_WR(smi, RTL8367B_TA_ADDR_REG, vid);
 969
 970         /* write table access control word */
 971         REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_READ);
 972
 973         for (i = 0; i < ARRAY_SIZE(data); i++)
 974                 REG_RD(smi, RTL8367B_TA_RDDATA_REG(i), &data[i]);
 975
 976         vlan4k->vid = vid;
 977         vlan4k->member = (data[0] >> RTL8367B_TA_VLAN0_MEMBER_SHIFT) &
 978                          RTL8367B_TA_VLAN0_MEMBER_MASK;
 979         vlan4k->untag = (data[0] >> RTL8367B_TA_VLAN0_UNTAG_SHIFT) &
 980                         RTL8367B_TA_VLAN0_UNTAG_MASK;
 981         vlan4k->fid = (data[1] >> RTL8367B_TA_VLAN1_FID_SHIFT) &
 982                       RTL8367B_TA_VLAN1_FID_MASK;
 983
 984         return 0;
 985 }
 986
 987 static int rtl8367b_set_vlan_4k(struct rtl8366_smi *smi,
 988                                 const struct rtl8366_vlan_4k *vlan4k)
 989 {
 990         u32 data[RTL8367B_TA_VLAN_NUM_WORDS];
 991         int err;
 992         int i;
 993
 994         if (vlan4k->vid >= RTL8367B_NUM_VIDS ||
 995             vlan4k->member > RTL8367B_TA_VLAN0_MEMBER_MASK ||
 996             vlan4k->untag > RTL8367B_UNTAG_MASK ||
 997             vlan4k->fid > RTL8367B_FIDMAX)
 998                 return -EINVAL;
 999
1000         memset(data, 0, sizeof(data));
1001
1002         data[0] = (vlan4k->member & RTL8367B_TA_VLAN0_MEMBER_MASK) <<
1003                   RTL8367B_TA_VLAN0_MEMBER_SHIFT;
1004         data[0] |= (vlan4k->untag & RTL8367B_TA_VLAN0_UNTAG_MASK) <<
1005                    RTL8367B_TA_VLAN0_UNTAG_SHIFT;
1006         data[1] = (vlan4k->fid & RTL8367B_TA_VLAN1_FID_MASK) <<
1007                   RTL8367B_TA_VLAN1_FID_SHIFT;
1008
1009         for (i = 0; i < ARRAY_SIZE(data); i++)
1010                 REG_WR(smi, RTL8367B_TA_WRDATA_REG(i), data[i]);
1011
1012         /* write VID */
1013         REG_WR(smi, RTL8367B_TA_ADDR_REG,
1014                vlan4k->vid & RTL8367B_TA_VLAN_VID_MASK);
1015
1016         /* write table access control word */
1017         REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_WRITE);
1018
1019         return 0;
1020 }
1021
1022 static int rtl8367b_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
1023                                 struct rtl8366_vlan_mc *vlanmc)
1024 {
1025         u32 data[RTL8367B_VLAN_MC_NUM_WORDS];
1026         int err;
1027         int i;
1028
1029         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1030
1031         if (index >= RTL8367B_NUM_VLANS)
1032                 return -EINVAL;
1033
1034         for (i = 0; i < ARRAY_SIZE(data); i++)
1035                 REG_RD(smi, RTL8367B_VLAN_MC_BASE(index) + i, &data[i]);
1036
1037         vlanmc->member = (data[0] >> RTL8367B_VLAN_MC0_MEMBER_SHIFT) &
1038                          RTL8367B_VLAN_MC0_MEMBER_MASK;
1039         vlanmc->fid = (data[1] >> RTL8367B_VLAN_MC1_FID_SHIFT) &
1040                       RTL8367B_VLAN_MC1_FID_MASK;
1041         vlanmc->vid = (data[3] >> RTL8367B_VLAN_MC3_EVID_SHIFT) &
1042                       RTL8367B_VLAN_MC3_EVID_MASK;
1043
1044         return 0;
1045 }
1046
1047 static int rtl8367b_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
1048                                 const struct rtl8366_vlan_mc *vlanmc)
1049 {
1050         u32 data[RTL8367B_VLAN_MC_NUM_WORDS];
1051         int err;
1052         int i;
1053
1054         if (index >= RTL8367B_NUM_VLANS ||
1055             vlanmc->vid >= RTL8367B_NUM_VIDS ||
1056             vlanmc->priority > RTL8367B_PRIORITYMAX ||
1057             vlanmc->member > RTL8367B_VLAN_MC0_MEMBER_MASK ||
1058             vlanmc->untag > RTL8367B_UNTAG_MASK ||
1059             vlanmc->fid > RTL8367B_FIDMAX)
1060                 return -EINVAL;
1061
1062         data[0] = (vlanmc->member & RTL8367B_VLAN_MC0_MEMBER_MASK) <<
1063                   RTL8367B_VLAN_MC0_MEMBER_SHIFT;
1064         data[1] = (vlanmc->fid & RTL8367B_VLAN_MC1_FID_MASK) <<
1065                   RTL8367B_VLAN_MC1_FID_SHIFT;
1066         data[2] = 0;
1067         data[3] = (vlanmc->vid & RTL8367B_VLAN_MC3_EVID_MASK) <<
1068                    RTL8367B_VLAN_MC3_EVID_SHIFT;
1069
1070         for (i = 0; i < ARRAY_SIZE(data); i++)
1071                 REG_WR(smi, RTL8367B_VLAN_MC_BASE(index) + i, data[i]);
1072
1073         return 0;
1074 }
1075
1076 static int rtl8367b_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
1077 {
1078         u32 data;
1079         int err;
1080
1081         if (port >= RTL8367B_NUM_PORTS)
1082                 return -EINVAL;
1083
1084         REG_RD(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), &data);
1085
1086         *val = (data >> RTL8367B_VLAN_PVID_CTRL_SHIFT(port)) &
1087                RTL8367B_VLAN_PVID_CTRL_MASK;
1088
1089         return 0;
1090 }
1091
1092 static int rtl8367b_set_mc_index(struct rtl8366_smi *smi, int port, int index)
1093 {
1094         if (port >= RTL8367B_NUM_PORTS || index >= RTL8367B_NUM_VLANS)
1095                 return -EINVAL;
1096
1097         return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_PVID_CTRL_REG(port),
1098                                 RTL8367B_VLAN_PVID_CTRL_MASK <<
1099                                         RTL8367B_VLAN_PVID_CTRL_SHIFT(port),
1100                                 (index & RTL8367B_VLAN_PVID_CTRL_MASK) <<
1101                                         RTL8367B_VLAN_PVID_CTRL_SHIFT(port));
1102 }
1103
1104 static int rtl8367b_enable_vlan(struct rtl8366_smi *smi, int enable)
1105 {
1106         return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_CTRL_REG,
1107                                 RTL8367B_VLAN_CTRL_ENABLE,
1108                                 (enable) ? RTL8367B_VLAN_CTRL_ENABLE : 0);
1109 }
1110
1111 static int rtl8367b_enable_vlan4k(struct rtl8366_smi *smi, int enable)
1112 {
1113         return 0;
1114 }
1115
1116 static int rtl8367b_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
1117 {
1118         unsigned max = RTL8367B_NUM_VLANS;
1119
1120         if (smi->vlan4k_enabled)
1121                 max = RTL8367B_NUM_VIDS - 1;
1122
1123         if (vlan == 0 || vlan >= max)
1124                 return 0;
1125
1126         return 1;
1127 }
1128
1129 static int rtl8367b_enable_port(struct rtl8366_smi *smi, int port, int enable)
1130 {
1131         int err;
1132
1133         REG_WR(smi, RTL8367B_PORT_ISOLATION_REG(port),
1134                (enable) ? RTL8367B_PORTS_ALL : 0);
1135
1136         return 0;
1137 }
1138
1139 static int rtl8367b_sw_reset_mibs(struct switch_dev *dev,
1140                                   const struct switch_attr *attr,
1141                                   struct switch_val *val)
1142 {
1143         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1144
1145         return rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(0), 0,
1146                                 RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK);
1147 }
1148
1149 static int rtl8367b_sw_get_port_link(struct switch_dev *dev,
1150                                     int port,
1151                                     struct switch_port_link *link)
1152 {
1153         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1154         u32 data = 0;
1155         u32 speed;
1156
1157         if (port >= RTL8367B_NUM_PORTS)
1158                 return -EINVAL;
1159
1160         rtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data);
1161
1162         link->link = !!(data & RTL8367B_PORT_STATUS_LINK);
1163         if (!link->link)
1164                 return 0;
1165
1166         link->duplex = !!(data & RTL8367B_PORT_STATUS_DUPLEX);
1167         link->rx_flow = !!(data & RTL8367B_PORT_STATUS_RXPAUSE);
1168         link->tx_flow = !!(data & RTL8367B_PORT_STATUS_TXPAUSE);
1169         link->aneg = !!(data & RTL8367B_PORT_STATUS_NWAY);
1170
1171         speed = (data & RTL8367B_PORT_STATUS_SPEED_MASK);
1172         switch (speed) {
1173         case 0:
1174                 link->speed = SWITCH_PORT_SPEED_10;
1175                 break;
1176         case 1:
1177                 link->speed = SWITCH_PORT_SPEED_100;
1178                 break;
1179         case 2:
1180                 link->speed = SWITCH_PORT_SPEED_1000;
1181                 break;
1182         default:
1183                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1184                 break;
1185         }
1186
1187         return 0;
1188 }
1189
1190 static int rtl8367b_sw_get_max_length(struct switch_dev *dev,
1191                                      const struct switch_attr *attr,
1192                                      struct switch_val *val)
1193 {
1194         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1195         u32 data;
1196
1197         rtl8366_smi_read_reg(smi, RTL8367B_SWC0_REG, &data);
1198         val->value.i = (data & RTL8367B_SWC0_MAX_LENGTH_MASK) >>
1199                         RTL8367B_SWC0_MAX_LENGTH_SHIFT;
1200
1201         return 0;
1202 }
1203
1204 static int rtl8367b_sw_set_max_length(struct switch_dev *dev,
1205                                      const struct switch_attr *attr,
1206                                      struct switch_val *val)
1207 {
1208         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1209         u32 max_len;
1210
1211         switch (val->value.i) {
1212         case 0:
1213                 max_len = RTL8367B_SWC0_MAX_LENGTH_1522;
1214                 break;
1215         case 1:
1216                 max_len = RTL8367B_SWC0_MAX_LENGTH_1536;
1217                 break;
1218         case 2:
1219                 max_len = RTL8367B_SWC0_MAX_LENGTH_1552;
1220                 break;
1221         case 3:
1222                 max_len = RTL8367B_SWC0_MAX_LENGTH_16000;
1223                 break;
1224         default:
1225                 return -EINVAL;
1226         }
1227
1228         return rtl8366_smi_rmwr(smi, RTL8367B_SWC0_REG,
1229                                 RTL8367B_SWC0_MAX_LENGTH_MASK, max_len);
1230 }
1231
1232
1233 static int rtl8367b_sw_reset_port_mibs(struct switch_dev *dev,
1234                                        const struct switch_attr *attr,
1235                                        struct switch_val *val)
1236 {
1237         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1238         int port;
1239
1240         port = val->port_vlan;
1241         if (port >= RTL8367B_NUM_PORTS)
1242                 return -EINVAL;
1243
1244         return rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(port / 8), 0,
1245                                 RTL8367B_MIB_CTRL0_PORT_RESET_MASK(port % 8));
1246 }
1247
1248 static struct switch_attr rtl8367b_globals[] = {
1249         {
1250                 .type = SWITCH_TYPE_INT,
1251                 .name = "enable_vlan",
1252                 .description = "Enable VLAN mode",
1253                 .set = rtl8366_sw_set_vlan_enable,
1254                 .get = rtl8366_sw_get_vlan_enable,
1255                 .max = 1,
1256                 .ofs = 1
1257         }, {
1258                 .type = SWITCH_TYPE_INT,
1259                 .name = "enable_vlan4k",
1260                 .description = "Enable VLAN 4K mode",
1261                 .set = rtl8366_sw_set_vlan_enable,
1262                 .get = rtl8366_sw_get_vlan_enable,
1263                 .max = 1,
1264                 .ofs = 2
1265         }, {
1266                 .type = SWITCH_TYPE_NOVAL,
1267                 .name = "reset_mibs",
1268                 .description = "Reset all MIB counters",
1269                 .set = rtl8367b_sw_reset_mibs,
1270         }, {
1271                 .type = SWITCH_TYPE_INT,
1272                 .name = "max_length",
1273                 .description = "Get/Set the maximum length of valid packets"
1274                                "(0:1522, 1:1536, 2:1552, 3:16000)",
1275                 .set = rtl8367b_sw_set_max_length,
1276                 .get = rtl8367b_sw_get_max_length,
1277                 .max = 3,
1278         }
1279 };
1280
1281 static struct switch_attr rtl8367b_port[] = {
1282         {
1283                 .type = SWITCH_TYPE_NOVAL,
1284                 .name = "reset_mib",
1285                 .description = "Reset single port MIB counters",
1286                 .set = rtl8367b_sw_reset_port_mibs,
1287         }, {
1288                 .type = SWITCH_TYPE_STRING,
1289                 .name = "mib",
1290                 .description = "Get MIB counters for port",
1291                 .max = 33,
1292                 .set = NULL,
1293                 .get = rtl8366_sw_get_port_mib,
1294         },
1295 };
1296
1297 static struct switch_attr rtl8367b_vlan[] = {
1298         {
1299                 .type = SWITCH_TYPE_STRING,
1300                 .name = "info",
1301                 .description = "Get vlan information",
1302                 .max = 1,
1303                 .set = NULL,
1304                 .get = rtl8366_sw_get_vlan_info,
1305         },
1306 };
1307
1308 static const struct switch_dev_ops rtl8367b_sw_ops = {
1309         .attr_global = {
1310                 .attr = rtl8367b_globals,
1311                 .n_attr = ARRAY_SIZE(rtl8367b_globals),
1312         },
1313         .attr_port = {
1314                 .attr = rtl8367b_port,
1315                 .n_attr = ARRAY_SIZE(rtl8367b_port),
1316         },
1317         .attr_vlan = {
1318                 .attr = rtl8367b_vlan,
1319                 .n_attr = ARRAY_SIZE(rtl8367b_vlan),
1320         },
1321
1322         .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1323         .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1324         .get_port_pvid = rtl8366_sw_get_port_pvid,
1325         .set_port_pvid = rtl8366_sw_set_port_pvid,
1326         .reset_switch = rtl8366_sw_reset_switch,
1327         .get_port_link = rtl8367b_sw_get_port_link,
1328 };
1329
1330 static int rtl8367b_switch_init(struct rtl8366_smi *smi)
1331 {
1332         struct switch_dev *dev = &smi->sw_dev;
1333         int err;
1334
1335         dev->name = "RTL8367B";
1336         dev->cpu_port = RTL8367B_CPU_PORT_NUM;
1337         dev->ports = RTL8367B_NUM_PORTS;
1338         dev->vlans = RTL8367B_NUM_VIDS;
1339         dev->ops = &rtl8367b_sw_ops;
1340         dev->alias = dev_name(smi->parent);
1341
1342         err = register_switch(dev, NULL);
1343         if (err)
1344                 dev_err(smi->parent, "switch registration failed\n");
1345
1346         return err;
1347 }
1348
1349 static void rtl8367b_switch_cleanup(struct rtl8366_smi *smi)
1350 {
1351         unregister_switch(&smi->sw_dev);
1352 }
1353
1354 static int rtl8367b_mii_read(struct mii_bus *bus, int addr, int reg)
1355 {
1356         struct rtl8366_smi *smi = bus->priv;
1357         u32 val = 0;
1358         int err;
1359
1360         err = rtl8367b_read_phy_reg(smi, addr, reg, &val);
1361         if (err)
1362                 return 0xffff;
1363
1364         return val;
1365 }
1366
1367 static int rtl8367b_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1368 {
1369         struct rtl8366_smi *smi = bus->priv;
1370         u32 t;
1371         int err;
1372
1373         err = rtl8367b_write_phy_reg(smi, addr, reg, val);
1374         if (err)
1375                 return err;
1376
1377         /* flush write */
1378         (void) rtl8367b_read_phy_reg(smi, addr, reg, &t);
1379
1380         return err;
1381 }
1382
1383 static int __devinit rtl8367b_detect(struct rtl8366_smi *smi)
1384 {
1385         const char *chip_name;
1386         u32 chip_num;
1387         u32 chip_ver;
1388         u32 chip_mode;
1389         int ret;
1390
1391         /* TODO: improve chip detection */
1392         rtl8366_smi_write_reg(smi, RTL8367B_RTL_MAGIC_ID_REG,
1393                               RTL8367B_RTL_MAGIC_ID_VAL);
1394
1395         ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_NUMBER_REG, &chip_num);
1396         if (ret) {
1397                 dev_err(smi->parent, "unable to read %s register\n",
1398                         "chip number");
1399                 return ret;
1400         }
1401
1402         ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_VER_REG, &chip_ver);
1403         if (ret) {
1404                 dev_err(smi->parent, "unable to read %s register\n",
1405                         "chip version");
1406                 return ret;
1407         }
1408
1409         ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_MODE_REG, &chip_mode);
1410         if (ret) {
1411                 dev_err(smi->parent, "unable to read %s register\n",
1412                         "chip mode");
1413                 return ret;
1414         }
1415
1416         switch (chip_ver) {
1417         case 0x1000:
1418                 chip_name = "8367RB";
1419                 break;
1420         case 0x1010:
1421                 chip_name = "8367R-VB";
1422                 break;
1423         default:
1424                 dev_err(smi->parent,
1425                         "unknown chip num:%04x ver:%04x, mode:%04x\n",
1426                         chip_num, chip_ver, chip_mode);
1427                 return -ENODEV;
1428         }
1429
1430         dev_info(smi->parent, "RTL%s chip found\n", chip_name);
1431
1432         return 0;
1433 }
1434
1435 static struct rtl8366_smi_ops rtl8367b_smi_ops = {
1436         .detect         = rtl8367b_detect,
1437         .reset_chip     = rtl8367b_reset_chip,
1438         .setup          = rtl8367b_setup,
1439
1440         .mii_read       = rtl8367b_mii_read,
1441         .mii_write      = rtl8367b_mii_write,
1442
1443         .get_vlan_mc    = rtl8367b_get_vlan_mc,
1444         .set_vlan_mc    = rtl8367b_set_vlan_mc,
1445         .get_vlan_4k    = rtl8367b_get_vlan_4k,
1446         .set_vlan_4k    = rtl8367b_set_vlan_4k,
1447         .get_mc_index   = rtl8367b_get_mc_index,
1448         .set_mc_index   = rtl8367b_set_mc_index,
1449         .get_mib_counter = rtl8367b_get_mib_counter,
1450         .is_vlan_valid  = rtl8367b_is_vlan_valid,
1451         .enable_vlan    = rtl8367b_enable_vlan,
1452         .enable_vlan4k  = rtl8367b_enable_vlan4k,
1453         .enable_port    = rtl8367b_enable_port,
1454 };
1455
1456 static int __devinit rtl8367b_probe(struct platform_device *pdev)
1457 {
1458         struct rtl8367_platform_data *pdata;
1459         struct rtl8366_smi *smi;
1460         int err;
1461
1462         smi = rtl8366_smi_probe(pdev);
1463         if (!smi)
1464                 return -ENODEV;
1465
1466         smi->clk_delay = 1500;
1467         smi->cmd_read = 0xb9;
1468         smi->cmd_write = 0xb8;
1469         smi->ops = &rtl8367b_smi_ops;
1470         smi->cpu_port = RTL8367B_CPU_PORT_NUM;
1471         smi->num_ports = RTL8367B_NUM_PORTS;
1472         smi->num_vlan_mc = RTL8367B_NUM_VLANS;
1473         smi->mib_counters = rtl8367b_mib_counters;
1474         smi->num_mib_counters = ARRAY_SIZE(rtl8367b_mib_counters);
1475
1476         err = rtl8366_smi_init(smi);
1477         if (err)
1478                 goto err_free_smi;
1479
1480         platform_set_drvdata(pdev, smi);
1481
1482         err = rtl8367b_switch_init(smi);
1483         if (err)
1484                 goto err_clear_drvdata;
1485
1486         return 0;
1487
1488  err_clear_drvdata:
1489         platform_set_drvdata(pdev, NULL);
1490         rtl8366_smi_cleanup(smi);
1491  err_free_smi:
1492         kfree(smi);
1493  err_out:
1494         return err;
1495 }
1496
1497 static int __devexit rtl8367b_remove(struct platform_device *pdev)
1498 {
1499         struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1500
1501         if (smi) {
1502                 rtl8367b_switch_cleanup(smi);
1503                 platform_set_drvdata(pdev, NULL);
1504                 rtl8366_smi_cleanup(smi);
1505                 kfree(smi);
1506         }
1507
1508         return 0;
1509 }
1510
1511 static void rtl8367b_shutdown(struct platform_device *pdev)
1512 {
1513         struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1514
1515         if (smi)
1516                 rtl8367b_reset_chip(smi);
1517 }
1518
1519 #ifdef CONFIG_OF
1520 static const struct of_device_id rtl8367b_match[] = {
1521         { .compatible = "rtl8367b" },
1522         {},
1523 };
1524 MODULE_DEVICE_TABLE(of, rtl8367b_match);
1525 #endif
1526
1527 static struct platform_driver rtl8367b_driver = {
1528         .driver = {
1529                 .name           = RTL8367B_DRIVER_NAME,
1530                 .owner          = THIS_MODULE,
1531                 .of_match_table = of_match_ptr(rtl8367b_match),
1532         },
1533         .probe          = rtl8367b_probe,
1534         .remove         = __devexit_p(rtl8367b_remove),
1535         .shutdown       = rtl8367b_shutdown,
1536 };
1537
1538 module_platform_driver(rtl8367b_driver);
1539
1540 MODULE_DESCRIPTION(RTL8367B_DRIVER_DESC);
1541 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1542 MODULE_LICENSE("GPL v2");
1543 MODULE_ALIAS("platform:" RTL8367B_DRIVER_NAME);
1544