target/linux/generic/files/drivers/net/phy/rtl8366s.c

   1 /*
   2  * Platform driver for the Realtek RTL8366S ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/device.h>
  16 #include <linux/of.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/delay.h>
  19 #include <linux/skbuff.h>
  20 #include <linux/rtl8366.h>
  21
  22 #include "rtl8366_smi.h"
  23
  24 #define RTL8366S_DRIVER_DESC    "Realtek RTL8366S ethernet switch driver"
  25 #define RTL8366S_DRIVER_VER     "0.2.2"
  26
  27 #define RTL8366S_PHY_NO_MAX     4
  28 #define RTL8366S_PHY_PAGE_MAX   7
  29 #define RTL8366S_PHY_ADDR_MAX   31
  30
  31 /* Switch Global Configuration register */
  32 #define RTL8366S_SGCR                           0x0000
  33 #define RTL8366S_SGCR_EN_BC_STORM_CTRL          BIT(0)
  34 #define RTL8366S_SGCR_MAX_LENGTH(_x)            (_x << 4)
  35 #define RTL8366S_SGCR_MAX_LENGTH_MASK           RTL8366S_SGCR_MAX_LENGTH(0x3)
  36 #define RTL8366S_SGCR_MAX_LENGTH_1522           RTL8366S_SGCR_MAX_LENGTH(0x0)
  37 #define RTL8366S_SGCR_MAX_LENGTH_1536           RTL8366S_SGCR_MAX_LENGTH(0x1)
  38 #define RTL8366S_SGCR_MAX_LENGTH_1552           RTL8366S_SGCR_MAX_LENGTH(0x2)
  39 #define RTL8366S_SGCR_MAX_LENGTH_16000          RTL8366S_SGCR_MAX_LENGTH(0x3)
  40 #define RTL8366S_SGCR_EN_VLAN                   BIT(13)
  41
  42 /* Port Enable Control register */
  43 #define RTL8366S_PECR                           0x0001
  44
  45 /* Switch Security Control registers */
  46 #define RTL8366S_SSCR0                          0x0002
  47 #define RTL8366S_SSCR1                          0x0003
  48 #define RTL8366S_SSCR2                          0x0004
  49 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA          BIT(0)
  50
  51 #define RTL8366S_RESET_CTRL_REG                 0x0100
  52 #define RTL8366S_CHIP_CTRL_RESET_HW             1
  53 #define RTL8366S_CHIP_CTRL_RESET_SW             (1 << 1)
  54
  55 #define RTL8366S_CHIP_VERSION_CTRL_REG          0x0104
  56 #define RTL8366S_CHIP_VERSION_MASK              0xf
  57 #define RTL8366S_CHIP_ID_REG                    0x0105
  58 #define RTL8366S_CHIP_ID_8366                   0x8366
  59
  60 /* PHY registers control */
  61 #define RTL8366S_PHY_ACCESS_CTRL_REG            0x8028
  62 #define RTL8366S_PHY_ACCESS_DATA_REG            0x8029
  63
  64 #define RTL8366S_PHY_CTRL_READ                  1
  65 #define RTL8366S_PHY_CTRL_WRITE                 0
  66
  67 #define RTL8366S_PHY_REG_MASK                   0x1f
  68 #define RTL8366S_PHY_PAGE_OFFSET                5
  69 #define RTL8366S_PHY_PAGE_MASK                  (0x7 << 5)
  70 #define RTL8366S_PHY_NO_OFFSET                  9
  71 #define RTL8366S_PHY_NO_MASK                    (0x1f << 9)
  72
  73 /* LED control registers */
  74 #define RTL8366S_LED_BLINKRATE_REG              0x0420
  75 #define RTL8366S_LED_BLINKRATE_BIT              0
  76 #define RTL8366S_LED_BLINKRATE_MASK             0x0007
  77
  78 #define RTL8366S_LED_CTRL_REG                   0x0421
  79 #define RTL8366S_LED_0_1_CTRL_REG               0x0422
  80 #define RTL8366S_LED_2_3_CTRL_REG               0x0423
  81
  82 #define RTL8366S_MIB_COUNT                      33
  83 #define RTL8366S_GLOBAL_MIB_COUNT               1
  84 #define RTL8366S_MIB_COUNTER_PORT_OFFSET        0x0040
  85 #define RTL8366S_MIB_COUNTER_BASE               0x1000
  86 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2       0x0008
  87 #define RTL8366S_MIB_COUNTER_BASE2              0x1180
  88 #define RTL8366S_MIB_CTRL_REG                   0x11F0
  89 #define RTL8366S_MIB_CTRL_USER_MASK             0x01FF
  90 #define RTL8366S_MIB_CTRL_BUSY_MASK             0x0001
  91 #define RTL8366S_MIB_CTRL_RESET_MASK            0x0002
  92
  93 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK     0x0004
  94 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT        0x0003
  95 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK       0x01FC
  96
  97
  98 #define RTL8366S_PORT_VLAN_CTRL_BASE            0x0058
  99 #define RTL8366S_PORT_VLAN_CTRL_REG(_p)  \
 100                 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
 101 #define RTL8366S_PORT_VLAN_CTRL_MASK            0xf
 102 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p)       (4 * ((_p) % 4))
 103
 104
 105 #define RTL8366S_VLAN_TABLE_READ_BASE           0x018B
 106 #define RTL8366S_VLAN_TABLE_WRITE_BASE          0x0185
 107
 108 #define RTL8366S_VLAN_TB_CTRL_REG               0x010F
 109
 110 #define RTL8366S_TABLE_ACCESS_CTRL_REG          0x0180
 111 #define RTL8366S_TABLE_VLAN_READ_CTRL           0x0E01
 112 #define RTL8366S_TABLE_VLAN_WRITE_CTRL          0x0F01
 113
 114 #define RTL8366S_VLAN_MC_BASE(_x)               (0x0016 + (_x) * 2)
 115
 116 #define RTL8366S_VLAN_MEMBERINGRESS_REG         0x0379
 117
 118 #define RTL8366S_PORT_LINK_STATUS_BASE          0x0060
 119 #define RTL8366S_PORT_STATUS_SPEED_MASK         0x0003
 120 #define RTL8366S_PORT_STATUS_DUPLEX_MASK        0x0004
 121 #define RTL8366S_PORT_STATUS_LINK_MASK          0x0010
 122 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK       0x0020
 123 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK       0x0040
 124 #define RTL8366S_PORT_STATUS_AN_MASK            0x0080
 125
 126
 127 #define RTL8366S_PORT_NUM_CPU           5
 128 #define RTL8366S_NUM_PORTS              6
 129 #define RTL8366S_NUM_VLANS              16
 130 #define RTL8366S_NUM_LEDGROUPS          4
 131 #define RTL8366S_NUM_VIDS               4096
 132 #define RTL8366S_PRIORITYMAX            7
 133 #define RTL8366S_FIDMAX                 7
 134
 135
 136 #define RTL8366S_PORT_1                 (1 << 0) /* In userspace port 0 */
 137 #define RTL8366S_PORT_2                 (1 << 1) /* In userspace port 1 */
 138 #define RTL8366S_PORT_3                 (1 << 2) /* In userspace port 2 */
 139 #define RTL8366S_PORT_4                 (1 << 3) /* In userspace port 3 */
 140
 141 #define RTL8366S_PORT_UNKNOWN           (1 << 4) /* No known connection */
 142 #define RTL8366S_PORT_CPU               (1 << 5) /* CPU port */
 143
 144 #define RTL8366S_PORT_ALL               (RTL8366S_PORT_1 |      \
 145                                          RTL8366S_PORT_2 |      \
 146                                          RTL8366S_PORT_3 |      \
 147                                          RTL8366S_PORT_4 |      \
 148                                          RTL8366S_PORT_UNKNOWN | \
 149                                          RTL8366S_PORT_CPU)
 150
 151 #define RTL8366S_PORT_ALL_BUT_CPU       (RTL8366S_PORT_1 |      \
 152                                          RTL8366S_PORT_2 |      \
 153                                          RTL8366S_PORT_3 |      \
 154                                          RTL8366S_PORT_4 |      \
 155                                          RTL8366S_PORT_UNKNOWN)
 156
 157 #define RTL8366S_PORT_ALL_EXTERNAL      (RTL8366S_PORT_1 |      \
 158                                          RTL8366S_PORT_2 |      \
 159                                          RTL8366S_PORT_3 |      \
 160                                          RTL8366S_PORT_4)
 161
 162 #define RTL8366S_PORT_ALL_INTERNAL      (RTL8366S_PORT_UNKNOWN | \
 163                                          RTL8366S_PORT_CPU)
 164
 165 #define RTL8366S_VLAN_VID_MASK          0xfff
 166 #define RTL8366S_VLAN_PRIORITY_SHIFT    12
 167 #define RTL8366S_VLAN_PRIORITY_MASK     0x7
 168 #define RTL8366S_VLAN_MEMBER_MASK       0x3f
 169 #define RTL8366S_VLAN_UNTAG_SHIFT       6
 170 #define RTL8366S_VLAN_UNTAG_MASK        0x3f
 171 #define RTL8366S_VLAN_FID_SHIFT         12
 172 #define RTL8366S_VLAN_FID_MASK          0x7
 173
 174 static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
 175         { 0,  0, 4, "IfInOctets"                                },
 176         { 0,  4, 4, "EtherStatsOctets"                          },
 177         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 178         { 0, 10, 2, "EtherFragments"                            },
 179         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 180         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 181         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 182         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 183         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 184         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 185         { 0, 24, 2, "EtherOversizeStats"                        },
 186         { 0, 26, 2, "EtherStatsJabbers"                         },
 187         { 0, 28, 2, "IfInUcastPkts"                             },
 188         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 189         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 190         { 0, 34, 2, "EtherStatsDropEvents"                      },
 191         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 192         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 193         { 0, 40, 2, "Dot3InPauseFrames"                         },
 194         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 195         { 0, 44, 4, "IfOutOctets"                               },
 196         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 197         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 198         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 199         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 200         { 0, 56, 2, "EtherStatsCollisions"                      },
 201         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 202         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 203         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 204
 205         /*
 206          * The following counters are accessible at a different
 207          * base address.
 208          */
 209         { 1,  0, 2, "Dot1dTpPortInDiscards"                     },
 210         { 1,  2, 2, "IfOutUcastPkts"                            },
 211         { 1,  4, 2, "IfOutMulticastPkts"                        },
 212         { 1,  6, 2, "IfOutBroadcastPkts"                        },
 213 };
 214
 215 #define REG_WR(_smi, _reg, _val)                                        \
 216         do {                                                            \
 217                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 218                 if (err)                                                \
 219                         return err;                                     \
 220         } while (0)
 221
 222 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 223         do {                                                            \
 224                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 225                 if (err)                                                \
 226                         return err;                                     \
 227         } while (0)
 228
 229 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
 230 {
 231         int timeout = 10;
 232         u32 data;
 233
 234         rtl8366_smi_write_reg_noack(smi, RTL8366S_RESET_CTRL_REG,
 235                                     RTL8366S_CHIP_CTRL_RESET_HW);
 236         do {
 237                 msleep(1);
 238                 if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
 239                         return -EIO;
 240
 241                 if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
 242                         break;
 243         } while (--timeout);
 244
 245         if (!timeout) {
 246                 printk("Timeout waiting for the switch to reset\n");
 247                 return -EIO;
 248         }
 249
 250         return 0;
 251 }
 252
 253 static int rtl8366s_setup(struct rtl8366_smi *smi)
 254 {
 255         struct rtl8366_platform_data *pdata;
 256         int err;
 257
 258         pdata = smi->parent->platform_data;
 259         if (pdata->num_initvals && pdata->initvals) {
 260                 unsigned i;
 261
 262                 dev_info(smi->parent, "applying initvals\n");
 263                 for (i = 0; i < pdata->num_initvals; i++)
 264                         REG_WR(smi, pdata->initvals[i].reg,
 265                                pdata->initvals[i].val);
 266         }
 267
 268         /* set maximum packet length to 1536 bytes */
 269         REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
 270                 RTL8366S_SGCR_MAX_LENGTH_1536);
 271
 272         /* enable learning for all ports */
 273         REG_WR(smi, RTL8366S_SSCR0, 0);
 274
 275         /* enable auto ageing for all ports */
 276         REG_WR(smi, RTL8366S_SSCR1, 0);
 277
 278         /*
 279          * discard VLAN tagged packets if the port is not a member of
 280          * the VLAN with which the packets is associated.
 281          */
 282         REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL);
 283
 284         /* don't drop packets whose DA has not been learned */
 285         REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
 286
 287         return 0;
 288 }
 289
 290 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
 291                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 292 {
 293         u32 reg;
 294         int ret;
 295
 296         if (phy_no > RTL8366S_PHY_NO_MAX)
 297                 return -EINVAL;
 298
 299         if (page > RTL8366S_PHY_PAGE_MAX)
 300                 return -EINVAL;
 301
 302         if (addr > RTL8366S_PHY_ADDR_MAX)
 303                 return -EINVAL;
 304
 305         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 306                                     RTL8366S_PHY_CTRL_READ);
 307         if (ret)
 308                 return ret;
 309
 310         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 311               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 312               (addr & RTL8366S_PHY_REG_MASK);
 313
 314         ret = rtl8366_smi_write_reg(smi, reg, 0);
 315         if (ret)
 316                 return ret;
 317
 318         ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
 319         if (ret)
 320                 return ret;
 321
 322         return 0;
 323 }
 324
 325 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
 326                                   u32 phy_no, u32 page, u32 addr, u32 data)
 327 {
 328         u32 reg;
 329         int ret;
 330
 331         if (phy_no > RTL8366S_PHY_NO_MAX)
 332                 return -EINVAL;
 333
 334         if (page > RTL8366S_PHY_PAGE_MAX)
 335                 return -EINVAL;
 336
 337         if (addr > RTL8366S_PHY_ADDR_MAX)
 338                 return -EINVAL;
 339
 340         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 341                                     RTL8366S_PHY_CTRL_WRITE);
 342         if (ret)
 343                 return ret;
 344
 345         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 346               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 347               (addr & RTL8366S_PHY_REG_MASK);
 348
 349         ret = rtl8366_smi_write_reg(smi, reg, data);
 350         if (ret)
 351                 return ret;
 352
 353         return 0;
 354 }
 355
 356 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
 357                                    int port, unsigned long long *val)
 358 {
 359         int i;
 360         int err;
 361         u32 addr, data;
 362         u64 mibvalue;
 363
 364         if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
 365                 return -EINVAL;
 366
 367         switch (rtl8366s_mib_counters[counter].base) {
 368         case 0:
 369                 addr = RTL8366S_MIB_COUNTER_BASE +
 370                        RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
 371                 break;
 372
 373         case 1:
 374                 addr = RTL8366S_MIB_COUNTER_BASE2 +
 375                         RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
 376                 break;
 377
 378         default:
 379                 return -EINVAL;
 380         }
 381
 382         addr += rtl8366s_mib_counters[counter].offset;
 383
 384         /*
 385          * Writing access counter address first
 386          * then ASIC will prepare 64bits counter wait for being retrived
 387          */
 388         data = 0; /* writing data will be discard by ASIC */
 389         err = rtl8366_smi_write_reg(smi, addr, data);
 390         if (err)
 391                 return err;
 392
 393         /* read MIB control register */
 394         err =  rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
 395         if (err)
 396                 return err;
 397
 398         if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
 399                 return -EBUSY;
 400
 401         if (data & RTL8366S_MIB_CTRL_RESET_MASK)
 402                 return -EIO;
 403
 404         mibvalue = 0;
 405         for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
 406                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 407                 if (err)
 408                         return err;
 409
 410                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 411         }
 412
 413         *val = mibvalue;
 414         return 0;
 415 }
 416
 417 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 418                                 struct rtl8366_vlan_4k *vlan4k)
 419 {
 420         u32 data[2];
 421         int err;
 422         int i;
 423
 424         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 425
 426         if (vid >= RTL8366S_NUM_VIDS)
 427                 return -EINVAL;
 428
 429         /* write VID */
 430         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE,
 431                                     vid & RTL8366S_VLAN_VID_MASK);
 432         if (err)
 433                 return err;
 434
 435         /* write table access control word */
 436         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 437                                     RTL8366S_TABLE_VLAN_READ_CTRL);
 438         if (err)
 439                 return err;
 440
 441         for (i = 0; i < 2; i++) {
 442                 err = rtl8366_smi_read_reg(smi,
 443                                            RTL8366S_VLAN_TABLE_READ_BASE + i,
 444                                            &data[i]);
 445                 if (err)
 446                         return err;
 447         }
 448
 449         vlan4k->vid = vid;
 450         vlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
 451                         RTL8366S_VLAN_UNTAG_MASK;
 452         vlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
 453         vlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
 454                         RTL8366S_VLAN_FID_MASK;
 455
 456         return 0;
 457 }
 458
 459 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
 460                                 const struct rtl8366_vlan_4k *vlan4k)
 461 {
 462         u32 data[2];
 463         int err;
 464         int i;
 465
 466         if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
 467             vlan4k->member > RTL8366S_VLAN_MEMBER_MASK ||
 468             vlan4k->untag > RTL8366S_VLAN_UNTAG_MASK ||
 469             vlan4k->fid > RTL8366S_FIDMAX)
 470                 return -EINVAL;
 471
 472         data[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK;
 473         data[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) |
 474                   ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) <<
 475                         RTL8366S_VLAN_UNTAG_SHIFT) |
 476                   ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) <<
 477                         RTL8366S_VLAN_FID_SHIFT);
 478
 479         for (i = 0; i < 2; i++) {
 480                 err = rtl8366_smi_write_reg(smi,
 481                                             RTL8366S_VLAN_TABLE_WRITE_BASE + i,
 482                                             data[i]);
 483                 if (err)
 484                         return err;
 485         }
 486
 487         /* write table access control word */
 488         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 489                                     RTL8366S_TABLE_VLAN_WRITE_CTRL);
 490
 491         return err;
 492 }
 493
 494 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 495                                 struct rtl8366_vlan_mc *vlanmc)
 496 {
 497         u32 data[2];
 498         int err;
 499         int i;
 500
 501         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 502
 503         if (index >= RTL8366S_NUM_VLANS)
 504                 return -EINVAL;
 505
 506         for (i = 0; i < 2; i++) {
 507                 err = rtl8366_smi_read_reg(smi,
 508                                            RTL8366S_VLAN_MC_BASE(index) + i,
 509                                            &data[i]);
 510                 if (err)
 511                         return err;
 512         }
 513
 514         vlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK;
 515         vlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) &
 516                            RTL8366S_VLAN_PRIORITY_MASK;
 517         vlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
 518                         RTL8366S_VLAN_UNTAG_MASK;
 519         vlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
 520         vlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
 521                       RTL8366S_VLAN_FID_MASK;
 522
 523         return 0;
 524 }
 525
 526 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 527                                 const struct rtl8366_vlan_mc *vlanmc)
 528 {
 529         u32 data[2];
 530         int err;
 531         int i;
 532
 533         if (index >= RTL8366S_NUM_VLANS ||
 534             vlanmc->vid >= RTL8366S_NUM_VIDS ||
 535             vlanmc->priority > RTL8366S_PRIORITYMAX ||
 536             vlanmc->member > RTL8366S_VLAN_MEMBER_MASK ||
 537             vlanmc->untag > RTL8366S_VLAN_UNTAG_MASK ||
 538             vlanmc->fid > RTL8366S_FIDMAX)
 539                 return -EINVAL;
 540
 541         data[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) |
 542                   ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) <<
 543                         RTL8366S_VLAN_PRIORITY_SHIFT);
 544         data[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) |
 545                   ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) <<
 546                         RTL8366S_VLAN_UNTAG_SHIFT) |
 547                   ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) <<
 548                         RTL8366S_VLAN_FID_SHIFT);
 549
 550         for (i = 0; i < 2; i++) {
 551                 err = rtl8366_smi_write_reg(smi,
 552                                             RTL8366S_VLAN_MC_BASE(index) + i,
 553                                             data[i]);
 554                 if (err)
 555                         return err;
 556         }
 557
 558         return 0;
 559 }
 560
 561 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 562 {
 563         u32 data;
 564         int err;
 565
 566         if (port >= RTL8366S_NUM_PORTS)
 567                 return -EINVAL;
 568
 569         err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 570                                    &data);
 571         if (err)
 572                 return err;
 573
 574         *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
 575                RTL8366S_PORT_VLAN_CTRL_MASK;
 576
 577         return 0;
 578 }
 579
 580 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 581 {
 582         if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
 583                 return -EINVAL;
 584
 585         return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 586                                 RTL8366S_PORT_VLAN_CTRL_MASK <<
 587                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
 588                                 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
 589                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
 590 }
 591
 592 static int rtl8366s_enable_vlan(struct rtl8366_smi *smi, int enable)
 593 {
 594         return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,
 595                                 (enable) ? RTL8366S_SGCR_EN_VLAN : 0);
 596 }
 597
 598 static int rtl8366s_enable_vlan4k(struct rtl8366_smi *smi, int enable)
 599 {
 600         return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
 601                                 1, (enable) ? 1 : 0);
 602 }
 603
 604 static int rtl8366s_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
 605 {
 606         unsigned max = RTL8366S_NUM_VLANS;
 607
 608         if (smi->vlan4k_enabled)
 609                 max = RTL8366S_NUM_VIDS - 1;
 610
 611         if (vlan == 0 || vlan >= max)
 612                 return 0;
 613
 614         return 1;
 615 }
 616
 617 static int rtl8366s_enable_port(struct rtl8366_smi *smi, int port, int enable)
 618 {
 619         return rtl8366_smi_rmwr(smi, RTL8366S_PECR, (1 << port),
 620                                 (enable) ? 0 : (1 << port));
 621 }
 622
 623 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
 624                                   const struct switch_attr *attr,
 625                                   struct switch_val *val)
 626 {
 627         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 628
 629         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
 630 }
 631
 632 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
 633                                      const struct switch_attr *attr,
 634                                      struct switch_val *val)
 635 {
 636         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 637         u32 data;
 638
 639         rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
 640
 641         val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
 642
 643         return 0;
 644 }
 645
 646 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
 647                                     const struct switch_attr *attr,
 648                                     struct switch_val *val)
 649 {
 650         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 651
 652         if (val->value.i >= 6)
 653                 return -EINVAL;
 654
 655         return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
 656                                 RTL8366S_LED_BLINKRATE_MASK,
 657                                 val->value.i);
 658 }
 659
 660 static int rtl8366s_sw_get_max_length(struct switch_dev *dev,
 661                                         const struct switch_attr *attr,
 662                                         struct switch_val *val)
 663 {
 664         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 665         u32 data;
 666
 667         rtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data);
 668
 669         val->value.i = ((data & (RTL8366S_SGCR_MAX_LENGTH_MASK)) >> 4);
 670
 671         return 0;
 672 }
 673
 674 static int rtl8366s_sw_set_max_length(struct switch_dev *dev,
 675                                         const struct switch_attr *attr,
 676                                         struct switch_val *val)
 677 {
 678         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 679         char length_code;
 680
 681         switch (val->value.i) {
 682                 case 0:
 683                         length_code = RTL8366S_SGCR_MAX_LENGTH_1522;
 684                         break;
 685                 case 1:
 686                         length_code = RTL8366S_SGCR_MAX_LENGTH_1536;
 687                         break;
 688                 case 2:
 689                         length_code = RTL8366S_SGCR_MAX_LENGTH_1552;
 690                         break;
 691                 case 3:
 692                         length_code = RTL8366S_SGCR_MAX_LENGTH_16000;
 693                         break;
 694                 default:
 695                         return -EINVAL;
 696         }
 697
 698         return rtl8366_smi_rmwr(smi, RTL8366S_SGCR,
 699                         RTL8366S_SGCR_MAX_LENGTH_MASK,
 700                         length_code);
 701 }
 702
 703 static int rtl8366s_sw_get_learning_enable(struct switch_dev *dev,
 704                                            const struct switch_attr *attr,
 705                                            struct switch_val *val)
 706 {
 707         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 708         u32 data;
 709
 710         rtl8366_smi_read_reg(smi,RTL8366S_SSCR0, &data);
 711         val->value.i = !data;
 712
 713         return 0;
 714 }
 715
 716
 717 static int rtl8366s_sw_set_learning_enable(struct switch_dev *dev,
 718                                            const struct switch_attr *attr,
 719                                            struct switch_val *val)
 720 {
 721         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 722         u32 portmask = 0;
 723         int err = 0;
 724
 725         if (!val->value.i)
 726                 portmask = RTL8366S_PORT_ALL;
 727
 728         /* set learning for all ports */
 729         REG_WR(smi, RTL8366S_SSCR0, portmask);
 730
 731         /* set auto ageing for all ports */
 732         REG_WR(smi, RTL8366S_SSCR1, portmask);
 733
 734         return 0;
 735 }
 736
 737 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
 738                                      int port,
 739                                      struct switch_port_link *link)
 740 {
 741         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 742         u32 data = 0;
 743         u32 speed;
 744
 745         if (port >= RTL8366S_NUM_PORTS)
 746                 return -EINVAL;
 747
 748         rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE + (port / 2),
 749                              &data);
 750
 751         if (port % 2)
 752                 data = data >> 8;
 753
 754         link->link = !!(data & RTL8366S_PORT_STATUS_LINK_MASK);
 755         if (!link->link)
 756                 return 0;
 757
 758         link->duplex = !!(data & RTL8366S_PORT_STATUS_DUPLEX_MASK);
 759         link->rx_flow = !!(data & RTL8366S_PORT_STATUS_RXPAUSE_MASK);
 760         link->tx_flow = !!(data & RTL8366S_PORT_STATUS_TXPAUSE_MASK);
 761         link->aneg = !!(data & RTL8366S_PORT_STATUS_AN_MASK);
 762
 763         speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);
 764         switch (speed) {
 765         case 0:
 766                 link->speed = SWITCH_PORT_SPEED_10;
 767                 break;
 768         case 1:
 769                 link->speed = SWITCH_PORT_SPEED_100;
 770                 break;
 771         case 2:
 772                 link->speed = SWITCH_PORT_SPEED_1000;
 773                 break;
 774         default:
 775                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 776                 break;
 777         }
 778
 779         return 0;
 780 }
 781
 782 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
 783                                     const struct switch_attr *attr,
 784                                     struct switch_val *val)
 785 {
 786         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 787         u32 data;
 788         u32 mask;
 789         u32 reg;
 790
 791         if (val->port_vlan >= RTL8366S_NUM_PORTS ||
 792             (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
 793                 return -EINVAL;
 794
 795         if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
 796                 reg = RTL8366S_LED_BLINKRATE_REG;
 797                 mask = 0xF << 4;
 798                 data = val->value.i << 4;
 799         } else {
 800                 reg = RTL8366S_LED_CTRL_REG;
 801                 mask = 0xF << (val->port_vlan * 4),
 802                 data = val->value.i << (val->port_vlan * 4);
 803         }
 804
 805         return rtl8366_smi_rmwr(smi, reg, mask, data);
 806 }
 807
 808 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
 809                                     const struct switch_attr *attr,
 810                                     struct switch_val *val)
 811 {
 812         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 813         u32 data = 0;
 814
 815         if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
 816                 return -EINVAL;
 817
 818         rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
 819         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 820
 821         return 0;
 822 }
 823
 824 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
 825                                        const struct switch_attr *attr,
 826                                        struct switch_val *val)
 827 {
 828         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 829
 830         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 831                 return -EINVAL;
 832
 833
 834         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
 835                                 0, (1 << (val->port_vlan + 3)));
 836 }
 837
 838 static struct switch_attr rtl8366s_globals[] = {
 839         {
 840                 .type = SWITCH_TYPE_INT,
 841                 .name = "enable_learning",
 842                 .description = "Enable learning, enable aging",
 843                 .set = rtl8366s_sw_set_learning_enable,
 844                 .get = rtl8366s_sw_get_learning_enable,
 845                 .max = 1,
 846         }, {
 847                 .type = SWITCH_TYPE_INT,
 848                 .name = "enable_vlan",
 849                 .description = "Enable VLAN mode",
 850                 .set = rtl8366_sw_set_vlan_enable,
 851                 .get = rtl8366_sw_get_vlan_enable,
 852                 .max = 1,
 853                 .ofs = 1
 854         }, {
 855                 .type = SWITCH_TYPE_INT,
 856                 .name = "enable_vlan4k",
 857                 .description = "Enable VLAN 4K mode",
 858                 .set = rtl8366_sw_set_vlan_enable,
 859                 .get = rtl8366_sw_get_vlan_enable,
 860                 .max = 1,
 861                 .ofs = 2
 862         }, {
 863                 .type = SWITCH_TYPE_NOVAL,
 864                 .name = "reset_mibs",
 865                 .description = "Reset all MIB counters",
 866                 .set = rtl8366s_sw_reset_mibs,
 867         }, {
 868                 .type = SWITCH_TYPE_INT,
 869                 .name = "blinkrate",
 870                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
 871                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
 872                 .set = rtl8366s_sw_set_blinkrate,
 873                 .get = rtl8366s_sw_get_blinkrate,
 874                 .max = 5
 875         }, {
 876                 .type = SWITCH_TYPE_INT,
 877                 .name = "max_length",
 878                 .description = "Get/Set the maximum length of valid packets"
 879                 " (0 = 1522, 1 = 1536, 2 = 1552, 3 = 16000 (9216?))",
 880                 .set = rtl8366s_sw_set_max_length,
 881                 .get = rtl8366s_sw_get_max_length,
 882                 .max = 3,
 883         },
 884 };
 885
 886 static struct switch_attr rtl8366s_port[] = {
 887         {
 888                 .type = SWITCH_TYPE_NOVAL,
 889                 .name = "reset_mib",
 890                 .description = "Reset single port MIB counters",
 891                 .set = rtl8366s_sw_reset_port_mibs,
 892         }, {
 893                 .type = SWITCH_TYPE_STRING,
 894                 .name = "mib",
 895                 .description = "Get MIB counters for port",
 896                 .max = 33,
 897                 .set = NULL,
 898                 .get = rtl8366_sw_get_port_mib,
 899         }, {
 900                 .type = SWITCH_TYPE_INT,
 901                 .name = "led",
 902                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
 903                 .max = 15,
 904                 .set = rtl8366s_sw_set_port_led,
 905                 .get = rtl8366s_sw_get_port_led,
 906         },
 907 };
 908
 909 static struct switch_attr rtl8366s_vlan[] = {
 910         {
 911                 .type = SWITCH_TYPE_STRING,
 912                 .name = "info",
 913                 .description = "Get vlan information",
 914                 .max = 1,
 915                 .set = NULL,
 916                 .get = rtl8366_sw_get_vlan_info,
 917         }, {
 918                 .type = SWITCH_TYPE_INT,
 919                 .name = "fid",
 920                 .description = "Get/Set vlan FID",
 921                 .max = RTL8366S_FIDMAX,
 922                 .set = rtl8366_sw_set_vlan_fid,
 923                 .get = rtl8366_sw_get_vlan_fid,
 924         },
 925 };
 926
 927 static const struct switch_dev_ops rtl8366_ops = {
 928         .attr_global = {
 929                 .attr = rtl8366s_globals,
 930                 .n_attr = ARRAY_SIZE(rtl8366s_globals),
 931         },
 932         .attr_port = {
 933                 .attr = rtl8366s_port,
 934                 .n_attr = ARRAY_SIZE(rtl8366s_port),
 935         },
 936         .attr_vlan = {
 937                 .attr = rtl8366s_vlan,
 938                 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
 939         },
 940
 941         .get_vlan_ports = rtl8366_sw_get_vlan_ports,
 942         .set_vlan_ports = rtl8366_sw_set_vlan_ports,
 943         .get_port_pvid = rtl8366_sw_get_port_pvid,
 944         .set_port_pvid = rtl8366_sw_set_port_pvid,
 945         .reset_switch = rtl8366_sw_reset_switch,
 946         .get_port_link = rtl8366s_sw_get_port_link,
 947 };
 948
 949 static int rtl8366s_switch_init(struct rtl8366_smi *smi)
 950 {
 951         struct switch_dev *dev = &smi->sw_dev;
 952         int err;
 953
 954         dev->name = "RTL8366S";
 955         dev->cpu_port = RTL8366S_PORT_NUM_CPU;
 956         dev->ports = RTL8366S_NUM_PORTS;
 957         dev->vlans = RTL8366S_NUM_VIDS;
 958         dev->ops = &rtl8366_ops;
 959         dev->alias = dev_name(smi->parent);
 960
 961         err = register_switch(dev, NULL);
 962         if (err)
 963                 dev_err(smi->parent, "switch registration failed\n");
 964
 965         return err;
 966 }
 967
 968 static void rtl8366s_switch_cleanup(struct rtl8366_smi *smi)
 969 {
 970         unregister_switch(&smi->sw_dev);
 971 }
 972
 973 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
 974 {
 975         struct rtl8366_smi *smi = bus->priv;
 976         u32 val = 0;
 977         int err;
 978
 979         err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
 980         if (err)
 981                 return 0xffff;
 982
 983         return val;
 984 }
 985
 986 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
 987 {
 988         struct rtl8366_smi *smi = bus->priv;
 989         u32 t;
 990         int err;
 991
 992         err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
 993         /* flush write */
 994         (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
 995
 996         return err;
 997 }
 998
 999 static int rtl8366s_detect(struct rtl8366_smi *smi)
1000 {
1001         u32 chip_id = 0;
1002         u32 chip_ver = 0;
1003         int ret;
1004
1005         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1006         if (ret) {
1007                 dev_err(smi->parent, "unable to read chip id\n");
1008                 return ret;
1009         }
1010
1011         switch (chip_id) {
1012         case RTL8366S_CHIP_ID_8366:
1013                 break;
1014         default:
1015                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1016                 return -ENODEV;
1017         }
1018
1019         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1020                                    &chip_ver);
1021         if (ret) {
1022                 dev_err(smi->parent, "unable to read chip version\n");
1023                 return ret;
1024         }
1025
1026         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1027                  chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1028
1029         return 0;
1030 }
1031
1032 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1033         .detect         = rtl8366s_detect,
1034         .reset_chip     = rtl8366s_reset_chip,
1035         .setup          = rtl8366s_setup,
1036
1037         .mii_read       = rtl8366s_mii_read,
1038         .mii_write      = rtl8366s_mii_write,
1039
1040         .get_vlan_mc    = rtl8366s_get_vlan_mc,
1041         .set_vlan_mc    = rtl8366s_set_vlan_mc,
1042         .get_vlan_4k    = rtl8366s_get_vlan_4k,
1043         .set_vlan_4k    = rtl8366s_set_vlan_4k,
1044         .get_mc_index   = rtl8366s_get_mc_index,
1045         .set_mc_index   = rtl8366s_set_mc_index,
1046         .get_mib_counter = rtl8366_get_mib_counter,
1047         .is_vlan_valid  = rtl8366s_is_vlan_valid,
1048         .enable_vlan    = rtl8366s_enable_vlan,
1049         .enable_vlan4k  = rtl8366s_enable_vlan4k,
1050         .enable_port    = rtl8366s_enable_port,
1051 };
1052
1053 static int rtl8366s_probe(struct platform_device *pdev)
1054 {
1055         static int rtl8366_smi_version_printed;
1056         struct rtl8366_smi *smi;
1057         int err;
1058
1059         if (!rtl8366_smi_version_printed++)
1060                 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1061                        " version " RTL8366S_DRIVER_VER"\n");
1062
1063         smi = rtl8366_smi_probe(pdev);
1064         if (!smi)
1065                 return -ENODEV;
1066
1067         smi->clk_delay = 10;
1068         smi->cmd_read = 0xa9;
1069         smi->cmd_write = 0xa8;
1070         smi->ops = &rtl8366s_smi_ops;
1071         smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1072         smi->num_ports = RTL8366S_NUM_PORTS;
1073         smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1074         smi->mib_counters = rtl8366s_mib_counters;
1075         smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
1076
1077         err = rtl8366_smi_init(smi);
1078         if (err)
1079                 goto err_free_smi;
1080
1081         platform_set_drvdata(pdev, smi);
1082
1083         err = rtl8366s_switch_init(smi);
1084         if (err)
1085                 goto err_clear_drvdata;
1086
1087         return 0;
1088
1089  err_clear_drvdata:
1090         platform_set_drvdata(pdev, NULL);
1091         rtl8366_smi_cleanup(smi);
1092  err_free_smi:
1093         kfree(smi);
1094         return err;
1095 }
1096
1097 static int rtl8366s_remove(struct platform_device *pdev)
1098 {
1099         struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1100
1101         if (smi) {
1102                 rtl8366s_switch_cleanup(smi);
1103                 platform_set_drvdata(pdev, NULL);
1104                 rtl8366_smi_cleanup(smi);
1105                 kfree(smi);
1106         }
1107
1108         return 0;
1109 }
1110
1111 #ifdef CONFIG_OF
1112 static const struct of_device_id rtl8366s_match[] = {
1113         { .compatible = "rtl8366s" },
1114         {},
1115 };
1116 MODULE_DEVICE_TABLE(of, rtl8366s_match);
1117 #endif
1118
1119 static struct platform_driver rtl8366s_driver = {
1120         .driver = {
1121                 .name           = RTL8366S_DRIVER_NAME,
1122                 .owner          = THIS_MODULE,
1123 #ifdef CONFIG_OF
1124                 .of_match_table = of_match_ptr(rtl8366s_match),
1125 #endif
1126         },
1127         .probe          = rtl8366s_probe,
1128         .remove         = rtl8366s_remove,
1129 };
1130
1131 static int __init rtl8366s_module_init(void)
1132 {
1133         return platform_driver_register(&rtl8366s_driver);
1134 }
1135 module_init(rtl8366s_module_init);
1136
1137 static void __exit rtl8366s_module_exit(void)
1138 {
1139         platform_driver_unregister(&rtl8366s_driver);
1140 }
1141 module_exit(rtl8366s_module_exit);
1142
1143 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1144 MODULE_VERSION(RTL8366S_DRIVER_VER);
1145 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1146 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1147 MODULE_LICENSE("GPL v2");
1148 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);