target/linux/generic/files/drivers/net/phy/rtl8366rb.c

   1 /*
   2  * Platform driver for the Realtek RTL8366S ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/skbuff.h>
  18 #include <linux/rtl8366rb.h>
  19
  20 #include "rtl8366_smi.h"
  21
  22 #define RTL8366RB_DRIVER_DESC   "Realtek RTL8366RB ethernet switch driver"
  23 #define RTL8366RB_DRIVER_VER    "0.2.2"
  24
  25 #define RTL8366RB_PHY_NO_MAX    4
  26 #define RTL8366RB_PHY_PAGE_MAX  7
  27 #define RTL8366RB_PHY_ADDR_MAX  31
  28
  29 /* Switch Global Configuration register */
  30 #define RTL8366RB_SGCR                          0x0000
  31 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL         BIT(0)
  32 #define RTL8366RB_SGCR_MAX_LENGTH(_x)           (_x << 4)
  33 #define RTL8366RB_SGCR_MAX_LENGTH_MASK          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  34 #define RTL8366RB_SGCR_MAX_LENGTH_1522          RTL8366RB_SGCR_MAX_LENGTH(0x0)
  35 #define RTL8366RB_SGCR_MAX_LENGTH_1536          RTL8366RB_SGCR_MAX_LENGTH(0x1)
  36 #define RTL8366RB_SGCR_MAX_LENGTH_1552          RTL8366RB_SGCR_MAX_LENGTH(0x2)
  37 #define RTL8366RB_SGCR_MAX_LENGTH_9216          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  38 #define RTL8366RB_SGCR_EN_VLAN                  BIT(13)
  39 #define RTL8366RB_SGCR_EN_VLAN_4KTB             BIT(14)
  40
  41 /* Port Enable Control register */
  42 #define RTL8366RB_PECR                          0x0001
  43
  44 /* Switch Security Control registers */
  45 #define RTL8366RB_SSCR0                         0x0002
  46 #define RTL8366RB_SSCR1                         0x0003
  47 #define RTL8366RB_SSCR2                         0x0004
  48 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA         BIT(0)
  49
  50 #define RTL8366RB_RESET_CTRL_REG                0x0100
  51 #define RTL8366RB_CHIP_CTRL_RESET_HW            1
  52 #define RTL8366RB_CHIP_CTRL_RESET_SW            (1 << 1)
  53
  54 #define RTL8366RB_CHIP_VERSION_CTRL_REG         0x050A
  55 #define RTL8366RB_CHIP_VERSION_MASK             0xf
  56 #define RTL8366RB_CHIP_ID_REG                   0x0509
  57 #define RTL8366RB_CHIP_ID_8366                  0x5937
  58
  59 /* PHY registers control */
  60 #define RTL8366RB_PHY_ACCESS_CTRL_REG           0x8000
  61 #define RTL8366RB_PHY_ACCESS_DATA_REG           0x8002
  62
  63 #define RTL8366RB_PHY_CTRL_READ                 1
  64 #define RTL8366RB_PHY_CTRL_WRITE                0
  65
  66 #define RTL8366RB_PHY_REG_MASK                  0x1f
  67 #define RTL8366RB_PHY_PAGE_OFFSET               5
  68 #define RTL8366RB_PHY_PAGE_MASK                 (0xf << 5)
  69 #define RTL8366RB_PHY_NO_OFFSET                 9
  70 #define RTL8366RB_PHY_NO_MASK                   (0x1f << 9)
  71
  72 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG        0x037f
  73
  74 /* LED control registers */
  75 #define RTL8366RB_LED_BLINKRATE_REG             0x0430
  76 #define RTL8366RB_LED_BLINKRATE_BIT             0
  77 #define RTL8366RB_LED_BLINKRATE_MASK            0x0007
  78
  79 #define RTL8366RB_LED_CTRL_REG                  0x0431
  80 #define RTL8366RB_LED_0_1_CTRL_REG              0x0432
  81 #define RTL8366RB_LED_2_3_CTRL_REG              0x0433
  82
  83 #define RTL8366RB_MIB_COUNT                     33
  84 #define RTL8366RB_GLOBAL_MIB_COUNT              1
  85 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET       0x0050
  86 #define RTL8366RB_MIB_COUNTER_BASE              0x1000
  87 #define RTL8366RB_MIB_CTRL_REG                  0x13F0
  88 #define RTL8366RB_MIB_CTRL_USER_MASK            0x0FFC
  89 #define RTL8366RB_MIB_CTRL_BUSY_MASK            BIT(0)
  90 #define RTL8366RB_MIB_CTRL_RESET_MASK           BIT(1)
  91 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p)       BIT(2 + (_p))
  92 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET         BIT(11)
  93
  94 #define RTL8366RB_PORT_VLAN_CTRL_BASE           0x0063
  95 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p)  \
  96                 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
  97 #define RTL8366RB_PORT_VLAN_CTRL_MASK           0xf
  98 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p)      (4 * ((_p) % 4))
  99
 100
 101 #define RTL8366RB_VLAN_TABLE_READ_BASE          0x018C
 102 #define RTL8366RB_VLAN_TABLE_WRITE_BASE         0x0185
 103
 104
 105 #define RTL8366RB_TABLE_ACCESS_CTRL_REG         0x0180
 106 #define RTL8366RB_TABLE_VLAN_READ_CTRL          0x0E01
 107 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL         0x0F01
 108
 109 #define RTL8366RB_VLAN_MC_BASE(_x)              (0x0020 + (_x) * 3)
 110
 111
 112 #define RTL8366RB_PORT_LINK_STATUS_BASE         0x0014
 113 #define RTL8366RB_PORT_STATUS_SPEED_MASK        0x0003
 114 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK       0x0004
 115 #define RTL8366RB_PORT_STATUS_LINK_MASK         0x0010
 116 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK      0x0020
 117 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK      0x0040
 118 #define RTL8366RB_PORT_STATUS_AN_MASK           0x0080
 119
 120
 121 #define RTL8366RB_PORT_NUM_CPU          5
 122 #define RTL8366RB_NUM_PORTS             6
 123 #define RTL8366RB_NUM_VLANS             16
 124 #define RTL8366RB_NUM_LEDGROUPS         4
 125 #define RTL8366RB_NUM_VIDS              4096
 126 #define RTL8366RB_PRIORITYMAX           7
 127 #define RTL8366RB_FIDMAX                7
 128
 129
 130 #define RTL8366RB_PORT_1                (1 << 0) /* In userspace port 0 */
 131 #define RTL8366RB_PORT_2                (1 << 1) /* In userspace port 1 */
 132 #define RTL8366RB_PORT_3                (1 << 2) /* In userspace port 2 */
 133 #define RTL8366RB_PORT_4                (1 << 3) /* In userspace port 3 */
 134 #define RTL8366RB_PORT_5                (1 << 4) /* In userspace port 4 */
 135
 136 #define RTL8366RB_PORT_CPU              (1 << 5) /* CPU port */
 137
 138 #define RTL8366RB_PORT_ALL              (RTL8366RB_PORT_1 |     \
 139                                          RTL8366RB_PORT_2 |     \
 140                                          RTL8366RB_PORT_3 |     \
 141                                          RTL8366RB_PORT_4 |     \
 142                                          RTL8366RB_PORT_5 |     \
 143                                          RTL8366RB_PORT_CPU)
 144
 145 #define RTL8366RB_PORT_ALL_BUT_CPU      (RTL8366RB_PORT_1 |     \
 146                                          RTL8366RB_PORT_2 |     \
 147                                          RTL8366RB_PORT_3 |     \
 148                                          RTL8366RB_PORT_4 |     \
 149                                          RTL8366RB_PORT_5)
 150
 151 #define RTL8366RB_PORT_ALL_EXTERNAL     (RTL8366RB_PORT_1 |     \
 152                                          RTL8366RB_PORT_2 |     \
 153                                          RTL8366RB_PORT_3 |     \
 154                                          RTL8366RB_PORT_4)
 155
 156 #define RTL8366RB_PORT_ALL_INTERNAL      RTL8366RB_PORT_CPU
 157
 158 #define RTL8366RB_VLAN_VID_MASK         0xfff
 159 #define RTL8366RB_VLAN_PRIORITY_SHIFT   12
 160 #define RTL8366RB_VLAN_PRIORITY_MASK    0x7
 161 #define RTL8366RB_VLAN_UNTAG_SHIFT      8
 162 #define RTL8366RB_VLAN_UNTAG_MASK       0xff
 163 #define RTL8366RB_VLAN_MEMBER_MASK      0xff
 164 #define RTL8366RB_VLAN_FID_MASK         0x7
 165
 166 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
 167         { 0,  0, 4, "IfInOctets"                                },
 168         { 0,  4, 4, "EtherStatsOctets"                          },
 169         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 170         { 0, 10, 2, "EtherFragments"                            },
 171         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 172         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 173         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 174         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 175         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 176         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 177         { 0, 24, 2, "EtherOversizeStats"                        },
 178         { 0, 26, 2, "EtherStatsJabbers"                         },
 179         { 0, 28, 2, "IfInUcastPkts"                             },
 180         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 181         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 182         { 0, 34, 2, "EtherStatsDropEvents"                      },
 183         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 184         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 185         { 0, 40, 2, "Dot3InPauseFrames"                         },
 186         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 187         { 0, 44, 4, "IfOutOctets"                               },
 188         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 189         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 190         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 191         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 192         { 0, 56, 2, "EtherStatsCollisions"                      },
 193         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 194         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 195         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 196         { 0, 64, 2, "Dot1dTpPortInDiscards"                     },
 197         { 0, 66, 2, "IfOutUcastPkts"                            },
 198         { 0, 68, 2, "IfOutMulticastPkts"                        },
 199         { 0, 70, 2, "IfOutBroadcastPkts"                        },
 200 };
 201
 202 #define REG_WR(_smi, _reg, _val)                                        \
 203         do {                                                            \
 204                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 205                 if (err)                                                \
 206                         return err;                                     \
 207         } while (0)
 208
 209 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 210         do {                                                            \
 211                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 212                 if (err)                                                \
 213                         return err;                                     \
 214         } while (0)
 215
 216 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
 217 {
 218         int timeout = 10;
 219         u32 data;
 220
 221         rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
 222                               RTL8366RB_CHIP_CTRL_RESET_HW);
 223         do {
 224                 msleep(1);
 225                 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
 226                         return -EIO;
 227
 228                 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
 229                         break;
 230         } while (--timeout);
 231
 232         if (!timeout) {
 233                 printk("Timeout waiting for the switch to reset\n");
 234                 return -EIO;
 235         }
 236
 237         return 0;
 238 }
 239
 240 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
 241 {
 242         int err;
 243
 244         /* set maximum packet length to 1536 bytes */
 245         REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
 246                 RTL8366RB_SGCR_MAX_LENGTH_1536);
 247
 248         /* enable all ports */
 249         REG_WR(smi, RTL8366RB_PECR, 0);
 250
 251         /* enable learning for all ports */
 252         REG_WR(smi, RTL8366RB_SSCR0, 0);
 253
 254         /* enable auto ageing for all ports */
 255         REG_WR(smi, RTL8366RB_SSCR1, 0);
 256
 257         /*
 258          * discard VLAN tagged packets if the port is not a member of
 259          * the VLAN with which the packets is associated.
 260          */
 261         REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
 262
 263         /* don't drop packets whose DA has not been learned */
 264         REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
 265
 266         return 0;
 267 }
 268
 269 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
 270                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 271 {
 272         u32 reg;
 273         int ret;
 274
 275         if (phy_no > RTL8366RB_PHY_NO_MAX)
 276                 return -EINVAL;
 277
 278         if (page > RTL8366RB_PHY_PAGE_MAX)
 279                 return -EINVAL;
 280
 281         if (addr > RTL8366RB_PHY_ADDR_MAX)
 282                 return -EINVAL;
 283
 284         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 285                                     RTL8366RB_PHY_CTRL_READ);
 286         if (ret)
 287                 return ret;
 288
 289         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 290               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 291               (addr & RTL8366RB_PHY_REG_MASK);
 292
 293         ret = rtl8366_smi_write_reg(smi, reg, 0);
 294         if (ret)
 295                 return ret;
 296
 297         ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
 298         if (ret)
 299                 return ret;
 300
 301         return 0;
 302 }
 303
 304 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
 305                                   u32 phy_no, u32 page, u32 addr, u32 data)
 306 {
 307         u32 reg;
 308         int ret;
 309
 310         if (phy_no > RTL8366RB_PHY_NO_MAX)
 311                 return -EINVAL;
 312
 313         if (page > RTL8366RB_PHY_PAGE_MAX)
 314                 return -EINVAL;
 315
 316         if (addr > RTL8366RB_PHY_ADDR_MAX)
 317                 return -EINVAL;
 318
 319         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 320                                     RTL8366RB_PHY_CTRL_WRITE);
 321         if (ret)
 322                 return ret;
 323
 324         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 325               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 326               (addr & RTL8366RB_PHY_REG_MASK);
 327
 328         ret = rtl8366_smi_write_reg(smi, reg, data);
 329         if (ret)
 330                 return ret;
 331
 332         return 0;
 333 }
 334
 335 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
 336                                      int port, unsigned long long *val)
 337 {
 338         int i;
 339         int err;
 340         u32 addr, data;
 341         u64 mibvalue;
 342
 343         if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
 344                 return -EINVAL;
 345
 346         addr = RTL8366RB_MIB_COUNTER_BASE +
 347                RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
 348                rtl8366rb_mib_counters[counter].offset;
 349
 350         /*
 351          * Writing access counter address first
 352          * then ASIC will prepare 64bits counter wait for being retrived
 353          */
 354         data = 0; /* writing data will be discard by ASIC */
 355         err = rtl8366_smi_write_reg(smi, addr, data);
 356         if (err)
 357                 return err;
 358
 359         /* read MIB control register */
 360         err =  rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
 361         if (err)
 362                 return err;
 363
 364         if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
 365                 return -EBUSY;
 366
 367         if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
 368                 return -EIO;
 369
 370         mibvalue = 0;
 371         for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
 372                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 373                 if (err)
 374                         return err;
 375
 376                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 377         }
 378
 379         *val = mibvalue;
 380         return 0;
 381 }
 382
 383 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 384                                  struct rtl8366_vlan_4k *vlan4k)
 385 {
 386         u32 data[3];
 387         int err;
 388         int i;
 389
 390         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 391
 392         if (vid >= RTL8366RB_NUM_VIDS)
 393                 return -EINVAL;
 394
 395         /* write VID */
 396         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
 397                                     vid & RTL8366RB_VLAN_VID_MASK);
 398         if (err)
 399                 return err;
 400
 401         /* write table access control word */
 402         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 403                                     RTL8366RB_TABLE_VLAN_READ_CTRL);
 404         if (err)
 405                 return err;
 406
 407         for (i = 0; i < 3; i++) {
 408                 err = rtl8366_smi_read_reg(smi,
 409                                            RTL8366RB_VLAN_TABLE_READ_BASE + i,
 410                                            &data[i]);
 411                 if (err)
 412                         return err;
 413         }
 414
 415         vlan4k->vid = vid;
 416         vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
 417                         RTL8366RB_VLAN_UNTAG_MASK;
 418         vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
 419         vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
 420
 421         return 0;
 422 }
 423
 424 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
 425                                  const struct rtl8366_vlan_4k *vlan4k)
 426 {
 427         u32 data[3];
 428         int err;
 429         int i;
 430
 431         if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
 432             vlan4k->member > RTL8366RB_PORT_ALL ||
 433             vlan4k->untag > RTL8366RB_PORT_ALL ||
 434             vlan4k->fid > RTL8366RB_FIDMAX)
 435                 return -EINVAL;
 436
 437         data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
 438         data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
 439                   ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
 440                         RTL8366RB_VLAN_UNTAG_SHIFT);
 441         data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
 442
 443         for (i = 0; i < 3; i++) {
 444                 err = rtl8366_smi_write_reg(smi,
 445                                             RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
 446                                             data[i]);
 447                 if (err)
 448                         return err;
 449         }
 450
 451         /* write table access control word */
 452         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 453                                     RTL8366RB_TABLE_VLAN_WRITE_CTRL);
 454
 455         return err;
 456 }
 457
 458 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 459                                  struct rtl8366_vlan_mc *vlanmc)
 460 {
 461         u32 data[3];
 462         int err;
 463         int i;
 464
 465         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 466
 467         if (index >= RTL8366RB_NUM_VLANS)
 468                 return -EINVAL;
 469
 470         for (i = 0; i < 3; i++) {
 471                 err = rtl8366_smi_read_reg(smi,
 472                                            RTL8366RB_VLAN_MC_BASE(index) + i,
 473                                            &data[i]);
 474                 if (err)
 475                         return err;
 476         }
 477
 478         vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
 479         vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
 480                            RTL8366RB_VLAN_PRIORITY_MASK;
 481         vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
 482                         RTL8366RB_VLAN_UNTAG_MASK;
 483         vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
 484         vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
 485
 486         return 0;
 487 }
 488
 489 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 490                                  const struct rtl8366_vlan_mc *vlanmc)
 491 {
 492         u32 data[3];
 493         int err;
 494         int i;
 495
 496         if (index >= RTL8366RB_NUM_VLANS ||
 497             vlanmc->vid >= RTL8366RB_NUM_VIDS ||
 498             vlanmc->priority > RTL8366RB_PRIORITYMAX ||
 499             vlanmc->member > RTL8366RB_PORT_ALL ||
 500             vlanmc->untag > RTL8366RB_PORT_ALL ||
 501             vlanmc->fid > RTL8366RB_FIDMAX)
 502                 return -EINVAL;
 503
 504         data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
 505                   ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
 506                         RTL8366RB_VLAN_PRIORITY_SHIFT);
 507         data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
 508                   ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
 509                         RTL8366RB_VLAN_UNTAG_SHIFT);
 510         data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
 511
 512         for (i = 0; i < 3; i++) {
 513                 err = rtl8366_smi_write_reg(smi,
 514                                             RTL8366RB_VLAN_MC_BASE(index) + i,
 515                                             data[i]);
 516                 if (err)
 517                         return err;
 518         }
 519
 520         return 0;
 521 }
 522
 523 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 524 {
 525         u32 data;
 526         int err;
 527
 528         if (port >= RTL8366RB_NUM_PORTS)
 529                 return -EINVAL;
 530
 531         err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 532                                    &data);
 533         if (err)
 534                 return err;
 535
 536         *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
 537                RTL8366RB_PORT_VLAN_CTRL_MASK;
 538
 539         return 0;
 540
 541 }
 542
 543 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 544 {
 545         if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
 546                 return -EINVAL;
 547
 548         return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 549                                 RTL8366RB_PORT_VLAN_CTRL_MASK <<
 550                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
 551                                 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
 552                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
 553 }
 554
 555 static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
 556 {
 557         if (vlan == 0 || vlan >= RTL8366RB_NUM_VLANS)
 558                 return 0;
 559
 560         return 1;
 561 }
 562
 563 static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)
 564 {
 565         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
 566                                 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
 567 }
 568
 569 static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)
 570 {
 571         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
 572                                 RTL8366RB_SGCR_EN_VLAN_4KTB,
 573                                 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
 574 }
 575
 576 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
 577                                   const struct switch_attr *attr,
 578                                   struct switch_val *val)
 579 {
 580         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 581
 582         return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 583                                 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
 584 }
 585
 586 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
 587                                      const struct switch_attr *attr,
 588                                      struct switch_val *val)
 589 {
 590         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 591         u32 data;
 592
 593         rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
 594
 595         val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
 596
 597         return 0;
 598 }
 599
 600 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
 601                                     const struct switch_attr *attr,
 602                                     struct switch_val *val)
 603 {
 604         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 605
 606         if (val->value.i >= 6)
 607                 return -EINVAL;
 608
 609         return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
 610                                 RTL8366RB_LED_BLINKRATE_MASK,
 611                                 val->value.i);
 612 }
 613
 614 static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
 615                                        const struct switch_attr *attr,
 616                                        struct switch_val *val)
 617 {
 618         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 619         u32 data;
 620
 621         rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
 622         val->value.i = !data;
 623
 624         return 0;
 625 }
 626
 627
 628 static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
 629                                        const struct switch_attr *attr,
 630                                        struct switch_val *val)
 631 {
 632         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 633         u32 portmask = 0;
 634         int err = 0;
 635
 636         if (!val->value.i)
 637                 portmask = RTL8366RB_PORT_ALL;
 638
 639         /* set learning for all ports */
 640         REG_WR(smi, RTL8366RB_SSCR0, portmask);
 641
 642         /* set auto ageing for all ports */
 643         REG_WR(smi, RTL8366RB_SSCR1, portmask);
 644
 645         return 0;
 646 }
 647
 648
 649 static const char *rtl8366rb_speed_str(unsigned speed)
 650 {
 651         switch (speed) {
 652         case 0:
 653                 return "10baseT";
 654         case 1:
 655                 return "100baseT";
 656         case 2:
 657                 return "1000baseT";
 658         }
 659
 660         return "unknown";
 661 }
 662
 663 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
 664                                      const struct switch_attr *attr,
 665                                      struct switch_val *val)
 666 {
 667         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 668         u32 len = 0, data = 0;
 669
 670         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 671                 return -EINVAL;
 672
 673         memset(smi->buf, '\0', sizeof(smi->buf));
 674         rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
 675                              (val->port_vlan / 2), &data);
 676
 677         if (val->port_vlan % 2)
 678                 data = data >> 8;
 679
 680         if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
 681                 len = snprintf(smi->buf, sizeof(smi->buf),
 682                                 "port:%d link:up speed:%s %s-duplex %s%s%s",
 683                                 val->port_vlan,
 684                                 rtl8366rb_speed_str(data &
 685                                           RTL8366RB_PORT_STATUS_SPEED_MASK),
 686                                 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
 687                                         "full" : "half",
 688                                 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
 689                                         "tx-pause ": "",
 690                                 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
 691                                         "rx-pause " : "",
 692                                 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
 693                                         "nway ": "");
 694         } else {
 695                 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
 696                                 val->port_vlan);
 697         }
 698
 699         val->value.s = smi->buf;
 700         val->len = len;
 701
 702         return 0;
 703 }
 704
 705 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
 706                                     const struct switch_attr *attr,
 707                                     struct switch_val *val)
 708 {
 709         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 710         u32 data;
 711         u32 mask;
 712         u32 reg;
 713
 714         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 715                 return -EINVAL;
 716
 717         if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
 718                 reg = RTL8366RB_LED_BLINKRATE_REG;
 719                 mask = 0xF << 4;
 720                 data = val->value.i << 4;
 721         } else {
 722                 reg = RTL8366RB_LED_CTRL_REG;
 723                 mask = 0xF << (val->port_vlan * 4),
 724                 data = val->value.i << (val->port_vlan * 4);
 725         }
 726
 727         return rtl8366_smi_rmwr(smi, reg, mask, data);
 728 }
 729
 730 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
 731                                     const struct switch_attr *attr,
 732                                     struct switch_val *val)
 733 {
 734         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 735         u32 data = 0;
 736
 737         if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
 738                 return -EINVAL;
 739
 740         rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
 741         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 742
 743         return 0;
 744 }
 745
 746 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
 747                                        const struct switch_attr *attr,
 748                                        struct switch_val *val)
 749 {
 750         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 751
 752         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 753                 return -EINVAL;
 754
 755         return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 756                                 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
 757 }
 758
 759 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
 760 {
 761         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 762         int err;
 763
 764         err = rtl8366rb_reset_chip(smi);
 765         if (err)
 766                 return err;
 767
 768         err = rtl8366rb_hw_init(smi);
 769         if (err)
 770                 return err;
 771
 772         return rtl8366_reset_vlan(smi);
 773 }
 774
 775 static struct switch_attr rtl8366rb_globals[] = {
 776         {
 777                 .type = SWITCH_TYPE_INT,
 778                 .name = "enable_learning",
 779                 .description = "Enable learning, enable aging",
 780                 .set = rtl8366rb_sw_set_learning_enable,
 781                 .get = rtl8366rb_sw_get_learning_enable,
 782                 .max = 1
 783         }, {
 784                 .type = SWITCH_TYPE_INT,
 785                 .name = "enable_vlan",
 786                 .description = "Enable VLAN mode",
 787                 .set = rtl8366_sw_set_vlan_enable,
 788                 .get = rtl8366_sw_get_vlan_enable,
 789                 .max = 1,
 790                 .ofs = 1
 791         }, {
 792                 .type = SWITCH_TYPE_INT,
 793                 .name = "enable_vlan4k",
 794                 .description = "Enable VLAN 4K mode",
 795                 .set = rtl8366_sw_set_vlan_enable,
 796                 .get = rtl8366_sw_get_vlan_enable,
 797                 .max = 1,
 798                 .ofs = 2
 799         }, {
 800                 .type = SWITCH_TYPE_NOVAL,
 801                 .name = "reset_mibs",
 802                 .description = "Reset all MIB counters",
 803                 .set = rtl8366rb_sw_reset_mibs,
 804         }, {
 805                 .type = SWITCH_TYPE_INT,
 806                 .name = "blinkrate",
 807                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
 808                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
 809                 .set = rtl8366rb_sw_set_blinkrate,
 810                 .get = rtl8366rb_sw_get_blinkrate,
 811                 .max = 5
 812         },
 813 };
 814
 815 static struct switch_attr rtl8366rb_port[] = {
 816         {
 817                 .type = SWITCH_TYPE_STRING,
 818                 .name = "link",
 819                 .description = "Get port link information",
 820                 .max = 1,
 821                 .set = NULL,
 822                 .get = rtl8366rb_sw_get_port_link,
 823         }, {
 824                 .type = SWITCH_TYPE_NOVAL,
 825                 .name = "reset_mib",
 826                 .description = "Reset single port MIB counters",
 827                 .set = rtl8366rb_sw_reset_port_mibs,
 828         }, {
 829                 .type = SWITCH_TYPE_STRING,
 830                 .name = "mib",
 831                 .description = "Get MIB counters for port",
 832                 .max = 33,
 833                 .set = NULL,
 834                 .get = rtl8366_sw_get_port_mib,
 835         }, {
 836                 .type = SWITCH_TYPE_INT,
 837                 .name = "led",
 838                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
 839                 .max = 15,
 840                 .set = rtl8366rb_sw_set_port_led,
 841                 .get = rtl8366rb_sw_get_port_led,
 842         },
 843 };
 844
 845 static struct switch_attr rtl8366rb_vlan[] = {
 846         {
 847                 .type = SWITCH_TYPE_STRING,
 848                 .name = "info",
 849                 .description = "Get vlan information",
 850                 .max = 1,
 851                 .set = NULL,
 852                 .get = rtl8366_sw_get_vlan_info,
 853         },
 854 };
 855
 856 static const struct switch_dev_ops rtl8366_ops = {
 857         .attr_global = {
 858                 .attr = rtl8366rb_globals,
 859                 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
 860         },
 861         .attr_port = {
 862                 .attr = rtl8366rb_port,
 863                 .n_attr = ARRAY_SIZE(rtl8366rb_port),
 864         },
 865         .attr_vlan = {
 866                 .attr = rtl8366rb_vlan,
 867                 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
 868         },
 869
 870         .get_vlan_ports = rtl8366_sw_get_vlan_ports,
 871         .set_vlan_ports = rtl8366_sw_set_vlan_ports,
 872         .get_port_pvid = rtl8366_sw_get_port_pvid,
 873         .set_port_pvid = rtl8366_sw_set_port_pvid,
 874         .reset_switch = rtl8366rb_sw_reset_switch,
 875 };
 876
 877 static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
 878 {
 879         struct switch_dev *dev = &smi->sw_dev;
 880         int err;
 881
 882         dev->name = "RTL8366RB";
 883         dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
 884         dev->ports = RTL8366RB_NUM_PORTS;
 885         dev->vlans = RTL8366RB_NUM_VLANS;
 886         dev->ops = &rtl8366_ops;
 887         dev->devname = dev_name(smi->parent);
 888
 889         err = register_switch(dev, NULL);
 890         if (err)
 891                 dev_err(smi->parent, "switch registration failed\n");
 892
 893         return err;
 894 }
 895
 896 static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
 897 {
 898         unregister_switch(&smi->sw_dev);
 899 }
 900
 901 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
 902 {
 903         struct rtl8366_smi *smi = bus->priv;
 904         u32 val = 0;
 905         int err;
 906
 907         err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
 908         if (err)
 909                 return 0xffff;
 910
 911         return val;
 912 }
 913
 914 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
 915 {
 916         struct rtl8366_smi *smi = bus->priv;
 917         u32 t;
 918         int err;
 919
 920         err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
 921         /* flush write */
 922         (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
 923
 924         return err;
 925 }
 926
 927 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
 928 {
 929         return (bus->read == rtl8366rb_mii_read &&
 930                 bus->write == rtl8366rb_mii_write);
 931 }
 932
 933 static int rtl8366rb_setup(struct rtl8366_smi *smi)
 934 {
 935         int ret;
 936
 937         ret = rtl8366rb_reset_chip(smi);
 938         if (ret)
 939                 return ret;
 940
 941         ret = rtl8366rb_hw_init(smi);
 942         return ret;
 943 }
 944
 945 static int rtl8366rb_detect(struct rtl8366_smi *smi)
 946 {
 947         u32 chip_id = 0;
 948         u32 chip_ver = 0;
 949         int ret;
 950
 951         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
 952         if (ret) {
 953                 dev_err(smi->parent, "unable to read chip id\n");
 954                 return ret;
 955         }
 956
 957         switch (chip_id) {
 958         case RTL8366RB_CHIP_ID_8366:
 959                 break;
 960         default:
 961                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
 962                 return -ENODEV;
 963         }
 964
 965         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
 966                                    &chip_ver);
 967         if (ret) {
 968                 dev_err(smi->parent, "unable to read chip version\n");
 969                 return ret;
 970         }
 971
 972         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
 973                  chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
 974
 975         return 0;
 976 }
 977
 978 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
 979         .detect         = rtl8366rb_detect,
 980         .setup          = rtl8366rb_setup,
 981
 982         .mii_read       = rtl8366rb_mii_read,
 983         .mii_write      = rtl8366rb_mii_write,
 984
 985         .get_vlan_mc    = rtl8366rb_get_vlan_mc,
 986         .set_vlan_mc    = rtl8366rb_set_vlan_mc,
 987         .get_vlan_4k    = rtl8366rb_get_vlan_4k,
 988         .set_vlan_4k    = rtl8366rb_set_vlan_4k,
 989         .get_mc_index   = rtl8366rb_get_mc_index,
 990         .set_mc_index   = rtl8366rb_set_mc_index,
 991         .get_mib_counter = rtl8366rb_get_mib_counter,
 992         .is_vlan_valid  = rtl8366rb_is_vlan_valid,
 993         .enable_vlan    = rtl8366rb_enable_vlan,
 994         .enable_vlan4k  = rtl8366rb_enable_vlan4k,
 995 };
 996
 997 static int __init rtl8366rb_probe(struct platform_device *pdev)
 998 {
 999         static int rtl8366_smi_version_printed;
1000         struct rtl8366rb_platform_data *pdata;
1001         struct rtl8366_smi *smi;
1002         int err;
1003
1004         if (!rtl8366_smi_version_printed++)
1005                 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1006                        " version " RTL8366RB_DRIVER_VER"\n");
1007
1008         pdata = pdev->dev.platform_data;
1009         if (!pdata) {
1010                 dev_err(&pdev->dev, "no platform data specified\n");
1011                 err = -EINVAL;
1012                 goto err_out;
1013         }
1014
1015         smi = rtl8366_smi_alloc(&pdev->dev);
1016         if (!smi) {
1017                 err = -ENOMEM;
1018                 goto err_out;
1019         }
1020
1021         smi->gpio_sda = pdata->gpio_sda;
1022         smi->gpio_sck = pdata->gpio_sck;
1023         smi->ops = &rtl8366rb_smi_ops;
1024         smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1025         smi->num_ports = RTL8366RB_NUM_PORTS;
1026         smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1027         smi->mib_counters = rtl8366rb_mib_counters;
1028         smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1029
1030         err = rtl8366_smi_init(smi);
1031         if (err)
1032                 goto err_free_smi;
1033
1034         platform_set_drvdata(pdev, smi);
1035
1036         err = rtl8366rb_switch_init(smi);
1037         if (err)
1038                 goto err_clear_drvdata;
1039
1040         return 0;
1041
1042  err_clear_drvdata:
1043         platform_set_drvdata(pdev, NULL);
1044         rtl8366_smi_cleanup(smi);
1045  err_free_smi:
1046         kfree(smi);
1047  err_out:
1048         return err;
1049 }
1050
1051 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1052 {
1053         if (!rtl8366rb_mii_bus_match(phydev->bus))
1054                 return -EINVAL;
1055
1056         return 0;
1057 }
1058
1059 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1060 {
1061         return 0;
1062 }
1063
1064 static struct phy_driver rtl8366rb_phy_driver = {
1065         .phy_id         = 0x001cc960,
1066         .name           = "Realtek RTL8366RB",
1067         .phy_id_mask    = 0x1ffffff0,
1068         .features       = PHY_GBIT_FEATURES,
1069         .config_aneg    = rtl8366rb_phy_config_aneg,
1070         .config_init    = rtl8366rb_phy_config_init,
1071         .read_status    = genphy_read_status,
1072         .driver         = {
1073                 .owner = THIS_MODULE,
1074         },
1075 };
1076
1077 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1078 {
1079         struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1080
1081         if (smi) {
1082                 rtl8366rb_switch_cleanup(smi);
1083                 platform_set_drvdata(pdev, NULL);
1084                 rtl8366_smi_cleanup(smi);
1085                 kfree(smi);
1086         }
1087
1088         return 0;
1089 }
1090
1091 static struct platform_driver rtl8366rb_driver = {
1092         .driver = {
1093                 .name           = RTL8366RB_DRIVER_NAME,
1094                 .owner          = THIS_MODULE,
1095         },
1096         .probe          = rtl8366rb_probe,
1097         .remove         = __devexit_p(rtl8366rb_remove),
1098 };
1099
1100 static int __init rtl8366rb_module_init(void)
1101 {
1102         int ret;
1103         ret = platform_driver_register(&rtl8366rb_driver);
1104         if (ret)
1105                 return ret;
1106
1107         ret = phy_driver_register(&rtl8366rb_phy_driver);
1108         if (ret)
1109                 goto err_platform_unregister;
1110
1111         return 0;
1112
1113  err_platform_unregister:
1114         platform_driver_unregister(&rtl8366rb_driver);
1115         return ret;
1116 }
1117 module_init(rtl8366rb_module_init);
1118
1119 static void __exit rtl8366rb_module_exit(void)
1120 {
1121         phy_driver_unregister(&rtl8366rb_phy_driver);
1122         platform_driver_unregister(&rtl8366rb_driver);
1123 }
1124 module_exit(rtl8366rb_module_exit);
1125
1126 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1127 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1128 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1129 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1130 MODULE_LICENSE("GPL v2");
1131 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);