target/linux/generic-2.6/patches/003-net-b44-2.patch

   1 diff -ur linux-2.6.14.3/drivers/net/b44.c linux-2.6.14.3-openwrt/drivers/net/b44.c
   2 --- linux-2.6.14.3/drivers/net/b44.c    2005-11-24 23:10:21.000000000 +0100
   3 +++ linux-2.6.14.3-openwrt/drivers/net/b44.c    2005-12-08 13:24:35.000000000 +0100
   4 @@ -1,7 +1,8 @@
   5 -/* b44.c: Broadcom 4400 device driver.
   6 +/* b44.c: Broadcom 4400/47xx device driver.
   7   *
   8   * Copyright (C) 2002 David S. Miller (davem@redhat.com)
   9 - * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
  10 + * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
  11 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
  12   *
  13   * Distribute under GPL.
  14   */
  15 @@ -78,7 +79,7 @@
  16         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  17
  18  MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
  19 -MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
  20 +MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
  21  MODULE_LICENSE("GPL");
  22  MODULE_VERSION(DRV_MODULE_VERSION);
  23
  24 @@ -93,6 +94,8 @@
  25           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  26         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
  27           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  28 +       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713,
  29 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  30         { }     /* terminate list with empty entry */
  31  };
  32
  33 @@ -106,24 +109,13 @@
  34  static void b44_poll_controller(struct net_device *dev);
  35  #endif
  36
  37 -static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
  38 -{
  39 -       return readl(bp->regs + reg);
  40 -}
  41 -
  42 -static inline void bw32(const struct b44 *bp,
  43 -                       unsigned long reg, unsigned long val)
  44 -{
  45 -       writel(val, bp->regs + reg);
  46 -}
  47 -
  48  static int b44_wait_bit(struct b44 *bp, unsigned long reg,
  49                         u32 bit, unsigned long timeout, const int clear)
  50  {
  51         unsigned long i;
  52
  53         for (i = 0; i < timeout; i++) {
  54 -               u32 val = br32(bp, reg);
  55 +               u32 val = br32(reg);
  56
  57                 if (clear && !(val & bit))
  58                         break;
  59 @@ -154,7 +146,7 @@
  60
  61  static u32 ssb_get_core_rev(struct b44 *bp)
  62  {
  63 -       return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
  64 +       return (br32(B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
  65  }
  66
  67  static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
  68 @@ -165,13 +157,13 @@
  69         pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
  70         pci_rev = ssb_get_core_rev(bp);
  71
  72 -       val = br32(bp, B44_SBINTVEC);
  73 +       val = br32(B44_SBINTVEC);
  74         val |= cores;
  75 -       bw32(bp, B44_SBINTVEC, val);
  76 +       bw32(B44_SBINTVEC, val);
  77
  78 -       val = br32(bp, SSB_PCI_TRANS_2);
  79 +       val = br32(SSB_PCI_TRANS_2);
  80         val |= SSB_PCI_PREF | SSB_PCI_BURST;
  81 -       bw32(bp, SSB_PCI_TRANS_2, val);
  82 +       bw32(SSB_PCI_TRANS_2, val);
  83
  84         pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
  85
  86 @@ -180,18 +172,18 @@
  87
  88  static void ssb_core_disable(struct b44 *bp)
  89  {
  90 -       if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
  91 +       if (br32(B44_SBTMSLOW) & SBTMSLOW_RESET)
  92                 return;
  93
  94 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
  95 +       bw32(B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
  96         b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
  97         b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
  98 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
  99 +       bw32(B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
 100                             SBTMSLOW_REJECT | SBTMSLOW_RESET));
 101 -       br32(bp, B44_SBTMSLOW);
 102 +       br32(B44_SBTMSLOW);
 103         udelay(1);
 104 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
 105 -       br32(bp, B44_SBTMSLOW);
 106 +       bw32(B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
 107 +       br32(B44_SBTMSLOW);
 108         udelay(1);
 109  }
 110
 111 @@ -200,58 +192,65 @@
 112         u32 val;
 113
 114         ssb_core_disable(bp);
 115 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 116 -       br32(bp, B44_SBTMSLOW);
 117 +       bw32(B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 118 +       br32(B44_SBTMSLOW);
 119         udelay(1);
 120
 121         /* Clear SERR if set, this is a hw bug workaround.  */
 122 -       if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
 123 -               bw32(bp, B44_SBTMSHIGH, 0);
 124 +       if (br32(B44_SBTMSHIGH) & SBTMSHIGH_SERR)
 125 +               bw32(B44_SBTMSHIGH, 0);
 126
 127 -       val = br32(bp, B44_SBIMSTATE);
 128 +       val = br32(B44_SBIMSTATE);
 129         if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
 130 -               bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
 131 +               bw32(B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
 132
 133 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 134 -       br32(bp, B44_SBTMSLOW);
 135 +       bw32(B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 136 +       br32(B44_SBTMSLOW);
 137         udelay(1);
 138
 139 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
 140 -       br32(bp, B44_SBTMSLOW);
 141 +       bw32(B44_SBTMSLOW, (SBTMSLOW_CLOCK));
 142 +       br32(B44_SBTMSLOW);
 143         udelay(1);
 144  }
 145
 146 +static int b44_4713_instance;
 147 +
 148  static int ssb_core_unit(struct b44 *bp)
 149  {
 150 -#if 0
 151 -       u32 val = br32(bp, B44_SBADMATCH0);
 152 -       u32 base;
 153 -
 154 -       type = val & SBADMATCH0_TYPE_MASK;
 155 -       switch (type) {
 156 -       case 0:
 157 -               base = val & SBADMATCH0_BS0_MASK;
 158 -               break;
 159 -
 160 -       case 1:
 161 -               base = val & SBADMATCH0_BS1_MASK;
 162 -               break;
 163 -
 164 -       case 2:
 165 -       default:
 166 -               base = val & SBADMATCH0_BS2_MASK;
 167 -               break;
 168 -       };
 169 -#endif
 170 -       return 0;
 171 +       if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
 172 +               return b44_4713_instance++;
 173 +       else
 174 +               return 0;
 175  }
 176
 177  static int ssb_is_core_up(struct b44 *bp)
 178  {
 179 -       return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
 180 +       return ((br32(B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
 181                 == SBTMSLOW_CLOCK);
 182  }
 183
 184 +static void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
 185 +{
 186 +       u32 val;
 187 +
 188 +       bw32(B44_CAM_CTRL, (CAM_CTRL_READ |
 189 +                           (index << CAM_CTRL_INDEX_SHIFT)));
 190 +
 191 +       b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 192 +
 193 +       val = br32(B44_CAM_DATA_LO);
 194 +
 195 +       data[2] = (val >> 24) & 0xFF;
 196 +       data[3] = (val >> 16) & 0xFF;
 197 +       data[4] = (val >> 8) & 0xFF;
 198 +       data[5] = (val >> 0) & 0xFF;
 199 +
 200 +       val = br32(B44_CAM_DATA_HI);
 201 +
 202 +       data[0] = (val >> 8) & 0xFF;
 203 +       data[1] = (val >> 0) & 0xFF;
 204 +}
 205 +
 206  static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
 207  {
 208         u32 val;
 209 @@ -260,19 +259,19 @@
 210         val |= ((u32) data[3]) << 16;
 211         val |= ((u32) data[4]) <<  8;
 212         val |= ((u32) data[5]) <<  0;
 213 -       bw32(bp, B44_CAM_DATA_LO, val);
 214 +       bw32(B44_CAM_DATA_LO, val);
 215         val = (CAM_DATA_HI_VALID |
 216                (((u32) data[0]) << 8) |
 217                (((u32) data[1]) << 0));
 218 -       bw32(bp, B44_CAM_DATA_HI, val);
 219 -       bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
 220 +       bw32(B44_CAM_DATA_HI, val);
 221 +       bw32(B44_CAM_CTRL, (CAM_CTRL_WRITE |
 222                             (index << CAM_CTRL_INDEX_SHIFT)));
 223         b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 224  }
 225
 226  static inline void __b44_disable_ints(struct b44 *bp)
 227  {
 228 -       bw32(bp, B44_IMASK, 0);
 229 +       bw32(B44_IMASK, 0);
 230  }
 231
 232  static void b44_disable_ints(struct b44 *bp)
 233 @@ -280,42 +279,59 @@
 234         __b44_disable_ints(bp);
 235
 236         /* Flush posted writes. */
 237 -       br32(bp, B44_IMASK);
 238 +       br32(B44_IMASK);
 239  }
 240
 241  static void b44_enable_ints(struct b44 *bp)
 242  {
 243 -       bw32(bp, B44_IMASK, bp->imask);
 244 +       bw32(B44_IMASK, bp->imask);
 245  }
 246
 247 -static int b44_readphy(struct b44 *bp, int reg, u32 *val)
 248 +static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
 249  {
 250         int err;
 251
 252 -       bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 253 -       bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 254 +       bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
 255 +       bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
 256                              (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
 257 -                            (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 258 +                            (phy_addr << MDIO_DATA_PMD_SHIFT) |
 259                              (reg << MDIO_DATA_RA_SHIFT) |
 260                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
 261         err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 262 -       *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
 263 +       *val = br32(B44_MDIO_DATA) & MDIO_DATA_DATA;
 264
 265         return err;
 266  }
 267
 268 -static int b44_writephy(struct b44 *bp, int reg, u32 val)
 269 +static int b44_readphy(struct b44 *bp, int reg, u32 *val)
 270 +{
 271 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 272 +               return 0;
 273 +
 274 +       return __b44_readphy(bp, bp->phy_addr, reg, val);
 275 +}
 276 +
 277 +static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
 278  {
 279 -       bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 280 -       bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 281 +       bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
 282 +       bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
 283                              (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
 284 -                            (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 285 +                            (phy_addr << MDIO_DATA_PMD_SHIFT) |
 286                              (reg << MDIO_DATA_RA_SHIFT) |
 287                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
 288                              (val & MDIO_DATA_DATA)));
 289         return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 290  }
 291
 292 +static int b44_writephy(struct b44 *bp, int reg, u32 val)
 293 +{
 294 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 295 +               return 0;
 296 +
 297 +       return __b44_writephy(bp, bp->phy_addr, reg, val);
 298 +}
 299 +
 300 +
 301  /* miilib interface */
 302  /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
 303   * due to code existing before miilib use was added to this driver.
 304 @@ -344,6 +360,9 @@
 305         u32 val;
 306         int err;
 307
 308 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 309 +               return 0;
 310 +
 311         err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
 312         if (err)
 313                 return err;
 314 @@ -367,20 +386,20 @@
 315         bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
 316         bp->flags |= pause_flags;
 317
 318 -       val = br32(bp, B44_RXCONFIG);
 319 +       val = br32(B44_RXCONFIG);
 320         if (pause_flags & B44_FLAG_RX_PAUSE)
 321                 val |= RXCONFIG_FLOW;
 322         else
 323                 val &= ~RXCONFIG_FLOW;
 324 -       bw32(bp, B44_RXCONFIG, val);
 325 +       bw32(B44_RXCONFIG, val);
 326
 327 -       val = br32(bp, B44_MAC_FLOW);
 328 +       val = br32(B44_MAC_FLOW);
 329         if (pause_flags & B44_FLAG_TX_PAUSE)
 330                 val |= (MAC_FLOW_PAUSE_ENAB |
 331                         (0xc0 & MAC_FLOW_RX_HI_WATER));
 332         else
 333                 val &= ~MAC_FLOW_PAUSE_ENAB;
 334 -       bw32(bp, B44_MAC_FLOW, val);
 335 +       bw32(B44_MAC_FLOW, val);
 336  }
 337
 338  static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
 339 @@ -414,6 +433,9 @@
 340         u32 val;
 341         int err;
 342
 343 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 344 +               return 0;
 345 +
 346         if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
 347                 goto out;
 348         if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
 349 @@ -476,11 +498,11 @@
 350
 351         val = &bp->hw_stats.tx_good_octets;
 352         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
 353 -               *val++ += br32(bp, reg);
 354 +               *val++ += br32(reg);
 355         }
 356         val = &bp->hw_stats.rx_good_octets;
 357         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
 358 -               *val++ += br32(bp, reg);
 359 +               *val++ += br32(reg);
 360         }
 361  }
 362
 363 @@ -506,6 +528,19 @@
 364  {
 365         u32 bmsr, aux;
 366
 367 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
 368 +               bp->flags |= B44_FLAG_100_BASE_T;
 369 +               bp->flags |= B44_FLAG_FULL_DUPLEX;
 370 +               if (!netif_carrier_ok(bp->dev)) {
 371 +                       u32 val = br32(B44_TX_CTRL);
 372 +                       val |= TX_CTRL_DUPLEX;
 373 +                       bw32(B44_TX_CTRL, val);
 374 +                       netif_carrier_on(bp->dev);
 375 +                       b44_link_report(bp);
 376 +               }
 377 +               return;
 378 +       }
 379 +
 380         if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
 381             !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
 382             (bmsr != 0xffff)) {
 383 @@ -520,14 +555,14 @@
 384
 385                 if (!netif_carrier_ok(bp->dev) &&
 386                     (bmsr & BMSR_LSTATUS)) {
 387 -                       u32 val = br32(bp, B44_TX_CTRL);
 388 +                       u32 val = br32(B44_TX_CTRL);
 389                         u32 local_adv, remote_adv;
 390
 391                         if (bp->flags & B44_FLAG_FULL_DUPLEX)
 392                                 val |= TX_CTRL_DUPLEX;
 393                         else
 394                                 val &= ~TX_CTRL_DUPLEX;
 395 -                       bw32(bp, B44_TX_CTRL, val);
 396 +                       bw32(B44_TX_CTRL, val);
 397
 398                         if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
 399                             !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
 400 @@ -572,7 +607,7 @@
 401  {
 402         u32 cur, cons;
 403
 404 -       cur  = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
 405 +       cur  = br32(B44_DMATX_STAT) & DMATX_STAT_CDMASK;
 406         cur /= sizeof(struct dma_desc);
 407
 408         /* XXX needs updating when NETIF_F_SG is supported */
 409 @@ -596,7 +631,7 @@
 410             TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
 411                 netif_wake_queue(bp->dev);
 412
 413 -       bw32(bp, B44_GPTIMER, 0);
 414 +       bw32(B44_GPTIMER, 0);
 415  }
 416
 417  /* Works like this.  This chip writes a 'struct rx_header" 30 bytes
 418 @@ -713,7 +748,7 @@
 419         u32 cons, prod;
 420
 421         received = 0;
 422 -       prod  = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
 423 +       prod  = br32(B44_DMARX_STAT) & DMARX_STAT_CDMASK;
 424         prod /= sizeof(struct dma_desc);
 425         cons = bp->rx_cons;
 426
 427 @@ -792,7 +827,7 @@
 428         }
 429
 430         bp->rx_cons = cons;
 431 -       bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
 432 +       bw32(B44_DMARX_PTR, cons * sizeof(struct dma_desc));
 433
 434         return received;
 435  }
 436 @@ -856,8 +891,8 @@
 437
 438         spin_lock_irqsave(&bp->lock, flags);
 439
 440 -       istat = br32(bp, B44_ISTAT);
 441 -       imask = br32(bp, B44_IMASK);
 442 +       istat = br32(B44_ISTAT);
 443 +       imask = br32(B44_IMASK);
 444
 445         /* ??? What the fuck is the purpose of the interrupt mask
 446          * ??? register if we have to mask it out by hand anyways?
 447 @@ -877,8 +912,8 @@
 448                                dev->name);
 449                 }
 450
 451 -               bw32(bp, B44_ISTAT, istat);
 452 -               br32(bp, B44_ISTAT);
 453 +               bw32(B44_ISTAT, istat);
 454 +               br32(B44_ISTAT);
 455         }
 456         spin_unlock_irqrestore(&bp->lock, flags);
 457         return IRQ_RETVAL(handled);
 458 @@ -965,11 +1000,11 @@
 459
 460         wmb();
 461
 462 -       bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
 463 +       bw32(B44_DMATX_PTR, entry * sizeof(struct dma_desc));
 464         if (bp->flags & B44_FLAG_BUGGY_TXPTR)
 465 -               bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
 466 +               bw32(B44_DMATX_PTR, entry * sizeof(struct dma_desc));
 467         if (bp->flags & B44_FLAG_REORDER_BUG)
 468 -               br32(bp, B44_DMATX_PTR);
 469 +               br32(B44_DMATX_PTR);
 470
 471         if (TX_BUFFS_AVAIL(bp) < 1)
 472                 netif_stop_queue(dev);
 473 @@ -1137,32 +1172,35 @@
 474  {
 475         unsigned long reg;
 476
 477 -       bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
 478 +       bw32(B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
 479         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
 480 -               br32(bp, reg);
 481 +               br32(reg);
 482         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
 483 -               br32(bp, reg);
 484 +               br32(reg);
 485  }
 486
 487  /* bp->lock is held. */
 488  static void b44_chip_reset(struct b44 *bp)
 489  {
 490 +       unsigned int sb_clock;
 491 +
 492         if (ssb_is_core_up(bp)) {
 493 -               bw32(bp, B44_RCV_LAZY, 0);
 494 -               bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
 495 +               bw32(B44_RCV_LAZY, 0);
 496 +               bw32(B44_ENET_CTRL, ENET_CTRL_DISABLE);
 497                 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
 498 -               bw32(bp, B44_DMATX_CTRL, 0);
 499 +               bw32(B44_DMATX_CTRL, 0);
 500                 bp->tx_prod = bp->tx_cons = 0;
 501 -               if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
 502 +               if (br32(B44_DMARX_STAT) & DMARX_STAT_EMASK) {
 503                         b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
 504                                      100, 0);
 505                 }
 506 -               bw32(bp, B44_DMARX_CTRL, 0);
 507 +               bw32(B44_DMARX_CTRL, 0);
 508                 bp->rx_prod = bp->rx_cons = 0;
 509         } else {
 510 -               ssb_pci_setup(bp, (bp->core_unit == 0 ?
 511 -                                  SBINTVEC_ENET0 :
 512 -                                  SBINTVEC_ENET1));
 513 +               if (bp->pdev->device != PCI_DEVICE_ID_BCM4713)
 514 +                       ssb_pci_setup(bp, (bp->core_unit == 0 ?
 515 +                                          SBINTVEC_ENET0 :
 516 +                                          SBINTVEC_ENET1));
 517         }
 518
 519         ssb_core_reset(bp);
 520 @@ -1170,20 +1208,26 @@
 521         b44_clear_stats(bp);
 522
 523         /* Make PHY accessible. */
 524 -       bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
 525 -                            (0x0d & MDIO_CTRL_MAXF_MASK)));
 526 -       br32(bp, B44_MDIO_CTRL);
 527 -
 528 -       if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
 529 -               bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
 530 -               br32(bp, B44_ENET_CTRL);
 531 +       if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
 532 +               sb_clock = 100000000; /* 100 MHz */
 533 +       else
 534 +               sb_clock = 62500000; /* 62.5 MHz */
 535 +
 536 +       bw32(B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
 537 +                            (((sb_clock + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
 538 +                            & MDIO_CTRL_MAXF_MASK)));
 539 +       br32(B44_MDIO_CTRL);
 540 +
 541 +       if (!(br32(B44_DEVCTRL) & DEVCTRL_IPP)) {
 542 +               bw32(B44_ENET_CTRL, ENET_CTRL_EPSEL);
 543 +               br32(B44_ENET_CTRL);
 544                 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
 545         } else {
 546 -               u32 val = br32(bp, B44_DEVCTRL);
 547 +               u32 val = br32(B44_DEVCTRL);
 548
 549                 if (val & DEVCTRL_EPR) {
 550 -                       bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
 551 -                       br32(bp, B44_DEVCTRL);
 552 +                       bw32(B44_DEVCTRL, (val & ~DEVCTRL_EPR));
 553 +                       br32(B44_DEVCTRL);
 554                         udelay(100);
 555                 }
 556                 bp->flags |= B44_FLAG_INTERNAL_PHY;
 557 @@ -1200,13 +1244,13 @@
 558  /* bp->lock is held. */
 559  static void __b44_set_mac_addr(struct b44 *bp)
 560  {
 561 -       bw32(bp, B44_CAM_CTRL, 0);
 562 +       bw32(B44_CAM_CTRL, 0);
 563         if (!(bp->dev->flags & IFF_PROMISC)) {
 564                 u32 val;
 565
 566                 __b44_cam_write(bp, bp->dev->dev_addr, 0);
 567 -               val = br32(bp, B44_CAM_CTRL);
 568 -               bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
 569 +               val = br32(B44_CAM_CTRL);
 570 +               bw32(B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
 571         }
 572  }
 573
 574 @@ -1240,30 +1284,30 @@
 575         b44_setup_phy(bp);
 576
 577         /* Enable CRC32, set proper LED modes and power on PHY */
 578 -       bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
 579 -       bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
 580 +       bw32(B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
 581 +       bw32(B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
 582
 583         /* This sets the MAC address too.  */
 584         __b44_set_rx_mode(bp->dev);
 585
 586         /* MTU + eth header + possible VLAN tag + struct rx_header */
 587 -       bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
 588 -       bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
 589 +       bw32(B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
 590 +       bw32(B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
 591
 592 -       bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
 593 -       bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
 594 -       bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
 595 -       bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
 596 +       bw32(B44_TX_WMARK, 56); /* XXX magic */
 597 +       bw32(B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
 598 +       bw32(B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
 599 +       bw32(B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
 600                               (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
 601 -       bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
 602 +       bw32(B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
 603
 604 -       bw32(bp, B44_DMARX_PTR, bp->rx_pending);
 605 +       bw32(B44_DMARX_PTR, bp->rx_pending);
 606         bp->rx_prod = bp->rx_pending;
 607
 608 -       bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
 609 +       bw32(B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
 610
 611 -       val = br32(bp, B44_ENET_CTRL);
 612 -       bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
 613 +       val = br32(B44_ENET_CTRL);
 614 +       bw32(B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
 615  }
 616
 617  static int b44_open(struct net_device *dev)
 618 @@ -1419,11 +1463,11 @@
 619         int i=0;
 620         unsigned char zero[6] = {0,0,0,0,0,0};
 621
 622 -       val = br32(bp, B44_RXCONFIG);
 623 +       val = br32(B44_RXCONFIG);
 624         val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
 625         if (dev->flags & IFF_PROMISC) {
 626                 val |= RXCONFIG_PROMISC;
 627 -               bw32(bp, B44_RXCONFIG, val);
 628 +               bw32(B44_RXCONFIG, val);
 629         } else {
 630                 __b44_set_mac_addr(bp);
 631
 632 @@ -1435,9 +1479,9 @@
 633                 for(;i<64;i++) {
 634                         __b44_cam_write(bp, zero, i);
 635                 }
 636 -               bw32(bp, B44_RXCONFIG, val);
 637 -               val = br32(bp, B44_CAM_CTRL);
 638 -               bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
 639 +               bw32(B44_RXCONFIG, val);
 640 +               val = br32(B44_CAM_CTRL);
 641 +               bw32(B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
 642         }
 643  }
 644
 645 @@ -1678,17 +1722,288 @@
 646         .set_msglevel           = b44_set_msglevel,
 647  };
 648
 649 +static int b44_ethtool_ioctl (struct net_device *dev, void __user *useraddr)
 650 +{
 651 +       struct b44 *bp = dev->priv;
 652 +       struct pci_dev *pci_dev = bp->pdev;
 653 +       u32 ethcmd;
 654 +
 655 +       if (copy_from_user (&ethcmd, useraddr, sizeof (ethcmd)))
 656 +               return -EFAULT;
 657 +
 658 +       switch (ethcmd) {
 659 +       case ETHTOOL_GDRVINFO: {
 660 +               struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
 661 +               strcpy (info.driver, DRV_MODULE_NAME);
 662 +               strcpy (info.version, DRV_MODULE_VERSION);
 663 +               memset(&info.fw_version, 0, sizeof(info.fw_version));
 664 +               strcpy (info.bus_info, pci_name(pci_dev));
 665 +               info.eedump_len = 0;
 666 +               info.regdump_len = 0;
 667 +               if (copy_to_user (useraddr, &info, sizeof (info)))
 668 +                       return -EFAULT;
 669 +               return 0;
 670 +       }
 671 +
 672 +       case ETHTOOL_GSET: {
 673 +               struct ethtool_cmd cmd = { ETHTOOL_GSET };
 674 +
 675 +               if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
 676 +                       return -EAGAIN;
 677 +               cmd.supported = (SUPPORTED_Autoneg);
 678 +               cmd.supported |= (SUPPORTED_100baseT_Half |
 679 +                                 SUPPORTED_100baseT_Full |
 680 +                                 SUPPORTED_10baseT_Half |
 681 +                                 SUPPORTED_10baseT_Full |
 682 +                                 SUPPORTED_MII);
 683 +
 684 +               cmd.advertising = 0;
 685 +               if (bp->flags & B44_FLAG_ADV_10HALF)
 686 +                       cmd.advertising |= ADVERTISE_10HALF;
 687 +               if (bp->flags & B44_FLAG_ADV_10FULL)
 688 +                       cmd.advertising |= ADVERTISE_10FULL;
 689 +               if (bp->flags & B44_FLAG_ADV_100HALF)
 690 +                       cmd.advertising |= ADVERTISE_100HALF;
 691 +               if (bp->flags & B44_FLAG_ADV_100FULL)
 692 +                       cmd.advertising |= ADVERTISE_100FULL;
 693 +               cmd.advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 694 +               cmd.speed = (bp->flags & B44_FLAG_100_BASE_T) ?
 695 +                       SPEED_100 : SPEED_10;
 696 +               cmd.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
 697 +                       DUPLEX_FULL : DUPLEX_HALF;
 698 +               cmd.port = 0;
 699 +               cmd.phy_address = bp->phy_addr;
 700 +               cmd.transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
 701 +                       XCVR_INTERNAL : XCVR_EXTERNAL;
 702 +               cmd.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
 703 +                       AUTONEG_DISABLE : AUTONEG_ENABLE;
 704 +               cmd.maxtxpkt = 0;
 705 +               cmd.maxrxpkt = 0;
 706 +               if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
 707 +                       return -EFAULT;
 708 +               return 0;
 709 +       }
 710 +       case ETHTOOL_SSET: {
 711 +               struct ethtool_cmd cmd;
 712 +
 713 +               if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
 714 +                       return -EAGAIN;
 715 +
 716 +               if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
 717 +                       return -EFAULT;
 718 +
 719 +               /* We do not support gigabit. */
 720 +               if (cmd.autoneg == AUTONEG_ENABLE) {
 721 +                       if (cmd.advertising &
 722 +                           (ADVERTISED_1000baseT_Half |
 723 +                            ADVERTISED_1000baseT_Full))
 724 +                               return -EINVAL;
 725 +               } else if ((cmd.speed != SPEED_100 &&
 726 +                           cmd.speed != SPEED_10) ||
 727 +                          (cmd.duplex != DUPLEX_HALF &&
 728 +                           cmd.duplex != DUPLEX_FULL)) {
 729 +                               return -EINVAL;
 730 +               }
 731 +
 732 +               spin_lock_irq(&bp->lock);
 733 +
 734 +               if (cmd.autoneg == AUTONEG_ENABLE) {
 735 +                       bp->flags &= ~B44_FLAG_FORCE_LINK;
 736 +                       bp->flags &= ~(B44_FLAG_ADV_10HALF |
 737 +                                      B44_FLAG_ADV_10FULL |
 738 +                                      B44_FLAG_ADV_100HALF |
 739 +                                      B44_FLAG_ADV_100FULL);
 740 +                       if (cmd.advertising & ADVERTISE_10HALF)
 741 +                               bp->flags |= B44_FLAG_ADV_10HALF;
 742 +                       if (cmd.advertising & ADVERTISE_10FULL)
 743 +                               bp->flags |= B44_FLAG_ADV_10FULL;
 744 +                       if (cmd.advertising & ADVERTISE_100HALF)
 745 +                               bp->flags |= B44_FLAG_ADV_100HALF;
 746 +                       if (cmd.advertising & ADVERTISE_100FULL)
 747 +                               bp->flags |= B44_FLAG_ADV_100FULL;
 748 +               } else {
 749 +                       bp->flags |= B44_FLAG_FORCE_LINK;
 750 +                       if (cmd.speed == SPEED_100)
 751 +                               bp->flags |= B44_FLAG_100_BASE_T;
 752 +                       if (cmd.duplex == DUPLEX_FULL)
 753 +                               bp->flags |= B44_FLAG_FULL_DUPLEX;
 754 +               }
 755 +
 756 +               b44_setup_phy(bp);
 757 +
 758 +               spin_unlock_irq(&bp->lock);
 759 +
 760 +               return 0;
 761 +       }
 762 +
 763 +       case ETHTOOL_GMSGLVL: {
 764 +               struct ethtool_value edata = { ETHTOOL_GMSGLVL };
 765 +               edata.data = bp->msg_enable;
 766 +               if (copy_to_user(useraddr, &edata, sizeof(edata)))
 767 +                       return -EFAULT;
 768 +               return 0;
 769 +       }
 770 +       case ETHTOOL_SMSGLVL: {
 771 +               struct ethtool_value edata;
 772 +               if (copy_from_user(&edata, useraddr, sizeof(edata)))
 773 +                       return -EFAULT;
 774 +               bp->msg_enable = edata.data;
 775 +               return 0;
 776 +       }
 777 +       case ETHTOOL_NWAY_RST: {
 778 +               u32 bmcr;
 779 +               int r;
 780 +
 781 +               spin_lock_irq(&bp->lock);
 782 +               b44_readphy(bp, MII_BMCR, &bmcr);
 783 +               b44_readphy(bp, MII_BMCR, &bmcr);
 784 +               r = -EINVAL;
 785 +               if (bmcr & BMCR_ANENABLE) {
 786 +                       b44_writephy(bp, MII_BMCR,
 787 +                                    bmcr | BMCR_ANRESTART);
 788 +                       r = 0;
 789 +               }
 790 +               spin_unlock_irq(&bp->lock);
 791 +
 792 +               return r;
 793 +       }
 794 +       case ETHTOOL_GLINK: {
 795 +               struct ethtool_value edata = { ETHTOOL_GLINK };
 796 +               edata.data = netif_carrier_ok(bp->dev) ? 1 : 0;
 797 +               if (copy_to_user(useraddr, &edata, sizeof(edata)))
 798 +                       return -EFAULT;
 799 +               return 0;
 800 +       }
 801 +       case ETHTOOL_GRINGPARAM: {
 802 +               struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM };
 803 +
 804 +               ering.rx_max_pending = B44_RX_RING_SIZE - 1;
 805 +               ering.rx_pending = bp->rx_pending;
 806 +
 807 +               /* XXX ethtool lacks a tx_max_pending, oops... */
 808 +
 809 +               if (copy_to_user(useraddr, &ering, sizeof(ering)))
 810 +                       return -EFAULT;
 811 +               return 0;
 812 +       }
 813 +       case ETHTOOL_SRINGPARAM: {
 814 +               struct ethtool_ringparam ering;
 815 +
 816 +               if (copy_from_user(&ering, useraddr, sizeof(ering)))
 817 +                       return -EFAULT;
 818 +
 819 +               if ((ering.rx_pending > B44_RX_RING_SIZE - 1) ||
 820 +                   (ering.rx_mini_pending != 0) ||
 821 +                   (ering.rx_jumbo_pending != 0) ||
 822 +                   (ering.tx_pending > B44_TX_RING_SIZE - 1))
 823 +                       return -EINVAL;
 824 +
 825 +               spin_lock_irq(&bp->lock);
 826 +
 827 +               bp->rx_pending = ering.rx_pending;
 828 +               bp->tx_pending = ering.tx_pending;
 829 +
 830 +               b44_halt(bp);
 831 +               b44_init_rings(bp);
 832 +               b44_init_hw(bp);
 833 +               netif_wake_queue(bp->dev);
 834 +               spin_unlock_irq(&bp->lock);
 835 +
 836 +               b44_enable_ints(bp);
 837 +
 838 +               return 0;
 839 +       }
 840 +       case ETHTOOL_GPAUSEPARAM: {
 841 +               struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
 842 +
 843 +               epause.autoneg =
 844 +                       (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
 845 +               epause.rx_pause =
 846 +                       (bp->flags & B44_FLAG_RX_PAUSE) != 0;
 847 +               epause.tx_pause =
 848 +                       (bp->flags & B44_FLAG_TX_PAUSE) != 0;
 849 +               if (copy_to_user(useraddr, &epause, sizeof(epause)))
 850 +                       return -EFAULT;
 851 +               return 0;
 852 +       }
 853 +       case ETHTOOL_SPAUSEPARAM: {
 854 +               struct ethtool_pauseparam epause;
 855 +
 856 +               if (copy_from_user(&epause, useraddr, sizeof(epause)))
 857 +                       return -EFAULT;
 858 +
 859 +               spin_lock_irq(&bp->lock);
 860 +               if (epause.autoneg)
 861 +                       bp->flags |= B44_FLAG_PAUSE_AUTO;
 862 +               else
 863 +                       bp->flags &= ~B44_FLAG_PAUSE_AUTO;
 864 +               if (epause.rx_pause)
 865 +                       bp->flags |= B44_FLAG_RX_PAUSE;
 866 +               else
 867 +                       bp->flags &= ~B44_FLAG_RX_PAUSE;
 868 +               if (epause.tx_pause)
 869 +                       bp->flags |= B44_FLAG_TX_PAUSE;
 870 +               else
 871 +                       bp->flags &= ~B44_FLAG_TX_PAUSE;
 872 +               if (bp->flags & B44_FLAG_PAUSE_AUTO) {
 873 +                       b44_halt(bp);
 874 +                       b44_init_rings(bp);
 875 +                       b44_init_hw(bp);
 876 +               } else {
 877 +                       __b44_set_flow_ctrl(bp, bp->flags);
 878 +               }
 879 +               spin_unlock_irq(&bp->lock);
 880 +
 881 +               b44_enable_ints(bp);
 882 +
 883 +               return 0;
 884 +       }
 885 +       };
 886 +
 887 +       return -EOPNOTSUPP;
 888 +}
 889 +
 890  static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 891  {
 892         struct mii_ioctl_data *data = if_mii(ifr);
 893         struct b44 *bp = netdev_priv(dev);
 894         int err;
 895
 896 -       spin_lock_irq(&bp->lock);
 897 -       err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
 898 -       spin_unlock_irq(&bp->lock);
 899 +       switch (cmd) {
 900 +       case SIOCETHTOOL:
 901 +               return b44_ethtool_ioctl(dev, (void __user*) ifr->ifr_data);
 902 +
 903 +       case SIOCGMIIPHY:
 904 +               data->phy_id = bp->phy_addr;
 905 +
 906 +               /* fallthru */
 907 +       case SIOCGMIIREG: {
 908 +               u32 mii_regval;
 909
 910 -       return err;
 911 +               spin_lock_irq(&bp->lock);
 912 +               err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
 913 +               spin_unlock_irq(&bp->lock);
 914 +
 915 +               data->val_out = mii_regval;
 916 +
 917 +               return err;
 918 +       }
 919 +
 920 +       case SIOCSMIIREG:
 921 +               if (!capable(CAP_NET_ADMIN))
 922 +                       return -EPERM;
 923 +
 924 +               spin_lock_irq(&bp->lock);
 925 +               err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
 926 +               spin_unlock_irq(&bp->lock);
 927 +
 928 +               return err;
 929 +
 930 +       default:
 931 +               /* do nothing */
 932 +               break;
 933 +       };
 934 +       return -EOPNOTSUPP;
 935  }
 936
 937  /* Read 128-bytes of EEPROM. */
 938 @@ -1698,7 +2013,7 @@
 939         u16 *ptr = (u16 *) data;
 940
 941         for (i = 0; i < 128; i += 2)
 942 -               ptr[i / 2] = readw(bp->regs + 4096 + i);
 943 +               ptr[i / 2] = readw((void *)bp->regs + 4096 + i);
 944
 945         return 0;
 946  }
 947 @@ -1707,19 +2022,41 @@
 948  {
 949         u8 eeprom[128];
 950         int err;
 951 +       unsigned long flags;
 952
 953 -       err = b44_read_eeprom(bp, &eeprom[0]);
 954 -       if (err)
 955 -               goto out;
 956 -
 957 -       bp->dev->dev_addr[0] = eeprom[79];
 958 -       bp->dev->dev_addr[1] = eeprom[78];
 959 -       bp->dev->dev_addr[2] = eeprom[81];
 960 -       bp->dev->dev_addr[3] = eeprom[80];
 961 -       bp->dev->dev_addr[4] = eeprom[83];
 962 -       bp->dev->dev_addr[5] = eeprom[82];
 963 -
 964 -       bp->phy_addr = eeprom[90] & 0x1f;
 965 +       if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) {
 966 +               /*
 967 +                * BCM47xx boards don't have a EEPROM. The MAC is stored in
 968 +                * a NVRAM area somewhere in the flash memory. As we don't
 969 +                * know the location and/or the format of the NVRAM area
 970 +                * here, we simply rely on the bootloader to write the
 971 +                * MAC into the CAM.
 972 +                */
 973 +               spin_lock_irqsave(&bp->lock, flags);
 974 +               __b44_cam_read(bp, bp->dev->dev_addr, 0);
 975 +               spin_unlock_irqrestore(&bp->lock, flags);
 976 +
 977 +               /*
 978 +                * BCM47xx boards don't have a PHY. Usually there is a switch
 979 +                * chip with multiple PHYs connected to the PHY port.
 980 +                */
 981 +               bp->phy_addr = B44_PHY_ADDR_NO_PHY;
 982 +               bp->dma_offset = 0;
 983 +       } else {
 984 +               err = b44_read_eeprom(bp, &eeprom[0]);
 985 +               if (err)
 986 +                       return err;
 987 +
 988 +               bp->dev->dev_addr[0] = eeprom[79];
 989 +               bp->dev->dev_addr[1] = eeprom[78];
 990 +               bp->dev->dev_addr[2] = eeprom[81];
 991 +               bp->dev->dev_addr[3] = eeprom[80];
 992 +               bp->dev->dev_addr[4] = eeprom[83];
 993 +               bp->dev->dev_addr[5] = eeprom[82];
 994 +
 995 +               bp->phy_addr = eeprom[90] & 0x1f;
 996 +               bp->dma_offset = SB_PCI_DMA;
 997 +       }
 998
 999         /* With this, plus the rx_header prepended to the data by the
1000          * hardware, we'll land the ethernet header on a 2-byte boundary.
1001 @@ -1729,13 +2066,12 @@
1002         bp->imask = IMASK_DEF;
1003
1004         bp->core_unit = ssb_core_unit(bp);
1005 -       bp->dma_offset = SB_PCI_DMA;
1006
1007         /* XXX - really required?
1008            bp->flags |= B44_FLAG_BUGGY_TXPTR;
1009           */
1010 -out:
1011 -       return err;
1012 +
1013 +       return 0;
1014  }
1015
1016  static int __devinit b44_init_one(struct pci_dev *pdev,
1017 @@ -1813,7 +2149,7 @@
1018
1019         spin_lock_init(&bp->lock);
1020
1021 -       bp->regs = ioremap(b44reg_base, b44reg_len);
1022 +       bp->regs = (unsigned long) ioremap(b44reg_base, b44reg_len);
1023         if (bp->regs == 0UL) {
1024                 printk(KERN_ERR PFX "Cannot map device registers, "
1025                        "aborting.\n");
1026 @@ -1874,15 +2210,21 @@
1027
1028         pci_save_state(bp->pdev);
1029
1030 -       printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
1031 +       printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name,
1032 +               (pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400");
1033         for (i = 0; i < 6; i++)
1034                 printk("%2.2x%c", dev->dev_addr[i],
1035                        i == 5 ? '\n' : ':');
1036
1037 +       /* Initialize phy */
1038 +       spin_lock_irq(&bp->lock);
1039 +       b44_chip_reset(bp);
1040 +       spin_unlock_irq(&bp->lock);
1041 +
1042         return 0;
1043
1044  err_out_iounmap:
1045 -       iounmap(bp->regs);
1046 +       iounmap((void *) bp->regs);
1047
1048  err_out_free_dev:
1049         free_netdev(dev);
1050 @@ -1904,7 +2246,7 @@
1051                 struct b44 *bp = netdev_priv(dev);
1052
1053                 unregister_netdev(dev);
1054 -               iounmap(bp->regs);
1055 +               iounmap((void *) bp->regs);
1056                 free_netdev(dev);
1057                 pci_release_regions(pdev);
1058                 pci_disable_device(pdev);
1059 diff -ur linux-2.6.14.3/drivers/net/b44.h linux-2.6.14.3-openwrt/drivers/net/b44.h
1060 --- linux-2.6.14.3/drivers/net/b44.h    2005-11-24 23:10:21.000000000 +0100
1061 +++ linux-2.6.14.3-openwrt/drivers/net/b44.h    2005-12-08 13:24:35.000000000 +0100
1062 @@ -292,6 +292,9 @@
1063  #define SSB_PCI_MASK1          0xfc000000
1064  #define SSB_PCI_MASK2          0xc0000000
1065
1066 +#define br32(REG)      readl((void *)bp->regs + (REG))
1067 +#define bw32(REG,VAL)  writel((VAL), (void *)bp->regs + (REG))
1068 +
1069  /* 4400 PHY registers */
1070  #define B44_MII_AUXCTRL                24      /* Auxiliary Control */
1071  #define  MII_AUXCTRL_DUPLEX    0x0001  /* Full Duplex */
1072 @@ -345,6 +348,8 @@
1073  };
1074
1075  #define B44_MCAST_TABLE_SIZE   32
1076 +#define B44_PHY_ADDR_NO_PHY    30
1077 +#define B44_MDC_RATIO          5000000
1078
1079  /* SW copy of device statistics, kept up to date by periodic timer
1080   * which probes HW values.  Must have same relative layout as HW
1081 @@ -410,7 +415,7 @@
1082         struct net_device_stats stats;
1083         struct b44_hw_stats     hw_stats;
1084
1085 -       void __iomem            *regs;
1086 +       unsigned long           regs;
1087         struct pci_dev          *pdev;
1088         struct net_device       *dev;
1089