target/linux/gemini/patches-3.3/120-net-add-gemini-gmac-driver.patch

   1 --- /dev/null
   2 +++ b/arch/arm/mach-gemini/include/mach/gmac.h
   3 @@ -0,0 +1,21 @@
   4 +/*
   5 + * Gemini GMAC specific defines
   6 + *
   7 + * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
   8 + *
   9 + * This program is free software; you can redistribute it and/or modify
  10 + * it under the terms of the GNU General Public License as published by
  11 + * the Free Software Foundation; either version 2 of the License, or
  12 + * (at your option) any later version.
  13 + */
  14 +#ifndef __MACH_GMAC_H__
  15 +#define __MACH_GMAC_H__
  16 +
  17 +#include <linux/phy.h>
  18 +
  19 +struct gemini_gmac_platform_data {
  20 +       char *bus_id[2]; /* NULL means that this port is not used */
  21 +       phy_interface_t interface[2];
  22 +};
  23 +
  24 +#endif /* __MACH_GMAC_H__ */
  25 --- /dev/null
  26 +++ b/drivers/net/gemini_negmac/gm_gmac.c
  27 @@ -0,0 +1,1351 @@
  28 +/*
  29 + *  Ethernet device driver for Gemini SoC.
  30 + *
  31 + *  Copyright (C) 2006, Storlink, Corp.
  32 + *  Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
  33 + *
  34 + * This program is free software; you can redistribute it and/or modify
  35 + * it under the terms of the GNU General Public License as published by
  36 + * the Free Software Foundation; either version 2 of the License, or
  37 + * (at your option) any later version.
  38 + */
  39 +#include <linux/module.h>
  40 +#include <linux/kernel.h>
  41 +#include <linux/platform_device.h>
  42 +#include <linux/slab.h>
  43 +#include <linux/mm.h>
  44 +#include <linux/compiler.h>
  45 +#include <linux/dma-mapping.h>
  46 +#include <linux/init.h>
  47 +#include <linux/ioport.h>
  48 +#include <linux/netdevice.h>
  49 +#include <linux/etherdevice.h>
  50 +#include <linux/rtnetlink.h>
  51 +#include <linux/delay.h>
  52 +#include <linux/ethtool.h>
  53 +#include <linux/mii.h>
  54 +#include <linux/phy.h>
  55 +#include <linux/irq.h>
  56 +#include <linux/interrupt.h>
  57 +#include <linux/completion.h>
  58 +#include <linux/kthread.h>
  59 +#include <linux/io.h>
  60 +#include <mach/hardware.h>
  61 +#include <linux/semaphore.h>
  62 +#include <mach/irqs.h>
  63 +#include <linux/skbuff.h>
  64 +#include <linux/in.h>
  65 +#include <linux/ip.h>
  66 +#include <linux/tcp.h>
  67 +#include <linux/udp.h>
  68 +#include <mach/gmac.h>
  69 +
  70 +#include "gm_gmac.h"
  71 +
  72 +/* #define GMAX_TX_INTR_DISABLED */
  73 +/* #define DO_HW_CHKSUM */
  74 +/* #define ENABLE_TSO */
  75 +#define GMAC_USE_TXQ0
  76 +/* #define GMAC_LEN_1_2_ISSUE */
  77 +
  78 +#define DEFAULT_RXQ_MAX_CNT                    256
  79 +
  80 +/* define chip information */
  81 +#define DRV_VERSION                    "0.2"
  82 +#define SL351x_DRIVER_NAME             "Gemini Ethernet driver " DRV_VERSION
  83 +
  84 +#ifdef GMAC_LEN_1_2_ISSUE
  85 +       #define _DEBUG_PREFETCH_NUM     256
  86 +static int     _debug_prefetch_cnt;
  87 +static char _debug_prefetch_buf[_DEBUG_PREFETCH_NUM][4] __attribute__((aligned(4)));
  88 +#endif
  89 +
  90 +static inline void gmac_write_reg(void __iomem *base, unsigned int offset,
  91 +                                 unsigned int data, unsigned int bit_mask)
  92 +{
  93 +       unsigned int reg_val;
  94 +
  95 +       reg_val = (__raw_readl(base + offset) & (~bit_mask)) | (data & bit_mask);
  96 +       __raw_writel(reg_val, base + offset);
  97 +}
  98 +
  99 +/*----------------------------------------------------------------------
 100 +*      toe_init_free_queue
 101 +*      (1) Initialize the Free Queue Descriptor Base Address & size
 102 +*              Register: TOE_GLOBAL_BASE + 0x0004
 103 +*      (2) Initialize DMA Read/Write pointer for
 104 +*              SW Free Queue and HW Free Queue
 105 +*      (3)     Initialize DMA Descriptors for
 106 +*              SW Free Queue and HW Free Queue,
 107 +*----------------------------------------------------------------------*/
 108 +static void toe_init_free_queue(struct toe_private *toe)
 109 +{
 110 +       int                     i;
 111 +       DMA_RWPTR_T             rwptr_reg;
 112 +       void                    *desc_buf;
 113 +       GMAC_RXDESC_T           *sw_desc_ptr;
 114 +       struct sk_buff          *skb;
 115 +
 116 +       desc_buf = dma_alloc_coherent(toe->dev, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),
 117 +                                     &toe->sw_freeq_desc_base_dma, GFP_KERNEL);
 118 +       sw_desc_ptr = (GMAC_RXDESC_T *)desc_buf;
 119 +       if (!desc_buf) {
 120 +               dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
 121 +               return;
 122 +       }
 123 +       memset(desc_buf, 0, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T));
 124 +
 125 +       /* DMA Queue Base & Size */
 126 +       __raw_writel((toe->sw_freeq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_SW_FREEQ_DESC_POWER,
 127 +                       toe->global_base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
 128 +
 129 +       /* init descriptor base */
 130 +       toe->swfq_desc_base = (unsigned int)desc_buf;
 131 +
 132 +       /* SW Free Queue Descriptors */
 133 +       for (i = 0; i < TOE_SW_FREEQ_DESC_NUM; i++) {
 134 +               sw_desc_ptr->word0.bits.buffer_size = SW_RX_BUF_SIZE;
 135 +               skb = dev_alloc_skb(SW_RX_BUF_SIZE);    /* allocate socket buffer */
 136 +               if (!skb) {
 137 +                       dev_err(toe->dev, "%s::skb buffer allocation fail\n", __func__);
 138 +                       return;
 139 +               }
 140 +               REG32(skb->data) = (unsigned int)skb;
 141 +               skb_reserve(skb, SKB_RESERVE_BYTES);
 142 +               sw_desc_ptr->word2.buf_adr = dma_map_single(toe->dev, skb->data,
 143 +                                       SW_RX_BUF_SIZE - SKB_RESERVE_BYTES,
 144 +                                       DMA_FROM_DEVICE);
 145 +               sw_desc_ptr++;
 146 +       }
 147 +
 148 +       dma_sync_single_for_device(toe->dev, toe->sw_freeq_desc_base_dma,
 149 +                               TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),
 150 +                               DMA_TO_DEVICE);
 151 +
 152 +       /* SW Free Queue Read/Write Pointer */
 153 +       rwptr_reg.bits.wptr = TOE_SW_FREEQ_DESC_NUM - 1;
 154 +       rwptr_reg.bits.rptr = 0;
 155 +       __raw_writel(rwptr_reg.bits32, toe->global_base + GLOBAL_SWFQ_RWPTR_REG);
 156 +
 157 +       /* DMA Queue Base & Size */
 158 +       __raw_writel(TOE_HW_FREEQ_DESC_POWER,
 159 +               toe->global_base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
 160 +       rwptr_reg.bits.wptr = TOE_HW_FREEQ_DESC_NUM - 1;
 161 +       rwptr_reg.bits.rptr = 0;
 162 +       __raw_writel(rwptr_reg.bits32, toe->global_base + GLOBAL_HWFQ_RWPTR_REG);
 163 +}
 164 +
 165 +/*----------------------------------------------------------------------
 166 +*      toe_init_swtx_queue
 167 +*      (2) Initialize the GMAC 0/1 SW TXQ Queue Descriptor Base Address & sizeup
 168 +*              GMAC_SW_TX_QUEUE_BASE_REG(0x0050)
 169 +*      (2) Initialize DMA Read/Write pointer for
 170 +*              GMAC 0/1 SW TX Q0-5
 171 +*----------------------------------------------------------------------*/
 172 +static void toe_init_swtx_queue(struct net_device *dev)
 173 +{
 174 +       int                     i;
 175 +       struct gmac_private     *gmac = netdev_priv(dev);
 176 +       struct toe_private      *toe = dev->ml_priv;
 177 +       DMA_RWPTR_T             rwptr_reg;
 178 +       unsigned int            rwptr_addr;
 179 +       void                    *desc_buf;
 180 +       unsigned int            offset;
 181 +
 182 +       desc_buf = dma_alloc_coherent(toe->dev, TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),
 183 +                                     &gmac->swtxq_desc_base_dma, GFP_KERNEL);
 184 +       gmac->swtxq_desc_base = (unsigned int)desc_buf;
 185 +       if (!desc_buf) {
 186 +               dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
 187 +               return;
 188 +       }
 189 +       memset(desc_buf, 0, TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
 190 +       dma_sync_single_for_device(toe->dev, gmac->swtxq_desc_base_dma,
 191 +                               TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),
 192 +                               DMA_TO_DEVICE);
 193 +       __raw_writel((gmac->swtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC_SWTXQ_DESC_POWER,
 194 +                       gmac->dma_base_addr + GMAC_SW_TX_QUEUE_BASE_REG);
 195 +
 196 +       /* GMAC0 SW TX Q0-Q5 */
 197 +       offset = 0;
 198 +       rwptr_reg.bits.wptr = 0;
 199 +       rwptr_reg.bits.rptr = 0;
 200 +       rwptr_addr = gmac->dma_base_addr + GMAC_SW_TX_QUEUE0_PTR_REG;
 201 +       for (i = 0; i < TOE_SW_TXQ_NUM; i++) {
 202 +               gmac->swtxq[i].rwptr_reg = rwptr_addr;
 203 +               gmac->swtxq[i].desc_base_dma = (unsigned int)gmac->swtxq_desc_base_dma + offset;
 204 +               gmac->swtxq[i].desc_base = (unsigned int)desc_buf + offset;
 205 +               offset += TOE_GMAC_SWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
 206 +               __raw_writel(rwptr_reg.bits32, rwptr_addr);
 207 +               rwptr_addr += 4;
 208 +       }
 209 +}
 210 +
 211 +/*----------------------------------------------------------------------
 212 +*      toe_init_default_queue
 213 +*      (1) Initialize the default 0/1 Queue Header
 214 +*              Register: TOE_DEFAULT_Q0_HDR_BASE (0x60002000)
 215 +*                        TOE_DEFAULT_Q1_HDR_BASE (0x60002008)
 216 +*      (2)     Initialize Descriptors of Default Queue 0/1
 217 +*----------------------------------------------------------------------*/
 218 +static void toe_init_default_queue(struct net_device *dev)
 219 +{
 220 +       struct gmac_private     *gmac = netdev_priv(dev);
 221 +       struct toe_private      *toe = dev->ml_priv;
 222 +       volatile NONTOE_QHDR_T  *qhdr;
 223 +       GMAC_RXDESC_T           *desc_ptr;
 224 +
 225 +       desc_ptr = dma_alloc_coherent(toe->dev, TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T),
 226 +                                     &gmac->default_desc_base_dma, GFP_KERNEL);
 227 +       if (!desc_ptr) {
 228 +               dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
 229 +               return;
 230 +       }
 231 +       memset(desc_ptr, 0, TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T));
 232 +       dma_sync_single_for_device(toe->dev, gmac->default_desc_base_dma,
 233 +                       TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T),
 234 +                       DMA_TO_DEVICE);
 235 +       gmac->default_desc_base = (unsigned int)desc_ptr;
 236 +       qhdr = (volatile NONTOE_QHDR_T *)(toe->global_base + TOE_DEFAULT_Q_HDR_BASE(gmac->port_id));
 237 +       qhdr->word0.base_size = ((unsigned int)gmac->default_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_DEFAULT_Q_DESC_POWER;
 238 +       qhdr->word1.bits32 = 0;
 239 +       gmac->default_qhdr = (NONTOE_QHDR_T *)qhdr;
 240 +}
 241 +
 242 +/*----------------------------------------------------------------------
 243 +*      toe_init_interrupt_config
 244 +*      Interrupt Select Registers are used to map interrupt to int0 or int1
 245 +*      Int0 and int1 are wired to CPU 0/1 GMAC 0/1
 246 +*      Interrupt Device Inteface data are used to pass device info to
 247 +*              upper device driver or store status/statistics
 248 +*      ISR handler
 249 +*              (1) If status bit ON but masked, the prinf error message (bug issue)
 250 +*              (2) If select bits are for me, handle it, else skip to let
 251 +*                      the other ISR handles it.
 252 +*  Notes:
 253 +*              GMACx init routine (for eCOS) or open routine (for Linux)
 254 +*              enable the interrupt bits only which are selected for it.
 255 +*
 256 +*      Default Setting:
 257 +*              GMAC0 intr bits ------> int0 ----> eth0
 258 +*              GMAC1 intr bits ------> int1 ----> eth1
 259 +*              TOE intr -------------> int0 ----> eth0
 260 +*              Classification Intr --> int0 ----> eth0
 261 +*              Default Q0 -----------> int0 ----> eth0
 262 +*              Default Q1 -----------> int1 ----> eth1
 263 +*----------------------------------------------------------------------*/
 264 +static void toe_init_interrupt_config(struct toe_private *toe)
 265 +{
 266 +       /* clear all status bits */
 267 +       __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
 268 +       __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
 269 +       __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
 270 +       __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
 271 +       __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
 272 +
 273 +       /* Init select registers */
 274 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
 275 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
 276 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
 277 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
 278 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
 279 +
 280 +       /* disable all interrupt */
 281 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_0_REG);
 282 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_1_REG);
 283 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_2_REG);
 284 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_3_REG);
 285 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_4_REG);
 286 +}
 287 +
 288 +static void toe_gmac_hw_start(struct gmac_private *gmac)
 289 +{
 290 +       GMAC_DMA_CTRL_T dma_ctrl;
 291 +
 292 +       /* program dma control register */
 293 +       dma_ctrl.bits32 = __raw_readl(gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
 294 +       dma_ctrl.bits.rd_enable = 1;
 295 +       dma_ctrl.bits.td_enable = 1;
 296 +       dma_ctrl.bits.loopback = 0;
 297 +       dma_ctrl.bits.drop_small_ack = 0;
 298 +       dma_ctrl.bits.rd_prot = 0;
 299 +       dma_ctrl.bits.rd_burst_size = 3;
 300 +       dma_ctrl.bits.rd_insert_bytes = RX_INSERT_BYTES;
 301 +       dma_ctrl.bits.rd_bus = 3;
 302 +       dma_ctrl.bits.td_prot = 0;
 303 +       dma_ctrl.bits.td_burst_size = 3;
 304 +       dma_ctrl.bits.td_bus = 3;
 305 +
 306 +       __raw_writel(dma_ctrl.bits32, gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
 307 +}
 308 +
 309 +static void toe_gmac_hw_stop(struct gmac_private *gmac)
 310 +{
 311 +       GMAC_DMA_CTRL_T dma_ctrl;
 312 +
 313 +       /* program dma control register */
 314 +       dma_ctrl.bits32 = __raw_readl(gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
 315 +       dma_ctrl.bits.rd_enable = 0;
 316 +       dma_ctrl.bits.td_enable = 0;
 317 +       __raw_writel(dma_ctrl.bits32, gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
 318 +}
 319 +
 320 +static void toe_gmac_init_chip(struct net_device *dev)
 321 +{
 322 +       struct gmac_private     *gmac = netdev_priv(dev);
 323 +       GMAC_CONFIG2_T  config2_val;
 324 +       GMAC_CONFIG0_T  config0;
 325 +       GMAC_CONFIG1_T  config1;
 326 +       GMAC_STATUS_T   status;
 327 +       GMAC_TX_WCR0_T  hw_weigh;
 328 +       GMAC_TX_WCR1_T  sw_weigh;
 329 +       GMAC_RX_FLTR_T  rx_filter;
 330 +
 331 +       /* set RX_FLTR register to receive all multicast packet */
 332 +       rx_filter.bits32 = __raw_readl(dev->base_addr + GMAC_RX_FLTR);
 333 +       rx_filter.bits.unicast = 1;
 334 +       rx_filter.bits.multicast = 1;
 335 +       rx_filter.bits.broadcast = 1;
 336 +       __raw_writel(rx_filter.bits32, dev->base_addr + GMAC_RX_FLTR);
 337 +
 338 +       /* set flow control threshold */
 339 +       config1.bits32 = 0;
 340 +       config1.bits.set_threshold = 32 / 2;
 341 +       config1.bits.rel_threshold = 32 / 4 * 3;
 342 +       __raw_writel(config1.bits32, dev->base_addr + GMAC_CONFIG1);
 343 +
 344 +       /* set flow control threshold */
 345 +       config2_val.bits32 = 0;
 346 +       config2_val.bits.set_threshold = TOE_SW_FREEQ_DESC_NUM / 4;
 347 +       config2_val.bits.rel_threshold = TOE_SW_FREEQ_DESC_NUM / 2;
 348 +       __raw_writel(config2_val.bits32, dev->base_addr + GMAC_CONFIG2);
 349 +
 350 +       /* disable TX/RX and disable internal loop back */
 351 +       config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
 352 +
 353 +       config0.bits.max_len = 2;
 354 +
 355 +       gmac->flow_control_enable = 0;
 356 +
 357 +       config0.bits.tx_fc_en = 0;      /* disable tx flow control */
 358 +       config0.bits.rx_fc_en = 0;      /* disable rx flow control */
 359 +       config0.bits.dis_rx = 1;        /* disable rx */
 360 +       config0.bits.dis_tx = 1;        /* disable tx */
 361 +       config0.bits.loop_back = 0;     /* enable/disable GMAC loopback */
 362 +       config0.bits.rx_err_detect = 1;
 363 +       config0.bits.rgmii_en = 0;
 364 +       config0.bits.rgmm_edge = 1;
 365 +       config0.bits.rxc_inv = 0;
 366 +       config0.bits.ipv4_rx_chksum = 1;        /* enable H/W to check ip checksum */
 367 +       config0.bits.ipv6_rx_chksum = 1;        /* enable H/W to check ip checksum */
 368 +       config0.bits.port0_chk_hwq = 1;
 369 +       config0.bits.port1_chk_hwq = 1;
 370 +       config0.bits.port0_chk_toeq = 1;
 371 +       config0.bits.port1_chk_toeq = 1;
 372 +       config0.bits.port0_chk_classq = 1;
 373 +       config0.bits.port1_chk_classq = 1;
 374 +
 375 +       __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
 376 +
 377 +       hw_weigh.bits32 = 0;
 378 +       hw_weigh.bits.hw_tq3 = 1;
 379 +       hw_weigh.bits.hw_tq2 = 1;
 380 +       hw_weigh.bits.hw_tq1 = 1;
 381 +       hw_weigh.bits.hw_tq0 = 1;
 382 +       __raw_writel(hw_weigh.bits32, gmac->dma_base_addr + GMAC_TX_WEIGHTING_CTRL_0_REG);
 383 +
 384 +       sw_weigh.bits32 = 0;
 385 +       sw_weigh.bits.sw_tq5 = 1;
 386 +       sw_weigh.bits.sw_tq4 = 1;
 387 +       sw_weigh.bits.sw_tq3 = 1;
 388 +       sw_weigh.bits.sw_tq2 = 1;
 389 +       sw_weigh.bits.sw_tq1 = 1;
 390 +       sw_weigh.bits.sw_tq0 = 1;
 391 +       __raw_writel(sw_weigh.bits32, gmac->dma_base_addr + GMAC_TX_WEIGHTING_CTRL_1_REG);
 392 +
 393 +       /* set interface type */
 394 +       status.bits32 = __raw_readl(dev->base_addr + GMAC_STATUS);
 395 +
 396 +       switch (gmac->phydev->interface) {
 397 +       case PHY_INTERFACE_MODE_MII:
 398 +               status.bits.mii_rmii = GMAC_PHY_MII;
 399 +               break;
 400 +       case PHY_INTERFACE_MODE_GMII:
 401 +               status.bits.mii_rmii = GMAC_PHY_GMII;
 402 +               break;
 403 +       case PHY_INTERFACE_MODE_RGMII:
 404 +               status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
 405 +               break;
 406 +       default:
 407 +               dev_err(&dev->dev, "Unsupported MII interface\n");
 408 +               return;
 409 +       }
 410 +
 411 +       __raw_writel(status.bits32, dev->base_addr + GMAC_STATUS);
 412 +}
 413 +
 414 +static void toe_init_gmac(struct net_device *dev)
 415 +{
 416 +       struct gmac_private     *gmac = netdev_priv(dev);
 417 +       struct toe_private      *toe = dev->ml_priv;
 418 +       u32                     data;
 419 +
 420 +       /* GMAC initialization */
 421 +       toe_gmac_init_chip(dev);
 422 +
 423 +       /* -----------------------------------------------------------
 424 +       Enable GMAC interrupt & disable loopback
 425 +       Notes:
 426 +               GMACx init routine (for eCOS) or open routine (for Linux)
 427 +               enable the interrupt bits only which are selected for him.
 428 +       --------------------------------------------------------------*/
 429 +
 430 +       /* Enable Interrupt Bits */
 431 +       if (gmac->port_id == 0) {
 432 +               gmac->intr0_selected =  GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT     |
 433 +                                       GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT     |
 434 +                                       GMAC0_SWTQ05_FIN_INT_BIT | GMAC0_SWTQ05_EOF_INT_BIT |
 435 +                                       GMAC0_SWTQ04_FIN_INT_BIT | GMAC0_SWTQ04_EOF_INT_BIT |
 436 +                                       GMAC0_SWTQ03_FIN_INT_BIT | GMAC0_SWTQ03_EOF_INT_BIT |
 437 +                                       GMAC0_SWTQ02_FIN_INT_BIT | GMAC0_SWTQ02_EOF_INT_BIT |
 438 +                                       GMAC0_SWTQ01_FIN_INT_BIT | GMAC0_SWTQ01_EOF_INT_BIT |
 439 +                                       GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
 440 +
 441 +#ifdef GMAX_TX_INTR_DISABLED
 442 +               gmac->intr0_enabled = 0;
 443 +#else
 444 +               gmac->intr0_enabled = GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
 445 +#endif
 446 +
 447 +               gmac->intr1_selected = TOE_IQ_ALL_BITS | TOE_CLASS_RX_INT_BITS |
 448 +                                       GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT |
 449 +                                       GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT |
 450 +                                       DEFAULT_Q0_INT_BIT;
 451 +               gmac->intr1_enabled =   DEFAULT_Q0_INT_BIT | TOE_IQ_ALL_BITS;
 452 +               gmac->intr2_selected =  0xffffffff;      /* TOE Queue 32-63 FUUL Intr */
 453 +               gmac->intr2_enabled =   0xffffffff;
 454 +               gmac->intr3_selected =  0xffffffff;      /* TOE Queue 0-31 FUUL Intr */
 455 +               gmac->intr3_enabled =   0xffffffff;
 456 +               gmac->intr4_selected =  GMAC0_INT_BITS | CLASS_RX_FULL_INT_BITS |
 457 +                                                       HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
 458 +               gmac->intr4_enabled =   GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT;
 459 +
 460 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG) & ~gmac->intr0_selected;
 461 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
 462 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG) & ~gmac->intr1_selected;
 463 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
 464 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG) & ~gmac->intr2_selected;
 465 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
 466 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG) & ~gmac->intr3_selected;
 467 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
 468 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG) & ~gmac->intr4_selected;
 469 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
 470 +       } else {
 471 +               gmac->intr0_selected =  GMAC1_TXDERR_INT_BIT | GMAC1_TXPERR_INT_BIT     |
 472 +                                       GMAC1_RXDERR_INT_BIT | GMAC1_RXPERR_INT_BIT     |
 473 +                                       GMAC1_SWTQ15_FIN_INT_BIT | GMAC1_SWTQ15_EOF_INT_BIT |
 474 +                                       GMAC1_SWTQ14_FIN_INT_BIT | GMAC1_SWTQ14_EOF_INT_BIT |
 475 +                                       GMAC1_SWTQ13_FIN_INT_BIT | GMAC1_SWTQ13_EOF_INT_BIT |
 476 +                                       GMAC1_SWTQ12_FIN_INT_BIT | GMAC1_SWTQ12_EOF_INT_BIT |
 477 +                                       GMAC1_SWTQ11_FIN_INT_BIT | GMAC1_SWTQ11_EOF_INT_BIT |
 478 +                                       GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
 479 +#ifdef GMAX_TX_INTR_DISABLED
 480 +               gmac->intr0_enabled =           0;
 481 +#else
 482 +               gmac->intr0_enabled =           GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
 483 +#endif
 484 +
 485 +               gmac->intr1_selected =  DEFAULT_Q1_INT_BIT;
 486 +               gmac->intr1_enabled =   DEFAULT_Q1_INT_BIT | TOE_IQ_ALL_BITS;
 487 +               gmac->intr2_selected =  0;       /* TOE Queue 32-63 FUUL Intr */
 488 +               gmac->intr2_enabled =   0;
 489 +               gmac->intr3_selected =  0;       /* TOE Queue 0-31 FUUL Intr */
 490 +               gmac->intr3_enabled =   0;
 491 +               gmac->intr4_selected =  GMAC1_INT_BITS;
 492 +               gmac->intr4_enabled =   GMAC1_INT_BITS;
 493 +
 494 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG) | gmac->intr0_selected;
 495 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
 496 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG) | gmac->intr1_selected;
 497 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
 498 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG) | gmac->intr2_selected;
 499 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
 500 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG) | gmac->intr3_selected;
 501 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
 502 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG) | gmac->intr4_selected;
 503 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
 504 +       }
 505 +
 506 +       /* enable only selected bits */
 507 +       gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_0_REG,
 508 +                                       gmac->intr0_enabled, gmac->intr0_selected);
 509 +       gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_1_REG,
 510 +                                       gmac->intr1_enabled, gmac->intr1_selected);
 511 +       gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_2_REG,
 512 +                                       gmac->intr2_enabled, gmac->intr2_selected);
 513 +       gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_3_REG,
 514 +                                       gmac->intr3_enabled, gmac->intr3_selected);
 515 +       gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_4_REG,
 516 +                                       gmac->intr4_enabled, gmac->intr4_selected);
 517 +
 518 +       /* start DMA process */
 519 +       toe_gmac_hw_start(gmac);
 520 +}
 521 +
 522 +static void toe_gmac_enable_tx_rx(struct net_device *dev)
 523 +{
 524 +       GMAC_CONFIG0_T  config0;
 525 +
 526 +       /* enable TX/RX */
 527 +       config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
 528 +       config0.bits.dis_rx = 0;        /* enable rx */
 529 +       config0.bits.dis_tx = 0;        /* enable tx */
 530 +       __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
 531 +}
 532 +
 533 +static void toe_gmac_disable_tx_rx(struct net_device *dev)
 534 +{
 535 +       GMAC_CONFIG0_T  config0;
 536 +
 537 +       /* enable TX/RX */
 538 +       config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
 539 +       config0.bits.dis_rx = 1;        /* disable rx */
 540 +       config0.bits.dis_tx = 1;        /* disable tx */
 541 +       __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
 542 +}
 543 +
 544 +static void toe_gmac_tx_complete(struct net_device *dev, unsigned int tx_qid)
 545 +{
 546 +       struct gmac_private             *gmac = netdev_priv(dev);
 547 +       struct toe_private              *toe = dev->ml_priv;
 548 +       GMAC_TXDESC_T                   *curr_desc;
 549 +       GMAC_TXDESC_0_T                 word0;
 550 +       GMAC_TXDESC_1_T                 word1;
 551 +       unsigned int                    desc_count;
 552 +       GMAC_SWTXQ_T                    *swtxq;
 553 +       DMA_RWPTR_T                     rwptr;
 554 +
 555 +       /* get tx H/W completed descriptor virtual address */
 556 +       /* check tx status and accumulate tx statistics */
 557 +       swtxq = &gmac->swtxq[tx_qid];
 558 +       for (;;) {
 559 +               rwptr.bits32 = __raw_readl(swtxq->rwptr_reg);
 560 +               if (rwptr.bits.rptr == swtxq->finished_idx)
 561 +                       break;
 562 +               curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
 563 +               dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
 564 +                                               swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
 565 +                                               sizeof(GMAC_TXDESC_T),
 566 +                                               DMA_FROM_DEVICE);
 567 +               word0.bits32 = curr_desc->word0.bits32;
 568 +               word1.bits32 = curr_desc->word1.bits32;
 569 +
 570 +               if (word0.bits.status_tx_ok) {
 571 +                       dev->stats.tx_bytes += word1.bits.byte_count;
 572 +                       desc_count = word0.bits.desc_count;
 573 +                       if (desc_count == 0) {
 574 +                               dev_err(&dev->dev, "%s::Desc 0x%x = 0x%x, desc_count=%d\n", __func__, (u32)curr_desc, word0.bits32, desc_count);
 575 +                               BUG();
 576 +                       }
 577 +                       while (--desc_count) {
 578 +                               word0.bits.status_tx_ok = 0;
 579 +                               curr_desc->word0.bits32 = word0.bits32;
 580 +                               dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
 581 +                                                               swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
 582 +                                                               sizeof(GMAC_TXDESC_T),
 583 +                                                               DMA_TO_DEVICE);
 584 +                               swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, TOE_GMAC_SWTXQ_DESC_NUM);
 585 +                               curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
 586 +                               dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
 587 +                                                               swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
 588 +                                                               sizeof(GMAC_TXDESC_T),
 589 +                                                               DMA_FROM_DEVICE);
 590 +                               word0.bits32 = curr_desc->word0.bits32;
 591 +                       }
 592 +
 593 +                       word0.bits.status_tx_ok = 0;
 594 +                       dev_kfree_skb_any(swtxq->tx_skb[swtxq->finished_idx]);
 595 +                       swtxq->tx_skb[swtxq->finished_idx] = NULL;
 596 +
 597 +                       curr_desc->word0.bits32 = word0.bits32;
 598 +                       dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
 599 +                                                       swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
 600 +                                                       sizeof(GMAC_TXDESC_T),
 601 +                                                       DMA_TO_DEVICE);
 602 +                       dev->stats.tx_packets++;
 603 +                       swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, TOE_GMAC_SWTXQ_DESC_NUM);
 604 +               } else {
 605 +                       break;
 606 +               }
 607 +       }
 608 +
 609 +       if (netif_queue_stopped(dev))
 610 +               netif_wake_queue(dev);
 611 +}
 612 +
 613 +static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
 614 +{
 615 +       struct gmac_private     *gmac = netdev_priv(dev);
 616 +       struct toe_private      *toe = dev->ml_priv;
 617 +       DMA_RWPTR_T             rwptr;
 618 +       GMAC_TXDESC_T           *curr_desc;
 619 +       int                     snd_pages = skb_shinfo(skb)->nr_frags + 1;      /* get number of descriptor */
 620 +       int                     frag_id = 0;
 621 +       int                     len, total_len = skb->len;
 622 +       struct net_device_stats *isPtr = &dev->stats;
 623 +       unsigned int            free_desc;
 624 +       GMAC_SWTXQ_T            *swtxq;
 625 +       register unsigned long  word0, word1, word2, word3;
 626 +       unsigned short          wptr, rptr;
 627 +
 628 +#ifdef GMAC_LEN_1_2_ISSUE
 629 +       int                     total_pages;
 630 +       total_pages = snd_pages;
 631 +#endif
 632 +
 633 +       if (skb->len >= 0x10000) {
 634 +               isPtr->tx_dropped++;
 635 +               dev_err(&dev->dev, "%s::skb->len %d >= 64K\n", __func__, skb->len);
 636 +               netif_stop_queue(dev);
 637 +               return 1;
 638 +       }
 639 +
 640 +#ifdef GMAC_USE_TXQ0
 641 +       #define tx_qid  0
 642 +#endif
 643 +
 644 +       swtxq = &gmac->swtxq[tx_qid];
 645 +
 646 +       rwptr.bits32 = __raw_readl(swtxq->rwptr_reg);
 647 +       wptr = rwptr.bits.wptr;
 648 +       rptr = rwptr.bits.rptr;
 649 +
 650 +       /*
 651 +        * check finished desc or empty BD
 652 +        * cannot check by read ptr of RW PTR register,
 653 +        * because the HW complete to send but the SW may NOT handle it
 654 +        */
 655 +#ifdef GMAX_TX_INTR_DISABLED
 656 +       toe_gmac_tx_complete(dev, tx_qid);
 657 +#endif
 658 +       if (wptr >= swtxq->finished_idx)
 659 +               free_desc = TOE_GMAC_SWTXQ_DESC_NUM - wptr + swtxq->finished_idx;
 660 +       else
 661 +               free_desc = swtxq->finished_idx - wptr;
 662 +
 663 +       if (free_desc < snd_pages) {
 664 +               isPtr->tx_dropped++;
 665 +               netif_stop_queue(dev);
 666 +               return 1;
 667 +       }
 668 +
 669 +       while (snd_pages) {
 670 +               char *pkt_datap;
 671 +
 672 +               curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + wptr;
 673 +               if (frag_id == 0) {
 674 +                       len = skb_headlen(skb);
 675 +                       pkt_datap = dma_map_single(toe->dev, skb->data, len, DMA_TO_DEVICE);
 676 +               } else {
 677 +                       skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_id - 1];
 678 +                       len = frag->size;
 679 +                       pkt_datap = dma_map_page(toe->dev, frag->page.p, frag->page_offset, len, DMA_TO_DEVICE);
 680 +               }
 681 +
 682 +               /* set TX descriptor */
 683 +               word0 = len;
 684 +               word3 = (dev->mtu + 14) | EOFIE_BIT;
 685 +
 686 +#ifdef DO_HW_CHKSUM
 687 +               if (total_len <= 1514 && ip_hdr(skb) && (ip_hdr(skb)->frag_off & __constant_htons(0x3fff)))
 688 +                       word1  = total_len |
 689 +                                       TSS_IP_CHKSUM_BIT  |
 690 +                                       TSS_IPV6_ENABLE_BIT |
 691 +                                       TSS_MTU_ENABLE_BIT;
 692 +               else
 693 +                       word1 = total_len |
 694 +                                       TSS_UDP_CHKSUM_BIT |
 695 +                                       TSS_TCP_CHKSUM_BIT |
 696 +                                       TSS_IP_CHKSUM_BIT  |
 697 +                                       TSS_IPV6_ENABLE_BIT |
 698 +                                       TSS_MTU_ENABLE_BIT;
 699 +#else
 700 +               word1 = total_len | TSS_MTU_ENABLE_BIT;
 701 +#endif
 702 +               word2 = pkt_datap;
 703 +
 704 +               if (frag_id == 0)
 705 +                       word3 |= SOF_BIT;
 706 +
 707 +               if (snd_pages == 1) {
 708 +                       word3 |= EOF_BIT;
 709 +                       swtxq->tx_skb[wptr] = skb;
 710 +               } else
 711 +                       swtxq->tx_skb[wptr] = NULL;
 712 +
 713 +#ifdef GMAC_LEN_1_2_ISSUE
 714 +               if ((total_pages != snd_pages) && (len == 1 || len == 2) && ((u32)pkt_datap & 0x03)) {
 715 +                       memcpy((void *)&_debug_prefetch_buf[_debug_prefetch_cnt][0], pkt_datap, len);
 716 +                       pkt_datap = (char *)&_debug_prefetch_buf[_debug_prefetch_cnt][0];
 717 +                       word2 = (unsigned long)__pa(pkt_datap);
 718 +                       _debug_prefetch_cnt++;
 719 +                       if (_debug_prefetch_cnt >= _DEBUG_PREFETCH_NUM)
 720 +                               _debug_prefetch_cnt = 0;
 721 +               }
 722 +#endif
 723 +               curr_desc->word0.bits32 = word0;
 724 +               curr_desc->word1.bits32 = word1;
 725 +               curr_desc->word2.bits32 = word2;
 726 +               curr_desc->word3.bits32 = word3;
 727 +               free_desc--;
 728 +               dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
 729 +                                               wptr * sizeof(GMAC_TXDESC_T),
 730 +                                               sizeof(GMAC_TXDESC_T),
 731 +                                               DMA_TO_DEVICE);
 732 +               wptr = RWPTR_ADVANCE_ONE(wptr, TOE_GMAC_SWTXQ_DESC_NUM);
 733 +               frag_id++;
 734 +               snd_pages--;
 735 +       }
 736 +
 737 +       SET_WPTR(swtxq->rwptr_reg, wptr);
 738 +       dev->trans_start = jiffies;
 739 +
 740 +       return 0;
 741 +}
 742 +
 743 +static void __gmac_set_mac_address(struct net_device *dev)
 744 +{
 745 +       unsigned int    reg_val;
 746 +
 747 +       reg_val = dev->dev_addr[0] + (dev->dev_addr[1] << 8) +
 748 +                 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
 749 +       __raw_writel(reg_val, dev->base_addr + GMAC_STA_ADD0);
 750 +       reg_val = (__raw_readl(dev->base_addr + GMAC_STA_ADD1) & 0xFFFF0000) +
 751 +                 dev->dev_addr[4] + (dev->dev_addr[5] << 8);
 752 +       __raw_writel(reg_val, dev->base_addr + GMAC_STA_ADD1);
 753 +}
 754 +
 755 +static int gmac_set_mac_address(struct net_device *dev, void *addr)
 756 +{
 757 +       struct sockaddr *sa = addr;
 758 +
 759 +       memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
 760 +
 761 +       __gmac_set_mac_address(dev);
 762 +
 763 +       return 0;
 764 +}
 765 +
 766 +static void gmac_get_mac_address(struct net_device *dev)
 767 +{
 768 +       unsigned int reg_val;
 769 +
 770 +       reg_val = __raw_readl(dev->base_addr + GMAC_STA_ADD0);
 771 +       dev->dev_addr[0] = reg_val & 0xFF;
 772 +       dev->dev_addr[1] = (reg_val >> 8) & 0xFF;
 773 +       dev->dev_addr[2] = (reg_val >> 16) & 0xFF;
 774 +       dev->dev_addr[3] = (reg_val >> 24) & 0xFF;
 775 +       reg_val = __raw_readl(dev->base_addr + GMAC_STA_ADD1);
 776 +       dev->dev_addr[4] = reg_val & 0xFF;
 777 +       dev->dev_addr[5] = (reg_val >> 8) & 0xFF;
 778 +
 779 +       if (!is_valid_ether_addr(dev->dev_addr)) {
 780 +               random_ether_addr(dev->dev_addr);
 781 +               __gmac_set_mac_address(dev);
 782 +       }
 783 +}
 784 +
 785 +struct net_device_stats *gmac_get_stats(struct net_device *dev)
 786 +{
 787 +       if (netif_running(dev)) {
 788 +               unsigned short multicast;
 789 +
 790 +               multicast = __raw_readw(dev->base_addr + GMAC_IN_MCAST) +
 791 +                               __raw_readw(dev->base_addr + GMAC_IN_BCAST);
 792 +
 793 +               dev->stats.rx_dropped += __raw_readw(dev->base_addr + GMAC_IN_DISCARDS);
 794 +               dev->stats.rx_errors += __raw_readw(dev->base_addr + GMAC_IN_ERRORS);
 795 +               dev->stats.rx_packets += __raw_readl(dev->base_addr + GMAC_IN_MAC1) + multicast;
 796 +               dev->stats.multicast += multicast;
 797 +       }
 798 +
 799 +       return &dev->stats;
 800 +}
 801 +
 802 +/* TODO: If possible use crc32 from kernel lib */
 803 +static unsigned const ethernet_polynomial = 0x04c11db7U;
 804 +static unsigned int ether_crc(int length, unsigned char *data)
 805 +{
 806 +       int crc = -1;
 807 +       unsigned int i;
 808 +       unsigned int crc_val = 0;
 809 +
 810 +       while (--length >= 0) {
 811 +               unsigned char current_octet = *data++;
 812 +               int bit;
 813 +               for (bit = 0; bit < 8; bit++, current_octet >>= 1)
 814 +                       crc = (crc << 1) ^ ((crc < 0) ^ (current_octet & 1) ?
 815 +                               ethernet_polynomial : 0);
 816 +       }
 817 +       crc = ~crc;
 818 +       for (i = 0; i < 32; i++)
 819 +               crc_val = crc_val + (((crc << i) & 0x80000000) >> (31 - i));
 820 +
 821 +       return crc_val;
 822 +}
 823 +
 824 +/*----------------------------------------------------------------------
 825 +* toe_gmac_fill_free_q
 826 +* allocate buffers for free queue.
 827 +*----------------------------------------------------------------------*/
 828 +static void toe_gmac_fill_free_q(struct toe_private *toe)
 829 +{
 830 +       struct sk_buff  *skb;
 831 +       DMA_RWPTR_T     fq_rwptr;
 832 +       GMAC_RXDESC_T   *fq_desc;
 833 +       unsigned long   flags;
 834 +
 835 +       spin_lock_irqsave(&toe->freeq_lock, flags);
 836 +       fq_rwptr.bits32 = __raw_readl(toe->global_base + GLOBAL_SWFQ_RWPTR_REG);
 837 +       while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
 838 +               TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
 839 +               skb = dev_alloc_skb(SW_RX_BUF_SIZE);
 840 +               if (skb == NULL) {
 841 +                       dev_err(toe->dev, "%s::skb allocation fail\n", __func__);
 842 +                       break;
 843 +               }
 844 +               REG32(skb->data) = (unsigned int)skb;
 845 +               skb_reserve(skb, SKB_RESERVE_BYTES);
 846 +               fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
 847 +                       TOE_SW_FREEQ_DESC_NUM);
 848 +               fq_desc = (GMAC_RXDESC_T *)toe->swfq_desc_base + fq_rwptr.bits.wptr;
 849 +               fq_desc->word2.buf_adr = dma_map_single(toe->dev, skb->data,
 850 +                                       SW_RX_BUF_SIZE - SKB_RESERVE_BYTES,
 851 +                                       DMA_FROM_DEVICE);
 852 +               dma_sync_single_range_for_device(toe->dev,
 853 +                               toe->sw_freeq_desc_base_dma,
 854 +                               fq_rwptr.bits.wptr * sizeof(GMAC_RXDESC_T),
 855 +                               sizeof(GMAC_RXDESC_T),
 856 +                               DMA_TO_DEVICE);
 857 +               SET_WPTR(toe->global_base + GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
 858 +       }
 859 +       spin_unlock_irqrestore(&toe->freeq_lock, flags);
 860 +}
 861 +
 862 +static void fill_free_q_worker(struct work_struct *work)
 863 +{
 864 +       struct toe_private *toe = container_of(work, struct toe_private, freq_work);
 865 +
 866 +       toe_gmac_fill_free_q(toe);
 867 +}
 868 +
 869 +/*----------------------------------------------------------------------
 870 +*      toe_gmac_handle_default_rxq
 871 +*      (1) Get rx Buffer for default Rx queue
 872 +*      (2) notify or call upper-routine to handle it
 873 +*      (3) get a new buffer and insert it into SW free queue
 874 +*      (4) Note: The SW free queue Read-Write Pointer should be locked when accessing
 875 +*----------------------------------------------------------------------*/
 876 +static void toe_gmac_handle_default_rxq(struct net_device *dev)
 877 +{
 878 +       struct gmac_private *gmac = netdev_priv(dev);
 879 +       struct toe_private *toe = dev->ml_priv;
 880 +       GMAC_RXDESC_T   *curr_desc;
 881 +       struct sk_buff  *skb;
 882 +       DMA_RWPTR_T     rwptr;
 883 +       unsigned int    pkt_size;
 884 +       int             max_cnt;
 885 +       unsigned int    desc_count;
 886 +       unsigned int    chksum_status, rx_status;
 887 +       struct net_device_stats *isPtr = &dev->stats;
 888 +
 889 +       rwptr.bits32 = __raw_readl(&gmac->default_qhdr->word1);
 890 +       max_cnt = DEFAULT_RXQ_MAX_CNT;
 891 +       while ((--max_cnt) && rwptr.bits.rptr != rwptr.bits.wptr) {
 892 +               curr_desc = (GMAC_RXDESC_T *)gmac->default_desc_base + rwptr.bits.rptr;
 893 +               dma_sync_single_range_for_device(toe->dev,
 894 +                               gmac->default_desc_base_dma,
 895 +                               rwptr.bits.rptr * sizeof(GMAC_RXDESC_T),
 896 +                               sizeof(GMAC_RXDESC_T),
 897 +                               DMA_FROM_DEVICE);
 898 +               rx_status = curr_desc->word0.bits.status;
 899 +               chksum_status = curr_desc->word0.bits.chksum_status;
 900 +               pkt_size = curr_desc->word1.bits.byte_count;    /* total byte count in a frame */
 901 +               desc_count = curr_desc->word0.bits.desc_count;  /* get descriptor count per frame */
 902 +               skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
 903 +
 904 +               if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
 905 +                       || (pkt_size < 60) || (chksum_status & 0x4) || rx_status) {
 906 +                       if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
 907 +                               dev_err(&dev->dev, "%s::derr\n", __func__);
 908 +                       if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_perr)
 909 +                               dev_err(&dev->dev, "%s::perr\n", __func__);
 910 +                       if (rx_status && (rx_status == 4 || rx_status == 7))
 911 +                               isPtr->rx_crc_errors++;
 912 +
 913 +                       dev_kfree_skb_irq(skb);
 914 +                       goto bad_frame;
 915 +               }
 916 +
 917 +               if (curr_desc->word0.bits.drop)
 918 +                       dev_warn(&dev->dev, "%s::Drop\n", __func__);
 919 +
 920 +               /* get frame information from the first descriptor of the frame */
 921 +               skb_reserve(skb, RX_INSERT_BYTES);      /* 16 byte align the IP fields. */
 922 +               skb_put(skb, pkt_size);
 923 +               skb->dev = dev;
 924 +               skb->protocol = eth_type_trans(skb, dev);
 925 +               if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK || chksum_status == RX_CHKSUM_IP_OK_ONLY)
 926 +                       skb->ip_summed = CHECKSUM_UNNECESSARY;
 927 +
 928 +               netif_rx(skb);  /* socket rx */
 929 +               dev->last_rx = jiffies;
 930 +
 931 +               isPtr->rx_bytes += pkt_size;
 932 +
 933 +bad_frame:
 934 +               /* advance one for Rx default Q 0/1 */
 935 +               rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, TOE_DEFAULT_Q_DESC_NUM);
 936 +               SET_RPTR(&gmac->default_qhdr->word1, rwptr.bits.rptr);
 937 +       }
 938 +
 939 +       schedule_work(&toe->freq_work);
 940 +}
 941 +
 942 +static irqreturn_t toe_gmac_interrupt(int irq, void *dev_instance)
 943 +{
 944 +       struct net_device       *dev = dev_instance;
 945 +       struct gmac_private     *gmac = netdev_priv(dev);
 946 +       struct toe_private      *toe = dev->ml_priv;
 947 +       unsigned int            status0;
 948 +       unsigned int            status1;
 949 +       unsigned int            status2;
 950 +       unsigned int            status3;
 951 +       unsigned int            status4;
 952 +       int                     handled = 0;
 953 +
 954 +       /* read Interrupt status */
 955 +       status0 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
 956 +       status1 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
 957 +       status2 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
 958 +       status3 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
 959 +       status4 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
 960 +
 961 +       /* clear interrupts */
 962 +       if (status0)
 963 +               __raw_writel(status0, toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
 964 +       if (status1)
 965 +               __raw_writel(status1, toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
 966 +       if (status2)
 967 +               __raw_writel(status2, toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
 968 +       if (status3)
 969 +               __raw_writel(status3, toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
 970 +       if (status4)
 971 +               __raw_writel(status4, toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
 972 +
 973 +       /* handle freeq interrupt first */
 974 +       if (status4 & gmac->intr4_enabled) {
 975 +               if ((status4 & SWFQ_EMPTY_INT_BIT) && (gmac->intr4_enabled & SWFQ_EMPTY_INT_BIT)) {
 976 +                       toe_gmac_fill_free_q(toe);
 977 +                       handled = 1;
 978 +               }
 979 +       }
 980 +
 981 +       /* Interrupt Status 1 */
 982 +       if (status1 & gmac->intr1_enabled) {
 983 +               /*
 984 +                * Handle GMAC 0/1 HW Tx queue 0-3 EOF events
 985 +                * Only count
 986 +                * TOE, Classification, and default queues interrupts are handled by ISR
 987 +                * because they should pass packets to upper layer
 988 +                */
 989 +               if (gmac->port_id == 0) {
 990 +                       if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (gmac->intr1_enabled & DEFAULT_Q0_INT_BIT)) {
 991 +                               toe_gmac_handle_default_rxq(dev);
 992 +                               handled = 1;
 993 +                       }
 994 +               } else if (gmac->port_id == 1) {
 995 +                       if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (gmac->intr1_enabled & DEFAULT_Q1_INT_BIT)) {
 996 +                               toe_gmac_handle_default_rxq(dev);
 997 +                               handled = 1;
 998 +                       }
 999 +               }
1000 +       }
1001 +
1002 +       /* Interrupt Status 0 */
1003 +       if (status0 & gmac->intr0_enabled) {
1004 +#ifndef        GMAX_TX_INTR_DISABLED
1005 +               if (gmac->port_id == 1 && netif_running(dev) &&
1006 +                       (((status0 & GMAC1_SWTQ10_FIN_INT_BIT) && (gmac->intr0_enabled & GMAC1_SWTQ10_FIN_INT_BIT))
1007 +                       ||
1008 +                       ((status0 & GMAC1_SWTQ10_EOF_INT_BIT) && (gmac->intr0_enabled & GMAC1_SWTQ10_EOF_INT_BIT)))) {
1009 +                       toe_gmac_tx_complete(dev, 0);
1010 +                       handled = 1;
1011 +               }
1012 +
1013 +               if (gmac->port_id == 0 && netif_running(dev) &&
1014 +                       (((status0 & GMAC0_SWTQ00_FIN_INT_BIT) && (gmac->intr0_enabled & GMAC0_SWTQ00_FIN_INT_BIT))
1015 +                       ||
1016 +                       ((status0 & GMAC0_SWTQ00_EOF_INT_BIT) && (gmac->intr0_enabled & GMAC0_SWTQ00_EOF_INT_BIT)))) {
1017 +                       toe_gmac_tx_complete(dev, 0);
1018 +                       handled = 1;
1019 +               }
1020 +#endif
1021 +       }
1022 +
1023 +       return IRQ_RETVAL(handled);
1024 +}
1025 +
1026 +static int gmac_open(struct net_device *dev)
1027 +{
1028 +       struct gmac_private     *gmac = netdev_priv(dev);
1029 +       int                     retval;
1030 +
1031 +       /* hook ISR */
1032 +       retval = request_irq(dev->irq, toe_gmac_interrupt, 0, dev->name, dev);
1033 +       if (retval)
1034 +               return retval;
1035 +
1036 +       toe_init_gmac(dev);
1037 +
1038 +       netif_carrier_off(dev);
1039 +       phy_start(gmac->phydev);
1040 +
1041 +       netif_start_queue(dev);
1042 +
1043 +       return 0;
1044 +}
1045 +
1046 +static int gmac_close(struct net_device *dev)
1047 +{
1048 +       struct gmac_private     *gmac = netdev_priv(dev);
1049 +
1050 +       netif_stop_queue(dev);
1051 +       mdelay(20);
1052 +
1053 +       if (gmac->phydev)
1054 +               phy_stop(gmac->phydev);
1055 +
1056 +       /* stop tx/rx packet */
1057 +       toe_gmac_disable_tx_rx(dev);
1058 +       mdelay(20);
1059 +
1060 +       /* stop the chip's Tx and Rx DMA processes */
1061 +       toe_gmac_hw_stop(gmac);
1062 +
1063 +       disable_irq(dev->irq);
1064 +       free_irq(dev->irq, dev);
1065 +
1066 +       return 0;
1067 +}
1068 +
1069 +static void gmac_get_phy_status(struct net_device *dev)
1070 +{
1071 +       struct gmac_private *gmac = netdev_priv(dev);
1072 +       GMAC_CONFIG0_T  config0;
1073 +       GMAC_STATUS_T   status, old_status;
1074 +       struct phy_device *phydev = gmac->phydev;
1075 +
1076 +       old_status.bits32 = status.bits32 = __raw_readl(dev->base_addr + GMAC_STATUS);
1077 +
1078 +       status.bits.link = phydev->link;
1079 +       status.bits.duplex = phydev->duplex;
1080 +
1081 +       switch (phydev->speed) {
1082 +       case 1000:
1083 +               status.bits.speed = GMAC_SPEED_1000;
1084 +               if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1085 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
1086 +               break;
1087 +       case 100:
1088 +               status.bits.speed = GMAC_SPEED_100;
1089 +               if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1090 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
1091 +               break;
1092 +       case 10:
1093 +               status.bits.speed = GMAC_SPEED_10;
1094 +               if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1095 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
1096 +               break;
1097 +       default:
1098 +               dev_warn(&dev->dev, "Not supported PHY speed (%d)\n", phydev->speed);
1099 +       }
1100 +
1101 +       if (phydev->pause) {
1102 +               if (gmac->flow_control_enable == 0) {
1103 +                       config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
1104 +                       config0.bits.tx_fc_en = 1;      /* enable tx flow control */
1105 +                       config0.bits.rx_fc_en = 1;      /* enable rx flow control */
1106 +                       __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
1107 +                       dev_info(&dev->dev, "MII flow control enabled\n");
1108 +               }
1109 +               gmac->flow_control_enable = 1;
1110 +       } else {
1111 +               if (gmac->flow_control_enable == 1) {
1112 +                       config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
1113 +                       config0.bits.tx_fc_en = 0;      /* disable tx flow control */
1114 +                       config0.bits.rx_fc_en = 0;      /* disable rx flow control */
1115 +                       __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
1116 +                       dev_info(&dev->dev, "MII flow control disabled\n");
1117 +               }
1118 +               gmac->flow_control_enable = 0;
1119 +       }
1120 +
1121 +       if (old_status.bits32 != status.bits32) {
1122 +               toe_gmac_disable_tx_rx(dev);
1123 +               phy_print_status(phydev);
1124 +               mdelay(10);     /* let GMAC consume packet */
1125 +               __raw_writel(status.bits32, dev->base_addr + GMAC_STATUS);
1126 +               if (status.bits.link)
1127 +                       toe_gmac_enable_tx_rx(dev);
1128 +       }
1129 +}
1130 +
1131 +static void gmac_set_rx_mode(struct net_device *dev)
1132 +{
1133 +       GMAC_RX_FLTR_T  filter;
1134 +       unsigned int    mc_filter[2];   /* Multicast hash filter */
1135 +       int             bit_nr;
1136 +
1137 +       filter.bits32 = 0;
1138 +       filter.bits.error = 0;
1139 +       if (dev->flags & IFF_PROMISC) {
1140 +               filter.bits.error = 1;
1141 +               filter.bits.promiscuous = 1;
1142 +               filter.bits.broadcast = 1;
1143 +               filter.bits.multicast = 1;
1144 +               filter.bits.unicast = 1;
1145 +               mc_filter[1] = mc_filter[0] = 0xffffffff;
1146 +       } else if (dev->flags & IFF_ALLMULTI) {
1147 +               filter.bits.broadcast = 1;
1148 +               filter.bits.multicast = 1;
1149 +               filter.bits.unicast = 1;
1150 +               mc_filter[1] = mc_filter[0] = 0xffffffff;
1151 +       } else {
1152 +               struct netdev_hw_addr *ha;
1153 +
1154 +               filter.bits.broadcast = 1;
1155 +               filter.bits.multicast = 1;
1156 +               filter.bits.unicast = 1;
1157 +               mc_filter[1] = mc_filter[0] = 0;
1158 +               netdev_for_each_mc_addr(ha, dev) {
1159 +                       bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3f;
1160 +                       if (bit_nr <= 32)
1161 +                               mc_filter[0] = mc_filter[0] | (1 << bit_nr);
1162 +                       else
1163 +                               mc_filter[1] = mc_filter[1] | (1 << (bit_nr - 32));
1164 +               }
1165 +       }
1166 +       __raw_writel(filter.bits32, dev->base_addr + GMAC_RX_FLTR);
1167 +       __raw_writel(mc_filter[0], dev->base_addr + GMAC_MCAST_FIL0);
1168 +       __raw_writel(mc_filter[1], dev->base_addr + GMAC_MCAST_FIL1);
1169 +}
1170 +
1171 +static void gmac_tx_timeout(struct net_device *dev)
1172 +{
1173 +       if (!netif_queue_stopped(dev))
1174 +               netif_wake_queue(dev);
1175 +
1176 +       dev_warn(&dev->dev, "TX timeout\n");
1177 +}
1178 +
1179 +const static struct net_device_ops gemini_gmac_ops = {
1180 +       .ndo_open               = gmac_open,
1181 +       .ndo_stop               = gmac_close,
1182 +       .ndo_start_xmit         = gmac_start_xmit,
1183 +       .ndo_get_stats          = gmac_get_stats,
1184 +       .ndo_set_rx_mode        = gmac_set_rx_mode,
1185 +       .ndo_set_mac_address    = gmac_set_mac_address,
1186 +       .ndo_tx_timeout         = gmac_tx_timeout,
1187 +};
1188 +
1189 +static void __devinit mac_init_drv(struct toe_private *toe)
1190 +{
1191 +       QUEUE_THRESHOLD_T       threshold;
1192 +       DMA_SKB_SIZE_T          skb_size;
1193 +
1194 +       /* clear non TOE Queue Header Area */
1195 +       memset(toe->global_base + TOE_NONTOE_QUE_HDR_BASE, 0,
1196 +               NONTOE_Q_HDR_AREA_END - TOE_NONTOE_QUE_HDR_BASE);
1197 +
1198 +       /* clear TOE Queue Header Area */
1199 +       memset(toe->global_base + TOE_TOE_QUE_HDR_BASE, 0,
1200 +               TOE_Q_HDR_AREA_END - TOE_TOE_QUE_HDR_BASE);
1201 +
1202 +       /* Write GLOBAL_QUEUE_THRESHOLD_REG */
1203 +       threshold.bits32 = 0;
1204 +       threshold.bits.swfq_empty = (TOE_SW_FREEQ_DESC_NUM > 256) ? 255 :
1205 +                                       TOE_SW_FREEQ_DESC_NUM / 2;
1206 +       threshold.bits.hwfq_empty = (TOE_HW_FREEQ_DESC_NUM > 256) ? 256 / 4 :
1207 +                                       TOE_HW_FREEQ_DESC_NUM / 4;
1208 +       threshold.bits.toe_class = (TOE_TOE_DESC_NUM > 256) ? 256 / 4 :
1209 +                                       TOE_TOE_DESC_NUM / 4;
1210 +       threshold.bits.intrq = (TOE_INTR_DESC_NUM > 256) ? 256 / 4 :
1211 +                                       TOE_INTR_DESC_NUM / 4;
1212 +       __raw_writel(threshold.bits32, toe->global_base + GLOBAL_QUEUE_THRESHOLD_REG);
1213 +
1214 +       /* Init skb size */
1215 +       skb_size.bits.hw_skb_size = HW_RX_BUF_SIZE;
1216 +       skb_size.bits.sw_skb_size = SW_RX_BUF_SIZE;
1217 +       __raw_writel(skb_size.bits32, toe->global_base + GLOBAL_DMA_SKB_SIZE_REG);
1218 +
1219 +       toe_init_free_queue(toe);
1220 +       toe_init_interrupt_config(toe);
1221 +}
1222 +
1223 +static int __devinit gmac_init_eth(struct platform_device *pdev,
1224 +                                  unsigned int num)
1225 +{
1226 +       struct gmac_private     *gmac;
1227 +       struct net_device       *dev;
1228 +       struct toe_private      *toe = platform_get_drvdata(pdev);
1229 +       struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data;
1230 +
1231 +       if (!pdata->bus_id[num])
1232 +               return 0;
1233 +
1234 +       dev = alloc_etherdev(sizeof(*gmac));
1235 +       if (dev == NULL) {
1236 +               dev_err(&pdev->dev, "Can't allocate ethernet device #%d\n", num);
1237 +               return -ENOMEM;
1238 +       }
1239 +
1240 +       gmac = netdev_priv(dev);
1241 +       dev->ml_priv = toe;
1242 +       toe->net_dev[num] = dev;
1243 +
1244 +       gmac->dma_base_addr = toe->global_base + TOE_GMAC_DMA_BASE(num);
1245 +       gmac->port_id = num;
1246 +
1247 +       dev->base_addr = toe->global_base + TOE_GMAC_BASE(num);
1248 +       dev->irq = platform_get_irq(pdev, num);
1249 +       dev->netdev_ops = &gemini_gmac_ops;
1250 +       dev->watchdog_timeo = GMAC_DEV_TX_TIMEOUT;
1251 +       dev->tx_queue_len = TOE_GMAC_SWTXQ_DESC_NUM;
1252 +
1253 +#ifdef DO_HW_CHKSUM
1254 +       dev->features = NETIF_F_SG | NETIF_F_HW_CSUM;
1255 +#ifdef ENABLE_TSO
1256 +       dev->features |= NETIF_F_TSO;
1257 +#endif
1258 +#endif
1259 +
1260 +       toe_init_swtx_queue(dev);
1261 +       toe_init_default_queue(dev);
1262 +
1263 +       gmac_get_mac_address(dev);
1264 +
1265 +       /* TODO: Do we need this? */
1266 +       __raw_writel(0x55aa55aa, dev->base_addr + GMAC_STA_ADD2);
1267 +
1268 +       if (register_netdev(dev))
1269 +               return -1;
1270 +
1271 +       gmac->phydev = phy_connect(dev, pdata->bus_id[num], &gmac_get_phy_status, 0,
1272 +                                pdata->interface[num]);
1273 +       if (IS_ERR(gmac->phydev))
1274 +               return PTR_ERR(gmac->phydev);
1275 +
1276 +       gmac->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause;
1277 +       gmac->phydev->advertising = gmac->phydev->supported;
1278 +
1279 +       return 0;
1280 +}
1281 +
1282 +static int __devinit gmac_probe(struct platform_device *pdev)
1283 +{
1284 +       struct resource                         *res;
1285 +       struct toe_private                      *toe;
1286 +       int                                     retval;
1287 +
1288 +       if (!pdev->dev.platform_data)
1289 +               return -EINVAL;
1290 +
1291 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1292 +       if (!res) {
1293 +               dev_err(&pdev->dev, "can't get device resources\n");
1294 +               return -ENODEV;
1295 +       }
1296 +
1297 +       toe = kzalloc(sizeof(struct toe_private), GFP_KERNEL);
1298 +       if (!toe)
1299 +               return -ENOMEM;
1300 +
1301 +       toe->dev = &pdev->dev;
1302 +
1303 +       toe->global_base = ioremap(res->start, resource_size(res));
1304 +       if (!toe->global_base) {
1305 +               dev_err(toe->dev, "ioremap failed\n");
1306 +               retval = -EIO;
1307 +               goto err_data;
1308 +       }
1309 +
1310 +       platform_set_drvdata(pdev, toe);
1311 +
1312 +       mac_init_drv(toe);
1313 +
1314 +       INIT_WORK(&toe->freq_work, fill_free_q_worker);
1315 +       spin_lock_init(&toe->freeq_lock);
1316 +
1317 +       retval = gmac_init_eth(pdev, GMAC_PORT0);
1318 +       if (retval)
1319 +               goto err_unmap;
1320 +       retval = gmac_init_eth(pdev, GMAC_PORT1);
1321 +       if (retval)
1322 +               goto err_unmap;
1323 +
1324 +       dev_info(&pdev->dev, SL351x_DRIVER_NAME "\n");
1325 +
1326 +       return 0;
1327 +
1328 +err_unmap:
1329 +       iounmap(toe->global_base);
1330 +err_data:
1331 +       kfree(toe);
1332 +       return retval;
1333 +}
1334 +
1335 +static int __devexit gmac_remove(struct platform_device *pdev)
1336 +{
1337 +       struct toe_private *toe = platform_get_drvdata(pdev);
1338 +       int i;
1339 +
1340 +       for (i = 0; i < 2; i++)
1341 +               if (toe->net_dev[i]) {
1342 +                       unregister_netdev(toe->net_dev[i]);
1343 +                       kfree(toe->net_dev[i]);
1344 +               }
1345 +
1346 +       iounmap(toe->global_base);
1347 +
1348 +       kfree(toe);
1349 +
1350 +       return 0;
1351 +}
1352 +
1353 +static struct platform_driver gemini_gmac_driver = {
1354 +       .probe          = gmac_probe,
1355 +       .remove         = __devexit_p(gmac_remove),
1356 +       .driver         = {
1357 +               .name   = "gemini-gmac",
1358 +               .owner  = THIS_MODULE,
1359 +       },
1360 +};
1361 +
1362 +static int __init gemini_gmac_init(void)
1363 +{
1364 +       return platform_driver_register(&gemini_gmac_driver);
1365 +}
1366 +
1367 +static void __exit gemini_gmac_exit(void)
1368 +{
1369 +       platform_driver_unregister(&gemini_gmac_driver);
1370 +}
1371 +
1372 +module_init(gemini_gmac_init);
1373 +module_exit(gemini_gmac_exit);
1374 +
1375 +MODULE_AUTHOR("Paulius Zaleckas");
1376 +MODULE_DESCRIPTION("Ethernet device driver for Gemini SoC");
1377 +MODULE_LICENSE("GPL");
1378 +MODULE_ALIAS("platform:gemini-gmac");
1379 --- /dev/null
1380 +++ b/drivers/net/gemini_negmac/gm_gmac.h
1381 @@ -0,0 +1,1488 @@
1382 +/*
1383 + *  Register definitions for Gemini Ethernet device driver.
1384 + *
1385 + *  Copyright (C) 2006, Storlink, Corp.
1386 + *  Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
1387 + *
1388 + * This program is free software; you can redistribute it and/or modify
1389 + * it under the terms of the GNU General Public License as published by
1390 + * the Free Software Foundation; either version 2 of the License, or
1391 + * (at your option) any later version.
1392 + */
1393 +#ifndef _GMAC_SL351x_H
1394 +#define _GMAC_SL351x_H
1395 +#include <linux/skbuff.h>
1396 +
1397 +#define _PACKED_                       __attribute__ ((aligned(1), packed))
1398 +
1399 +#ifndef BIT
1400 +#define BIT(x)                         (1 << (x))
1401 +#endif
1402 +
1403 +#define REG32(addr)                    (*(volatile unsigned long  * const)(addr))
1404 +
1405 +/* Define frame size */
1406 +#define GMAC_MAX_ETH_FRAME_SIZE                1514
1407 +#define GMAC_TX_BUF_SIZE               ((GMAC_MAX_ETH_FRAME_SIZE + 31) & (~31))
1408 +
1409 +#define SW_RX_BUF_SIZE                 1536
1410 +#define HW_RX_BUF_SIZE                 1536
1411 +
1412 +#define GMAC_DEV_TX_TIMEOUT            (10*HZ)
1413 +#define        SKB_RESERVE_BYTES               16
1414 +
1415 +/*
1416 + * Base Registers
1417 + */
1418 +#define TOE_NONTOE_QUE_HDR_BASE                0x2000
1419 +#define TOE_TOE_QUE_HDR_BASE           0x3000
1420 +#define TOE_V_BIT_BASE                 0x4000
1421 +#define TOE_A_BIT_BASE                 0x6000
1422 +#define TOE_GMAC_DMA_BASE(x)           (0x8000 + 0x4000 * (x))
1423 +#define TOE_GMAC_BASE(x)               (0xA000 + 0x4000 * (x))
1424 +
1425 +/*
1426 + * Queue ID
1427 + */
1428 +#define TOE_SW_FREE_QID                        0x00
1429 +#define TOE_HW_FREE_QID                        0x01
1430 +#define TOE_GMAC0_SW_TXQ0_QID          0x02
1431 +#define TOE_GMAC0_SW_TXQ1_QID          0x03
1432 +#define TOE_GMAC0_SW_TXQ2_QID          0x04
1433 +#define TOE_GMAC0_SW_TXQ3_QID          0x05
1434 +#define TOE_GMAC0_SW_TXQ4_QID          0x06
1435 +#define TOE_GMAC0_SW_TXQ5_QID          0x07
1436 +#define TOE_GMAC0_HW_TXQ0_QID          0x08
1437 +#define TOE_GMAC0_HW_TXQ1_QID          0x09
1438 +#define TOE_GMAC0_HW_TXQ2_QID          0x0A
1439 +#define TOE_GMAC0_HW_TXQ3_QID          0x0B
1440 +#define TOE_GMAC1_SW_TXQ0_QID          0x12
1441 +#define TOE_GMAC1_SW_TXQ1_QID          0x13
1442 +#define TOE_GMAC1_SW_TXQ2_QID          0x14
1443 +#define TOE_GMAC1_SW_TXQ3_QID          0x15
1444 +#define TOE_GMAC1_SW_TXQ4_QID          0x16
1445 +#define TOE_GMAC1_SW_TXQ5_QID          0x17
1446 +#define TOE_GMAC1_HW_TXQ0_QID          0x18
1447 +#define TOE_GMAC1_HW_TXQ1_QID          0x19
1448 +#define TOE_GMAC1_HW_TXQ2_QID          0x1A
1449 +#define TOE_GMAC1_HW_TXQ3_QID          0x1B
1450 +#define TOE_GMAC0_DEFAULT_QID          0x20
1451 +#define TOE_GMAC1_DEFAULT_QID          0x21
1452 +#define TOE_CLASSIFICATION_QID(x)      (0x22 + x)      // 0x22 ~ 0x2F
1453 +#define TOE_TOE_QID(x)                 (0x40 + x)      // 0x40 ~ 0x7F
1454 +
1455 +/*
1456 + * TOE DMA Queue Number should be 2^n, n = 6...12
1457 + * TOE DMA Queues are the following queue types:
1458 + *             SW Free Queue, HW Free Queue,
1459 + *             GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
1460 + * They have same descriptor numbers.
1461 + * The base address and descriptor number are configured at
1462 + * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
1463 + */
1464 +#define TOE_SW_FREEQ_DESC_POWER                8
1465 +#define TOE_SW_FREEQ_DESC_NUM          (1<<TOE_SW_FREEQ_DESC_POWER)
1466 +#define TOE_HW_FREEQ_DESC_POWER                8
1467 +#define TOE_HW_FREEQ_DESC_NUM          (1<<TOE_HW_FREEQ_DESC_POWER)
1468 +#define TOE_GMAC_SWTXQ_DESC_POWER      8
1469 +#define TOE_GMAC_SWTXQ_DESC_NUM                (1<<TOE_GMAC_SWTXQ_DESC_POWER)
1470 +#define TOE_GMAC_HWTXQ_DESC_POWER      8
1471 +#define TOE_GMAC_HWTXQ_DESC_NUM                (1<<TOE_GMAC_HWTXQ_DESC_POWER)
1472 +#define TOE_DEFAULT_Q_DESC_POWER       8
1473 +#define TOE_DEFAULT_Q_DESC_NUM         (1<<TOE_DEFAULT_Q_DESC_POWER)
1474 +#define TOE_TOE_DESC_POWER             8
1475 +#define TOE_TOE_DESC_NUM               (1<<TOE_TOE_DESC_POWER)
1476 +#define TOE_CLASS_DESC_POWER           8
1477 +#define TOE_CLASS_DESC_NUM             (1<<TOE_CLASS_DESC_POWER)
1478 +#define TOE_INTR_DESC_POWER            8
1479 +#define TOE_INTR_DESC_NUM              (1<<TOE_INTR_DESC_POWER)
1480 +
1481 +#define TOE_TOE_QUEUE_MAX      64
1482 +#define TOE_TOE_QUEUE_NUM      64
1483 +#define TOE_CLASS_QUEUE_MAX    14
1484 +#define TOE_CLASS_QUEUE_NUM    14
1485 +#define TOE_INTR_QUEUE_MAX     4
1486 +#define TOE_INTR_QUEUE_NUM     4
1487 +#define TOE_SW_TXQ_MAX         6
1488 +#define TOE_SW_TXQ_NUM         1
1489 +#define TOE_HW_TXQ_MAX         4
1490 +#define TOE_HW_TXQ_NUM         4
1491 +
1492 +#define RWPTR_ADVANCE_ONE(x, max)      ((x == (max -1)) ? 0 : x+1)
1493 +#define RWPTR_RECEDE_ONE(x, max)       ((x == 0) ? (max -1) : x-1)
1494 +#define SET_WPTR(addr, data)           (*(volatile u16 * const)((u32)(addr) + 2) = (u16)data)
1495 +#define SET_RPTR(addr, data)           (*(volatile u16 * const)((u32)(addr)) = (u16)data)
1496 +
1497 +/*
1498 + * Global registers
1499 + * #define TOE_GLOBAL_BASE                     (TOE_BASE + 0x0000)
1500 + * Base 0x60000000
1501 + */
1502 +#define GLOBAL_TOE_VERSION_REG         0x0000
1503 +#define GLOBAL_SW_FREEQ_BASE_SIZE_REG  0x0004
1504 +#define GLOBAL_HW_FREEQ_BASE_SIZE_REG  0x0008
1505 +#define GLOBAL_DMA_SKB_SIZE_REG                0x0010
1506 +#define GLOBAL_SWFQ_RWPTR_REG          0x0014
1507 +#define GLOBAL_HWFQ_RWPTR_REG          0x0018
1508 +#define GLOBAL_INTERRUPT_STATUS_0_REG  0x0020
1509 +#define GLOBAL_INTERRUPT_ENABLE_0_REG  0x0024
1510 +#define GLOBAL_INTERRUPT_SELECT_0_REG  0x0028
1511 +#define GLOBAL_INTERRUPT_STATUS_1_REG  0x0030
1512 +#define GLOBAL_INTERRUPT_ENABLE_1_REG  0x0034
1513 +#define GLOBAL_INTERRUPT_SELECT_1_REG  0x0038
1514 +#define GLOBAL_INTERRUPT_STATUS_2_REG  0x0040
1515 +#define GLOBAL_INTERRUPT_ENABLE_2_REG  0x0044
1516 +#define GLOBAL_INTERRUPT_SELECT_2_REG  0x0048
1517 +#define GLOBAL_INTERRUPT_STATUS_3_REG  0x0050
1518 +#define GLOBAL_INTERRUPT_ENABLE_3_REG  0x0054
1519 +#define GLOBAL_INTERRUPT_SELECT_3_REG  0x0058
1520 +#define GLOBAL_INTERRUPT_STATUS_4_REG  0x0060
1521 +#define GLOBAL_INTERRUPT_ENABLE_4_REG  0x0064
1522 +#define GLOBAL_INTERRUPT_SELECT_4_REG  0x0068
1523 +#define GLOBAL_HASH_TABLE_BASE_REG     0x006C
1524 +#define GLOBAL_QUEUE_THRESHOLD_REG     0x0070
1525 +
1526 +/*
1527 + * GMAC 0/1 DMA/TOE register
1528 + * #define TOE_GMAC0_DMA_BASE          (TOE_BASE + 0x8000)
1529 + * #define TOE_GMAC1_DMA_BASE          (TOE_BASE + 0xC000)
1530 + * Base 0x60008000 or 0x6000C000
1531 + */
1532 +#define GMAC_DMA_CTRL_REG              0x0000
1533 +#define GMAC_TX_WEIGHTING_CTRL_0_REG   0x0004
1534 +#define GMAC_TX_WEIGHTING_CTRL_1_REG   0x0008
1535 +#define GMAC_SW_TX_QUEUE0_PTR_REG      0x000C
1536 +#define GMAC_SW_TX_QUEUE1_PTR_REG      0x0010
1537 +#define GMAC_SW_TX_QUEUE2_PTR_REG      0x0014
1538 +#define GMAC_SW_TX_QUEUE3_PTR_REG      0x0018
1539 +#define GMAC_SW_TX_QUEUE4_PTR_REG      0x001C
1540 +#define GMAC_SW_TX_QUEUE5_PTR_REG      0x0020
1541 +#define GMAC_HW_TX_QUEUE0_PTR_REG      0x0024
1542 +#define GMAC_HW_TX_QUEUE1_PTR_REG      0x0028
1543 +#define GMAC_HW_TX_QUEUE2_PTR_REG      0x002C
1544 +#define GMAC_HW_TX_QUEUE3_PTR_REG      0x0030
1545 +#define GMAC_DMA_TX_FIRST_DESC_REG     0x0038
1546 +#define GMAC_DMA_TX_CURR_DESC_REG      0x003C
1547 +#define GMAC_DMA_TX_DESC_WORD0_REG     0x0040
1548 +#define GMAC_DMA_TX_DESC_WORD1_REG     0x0044
1549 +#define GMAC_DMA_TX_DESC_WORD2_REG     0x0048
1550 +#define GMAC_DMA_TX_DESC_WORD3_REG     0x004C
1551 +#define GMAC_SW_TX_QUEUE_BASE_REG      0x0050
1552 +#define GMAC_HW_TX_QUEUE_BASE_REG      0x0054
1553 +#define GMAC_DMA_RX_FIRST_DESC_REG     0x0058
1554 +#define GMAC_DMA_RX_CURR_DESC_REG      0x005C
1555 +#define GMAC_DMA_RX_DESC_WORD0_REG     0x0060
1556 +#define GMAC_DMA_RX_DESC_WORD1_REG     0x0064
1557 +#define GMAC_DMA_RX_DESC_WORD2_REG     0x0068
1558 +#define GMAC_DMA_RX_DESC_WORD3_REG     0x006C
1559 +#define GMAC_HASH_ENGINE_REG0          0x0070
1560 +#define GMAC_HASH_ENGINE_REG1          0x0074
1561 +/* matching rule 0 Control register 0 */
1562 +#define GMAC_MR0CR0                    0x0078
1563 +#define GMAC_MR0CR1                    0x007C
1564 +#define GMAC_MR0CR2                    0x0080
1565 +#define GMAC_MR1CR0                    0x0084
1566 +#define GMAC_MR1CR1                    0x0088
1567 +#define GMAC_MR1CR2                    0x008C
1568 +#define GMAC_MR2CR0                    0x0090
1569 +#define GMAC_MR2CR1                    0x0094
1570 +#define GMAC_MR2CR2                    0x0098
1571 +#define GMAC_MR3CR0                    0x009C
1572 +#define GMAC_MR3CR1                    0x00A0
1573 +#define GMAC_MR3CR2                    0x00A4
1574 +/* Support Protocol Regsister 0 */
1575 +#define GMAC_SPR0                      0x00A8
1576 +#define GMAC_SPR1                      0x00AC
1577 +#define GMAC_SPR2                      0x00B0
1578 +#define GMAC_SPR3                      0x00B4
1579 +#define GMAC_SPR4                      0x00B8
1580 +#define GMAC_SPR5                      0x00BC
1581 +#define GMAC_SPR6                      0x00C0
1582 +#define GMAC_SPR7                      0x00C4
1583 +/* GMAC Hash/Rx/Tx AHB Weighting register */
1584 +#define GMAC_AHB_WEIGHT_REG            0x00C8
1585 +
1586 +/*
1587 + * TOE GMAC 0/1 register
1588 + * #define TOE_GMAC0_BASE                              (TOE_BASE + 0xA000)
1589 + * #define TOE_GMAC1_BASE                              (TOE_BASE + 0xE000)
1590 + * Base 0x6000A000 or 0x6000E000
1591 + */
1592 +enum GMAC_REGISTER {
1593 +       GMAC_STA_ADD0   = 0x0000,
1594 +       GMAC_STA_ADD1   = 0x0004,
1595 +       GMAC_STA_ADD2   = 0x0008,
1596 +       GMAC_RX_FLTR    = 0x000c,
1597 +       GMAC_MCAST_FIL0 = 0x0010,
1598 +       GMAC_MCAST_FIL1 = 0x0014,
1599 +       GMAC_CONFIG0    = 0x0018,
1600 +       GMAC_CONFIG1    = 0x001c,
1601 +       GMAC_CONFIG2    = 0x0020,
1602 +       GMAC_CONFIG3    = 0x0024,
1603 +       GMAC_RESERVED   = 0x0028,
1604 +       GMAC_STATUS     = 0x002c,
1605 +       GMAC_IN_DISCARDS= 0x0030,
1606 +       GMAC_IN_ERRORS  = 0x0034,
1607 +       GMAC_IN_MCAST   = 0x0038,
1608 +       GMAC_IN_BCAST   = 0x003c,
1609 +       GMAC_IN_MAC1    = 0x0040,       /* for STA 1 MAC Address */
1610 +       GMAC_IN_MAC2    = 0x0044        /* for STA 2 MAC Address */
1611 +};
1612 +
1613 +/*
1614 + * DMA Queues description Ring Base Address/Size Register (offset 0x0004)
1615 + */
1616 +typedef union {
1617 +       unsigned int bits32;
1618 +       unsigned int base_size;
1619 +} DMA_Q_BASE_SIZE_T;
1620 +#define DMA_Q_BASE_MASK        (~0x0f)
1621 +
1622 +/*
1623 + * DMA SKB Buffer register (offset 0x0008)
1624 + */
1625 +typedef union {
1626 +       unsigned int bits32;
1627 +       struct bit_0008 {
1628 +               unsigned int sw_skb_size : 16;  /* SW Free poll SKB Size */
1629 +               unsigned int hw_skb_size : 16;  /* HW Free poll SKB Size */
1630 +       } bits;
1631 +} DMA_SKB_SIZE_T;
1632 +
1633 +/*
1634 + * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C)
1635 + */
1636 +typedef union {
1637 +       unsigned int bits32;
1638 +       struct bit_000c {
1639 +               unsigned int rptr       : 16;   /* Read Ptr, RO */
1640 +               unsigned int wptr       : 16;   /* Write Ptr, RW */
1641 +       } bits;
1642 +} DMA_RWPTR_T;
1643 +
1644 +/*
1645 + * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010)
1646 + * see DMA_RWPTR_T structure
1647 + */
1648 +
1649 +/*
1650 + * Interrupt Status Register 0         (offset 0x0020)
1651 + * Interrupt Mask Register 0   (offset 0x0024)
1652 + * Interrupt Select Register 0         (offset 0x0028)
1653 + */
1654 +typedef union {
1655 +       unsigned int bits32;
1656 +       struct bit_0020 {
1657 +               /* GMAC0 SW Tx Queue 0 EOF Interrupt */
1658 +               unsigned int swtq00_eof : 1;
1659 +               unsigned int swtq01_eof : 1;
1660 +               unsigned int swtq02_eof : 1;
1661 +               unsigned int swtq03_eof : 1;
1662 +               unsigned int swtq04_eof : 1;
1663 +               unsigned int swtq05_eof : 1;
1664 +               /* GMAC1 SW Tx Queue 0 EOF Interrupt */
1665 +               unsigned int swtq10_eof : 1;
1666 +               unsigned int swtq11_eof : 1;
1667 +               unsigned int swtq12_eof : 1;
1668 +               unsigned int swtq13_eof : 1;
1669 +               unsigned int swtq14_eof : 1;
1670 +               unsigned int swtq15_eof : 1;
1671 +               /* GMAC0 SW Tx Queue 0 Finish Interrupt */
1672 +               unsigned int swtq00_fin : 1;
1673 +               unsigned int swtq01_fin : 1;
1674 +               unsigned int swtq02_fin : 1;
1675 +               unsigned int swtq03_fin : 1;
1676 +               unsigned int swtq04_fin : 1;
1677 +               unsigned int swtq05_fin : 1;
1678 +               /* GMAC1 SW Tx Queue 0 Finish Interrupt */
1679 +               unsigned int swtq10_fin : 1;
1680 +               unsigned int swtq11_fin : 1;
1681 +               unsigned int swtq12_fin : 1;
1682 +               unsigned int swtq13_fin : 1;
1683 +               unsigned int swtq14_fin : 1;
1684 +               unsigned int swtq15_fin : 1;
1685 +               /* GMAC0 Rx Descriptor Protocol Error */
1686 +               unsigned int rxPerr0    : 1;
1687 +               /* GMAC0 AHB Bus Error while Rx */
1688 +               unsigned int rxDerr0    : 1;
1689 +               /* GMAC1 Rx Descriptor Protocol Error */
1690 +               unsigned int rxPerr1    : 1;
1691 +               /* GMAC1 AHB Bus Error while Rx */
1692 +               unsigned int rxDerr1    : 1;
1693 +               /* GMAC0 Tx Descriptor Protocol Error */
1694 +               unsigned int txPerr0    : 1;
1695 +               /* GMAC0 AHB Bus Error while Tx */
1696 +               unsigned int txDerr0    : 1;
1697 +               /* GMAC1 Tx Descriptor Protocol Error */
1698 +               unsigned int txPerr1    : 1;
1699 +               /* GMAC1 AHB Bus Error while Tx */
1700 +               unsigned int txDerr1    : 1;
1701 +       } bits;
1702 +} INTR_REG0_T;
1703 +
1704 +#define GMAC1_TXDERR_INT_BIT           BIT(31)
1705 +#define GMAC1_TXPERR_INT_BIT           BIT(30)
1706 +#define GMAC0_TXDERR_INT_BIT           BIT(29)
1707 +#define GMAC0_TXPERR_INT_BIT           BIT(28)
1708 +#define GMAC1_RXDERR_INT_BIT           BIT(27)
1709 +#define GMAC1_RXPERR_INT_BIT           BIT(26)
1710 +#define GMAC0_RXDERR_INT_BIT           BIT(25)
1711 +#define GMAC0_RXPERR_INT_BIT           BIT(24)
1712 +#define GMAC1_SWTQ15_FIN_INT_BIT       BIT(23)
1713 +#define GMAC1_SWTQ14_FIN_INT_BIT       BIT(22)
1714 +#define GMAC1_SWTQ13_FIN_INT_BIT       BIT(21)
1715 +#define GMAC1_SWTQ12_FIN_INT_BIT       BIT(20)
1716 +#define GMAC1_SWTQ11_FIN_INT_BIT       BIT(19)
1717 +#define GMAC1_SWTQ10_FIN_INT_BIT       BIT(18)
1718 +#define GMAC0_SWTQ05_FIN_INT_BIT       BIT(17)
1719 +#define GMAC0_SWTQ04_FIN_INT_BIT       BIT(16)
1720 +#define GMAC0_SWTQ03_FIN_INT_BIT       BIT(15)
1721 +#define GMAC0_SWTQ02_FIN_INT_BIT       BIT(14)
1722 +#define GMAC0_SWTQ01_FIN_INT_BIT       BIT(13)
1723 +#define GMAC0_SWTQ00_FIN_INT_BIT       BIT(12)
1724 +#define GMAC1_SWTQ15_EOF_INT_BIT       BIT(11)
1725 +#define GMAC1_SWTQ14_EOF_INT_BIT       BIT(10)
1726 +#define GMAC1_SWTQ13_EOF_INT_BIT       BIT(9)
1727 +#define GMAC1_SWTQ12_EOF_INT_BIT       BIT(8)
1728 +#define GMAC1_SWTQ11_EOF_INT_BIT       BIT(7)
1729 +#define GMAC1_SWTQ10_EOF_INT_BIT       BIT(6)
1730 +#define GMAC0_SWTQ05_EOF_INT_BIT       BIT(5)
1731 +#define GMAC0_SWTQ04_EOF_INT_BIT       BIT(4)
1732 +#define GMAC0_SWTQ03_EOF_INT_BIT       BIT(3)
1733 +#define GMAC0_SWTQ02_EOF_INT_BIT       BIT(2)
1734 +#define GMAC0_SWTQ01_EOF_INT_BIT       BIT(1)
1735 +#define GMAC0_SWTQ00_EOF_INT_BIT       BIT(0)
1736 +
1737 +/*
1738 + * Interrupt Status Register 1         (offset 0x0030)
1739 + * Interrupt Mask Register 1   (offset 0x0034)
1740 + * Interrupt Select Register 1         (offset 0x0038)
1741 + */
1742 +typedef union {
1743 +       unsigned int bits32;
1744 +       struct bit_0030 {
1745 +               unsigned int default_q0_eof     : 1;    /* Default Queue 0 EOF Interrupt */
1746 +               unsigned int default_q1_eof     : 1;    /* Default Queue 1 EOF Interrupt */
1747 +               unsigned int class_rx           : 14;   /* Classification Queue Rx Interrupt */
1748 +               unsigned int hwtq00_eof         : 1;    /* GMAC0 HW Tx Queue0 EOF Interrupt */
1749 +               unsigned int hwtq01_eof         : 1;    /* GMAC0 HW Tx Queue1 EOF Interrupt */
1750 +               unsigned int hwtq02_eof         : 1;    /* GMAC0 HW Tx Queue2 EOF Interrupt */
1751 +               unsigned int hwtq03_eof         : 1;    /* GMAC0 HW Tx Queue3 EOF Interrupt */
1752 +               unsigned int hwtq10_eof         : 1;    /* GMAC1 HW Tx Queue0 EOF Interrupt */
1753 +               unsigned int hwtq11_eof         : 1;    /* GMAC1 HW Tx Queue1 EOF Interrupt */
1754 +               unsigned int hwtq12_eof         : 1;    /* GMAC1 HW Tx Queue2 EOF Interrupt */
1755 +               unsigned int hwtq13_eof         : 1;    /* GMAC1 HW Tx Queue3 EOF Interrupt */
1756 +               unsigned int toe_iq0_intr       : 1;    /* TOE Interrupt Queue 0 with Interrupts */
1757 +               unsigned int toe_iq1_intr       : 1;    /* TOE Interrupt Queue 1 with Interrupts */
1758 +               unsigned int toe_iq2_intr       : 1;    /* TOE Interrupt Queue 2 with Interrupts */
1759 +               unsigned int toe_iq3_intr       : 1;    /* TOE Interrupt Queue 3 with Interrupts */
1760 +               unsigned int toe_iq0_full       : 1;    /* TOE Interrupt Queue 0 Full Interrupt */
1761 +               unsigned int toe_iq1_full       : 1;    /* TOE Interrupt Queue 1 Full Interrupt */
1762 +               unsigned int toe_iq2_full       : 1;    /* TOE Interrupt Queue 2 Full Interrupt */
1763 +               unsigned int toe_iq3_full       : 1;    /* TOE Interrupt Queue 3 Full Interrupt */
1764 +       } bits;
1765 +} INTR_REG1_T;
1766 +
1767 +#define TOE_IQ3_FULL_INT_BIT           BIT(31)
1768 +#define TOE_IQ2_FULL_INT_BIT           BIT(30)
1769 +#define TOE_IQ1_FULL_INT_BIT           BIT(29)
1770 +#define TOE_IQ0_FULL_INT_BIT           BIT(28)
1771 +#define TOE_IQ3_INT_BIT                        BIT(27)
1772 +#define TOE_IQ2_INT_BIT                        BIT(26)
1773 +#define TOE_IQ1_INT_BIT                        BIT(25)
1774 +#define TOE_IQ0_INT_BIT                        BIT(24)
1775 +#define GMAC1_HWTQ13_EOF_INT_BIT       BIT(23)
1776 +#define GMAC1_HWTQ12_EOF_INT_BIT       BIT(22)
1777 +#define GMAC1_HWTQ11_EOF_INT_BIT       BIT(21)
1778 +#define GMAC1_HWTQ10_EOF_INT_BIT       BIT(20)
1779 +#define GMAC0_HWTQ03_EOF_INT_BIT       BIT(19)
1780 +#define GMAC0_HWTQ02_EOF_INT_BIT       BIT(18)
1781 +#define GMAC0_HWTQ01_EOF_INT_BIT       BIT(17)
1782 +#define GMAC0_HWTQ00_EOF_INT_BIT       BIT(16)
1783 +#define CLASS_RX_INT_BIT(x)            BIT((x + 2))
1784 +#define DEFAULT_Q1_INT_BIT             BIT(1)
1785 +#define DEFAULT_Q0_INT_BIT             BIT(0)
1786 +
1787 +#define TOE_IQ_INT_BITS                (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
1788 +                                TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
1789 +#define        TOE_IQ_FULL_BITS        (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
1790 +                                TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
1791 +#define        TOE_IQ_ALL_BITS         (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
1792 +#define TOE_CLASS_RX_INT_BITS  0xfffc
1793 +
1794 +/*
1795 + * Interrupt Status Register 2         (offset 0x0040)
1796 + * Interrupt Mask Register 2   (offset 0x0044)
1797 + * Interrupt Select Register 2         (offset 0x0048)
1798 + */
1799 +typedef union {
1800 +       unsigned int bits32;
1801 +       struct bit_0040 {
1802 +               unsigned int toe_q0_full        : 1;    // bit 0        TOE Queue 0 Full Interrupt
1803 +               unsigned int toe_q1_full        : 1;    // bit 1        TOE Queue 1 Full Interrupt
1804 +               unsigned int toe_q2_full        : 1;    // bit 2        TOE Queue 2 Full Interrupt
1805 +               unsigned int toe_q3_full        : 1;    // bit 3        TOE Queue 3 Full Interrupt
1806 +               unsigned int toe_q4_full        : 1;    // bit 4        TOE Queue 4 Full Interrupt
1807 +               unsigned int toe_q5_full        : 1;    // bit 5        TOE Queue 5 Full Interrupt
1808 +               unsigned int toe_q6_full        : 1;    // bit 6        TOE Queue 6 Full Interrupt
1809 +               unsigned int toe_q7_full        : 1;    // bit 7        TOE Queue 7 Full Interrupt
1810 +               unsigned int toe_q8_full        : 1;    // bit 8        TOE Queue 8 Full Interrupt
1811 +               unsigned int toe_q9_full        : 1;    // bit 9        TOE Queue 9 Full Interrupt
1812 +               unsigned int toe_q10_full       : 1;    // bit 10       TOE Queue 10 Full Interrupt
1813 +               unsigned int toe_q11_full       : 1;    // bit 11       TOE Queue 11 Full Interrupt
1814 +               unsigned int toe_q12_full       : 1;    // bit 12       TOE Queue 12 Full Interrupt
1815 +               unsigned int toe_q13_full       : 1;    // bit 13       TOE Queue 13 Full Interrupt
1816 +               unsigned int toe_q14_full       : 1;    // bit 14       TOE Queue 14 Full Interrupt
1817 +               unsigned int toe_q15_full       : 1;    // bit 15       TOE Queue 15 Full Interrupt
1818 +               unsigned int toe_q16_full       : 1;    // bit 16       TOE Queue 16 Full Interrupt
1819 +               unsigned int toe_q17_full       : 1;    // bit 17       TOE Queue 17 Full Interrupt
1820 +               unsigned int toe_q18_full       : 1;    // bit 18       TOE Queue 18 Full Interrupt
1821 +               unsigned int toe_q19_full       : 1;    // bit 19       TOE Queue 19 Full Interrupt
1822 +               unsigned int toe_q20_full       : 1;    // bit 20       TOE Queue 20 Full Interrupt
1823 +               unsigned int toe_q21_full       : 1;    // bit 21       TOE Queue 21 Full Interrupt
1824 +               unsigned int toe_q22_full       : 1;    // bit 22       TOE Queue 22 Full Interrupt
1825 +               unsigned int toe_q23_full       : 1;    // bit 23       TOE Queue 23 Full Interrupt
1826 +               unsigned int toe_q24_full       : 1;    // bit 24       TOE Queue 24 Full Interrupt
1827 +               unsigned int toe_q25_full       : 1;    // bit 25       TOE Queue 25 Full Interrupt
1828 +               unsigned int toe_q26_full       : 1;    // bit 26       TOE Queue 26 Full Interrupt
1829 +               unsigned int toe_q27_full       : 1;    // bit 27       TOE Queue 27 Full Interrupt
1830 +               unsigned int toe_q28_full       : 1;    // bit 28       TOE Queue 28 Full Interrupt
1831 +               unsigned int toe_q29_full       : 1;    // bit 29       TOE Queue 29 Full Interrupt
1832 +               unsigned int toe_q30_full       : 1;    // bit 30       TOE Queue 30 Full Interrupt
1833 +               unsigned int toe_q31_full       : 1;    // bit 31       TOE Queue 31 Full Interrupt
1834 +       } bits;
1835 +} INTR_REG2_T;
1836 +
1837 +#define TOE_QL_FULL_INT_BIT(x)         BIT(x)
1838 +
1839 +/*
1840 + * Interrupt Status Register 3         (offset 0x0050)
1841 + * Interrupt Mask Register 3   (offset 0x0054)
1842 + * Interrupt Select Register 3         (offset 0x0058)
1843 + */
1844 +typedef union {
1845 +       unsigned int bits32;
1846 +       struct bit_0050 {
1847 +               unsigned int toe_q32_full       : 1;    // bit 32       TOE Queue 32 Full Interrupt
1848 +               unsigned int toe_q33_full       : 1;    // bit 33       TOE Queue 33 Full Interrupt
1849 +               unsigned int toe_q34_full       : 1;    // bit 34       TOE Queue 34 Full Interrupt
1850 +               unsigned int toe_q35_full       : 1;    // bit 35       TOE Queue 35 Full Interrupt
1851 +               unsigned int toe_q36_full       : 1;    // bit 36       TOE Queue 36 Full Interrupt
1852 +               unsigned int toe_q37_full       : 1;    // bit 37       TOE Queue 37 Full Interrupt
1853 +               unsigned int toe_q38_full       : 1;    // bit 38       TOE Queue 38 Full Interrupt
1854 +               unsigned int toe_q39_full       : 1;    // bit 39       TOE Queue 39 Full Interrupt
1855 +               unsigned int toe_q40_full       : 1;    // bit 40       TOE Queue 40 Full Interrupt
1856 +               unsigned int toe_q41_full       : 1;    // bit 41       TOE Queue 41 Full Interrupt
1857 +               unsigned int toe_q42_full       : 1;    // bit 42       TOE Queue 42 Full Interrupt
1858 +               unsigned int toe_q43_full       : 1;    // bit 43       TOE Queue 43 Full Interrupt
1859 +               unsigned int toe_q44_full       : 1;    // bit 44       TOE Queue 44 Full Interrupt
1860 +               unsigned int toe_q45_full       : 1;    // bit 45       TOE Queue 45 Full Interrupt
1861 +               unsigned int toe_q46_full       : 1;    // bit 46       TOE Queue 46 Full Interrupt
1862 +               unsigned int toe_q47_full       : 1;    // bit 47       TOE Queue 47 Full Interrupt
1863 +               unsigned int toe_q48_full       : 1;    // bit 48       TOE Queue 48 Full Interrupt
1864 +               unsigned int toe_q49_full       : 1;    // bit 49       TOE Queue 49 Full Interrupt
1865 +               unsigned int toe_q50_full       : 1;    // bit 50       TOE Queue 50 Full Interrupt
1866 +               unsigned int toe_q51_full       : 1;    // bit 51       TOE Queue 51 Full Interrupt
1867 +               unsigned int toe_q52_full       : 1;    // bit 52       TOE Queue 52 Full Interrupt
1868 +               unsigned int toe_q53_full       : 1;    // bit 53       TOE Queue 53 Full Interrupt
1869 +               unsigned int toe_q54_full       : 1;    // bit 54       TOE Queue 54 Full Interrupt
1870 +               unsigned int toe_q55_full       : 1;    // bit 55       TOE Queue 55 Full Interrupt
1871 +               unsigned int toe_q56_full       : 1;    // bit 56       TOE Queue 56 Full Interrupt
1872 +               unsigned int toe_q57_full       : 1;    // bit 57       TOE Queue 57 Full Interrupt
1873 +               unsigned int toe_q58_full       : 1;    // bit 58       TOE Queue 58 Full Interrupt
1874 +               unsigned int toe_q59_full       : 1;    // bit 59       TOE Queue 59 Full Interrupt
1875 +               unsigned int toe_q60_full       : 1;    // bit 60       TOE Queue 60 Full Interrupt
1876 +               unsigned int toe_q61_full       : 1;    // bit 61       TOE Queue 61 Full Interrupt
1877 +               unsigned int toe_q62_full       : 1;    // bit 62       TOE Queue 62 Full Interrupt
1878 +               unsigned int toe_q63_full       : 1;    // bit 63       TOE Queue 63 Full Interrupt
1879 +       } bits;
1880 +} INTR_REG3_T;
1881 +
1882 +#define TOE_QH_FULL_INT_BIT(x)         BIT(x-32)
1883 +
1884 +/*
1885 + * Interrupt Status Register 4         (offset 0x0060)
1886 + * Interrupt Mask Register 4   (offset 0x0064)
1887 + * Interrupt Select Register 4         (offset 0x0068)
1888 + */
1889 +typedef union {
1890 +       unsigned char byte;
1891 +       struct bit_0060 {
1892 +               unsigned char status_changed    : 1;    // Status Changed Intr for RGMII Mode
1893 +               unsigned char rx_overrun        : 1;   // GMAC Rx FIFO overrun interrupt
1894 +               unsigned char tx_pause_off      : 1;    // received pause off frame interrupt
1895 +               unsigned char rx_pause_off      : 1;    // received pause off frame interrupt
1896 +               unsigned char tx_pause_on       : 1;    // transmit pause on frame interrupt
1897 +               unsigned char rx_pause_on       : 1;    // received pause on frame interrupt
1898 +               unsigned char cnt_full          : 1;    // MIB counters half full interrupt
1899 +               unsigned char reserved          : 1;    //
1900 +       } _PACKED_ bits;
1901 +} _PACKED_ GMAC_INTR_T;
1902 +
1903 +typedef union {
1904 +       unsigned int bits32;
1905 +       struct bit_0060_2 {
1906 +               unsigned int    swfq_empty      : 1;    // bit 0        Software Free Queue Empty Intr.
1907 +               unsigned int    hwfq_empty      : 1;    // bit 1        Hardware Free Queue Empty Intr.
1908 +               unsigned int    class_qf_int    : 14;   // bit 15:2 Classification Rx Queue13-0 Full Intr.
1909 +               GMAC_INTR_T     gmac0;
1910 +               GMAC_INTR_T     gmac1;
1911 +       } bits;
1912 +} INTR_REG4_T;
1913 +
1914 +#define GMAC1_RESERVED_INT_BIT         BIT(31)
1915 +#define GMAC1_MIB_INT_BIT              BIT(30)
1916 +#define GMAC1_RX_PAUSE_ON_INT_BIT      BIT(29)
1917 +#define GMAC1_TX_PAUSE_ON_INT_BIT      BIT(28)
1918 +#define GMAC1_RX_PAUSE_OFF_INT_BIT     BIT(27)
1919 +#define GMAC1_TX_PAUSE_OFF_INT_BIT     BIT(26)
1920 +#define GMAC1_RX_OVERRUN_INT_BIT       BIT(25)
1921 +#define GMAC1_STATUS_CHANGE_INT_BIT    BIT(24)
1922 +#define GMAC0_RESERVED_INT_BIT         BIT(23)
1923 +#define GMAC0_MIB_INT_BIT              BIT(22)
1924 +#define GMAC0_RX_PAUSE_ON_INT_BIT      BIT(21)
1925 +#define GMAC0_TX_PAUSE_ON_INT_BIT      BIT(20)
1926 +#define GMAC0_RX_PAUSE_OFF_INT_BIT     BIT(19)
1927 +#define GMAC0_TX_PAUSE_OFF_INT_BIT     BIT(18)
1928 +#define GMAC0_RX_OVERRUN_INT_BIT       BIT(17)
1929 +#define GMAC0_STATUS_CHANGE_INT_BIT    BIT(16)
1930 +#define CLASS_RX_FULL_INT_BIT(x)       BIT((x+2))
1931 +#define HWFQ_EMPTY_INT_BIT             BIT(1)
1932 +#define SWFQ_EMPTY_INT_BIT             BIT(0)
1933 +
1934 +#if 1
1935 +#define GMAC0_INT_BITS         (GMAC0_MIB_INT_BIT)
1936 +#define GMAC1_INT_BITS         (GMAC1_MIB_INT_BIT)
1937 +#else
1938 +#define GMAC0_INT_BITS         (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
1939 +                                GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT |        \
1940 +                                GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT |      \
1941 +                                GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT)
1942 +#define GMAC1_INT_BITS         (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
1943 +                                GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT |        \
1944 +                                GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT |      \
1945 +                                GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT)
1946 +#endif
1947 +
1948 +#define CLASS_RX_FULL_INT_BITS         0xfffc
1949 +
1950 +/*
1951 + * GLOBAL_QUEUE_THRESHOLD_REG  (offset 0x0070)
1952 + */
1953 +typedef union {
1954 +       unsigned int bits32;
1955 +       struct bit_0070_2 {
1956 +               unsigned int    swfq_empty      : 8;    //  7:0         Software Free Queue Empty Threshold
1957 +               unsigned int    hwfq_empty      : 8;    // 15:8         Hardware Free Queue Empty Threshold
1958 +               unsigned int    intrq           : 8;    // 23:16
1959 +               unsigned int    toe_class       : 8;    // 31:24
1960 +       } bits;
1961 +} QUEUE_THRESHOLD_T;
1962 +
1963 +
1964 +/*
1965 + * GMAC DMA Control Register
1966 + * GMAC0 offset 0x8000
1967 + * GMAC1 offset 0xC000
1968 + */
1969 +typedef union {
1970 +       unsigned int bits32;
1971 +       struct bit_8000 {
1972 +               unsigned int    td_bus          : 2;    // bit 1:0      Peripheral Bus Width
1973 +               unsigned int    td_burst_size   : 2;    // bit 3:2      TxDMA max burst size for every AHB request
1974 +               unsigned int    td_prot         : 4;    // bit 7:4      TxDMA protection control
1975 +               unsigned int    rd_bus          : 2;    // bit 9:8      Peripheral Bus Width
1976 +               unsigned int    rd_burst_size   : 2;    // bit 11:10    DMA max burst size for every AHB request
1977 +               unsigned int    rd_prot         : 4;    // bit 15:12    DMA Protection Control
1978 +               unsigned int    rd_insert_bytes : 2;    // bit 17:16
1979 +               unsigned int    reserved        : 10;   // bit 27:18
1980 +               unsigned int    drop_small_ack  : 1;    // bit 28       1: Drop, 0: Accept
1981 +               unsigned int    loopback        : 1;    // bit 29       Loopback TxDMA to RxDMA
1982 +               unsigned int    td_enable       : 1;    // bit 30       Tx DMA Enable
1983 +               unsigned int    rd_enable       : 1;    // bit 31       Rx DMA Enable
1984 +       } bits;
1985 +} GMAC_DMA_CTRL_T;
1986 +
1987 +/*
1988 + * GMAC Tx Weighting Control Register 0
1989 + * GMAC0 offset 0x8004
1990 + * GMAC1 offset 0xC004
1991 + */
1992 +typedef union {
1993 +       unsigned int bits32;
1994 +       struct bit_8004 {
1995 +               unsigned int    hw_tq0          : 6;    // bit 5:0      HW TX Queue 3
1996 +               unsigned int    hw_tq1          : 6;    // bit 11:6     HW TX Queue 2
1997 +               unsigned int    hw_tq2          : 6;    // bit 17:12    HW TX Queue 1
1998 +               unsigned int    hw_tq3          : 6;    // bit 23:18    HW TX Queue 0
1999 +               unsigned int    reserved        : 8;    // bit 31:24
2000 +       } bits;
2001 +} GMAC_TX_WCR0_T;      /* Weighting Control Register 0 */
2002 +
2003 +/*
2004 + * GMAC Tx Weighting Control Register 1
2005 + * GMAC0 offset 0x8008
2006 + * GMAC1 offset 0xC008
2007 + */
2008 +typedef union {
2009 +       unsigned int bits32;
2010 +       struct bit_8008 {
2011 +               unsigned int    sw_tq0          : 5;    // bit 4:0      SW TX Queue 0
2012 +               unsigned int    sw_tq1          : 5;    // bit 9:5      SW TX Queue 1
2013 +               unsigned int    sw_tq2          : 5;    // bit 14:10    SW TX Queue 2
2014 +               unsigned int    sw_tq3          : 5;    // bit 19:15    SW TX Queue 3
2015 +               unsigned int    sw_tq4          : 5;    // bit 24:20    SW TX Queue 4
2016 +               unsigned int    sw_tq5          : 5;    // bit 29:25    SW TX Queue 5
2017 +               unsigned int    reserved        : 2;    // bit 31:30
2018 +       } bits;
2019 +} GMAC_TX_WCR1_T;      /* Weighting Control Register 1 */
2020 +
2021 +/*
2022 + * Queue Read/Write Pointer
2023 + * GMAC SW TX Queue 0~5 Read/Write Pointer register
2024 + * GMAC0 offset 0x800C ~ 0x8020
2025 + * GMAC1 offset 0xC00C ~ 0xC020
2026 + * GMAC HW TX Queue 0~3 Read/Write Pointer register
2027 + * GMAC0 offset 0x8024 ~ 0x8030
2028 + * GMAC1 offset 0xC024 ~ 0xC030
2029 + *
2030 + * see DMA_RWPTR_T structure
2031 + */
2032 +
2033 +/*
2034 + * GMAC DMA Tx First Description Address Register
2035 + * GMAC0 offset 0x8038
2036 + * GMAC1 offset 0xC038
2037 + */
2038 +typedef union {
2039 +       unsigned int bits32;
2040 +       struct bit_8038 {
2041 +               unsigned int reserved           :  3;
2042 +               unsigned int td_busy            :  1;   // bit 3        1: TxDMA busy; 0: TxDMA idle
2043 +               unsigned int td_first_des_ptr   : 28;   // bit 31:4     first descriptor address
2044 +       } bits;
2045 +} GMAC_TXDMA_FIRST_DESC_T;
2046 +
2047 +/*
2048 + * GMAC DMA Tx Current Description Address Register
2049 + * GMAC0 offset 0x803C
2050 + * GMAC1 offset 0xC03C
2051 + */
2052 +typedef union {
2053 +       unsigned int bits32;
2054 +       struct bit_803C {
2055 +               unsigned int reserved           :  4;
2056 +               unsigned int td_curr_desc_ptr   : 28;   // bit 31:4     current descriptor address
2057 +       } bits;
2058 +} GMAC_TXDMA_CURR_DESC_T;
2059 +
2060 +/*
2061 + * GMAC DMA Tx Description Word 0 Register
2062 + * GMAC0 offset 0x8040
2063 + * GMAC1 offset 0xC040
2064 + */
2065 +typedef union {
2066 +       unsigned int bits32;
2067 +       struct bit_8040 {
2068 +               unsigned int buffer_size        : 16;   // bit 15:0     Transfer size
2069 +               unsigned int desc_count         : 6;    // bit 21:16    number of descriptors used for the current frame
2070 +               unsigned int status_tx_ok       : 1;    // bit 22       Tx Status, 1: Successful 0: Failed
2071 +               unsigned int status_rvd         : 6;    // bit 28:23    Tx Status, Reserved bits
2072 +               unsigned int perr               : 1;    // bit 29       protocol error during processing this descriptor
2073 +               unsigned int derr               : 1;    // bit 30       data error during processing this descriptor
2074 +               unsigned int reserved           : 1;    // bit 31
2075 +       } bits;
2076 +} GMAC_TXDESC_0_T;
2077 +
2078 +/*
2079 + * GMAC DMA Tx Description Word 1 Register
2080 + * GMAC0 offset 0x8044
2081 + * GMAC1 offset 0xC044
2082 + */
2083 +typedef union {
2084 +       unsigned int bits32;
2085 +       struct txdesc_word1 {
2086 +               unsigned int    byte_count      : 16;   // bit 15: 0    Tx Frame Byte Count
2087 +               unsigned int    mtu_enable      : 1;    // bit 16       TSS segmentation use MTU setting
2088 +               unsigned int    ip_chksum       : 1;    // bit 17       IPV4 Header Checksum Enable
2089 +               unsigned int    ipv6_enable     : 1;    // bit 18       IPV6 Tx Enable
2090 +               unsigned int    tcp_chksum      : 1;    // bit 19       TCP Checksum Enable
2091 +               unsigned int    udp_chksum      : 1;    // bit 20       UDP Checksum Enable
2092 +               unsigned int    bypass_tss      : 1;    // bit 21
2093 +               unsigned int    ip_fixed_len    : 1;    // bit 22
2094 +               unsigned int    reserved        : 9;    // bit 31:23    Tx Flag, Reserved
2095 +       } bits;
2096 +} GMAC_TXDESC_1_T;
2097 +
2098 +#define TSS_IP_FIXED_LEN_BIT   BIT(22)
2099 +#define TSS_UDP_CHKSUM_BIT     BIT(20)
2100 +#define TSS_TCP_CHKSUM_BIT     BIT(19)
2101 +#define TSS_IPV6_ENABLE_BIT    BIT(18)
2102 +#define TSS_IP_CHKSUM_BIT      BIT(17)
2103 +#define TSS_MTU_ENABLE_BIT     BIT(16)
2104 +
2105 +/*
2106 + * GMAC DMA Tx Description Word 2 Register
2107 + * GMAC0 offset 0x8048
2108 + * GMAC1 offset 0xC048
2109 + */
2110 +typedef union {
2111 +       unsigned int    bits32;
2112 +       unsigned int    buf_adr;
2113 +} GMAC_TXDESC_2_T;
2114 +
2115 +/*
2116 + * GMAC DMA Tx Description Word 3 Register
2117 + * GMAC0 offset 0x804C
2118 + * GMAC1 offset 0xC04C
2119 + */
2120 +typedef union {
2121 +       unsigned int bits32;
2122 +       struct txdesc_word3 {
2123 +               unsigned int    mtu_size        : 11;   // bit 10: 0    Tx Frame Byte Count
2124 +               unsigned int    reserved        : 18;   // bit 28:11
2125 +               unsigned int    eofie           : 1;    // bit 29       End of frame interrupt enable
2126 +               unsigned int    sof_eof         : 2;    // bit 31:30    11: only one, 10: first, 01: last, 00: linking
2127 +       } bits;
2128 +} GMAC_TXDESC_3_T;
2129 +#define SOF_EOF_BIT_MASK       0x3fffffff
2130 +#define SOF_BIT                        0x80000000
2131 +#define EOF_BIT                        0x40000000
2132 +#define EOFIE_BIT              BIT(29)
2133 +#define MTU_SIZE_BIT_MASK      0x7ff
2134 +
2135 +/*
2136 + * GMAC Tx Descriptor
2137 + */
2138 +typedef struct {
2139 +       GMAC_TXDESC_0_T word0;
2140 +       GMAC_TXDESC_1_T word1;
2141 +       GMAC_TXDESC_2_T word2;
2142 +       GMAC_TXDESC_3_T word3;
2143 +} GMAC_TXDESC_T;
2144 +
2145 +/*
2146 + * GMAC DMA Rx First Description Address Register
2147 + * GMAC0 offset 0x8058
2148 + * GMAC1 offset 0xC058
2149 + */
2150 +typedef union {
2151 +       unsigned int bits32;
2152 +       struct bit_8058 {
2153 +               unsigned int reserved           :  3;   // bit 2:0
2154 +               unsigned int rd_busy            :  1;   // bit 3        1-RxDMA busy; 0-RxDMA idle
2155 +               unsigned int rd_first_des_ptr   : 28;   // bit 31:4 first descriptor address
2156 +       } bits;
2157 +} GMAC_RXDMA_FIRST_DESC_T;
2158 +
2159 +/*
2160 + * GMAC DMA Rx Current Description Address Register
2161 + * GMAC0 offset 0x805C
2162 + * GMAC1 offset 0xC05C
2163 + */
2164 +typedef union {
2165 +       unsigned int bits32;
2166 +       struct bit_805C {
2167 +               unsigned int reserved           :  4;   // bit 3:0
2168 +               unsigned int rd_curr_des_ptr    : 28;   // bit 31:4 current descriptor address
2169 +       } bits;
2170 +} GMAC_RXDMA_CURR_DESC_T;
2171 +
2172 +/*
2173 + * GMAC DMA Rx Description Word 0 Register
2174 + * GMAC0 offset 0x8060
2175 + * GMAC1 offset 0xC060
2176 + */
2177 +typedef union {
2178 +       unsigned int bits32;
2179 +       struct bit_8060 {
2180 +               unsigned int buffer_size        : 16;   // bit 15:0  number of descriptors used for the current frame
2181 +               unsigned int desc_count         : 6;    // bit 21:16 number of descriptors used for the current frame
2182 +               unsigned int status             : 4;    // bit 24:22 Status of rx frame
2183 +               unsigned int chksum_status      : 3;    // bit 28:26 Check Sum Status
2184 +               unsigned int perr               : 1;    // bit 29        protocol error during processing this descriptor
2185 +               unsigned int derr               : 1;    // bit 30        data error during processing this descriptor
2186 +               unsigned int drop               : 1;    // bit 31        TOE/CIS Queue Full dropped packet to default queue
2187 +       } bits;
2188 +} GMAC_RXDESC_0_T;
2189 +
2190 +#define                GMAC_RXDESC_0_T_derr                    BIT(30)
2191 +#define                GMAC_RXDESC_0_T_perr                    BIT(29)
2192 +#define                GMAC_RXDESC_0_T_chksum_status(x)        BIT((x+26))
2193 +#define                GMAC_RXDESC_0_T_status(x)               BIT((x+22))
2194 +#define                GMAC_RXDESC_0_T_desc_count(x)           BIT((x+16))
2195 +
2196 +#define        RX_CHKSUM_IP_UDP_TCP_OK                 0
2197 +#define        RX_CHKSUM_IP_OK_ONLY                    1
2198 +#define        RX_CHKSUM_NONE                          2
2199 +#define        RX_CHKSUM_IP_ERR_UNKNOWN                4
2200 +#define        RX_CHKSUM_IP_ERR                        5
2201 +#define        RX_CHKSUM_TCP_UDP_ERR                   6
2202 +#define RX_CHKSUM_NUM                          8
2203 +
2204 +#define RX_STATUS_GOOD_FRAME                   0
2205 +#define RX_STATUS_TOO_LONG_GOOD_CRC            1
2206 +#define RX_STATUS_RUNT_FRAME                   2
2207 +#define RX_STATUS_SFD_NOT_FOUND                        3
2208 +#define RX_STATUS_CRC_ERROR                    4
2209 +#define RX_STATUS_TOO_LONG_BAD_CRC             5
2210 +#define RX_STATUS_ALIGNMENT_ERROR              6
2211 +#define RX_STATUS_TOO_LONG_BAD_ALIGN           7
2212 +#define RX_STATUS_RX_ERR                       8
2213 +#define RX_STATUS_DA_FILTERED                  9
2214 +#define RX_STATUS_BUFFER_FULL                  10
2215 +#define RX_STATUS_NUM                          16
2216 +
2217 +
2218 +/*
2219 + * GMAC DMA Rx Description Word 1 Register
2220 + * GMAC0 offset 0x8064
2221 + * GMAC1 offset 0xC064
2222 + */
2223 +typedef union {
2224 +       unsigned int bits32;
2225 +       struct rxdesc_word1 {
2226 +               unsigned int    byte_count      : 16;   // bit 15: 0    Rx Frame Byte Count
2227 +               unsigned int    sw_id           : 16;   // bit 31:16    Software ID
2228 +       } bits;
2229 +} GMAC_RXDESC_1_T;
2230 +
2231 +/*
2232 + * GMAC DMA Rx Description Word 2 Register
2233 + * GMAC0 offset 0x8068
2234 + * GMAC1 offset 0xC068
2235 + */
2236 +typedef union {
2237 +       unsigned int    bits32;
2238 +       unsigned int    buf_adr;
2239 +} GMAC_RXDESC_2_T;
2240 +
2241 +#define RX_INSERT_NONE         0
2242 +#define RX_INSERT_1_BYTE       1
2243 +#define RX_INSERT_2_BYTE       2
2244 +#define RX_INSERT_3_BYTE       3
2245 +
2246 +#define RX_INSERT_BYTES                RX_INSERT_2_BYTE
2247 +/*
2248 + * GMAC DMA Rx Description Word 3 Register
2249 + * GMAC0 offset 0x806C
2250 + * GMAC1 offset 0xC06C
2251 + */
2252 +typedef union {
2253 +       unsigned int bits32;
2254 +       struct rxdesc_word3 {
2255 +               unsigned int    l3_offset       : 8;    // bit 7: 0     L3 data offset
2256 +               unsigned int    l4_offset       : 8;    // bit 15: 8    L4 data offset
2257 +               unsigned int    l7_offset       : 8;    // bit 23: 16   L7 data offset
2258 +               unsigned int    dup_ack         : 1;    // bit 24       Duplicated ACK detected
2259 +               unsigned int    abnormal        : 1;    // bit 25       abnormal case found
2260 +               unsigned int    option          : 1;    // bit 26       IPV4 option or IPV6 extension header
2261 +               unsigned int    out_of_seq      : 1;    // bit 27       Out of Sequence packet
2262 +               unsigned int    ctrl_flag       : 1;    // bit 28       Control Flag is present
2263 +               unsigned int    eofie           : 1;    // bit 29       End of frame interrupt enable
2264 +               unsigned int    sof_eof         : 2;    // bit 31:30    11: only one, 10: first, 01: last, 00: linking
2265 +       } bits;
2266 +} GMAC_RXDESC_3_T;
2267 +
2268 +/*
2269 + * GMAC Rx Descriptor
2270 + */
2271 +typedef struct {
2272 +       GMAC_RXDESC_0_T word0;
2273 +       GMAC_RXDESC_1_T word1;
2274 +       GMAC_RXDESC_2_T word2;
2275 +       GMAC_RXDESC_3_T word3;
2276 +} GMAC_RXDESC_T;
2277 +
2278 +/*
2279 + * GMAC Hash Engine Enable/Action Register 0 Offset Register
2280 + * GMAC0 offset 0x8070
2281 + * GMAC1 offset 0xC070
2282 + */
2283 +typedef union {
2284 +       unsigned int bits32;
2285 +       struct bit_8070 {
2286 +               unsigned int    mr0hel          : 6;    // bit 5:0      match rule 0 hash entry size
2287 +               unsigned int    mr0_action      : 5;    // bit 10:6     Matching Rule 0 action offset
2288 +               unsigned int    reserved0       : 4;    // bit 14:11
2289 +               unsigned int    mr0en           : 1;    // bit 15       Enable Matching Rule 0
2290 +               unsigned int    mr1hel          : 6;    // bit 21:16    match rule 1 hash entry size
2291 +               unsigned int    mr1_action      : 5;    // bit 26:22    Matching Rule 1 action offset
2292 +               unsigned int    timing          : 3;    // bit 29:27
2293 +               unsigned int    reserved1       : 1;    // bit 30
2294 +               unsigned int    mr1en           : 1;    // bit 31       Enable Matching Rule 1
2295 +       } bits;
2296 +} GMAC_HASH_ENABLE_REG0_T;
2297 +
2298 +/*
2299 + * GMAC Hash Engine Enable/Action Register 1 Offset Register
2300 + * GMAC0 offset 0x8074
2301 + * GMAC1 offset 0xC074
2302 + */
2303 +typedef union {
2304 +       unsigned int bits32;
2305 +       struct bit_8074 {
2306 +               unsigned int    mr2hel          : 6;    // bit 5:0      match rule 2 hash entry size
2307 +               unsigned int    mr2_action      : 5;    // bit 10:6     Matching Rule 2 action offset
2308 +               unsigned int    reserved2       : 4;    // bit 14:11
2309 +               unsigned int    mr2en           : 1;    // bit 15       Enable Matching Rule 2
2310 +               unsigned int    mr3hel          : 6;    // bit 21:16    match rule 3 hash entry size
2311 +               unsigned int    mr3_action      : 5;    // bit 26:22    Matching Rule 3 action offset
2312 +               unsigned int    reserved1       : 4;    // bit 30:27
2313 +               unsigned int    mr3en           : 1;    // bit 31       Enable Matching Rule 3
2314 +       } bits;
2315 +} GMAC_HASH_ENABLE_REG1_T;
2316 +
2317 +/*
2318 + * GMAC Matching Rule Control Register 0
2319 + * GMAC0 offset 0x8078
2320 + * GMAC1 offset 0xC078
2321 + */
2322 +typedef union {
2323 +       unsigned int bits32;
2324 +       struct bit_8078 {
2325 +               unsigned int    sprx            : 8;    // bit 7:0      Support Protocol Register 7:0
2326 +               unsigned int    reserved2       : 4;    // bit 11:8
2327 +               unsigned int    tos_traffic     : 1;    // bit 12       IPV4 TOS or IPV6 Traffice Class
2328 +               unsigned int    flow_lable      : 1;    // bit 13       IPV6 Flow label
2329 +               unsigned int    ip_hdr_len      : 1;    // bit 14       IPV4 Header length
2330 +               unsigned int    ip_version      : 1;    // bit 15       0: IPV4, 1: IPV6
2331 +               unsigned int    reserved1       : 3;    // bit 18:16
2332 +               unsigned int    pppoe           : 1;    // bit 19       PPPoE Session ID enable
2333 +               unsigned int    vlan            : 1;    // bit 20       VLAN ID enable
2334 +               unsigned int    ether_type      : 1;    // bit 21       Ethernet type enable
2335 +               unsigned int    sa              : 1;    // bit 22       MAC SA enable
2336 +               unsigned int    da              : 1;    // bit 23       MAC DA enable
2337 +               unsigned int    priority        : 3;    // bit 26:24    priority if multi-rules matched
2338 +               unsigned int    port            : 1;    // bit 27       PORT ID matching enable
2339 +               unsigned int    l7              : 1;    // bit 28       L7 matching enable
2340 +               unsigned int    l4              : 1;    // bit 29       L4 matching enable
2341 +               unsigned int    l3              : 1;    // bit 30       L3 matching enable
2342 +               unsigned int    l2              : 1;    // bit 31       L2 matching enable
2343 +       } bits;
2344 +} GMAC_MRxCR0_T;
2345 +
2346 +#define MR_L2_BIT              BIT(31)
2347 +#define MR_L3_BIT              BIT(30)
2348 +#define MR_L4_BIT              BIT(29)
2349 +#define MR_L7_BIT              BIT(28)
2350 +#define MR_PORT_BIT            BIT(27)
2351 +#define MR_PRIORITY_BIT                BIT(26)
2352 +#define MR_DA_BIT              BIT(23)
2353 +#define MR_SA_BIT              BIT(22)
2354 +#define MR_ETHER_TYPE_BIT      BIT(21)
2355 +#define MR_VLAN_BIT            BIT(20)
2356 +#define MR_PPPOE_BIT           BIT(19)
2357 +#define MR_IP_VER_BIT          BIT(15)
2358 +#define MR_IP_HDR_LEN_BIT      BIT(14)
2359 +#define MR_FLOW_LABLE_BIT      BIT(13)
2360 +#define MR_TOS_TRAFFIC_BIT     BIT(12)
2361 +#define MR_SPR_BIT(x)          BIT(x)
2362 +#define MR_SPR_BITS            0xff
2363 +
2364 +/*
2365 + * GMAC Matching Rule Control Register 1
2366 + * GMAC0 offset 0x807C
2367 + * GMAC1 offset 0xC07C
2368 + */
2369 +typedef union {
2370 +       unsigned int bits32;
2371 +       struct bit_807C {
2372 +               unsigned int    l4_byte0_15     : 16;   // bit 15: 0
2373 +               unsigned int    dip_netmask     : 7;    // bit 22:16    Dest IP net mask, number of mask bits
2374 +               unsigned int    dip             : 1;    // bit 23               Dest IP
2375 +               unsigned int    sip_netmask     : 7;    // bit 30:24    Srce IP net mask, number of mask bits
2376 +               unsigned int    sip             : 1;    // bit 31               Srce IP
2377 +       } bits;
2378 +} GMAC_MRxCR1_T;
2379 +
2380 +/*
2381 + * GMAC Matching Rule Control Register 2
2382 + * GMAC0 offset 0x8080
2383 + * GMAC1 offset 0xC080
2384 + */
2385 +typedef union {
2386 +       unsigned int bits32;
2387 +       struct bit_8080 {
2388 +               unsigned int    l7_byte0_23     : 24;   // bit 23:0
2389 +               unsigned int    l4_byte16_24    : 8;    // bit 31: 24
2390 +       } bits;
2391 +} GMAC_MRxCR2_T;
2392 +
2393 +/*
2394 + * GMAC Support registers
2395 + * GMAC0 offset 0x80A8
2396 + * GMAC1 offset 0xC0A8
2397 + */
2398 +typedef union {
2399 +       unsigned int bits32;
2400 +       struct bit_80A8 {
2401 +               unsigned int    protocol        : 8;    // bit 7:0              Supported protocol
2402 +               unsigned int    swap            : 3;    // bit 10:8             Swap
2403 +               unsigned int    reserved        : 21;   // bit 31:11
2404 +       } bits;
2405 +} GMAC_SPR_T;
2406 +
2407 +/*
2408 + * GMAC_AHB_WEIGHT registers
2409 + * GMAC0 offset 0x80C8
2410 + * GMAC1 offset 0xC0C8
2411 + */
2412 +typedef union {
2413 +       unsigned int bits32;
2414 +       struct bit_80C8 {
2415 +               unsigned int    hash_weight     : 5;    // 4:0
2416 +               unsigned int    rx_weight       : 5;    // 9:5
2417 +               unsigned int    tx_weight       : 5;    // 14:10
2418 +               unsigned int    pre_req         : 5;    // 19:15 Rx Data Pre Request FIFO Threshold
2419 +               unsigned int    tqDV_threshold  : 5;    // 24:20 DMA TqCtrl to Start tqDV FIFO Threshold
2420 +               unsigned int    reserved        : 7;    // 31:25
2421 +       } bits;
2422 +} GMAC_AHB_WEIGHT_T;
2423 +
2424 +/*
2425 + * the register structure of GMAC
2426 + */
2427 +
2428 +/*
2429 + * GMAC RX FLTR
2430 + * GMAC0 Offset 0xA00C
2431 + * GMAC1 Offset 0xE00C
2432 + */
2433 +typedef union {
2434 +       unsigned int bits32;
2435 +       struct bit1_000c {
2436 +               unsigned int unicast            :  1;   /* enable receive of unicast frames that are sent to STA address */
2437 +               unsigned int multicast          :  1;   /* enable receive of multicast frames that pass multicast filter */
2438 +               unsigned int broadcast          :  1;   /* enable receive of broadcast frames */
2439 +               unsigned int promiscuous        :  1;   /* enable receive of all frames */
2440 +               unsigned int error              :  1;   /* enable receive of all error frames */
2441 +               unsigned int                    : 27;
2442 +       } bits;
2443 +} GMAC_RX_FLTR_T;
2444 +
2445 +/*
2446 + * GMAC Configuration 0
2447 + * GMAC0 Offset 0xA018
2448 + * GMAC1 Offset 0xE018
2449 + */
2450 +typedef union {
2451 +       unsigned int bits32;
2452 +       struct bit1_0018 {
2453 +               unsigned int dis_tx             :  1;   /* 0: disable transmit */
2454 +               unsigned int dis_rx             :  1;   /* 1: disable receive */
2455 +               unsigned int loop_back          :  1;   /* 2: transmit data loopback enable */
2456 +               unsigned int flow_ctrl          :  1;   /* 3: flow control also trigged by Rx queues */
2457 +               unsigned int adj_ifg            :  4;   /* 4-7: adjust IFG from 96+/-56 */
2458 +               unsigned int max_len            :  3;   /* 8-10 maximum receive frame length allowed */
2459 +               unsigned int dis_bkoff          :  1;   /* 11: disable back-off function */
2460 +               unsigned int dis_col            :  1;   /* 12: disable 16 collisions abort function */
2461 +               unsigned int sim_test           :  1;   /* 13: speed up timers in simulation */
2462 +               unsigned int rx_fc_en           :  1;   /* 14: RX flow control enable */
2463 +               unsigned int tx_fc_en           :  1;   /* 15: TX flow control enable */
2464 +               unsigned int rgmii_en           :  1;   /* 16: RGMII in-band status enable */
2465 +               unsigned int ipv4_rx_chksum     :  1;   /* 17: IPv4 RX Checksum enable */
2466 +               unsigned int ipv6_rx_chksum     :  1;   /* 18: IPv6 RX Checksum enable */
2467 +               unsigned int rx_tag_remove      :  1;   /* 19: Remove Rx VLAN tag */
2468 +               unsigned int rgmm_edge          :  1;   // 20
2469 +               unsigned int rxc_inv            :  1;   // 21
2470 +               unsigned int ipv6_exthdr_order  :  1;   // 22
2471 +               unsigned int rx_err_detect      :  1;   // 23
2472 +               unsigned int port0_chk_hwq      :  1;   // 24
2473 +               unsigned int port1_chk_hwq      :  1;   // 25
2474 +               unsigned int port0_chk_toeq     :  1;   // 26
2475 +               unsigned int port1_chk_toeq     :  1;   // 27
2476 +               unsigned int port0_chk_classq   :  1;   // 28
2477 +               unsigned int port1_chk_classq   :  1;   // 29
2478 +               unsigned int reserved           :  2;   // 31
2479 +       } bits;
2480 +} GMAC_CONFIG0_T;
2481 +
2482 +/*
2483 + * GMAC Configuration 1
2484 + * GMAC0 Offset 0xA01C
2485 + * GMAC1 Offset 0xE01C
2486 + */
2487 +typedef union {
2488 +       unsigned int bits32;
2489 +       struct bit1_001c {
2490 +               unsigned int set_threshold      : 8;    /* flow control set threshold */
2491 +               unsigned int rel_threshold      : 8;    /* flow control release threshold */
2492 +               unsigned int reserved           : 16;
2493 +       } bits;
2494 +} GMAC_CONFIG1_T;
2495 +
2496 +#define GMAC_FLOWCTRL_SET_MAX          32
2497 +#define GMAC_FLOWCTRL_SET_MIN          0
2498 +#define GMAC_FLOWCTRL_RELEASE_MAX      32
2499 +#define GMAC_FLOWCTRL_RELEASE_MIN      0
2500 +
2501 +/*
2502 + * GMAC Configuration 2
2503 + * GMAC0 Offset 0xA020
2504 + * GMAC1 Offset 0xE020
2505 + */
2506 +typedef union {
2507 +       unsigned int bits32;
2508 +       struct bit1_0020 {
2509 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
2510 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
2511 +       } bits;
2512 +} GMAC_CONFIG2_T;
2513 +
2514 +/*
2515 + * GMAC Configuration 3
2516 + * GMAC0 Offset 0xA024
2517 + * GMAC1 Offset 0xE024
2518 + */
2519 +typedef union {
2520 +       unsigned int bits32;
2521 +       struct bit1_0024 {
2522 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
2523 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
2524 +       } bits;
2525 +} GMAC_CONFIG3_T;
2526 +
2527 +
2528 +/*
2529 + * GMAC STATUS
2530 + * GMAC0 Offset 0xA02C
2531 + * GMAC1 Offset 0xE02C
2532 + */
2533 +typedef union {
2534 +       unsigned int bits32;
2535 +       struct bit1_002c {
2536 +               unsigned int link               :  1;   /* link status */
2537 +               unsigned int speed              :  2;   /* link speed(00->2.5M 01->25M 10->125M) */
2538 +               unsigned int duplex             :  1;   /* duplex mode */
2539 +               unsigned int reserved           :  1;
2540 +               unsigned int mii_rmii           :  2;   /* PHY interface type */
2541 +               unsigned int                    : 25;
2542 +       } bits;
2543 +} GMAC_STATUS_T;
2544 +
2545 +#define GMAC_SPEED_10                  0
2546 +#define GMAC_SPEED_100                 1
2547 +#define GMAC_SPEED_1000                        2
2548 +
2549 +#define GMAC_PHY_MII                   0
2550 +#define GMAC_PHY_GMII                  1
2551 +#define GMAC_PHY_RGMII_100_10          2
2552 +#define GMAC_PHY_RGMII_1000            3
2553 +
2554 +/*
2555 + * Queue Header
2556 + *     (1) TOE Queue Header
2557 + *     (2) Non-TOE Queue Header
2558 + *     (3) Interrupt Queue Header
2559 + *
2560 + * memory Layout
2561 + *     TOE Queue Header
2562 + *      0x60003000 +---------------------------+ 0x0000
2563 + *                             |     TOE Queue 0 Header        |
2564 + *                             |         8 * 4 Bytes       |
2565 + *                             +---------------------------+ 0x0020
2566 + *                             |     TOE Queue 1 Header        |
2567 + *                             |         8 * 4 Bytes           |
2568 + *                             +---------------------------+ 0x0040
2569 + *                             |       ......                          |
2570 + *                             |                                               |
2571 + *                             +---------------------------+
2572 + *
2573 + *     Non TOE Queue Header
2574 + *      0x60002000 +---------------------------+ 0x0000
2575 + *                             |   Default Queue 0 Header  |
2576 + *                             |         2 * 4 Bytes           |
2577 + *                             +---------------------------+ 0x0008
2578 + *                             |   Default Queue 1 Header      |
2579 + *                             |         2 * 4 Bytes           |
2580 + *                             +---------------------------+ 0x0010
2581 + *                             |   Classification Queue 0      |
2582 + *                             |         2 * 4 Bytes           |
2583 + *                             +---------------------------+
2584 + *                             |   Classification Queue 1      |
2585 + *                             |         2 * 4 Bytes           |
2586 + *                             +---------------------------+ (n * 8 + 0x10)
2587 + *                             |               ...                             |
2588 + *                             |         2 * 4 Bytes           |
2589 + *                             +---------------------------+ (13 * 8 + 0x10)
2590 + *                             |   Classification Queue 13     |
2591 + *                             |         2 * 4 Bytes           |
2592 + *                             +---------------------------+ 0x80
2593 + *                             |      Interrupt Queue 0        |
2594 + *                             |         2 * 4 Bytes           |
2595 + *                             +---------------------------+
2596 + *                             |      Interrupt Queue 1        |
2597 + *                             |         2 * 4 Bytes           |
2598 + *                             +---------------------------+
2599 + *                             |      Interrupt Queue 2        |
2600 + *                             |         2 * 4 Bytes           |
2601 + *                             +---------------------------+
2602 + *                             |      Interrupt Queue 3        |
2603 + *                             |         2 * 4 Bytes           |
2604 + *                             +---------------------------+
2605 + *
2606 + */
2607 +#define TOE_QUEUE_HDR_ADDR(n)          (TOE_TOE_QUE_HDR_BASE + n * 32)
2608 +#define TOE_Q_HDR_AREA_END             (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
2609 +#define TOE_DEFAULT_Q_HDR_BASE(x)      (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x))
2610 +#define TOE_CLASS_Q_HDR_BASE           (TOE_NONTOE_QUE_HDR_BASE + 0x10)
2611 +#define TOE_INTR_Q_HDR_BASE            (TOE_NONTOE_QUE_HDR_BASE + 0x80)
2612 +#define INTERRUPT_QUEUE_HDR_ADDR(n)    (TOE_INTR_Q_HDR_BASE + n * 8)
2613 +#define NONTOE_Q_HDR_AREA_END          (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
2614 +/*
2615 + * TOE Queue Header Word 0
2616 + */
2617 +typedef union {
2618 +       unsigned int bits32;
2619 +       unsigned int base_size;
2620 +} TOE_QHDR0_T;
2621 +
2622 +#define TOE_QHDR0_BASE_MASK    (~0x0f)
2623 +
2624 +/*
2625 + * TOE Queue Header Word 1
2626 + */
2627 +typedef union {
2628 +       unsigned int bits32;
2629 +       struct bit_qhdr1 {
2630 +               unsigned int rptr       : 16;   // bit 15:0
2631 +               unsigned int wptr       : 16;   // bit 31:16
2632 +       } bits;
2633 +} TOE_QHDR1_T;
2634 +
2635 +/*
2636 + * TOE Queue Header Word 2
2637 + */
2638 +typedef union {
2639 +       unsigned int bits32;
2640 +       struct bit_qhdr2 {
2641 +               unsigned int TotalPktSize       : 17;   // bit 16: 0    Total packet size
2642 +               unsigned int reserved           : 7;    // bit 23:17
2643 +               unsigned int dack               : 1;    // bit 24       1: Duplicated ACK
2644 +               unsigned int abn                : 1;    // bit 25       1: Abnormal case Found
2645 +               unsigned int tcp_opt            : 1;    // bit 26       1: Have TCP option
2646 +               unsigned int ip_opt             : 1;    // bit 27       1: have IPV4 option or IPV6 Extension header
2647 +               unsigned int sat                : 1;    // bit 28       1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
2648 +               unsigned int osq                : 1;    // bit 29       1: out of sequence
2649 +               unsigned int ctl                : 1;    // bit 30       1: have control flag bits (except ack)
2650 +               unsigned int usd                : 1;    // bit 31       0: if no data assembled yet
2651 +       } bits;
2652 +} TOE_QHDR2_T;
2653 +
2654 +/*
2655 + * TOE Queue Header Word 3
2656 + */
2657 +typedef union {
2658 +       unsigned int bits32;
2659 +       unsigned int seq_num;
2660 +} TOE_QHDR3_T;
2661 +
2662 +/*
2663 + * TOE Queue Header Word 4
2664 + */
2665 +typedef union {
2666 +       unsigned int bits32;
2667 +       unsigned int ack_num;
2668 +} TOE_QHDR4_T;
2669 +
2670 +/*
2671 + * TOE Queue Header Word 5
2672 + */
2673 +typedef union {
2674 +       unsigned int bits32;
2675 +       struct bit_qhdr5 {
2676 +               unsigned int AckCnt     : 16;   // bit 15:0
2677 +               unsigned int SeqCnt     : 16;   // bit 31:16
2678 +       } bits;
2679 +} TOE_QHDR5_T;
2680 +
2681 +/*
2682 + * TOE Queue Header Word 6
2683 + */
2684 +typedef union {
2685 +       unsigned int bits32;
2686 +       struct bit_qhdr6 {
2687 +               unsigned int WinSize    : 16;   // bit 15:0
2688 +               unsigned int iq_num     : 2;    // bit 17:16
2689 +               unsigned int MaxPktSize : 14;   // bit 31:18
2690 +       } bits;
2691 +} TOE_QHDR6_T;
2692 +
2693 +/*
2694 + * TOE Queue Header Word 7
2695 + */
2696 +typedef union {
2697 +       unsigned int bits32;
2698 +       struct bit_qhdr7 {
2699 +               unsigned int AckThreshold       : 16;   // bit 15:0
2700 +               unsigned int SeqThreshold       : 16;   // bit 31:16
2701 +       } bits;
2702 +} TOE_QHDR7_T;
2703 +
2704 +/*
2705 + * TOE Queue Header
2706 + */
2707 +typedef struct {
2708 +       TOE_QHDR0_T             word0;
2709 +       TOE_QHDR1_T             word1;
2710 +       TOE_QHDR2_T             word2;
2711 +       TOE_QHDR3_T             word3;
2712 +       TOE_QHDR4_T             word4;
2713 +       TOE_QHDR5_T             word5;
2714 +       TOE_QHDR6_T             word6;
2715 +       TOE_QHDR7_T             word7;
2716 +} TOE_QHDR_T;
2717 +
2718 +/*
2719 + * NONTOE Queue Header Word 0
2720 + */
2721 +typedef union {
2722 +       unsigned int bits32;
2723 +       unsigned int base_size;
2724 +} NONTOE_QHDR0_T;
2725 +
2726 +#define NONTOE_QHDR0_BASE_MASK         (~0x0f)
2727 +
2728 +/*
2729 + * NONTOE Queue Header Word 1
2730 + */
2731 +typedef union {
2732 +       unsigned int bits32;
2733 +       struct bit_nonqhdr1 {
2734 +               unsigned int rptr       : 16;   // bit 15:0
2735 +               unsigned int wptr       : 16;   // bit 31:16
2736 +       } bits;
2737 +} NONTOE_QHDR1_T;
2738 +
2739 +/*
2740 + * Non-TOE Queue Header
2741 + */
2742 +typedef struct {
2743 +       NONTOE_QHDR0_T          word0;
2744 +       NONTOE_QHDR1_T          word1;
2745 +} NONTOE_QHDR_T;
2746 +
2747 +/*
2748 + * Interrupt Queue Header Word 0
2749 + */
2750 +typedef union {
2751 +       unsigned int bits32;
2752 +       struct bit_intrqhdr0 {
2753 +               unsigned int win_size   : 16;   // bit 15:0     Descriptor Ring Size
2754 +               unsigned int wptr       : 16;   // bit 31:16    Write Pointer where hw stopped
2755 +       } bits;
2756 +} INTR_QHDR0_T;
2757 +
2758 +/*
2759 + * Interrupt Queue Header Word 1
2760 + */
2761 +typedef union {
2762 +       unsigned int bits32;
2763 +       struct bit_intrqhdr1 {
2764 +               unsigned int TotalPktSize       : 17;   // bit 16: 0    Total packet size
2765 +               unsigned int tcp_qid            : 8;    // bit 24:17    TCP Queue ID
2766 +               unsigned int dack               : 1;    // bit 25       1: Duplicated ACK
2767 +               unsigned int abn                : 1;    // bit 26       1: Abnormal case Found
2768 +               unsigned int tcp_opt            : 1;    // bit 27       1: Have TCP option
2769 +               unsigned int ip_opt             : 1;    // bit 28       1: have IPV4 option or IPV6 Extension header
2770 +               unsigned int sat                : 1;    // bit 29       1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
2771 +               unsigned int osq                : 1;    // bit 30       1: out of sequence
2772 +               unsigned int ctl                : 1;    // bit 31       1: have control flag bits (except ack)
2773 +       } bits;
2774 +} INTR_QHDR1_T;
2775 +
2776 +/*
2777 + * Interrupt Queue Header Word 2
2778 + */
2779 +typedef union {
2780 +       unsigned int bits32;
2781 +       unsigned int seq_num;
2782 +} INTR_QHDR2_T;
2783 +
2784 +/*
2785 + * Interrupt Queue Header Word 3
2786 + */
2787 +typedef union {
2788 +       unsigned int bits32;
2789 +       unsigned int ack_num;
2790 +} INTR_QHDR3_T;
2791 +
2792 +/*
2793 + * Interrupt Queue Header Word 4
2794 + */
2795 +typedef union {
2796 +       unsigned int bits32;
2797 +       struct bit_intrqhdr4 {
2798 +               unsigned int AckCnt             : 16;   // bit 15:0     Ack# change since last ack# intr.
2799 +               unsigned int SeqCnt             : 16;   // bit 31:16    Seq# change since last seq# intr.
2800 +       } bits;
2801 +} INTR_QHDR4_T;
2802 +
2803 +/*
2804 + * Interrupt Queue Header
2805 + */
2806 +typedef struct {
2807 +       INTR_QHDR0_T            word0;
2808 +       INTR_QHDR1_T            word1;
2809 +       INTR_QHDR2_T            word2;
2810 +       INTR_QHDR3_T            word3;
2811 +       INTR_QHDR4_T            word4;
2812 +       unsigned int            word5;
2813 +       unsigned int            word6;
2814 +       unsigned int            word7;
2815 +} INTR_QHDR_T;
2816 +
2817 +/*
2818 + * GMAC private data
2819 + */
2820 +typedef struct {
2821 +       unsigned int            rwptr_reg;
2822 +       unsigned int            desc_base;
2823 +       unsigned int            desc_base_dma;
2824 +       unsigned short          finished_idx;
2825 +       struct sk_buff          *tx_skb[TOE_GMAC_SWTXQ_DESC_NUM];
2826 +} GMAC_SWTXQ_T;
2827 +
2828 +struct gmac_private {
2829 +       struct phy_device       *phydev;
2830 +       unsigned int            port_id;
2831 +       unsigned int            dma_base_addr;
2832 +       unsigned int            swtxq_desc_base;
2833 +       GMAC_SWTXQ_T            swtxq[TOE_SW_TXQ_NUM];
2834 +       NONTOE_QHDR_T           *default_qhdr;
2835 +       unsigned int            default_desc_base;
2836 +       dma_addr_t              default_desc_base_dma;
2837 +       dma_addr_t              swtxq_desc_base_dma;
2838 +       unsigned int            flow_control_enable;
2839 +       unsigned int            intr0_enabled;
2840 +       unsigned int            intr1_enabled;
2841 +       unsigned int            intr2_enabled;
2842 +       unsigned int            intr3_enabled;
2843 +       unsigned int            intr4_enabled;
2844 +       unsigned int            intr0_selected;
2845 +       unsigned int            intr1_selected;
2846 +       unsigned int            intr2_selected;
2847 +       unsigned int            intr3_selected;
2848 +       unsigned int            intr4_selected;
2849 +};
2850 +
2851 +struct toe_private {
2852 +       void __iomem            *global_base;
2853 +       struct net_device       *net_dev[2];
2854 +       struct device           *dev;
2855 +       struct work_struct      freq_work;
2856 +       spinlock_t              freeq_lock;
2857 +       unsigned int            swfq_desc_base;
2858 +       unsigned int            hwfq_desc_base;
2859 +       unsigned int            hwfq_buf_base;
2860 +       dma_addr_t              sw_freeq_desc_base_dma;
2861 +       dma_addr_t              hw_freeq_desc_base_dma;
2862 +       dma_addr_t              hwfq_buf_base_dma;
2863 +       dma_addr_t              hwfq_buf_end_dma;
2864 +};
2865 +
2866 +#define GMAC_PORT0     0
2867 +#define GMAC_PORT1     1
2868 +
2869 +#endif /* _GMAC_SL351x_H */
2870 --- /dev/null
2871 +++ b/drivers/net/gemini_negmac/Makefile
2872 @@ -0,0 +1,3 @@
2873 +obj-$(CONFIG_GEMINI_NET_ENGINE_GMAC)+= gemini_negmac.o
2874 +
2875 +gemini_negmac-objs := gm_gmac.o
2876 --- a/drivers/net/Kconfig
2877 +++ b/drivers/net/Kconfig
2878 @@ -103,6 +103,13 @@ config NET_FC
2879           adaptor below. You also should have said Y to "SCSI support" and
2880           "SCSI generic support".
2881
2882 +config GEMINI_NET_ENGINE_GMAC
2883 +       tristate "Gemini Gigabit Ethernet support"
2884 +       depends on ARCH_GEMINI
2885 +       select PHYLIB
2886 +       help
2887 +         This driver supports Gemini TOE and NAT dual Gigabit Ethernet.
2888 +
2889  config MII
2890         tristate "Generic Media Independent Interface device support"
2891         help
2892 --- a/drivers/net/Makefile
2893 +++ b/drivers/net/Makefile
2894 @@ -33,6 +33,7 @@ obj-$(CONFIG_ETRAX_ETHERNET) += cris/
2895  obj-$(CONFIG_NET_DSA) += dsa/
2896  obj-$(CONFIG_ETHERNET) += ethernet/
2897  obj-$(CONFIG_FDDI) += fddi/
2898 +obj-$(CONFIG_GEMINI_NET_ENGINE_GMAC) += gemini_negmac/
2899  obj-$(CONFIG_HIPPI) += hippi/
2900  obj-$(CONFIG_HAMRADIO) += hamradio/
2901  obj-$(CONFIG_IRDA) += irda/