target/linux/etrax-2.6/image/e100boot/src/sbl/reg_des.h

   1 struct reg_des {
   2   char *name;
   3   unsigned int addr;
   4 } reg_des[] = {
   5   { "R_WAITSTATES", 0xb0000000 },
   6   { "R_BUS_CONFIG", 0xb0000004 },
   7   { "R_BUS_STATUS", 0xb0000004 },
   8   { "R_DRAM_TIMING", 0xb0000008 },
   9   { "R_SDRAM_TIMING", 0xb0000008 },
  10   { "R_DRAM_CONFIG", 0xb000000c },
  11   { "R_SDRAM_CONFIG", 0xb000000c },
  12   { "R_EXT_DMA_0_CMD", 0xb0000010 },
  13   { "R_EXT_DMA_0_STAT", 0xb0000010 },
  14   { "R_EXT_DMA_0_ADDR", 0xb0000014 },
  15   { "R_EXT_DMA_1_CMD", 0xb0000018 },
  16   { "R_EXT_DMA_1_STAT", 0xb0000018 },
  17   { "R_EXT_DMA_1_ADDR", 0xb000001c },
  18   { "R_TIMER_CTRL", 0xb0000020 },
  19   { "R_TIMER_DATA", 0xb0000020 },
  20   { "R_WATCHDOG", 0xb0000024 },
  21   { "R_SHARED_RAM_CONFIG", 0xb0000040 },
  22   { "R_SHARED_RAM_ADDR", 0xb0000044 },
  23   { "R_GEN_CONFIG", 0xb000002c },
  24   { "R_PORT_G_DATA", 0xb0000028 },
  25   { "R_PORT_PA_SET", 0xb0000030 },
  26   { "R_PORT_PA_READ", 0xb0000030 },
  27   { "R_PORT_PB_SET", 0xb0000038 },
  28   { "R_PORT_PB_READ", 0xb0000038 },
  29   { "R_SERIAL0_CTRL", 0xb0000060 },
  30   { "R_SERIAL0_READ", 0xb0000060 },
  31   { "R_SERIAL0_XOFF", 0xb0000064 },
  32   { "R_SERIAL1_CTRL", 0xb0000068 },
  33   { "R_SERIAL1_READ", 0xb0000068 },
  34   { "R_SERIAL1_XOFF", 0xb000006c },
  35   { "R_SERIAL2_CTRL", 0xb0000070 },
  36   { "R_SERIAL2_READ", 0xb0000070 },
  37   { "R_SERIAL2_XOFF", 0xb0000074 },
  38   { "R_SERIAL3_CTRL", 0xb0000078 },
  39   { "R_SERIAL3_READ", 0xb0000078 },
  40   { "R_SERIAL3_XOFF", 0xb000007c },
  41   { "R_NETWORK_SA_0", 0xb0000080 },
  42   { "R_NETWORK_SA_1", 0xb0000084 },
  43   { "R_NETWORK_SA_2", 0xb0000088 },
  44   { "R_NETWORK_GA_0", 0xb000008c },
  45   { "R_NETWORK_GA_1", 0xb0000090 },
  46   { "R_NETWORK_REC_CONFIG", 0xb0000094 },
  47   { "R_NETWORK_GEN_CONFIG", 0xb0000098 },
  48   { "R_NETWORK_TR_CTRL", 0xb000009c },
  49   { "R_NETWORK_MGM_CTRL", 0xb00000a0 },
  50   { "R_NETWORK_STAT", 0xb00000a0 },
  51   { "R_REC_COUNTERS", 0xb00000a4 },
  52   { "R_TR_COUNTERS", 0xb00000a8 },
  53   { "R_PHY_COUNTERS", 0xb00000ac },
  54   { "R_PAR0_CTRL_DATA", 0xb0000040 },
  55   { "R_PAR0_STATUS_DATA", 0xb0000040 },
  56   { "R_PAR0_CONFIG", 0xb0000044 },
  57   { "R_PAR0_DELAY", 0xb0000048 },
  58   { "R_PAR1_CTRL_DATA", 0xb0000050 },
  59   { "R_PAR1_STATUS_DATA", 0xb0000050 },
  60   { "R_PAR1_CONFIG", 0xb0000054 },
  61   { "R_PAR1_DELAY", 0xb0000058 },
  62   { "R_ATA_CTRL_DATA", 0xb0000040 },
  63   { "R_ATA_STATUS_DATA", 0xb0000040 },
  64   { "R_ATA_CONFIG", 0xb0000044 },
  65   { "R_ATA_TRANSFER_CNT", 0xb0000048 },
  66   { "R_SCSI0_CTRL", 0xb0000044 },
  67   { "R_SCSI0_CMD_DATA", 0xb0000040 },
  68   { "R_SCSI0_STATUS", 0xb0000048 },
  69   { "R_SCSI1_CTRL", 0xb0000054 },
  70   { "R_SCSI1_CMD_DATA", 0xb0000050 },
  71   { "R_SCSI1_STATUS", 0xb0000058 },
  72   { "R_IRQ_MASK0_RD", 0xb00000c0 },
  73   { "R_IRQ_MASK0_CLR", 0xb00000c0 },
  74   { "R_IRQ_READ0", 0xb00000c4 },
  75   { "R_IRQ_MASK0_SET", 0xb00000c4 },
  76   { "R_IRQ_MASK1_RD", 0xb00000c8 },
  77   { "R_IRQ_MASK1_CLR", 0xb00000c8 },
  78   { "R_IRQ_READ1", 0xb00000cc },
  79   { "R_IRQ_MASK1_SET", 0xb00000cc },
  80   { "R_IRQ_MASK2_RD", 0xb00000d0 },
  81   { "R_IRQ_MASK2_CLR", 0xb00000d0 },
  82   { "R_IRQ_READ2", 0xb00000d4 },
  83   { "R_IRQ_MASK2_SET", 0xb00000d4 },
  84   { "R_VECT_MASK_RD", 0xb00000d8 },
  85   { "R_VECT_MASK_CLR", 0xb00000d8 },
  86   { "R_VECT_READ", 0xb00000dc },
  87   { "R_VECT_MASK_SET", 0xb00000dc },
  88   { "R_SET_EOP", 0xb000003c },
  89   { "R_DMA_CH0_HWSW", 0xb0000100 },
  90   { "R_DMA_CH0_DESCR", 0xb000010c },
  91   { "R_DMA_CH0_NEXT", 0xb0000104 },
  92   { "R_DMA_CH0_BUF", 0xb0000108 },
  93   { "R_DMA_CH0_FIRST", 0xb00001a0 },
  94   { "R_DMA_CH1_HWSW", 0xb0000110 },
  95   { "R_DMA_CH1_DESCR", 0xb000011c },
  96   { "R_DMA_CH1_NEXT", 0xb0000114 },
  97   { "R_DMA_CH1_BUF", 0xb0000118 },
  98   { "R_DMA_CH1_FIRST", 0xb00001a4 },
  99   { "R_DMA_CH2_HWSW", 0xb0000120 },
 100   { "R_DMA_CH2_DESCR", 0xb000012c },
 101   { "R_DMA_CH2_NEXT", 0xb0000124 },
 102   { "R_DMA_CH2_BUF", 0xb0000128 },
 103   { "R_DMA_CH2_FIRST", 0xb00001a8 },
 104   { "R_DMA_CH3_HWSW", 0xb0000130 },
 105   { "R_DMA_CH3_DESCR", 0xb000013c },
 106   { "R_DMA_CH3_NEXT", 0xb0000134 },
 107   { "R_DMA_CH3_BUF", 0xb0000138 },
 108   { "R_DMA_CH3_FIRST", 0xb00001ac },
 109   { "R_DMA_CH4_HWSW", 0xb0000140 },
 110   { "R_DMA_CH4_DESCR", 0xb000014c },
 111   { "R_DMA_CH4_NEXT", 0xb0000144 },
 112   { "R_DMA_CH4_BUF", 0xb0000148 },
 113   { "R_DMA_CH4_FIRST", 0xb00001b0 },
 114   { "R_DMA_CH5_HWSW", 0xb0000150 },
 115   { "R_DMA_CH5_DESCR", 0xb000015c },
 116   { "R_DMA_CH5_NEXT", 0xb0000154 },
 117   { "R_DMA_CH5_BUF", 0xb0000158 },
 118   { "R_DMA_CH5_FIRST", 0xb00001b4 },
 119   { "R_DMA_CH6_HWSW", 0xb0000160 },
 120   { "R_DMA_CH6_DESCR", 0xb000016c },
 121   { "R_DMA_CH6_NEXT", 0xb0000164 },
 122   { "R_DMA_CH6_BUF", 0xb0000168 },
 123   { "R_DMA_CH6_FIRST", 0xb00001b8 },
 124   { "R_DMA_CH7_HWSW", 0xb0000170 },
 125   { "R_DMA_CH7_DESCR", 0xb000017c },
 126   { "R_DMA_CH7_NEXT", 0xb0000174 },
 127   { "R_DMA_CH7_BUF", 0xb0000178 },
 128   { "R_DMA_CH7_FIRST", 0xb00001bc },
 129   { "R_DMA_CH8_HWSW", 0xb0000180 },
 130   { "R_DMA_CH8_DESCR", 0xb000018c },
 131   { "R_DMA_CH8_NEXT", 0xb0000184 },
 132   { "R_DMA_CH8_BUF", 0xb0000188 },
 133   { "R_DMA_CH8_FIRST", 0xb00001c0 },
 134   { "R_DMA_CH9_HWSW", 0xb0000190 },
 135   { "R_DMA_CH9_DESCR", 0xb000019c },
 136   { "R_DMA_CH9_NEXT", 0xb0000194 },
 137   { "R_DMA_CH9_BUF", 0xb0000198 },
 138   { "R_DMA_CH9_FIRST", 0xb00001c4 },
 139   { "R_TEST_MODE", 0xb00000fc },
 140   { NULL, 0 }
 141 };