2 * arch/mips/danube/setup.c
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
18 * Copyright (C) 2004 peng.liu@infineon.com
20 * Rewrite of Infineon Danube code, thanks to infineon for the support,
21 * software and hardware
23 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
27 #include <linux/init.h>
30 #include <asm/traps.h>
33 #include <asm/danube/danube.h>
34 #include <asm/danube/danube_irq.h>
35 #include <asm/danube/danube_pmu.h>
37 static unsigned int r4k_offset; /* Amount to increment compare reg each time */
38 static unsigned int r4k_cur; /* What counter should be at next timer irq */
40 extern void danube_reboot_setup (void);
41 void prom_printf (const char * fmt, ...);
44 __init bus_error_init (void)
50 danube_get_ddr_hz (void)
52 switch (readl(DANUBE_CGU_SYS) & 0x3)
63 EXPORT_SYMBOL(danube_get_ddr_hz);
66 danube_get_cpu_hz (void)
68 unsigned int ddr_clock = danube_get_ddr_hz();
69 switch (readl(DANUBE_CGU_SYS) & 0xc)
76 return ddr_clock << 1;
78 EXPORT_SYMBOL(danube_get_cpu_hz);
81 danube_get_fpi_hz (void)
83 unsigned int ddr_clock = danube_get_ddr_hz();
84 if (readl(DANUBE_CGU_SYS) & 0x40)
86 return ddr_clock >> 1;
90 EXPORT_SYMBOL(danube_get_fpi_hz);
93 danube_get_cpu_ver (void)
95 return readl(DANUBE_MCD_CHIPID) & 0xFFFFF000;
97 EXPORT_SYMBOL(danube_get_cpu_ver);
100 danube_time_init (void)
102 mips_hpt_frequency = danube_get_cpu_hz() / 2;
103 r4k_offset = mips_hpt_frequency / HZ;
104 printk("mips_hpt_frequency:%d\n", mips_hpt_frequency);
105 printk("r4k_offset: %08x(%d)\n", r4k_offset, r4k_offset);
109 danube_be_handler(struct pt_regs *regs, int is_fixup)
112 printk(KERN_ERR "TODO: BUS error\n");
114 return MIPS_BE_FATAL;
117 /* ISR GPTU Timer 6 for high resolution timer */
119 danube_timer6_interrupt(int irq, void *dev_id)
121 timer_interrupt(DANUBE_TIMER6_INT, NULL);
126 static struct irqaction hrt_irqaction = {
127 .handler = danube_timer6_interrupt,
128 .flags = IRQF_DISABLED,
133 plat_timer_setup (struct irqaction *irq)
137 setup_irq(MIPS_CPU_TIMER_IRQ, irq);
139 r4k_cur = (read_c0_count() + r4k_offset);
140 write_c0_compare(r4k_cur);
142 danube_pmu_enable(DANUBE_PMU_PWDCR_GPT | DANUBE_PMU_PWDCR_FPI);
144 writel(0x100, DANUBE_GPTU_GPT_CLC);
146 writel(0xffff, DANUBE_GPTU_GPT_CAPREL);
147 writel(0x80C0, DANUBE_GPTU_GPT_T6CON);
149 retval = setup_irq(DANUBE_TIMER6_INT, &hrt_irqaction);
153 prom_printf("reqeust_irq failed %d. HIGH_RES_TIMER is diabled\n", DANUBE_TIMER6_INT);
158 plat_mem_setup (void)
161 prom_printf("This %s has a cpu rev of 0x%X\n", BOARD_SYSTEM_TYPE, danube_get_cpu_ver());
165 status = read_c0_status();
166 status &= (~(1<<25));
167 write_c0_status(status);
169 danube_reboot_setup();
170 board_time_init = danube_time_init;
171 board_be_handler = &danube_be_handler;
173 ioport_resource.start = IOPORT_RESOURCE_START;
174 ioport_resource.end = IOPORT_RESOURCE_END;
175 iomem_resource.start = IOMEM_RESOURCE_START;
176 iomem_resource.end = IOMEM_RESOURCE_END;