target/linux/cns3xxx/files/drivers/usb/dwc/otg_cil_intr.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
   3  * $Revision: #10 $
   4  * $Date: 2008/07/16 $
   5  * $Change: 1065567 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33
  34 /** @file
  35  *
  36  * The Core Interface Layer provides basic services for accessing and
  37  * managing the DWC_otg hardware. These services are used by both the
  38  * Host Controller Driver and the Peripheral Controller Driver.
  39  *
  40  * This file contains the Common Interrupt handlers.
  41  */
  42 #include "otg_plat.h"
  43 #include "otg_regs.h"
  44 #include "otg_cil.h"
  45 #include "otg_pcd.h"
  46
  47 #ifdef DEBUG
  48 inline const char *op_state_str(dwc_otg_core_if_t *core_if)
  49 {
  50         return (core_if->op_state==A_HOST?"a_host":
  51                 (core_if->op_state==A_SUSPEND?"a_suspend":
  52                  (core_if->op_state==A_PERIPHERAL?"a_peripheral":
  53                   (core_if->op_state==B_PERIPHERAL?"b_peripheral":
  54                    (core_if->op_state==B_HOST?"b_host":
  55                     "unknown")))));
  56 }
  57 #endif
  58
  59 /** This function will log a debug message
  60  *
  61  * @param core_if Programming view of DWC_otg controller.
  62  */
  63 int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *core_if)
  64 {
  65         gintsts_data_t gintsts;
  66         DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
  67                  dwc_otg_mode(core_if) ? "Host" : "Device");
  68
  69         /* Clear interrupt */
  70         gintsts.d32 = 0;
  71         gintsts.b.modemismatch = 1;
  72         dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
  73         return 1;
  74 }
  75
  76 /** Start the HCD.  Helper function for using the HCD callbacks.
  77  *
  78  * @param core_if Programming view of DWC_otg controller.
  79  */
  80 static inline void hcd_start(dwc_otg_core_if_t *core_if)
  81 {
  82         if (core_if->hcd_cb && core_if->hcd_cb->start) {
  83                 core_if->hcd_cb->start(core_if->hcd_cb->p);
  84         }
  85 }
  86 /** Stop the HCD.  Helper function for using the HCD callbacks.
  87  *
  88  * @param core_if Programming view of DWC_otg controller.
  89  */
  90 static inline void hcd_stop(dwc_otg_core_if_t *core_if)
  91 {
  92         if (core_if->hcd_cb && core_if->hcd_cb->stop) {
  93                 core_if->hcd_cb->stop(core_if->hcd_cb->p);
  94         }
  95 }
  96 /** Disconnect the HCD.  Helper function for using the HCD callbacks.
  97  *
  98  * @param core_if Programming view of DWC_otg controller.
  99  */
 100 static inline void hcd_disconnect(dwc_otg_core_if_t *core_if)
 101 {
 102         if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
 103                 core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
 104         }
 105 }
 106 /** Inform the HCD the a New Session has begun.  Helper function for
 107  * using the HCD callbacks.
 108  *
 109  * @param core_if Programming view of DWC_otg controller.
 110  */
 111 static inline void hcd_session_start(dwc_otg_core_if_t *core_if)
 112 {
 113         if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
 114                 core_if->hcd_cb->session_start(core_if->hcd_cb->p);
 115         }
 116 }
 117
 118 /** Start the PCD.  Helper function for using the PCD callbacks.
 119  *
 120  * @param core_if Programming view of DWC_otg controller.
 121  */
 122 static inline void pcd_start(dwc_otg_core_if_t *core_if)
 123 {
 124         if (core_if->pcd_cb && core_if->pcd_cb->start) {
 125                 core_if->pcd_cb->start(core_if->pcd_cb->p);
 126         }
 127 }
 128 /** Stop the PCD.  Helper function for using the PCD callbacks.
 129  *
 130  * @param core_if Programming view of DWC_otg controller.
 131  */
 132 static inline void pcd_stop(dwc_otg_core_if_t *core_if)
 133 {
 134         if (core_if->pcd_cb && core_if->pcd_cb->stop) {
 135                 core_if->pcd_cb->stop(core_if->pcd_cb->p);
 136         }
 137 }
 138 /** Suspend the PCD.  Helper function for using the PCD callbacks.
 139  *
 140  * @param core_if Programming view of DWC_otg controller.
 141  */
 142 static inline void pcd_suspend(dwc_otg_core_if_t *core_if)
 143 {
 144         if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
 145                 core_if->pcd_cb->suspend(core_if->pcd_cb->p);
 146         }
 147 }
 148 /** Resume the PCD.  Helper function for using the PCD callbacks.
 149  *
 150  * @param core_if Programming view of DWC_otg controller.
 151  */
 152 static inline void pcd_resume(dwc_otg_core_if_t *core_if)
 153 {
 154         if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
 155                 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
 156         }
 157 }
 158
 159 /**
 160  * This function handles the OTG Interrupts. It reads the OTG
 161  * Interrupt Register (GOTGINT) to determine what interrupt has
 162  * occurred.
 163  *
 164  * @param core_if Programming view of DWC_otg controller.
 165  */
 166 int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *core_if)
 167 {
 168         dwc_otg_core_global_regs_t *global_regs =
 169                 core_if->core_global_regs;
 170         gotgint_data_t gotgint;
 171         gotgctl_data_t gotgctl;
 172         gintmsk_data_t gintmsk;
 173         gotgint.d32 = dwc_read_reg32(&global_regs->gotgint);
 174         gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
 175         DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
 176                     op_state_str(core_if));
 177         //DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32);
 178
 179         if (gotgint.b.sesenddet) {
 180                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
 181                             "Session End Detected++ (%s)\n",
 182                             op_state_str(core_if));
 183                 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
 184
 185                 if (core_if->op_state == B_HOST) {
 186
 187                         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)core_if->pcd_cb->p;
 188                         if(unlikely(!pcd)) {
 189                                 DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
 190                                 BUG();
 191                         }
 192                         SPIN_LOCK(&pcd->lock);
 193
 194                         pcd_start(core_if);
 195
 196                         SPIN_UNLOCK(&pcd->lock);
 197                         core_if->op_state = B_PERIPHERAL;
 198                 } else {
 199                         dwc_otg_pcd_t *pcd;
 200
 201                         /* If not B_HOST and Device HNP still set. HNP
 202                          * Did not succeed!*/
 203                         if (gotgctl.b.devhnpen) {
 204                                 DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
 205                                 DWC_ERROR("Device Not Connected/Responding!\n");
 206                         }
 207
 208                         /* If Session End Detected the B-Cable has
 209                          * been disconnected. */
 210                         /* Reset PCD and Gadget driver to a
 211                          * clean state. */
 212
 213                         pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
 214                         if(unlikely(!pcd)) {
 215                                 DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
 216                                 BUG();
 217                         }
 218                         SPIN_LOCK(&pcd->lock);
 219
 220                         pcd_stop(core_if);
 221
 222                         SPIN_UNLOCK(&pcd->lock);
 223                 }
 224                 gotgctl.d32 = 0;
 225                 gotgctl.b.devhnpen = 1;
 226                 dwc_modify_reg32(&global_regs->gotgctl,
 227                                   gotgctl.d32, 0);
 228         }
 229         if (gotgint.b.sesreqsucstschng) {
 230                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
 231                             "Session Reqeust Success Status Change++\n");
 232                 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
 233                 if (gotgctl.b.sesreqscs) {
 234                         if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
 235                             (core_if->core_params->i2c_enable)) {
 236                                 core_if->srp_success = 1;
 237                         }
 238                         else {
 239                                 dwc_otg_pcd_t *pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
 240                                 if(unlikely(!pcd)) {
 241                                         DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
 242                                         BUG();
 243                                 }
 244                                 SPIN_LOCK(&pcd->lock);
 245
 246                                 pcd_resume(core_if);
 247
 248                                 SPIN_UNLOCK(&pcd->lock);
 249                                 /* Clear Session Request */
 250                                 gotgctl.d32 = 0;
 251                                 gotgctl.b.sesreq = 1;
 252                                 dwc_modify_reg32(&global_regs->gotgctl,
 253                                                   gotgctl.d32, 0);
 254                         }
 255                 }
 256         }
 257         if (gotgint.b.hstnegsucstschng) {
 258                 /* Print statements during the HNP interrupt handling
 259                  * can cause it to fail.*/
 260                 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
 261                 if (gotgctl.b.hstnegscs) {
 262                         if (dwc_otg_is_host_mode(core_if)) {
 263                                 dwc_otg_pcd_t *pcd;
 264
 265                                 core_if->op_state = B_HOST;
 266                                 /*
 267                                  * Need to disable SOF interrupt immediately.
 268                                  * When switching from device to host, the PCD
 269                                  * interrupt handler won't handle the
 270                                  * interrupt if host mode is already set. The
 271                                  * HCD interrupt handler won't get called if
 272                                  * the HCD state is HALT. This means that the
 273                                  * interrupt does not get handled and Linux
 274                                  * complains loudly.
 275                                  */
 276                                 gintmsk.d32 = 0;
 277                                 gintmsk.b.sofintr = 1;
 278                                 dwc_modify_reg32(&global_regs->gintmsk,
 279                                                  gintmsk.d32, 0);
 280
 281                                 pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
 282                                 if(unlikely(!pcd)) {
 283                                         DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
 284                                         BUG();
 285                                 }
 286                                 SPIN_LOCK(&pcd->lock);
 287
 288                                 pcd_stop(core_if);
 289
 290                                 SPIN_UNLOCK(&pcd->lock);
 291                                 /*
 292                                  * Initialize the Core for Host mode.
 293                                  */
 294                                 hcd_start(core_if);
 295                                 core_if->op_state = B_HOST;
 296                         }
 297                 } else {
 298                         gotgctl.d32 = 0;
 299                         gotgctl.b.hnpreq = 1;
 300                         gotgctl.b.devhnpen = 1;
 301                         dwc_modify_reg32(&global_regs->gotgctl,
 302                                           gotgctl.d32, 0);
 303                         DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
 304                         DWC_ERROR("Device Not Connected/Responding\n");
 305                 }
 306         }
 307         if (gotgint.b.hstnegdet) {
 308                 /* The disconnect interrupt is set at the same time as
 309                  * Host Negotiation Detected.  During the mode
 310                  * switch all interrupts are cleared so the disconnect
 311                  * interrupt handler will not get executed.
 312                  */
 313                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
 314                             "Host Negotiation Detected++ (%s)\n",
 315                             (dwc_otg_is_host_mode(core_if)?"Host":"Device"));
 316                 if (dwc_otg_is_device_mode(core_if)){
 317                         dwc_otg_pcd_t *pcd;
 318
 319                         DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n", core_if->op_state);
 320                         hcd_disconnect(core_if);
 321
 322                         pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
 323                         if(unlikely(!pcd)) {
 324                                 DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
 325                                 BUG();
 326                         }
 327                         SPIN_LOCK(&pcd->lock);
 328
 329                         pcd_start(core_if);
 330
 331                         SPIN_UNLOCK(&pcd->lock);
 332                         core_if->op_state = A_PERIPHERAL;
 333                 } else {
 334                         dwc_otg_pcd_t *pcd;
 335
 336                         /*
 337                          * Need to disable SOF interrupt immediately. When
 338                          * switching from device to host, the PCD interrupt
 339                          * handler won't handle the interrupt if host mode is
 340                          * already set. The HCD interrupt handler won't get
 341                          * called if the HCD state is HALT. This means that
 342                          * the interrupt does not get handled and Linux
 343                          * complains loudly.
 344                          */
 345                         gintmsk.d32 = 0;
 346                         gintmsk.b.sofintr = 1;
 347                         dwc_modify_reg32(&global_regs->gintmsk,
 348                                          gintmsk.d32, 0);
 349
 350                         pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
 351                         if(unlikely(!pcd)) {
 352                                 DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
 353                                 BUG();
 354                         }
 355                         SPIN_LOCK(&pcd->lock);
 356
 357                         pcd_stop(core_if);
 358
 359                         SPIN_UNLOCK(&pcd->lock);
 360                         hcd_start(core_if);
 361                         core_if->op_state = A_HOST;
 362                 }
 363         }
 364         if (gotgint.b.adevtoutchng) {
 365                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
 366                             "A-Device Timeout Change++\n");
 367         }
 368         if (gotgint.b.debdone) {
 369                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
 370                             "Debounce Done++\n");
 371         }
 372
 373         /* Clear GOTGINT */
 374         dwc_write_reg32 (&core_if->core_global_regs->gotgint, gotgint.d32);
 375
 376         return 1;
 377 }
 378
 379
 380 void w_conn_id_status_change(struct work_struct *p)
 381 {
 382         dwc_otg_core_if_t *core_if = container_of(p, dwc_otg_core_if_t, w_conn_id);
 383
 384         uint32_t count = 0;
 385         gotgctl_data_t gotgctl = { .d32 = 0 };
 386
 387         gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
 388         DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
 389         DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
 390
 391         /* B-Device connector (Device Mode) */
 392         if (gotgctl.b.conidsts) {
 393                 dwc_otg_pcd_t *pcd;
 394
 395                 /* Wait for switch to device mode. */
 396                 while (!dwc_otg_is_device_mode(core_if)){
 397                         DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n",
 398                                   (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral"));
 399                         MDELAY(100);
 400                         if (++count > 10000) *(uint32_t*)NULL=0;
 401                 }
 402                 core_if->op_state = B_PERIPHERAL;
 403                 dwc_otg_core_init(core_if);
 404                 dwc_otg_enable_global_interrupts(core_if);
 405
 406                 pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
 407                 if(unlikely(!pcd)) {
 408                         DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
 409                         BUG();
 410                 }
 411                 SPIN_LOCK(&pcd->lock);
 412
 413                 pcd_start(core_if);
 414
 415                 SPIN_UNLOCK(&pcd->lock);
 416         } else {
 417                 /* A-Device connector (Host Mode) */
 418                 while (!dwc_otg_is_host_mode(core_if)) {
 419                         DWC_PRINT("Waiting for Host Mode, Mode=%s\n",
 420                                   (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral"));
 421                         MDELAY(100);
 422                         if (++count > 10000) *(uint32_t*)NULL=0;
 423                 }
 424                 core_if->op_state = A_HOST;
 425                 /*
 426                  * Initialize the Core for Host mode.
 427                  */
 428                 dwc_otg_core_init(core_if);
 429                 dwc_otg_enable_global_interrupts(core_if);
 430                 hcd_start(core_if);
 431         }
 432 }
 433
 434
 435 /**
 436  * This function handles the Connector ID Status Change Interrupt.  It
 437  * reads the OTG Interrupt Register (GOTCTL) to determine whether this
 438  * is a Device to Host Mode transition or a Host Mode to Device
 439  * Transition.
 440  *
 441  * This only occurs when the cable is connected/removed from the PHY
 442  * connector.
 443  *
 444  * @param core_if Programming view of DWC_otg controller.
 445  */
 446 int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *core_if)
 447 {
 448
 449         /*
 450          * Need to disable SOF interrupt immediately. If switching from device
 451          * to host, the PCD interrupt handler won't handle the interrupt if
 452          * host mode is already set. The HCD interrupt handler won't get
 453          * called if the HCD state is HALT. This means that the interrupt does
 454          * not get handled and Linux complains loudly.
 455          */
 456         gintmsk_data_t gintmsk = { .d32 = 0 };
 457         gintsts_data_t gintsts = { .d32 = 0 };
 458
 459         gintmsk.b.sofintr = 1;
 460         dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
 461
 462         DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++  (%s)\n",
 463                     (dwc_otg_is_host_mode(core_if)?"Host":"Device"));
 464
 465         /*
 466          * Need to schedule a work, as there are possible DELAY function calls
 467         */
 468         queue_work(core_if->wq_otg, &core_if->w_conn_id);
 469
 470         /* Set flag and clear interrupt */
 471         gintsts.b.conidstschng = 1;
 472         dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
 473
 474         return 1;
 475 }
 476
 477 /**
 478  * This interrupt indicates that a device is initiating the Session
 479  * Request Protocol to request the host to turn on bus power so a new
 480  * session can begin. The handler responds by turning on bus power. If
 481  * the DWC_otg controller is in low power mode, the handler brings the
 482  * controller out of low power mode before turning on bus power.
 483  *
 484  * @param core_if Programming view of DWC_otg controller.
 485  */
 486 int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t *core_if)
 487 {
 488         hprt0_data_t hprt0;
 489         gintsts_data_t gintsts;
 490
 491 #ifndef DWC_HOST_ONLY
 492         DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
 493
 494         if (dwc_otg_is_device_mode(core_if)) {
 495                 DWC_PRINT("SRP: Device mode\n");
 496         } else {
 497                 DWC_PRINT("SRP: Host mode\n");
 498
 499                 /* Turn on the port power bit. */
 500                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
 501                 hprt0.b.prtpwr = 1;
 502                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 503
 504                 /* Start the Connection timer. So a message can be displayed
 505                  * if connect does not occur within 10 seconds. */
 506                 hcd_session_start(core_if);
 507         }
 508 #endif
 509
 510         /* Clear interrupt */
 511         gintsts.d32 = 0;
 512         gintsts.b.sessreqintr = 1;
 513         dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
 514
 515         return 1;
 516 }
 517
 518
 519 void w_wakeup_detected(struct work_struct *p)
 520 {
 521         struct delayed_work *dw = container_of(p, struct delayed_work, work);
 522         dwc_otg_core_if_t *core_if = container_of(dw, dwc_otg_core_if_t, w_wkp);
 523
 524         /*
 525          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
 526          * so that OPT tests pass with all PHYs).
 527          */
 528         hprt0_data_t hprt0 = {.d32=0};
 529         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 530         DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32);
 531 //      MDELAY(70);
 532         hprt0.b.prtres = 0; /* Resume */
 533         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 534         DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(core_if->host_if->hprt0));
 535 }
 536 /**
 537  * This interrupt indicates that the DWC_otg controller has detected a
 538  * resume or remote wakeup sequence. If the DWC_otg controller is in
 539  * low power mode, the handler must brings the controller out of low
 540  * power mode. The controller automatically begins resume
 541  * signaling. The handler schedules a time to stop resume signaling.
 542  */
 543 int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t *core_if)
 544 {
 545         gintsts_data_t gintsts;
 546
 547         DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n");
 548
 549         if (dwc_otg_is_device_mode(core_if)) {
 550                 dctl_data_t dctl = {.d32=0};
 551                 DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
 552                             dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts));
 553 #ifdef PARTIAL_POWER_DOWN
 554                 if (core_if->hwcfg4.b.power_optimiz) {
 555                         pcgcctl_data_t power = {.d32=0};
 556
 557                         power.d32 = dwc_read_reg32(core_if->pcgcctl);
 558                         DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32);
 559
 560                         power.b.stoppclk = 0;
 561                         dwc_write_reg32(core_if->pcgcctl, power.d32);
 562
 563                         power.b.pwrclmp = 0;
 564                         dwc_write_reg32(core_if->pcgcctl, power.d32);
 565
 566                         power.b.rstpdwnmodule = 0;
 567                         dwc_write_reg32(core_if->pcgcctl, power.d32);
 568                 }
 569 #endif
 570                 /* Clear the Remote Wakeup Signalling */
 571                 dctl.b.rmtwkupsig = 1;
 572                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl,
 573                                   dctl.d32, 0);
 574
 575                 if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
 576                         core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
 577                 }
 578
 579         } else {
 580                 pcgcctl_data_t pcgcctl = {.d32=0};
 581
 582                 /* Restart the Phy Clock */
 583                 pcgcctl.b.stoppclk = 1;
 584                 dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
 585
 586                 queue_delayed_work(core_if->wq_otg, &core_if->w_wkp, ((70 * HZ / 1000) + 1));
 587         }
 588
 589         /* Clear interrupt */
 590         gintsts.d32 = 0;
 591         gintsts.b.wkupintr = 1;
 592         dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
 593
 594         return 1;
 595 }
 596
 597 /**
 598  * This interrupt indicates that a device has been disconnected from
 599  * the root port.
 600  */
 601 int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t *core_if)
 602 {
 603         gintsts_data_t gintsts;
 604
 605         DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
 606                     (dwc_otg_is_host_mode(core_if)?"Host":"Device"),
 607                     op_state_str(core_if));
 608
 609 /** @todo Consolidate this if statement. */
 610 #ifndef DWC_HOST_ONLY
 611         if (core_if->op_state == B_HOST) {
 612                 dwc_otg_pcd_t *pcd;
 613
 614                 /* If in device mode Disconnect and stop the HCD, then
 615                  * start the PCD. */
 616                 hcd_disconnect(core_if);
 617
 618                 pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
 619                 if(unlikely(!pcd)) {
 620                         DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
 621                         BUG();
 622                 }
 623                 SPIN_LOCK(&pcd->lock);
 624
 625                 pcd_start(core_if);
 626
 627                 SPIN_UNLOCK(&pcd->lock);
 628                 core_if->op_state = B_PERIPHERAL;
 629         } else if (dwc_otg_is_device_mode(core_if)) {
 630                 gotgctl_data_t gotgctl = { .d32 = 0 };
 631                 gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
 632                 if (gotgctl.b.hstsethnpen==1) {
 633                         /* Do nothing, if HNP in process the OTG
 634                          * interrupt "Host Negotiation Detected"
 635                          * interrupt will do the mode switch.
 636                          */
 637                 } else if (gotgctl.b.devhnpen == 0) {
 638                         dwc_otg_pcd_t *pcd;
 639
 640                         /* If in device mode Disconnect and stop the HCD, then
 641                          * start the PCD. */
 642                         hcd_disconnect(core_if);
 643
 644                         pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
 645                         if(unlikely(!pcd)) {
 646                                 DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
 647                                 BUG();
 648                         }
 649                         SPIN_LOCK(&pcd->lock);
 650
 651                         pcd_start(core_if);
 652
 653                         SPIN_UNLOCK(&pcd->lock);
 654
 655                         core_if->op_state = B_PERIPHERAL;
 656                 } else {
 657                         DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n");
 658                 }
 659         } else {
 660                 if (core_if->op_state == A_HOST) {
 661                         /* A-Cable still connected but device disconnected. */
 662                         hcd_disconnect(core_if);
 663                 }
 664         }
 665 #endif
 666
 667         gintsts.d32 = 0;
 668         gintsts.b.disconnect = 1;
 669         dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
 670         return 1;
 671 }
 672 /**
 673  * This interrupt indicates that SUSPEND state has been detected on
 674  * the USB.
 675  *
 676  * For HNP the USB Suspend interrupt signals the change from
 677  * "a_peripheral" to "a_host".
 678  *
 679  * When power management is enabled the core will be put in low power
 680  * mode.
 681  */
 682 int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *core_if)
 683 {
 684         dsts_data_t dsts;
 685         gintsts_data_t gintsts;
 686
 687         DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n");
 688
 689         if (dwc_otg_is_device_mode(core_if)) {
 690                 dwc_otg_pcd_t *pcd;
 691
 692                 /* Check the Device status register to determine if the Suspend
 693                  * state is active. */
 694                 dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
 695                 DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
 696                 DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
 697                             "HWCFG4.power Optimize=%d\n",
 698                             dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
 699
 700
 701 #ifdef PARTIAL_POWER_DOWN
 702 /** @todo Add a module parameter for power management. */
 703                 if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
 704                         pcgcctl_data_t power = {.d32=0};
 705                         DWC_DEBUGPL(DBG_CIL, "suspend\n");
 706
 707                         power.b.pwrclmp = 1;
 708                         dwc_write_reg32(core_if->pcgcctl, power.d32);
 709
 710                         power.b.rstpdwnmodule = 1;
 711                         dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
 712
 713                         power.b.stoppclk = 1;
 714                         dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
 715                 } else {
 716                         DWC_DEBUGPL(DBG_ANY,"disconnect?\n");
 717                 }
 718 #endif
 719                 /* PCD callback for suspend. */
 720                 pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
 721                 if(unlikely(!pcd)) {
 722                         DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
 723                         BUG();
 724                 }
 725                 SPIN_LOCK(&pcd->lock);
 726
 727                 pcd_suspend(core_if);
 728
 729                 SPIN_UNLOCK(&pcd->lock);
 730         } else {
 731                 if (core_if->op_state == A_PERIPHERAL) {
 732                         dwc_otg_pcd_t *pcd;
 733
 734                         DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n");
 735                         /* Clear the a_peripheral flag, back to a_host. */
 736
 737                         pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
 738                         if(unlikely(!pcd)) {
 739                                 DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
 740                                 BUG();
 741                         }
 742                         SPIN_LOCK(&pcd->lock);
 743
 744                         pcd_stop(core_if);
 745
 746                         SPIN_UNLOCK(&pcd->lock);
 747
 748                         hcd_start(core_if);
 749                         core_if->op_state = A_HOST;
 750                 }
 751         }
 752
 753         /* Clear interrupt */
 754         gintsts.d32 = 0;
 755         gintsts.b.usbsuspend = 1;
 756         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
 757
 758         return 1;
 759 }
 760
 761
 762 /**
 763  * This function returns the Core Interrupt register.
 764  */
 765 static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *core_if)
 766 {
 767         gintsts_data_t gintsts;
 768         gintmsk_data_t gintmsk;
 769         gintmsk_data_t gintmsk_common = {.d32=0};
 770         gintmsk_common.b.wkupintr = 1;
 771         gintmsk_common.b.sessreqintr = 1;
 772         gintmsk_common.b.conidstschng = 1;
 773         gintmsk_common.b.otgintr = 1;
 774         gintmsk_common.b.modemismatch = 1;
 775         gintmsk_common.b.disconnect = 1;
 776         gintmsk_common.b.usbsuspend = 1;
 777         /** @todo: The port interrupt occurs while in device
 778          * mode. Added code to CIL to clear the interrupt for now!
 779          */
 780         gintmsk_common.b.portintr = 1;
 781
 782         gintsts.d32 = dwc_read_reg32(&core_if->core_global_regs->gintsts);
 783         gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
 784 #ifdef DEBUG
 785         /* if any common interrupts set */
 786         if (gintsts.d32 & gintmsk_common.d32) {
 787                 DWC_DEBUGPL(DBG_ANY, "gintsts=%08x  gintmsk=%08x\n",
 788                             gintsts.d32, gintmsk.d32);
 789         }
 790 #endif
 791
 792         return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
 793
 794 }
 795
 796 /**
 797  * Common interrupt handler.
 798  *
 799  * The common interrupts are those that occur in both Host and Device mode.
 800  * This handler handles the following interrupts:
 801  * - Mode Mismatch Interrupt
 802  * - Disconnect Interrupt
 803  * - OTG Interrupt
 804  * - Connector ID Status Change Interrupt
 805  * - Session Request Interrupt.
 806  * - Resume / Remote Wakeup Detected Interrupt.
 807  *
 808  */
 809 int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t *core_if)
 810 {
 811         int retval = 0;
 812         gintsts_data_t gintsts;
 813
 814         gintsts.d32 = dwc_otg_read_common_intr(core_if);
 815
 816         if (gintsts.b.modemismatch) {
 817                 retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
 818         }
 819         if (gintsts.b.otgintr) {
 820                 retval |= dwc_otg_handle_otg_intr(core_if);
 821         }
 822         if (gintsts.b.conidstschng) {
 823                 retval |= dwc_otg_handle_conn_id_status_change_intr(core_if);
 824         }
 825         if (gintsts.b.disconnect) {
 826                 retval |= dwc_otg_handle_disconnect_intr(core_if);
 827         }
 828         if (gintsts.b.sessreqintr) {
 829                 retval |= dwc_otg_handle_session_req_intr(core_if);
 830         }
 831         if (gintsts.b.wkupintr) {
 832                 retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
 833         }
 834         if (gintsts.b.usbsuspend) {
 835                 retval |= dwc_otg_handle_usb_suspend_intr(core_if);
 836         }
 837         if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
 838                 /* The port interrupt occurs while in device mode with HPRT0
 839                  * Port Enable/Disable.
 840                  */
 841                 gintsts.d32 = 0;
 842                 gintsts.b.portintr = 1;
 843                 dwc_write_reg32(&core_if->core_global_regs->gintsts,
 844                                 gintsts.d32);
 845                 retval |= 1;
 846
 847         }
 848
 849         S3C2410X_CLEAR_EINTPEND();
 850
 851         return retval;
 852 }