target/linux/brcm63xx/patches-3.9/424-bcm3368_support.patch

   1 --- a/arch/mips/bcm63xx/Kconfig
   2 +++ b/arch/mips/bcm63xx/Kconfig
   3 @@ -13,6 +13,10 @@ config BCM63XX_EHCI
   4         select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD
   5         select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD
   6
   7 +config BCM63XX_CPU_3368
   8 +       bool "support 3368 CPU"
   9 +       select HW_HAS_PCI
  10 +
  11  config BCM63XX_CPU_6328
  12         bool "support 6328 CPU"
  13         select HW_HAS_PCI
  14 --- a/arch/mips/bcm63xx/cpu.c
  15 +++ b/arch/mips/bcm63xx/cpu.c
  16 @@ -29,6 +29,14 @@ static u8 bcm63xx_cpu_rev;
  17  static unsigned int bcm63xx_cpu_freq;
  18  static unsigned int bcm63xx_memory_size;
  19
  20 +static const unsigned long bcm3368_regs_base[] = {
  21 +       __GEN_CPU_REGS_TABLE(3368)
  22 +};
  23 +
  24 +static const int bcm3368_irqs[] = {
  25 +       __GEN_CPU_IRQ_TABLE(3368)
  26 +};
  27 +
  28  static const unsigned long bcm6328_regs_base[] = {
  29         __GEN_CPU_REGS_TABLE(6328)
  30  };
  31 @@ -116,6 +124,9 @@ unsigned int bcm63xx_get_memory_size(voi
  32  static unsigned int detect_cpu_clock(void)
  33  {
  34         switch (bcm63xx_get_cpu_id()) {
  35 +       case BCM3368_CPU_ID:
  36 +               return 300000000;
  37 +
  38         case BCM6328_CPU_ID:
  39         {
  40                 unsigned int tmp, mips_pll_fcvo;
  41 @@ -266,7 +277,7 @@ static unsigned int detect_memory_size(v
  42                 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
  43         }
  44
  45 -       if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
  46 +       if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
  47                 val = bcm_memc_readl(MEMC_CFG_REG);
  48                 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
  49                 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
  50 @@ -302,10 +313,17 @@ void __init bcm63xx_cpu_init(void)
  51                 chipid_reg = BCM_6345_PERF_BASE;
  52                 break;
  53         case CPU_BMIPS4350:
  54 -               if ((read_c0_prid() & 0xf0) == 0x10)
  55 +               switch ((read_c0_prid() & 0xff)) {
  56 +               case 0x04:
  57 +                       chipid_reg = BCM_3368_PERF_BASE;
  58 +                       break;
  59 +               case 0x10:
  60                         chipid_reg = BCM_6345_PERF_BASE;
  61 -               else
  62 +                       break;
  63 +               default:
  64                         chipid_reg = BCM_6368_PERF_BASE;
  65 +                       break;
  66 +               }
  67                 break;
  68         }
  69
  70 @@ -322,6 +340,10 @@ void __init bcm63xx_cpu_init(void)
  71         bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
  72
  73         switch (bcm63xx_cpu_id) {
  74 +       case BCM3368_CPU_ID:
  75 +               bcm63xx_regs_base = bcm3368_regs_base;
  76 +               bcm63xx_irqs = bcm3368_irqs;
  77 +               break;
  78         case BCM6328_CPU_ID:
  79                 bcm63xx_regs_base = bcm6328_regs_base;
  80                 bcm63xx_irqs = bcm6328_irqs;
  81 --- a/arch/mips/bcm63xx/dev-uart.c
  82 +++ b/arch/mips/bcm63xx/dev-uart.c
  83 @@ -54,8 +54,8 @@ int __init bcm63xx_uart_register(unsigne
  84         if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
  85                 return -ENODEV;
  86
  87 -       if (id == 1 && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&
  88 -           !BCMCPU_IS_6368())
  89 +       if (id == 1 && !BCMCPU_IS_3368() && !BCMCPU_IS_6328() &&
  90 +                       !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
  91                 return -ENODEV;
  92
  93         if (id == 0) {
  94 --- a/arch/mips/bcm63xx/prom.c
  95 +++ b/arch/mips/bcm63xx/prom.c
  96 @@ -30,7 +30,9 @@ void __init prom_init(void)
  97         bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
  98
  99         /* disable all hardware blocks clock for now */
 100 -       if (BCMCPU_IS_6328())
 101 +       if (BCMCPU_IS_3368())
 102 +               mask = CKCTL_3368_ALL_SAFE_EN;
 103 +       else if (BCMCPU_IS_6328())
 104                 mask = CKCTL_6328_ALL_SAFE_EN;
 105         else if (BCMCPU_IS_6338())
 106                 mask = CKCTL_6338_ALL_SAFE_EN;
 107 --- a/arch/mips/bcm63xx/setup.c
 108 +++ b/arch/mips/bcm63xx/setup.c
 109 @@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void)
 110
 111         /* mask and clear all external irq */
 112         switch (bcm63xx_get_cpu_id()) {
 113 +       case BCM3368_CPU_ID:
 114 +               perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368;
 115 +               break;
 116         case BCM6328_CPU_ID:
 117                 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
 118                 break;
 119 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 120 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 121 @@ -9,6 +9,7 @@
 122   * compile time if only one CPU support is enabled (idea stolen from
 123   * arm mach-types)
 124   */
 125 +#define BCM3368_CPU_ID         0x3368
 126  #define BCM6328_CPU_ID         0x6328
 127  #define BCM6338_CPU_ID         0x6338
 128  #define BCM6345_CPU_ID         0x6345
 129 @@ -22,6 +23,19 @@ u16 __bcm63xx_get_cpu_id(void);
 130  u8 bcm63xx_get_cpu_rev(void);
 131  unsigned int bcm63xx_get_cpu_freq(void);
 132
 133 +#ifdef CONFIG_BCM63XX_CPU_3368
 134 +# ifdef bcm63xx_get_cpu_id
 135 +#  undef bcm63xx_get_cpu_id
 136 +#  define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
 137 +#  define BCMCPU_RUNTIME_DETECT
 138 +# else
 139 +#  define bcm63xx_get_cpu_id() BCM3368_CPU_ID
 140 +# endif
 141 +# define BCMCPU_IS_3368()      (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
 142 +#else
 143 +# define BCMCPU_IS_3368()      (0)
 144 +#endif
 145 +
 146  #ifdef CONFIG_BCM63XX_CPU_6328
 147  # ifdef bcm63xx_get_cpu_id
 148  #  undef bcm63xx_get_cpu_id
 149 @@ -196,6 +210,53 @@ enum bcm63xx_regs_set {
 150  #define RSET_RNG_SIZE                  20
 151
 152  /*
 153 + * 3368 register sets base address
 154 + */
 155 +#define BCM_3368_DSL_LMEM_BASE         (0xdeadbeef)
 156 +#define BCM_3368_PERF_BASE             (0xfff8c000)
 157 +#define BCM_3368_TIMER_BASE            (0xfff8c040)
 158 +#define BCM_3368_WDT_BASE              (0xfff8c080)
 159 +#define BCM_3368_UART0_BASE            (0xfff8c100)
 160 +#define BCM_3368_UART1_BASE            (0xfff8c120)
 161 +#define BCM_3368_GPIO_BASE             (0xfff8c080)
 162 +#define BCM_3368_SPI_BASE              (0xfff8c800)
 163 +#define BCM_3368_HSSPI_BASE            (0xdeadbeef)
 164 +#define BCM_3368_UDC0_BASE             (0xdeadbeef)
 165 +#define BCM_3368_USBDMA_BASE           (0xdeadbeef)
 166 +#define BCM_3368_OHCI0_BASE            (0xdeadbeef)
 167 +#define BCM_3368_OHCI_PRIV_BASE                (0xdeadbeef)
 168 +#define BCM_3368_USBH_PRIV_BASE                (0xdeadbeef)
 169 +#define BCM_3368_USBD_BASE             (0xdeadbeef)
 170 +#define BCM_3368_MPI_BASE              (0xfff80000)
 171 +#define BCM_3368_PCMCIA_BASE           (0xfff80054)
 172 +#define BCM_3368_PCIE_BASE             (0xdeadbeef)
 173 +#define BCM_3368_SDRAM_REGS_BASE       (0xdeadbeef)
 174 +#define BCM_3368_DSL_BASE              (0xdeadbeef)
 175 +#define BCM_3368_UBUS_BASE             (0xdeadbeef)
 176 +#define BCM_3368_ENET0_BASE            (0xfff98000)
 177 +#define BCM_3368_ENET1_BASE            (0xfff98800)
 178 +#define BCM_3368_ENETDMA_BASE          (0xfff99800)
 179 +#define BCM_3368_ENETDMAC_BASE         (0xfff99900)
 180 +#define BCM_3368_ENETDMAS_BASE         (0xfff99a00)
 181 +#define BCM_3368_ENETSW_BASE           (0xdeadbeef)
 182 +#define BCM_3368_EHCI0_BASE            (0xdeadbeef)
 183 +#define BCM_3368_SDRAM_BASE            (0xdeadbeef)
 184 +#define BCM_3368_MEMC_BASE             (0xfff84000)
 185 +#define BCM_3368_DDR_BASE              (0xdeadbeef)
 186 +#define BCM_3368_M2M_BASE              (0xdeadbeef)
 187 +#define BCM_3368_ATM_BASE              (0xdeadbeef)
 188 +#define BCM_3368_XTM_BASE              (0xdeadbeef)
 189 +#define BCM_3368_XTMDMA_BASE           (0xdeadbeef)
 190 +#define BCM_3368_XTMDMAC_BASE          (0xdeadbeef)
 191 +#define BCM_3368_XTMDMAS_BASE          (0xdeadbeef)
 192 +#define BCM_3368_PCM_BASE              (0xfff9c200)
 193 +#define BCM_3368_PCMDMA_BASE           (0xdeadbeef)
 194 +#define BCM_3368_PCMDMAC_BASE          (0xdeadbeef)
 195 +#define BCM_3368_PCMDMAS_BASE          (0xdeadbeef)
 196 +#define BCM_3368_RNG_BASE              (0xdeadbeef)
 197 +#define BCM_3368_MISC_BASE             (0xdeadbeef)
 198 +
 199 +/*
 200   * 6328 register sets base address
 201   */
 202  #define BCM_6328_DSL_LMEM_BASE         (0xdeadbeef)
 203 @@ -633,6 +694,9 @@ static inline unsigned long bcm63xx_regs
 204  #ifdef BCMCPU_RUNTIME_DETECT
 205         return bcm63xx_regs_base[set];
 206  #else
 207 +#ifdef CONFIG_BCM63XX_CPU_3368
 208 +       __GEN_RSET(3368)
 209 +#endif
 210  #ifdef CONFIG_BCM63XX_CPU_6328
 211         __GEN_RSET(6328)
 212  #endif
 213 @@ -701,6 +765,52 @@ enum bcm63xx_irq {
 214  };
 215
 216  /*
 217 + * 3368 irqs
 218 + */
 219 +#define BCM_3368_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
 220 +#define BCM_3368_SPI_IRQ               (IRQ_INTERNAL_BASE + 1)
 221 +#define BCM_3368_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 222 +#define BCM_3368_UART1_IRQ             (IRQ_INTERNAL_BASE + 3)
 223 +#define BCM_3368_DSL_IRQ               0
 224 +#define BCM_3368_UDC0_IRQ              0
 225 +#define BCM_3368_OHCI0_IRQ             0
 226 +#define BCM_3368_ENET0_IRQ             (IRQ_INTERNAL_BASE + 8)
 227 +#define BCM_3368_ENET1_IRQ             (IRQ_INTERNAL_BASE + 6)
 228 +#define BCM_3368_ENET_PHY_IRQ          (IRQ_INTERNAL_BASE + 9)
 229 +#define BCM_3368_ENET0_RXDMA_IRQ       (IRQ_INTERNAL_BASE + 15)
 230 +#define BCM_3368_ENET0_TXDMA_IRQ       (IRQ_INTERNAL_BASE + 16)
 231 +#define BCM_3368_HSSPI_IRQ             0
 232 +#define BCM_3368_EHCI0_IRQ             0
 233 +#define BCM_3368_USBD_IRQ              0
 234 +#define BCM_3368_USBD_RXDMA0_IRQ       0
 235 +#define BCM_3368_USBD_TXDMA0_IRQ       0
 236 +#define BCM_3368_USBD_RXDMA1_IRQ       0
 237 +#define BCM_3368_USBD_TXDMA1_IRQ       0
 238 +#define BCM_3368_USBD_RXDMA2_IRQ       0
 239 +#define BCM_3368_USBD_TXDMA2_IRQ       0
 240 +#define BCM_3368_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 17)
 241 +#define BCM_3368_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 18)
 242 +#define BCM_3368_PCI_IRQ               (IRQ_INTERNAL_BASE + 31)
 243 +#define BCM_3368_PCMCIA_IRQ            0
 244 +#define BCM_3368_ATM_IRQ               0
 245 +#define BCM_3368_ENETSW_RXDMA0_IRQ     0
 246 +#define BCM_3368_ENETSW_RXDMA1_IRQ     0
 247 +#define BCM_3368_ENETSW_RXDMA2_IRQ     0
 248 +#define BCM_3368_ENETSW_RXDMA3_IRQ     0
 249 +#define BCM_3368_ENETSW_TXDMA0_IRQ     0
 250 +#define BCM_3368_ENETSW_TXDMA1_IRQ     0
 251 +#define BCM_3368_ENETSW_TXDMA2_IRQ     0
 252 +#define BCM_3368_ENETSW_TXDMA3_IRQ     0
 253 +#define BCM_3368_XTM_IRQ               0
 254 +#define BCM_3368_XTM_DMA0_IRQ          0
 255 +
 256 +#define BCM_3368_EXT_IRQ0              (IRQ_INTERNAL_BASE + 25)
 257 +#define BCM_3368_EXT_IRQ1              (IRQ_INTERNAL_BASE + 26)
 258 +#define BCM_3368_EXT_IRQ2              (IRQ_INTERNAL_BASE + 27)
 259 +#define BCM_3368_EXT_IRQ3              (IRQ_INTERNAL_BASE + 28)
 260 +
 261 +
 262 +/*
 263   * 6328 irqs
 264   */
 265  #define BCM_6328_HIGH_IRQ_BASE         (IRQ_INTERNAL_BASE + 32)
 266 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
 267 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
 268 @@ -11,6 +11,7 @@ static inline unsigned long bcm63xx_gpio
 269         switch (bcm63xx_get_cpu_id()) {
 270         case BCM6328_CPU_ID:
 271                 return 32;
 272 +       case BCM3368_CPU_ID:
 273         case BCM6358_CPU_ID:
 274                 return 40;
 275         case BCM6338_CPU_ID:
 276 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 277 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 278 @@ -15,6 +15,39 @@
 279  /* Clock Control register */
 280  #define PERF_CKCTL_REG                 0x4
 281
 282 +#define CKCTL_3368_MAC_EN              (1 << 3)
 283 +#define CKCTL_3368_TC_EN               (1 << 5)
 284 +#define CKCTL_3368_US_TOP_EN           (1 << 6)
 285 +#define CKCTL_3368_DS_TOP_EN           (1 << 7)
 286 +#define CKCTL_3368_APM_EN              (1 << 8)
 287 +#define CKCTL_3368_SPI_EN              (1 << 9)
 288 +#define CKCTL_3368_USBS_EN             (1 << 10)
 289 +#define CKCTL_3368_BMU_EN              (1 << 11)
 290 +#define CKCTL_3368_PCM_EN              (1 << 12)
 291 +#define CKCTL_3368_NTP_EN              (1 << 13)
 292 +#define CKCTL_3368_ACP_B_EN            (1 << 14)
 293 +#define CKCTL_3368_ACP_A_EN            (1 << 15)
 294 +#define CKCTL_3368_EMUSB_EN            (1 << 17)
 295 +#define CKCTL_3368_ENET0_EN            (1 << 18)
 296 +#define CKCTL_3368_ENET1_EN            (1 << 19)
 297 +#define CKCTL_3368_USBU_EN             (1 << 20)
 298 +#define CKCTL_3368_EPHY_EN             (1 << 21)
 299 +
 300 +#define CKCTL_3368_ALL_SAFE_EN         (CKCTL_3368_MAC_EN | \
 301 +                                        CKCTL_3368_TC_EN | \
 302 +                                        CKCTL_3368_US_TOP_EN | \
 303 +                                        CKCTL_3368_DS_TOP_EN | \
 304 +                                        CKCTL_3368_APM_EN | \
 305 +                                        CKCTL_3368_SPI_EN | \
 306 +                                        CKCTL_3368_USBS_EN | \
 307 +                                        CKCTL_3368_BMU_EN | \
 308 +                                        CKCTL_3368_PCM_EN | \
 309 +                                        CKCTL_3368_NTP_EN | \
 310 +                                        CKCTL_3368_ACP_B_EN | \
 311 +                                        CKCTL_3368_ACP_A_EN | \
 312 +                                        CKCTL_3368_EMUSB_EN | \
 313 +                                        CKCTL_3368_USBU_EN)
 314 +
 315  #define CKCTL_6328_PHYMIPS_EN          (1 << 0)
 316  #define CKCTL_6328_ADSL_QPROC_EN       (1 << 1)
 317  #define CKCTL_6328_ADSL_AFE_EN         (1 << 2)
 318 @@ -181,6 +214,7 @@
 319  #define SYS_PLL_SOFT_RESET             0x1
 320
 321  /* Interrupt Mask register */
 322 +#define PERF_IRQMASK_3368_REG          0xc
 323  #define PERF_IRQMASK_6328_REG(x)       (0x20 + (x) * 0x10)
 324  #define PERF_IRQMASK_6338_REG          0xc
 325  #define PERF_IRQMASK_6345_REG          0xc
 326 @@ -190,6 +224,7 @@
 327  #define PERF_IRQMASK_6368_REG(x)       (0x20 + (x) * 0x10)
 328
 329  /* Interrupt Status register */
 330 +#define PERF_IRQSTAT_3368_REG          0x10
 331  #define PERF_IRQSTAT_6328_REG(x)       (0x28 + (x) * 0x10)
 332  #define PERF_IRQSTAT_6338_REG          0x10
 333  #define PERF_IRQSTAT_6345_REG          0x10
 334 @@ -199,6 +234,7 @@
 335  #define PERF_IRQSTAT_6368_REG(x)       (0x28 + (x) * 0x10)
 336
 337  /* External Interrupt Configuration register */
 338 +#define PERF_EXTIRQ_CFG_REG_3368       0x14
 339  #define PERF_EXTIRQ_CFG_REG_6328       0x18
 340  #define PERF_EXTIRQ_CFG_REG_6338       0x14
 341  #define PERF_EXTIRQ_CFG_REG_6345       0x14
 342 @@ -1386,7 +1422,7 @@
 343  #define SPI_6348_RX_DATA               0x80
 344  #define SPI_6348_RX_DATA_SIZE          0x3f
 345
 346 -/* BCM 6358/6262/6368 SPI core */
 347 +/* BCM 3368/6358/6262/6368 SPI core */
 348  #define SPI_6358_MSG_CTL               0x00    /* 16-bits register */
 349  #define SPI_6358_MSG_CTL_WIDTH         16
 350  #define SPI_6358_MSG_DATA              0x02
 351 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
 352 +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
 353 @@ -11,6 +11,10 @@ static inline phys_t fixup_bigphys_addr(
 354  static inline int is_bcm63xx_internal_registers(phys_t offset)
 355  {
 356         switch (bcm63xx_get_cpu_id()) {
 357 +       case BCM3368_CPU_ID:
 358 +               if (offset >= 0xfff80000)
 359 +                       return 1;
 360 +               break;
 361         case BCM6338_CPU_ID:
 362         case BCM6345_CPU_ID:
 363         case BCM6348_CPU_ID:
 364 --- a/arch/mips/bcm63xx/irq.c
 365 +++ b/arch/mips/bcm63xx/irq.c
 366 @@ -33,6 +33,19 @@ static DEFINE_SPINLOCK(ipic_lock);
 367  static DEFINE_SPINLOCK(epic_lock);
 368
 369  #ifndef BCMCPU_RUNTIME_DETECT
 370 +#ifdef CONFIG_BCM63XX_CPU_3368
 371 +#define irq_stat_reg0          PERF_IRQSTAT_3368_REG
 372 +#define irq_mask_reg0          PERF_IRQMASK_3368_REG
 373 +#define irq_stat_reg1          0
 374 +#define irq_mask_reg1          0
 375 +#define irq_bits               32
 376 +#define is_ext_irq_cascaded    0
 377 +#define ext_irq_start          0
 378 +#define ext_irq_end            0
 379 +#define ext_irq_count          4
 380 +#define ext_irq_cfg_reg1       PERF_EXTIRQ_CFG_REG_3368
 381 +#define ext_irq_cfg_reg2       0
 382 +#endif
 383  #ifdef CONFIG_BCM63XX_CPU_6328
 384  #define irq_stat_reg0          PERF_IRQSTAT_6328_REG(0)
 385  #define irq_mask_reg0          PERF_IRQMASK_6328_REG(0)
 386 @@ -165,6 +178,13 @@ static void bcm63xx_init_irq(void)
 387         irq_mask_addr1 = bcm63xx_regset_address(RSET_PERF);
 388
 389         switch (bcm63xx_get_cpu_id()) {
 390 +       case BCM3368_CPU_ID:
 391 +               irq_stat_addr0 += PERF_IRQSTAT_3368_REG;
 392 +               irq_mask_addr0 += PERF_IRQMASK_3368_REG;
 393 +               irq_bits = 32;
 394 +               ext_irq_count = 4;
 395 +               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
 396 +               break;
 397         case BCM6328_CPU_ID:
 398                 irq_stat_addr0 += PERF_IRQSTAT_6328_REG(0);
 399                 irq_mask_addr0 += PERF_IRQMASK_6328_REG(0);
 400 --- a/arch/mips/bcm63xx/dev-spi.c
 401 +++ b/arch/mips/bcm63xx/dev-spi.c
 402 @@ -37,7 +37,7 @@ static __init void bcm63xx_spi_regs_init
 403  {
 404         if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
 405                 bcm63xx_regs_spi = bcm6348_regs_spi;
 406 -       if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
 407 +       if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
 408                 bcm63xx_regs_spi = bcm6358_regs_spi;
 409  }
 410  #else
 411 @@ -87,7 +87,8 @@ int __init bcm63xx_spi_register(void)
 412                 spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;
 413         }
 414
 415 -       if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
 416 +       if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||
 417 +               BCMCPU_IS_6368()) {
 418                 spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
 419                 spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
 420                 spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
 421 --- a/arch/mips/bcm63xx/clk.c
 422 +++ b/arch/mips/bcm63xx/clk.c
 423 @@ -84,7 +84,7 @@ static void enetx_set(struct clk *clk, i
 424         else
 425                 clk_disable_unlocked(&clk_enet_misc);
 426
 427 -       if (BCMCPU_IS_6358()) {
 428 +       if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
 429                 u32 mask;
 430
 431                 if (clk->id == 0)
 432 @@ -110,9 +110,8 @@ static struct clk clk_enet1 = {
 433   */
 434  static void ephy_set(struct clk *clk, int enable)
 435  {
 436 -       if (!BCMCPU_IS_6358())
 437 -               return;
 438 -       bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
 439 +       if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
 440 +               bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
 441  }
 442
 443
 444 @@ -155,9 +154,10 @@ static struct clk clk_enetsw = {
 445   */
 446  static void pcm_set(struct clk *clk, int enable)
 447  {
 448 -       if (!BCMCPU_IS_6358())
 449 -               return;
 450 -       bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
 451 +       if (BCMCPU_IS_3368())
 452 +               bcm_hwclock_set(CKCTL_3368_PCM_EN, enable);
 453 +       if (BCMCPU_IS_6358())
 454 +               bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
 455  }
 456
 457  static struct clk clk_pcm = {
 458 @@ -221,7 +221,7 @@ static void spi_set(struct clk *clk, int
 459                 mask = CKCTL_6338_SPI_EN;
 460         else if (BCMCPU_IS_6348())
 461                 mask = CKCTL_6348_SPI_EN;
 462 -       else if (BCMCPU_IS_6358())
 463 +       else if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
 464                 mask = CKCTL_6358_SPI_EN;
 465         else if (BCMCPU_IS_6362())
 466                 mask = CKCTL_6362_SPI_EN;
 467 @@ -370,7 +370,7 @@ struct clk *clk_get(struct device *dev,
 468                 return &clk_xtm;
 469         if (!strcmp(id, "periph"))
 470                 return &clk_periph;
 471 -       if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
 472 +       if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
 473                 return &clk_pcm;
 474         if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
 475                 return &clk_ipsec;
 476 --- a/arch/mips/bcm63xx/dev-flash.c
 477 +++ b/arch/mips/bcm63xx/dev-flash.c
 478 @@ -102,6 +102,7 @@ static int __init bcm63xx_detect_flash_t
 479                 /* no way to auto detect so assume parallel */
 480                 bcm63xx_attached_flash = BCM63XX_FLASH_TYPE_PARALLEL;
 481                 break;
 482 +       case BCM3368_CPU_ID:
 483         case BCM6358_CPU_ID:
 484                 val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
 485                 if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL)
 486 --- a/arch/mips/pci/pci-bcm63xx.c
 487 +++ b/arch/mips/pci/pci-bcm63xx.c
 488 @@ -266,7 +266,7 @@ static int __init bcm63xx_register_pci(v
 489         /* setup PCI to local bus access, used by PCI device to target
 490          * local RAM while bus mastering */
 491         bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
 492 -       if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
 493 +       if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368())
 494                 val = MPI_SP0_REMAP_ENABLE_MASK;
 495         else
 496                 val = 0;
 497 @@ -338,6 +338,7 @@ static int __init bcm63xx_pci_init(void)
 498         case BCM6328_CPU_ID:
 499         case BCM6362_CPU_ID:
 500                 return bcm63xx_register_pcie();
 501 +       case BCM3368_CPU_ID:
 502         case BCM6348_CPU_ID:
 503         case BCM6358_CPU_ID:
 504         case BCM6368_CPU_ID: