target/linux/brcm63xx/patches-3.6/427-MIPS-BCM63XX-Register-SPI-flash-if-present.patch

   1 From d135d94b3d1fe599d13e7198d5f502912d694c13 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jonas.gorski@gmail.com>
   3 Date: Sun, 3 Jul 2011 15:00:38 +0200
   4 Subject: [PATCH 29/60] MIPS: BCM63XX: Register SPI flash if present
   5
   6 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
   7 ---
   8  arch/mips/bcm63xx/dev-flash.c                     |   33 +++++++++++++++++++-
   9  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    2 +
  10  2 files changed, 33 insertions(+), 2 deletions(-)
  11
  12 --- a/arch/mips/bcm63xx/dev-flash.c
  13 +++ b/arch/mips/bcm63xx/dev-flash.c
  14 @@ -16,9 +16,12 @@
  15  #include <linux/mtd/mtd.h>
  16  #include <linux/mtd/partitions.h>
  17  #include <linux/mtd/physmap.h>
  18 +#include <linux/spi/spi.h>
  19 +#include <linux/spi/flash.h>
  20
  21  #include <bcm63xx_cpu.h>
  22  #include <bcm63xx_dev_flash.h>
  23 +#include <bcm63xx_dev_hsspi.h>
  24  #include <bcm63xx_regs.h>
  25  #include <bcm63xx_io.h>
  26
  27 @@ -55,6 +58,21 @@ static struct platform_device mtd_dev =
  28         },
  29  };
  30
  31 +static struct flash_platform_data bcm63xx_flash_data = {
  32 +       .part_probe_types       = bcm63xx_part_types,
  33 +};
  34 +
  35 +static struct spi_board_info bcm63xx_spi_flash_info[] = {
  36 +       {
  37 +               .bus_num        = 0,
  38 +               .chip_select    = 0,
  39 +               .mode           = 0,
  40 +               .max_speed_hz   = 781000,
  41 +               .modalias       = "m25p80",
  42 +               .platform_data  = &bcm63xx_flash_data,
  43 +       },
  44 +};
  45 +
  46  static int __init bcm63xx_detect_flash_type(void)
  47  {
  48         u32 val;
  49 @@ -62,6 +80,11 @@ static int __init bcm63xx_detect_flash_t
  50         switch (bcm63xx_get_cpu_id()) {
  51         case BCM6328_CPU_ID:
  52                 val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
  53 +               if (val & STRAPBUS_6328_HSSPI_CLK_FAST)
  54 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 33333334;
  55 +               else
  56 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 16666667;
  57 +
  58                 if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
  59                         return BCM63XX_FLASH_TYPE_SERIAL;
  60                 else
  61 @@ -79,6 +102,9 @@ static int __init bcm63xx_detect_flash_t
  62                         return BCM63XX_FLASH_TYPE_SERIAL;
  63         case BCM6368_CPU_ID:
  64                 val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
  65 +               if (val & STRAPBUS_6368_SPI_CLK_FAST)
  66 +                       bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
  67 +
  68                 switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
  69                 case STRAPBUS_6368_BOOT_SEL_NAND:
  70                         return BCM63XX_FLASH_TYPE_NAND;
  71 @@ -110,8 +136,11 @@ int __init bcm63xx_flash_register(void)
  72
  73                 return platform_device_register(&mtd_dev);
  74         case BCM63XX_FLASH_TYPE_SERIAL:
  75 -               pr_warn("unsupported serial flash detected\n");
  76 -               return -ENODEV;
  77 +               if (BCMCPU_IS_6328())
  78 +                       bcm63xx_flash_data.max_transfer_len = HSSPI_BUFFER_LEN;
  79 +
  80 +               return spi_register_board_info(bcm63xx_spi_flash_info,
  81 +                                       ARRAY_SIZE(bcm63xx_spi_flash_info));
  82         case BCM63XX_FLASH_TYPE_NAND:
  83                 pr_warn("unsupported NAND flash detected\n");
  84                 return -ENODEV;
  85 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  86 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  87 @@ -608,6 +608,7 @@
  88  #define GPIO_STRAPBUS_REG              0x40
  89  #define STRAPBUS_6358_BOOT_SEL_PARALLEL        (1 << 1)
  90  #define STRAPBUS_6358_BOOT_SEL_SERIAL  (0 << 1)
  91 +#define STRAPBUS_6368_SPI_CLK_FAST     (1 << 6)
  92  #define STRAPBUS_6368_BOOT_SEL_MASK    0x3
  93  #define STRAPBUS_6368_BOOT_SEL_NAND    0
  94  #define STRAPBUS_6368_BOOT_SEL_SERIAL  1
  95 @@ -1300,6 +1301,7 @@
  96  #define STRAPBUS_6362_BOOT_SEL_NAND    (0 << 15)
  97
  98  #define MISC_STRAPBUS_6328_REG         0x240
  99 +#define STRAPBUS_6328_HSSPI_CLK_FAST   (1 << 4)
 100  #define STRAPBUS_6328_FCVO_SHIFT       7
 101  #define STRAPBUS_6328_FCVO_MASK                (0x1f << STRAPBUS_6328_FCVO_SHIFT)
 102  #define STRAPBUS_6328_BOOT_SEL_SERIAL  (1 << 28)