target/linux/brcm63xx/patches-3.6/426-SPI-MIPS-BCM63XX-Add-HS-SPI-driver.patch

   1 From 4b27423676485d05bcd6fc6f3809164fb8f9d22d Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jonas.gorski@gmail.com>
   3 Date: Sat, 12 Nov 2011 12:19:55 +0100
   4 Subject: [PATCH 30/60] SPI: MIPS: BCM63XX: Add HSSPI driver
   5
   6 Add a driver for the High Speed SPI controller found on newer BCM63XX SoCs.
   7
   8 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
   9 ---
  10  .../include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h   |    2 +
  11  drivers/spi/Kconfig                                |    7 +
  12  drivers/spi/Makefile                               |    1 +
  13  drivers/spi/spi-bcm63xx-hsspi.c                    |  427 ++++++++++++++++++++
  14  4 files changed, 437 insertions(+), 0 deletions(-)
  15  create mode 100644 drivers/spi/spi-bcm63xx-hsspi.c
  16
  17 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
  18 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
  19 @@ -17,4 +17,6 @@ struct bcm63xx_hsspi_pdata {
  20
  21  #define HSSPI_PLL_HZ_6328      133333333
  22
  23 +#define HSSPI_BUFFER_LEN       512
  24 +
  25  #endif /* BCM63XX_DEV_HSSPI_H */
  26 --- a/drivers/spi/Kconfig
  27 +++ b/drivers/spi/Kconfig
  28 @@ -100,6 +100,13 @@ config SPI_BCM63XX
  29         help
  30            Enable support for the SPI controller on the Broadcom BCM63xx SoCs.
  31
  32 +config SPI_BCM63XX_HSSPI
  33 +       tristate "Broadcom BCM63XX HS SPI controller driver"
  34 +       depends on BCM63XX
  35 +       help
  36 +         This enables support for the High Speed SPI controller present on
  37 +         newer Broadcom BCM63XX SoCs.
  38 +
  39  config SPI_BITBANG
  40         tristate "Utilities for Bitbanging SPI masters"
  41         help
  42 --- a/drivers/spi/Makefile
  43 +++ b/drivers/spi/Makefile
  44 @@ -15,6 +15,7 @@ obj-$(CONFIG_SPI_ATMEL)                       += spi-atmel.o
  45  obj-$(CONFIG_SPI_ATH79)                        += spi-ath79.o
  46  obj-$(CONFIG_SPI_AU1550)               += spi-au1550.o
  47  obj-$(CONFIG_SPI_BCM63XX)              += spi-bcm63xx.o
  48 +obj-$(CONFIG_SPI_BCM63XX_HSSPI)                += spi-bcm63xx-hsspi.o
  49  obj-$(CONFIG_SPI_BFIN5XX)              += spi-bfin5xx.o
  50  obj-$(CONFIG_SPI_BFIN_SPORT)           += spi-bfin-sport.o
  51  obj-$(CONFIG_SPI_BITBANG)              += spi-bitbang.o
  52 --- /dev/null
  53 +++ b/drivers/spi/spi-bcm63xx-hsspi.c
  54 @@ -0,0 +1,427 @@
  55 +/*
  56 + * Broadcom BCM63XX High Speed SPI Controller driver
  57 + *
  58 + * Copyright 2000-2010 Broadcom Corporation
  59 + * Copyright 2012 Jonas Gorski <jonas.gorski@gmail.com>
  60 + *
  61 + * Licensed under the GNU/GPL. See COPYING for details.
  62 + */
  63 +
  64 +#include <linux/kernel.h>
  65 +#include <linux/init.h>
  66 +#include <linux/io.h>
  67 +#include <linux/clk.h>
  68 +#include <linux/module.h>
  69 +#include <linux/platform_device.h>
  70 +#include <linux/delay.h>
  71 +#include <linux/dma-mapping.h>
  72 +#include <linux/err.h>
  73 +#include <linux/interrupt.h>
  74 +#include <linux/spi/spi.h>
  75 +#include <linux/workqueue.h>
  76 +
  77 +#include <bcm63xx_regs.h>
  78 +#include <bcm63xx_dev_hsspi.h>
  79 +
  80 +#define HSSPI_OP_CODE_SHIFT    13
  81 +#define HSSPI_OP_SLEEP         (0 << HSSPI_OP_CODE_SHIFT)
  82 +#define HSSPI_OP_READ_WRITE    (1 << HSSPI_OP_CODE_SHIFT)
  83 +#define HSSPI_OP_WRITE         (2 << HSSPI_OP_CODE_SHIFT)
  84 +#define HSSPI_OP_READ          (3 << HSSPI_OP_CODE_SHIFT)
  85 +
  86 +#define HSSPI_MAX_PREPEND_LEN  15
  87 +
  88 +#define HSSPI_MAX_SYNC_CLOCK   30000000
  89 +
  90 +struct bcm63xx_hsspi {
  91 +       struct completion       done;
  92 +       struct spi_transfer     *curr_trans;
  93 +
  94 +       struct platform_device  *pdev;
  95 +       struct clk              *clk;
  96 +       void __iomem            *regs;
  97 +       u8 __iomem              *fifo;
  98 +
  99 +       u32                     speed_hz;
 100 +       int                     irq;
 101 +};
 102 +
 103 +static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs, int hz,
 104 +                                 int profile)
 105 +{
 106 +       u32 reg;
 107 +
 108 +       reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
 109 +       bcm_hsspi_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
 110 +                        HSSPI_PROFILE_CLK_CTRL_REG(profile));
 111 +
 112 +       reg = bcm_hsspi_readl(HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
 113 +       if (hz > HSSPI_MAX_SYNC_CLOCK)
 114 +               reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
 115 +       else
 116 +               reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
 117 +       bcm_hsspi_writel(reg, HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
 118 +}
 119 +
 120 +static int bcm63xx_hsspi_do_txrx(struct spi_device *spi,
 121 +                                struct spi_transfer *t1,
 122 +                                struct spi_transfer *t2)
 123 +{
 124 +       struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
 125 +       u8 chip_select = spi->chip_select;
 126 +       u16 opcode = 0;
 127 +       int len, prepend_size = 0;
 128 +
 129 +       init_completion(&bs->done);
 130 +
 131 +       bs->curr_trans = t2 ? t2 : t1;
 132 +       bcm63xx_hsspi_set_clk(bs, bs->curr_trans->speed_hz, chip_select);
 133 +
 134 +       if (t2 && !t2->tx_buf)
 135 +               prepend_size = t1->len;
 136 +
 137 +       bcm_hsspi_writel(prepend_size << MODE_CTRL_PREPENDBYTE_CNT_SHIFT |
 138 +                        2 << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT |
 139 +                        2 << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT | 0xff,
 140 +                        HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
 141 +
 142 +       if (t1->rx_buf && t1->tx_buf)
 143 +               opcode = HSSPI_OP_READ_WRITE;
 144 +       else if (t1->rx_buf || (t2 && t2->rx_buf))
 145 +               opcode = HSSPI_OP_READ;
 146 +       else if (t1->tx_buf)
 147 +               opcode = HSSPI_OP_WRITE;
 148 +
 149 +       if (opcode == HSSPI_OP_READ && t2)
 150 +               len = t2->len;
 151 +       else
 152 +               len = t1->len;
 153 +
 154 +       if (t1->tx_buf) {
 155 +               memcpy_toio(bs->fifo + 2, t1->tx_buf, t1->len);
 156 +               if (t2 && t2->tx_buf) {
 157 +                       memcpy_toio(bs->fifo + 2 + t1->len,
 158 +                                   t2->tx_buf, t2->len);
 159 +                       len += t2->len;
 160 +               }
 161 +       }
 162 +
 163 +       opcode |= len;
 164 +       memcpy_toio(bs->fifo, &opcode, sizeof(opcode));
 165 +
 166 +       /* enable interrupt */
 167 +       bcm_hsspi_writel(HSSPI_PING0_CMD_DONE, HSSPI_INT_MASK_REG);
 168 +
 169 +       /* start the transfer */
 170 +       bcm_hsspi_writel(chip_select << PINGPONG_CMD_SS_SHIFT |
 171 +                        chip_select << PINGPONG_CMD_PROFILE_SHIFT |
 172 +                        PINGPONG_COMMAND_START_NOW,
 173 +                        HSSPI_PINGPONG_COMMAND_REG(0));
 174 +
 175 +       if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
 176 +               dev_err(&bs->pdev->dev, "transfer timed out!\n");
 177 +               return -ETIMEDOUT;
 178 +       }
 179 +
 180 +       return t1->len + (t2 ? t2->len : 0);
 181 +}
 182 +
 183 +static int bcm63xx_hsspi_setup(struct spi_device *spi)
 184 +{
 185 +       u32 reg;
 186 +
 187 +       if (spi->bits_per_word != 8)
 188 +               return -EINVAL;
 189 +
 190 +       if (spi->max_speed_hz == 0)
 191 +               return -EINVAL;
 192 +
 193 +       reg = bcm_hsspi_readl(HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
 194 +       reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
 195 +       if (spi->mode & SPI_CPHA)
 196 +               reg |= SIGNAL_CTRL_LAUNCH_RISING;
 197 +       else
 198 +               reg |= SIGNAL_CTRL_LATCH_RISING;
 199 +       bcm_hsspi_writel(reg, HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
 200 +
 201 +       return 0;
 202 +}
 203 +
 204 +static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
 205 +                                     struct spi_message *msg)
 206 +{
 207 +       struct spi_transfer *t, *prev = NULL;
 208 +       struct spi_device *spi = msg->spi;
 209 +       u32 reg;
 210 +       int ret = -EINVAL;
 211 +       int len = 0;
 212 +
 213 +       /* check if we are able to make these transfers */
 214 +       list_for_each_entry(t, &msg->transfers, transfer_list) {
 215 +               if (!t->tx_buf && !t->rx_buf)
 216 +                       goto out;
 217 +
 218 +               if (t->speed_hz == 0)
 219 +                       t->speed_hz = spi->max_speed_hz;
 220 +
 221 +               if (t->speed_hz > spi->max_speed_hz)
 222 +                       goto out;
 223 +
 224 +               if (t->len > HSSPI_BUFFER_LEN)
 225 +                       goto out;
 226 +
 227 +               /*
 228 +                * This controller does not support keeping the chip select
 229 +                * active between transfers.
 230 +                * This logic currently supports combining:
 231 +                *  write then read with no cs_change (e.g. m25p80 RDSR)
 232 +                *  write then write with no cs_change (e.g. m25p80 PP)
 233 +                */
 234 +               if (prev && prev->tx_buf && !prev->cs_change && !t->cs_change) {
 235 +                       /*
 236 +                        * reject if we have to combine two tx transfers and
 237 +                        * their combined length is bigger than the buffer
 238 +                        */
 239 +                       if (prev->tx_buf && t->tx_buf &&
 240 +                           (prev->len + t->len) > HSSPI_BUFFER_LEN)
 241 +                               goto out;
 242 +                       /*
 243 +                        * reject if we need write more than 15 bytes in read
 244 +                        * then write.
 245 +                        */
 246 +                       if (prev->tx_buf && t->rx_buf &&
 247 +                           prev->len > HSSPI_MAX_PREPEND_LEN)
 248 +                               goto out;
 249 +               }
 250 +
 251 +       }
 252 +
 253 +       /* setup clock polarity */
 254 +       reg = bcm_hsspi_readl(HSSPI_GLOBAL_CTRL_REG);
 255 +       reg &= ~GLOBAL_CTRL_CLK_POLARITY;
 256 +       if (spi->mode & SPI_CPOL)
 257 +               reg |= GLOBAL_CTRL_CLK_POLARITY;
 258 +       bcm_hsspi_writel(reg, HSSPI_GLOBAL_CTRL_REG);
 259 +
 260 +       list_for_each_entry(t, &msg->transfers, transfer_list) {
 261 +               if (prev && prev->tx_buf && !prev->cs_change && !t->cs_change) {
 262 +                       /* combine write with following transfer */
 263 +                       ret = bcm63xx_hsspi_do_txrx(msg->spi, prev, t);
 264 +                       if (ret < 0)
 265 +                               goto out;
 266 +
 267 +                       len += ret;
 268 +                       prev = NULL;
 269 +                       continue;
 270 +               }
 271 +
 272 +               /* write the previous pending transfer */
 273 +               if (prev != NULL) {
 274 +                       ret = bcm63xx_hsspi_do_txrx(msg->spi, prev, NULL);
 275 +                       if (ret < 0)
 276 +                               goto out;
 277 +
 278 +                       len += ret;
 279 +               }
 280 +
 281 +               prev = t;
 282 +       }
 283 +
 284 +       /* do last pending transfer */
 285 +       if (prev != NULL) {
 286 +               ret = bcm63xx_hsspi_do_txrx(msg->spi, prev, NULL);
 287 +               if (ret < 0)
 288 +                       goto out;
 289 +               len += ret;
 290 +       }
 291 +
 292 +       msg->actual_length = len;
 293 +       ret = 0;
 294 +out:
 295 +       msg->status = ret;
 296 +       spi_finalize_current_message(master);
 297 +       return 0;
 298 +}
 299 +
 300 +static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
 301 +{
 302 +       struct spi_master *master = (struct spi_master *)dev_id;
 303 +       struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
 304 +
 305 +       if (bcm_hsspi_readl(HSSPI_INT_STATUS_MASKED_REG) == 0)
 306 +               return IRQ_NONE;
 307 +
 308 +       bcm_hsspi_writel(HSSPI_INT_CLEAR_ALL, HSSPI_INT_STATUS_REG);
 309 +       bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
 310 +
 311 +       if (bs->curr_trans && bs->curr_trans->rx_buf)
 312 +               memcpy_fromio(bs->curr_trans->rx_buf,  bs->fifo,
 313 +                             bs->curr_trans->len);
 314 +       complete(&bs->done);
 315 +
 316 +       return IRQ_HANDLED;
 317 +}
 318 +
 319 +static int __devinit bcm63xx_hsspi_probe(struct platform_device *pdev)
 320 +{
 321 +
 322 +       struct spi_master *master;
 323 +       struct bcm63xx_hsspi *bs;
 324 +       struct resource *res_mem;
 325 +       void __iomem *regs;
 326 +       struct device *dev = &pdev->dev;
 327 +       struct bcm63xx_hsspi_pdata *pdata = pdev->dev.platform_data;
 328 +       struct clk *clk;
 329 +       int irq;
 330 +       int ret;
 331 +
 332 +       irq = platform_get_irq(pdev, 0);
 333 +       if (irq < 0) {
 334 +               dev_err(dev, "no irq\n");
 335 +               return -ENXIO;
 336 +       }
 337 +
 338 +       res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 339 +       regs = devm_request_and_ioremap(dev, res_mem);
 340 +       if (!regs) {
 341 +               dev_err(dev, "unable to ioremap regs\n");
 342 +               return -ENXIO;
 343 +       }
 344 +
 345 +       clk = clk_get(dev, "hsspi");
 346 +
 347 +       if (IS_ERR(clk)) {
 348 +               ret = PTR_ERR(clk);
 349 +               goto out_release;
 350 +       }
 351 +
 352 +       clk_prepare_enable(clk);
 353 +
 354 +       master = spi_alloc_master(&pdev->dev, sizeof(*bs));
 355 +       if (!master) {
 356 +               ret = -ENOMEM;
 357 +               goto out_disable_clk;
 358 +       }
 359 +
 360 +       bs = spi_master_get_devdata(master);
 361 +       bs->pdev = pdev;
 362 +       bs->clk = clk;
 363 +       bs->regs = regs;
 364 +
 365 +       master->bus_num = pdata->bus_num;
 366 +       master->num_chipselect = 8;
 367 +       master->setup = bcm63xx_hsspi_setup;
 368 +       master->transfer_one_message = bcm63xx_hsspi_transfer_one;
 369 +       master->mode_bits = SPI_CPOL | SPI_CPHA;
 370 +
 371 +       bs->speed_hz = pdata->speed_hz;
 372 +       bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
 373 +
 374 +       platform_set_drvdata(pdev, master);
 375 +
 376 +       bs->curr_trans = NULL;
 377 +
 378 +       /* Initialize the hardware */
 379 +       bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
 380 +
 381 +       /* clean up any pending interrupts */
 382 +       bcm_hsspi_writel(HSSPI_INT_CLEAR_ALL, HSSPI_INT_STATUS_REG);
 383 +
 384 +       bcm_hsspi_writel(bcm_hsspi_readl(HSSPI_GLOBAL_CTRL_REG) |
 385 +                        GLOBAL_CTRL_CLK_GATE_SSOFF,
 386 +                        HSSPI_GLOBAL_CTRL_REG);
 387 +
 388 +       ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
 389 +                              pdev->name, master);
 390 +
 391 +       if (ret)
 392 +               goto out_put_master;
 393 +
 394 +       /* register and we are done */
 395 +       ret = spi_register_master(master);
 396 +       if (ret)
 397 +               goto out_free_irq;
 398 +
 399 +       return 0;
 400 +
 401 +out_free_irq:
 402 +       devm_free_irq(dev, bs->irq, master);
 403 +out_put_master:
 404 +       spi_master_put(master);
 405 +out_disable_clk:
 406 +       clk_disable_unprepare(clk);
 407 +       clk_put(clk);
 408 +out_release:
 409 +       devm_ioremap_release(dev, regs);
 410 +
 411 +       return ret;
 412 +}
 413 +
 414 +
 415 +static int __exit bcm63xx_hsspi_remove(struct platform_device *pdev)
 416 +{
 417 +       struct spi_master *master = platform_get_drvdata(pdev);
 418 +       struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
 419 +
 420 +       spi_unregister_master(master);
 421 +
 422 +       /* reset the hardware and block queue progress */
 423 +       bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
 424 +       clk_disable_unprepare(bs->clk);
 425 +       clk_put(bs->clk);
 426 +
 427 +       return 0;
 428 +}
 429 +
 430 +#ifdef CONFIG_PM
 431 +static int bcm63xx_hsspi_suspend(struct platform_device *pdev,
 432 +                                pm_message_t mesg)
 433 +{
 434 +       struct spi_master *master = platform_get_drvdata(pdev);
 435 +       struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
 436 +
 437 +       spi_master_suspend(master);
 438 +       clk_disable(bs->clk);
 439 +
 440 +       return 0;
 441 +}
 442 +
 443 +static int bcm63xx_hsspi_resume(struct platform_device *pdev)
 444 +{
 445 +       struct spi_master *master = platform_get_drvdata(pdev);
 446 +       struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
 447 +
 448 +       clk_enable(bs->clk);
 449 +       spi_master_resume(master);
 450 +
 451 +       return 0;
 452 +}
 453 +
 454 +static const struct dev_pm_ops bcm63xx_hsspi_pm_ops = {
 455 +       .suspend        = bcm63xx_hsspi_suspend,
 456 +       .resume         = bcm63xx_hsspi_resume,
 457 +};
 458 +
 459 +#define BCM63XX_HSSPI_PM_OPS   (&bcm63xx_hsspi_pm_ops)
 460 +#else
 461 +#define BCM63XX_HSSPI_PM_OPS   NULL
 462 +#endif
 463 +
 464 +
 465 +
 466 +static struct platform_driver bcm63xx_hsspi_driver = {
 467 +       .driver = {
 468 +               .name   = "bcm63xx-hsspi",
 469 +               .owner  = THIS_MODULE,
 470 +               .pm     = BCM63XX_HSSPI_PM_OPS,
 471 +       },
 472 +       .probe          = bcm63xx_hsspi_probe,
 473 +       .remove         = __exit_p(bcm63xx_hsspi_remove),
 474 +};
 475 +
 476 +module_platform_driver(bcm63xx_hsspi_driver);
 477 +
 478 +MODULE_ALIAS("platform:bcm63xx_hsspi");
 479 +MODULE_DESCRIPTION("Broadcom BCM63xx HS SPI Controller driver");
 480 +MODULE_AUTHOR("Jonas Gorski <jonas.gorski@gmail.com>");
 481 +MODULE_LICENSE("GPL");