target/linux/brcm63xx/patches-3.2/240-spi.patch

   1 --- a/arch/mips/bcm63xx/cpu.c
   2 +++ b/arch/mips/bcm63xx/cpu.c
   3 @@ -58,6 +58,7 @@ static const unsigned long bcm96338_regs
   4
   5  static const int bcm96338_irqs[] = {
   6         [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
   7 +       [IRQ_SPI]               = BCM_6338_SPI_IRQ,
   8         [IRQ_UART0]             = BCM_6338_UART0_IRQ,
   9         [IRQ_DSL]               = BCM_6338_DSL_IRQ,
  10         [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
  11 @@ -132,6 +133,7 @@ static const unsigned long bcm96348_regs
  12
  13  static const int bcm96348_irqs[] = {
  14         [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
  15 +       [IRQ_SPI]               = BCM_6348_SPI_IRQ,
  16         [IRQ_UART0]             = BCM_6348_UART0_IRQ,
  17         [IRQ_DSL]               = BCM_6348_DSL_IRQ,
  18         [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
  19 @@ -175,6 +177,7 @@ static const unsigned long bcm96358_regs
  20
  21  static const int bcm96358_irqs[] = {
  22         [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
  23 +       [IRQ_SPI]               = BCM_6358_SPI_IRQ,
  24         [IRQ_UART0]             = BCM_6358_UART0_IRQ,
  25         [IRQ_UART1]             = BCM_6358_UART1_IRQ,
  26         [IRQ_DSL]               = BCM_6358_DSL_IRQ,
  27 --- /dev/null
  28 +++ b/arch/mips/bcm63xx/dev-spi.c
  29 @@ -0,0 +1,99 @@
  30 +/*
  31 + * This file is subject to the terms and conditions of the GNU General Public
  32 + * License.  See the file "COPYING" in the main directory of this archive
  33 + * for more details.
  34 + *
  35 + * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org>
  36 + * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
  37 + */
  38 +
  39 +#include <linux/init.h>
  40 +#include <linux/kernel.h>
  41 +#include <linux/platform_device.h>
  42 +#include <linux/export.h>
  43 +
  44 +#include <bcm63xx_cpu.h>
  45 +#include <bcm63xx_dev_spi.h>
  46 +#include <bcm63xx_regs.h>
  47 +
  48 +#ifdef BCMCPU_RUNTIME_DETECT
  49 +/*
  50 + * register offsets
  51 + */
  52 +static const unsigned long bcm96338_regs_spi[] = {
  53 +       __GEN_SPI_REGS_TABLE(6338)
  54 +};
  55 +
  56 +static const unsigned long bcm96348_regs_spi[] = {
  57 +       __GEN_SPI_REGS_TABLE(6348)
  58 +};
  59 +
  60 +static const unsigned long bcm96358_regs_spi[] = {
  61 +       __GEN_SPI_REGS_TABLE(6358)
  62 +};
  63 +
  64 +const unsigned long *bcm63xx_regs_spi;
  65 +EXPORT_SYMBOL(bcm63xx_regs_spi);
  66 +
  67 +static __init void bcm63xx_spi_regs_init(void)
  68 +{
  69 +       if (BCMCPU_IS_6338())
  70 +               bcm63xx_regs_spi = bcm96338_regs_spi;
  71 +       if (BCMCPU_IS_6348())
  72 +               bcm63xx_regs_spi = bcm96348_regs_spi;
  73 +       if (BCMCPU_IS_6358())
  74 +               bcm63xx_regs_spi = bcm96358_regs_spi;
  75 +}
  76 +#else
  77 +static __init void bcm63xx_spi_regs_init(void) { }
  78 +#endif
  79 +
  80 +static struct resource spi_resources[] = {
  81 +       {
  82 +               .start          = -1, /* filled at runtime */
  83 +               .end            = -1, /* filled at runtime */
  84 +               .flags          = IORESOURCE_MEM,
  85 +       },
  86 +       {
  87 +               .start          = -1, /* filled at runtime */
  88 +               .flags          = IORESOURCE_IRQ,
  89 +       },
  90 +};
  91 +
  92 +static struct bcm63xx_spi_pdata spi_pdata = {
  93 +       .bus_num                = 0,
  94 +       .num_chipselect         = 8,
  95 +       .speed_hz               = 50000000,     /* Fclk */
  96 +};
  97 +
  98 +static struct platform_device bcm63xx_spi_device = {
  99 +       .name           = "bcm63xx-spi",
 100 +       .id             = 0,
 101 +       .num_resources  = ARRAY_SIZE(spi_resources),
 102 +       .resource       = spi_resources,
 103 +       .dev            = {
 104 +               .platform_data = &spi_pdata,
 105 +       },
 106 +};
 107 +
 108 +int __init bcm63xx_spi_register(void)
 109 +{
 110 +       spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
 111 +       spi_resources[0].end = spi_resources[0].start;
 112 +       spi_resources[0].end += RSET_SPI_SIZE - 1;
 113 +       spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
 114 +
 115 +       if (BCMCPU_IS_6345())
 116 +               return -ENODEV;
 117 +
 118 +       /* Fill in platform data */
 119 +       if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
 120 +               spi_pdata.fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
 121 +
 122 +       if (BCMCPU_IS_6358())
 123 +               spi_pdata.fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
 124 +
 125 +       bcm63xx_spi_regs_init();
 126 +
 127 +       return platform_device_register(&bcm63xx_spi_device);
 128 +}
 129 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 130 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 131 @@ -109,6 +109,7 @@ enum bcm63xx_regs_set {
 132  #define RSET_WDT_SIZE                  12
 133  #define RSET_ENET_SIZE                 2048
 134  #define RSET_ENETDMA_SIZE              2048
 135 +#define RSET_SPI_SIZE                  256
 136  #define RSET_UART_SIZE                 24
 137  #define RSET_UDC_SIZE                  256
 138  #define RSET_OHCI_SIZE                 256
 139 @@ -214,8 +215,8 @@ enum bcm63xx_regs_set {
 140  #define BCM_6358_UART0_BASE            (0xfffe0100)
 141  #define BCM_6358_UART1_BASE            (0xfffe0120)
 142  #define BCM_6358_GPIO_BASE             (0xfffe0080)
 143 -#define BCM_6358_SPI_BASE              (0xdeadbeef)
 144 -#define BCM_6358_UDC0_BASE             (0xfffe0800)
 145 +#define BCM_6358_SPI_BASE              (0xfffe0800)
 146 +#define BCM_6358_UDC0_BASE             (0xdeadbeef)
 147  #define BCM_6358_OHCI0_BASE            (0xfffe1400)
 148  #define BCM_6358_OHCI_PRIV_BASE                (0xdeadbeef)
 149  #define BCM_6358_USBH_PRIV_BASE                (0xfffe1500)
 150 @@ -441,6 +442,7 @@ static inline unsigned long bcm63xx_regs
 151   */
 152  enum bcm63xx_irq {
 153         IRQ_TIMER = 0,
 154 +       IRQ_SPI,
 155         IRQ_UART0,
 156         IRQ_UART1,
 157         IRQ_DSL,
 158 @@ -506,6 +508,7 @@ enum bcm63xx_irq {
 159   * 6348 irqs
 160   */
 161  #define BCM_6348_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
 162 +#define BCM_6348_SPI_IRQ               (IRQ_INTERNAL_BASE + 1)
 163  #define BCM_6348_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 164  #define BCM_6348_DSL_IRQ               (IRQ_INTERNAL_BASE + 4)
 165  #define BCM_6348_ENET1_IRQ             (IRQ_INTERNAL_BASE + 7)
 166 @@ -523,6 +526,7 @@ enum bcm63xx_irq {
 167   * 6358 irqs
 168   */
 169  #define BCM_6358_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
 170 +#define BCM_6358_SPI_IRQ               (IRQ_INTERNAL_BASE + 1)
 171  #define BCM_6358_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 172  #define BCM_6358_UART1_IRQ             (IRQ_INTERNAL_BASE + 3)
 173  #define BCM_6358_OHCI0_IRQ             (IRQ_INTERNAL_BASE + 5)
 174 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 175 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 176 @@ -804,4 +804,116 @@
 177  #define DMIPSPLLCFG_N2_SHIFT           29
 178  #define DMIPSPLLCFG_N2_MASK            (0x7 << DMIPSPLLCFG_N2_SHIFT)
 179
 180 +/*************************************************************************
 181 + * _REG relative to RSET_SPI
 182 + *************************************************************************/
 183 +
 184 +/* BCM 6338 SPI core */
 185 +#define SPI_BCM_6338_SPI_CMD           0x00    /* 16-bits register */
 186 +#define SPI_BCM_6338_SPI_INT_STATUS    0x02
 187 +#define SPI_BCM_6338_SPI_INT_MASK_ST   0x03
 188 +#define SPI_BCM_6338_SPI_INT_MASK      0x04
 189 +#define SPI_BCM_6338_SPI_ST            0x05
 190 +#define SPI_BCM_6338_SPI_CLK_CFG       0x06
 191 +#define SPI_BCM_6338_SPI_FILL_BYTE     0x07
 192 +#define SPI_BCM_6338_SPI_MSG_TAIL      0x09
 193 +#define SPI_BCM_6338_SPI_RX_TAIL       0x0b
 194 +#define SPI_BCM_6338_SPI_MSG_CTL       0x40
 195 +#define SPI_BCM_6338_SPI_MSG_DATA      0x41
 196 +#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
 197 +#define SPI_BCM_6338_SPI_RX_DATA       0x80
 198 +#define SPI_BCM_6338_SPI_RX_DATA_SIZE  0x3f
 199 +
 200 +/* BCM 6348 SPI core */
 201 +#define SPI_BCM_6348_SPI_CMD           0x00    /* 16-bits register */
 202 +#define SPI_BCM_6348_SPI_INT_STATUS    0x02
 203 +#define SPI_BCM_6348_SPI_INT_MASK_ST   0x03
 204 +#define SPI_BCM_6348_SPI_INT_MASK      0x04
 205 +#define SPI_BCM_6348_SPI_ST            0x05
 206 +#define SPI_BCM_6348_SPI_CLK_CFG       0x06
 207 +#define SPI_BCM_6348_SPI_FILL_BYTE     0x07
 208 +#define SPI_BCM_6348_SPI_MSG_TAIL      0x09
 209 +#define SPI_BCM_6348_SPI_RX_TAIL       0x0b
 210 +#define SPI_BCM_6348_SPI_MSG_CTL       0x40
 211 +#define SPI_BCM_6348_SPI_MSG_DATA      0x41
 212 +#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
 213 +#define SPI_BCM_6348_SPI_RX_DATA       0x80
 214 +#define SPI_BCM_6348_SPI_RX_DATA_SIZE  0x3f
 215 +
 216 +/* BCM 6358 SPI core */
 217 +#define SPI_BCM_6358_SPI_MSG_CTL       0x00    /* 16-bits register */
 218 +
 219 +#define SPI_BCM_6358_SPI_MSG_DATA      0x02
 220 +#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
 221 +
 222 +#define SPI_BCM_6358_SPI_RX_DATA       0x400
 223 +#define SPI_BCM_6358_SPI_RX_DATA_SIZE  0x220
 224 +
 225 +#define SPI_BCM_6358_SPI_CMD           0x700   /* 16-bits register */
 226 +
 227 +#define SPI_BCM_6358_SPI_INT_STATUS    0x702
 228 +#define SPI_BCM_6358_SPI_INT_MASK_ST   0x703
 229 +
 230 +#define SPI_BCM_6358_SPI_INT_MASK      0x704
 231 +
 232 +#define SPI_BCM_6358_SPI_ST            0x705
 233 +
 234 +#define SPI_BCM_6358_SPI_CLK_CFG       0x706
 235 +
 236 +#define SPI_BCM_6358_SPI_FILL_BYTE     0x707
 237 +#define SPI_BCM_6358_SPI_MSG_TAIL      0x709
 238 +#define SPI_BCM_6358_SPI_RX_TAIL       0x70B
 239 +
 240 +/* Shared SPI definitions */
 241 +
 242 +/* Message configuration */
 243 +#define SPI_FD_RW                      0x00
 244 +#define SPI_HD_W                       0x01
 245 +#define SPI_HD_R                       0x02
 246 +#define SPI_BYTE_CNT_SHIFT             0
 247 +#define SPI_MSG_TYPE_SHIFT             14
 248 +
 249 +/* Command */
 250 +#define SPI_CMD_NOOP                   0x00
 251 +#define SPI_CMD_SOFT_RESET             0x01
 252 +#define SPI_CMD_HARD_RESET             0x02
 253 +#define SPI_CMD_START_IMMEDIATE                0x03
 254 +#define SPI_CMD_COMMAND_SHIFT          0
 255 +#define SPI_CMD_COMMAND_MASK           0x000f
 256 +#define SPI_CMD_DEVICE_ID_SHIFT                4
 257 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
 258 +#define SPI_CMD_ONE_BYTE_SHIFT         11
 259 +#define SPI_CMD_ONE_WIRE_SHIFT         12
 260 +#define SPI_DEV_ID_0                   0
 261 +#define SPI_DEV_ID_1                   1
 262 +#define SPI_DEV_ID_2                   2
 263 +#define SPI_DEV_ID_3                   3
 264 +
 265 +/* Interrupt mask */
 266 +#define SPI_INTR_CMD_DONE              0x01
 267 +#define SPI_INTR_RX_OVERFLOW           0x02
 268 +#define SPI_INTR_TX_UNDERFLOW          0x04
 269 +#define SPI_INTR_TX_OVERFLOW           0x08
 270 +#define SPI_INTR_RX_UNDERFLOW          0x10
 271 +#define SPI_INTR_CLEAR_ALL             0x1f
 272 +
 273 +/* Status */
 274 +#define SPI_RX_EMPTY                   0x02
 275 +#define SPI_CMD_BUSY                   0x04
 276 +#define SPI_SERIAL_BUSY                        0x08
 277 +
 278 +/* Clock configuration */
 279 +#define SPI_CLK_20MHZ                  0x00
 280 +#define SPI_CLK_0_391MHZ               0x01
 281 +#define SPI_CLK_0_781MHZ               0x02 /* default */
 282 +#define SPI_CLK_1_563MHZ               0x03
 283 +#define SPI_CLK_3_125MHZ               0x04
 284 +#define SPI_CLK_6_250MHZ               0x05
 285 +#define SPI_CLK_12_50MHZ               0x06
 286 +#define SPI_CLK_25MHZ                  0x07
 287 +#define SPI_CLK_MASK                   0x07
 288 +#define SPI_SSOFFTIME_MASK             0x38
 289 +#define SPI_SSOFFTIME_SHIFT            3
 290 +#define SPI_BYTE_SWAP                  0x80
 291 +
 292  #endif /* BCM63XX_REGS_H_ */
 293 --- /dev/null
 294 +++ b/drivers/spi/bcm63xx_spi.c
 295 @@ -0,0 +1,496 @@
 296 +/*
 297 + * Broadcom BCM63xx SPI controller support
 298 + *
 299 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
 300 + * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
 301 + *
 302 + * This program is free software; you can redistribute it and/or
 303 + * modify it under the terms of the GNU General Public License
 304 + * as published by the Free Software Foundation; either version 2
 305 + * of the License, or (at your option) any later version.
 306 + *
 307 + * This program is distributed in the hope that it will be useful,
 308 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 309 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 310 + * GNU General Public License for more details.
 311 + *
 312 + * You should have received a copy of the GNU General Public License
 313 + * along with this program; if not, write to the
 314 + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
 315 + */
 316 +
 317 +#include <linux/kernel.h>
 318 +#include <linux/init.h>
 319 +#include <linux/clk.h>
 320 +#include <linux/module.h>
 321 +#include <linux/platform_device.h>
 322 +#include <linux/delay.h>
 323 +#include <linux/interrupt.h>
 324 +#include <linux/spi/spi.h>
 325 +#include <linux/completion.h>
 326 +#include <linux/err.h>
 327 +
 328 +#include <bcm63xx_dev_spi.h>
 329 +
 330 +#define PFX            KBUILD_MODNAME
 331 +#define DRV_VER                "0.1.2"
 332 +
 333 +struct bcm63xx_spi {
 334 +       spinlock_t              lock;
 335 +       int                     stopping;
 336 +        struct completion      done;
 337 +
 338 +       void __iomem            *regs;
 339 +       int                     irq;
 340 +
 341 +       /* Platform data */
 342 +        u32                    speed_hz;
 343 +       unsigned                fifo_size;
 344 +
 345 +       /* Data buffers */
 346 +       const unsigned char     *tx_ptr;
 347 +       unsigned char           *rx_ptr;
 348 +
 349 +       /* data iomem */
 350 +       u8 __iomem              *tx_io;
 351 +       const u8 __iomem        *rx_io;
 352 +
 353 +       int                     remaining_bytes;
 354 +
 355 +       struct clk              *clk;
 356 +       struct platform_device  *pdev;
 357 +};
 358 +
 359 +static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
 360 +                               unsigned int offset)
 361 +{
 362 +       return bcm_readw(bs->regs + bcm63xx_spireg(offset));
 363 +}
 364 +
 365 +static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
 366 +                               unsigned int offset)
 367 +{
 368 +       return bcm_readw(bs->regs + bcm63xx_spireg(offset));
 369 +}
 370 +
 371 +static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
 372 +                                 u8 value, unsigned int offset)
 373 +{
 374 +       bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
 375 +}
 376 +
 377 +static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
 378 +                                 u16 value, unsigned int offset)
 379 +{
 380 +       bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
 381 +}
 382 +
 383 +static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
 384 +                                     struct spi_transfer *t)
 385 +{
 386 +       u8 bits_per_word;
 387 +       u8 clk_cfg;
 388 +       u32 hz;
 389 +       unsigned int div;
 390 +
 391 +       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 392 +
 393 +       bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
 394 +       hz = (t) ? t->speed_hz : spi->max_speed_hz;
 395 +       if (bits_per_word != 8) {
 396 +               dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
 397 +                       __func__, bits_per_word);
 398 +               return -EINVAL;
 399 +        }
 400 +
 401 +       if (spi->chip_select > spi->master->num_chipselect) {
 402 +               dev_err(&spi->dev, "%s, unsupported slave %d\n",
 403 +                       __func__, spi->chip_select);
 404 +               return -EINVAL;
 405 +       }
 406 +
 407 +       /* Check clock setting */
 408 +       div = (bs->speed_hz / hz);
 409 +       switch (div) {
 410 +       case 2:
 411 +               clk_cfg = SPI_CLK_25MHZ;
 412 +               break;
 413 +       case 4:
 414 +               clk_cfg = SPI_CLK_12_50MHZ;
 415 +               break;
 416 +       case 8:
 417 +               clk_cfg = SPI_CLK_6_250MHZ;
 418 +               break;
 419 +       case 16:
 420 +               clk_cfg = SPI_CLK_3_125MHZ;
 421 +               break;
 422 +       case 32:
 423 +               clk_cfg = SPI_CLK_1_563MHZ;
 424 +               break;
 425 +       case 64:
 426 +               clk_cfg = SPI_CLK_0_781MHZ;
 427 +               break;
 428 +       case 128:
 429 +       default:
 430 +               /* Set to slowest mode for compatibility */
 431 +               clk_cfg = SPI_CLK_0_391MHZ;
 432 +               break;
 433 +       }
 434 +
 435 +       bcm_spi_writeb(bs, clk_cfg, SPI_CLK_CFG);
 436 +       dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
 437 +               div, hz, clk_cfg);
 438 +
 439 +       return 0;
 440 +}
 441 +
 442 +/* the spi->mode bits understood by this driver: */
 443 +#define MODEBITS (SPI_CPOL | SPI_CPHA)
 444 +
 445 +static int bcm63xx_spi_setup(struct spi_device *spi)
 446 +{
 447 +       struct bcm63xx_spi *bs;
 448 +       int ret;
 449 +
 450 +       bs = spi_master_get_devdata(spi->master);
 451 +
 452 +       if (bs->stopping)
 453 +               return -ESHUTDOWN;
 454 +
 455 +       if (!spi->bits_per_word)
 456 +               spi->bits_per_word = 8;
 457 +
 458 +       if (spi->mode & ~MODEBITS) {
 459 +               dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
 460 +                       __func__, spi->mode & ~MODEBITS);
 461 +               return -EINVAL;
 462 +       }
 463 +
 464 +       ret = bcm63xx_spi_setup_transfer(spi, NULL);
 465 +       if (ret < 0) {
 466 +               dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
 467 +                       spi->mode & ~MODEBITS);
 468 +               return ret;
 469 +       }
 470 +
 471 +       dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
 472 +               __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
 473 +
 474 +       return 0;
 475 +}
 476 +
 477 +/* Fill the TX FIFO with as many bytes as possible */
 478 +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
 479 +{
 480 +       u8 size;
 481 +
 482 +        /* Fill the Tx FIFO with as many bytes as possible */
 483 +       size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :
 484 +               bs->fifo_size;
 485 +       memcpy_toio(bs->tx_io, bs->tx_ptr, size);
 486 +       bs->remaining_bytes -= size;
 487 +}
 488 +
 489 +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 490 +{
 491 +       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 492 +       u16 msg_ctl;
 493 +       u16 cmd;
 494 +
 495 +       dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 496 +               t->tx_buf, t->rx_buf, t->len);
 497 +
 498 +       /* Transmitter is inhibited */
 499 +       bs->tx_ptr = t->tx_buf;
 500 +       bs->rx_ptr = t->rx_buf;
 501 +       init_completion(&bs->done);
 502 +
 503 +       if (t->tx_buf) {
 504 +               bs->remaining_bytes = t->len;
 505 +               bcm63xx_spi_fill_tx_fifo(bs);
 506 +       }
 507 +
 508 +       /* Enable the command done interrupt which
 509 +        * we use to determine completion of a command */
 510 +       bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 511 +
 512 +       /* Fill in the Message control register */
 513 +       msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
 514 +
 515 +       if (t->rx_buf && t->tx_buf)
 516 +               msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
 517 +       else if (t->rx_buf)
 518 +               msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
 519 +       else if (t->tx_buf)
 520 +               msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
 521 +
 522 +       bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
 523 +
 524 +       /* Issue the transfer */
 525 +       cmd = SPI_CMD_START_IMMEDIATE;
 526 +       cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 527 +       cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
 528 +       bcm_spi_writew(bs, cmd, SPI_CMD);
 529 +       wait_for_completion(&bs->done);
 530 +
 531 +       /* Disable the CMD_DONE interrupt */
 532 +       bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 533 +
 534 +       return t->len - bs->remaining_bytes;
 535 +}
 536 +
 537 +static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m)
 538 +{
 539 +       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 540 +       struct spi_transfer *t;
 541 +       int ret = 0;
 542 +
 543 +       if (unlikely(list_empty(&m->transfers)))
 544 +               return -EINVAL;
 545 +
 546 +       if (bs->stopping)
 547 +               return -ESHUTDOWN;
 548 +
 549 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 550 +               ret += bcm63xx_txrx_bufs(spi, t);
 551 +       }
 552 +
 553 +       m->complete(m->context);
 554 +
 555 +       return ret;
 556 +}
 557 +
 558 +/* This driver supports single master mode only. Hence
 559 + * CMD_DONE is the only interrupt we care about
 560 + */
 561 +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
 562 +{
 563 +       struct spi_master *master = (struct spi_master *)dev_id;
 564 +       struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 565 +       u8 intr;
 566 +       u16 cmd;
 567 +
 568 +       /* Read interupts and clear them immediately */
 569 +       intr = bcm_spi_readb(bs, SPI_INT_STATUS);
 570 +       bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 571 +       bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 572 +
 573 +       /* A tansfer completed */
 574 +       if (intr & SPI_INTR_CMD_DONE) {
 575 +               u8 rx_tail;
 576 +
 577 +               rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
 578 +
 579 +               /* Read out all the data */
 580 +               if (rx_tail)
 581 +                       memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
 582 +
 583 +               /* See if there is more data to send */
 584 +               if (bs->remaining_bytes > 0) {
 585 +                       bcm63xx_spi_fill_tx_fifo(bs);
 586 +
 587 +                       /* Start the transfer */
 588 +                       bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT,
 589 +                                      SPI_MSG_CTL);
 590 +                       cmd = bcm_spi_readw(bs, SPI_CMD);
 591 +                       cmd |= SPI_CMD_START_IMMEDIATE;
 592 +                       cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 593 +                       bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 594 +                       bcm_spi_writew(bs, cmd, SPI_CMD);
 595 +               } else {
 596 +                       complete(&bs->done);
 597 +               }
 598 +       }
 599 +
 600 +       return IRQ_HANDLED;
 601 +}
 602 +
 603 +
 604 +static int __init bcm63xx_spi_probe(struct platform_device *pdev)
 605 +{
 606 +       struct resource *r;
 607 +       struct device *dev = &pdev->dev;
 608 +       struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
 609 +       int irq;
 610 +       struct spi_master *master;
 611 +       struct clk *clk;
 612 +       struct bcm63xx_spi *bs;
 613 +       int ret;
 614 +
 615 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 616 +       if (!r) {
 617 +               dev_err(dev, "no iomem\n");
 618 +               ret = -ENXIO;
 619 +               goto out;
 620 +       }
 621 +
 622 +       irq = platform_get_irq(pdev, 0);
 623 +       if (irq < 0) {
 624 +               dev_err(dev, "no irq\n");
 625 +               ret = -ENXIO;
 626 +               goto out;
 627 +       }
 628 +
 629 +       clk = clk_get(dev, "spi");
 630 +       if (IS_ERR(clk)) {
 631 +               dev_err(dev, "no clock for device\n");
 632 +               ret = -ENODEV;
 633 +               goto out;
 634 +       }
 635 +
 636 +       master = spi_alloc_master(dev, sizeof(*bs));
 637 +       if (!master) {
 638 +               dev_err(dev, "out of memory\n");
 639 +               ret = -ENOMEM;
 640 +               goto out_free;
 641 +       }
 642 +
 643 +       bs = spi_master_get_devdata(master);
 644 +       init_completion(&bs->done);
 645 +
 646 +       platform_set_drvdata(pdev, master);
 647 +       bs->pdev = pdev;
 648 +
 649 +       if (!request_mem_region(r->start, r->end - r->start, PFX)) {
 650 +               dev_err(dev, "iomem request failed\n");
 651 +               ret = -ENXIO;
 652 +               goto out_put_master;
 653 +       }
 654 +
 655 +       bs->regs = ioremap_nocache(r->start, r->end - r->start);
 656 +       if (!bs->regs) {
 657 +               dev_err(dev, "unable to ioremap regs\n");
 658 +               ret = -ENOMEM;
 659 +               goto out_put_master;
 660 +       }
 661 +       bs->irq = irq;
 662 +       bs->clk = clk;
 663 +       bs->fifo_size = pdata->fifo_size;
 664 +
 665 +       ret = request_irq(irq, bcm63xx_spi_interrupt, 0, pdev->name, master);
 666 +       if (ret) {
 667 +               dev_err(dev, "unable to request irq\n");
 668 +               goto out_unmap;
 669 +       }
 670 +
 671 +       master->bus_num = pdata->bus_num;
 672 +       master->num_chipselect = pdata->num_chipselect;
 673 +       master->setup = bcm63xx_spi_setup;
 674 +       master->transfer = bcm63xx_transfer;
 675 +       bs->speed_hz = pdata->speed_hz;
 676 +       bs->stopping = 0;
 677 +       bs->tx_io = (u8*)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
 678 +       bs->rx_io = (const u8*)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
 679 +       spin_lock_init(&bs->lock);
 680 +
 681 +       /* Initialize hardware */
 682 +       clk_enable(bs->clk);
 683 +       bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 684 +
 685 +       /* register and we are done */
 686 +       ret = spi_register_master(master);
 687 +       if (ret) {
 688 +               dev_err(dev, "spi register failed\n");
 689 +               goto out_reset_hw;
 690 +       }
 691 +
 692 +       dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
 693 +                r->start, irq, bs->fifo_size, DRV_VER);
 694 +
 695 +       return 0;
 696 +
 697 +out_reset_hw:
 698 +       clk_disable(clk);
 699 +       free_irq(irq, master);
 700 +out_unmap:
 701 +       iounmap(bs->regs);
 702 +out_put_master:
 703 +       spi_master_put(master);
 704 +out_free:
 705 +       clk_put(clk);
 706 +out:
 707 +       return ret;
 708 +}
 709 +
 710 +static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
 711 +{
 712 +       struct spi_master       *master = platform_get_drvdata(pdev);
 713 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 714 +       struct resource         *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 715 +
 716 +       /* reset spi block */
 717 +       bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 718 +       spin_lock(&bs->lock);
 719 +       bs->stopping = 1;
 720 +
 721 +       /* HW shutdown */
 722 +       clk_disable(bs->clk);
 723 +       clk_put(bs->clk);
 724 +
 725 +       spin_unlock(&bs->lock);
 726 +
 727 +       free_irq(bs->irq, master);
 728 +       iounmap(bs->regs);
 729 +       release_mem_region(r->start, r->end - r->start);
 730 +       platform_set_drvdata(pdev, 0);
 731 +       spi_unregister_master(master);
 732 +
 733 +       return 0;
 734 +}
 735 +
 736 +#ifdef CONFIG_PM
 737 +static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
 738 +{
 739 +       struct spi_master       *master = platform_get_drvdata(pdev);
 740 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 741 +
 742 +        clk_disable(bs->clk);
 743 +
 744 +       return 0;
 745 +}
 746 +
 747 +static int bcm63xx_spi_resume(struct platform_device *pdev)
 748 +{
 749 +       struct spi_master       *master = platform_get_drvdata(pdev);
 750 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 751 +
 752 +       clk_enable(bs->clk);
 753 +
 754 +       return 0;
 755 +}
 756 +#else
 757 +#define bcm63xx_spi_suspend    NULL
 758 +#define bcm63xx_spi_resume     NULL
 759 +#endif
 760 +
 761 +static struct platform_driver bcm63xx_spi_driver = {
 762 +       .driver = {
 763 +               .name   = "bcm63xx-spi",
 764 +               .owner  = THIS_MODULE,
 765 +       },
 766 +       .probe          = bcm63xx_spi_probe,
 767 +       .remove         = __exit_p(bcm63xx_spi_remove),
 768 +       .suspend        = bcm63xx_spi_suspend,
 769 +       .resume         = bcm63xx_spi_resume,
 770 +};
 771 +
 772 +
 773 +static int __init bcm63xx_spi_init(void)
 774 +{
 775 +       return platform_driver_register(&bcm63xx_spi_driver);
 776 +}
 777 +
 778 +static void __exit bcm63xx_spi_exit(void)
 779 +{
 780 +       platform_driver_unregister(&bcm63xx_spi_driver);
 781 +}
 782 +
 783 +module_init(bcm63xx_spi_init);
 784 +module_exit(bcm63xx_spi_exit);
 785 +
 786 +MODULE_ALIAS("platform:bcm63xx_spi");
 787 +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 788 +MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
 789 +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
 790 +MODULE_LICENSE("GPL");
 791 +MODULE_VERSION(DRV_VER);
 792 --- a/drivers/spi/Kconfig
 793 +++ b/drivers/spi/Kconfig
 794 @@ -74,6 +74,12 @@ config SPI_ATMEL
 795           This selects a driver for the Atmel SPI Controller, present on
 796           many AT32 (AVR32) and AT91 (ARM) chips.
 797
 798 +config SPI_BCM63XX
 799 +       tristate "Broadcom BCM63xx SPI controller"
 800 +       depends on BCM63XX
 801 +       help
 802 +         This is the SPI controller master driver for Broadcom BCM63xx SoC.
 803 +
 804  config SPI_BFIN
 805         tristate "SPI controller driver for ADI Blackfin5xx"
 806         depends on BLACKFIN
 807 --- a/drivers/spi/Makefile
 808 +++ b/drivers/spi/Makefile
 809 @@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_ALTERA)              += spi-altera.
 810  obj-$(CONFIG_SPI_ATMEL)                        += spi-atmel.o
 811  obj-$(CONFIG_SPI_ATH79)                        += spi-ath79.o
 812  obj-$(CONFIG_SPI_AU1550)               += spi-au1550.o
 813 +obj-$(CONFIG_SPI_BCM63XX)              += bcm63xx_spi.o
 814  obj-$(CONFIG_SPI_BFIN)                 += spi-bfin5xx.o
 815  obj-$(CONFIG_SPI_BFIN_SPORT)           += spi-bfin-sport.o
 816  obj-$(CONFIG_SPI_BITBANG)              += spi-bitbang.o
 817 --- /dev/null
 818 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
 819 @@ -0,0 +1,85 @@
 820 +#ifndef BCM63XX_DEV_SPI_H
 821 +#define BCM63XX_DEV_SPI_H
 822 +
 823 +#include <linux/types.h>
 824 +#include <bcm63xx_io.h>
 825 +#include <bcm63xx_regs.h>
 826 +
 827 +int __init bcm63xx_spi_register(void);
 828 +
 829 +struct bcm63xx_spi_pdata {
 830 +       unsigned int    fifo_size;
 831 +       int             bus_num;
 832 +       int             num_chipselect;
 833 +       u32             speed_hz;
 834 +};
 835 +
 836 +enum bcm63xx_regs_spi {
 837 +        SPI_CMD,
 838 +        SPI_INT_STATUS,
 839 +        SPI_INT_MASK_ST,
 840 +        SPI_INT_MASK,
 841 +        SPI_ST,
 842 +        SPI_CLK_CFG,
 843 +        SPI_FILL_BYTE,
 844 +        SPI_MSG_TAIL,
 845 +        SPI_RX_TAIL,
 846 +        SPI_MSG_CTL,
 847 +        SPI_MSG_DATA,
 848 +        SPI_RX_DATA,
 849 +};
 850 +
 851 +#define __GEN_SPI_RSET_BASE(__cpu, __rset)                             \
 852 +       case SPI_## __rset:                                             \
 853 +               return SPI_BCM_## __cpu ##_SPI_## __rset;
 854 +
 855 +#define __GEN_SPI_RSET(__cpu)                                          \
 856 +       switch (reg) {                                                  \
 857 +       __GEN_SPI_RSET_BASE(__cpu, CMD)                                 \
 858 +       __GEN_SPI_RSET_BASE(__cpu, INT_STATUS)                          \
 859 +       __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST)                         \
 860 +       __GEN_SPI_RSET_BASE(__cpu, INT_MASK)                            \
 861 +       __GEN_SPI_RSET_BASE(__cpu, ST)                                  \
 862 +       __GEN_SPI_RSET_BASE(__cpu, CLK_CFG)                             \
 863 +       __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE)                           \
 864 +       __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL)                            \
 865 +       __GEN_SPI_RSET_BASE(__cpu, RX_TAIL)                             \
 866 +       __GEN_SPI_RSET_BASE(__cpu, MSG_CTL)                             \
 867 +       __GEN_SPI_RSET_BASE(__cpu, MSG_DATA)                            \
 868 +       __GEN_SPI_RSET_BASE(__cpu, RX_DATA)                             \
 869 +       }
 870 +
 871 +#define __GEN_SPI_REGS_TABLE(__cpu)                                    \
 872 +       [SPI_CMD]               = SPI_BCM_## __cpu ##_SPI_CMD,          \
 873 +       [SPI_INT_STATUS]        = SPI_BCM_## __cpu ##_SPI_INT_STATUS,   \
 874 +       [SPI_INT_MASK_ST]       = SPI_BCM_## __cpu ##_SPI_INT_MASK_ST,  \
 875 +       [SPI_INT_MASK]          = SPI_BCM_## __cpu ##_SPI_INT_MASK,     \
 876 +       [SPI_ST]                = SPI_BCM_## __cpu ##_SPI_ST,           \
 877 +       [SPI_CLK_CFG]           = SPI_BCM_## __cpu ##_SPI_CLK_CFG,      \
 878 +       [SPI_FILL_BYTE]         = SPI_BCM_## __cpu ##_SPI_FILL_BYTE,    \
 879 +       [SPI_MSG_TAIL]          = SPI_BCM_## __cpu ##_SPI_MSG_TAIL,     \
 880 +       [SPI_RX_TAIL]           = SPI_BCM_## __cpu ##_SPI_RX_TAIL,      \
 881 +       [SPI_MSG_CTL]           = SPI_BCM_## __cpu ##_SPI_MSG_CTL,      \
 882 +       [SPI_MSG_DATA]          = SPI_BCM_## __cpu ##_SPI_MSG_DATA,     \
 883 +       [SPI_RX_DATA]           = SPI_BCM_## __cpu ##_SPI_RX_DATA,
 884 +
 885 +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
 886 +{
 887 +#ifdef BCMCPU_RUNTIME_DETECT
 888 +       extern const unsigned long *bcm63xx_regs_spi;
 889 +        return bcm63xx_regs_spi[reg];
 890 +#else
 891 +#ifdef CONFIG_BCM63XX_CPU_6338
 892 +       __GEN_SPI_RSET(6338)
 893 +#endif
 894 +#ifdef CONFIG_BCM63XX_CPU_6348
 895 +       __GEN_SPI_RSET(6348)
 896 +#endif
 897 +#ifdef CONFIG_BCM63XX_CPU_6358
 898 +       __GEN_SPI_RSET(6358)
 899 +#endif
 900 +#endif
 901 +       return 0;
 902 +}
 903 +
 904 +#endif /* BCM63XX_DEV_SPI_H */
 905 --- a/arch/mips/bcm63xx/Makefile
 906 +++ b/arch/mips/bcm63xx/Makefile
 907 @@ -1,6 +1,6 @@
 908  obj-y          += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
 909                    dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o \
 910 -                  dev-usb-ohci.o dev-usb-ehci.o
 911 +                  dev-usb-ohci.o dev-usb-ehci.o dev-spi.o
 912  obj-$(CONFIG_EARLY_PRINTK)     += early_printk.o
 913
 914  obj-y          += boards/
 915 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
 916 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
 917 @@ -30,6 +30,7 @@
 918  #include <bcm63xx_dev_pcmcia.h>
 919  #include <bcm63xx_dev_usb_ohci.h>
 920  #include <bcm63xx_dev_usb_ehci.h>
 921 +#include <bcm63xx_dev_spi.h>
 922  #include <board_bcm963xx.h>
 923
 924  #define PFX    "board_bcm963xx: "
 925 @@ -928,6 +929,8 @@ int __init board_register_devices(void)
 926         if (board.num_spis)
 927                 spi_register_board_info(board.spis, board.num_spis);
 928
 929 +       bcm63xx_spi_register();
 930 +
 931         /* read base address of boot chip select (0) */
 932         val = bcm_mpi_readl(MPI_CSBASE_REG(0));
 933         val &= MPI_CSBASE_BASE_MASK;