target/linux/brcm63xx/patches-3.0/240-spi.patch

   1 --- a/arch/mips/bcm63xx/cpu.c
   2 +++ b/arch/mips/bcm63xx/cpu.c
   3 @@ -58,6 +58,7 @@ static const unsigned long bcm96338_regs
   4
   5  static const int bcm96338_irqs[] = {
   6         [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
   7 +       [IRQ_SPI]               = BCM_6338_SPI_IRQ,
   8         [IRQ_UART0]             = BCM_6338_UART0_IRQ,
   9         [IRQ_DSL]               = BCM_6338_DSL_IRQ,
  10         [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
  11 @@ -132,6 +133,7 @@ static const unsigned long bcm96348_regs
  12
  13  static const int bcm96348_irqs[] = {
  14         [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
  15 +       [IRQ_SPI]               = BCM_6348_SPI_IRQ,
  16         [IRQ_UART0]             = BCM_6348_UART0_IRQ,
  17         [IRQ_DSL]               = BCM_6348_DSL_IRQ,
  18         [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
  19 @@ -175,6 +177,7 @@ static const unsigned long bcm96358_regs
  20
  21  static const int bcm96358_irqs[] = {
  22         [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
  23 +       [IRQ_SPI]               = BCM_6358_SPI_IRQ,
  24         [IRQ_UART0]             = BCM_6358_UART0_IRQ,
  25         [IRQ_UART1]             = BCM_6358_UART1_IRQ,
  26         [IRQ_DSL]               = BCM_6358_DSL_IRQ,
  27 --- /dev/null
  28 +++ b/arch/mips/bcm63xx/dev-spi.c
  29 @@ -0,0 +1,98 @@
  30 +/*
  31 + * This file is subject to the terms and conditions of the GNU General Public
  32 + * License.  See the file "COPYING" in the main directory of this archive
  33 + * for more details.
  34 + *
  35 + * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org>
  36 + * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
  37 + */
  38 +
  39 +#include <linux/init.h>
  40 +#include <linux/kernel.h>
  41 +#include <linux/platform_device.h>
  42 +
  43 +#include <bcm63xx_cpu.h>
  44 +#include <bcm63xx_dev_spi.h>
  45 +#include <bcm63xx_regs.h>
  46 +
  47 +#ifdef BCMCPU_RUNTIME_DETECT
  48 +/*
  49 + * register offsets
  50 + */
  51 +static const unsigned long bcm96338_regs_spi[] = {
  52 +       __GEN_SPI_REGS_TABLE(6338)
  53 +};
  54 +
  55 +static const unsigned long bcm96348_regs_spi[] = {
  56 +       __GEN_SPI_REGS_TABLE(6348)
  57 +};
  58 +
  59 +static const unsigned long bcm96358_regs_spi[] = {
  60 +       __GEN_SPI_REGS_TABLE(6358)
  61 +};
  62 +
  63 +const unsigned long *bcm63xx_regs_spi;
  64 +EXPORT_SYMBOL(bcm63xx_regs_spi);
  65 +
  66 +static __init void bcm63xx_spi_regs_init(void)
  67 +{
  68 +       if (BCMCPU_IS_6338())
  69 +               bcm63xx_regs_spi = bcm96338_regs_spi;
  70 +       if (BCMCPU_IS_6348())
  71 +               bcm63xx_regs_spi = bcm96348_regs_spi;
  72 +       if (BCMCPU_IS_6358())
  73 +               bcm63xx_regs_spi = bcm96358_regs_spi;
  74 +}
  75 +#else
  76 +static __init void bcm63xx_spi_regs_init(void) { }
  77 +#endif
  78 +
  79 +static struct resource spi_resources[] = {
  80 +       {
  81 +               .start          = -1, /* filled at runtime */
  82 +               .end            = -1, /* filled at runtime */
  83 +               .flags          = IORESOURCE_MEM,
  84 +       },
  85 +       {
  86 +               .start          = -1, /* filled at runtime */
  87 +               .flags          = IORESOURCE_IRQ,
  88 +       },
  89 +};
  90 +
  91 +static struct bcm63xx_spi_pdata spi_pdata = {
  92 +       .bus_num                = 0,
  93 +       .num_chipselect         = 8,
  94 +       .speed_hz               = 50000000,     /* Fclk */
  95 +};
  96 +
  97 +static struct platform_device bcm63xx_spi_device = {
  98 +       .name           = "bcm63xx-spi",
  99 +       .id             = 0,
 100 +       .num_resources  = ARRAY_SIZE(spi_resources),
 101 +       .resource       = spi_resources,
 102 +       .dev            = {
 103 +               .platform_data = &spi_pdata,
 104 +       },
 105 +};
 106 +
 107 +int __init bcm63xx_spi_register(void)
 108 +{
 109 +       spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
 110 +       spi_resources[0].end = spi_resources[0].start;
 111 +       spi_resources[0].end += RSET_SPI_SIZE - 1;
 112 +       spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
 113 +
 114 +       if (BCMCPU_IS_6345())
 115 +               return -ENODEV;
 116 +
 117 +       /* Fill in platform data */
 118 +       if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
 119 +               spi_pdata.fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
 120 +
 121 +       if (BCMCPU_IS_6358())
 122 +               spi_pdata.fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
 123 +
 124 +       bcm63xx_spi_regs_init();
 125 +
 126 +       return platform_device_register(&bcm63xx_spi_device);
 127 +}
 128 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 129 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 130 @@ -109,6 +109,7 @@ enum bcm63xx_regs_set {
 131  #define RSET_WDT_SIZE                  12
 132  #define RSET_ENET_SIZE                 2048
 133  #define RSET_ENETDMA_SIZE              2048
 134 +#define RSET_SPI_SIZE                  256
 135  #define RSET_UART_SIZE                 24
 136  #define RSET_UDC_SIZE                  256
 137  #define RSET_OHCI_SIZE                 256
 138 @@ -214,8 +215,8 @@ enum bcm63xx_regs_set {
 139  #define BCM_6358_UART0_BASE            (0xfffe0100)
 140  #define BCM_6358_UART1_BASE            (0xfffe0120)
 141  #define BCM_6358_GPIO_BASE             (0xfffe0080)
 142 -#define BCM_6358_SPI_BASE              (0xdeadbeef)
 143 -#define BCM_6358_UDC0_BASE             (0xfffe0800)
 144 +#define BCM_6358_SPI_BASE              (0xfffe0800)
 145 +#define BCM_6358_UDC0_BASE             (0xdeadbeef)
 146  #define BCM_6358_OHCI0_BASE            (0xfffe1400)
 147  #define BCM_6358_OHCI_PRIV_BASE                (0xdeadbeef)
 148  #define BCM_6358_USBH_PRIV_BASE                (0xfffe1500)
 149 @@ -441,6 +442,7 @@ static inline unsigned long bcm63xx_regs
 150   */
 151  enum bcm63xx_irq {
 152         IRQ_TIMER = 0,
 153 +       IRQ_SPI,
 154         IRQ_UART0,
 155         IRQ_UART1,
 156         IRQ_DSL,
 157 @@ -506,6 +508,7 @@ enum bcm63xx_irq {
 158   * 6348 irqs
 159   */
 160  #define BCM_6348_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
 161 +#define BCM_6348_SPI_IRQ               (IRQ_INTERNAL_BASE + 1)
 162  #define BCM_6348_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 163  #define BCM_6348_DSL_IRQ               (IRQ_INTERNAL_BASE + 4)
 164  #define BCM_6348_ENET1_IRQ             (IRQ_INTERNAL_BASE + 7)
 165 @@ -523,6 +526,7 @@ enum bcm63xx_irq {
 166   * 6358 irqs
 167   */
 168  #define BCM_6358_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
 169 +#define BCM_6358_SPI_IRQ               (IRQ_INTERNAL_BASE + 1)
 170  #define BCM_6358_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 171  #define BCM_6358_UART1_IRQ             (IRQ_INTERNAL_BASE + 3)
 172  #define BCM_6358_OHCI0_IRQ             (IRQ_INTERNAL_BASE + 5)
 173 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 174 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 175 @@ -805,4 +805,116 @@
 176  #define DMIPSPLLCFG_N2_SHIFT           29
 177  #define DMIPSPLLCFG_N2_MASK            (0x7 << DMIPSPLLCFG_N2_SHIFT)
 178
 179 +/*************************************************************************
 180 + * _REG relative to RSET_SPI
 181 + *************************************************************************/
 182 +
 183 +/* BCM 6338 SPI core */
 184 +#define SPI_BCM_6338_SPI_CMD           0x00    /* 16-bits register */
 185 +#define SPI_BCM_6338_SPI_INT_STATUS    0x02
 186 +#define SPI_BCM_6338_SPI_INT_MASK_ST   0x03
 187 +#define SPI_BCM_6338_SPI_INT_MASK      0x04
 188 +#define SPI_BCM_6338_SPI_ST            0x05
 189 +#define SPI_BCM_6338_SPI_CLK_CFG       0x06
 190 +#define SPI_BCM_6338_SPI_FILL_BYTE     0x07
 191 +#define SPI_BCM_6338_SPI_MSG_TAIL      0x09
 192 +#define SPI_BCM_6338_SPI_RX_TAIL       0x0b
 193 +#define SPI_BCM_6338_SPI_MSG_CTL       0x40
 194 +#define SPI_BCM_6338_SPI_MSG_DATA      0x41
 195 +#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
 196 +#define SPI_BCM_6338_SPI_RX_DATA       0x80
 197 +#define SPI_BCM_6338_SPI_RX_DATA_SIZE  0x3f
 198 +
 199 +/* BCM 6348 SPI core */
 200 +#define SPI_BCM_6348_SPI_CMD           0x00    /* 16-bits register */
 201 +#define SPI_BCM_6348_SPI_INT_STATUS    0x02
 202 +#define SPI_BCM_6348_SPI_INT_MASK_ST   0x03
 203 +#define SPI_BCM_6348_SPI_INT_MASK      0x04
 204 +#define SPI_BCM_6348_SPI_ST            0x05
 205 +#define SPI_BCM_6348_SPI_CLK_CFG       0x06
 206 +#define SPI_BCM_6348_SPI_FILL_BYTE     0x07
 207 +#define SPI_BCM_6348_SPI_MSG_TAIL      0x09
 208 +#define SPI_BCM_6348_SPI_RX_TAIL       0x0b
 209 +#define SPI_BCM_6348_SPI_MSG_CTL       0x40
 210 +#define SPI_BCM_6348_SPI_MSG_DATA      0x41
 211 +#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
 212 +#define SPI_BCM_6348_SPI_RX_DATA       0x80
 213 +#define SPI_BCM_6348_SPI_RX_DATA_SIZE  0x3f
 214 +
 215 +/* BCM 6358 SPI core */
 216 +#define SPI_BCM_6358_SPI_MSG_CTL       0x00    /* 16-bits register */
 217 +
 218 +#define SPI_BCM_6358_SPI_MSG_DATA      0x02
 219 +#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
 220 +
 221 +#define SPI_BCM_6358_SPI_RX_DATA       0x400
 222 +#define SPI_BCM_6358_SPI_RX_DATA_SIZE  0x220
 223 +
 224 +#define SPI_BCM_6358_SPI_CMD           0x700   /* 16-bits register */
 225 +
 226 +#define SPI_BCM_6358_SPI_INT_STATUS    0x702
 227 +#define SPI_BCM_6358_SPI_INT_MASK_ST   0x703
 228 +
 229 +#define SPI_BCM_6358_SPI_INT_MASK      0x704
 230 +
 231 +#define SPI_BCM_6358_SPI_ST            0x705
 232 +
 233 +#define SPI_BCM_6358_SPI_CLK_CFG       0x706
 234 +
 235 +#define SPI_BCM_6358_SPI_FILL_BYTE     0x707
 236 +#define SPI_BCM_6358_SPI_MSG_TAIL      0x709
 237 +#define SPI_BCM_6358_SPI_RX_TAIL       0x70B
 238 +
 239 +/* Shared SPI definitions */
 240 +
 241 +/* Message configuration */
 242 +#define SPI_FD_RW                      0x00
 243 +#define SPI_HD_W                       0x01
 244 +#define SPI_HD_R                       0x02
 245 +#define SPI_BYTE_CNT_SHIFT             0
 246 +#define SPI_MSG_TYPE_SHIFT             14
 247 +
 248 +/* Command */
 249 +#define SPI_CMD_NOOP                   0x00
 250 +#define SPI_CMD_SOFT_RESET             0x01
 251 +#define SPI_CMD_HARD_RESET             0x02
 252 +#define SPI_CMD_START_IMMEDIATE                0x03
 253 +#define SPI_CMD_COMMAND_SHIFT          0
 254 +#define SPI_CMD_COMMAND_MASK           0x000f
 255 +#define SPI_CMD_DEVICE_ID_SHIFT                4
 256 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
 257 +#define SPI_CMD_ONE_BYTE_SHIFT         11
 258 +#define SPI_CMD_ONE_WIRE_SHIFT         12
 259 +#define SPI_DEV_ID_0                   0
 260 +#define SPI_DEV_ID_1                   1
 261 +#define SPI_DEV_ID_2                   2
 262 +#define SPI_DEV_ID_3                   3
 263 +
 264 +/* Interrupt mask */
 265 +#define SPI_INTR_CMD_DONE              0x01
 266 +#define SPI_INTR_RX_OVERFLOW           0x02
 267 +#define SPI_INTR_TX_UNDERFLOW          0x04
 268 +#define SPI_INTR_TX_OVERFLOW           0x08
 269 +#define SPI_INTR_RX_UNDERFLOW          0x10
 270 +#define SPI_INTR_CLEAR_ALL             0x1f
 271 +
 272 +/* Status */
 273 +#define SPI_RX_EMPTY                   0x02
 274 +#define SPI_CMD_BUSY                   0x04
 275 +#define SPI_SERIAL_BUSY                        0x08
 276 +
 277 +/* Clock configuration */
 278 +#define SPI_CLK_20MHZ                  0x00
 279 +#define SPI_CLK_0_391MHZ               0x01
 280 +#define SPI_CLK_0_781MHZ               0x02 /* default */
 281 +#define SPI_CLK_1_563MHZ               0x03
 282 +#define SPI_CLK_3_125MHZ               0x04
 283 +#define SPI_CLK_6_250MHZ               0x05
 284 +#define SPI_CLK_12_50MHZ               0x06
 285 +#define SPI_CLK_25MHZ                  0x07
 286 +#define SPI_CLK_MASK                   0x07
 287 +#define SPI_SSOFFTIME_MASK             0x38
 288 +#define SPI_SSOFFTIME_SHIFT            3
 289 +#define SPI_BYTE_SWAP                  0x80
 290 +
 291  #endif /* BCM63XX_REGS_H_ */
 292 --- /dev/null
 293 +++ b/drivers/spi/bcm63xx_spi.c
 294 @@ -0,0 +1,496 @@
 295 +/*
 296 + * Broadcom BCM63xx SPI controller support
 297 + *
 298 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
 299 + * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
 300 + *
 301 + * This program is free software; you can redistribute it and/or
 302 + * modify it under the terms of the GNU General Public License
 303 + * as published by the Free Software Foundation; either version 2
 304 + * of the License, or (at your option) any later version.
 305 + *
 306 + * This program is distributed in the hope that it will be useful,
 307 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 308 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 309 + * GNU General Public License for more details.
 310 + *
 311 + * You should have received a copy of the GNU General Public License
 312 + * along with this program; if not, write to the
 313 + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
 314 + */
 315 +
 316 +#include <linux/kernel.h>
 317 +#include <linux/init.h>
 318 +#include <linux/clk.h>
 319 +#include <linux/module.h>
 320 +#include <linux/platform_device.h>
 321 +#include <linux/delay.h>
 322 +#include <linux/interrupt.h>
 323 +#include <linux/spi/spi.h>
 324 +#include <linux/completion.h>
 325 +#include <linux/err.h>
 326 +
 327 +#include <bcm63xx_dev_spi.h>
 328 +
 329 +#define PFX            KBUILD_MODNAME
 330 +#define DRV_VER                "0.1.2"
 331 +
 332 +struct bcm63xx_spi {
 333 +       spinlock_t              lock;
 334 +       int                     stopping;
 335 +        struct completion      done;
 336 +
 337 +       void __iomem            *regs;
 338 +       int                     irq;
 339 +
 340 +       /* Platform data */
 341 +        u32                    speed_hz;
 342 +       unsigned                fifo_size;
 343 +
 344 +       /* Data buffers */
 345 +       const unsigned char     *tx_ptr;
 346 +       unsigned char           *rx_ptr;
 347 +
 348 +       /* data iomem */
 349 +       u8 __iomem              *tx_io;
 350 +       const u8 __iomem        *rx_io;
 351 +
 352 +       int                     remaining_bytes;
 353 +
 354 +       struct clk              *clk;
 355 +       struct platform_device  *pdev;
 356 +};
 357 +
 358 +static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
 359 +                               unsigned int offset)
 360 +{
 361 +       return bcm_readw(bs->regs + bcm63xx_spireg(offset));
 362 +}
 363 +
 364 +static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
 365 +                               unsigned int offset)
 366 +{
 367 +       return bcm_readw(bs->regs + bcm63xx_spireg(offset));
 368 +}
 369 +
 370 +static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
 371 +                                 u8 value, unsigned int offset)
 372 +{
 373 +       bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
 374 +}
 375 +
 376 +static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
 377 +                                 u16 value, unsigned int offset)
 378 +{
 379 +       bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
 380 +}
 381 +
 382 +static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
 383 +                                     struct spi_transfer *t)
 384 +{
 385 +       u8 bits_per_word;
 386 +       u8 clk_cfg;
 387 +       u32 hz;
 388 +       unsigned int div;
 389 +
 390 +       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 391 +
 392 +       bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
 393 +       hz = (t) ? t->speed_hz : spi->max_speed_hz;
 394 +       if (bits_per_word != 8) {
 395 +               dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
 396 +                       __func__, bits_per_word);
 397 +               return -EINVAL;
 398 +        }
 399 +
 400 +       if (spi->chip_select > spi->master->num_chipselect) {
 401 +               dev_err(&spi->dev, "%s, unsupported slave %d\n",
 402 +                       __func__, spi->chip_select);
 403 +               return -EINVAL;
 404 +       }
 405 +
 406 +       /* Check clock setting */
 407 +       div = (bs->speed_hz / hz);
 408 +       switch (div) {
 409 +       case 2:
 410 +               clk_cfg = SPI_CLK_25MHZ;
 411 +               break;
 412 +       case 4:
 413 +               clk_cfg = SPI_CLK_12_50MHZ;
 414 +               break;
 415 +       case 8:
 416 +               clk_cfg = SPI_CLK_6_250MHZ;
 417 +               break;
 418 +       case 16:
 419 +               clk_cfg = SPI_CLK_3_125MHZ;
 420 +               break;
 421 +       case 32:
 422 +               clk_cfg = SPI_CLK_1_563MHZ;
 423 +               break;
 424 +       case 64:
 425 +               clk_cfg = SPI_CLK_0_781MHZ;
 426 +               break;
 427 +       case 128:
 428 +       default:
 429 +               /* Set to slowest mode for compatibility */
 430 +               clk_cfg = SPI_CLK_0_391MHZ;
 431 +               break;
 432 +       }
 433 +
 434 +       bcm_spi_writeb(bs, clk_cfg, SPI_CLK_CFG);
 435 +       dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
 436 +               div, hz, clk_cfg);
 437 +
 438 +       return 0;
 439 +}
 440 +
 441 +/* the spi->mode bits understood by this driver: */
 442 +#define MODEBITS (SPI_CPOL | SPI_CPHA)
 443 +
 444 +static int bcm63xx_spi_setup(struct spi_device *spi)
 445 +{
 446 +       struct bcm63xx_spi *bs;
 447 +       int ret;
 448 +
 449 +       bs = spi_master_get_devdata(spi->master);
 450 +
 451 +       if (bs->stopping)
 452 +               return -ESHUTDOWN;
 453 +
 454 +       if (!spi->bits_per_word)
 455 +               spi->bits_per_word = 8;
 456 +
 457 +       if (spi->mode & ~MODEBITS) {
 458 +               dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
 459 +                       __func__, spi->mode & ~MODEBITS);
 460 +               return -EINVAL;
 461 +       }
 462 +
 463 +       ret = bcm63xx_spi_setup_transfer(spi, NULL);
 464 +       if (ret < 0) {
 465 +               dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
 466 +                       spi->mode & ~MODEBITS);
 467 +               return ret;
 468 +       }
 469 +
 470 +       dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
 471 +               __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
 472 +
 473 +       return 0;
 474 +}
 475 +
 476 +/* Fill the TX FIFO with as many bytes as possible */
 477 +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
 478 +{
 479 +       u8 size;
 480 +
 481 +        /* Fill the Tx FIFO with as many bytes as possible */
 482 +       size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :
 483 +               bs->fifo_size;
 484 +       memcpy_toio(bs->tx_io, bs->tx_ptr, size);
 485 +       bs->remaining_bytes -= size;
 486 +}
 487 +
 488 +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 489 +{
 490 +       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 491 +       u16 msg_ctl;
 492 +       u16 cmd;
 493 +
 494 +       dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 495 +               t->tx_buf, t->rx_buf, t->len);
 496 +
 497 +       /* Transmitter is inhibited */
 498 +       bs->tx_ptr = t->tx_buf;
 499 +       bs->rx_ptr = t->rx_buf;
 500 +       init_completion(&bs->done);
 501 +
 502 +       if (t->tx_buf) {
 503 +               bs->remaining_bytes = t->len;
 504 +               bcm63xx_spi_fill_tx_fifo(bs);
 505 +       }
 506 +
 507 +       /* Enable the command done interrupt which
 508 +        * we use to determine completion of a command */
 509 +       bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 510 +
 511 +       /* Fill in the Message control register */
 512 +       msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
 513 +
 514 +       if (t->rx_buf && t->tx_buf)
 515 +               msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
 516 +       else if (t->rx_buf)
 517 +               msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
 518 +       else if (t->tx_buf)
 519 +               msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
 520 +
 521 +       bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
 522 +
 523 +       /* Issue the transfer */
 524 +       cmd = SPI_CMD_START_IMMEDIATE;
 525 +       cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 526 +       cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
 527 +       bcm_spi_writew(bs, cmd, SPI_CMD);
 528 +       wait_for_completion(&bs->done);
 529 +
 530 +       /* Disable the CMD_DONE interrupt */
 531 +       bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 532 +
 533 +       return t->len - bs->remaining_bytes;
 534 +}
 535 +
 536 +static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m)
 537 +{
 538 +       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 539 +       struct spi_transfer *t;
 540 +       int ret = 0;
 541 +
 542 +       if (unlikely(list_empty(&m->transfers)))
 543 +               return -EINVAL;
 544 +
 545 +       if (bs->stopping)
 546 +               return -ESHUTDOWN;
 547 +
 548 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 549 +               ret += bcm63xx_txrx_bufs(spi, t);
 550 +       }
 551 +
 552 +       m->complete(m->context);
 553 +
 554 +       return ret;
 555 +}
 556 +
 557 +/* This driver supports single master mode only. Hence
 558 + * CMD_DONE is the only interrupt we care about
 559 + */
 560 +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
 561 +{
 562 +       struct spi_master *master = (struct spi_master *)dev_id;
 563 +       struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 564 +       u8 intr;
 565 +       u16 cmd;
 566 +
 567 +       /* Read interupts and clear them immediately */
 568 +       intr = bcm_spi_readb(bs, SPI_INT_STATUS);
 569 +       bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 570 +       bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 571 +
 572 +       /* A tansfer completed */
 573 +       if (intr & SPI_INTR_CMD_DONE) {
 574 +               u8 rx_tail;
 575 +
 576 +               rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
 577 +
 578 +               /* Read out all the data */
 579 +               if (rx_tail)
 580 +                       memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
 581 +
 582 +               /* See if there is more data to send */
 583 +               if (bs->remaining_bytes > 0) {
 584 +                       bcm63xx_spi_fill_tx_fifo(bs);
 585 +
 586 +                       /* Start the transfer */
 587 +                       bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT,
 588 +                                      SPI_MSG_CTL);
 589 +                       cmd = bcm_spi_readw(bs, SPI_CMD);
 590 +                       cmd |= SPI_CMD_START_IMMEDIATE;
 591 +                       cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 592 +                       bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 593 +                       bcm_spi_writew(bs, cmd, SPI_CMD);
 594 +               } else {
 595 +                       complete(&bs->done);
 596 +               }
 597 +       }
 598 +
 599 +       return IRQ_HANDLED;
 600 +}
 601 +
 602 +
 603 +static int __init bcm63xx_spi_probe(struct platform_device *pdev)
 604 +{
 605 +       struct resource *r;
 606 +       struct device *dev = &pdev->dev;
 607 +       struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
 608 +       int irq;
 609 +       struct spi_master *master;
 610 +       struct clk *clk;
 611 +       struct bcm63xx_spi *bs;
 612 +       int ret;
 613 +
 614 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 615 +       if (!r) {
 616 +               dev_err(dev, "no iomem\n");
 617 +               ret = -ENXIO;
 618 +               goto out;
 619 +       }
 620 +
 621 +       irq = platform_get_irq(pdev, 0);
 622 +       if (irq < 0) {
 623 +               dev_err(dev, "no irq\n");
 624 +               ret = -ENXIO;
 625 +               goto out;
 626 +       }
 627 +
 628 +       clk = clk_get(dev, "spi");
 629 +       if (IS_ERR(clk)) {
 630 +               dev_err(dev, "no clock for device\n");
 631 +               ret = -ENODEV;
 632 +               goto out;
 633 +       }
 634 +
 635 +       master = spi_alloc_master(dev, sizeof(*bs));
 636 +       if (!master) {
 637 +               dev_err(dev, "out of memory\n");
 638 +               ret = -ENOMEM;
 639 +               goto out_free;
 640 +       }
 641 +
 642 +       bs = spi_master_get_devdata(master);
 643 +       init_completion(&bs->done);
 644 +
 645 +       platform_set_drvdata(pdev, master);
 646 +       bs->pdev = pdev;
 647 +
 648 +       if (!request_mem_region(r->start, r->end - r->start, PFX)) {
 649 +               dev_err(dev, "iomem request failed\n");
 650 +               ret = -ENXIO;
 651 +               goto out_put_master;
 652 +       }
 653 +
 654 +       bs->regs = ioremap_nocache(r->start, r->end - r->start);
 655 +       if (!bs->regs) {
 656 +               dev_err(dev, "unable to ioremap regs\n");
 657 +               ret = -ENOMEM;
 658 +               goto out_put_master;
 659 +       }
 660 +       bs->irq = irq;
 661 +       bs->clk = clk;
 662 +       bs->fifo_size = pdata->fifo_size;
 663 +
 664 +       ret = request_irq(irq, bcm63xx_spi_interrupt, 0, pdev->name, master);
 665 +       if (ret) {
 666 +               dev_err(dev, "unable to request irq\n");
 667 +               goto out_unmap;
 668 +       }
 669 +
 670 +       master->bus_num = pdata->bus_num;
 671 +       master->num_chipselect = pdata->num_chipselect;
 672 +       master->setup = bcm63xx_spi_setup;
 673 +       master->transfer = bcm63xx_transfer;
 674 +       bs->speed_hz = pdata->speed_hz;
 675 +       bs->stopping = 0;
 676 +       bs->tx_io = (u8*)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
 677 +       bs->rx_io = (const u8*)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
 678 +       spin_lock_init(&bs->lock);
 679 +
 680 +       /* Initialize hardware */
 681 +       clk_enable(bs->clk);
 682 +       bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 683 +
 684 +       /* register and we are done */
 685 +       ret = spi_register_master(master);
 686 +       if (ret) {
 687 +               dev_err(dev, "spi register failed\n");
 688 +               goto out_reset_hw;
 689 +       }
 690 +
 691 +       dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
 692 +                r->start, irq, bs->fifo_size, DRV_VER);
 693 +
 694 +       return 0;
 695 +
 696 +out_reset_hw:
 697 +       clk_disable(clk);
 698 +       free_irq(irq, master);
 699 +out_unmap:
 700 +       iounmap(bs->regs);
 701 +out_put_master:
 702 +       spi_master_put(master);
 703 +out_free:
 704 +       clk_put(clk);
 705 +out:
 706 +       return ret;
 707 +}
 708 +
 709 +static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
 710 +{
 711 +       struct spi_master       *master = platform_get_drvdata(pdev);
 712 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 713 +       struct resource         *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 714 +
 715 +       /* reset spi block */
 716 +       bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 717 +       spin_lock(&bs->lock);
 718 +       bs->stopping = 1;
 719 +
 720 +       /* HW shutdown */
 721 +       clk_disable(bs->clk);
 722 +       clk_put(bs->clk);
 723 +
 724 +       spin_unlock(&bs->lock);
 725 +
 726 +       free_irq(bs->irq, master);
 727 +       iounmap(bs->regs);
 728 +       release_mem_region(r->start, r->end - r->start);
 729 +       platform_set_drvdata(pdev, 0);
 730 +       spi_unregister_master(master);
 731 +
 732 +       return 0;
 733 +}
 734 +
 735 +#ifdef CONFIG_PM
 736 +static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
 737 +{
 738 +       struct spi_master       *master = platform_get_drvdata(pdev);
 739 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 740 +
 741 +        clk_disable(bs->clk);
 742 +
 743 +       return 0;
 744 +}
 745 +
 746 +static int bcm63xx_spi_resume(struct platform_device *pdev)
 747 +{
 748 +       struct spi_master       *master = platform_get_drvdata(pdev);
 749 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 750 +
 751 +       clk_enable(bs->clk);
 752 +
 753 +       return 0;
 754 +}
 755 +#else
 756 +#define bcm63xx_spi_suspend    NULL
 757 +#define bcm63xx_spi_resume     NULL
 758 +#endif
 759 +
 760 +static struct platform_driver bcm63xx_spi_driver = {
 761 +       .driver = {
 762 +               .name   = "bcm63xx-spi",
 763 +               .owner  = THIS_MODULE,
 764 +       },
 765 +       .probe          = bcm63xx_spi_probe,
 766 +       .remove         = __exit_p(bcm63xx_spi_remove),
 767 +       .suspend        = bcm63xx_spi_suspend,
 768 +       .resume         = bcm63xx_spi_resume,
 769 +};
 770 +
 771 +
 772 +static int __init bcm63xx_spi_init(void)
 773 +{
 774 +       return platform_driver_register(&bcm63xx_spi_driver);
 775 +}
 776 +
 777 +static void __exit bcm63xx_spi_exit(void)
 778 +{
 779 +       platform_driver_unregister(&bcm63xx_spi_driver);
 780 +}
 781 +
 782 +module_init(bcm63xx_spi_init);
 783 +module_exit(bcm63xx_spi_exit);
 784 +
 785 +MODULE_ALIAS("platform:bcm63xx_spi");
 786 +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 787 +MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
 788 +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
 789 +MODULE_LICENSE("GPL");
 790 +MODULE_VERSION(DRV_VER);
 791 --- a/drivers/spi/Kconfig
 792 +++ b/drivers/spi/Kconfig
 793 @@ -74,6 +74,12 @@ config SPI_ATMEL
 794           This selects a driver for the Atmel SPI Controller, present on
 795           many AT32 (AVR32) and AT91 (ARM) chips.
 796
 797 +config SPI_BCM63XX
 798 +       tristate "Broadcom BCM63xx SPI controller"
 799 +       depends on BCM63XX
 800 +       help
 801 +         This is the SPI controller master driver for Broadcom BCM63xx SoC.
 802 +
 803  config SPI_BFIN
 804         tristate "SPI controller driver for ADI Blackfin5xx"
 805         depends on BLACKFIN
 806 --- a/drivers/spi/Makefile
 807 +++ b/drivers/spi/Makefile
 808 @@ -56,6 +56,7 @@ obj-$(CONFIG_SPI_SH_SCI)              += spi_sh_sci.
 809  obj-$(CONFIG_SPI_SH_MSIOF)             += spi_sh_msiof.o
 810  obj-$(CONFIG_SPI_STMP3XXX)             += spi_stmp.o
 811  obj-$(CONFIG_SPI_NUC900)               += spi_nuc900.o
 812 +obj-$(CONFIG_SPI_BCM63XX)              += bcm63xx_spi.o
 813
 814  # special build for s3c24xx spi driver with fiq support
 815  spi_s3c24xx_hw-y                       := spi_s3c24xx.o
 816 --- /dev/null
 817 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
 818 @@ -0,0 +1,85 @@
 819 +#ifndef BCM63XX_DEV_SPI_H
 820 +#define BCM63XX_DEV_SPI_H
 821 +
 822 +#include <linux/types.h>
 823 +#include <bcm63xx_io.h>
 824 +#include <bcm63xx_regs.h>
 825 +
 826 +int __init bcm63xx_spi_register(void);
 827 +
 828 +struct bcm63xx_spi_pdata {
 829 +       unsigned int    fifo_size;
 830 +       int             bus_num;
 831 +       int             num_chipselect;
 832 +       u32             speed_hz;
 833 +};
 834 +
 835 +enum bcm63xx_regs_spi {
 836 +        SPI_CMD,
 837 +        SPI_INT_STATUS,
 838 +        SPI_INT_MASK_ST,
 839 +        SPI_INT_MASK,
 840 +        SPI_ST,
 841 +        SPI_CLK_CFG,
 842 +        SPI_FILL_BYTE,
 843 +        SPI_MSG_TAIL,
 844 +        SPI_RX_TAIL,
 845 +        SPI_MSG_CTL,
 846 +        SPI_MSG_DATA,
 847 +        SPI_RX_DATA,
 848 +};
 849 +
 850 +#define __GEN_SPI_RSET_BASE(__cpu, __rset)                             \
 851 +       case SPI_## __rset:                                             \
 852 +               return SPI_BCM_## __cpu ##_SPI_## __rset;
 853 +
 854 +#define __GEN_SPI_RSET(__cpu)                                          \
 855 +       switch (reg) {                                                  \
 856 +       __GEN_SPI_RSET_BASE(__cpu, CMD)                                 \
 857 +       __GEN_SPI_RSET_BASE(__cpu, INT_STATUS)                          \
 858 +       __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST)                         \
 859 +       __GEN_SPI_RSET_BASE(__cpu, INT_MASK)                            \
 860 +       __GEN_SPI_RSET_BASE(__cpu, ST)                                  \
 861 +       __GEN_SPI_RSET_BASE(__cpu, CLK_CFG)                             \
 862 +       __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE)                           \
 863 +       __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL)                            \
 864 +       __GEN_SPI_RSET_BASE(__cpu, RX_TAIL)                             \
 865 +       __GEN_SPI_RSET_BASE(__cpu, MSG_CTL)                             \
 866 +       __GEN_SPI_RSET_BASE(__cpu, MSG_DATA)                            \
 867 +       __GEN_SPI_RSET_BASE(__cpu, RX_DATA)                             \
 868 +       }
 869 +
 870 +#define __GEN_SPI_REGS_TABLE(__cpu)                                    \
 871 +       [SPI_CMD]               = SPI_BCM_## __cpu ##_SPI_CMD,          \
 872 +       [SPI_INT_STATUS]        = SPI_BCM_## __cpu ##_SPI_INT_STATUS,   \
 873 +       [SPI_INT_MASK_ST]       = SPI_BCM_## __cpu ##_SPI_INT_MASK_ST,  \
 874 +       [SPI_INT_MASK]          = SPI_BCM_## __cpu ##_SPI_INT_MASK,     \
 875 +       [SPI_ST]                = SPI_BCM_## __cpu ##_SPI_ST,           \
 876 +       [SPI_CLK_CFG]           = SPI_BCM_## __cpu ##_SPI_CLK_CFG,      \
 877 +       [SPI_FILL_BYTE]         = SPI_BCM_## __cpu ##_SPI_FILL_BYTE,    \
 878 +       [SPI_MSG_TAIL]          = SPI_BCM_## __cpu ##_SPI_MSG_TAIL,     \
 879 +       [SPI_RX_TAIL]           = SPI_BCM_## __cpu ##_SPI_RX_TAIL,      \
 880 +       [SPI_MSG_CTL]           = SPI_BCM_## __cpu ##_SPI_MSG_CTL,      \
 881 +       [SPI_MSG_DATA]          = SPI_BCM_## __cpu ##_SPI_MSG_DATA,     \
 882 +       [SPI_RX_DATA]           = SPI_BCM_## __cpu ##_SPI_RX_DATA,
 883 +
 884 +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
 885 +{
 886 +#ifdef BCMCPU_RUNTIME_DETECT
 887 +       extern const unsigned long *bcm63xx_regs_spi;
 888 +        return bcm63xx_regs_spi[reg];
 889 +#else
 890 +#ifdef CONFIG_BCM63XX_CPU_6338
 891 +       __GEN_SPI_RSET(6338)
 892 +#endif
 893 +#ifdef CONFIG_BCM63XX_CPU_6348
 894 +       __GEN_SPI_RSET(6348)
 895 +#endif
 896 +#ifdef CONFIG_BCM63XX_CPU_6358
 897 +       __GEN_SPI_RSET(6358)
 898 +#endif
 899 +#endif
 900 +       return 0;
 901 +}
 902 +
 903 +#endif /* BCM63XX_DEV_SPI_H */
 904 --- a/arch/mips/bcm63xx/Makefile
 905 +++ b/arch/mips/bcm63xx/Makefile
 906 @@ -1,6 +1,6 @@
 907  obj-y          += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
 908                    dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o \
 909 -                  dev-usb-ohci.o dev-usb-ehci.o
 910 +                  dev-usb-ohci.o dev-usb-ehci.o dev-spi.o
 911  obj-$(CONFIG_EARLY_PRINTK)     += early_printk.o
 912
 913  obj-y          += boards/
 914 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
 915 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
 916 @@ -29,6 +29,7 @@
 917  #include <bcm63xx_dev_pcmcia.h>
 918  #include <bcm63xx_dev_usb_ohci.h>
 919  #include <bcm63xx_dev_usb_ehci.h>
 920 +#include <bcm63xx_dev_spi.h>
 921  #include <board_bcm963xx.h>
 922
 923  #define PFX    "board_bcm963xx: "
 924 @@ -927,6 +928,8 @@ int __init board_register_devices(void)
 925         if (board.num_spis)
 926                 spi_register_board_info(board.spis, board.num_spis);
 927
 928 +       bcm63xx_spi_register();
 929 +
 930         /* read base address of boot chip select (0) */
 931         val = bcm_mpi_readl(MPI_CSBASE_REG(0));
 932         val &= MPI_CSBASE_BASE_MASK;