1 #ifndef BCM63XX_REGS_H_
2 #define BCM63XX_REGS_H_
4 /*************************************************************************
5 * _REG relative to RSET_PERF
6 *************************************************************************/
8 /* Chip Identifier / Revision register */
9 #define PERF_REV_REG 0x0
10 #define REV_CHIPID_SHIFT 16
11 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
12 #define REV_REVID_SHIFT 0
13 #define REV_REVID_MASK (0xffff << REV_REVID_SHIFT)
15 /* Clock Control register */
16 #define PERF_CKCTL_REG 0x4
18 #define CKCTL_6348_ADSLPHY_EN (1 << 0)
19 #define CKCTL_6348_MPI_EN (1 << 1)
20 #define CKCTL_6348_SDRAM_EN (1 << 2)
21 #define CKCTL_6348_M2M_EN (1 << 3)
22 #define CKCTL_6348_ENET_EN (1 << 4)
23 #define CKCTL_6348_SAR_EN (1 << 5)
24 #define CKCTL_6348_USBS_EN (1 << 6)
25 #define CKCTL_6348_USBH_EN (1 << 8)
26 #define CKCTL_6348_SPI_EN (1 << 9)
28 #define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \
30 CKCTL_6348_ENET_EN | \
32 CKCTL_6348_USBS_EN | \
33 CKCTL_6348_USBH_EN | \
36 #define CKCTL_6358_ENET_EN (1 << 4)
37 #define CKCTL_6358_ADSLPHY_EN (1 << 5)
38 #define CKCTL_6358_PCM_EN (1 << 8)
39 #define CKCTL_6358_SPI_EN (1 << 9)
40 #define CKCTL_6358_USBS_EN (1 << 10)
41 #define CKCTL_6358_SAR_EN (1 << 11)
42 #define CKCTL_6358_EMUSB_EN (1 << 17)
43 #define CKCTL_6358_ENET0_EN (1 << 18)
44 #define CKCTL_6358_ENET1_EN (1 << 19)
45 #define CKCTL_6358_USBSU_EN (1 << 20)
46 #define CKCTL_6358_EPHY_EN (1 << 21)
48 #define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \
49 CKCTL_6358_ADSLPHY_EN | \
52 CKCTL_6358_USBS_EN | \
54 CKCTL_6358_EMUSB_EN | \
55 CKCTL_6358_ENET0_EN | \
56 CKCTL_6358_ENET1_EN | \
57 CKCTL_6358_USBSU_EN | \
60 /* System PLL Control register */
61 #define PERF_SYS_PLL_CTL_REG 0x8
62 #define SYS_PLL_SOFT_RESET 0x1
64 /* Interrupt Mask register */
65 #define PERF_IRQMASK_REG 0xc
66 #define PERF_IRQSTAT_REG 0x10
68 /* Interrupt Status register */
69 #define PERF_IRQSTAT_REG 0x10
71 /* External Interrupt Configuration register */
72 #define PERF_EXTIRQ_CFG_REG 0x14
73 #define EXTIRQ_CFG_SENSE(x) (1 << (x))
74 #define EXTIRQ_CFG_STAT(x) (1 << (x + 5))
75 #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10))
76 #define EXTIRQ_CFG_MASK(x) (1 << (x + 15))
77 #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20))
78 #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25))
80 #define EXTIRQ_CFG_CLEAR_ALL (0xf << 10)
81 #define EXTIRQ_CFG_MASK_ALL (0xf << 15)
83 /* Soft Reset register */
84 #define PERF_SOFTRESET_REG 0x28
86 #define SOFTRESET_6348_SPI_MASK (1 << 0)
87 #define SOFTRESET_6348_ENET_MASK (1 << 2)
88 #define SOFTRESET_6348_USBH_MASK (1 << 3)
89 #define SOFTRESET_6348_USBS_MASK (1 << 4)
90 #define SOFTRESET_6348_ADSL_MASK (1 << 5)
91 #define SOFTRESET_6348_DMAMEM_MASK (1 << 6)
92 #define SOFTRESET_6348_SAR_MASK (1 << 7)
93 #define SOFTRESET_6348_ACLC_MASK (1 << 8)
94 #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
96 #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \
97 SOFTRESET_6348_ENET_MASK | \
98 SOFTRESET_6348_USBH_MASK | \
99 SOFTRESET_6348_USBS_MASK | \
100 SOFTRESET_6348_ADSL_MASK | \
101 SOFTRESET_6348_DMAMEM_MASK | \
102 SOFTRESET_6348_SAR_MASK | \
103 SOFTRESET_6348_ACLC_MASK | \
104 SOFTRESET_6348_ADSLMIPSPLL_MASK)
106 /* MIPS PLL control register */
107 #define PERF_MIPSPLLCTL_REG 0x34
108 #define MIPSPLLCTL_N1_SHIFT 20
109 #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT)
110 #define MIPSPLLCTL_N2_SHIFT 15
111 #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT)
112 #define MIPSPLLCTL_M1REF_SHIFT 12
113 #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT)
114 #define MIPSPLLCTL_M2REF_SHIFT 9
115 #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT)
116 #define MIPSPLLCTL_M1CPU_SHIFT 6
117 #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
118 #define MIPSPLLCTL_M1BUS_SHIFT 3
119 #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
120 #define MIPSPLLCTL_M2BUS_SHIFT 0
121 #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
123 /* ADSL PHY PLL Control register */
124 #define PERF_ADSLPLLCTL_REG 0x38
125 #define ADSLPLLCTL_N1_SHIFT 20
126 #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT)
127 #define ADSLPLLCTL_N2_SHIFT 15
128 #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT)
129 #define ADSLPLLCTL_M1REF_SHIFT 12
130 #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT)
131 #define ADSLPLLCTL_M2REF_SHIFT 9
132 #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT)
133 #define ADSLPLLCTL_M1CPU_SHIFT 6
134 #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
135 #define ADSLPLLCTL_M1BUS_SHIFT 3
136 #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
137 #define ADSLPLLCTL_M2BUS_SHIFT 0
138 #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
140 #define ADSLPLLCTL_VAL(n1,n2,m1ref,m2ref,m1cpu,m1bus,m2bus) \
141 (((n1) << ADSLPLLCTL_N1_SHIFT) | \
142 ((n2) << ADSLPLLCTL_N2_SHIFT) | \
143 ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \
144 ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \
145 ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \
146 ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \
147 ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
150 /*************************************************************************
151 * _REG relative to RSET_TIMER
152 *************************************************************************/
154 #define BCM63XX_TIMER_COUNT 4
155 #define TIMER_T0_ID 0
156 #define TIMER_T1_ID 1
157 #define TIMER_T2_ID 2
158 #define TIMER_WDT_ID 3
160 /* Timer irqstat register */
161 #define TIMER_IRQSTAT_REG 0
162 #define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x))
163 #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0)
164 #define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1)
165 #define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2)
166 #define TIMER_IRQSTAT_WDT_CAUSE (1 << 3)
167 #define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8))
168 #define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8)
169 #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
170 #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
172 /* Timer control register */
173 #define TIMER_CTLx_REG(x) (0x4 + (x * 4))
174 #define TIMER_CTL0_REG 0x4
175 #define TIMER_CTL1_REG 0x8
176 #define TIMER_CTL2_REG 0xC
177 #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff)
178 #define TIMER_CTL_MONOTONIC_MASK (1 << 30)
179 #define TIMER_CTL_ENABLE_MASK (1 << 31)
182 /*************************************************************************
183 * _REG relative to RSET_WDT
184 *************************************************************************/
186 /* Watchdog default count register */
187 #define WDT_DEFVAL_REG 0x0
189 /* Watchdog control register */
190 #define WDT_CTL_REG 0x4
192 /* Watchdog control register constants */
193 #define WDT_START_1 (0xff00)
194 #define WDT_START_2 (0x00ff)
195 #define WDT_STOP_1 (0xee00)
196 #define WDT_STOP_2 (0x00ee)
198 /* Watchdog reset length register */
199 #define WDT_RSTLEN_REG 0x8
202 /*************************************************************************
203 * _REG relative to RSET_UARTx
204 *************************************************************************/
206 /* UART Control Register */
207 #define UART_CTL_REG 0x0
208 #define UART_CTL_RXTMOUTCNT_SHIFT 0
209 #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
210 #define UART_CTL_RSTTXDN_SHIFT 5
211 #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
212 #define UART_CTL_RSTRXFIFO_SHIFT 6
213 #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
214 #define UART_CTL_RSTTXFIFO_SHIFT 7
215 #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
216 #define UART_CTL_STOPBITS_SHIFT 8
217 #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
218 #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
219 #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
220 #define UART_CTL_BITSPERSYM_SHIFT 12
221 #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
222 #define UART_CTL_XMITBRK_SHIFT 14
223 #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
224 #define UART_CTL_RSVD_SHIFT 15
225 #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
226 #define UART_CTL_RXPAREVEN_SHIFT 16
227 #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
228 #define UART_CTL_RXPAREN_SHIFT 17
229 #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
230 #define UART_CTL_TXPAREVEN_SHIFT 18
231 #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
232 #define UART_CTL_TXPAREN_SHIFT 18
233 #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
234 #define UART_CTL_LOOPBACK_SHIFT 20
235 #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
236 #define UART_CTL_RXEN_SHIFT 21
237 #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
238 #define UART_CTL_TXEN_SHIFT 22
239 #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
240 #define UART_CTL_BRGEN_SHIFT 23
241 #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
243 /* UART Baudword register */
244 #define UART_BAUD_REG 0x4
246 /* UART Misc Control register */
247 #define UART_MCTL_REG 0x8
248 #define UART_MCTL_DTR_SHIFT 0
249 #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
250 #define UART_MCTL_RTS_SHIFT 1
251 #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
252 #define UART_MCTL_RXFIFOTHRESH_SHIFT 8
253 #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
254 #define UART_MCTL_TXFIFOTHRESH_SHIFT 12
255 #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
256 #define UART_MCTL_RXFIFOFILL_SHIFT 16
257 #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
258 #define UART_MCTL_TXFIFOFILL_SHIFT 24
259 #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
261 /* UART External Input Configuration register */
262 #define UART_EXTINP_REG 0xc
263 #define UART_EXTINP_RI_SHIFT 0
264 #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
265 #define UART_EXTINP_CTS_SHIFT 1
266 #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
267 #define UART_EXTINP_DCD_SHIFT 2
268 #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
269 #define UART_EXTINP_DSR_SHIFT 3
270 #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
271 #define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
272 #define UART_EXTINP_IRMASK(x) (1 << (x + 8))
273 #define UART_EXTINP_IR_RI 0
274 #define UART_EXTINP_IR_CTS 1
275 #define UART_EXTINP_IR_DCD 2
276 #define UART_EXTINP_IR_DSR 3
277 #define UART_EXTINP_RI_NOSENSE_SHIFT 16
278 #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
279 #define UART_EXTINP_CTS_NOSENSE_SHIFT 17
280 #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
281 #define UART_EXTINP_DCD_NOSENSE_SHIFT 18
282 #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
283 #define UART_EXTINP_DSR_NOSENSE_SHIFT 19
284 #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
286 /* UART Interrupt register */
287 #define UART_IR_REG 0x10
288 #define UART_IR_MASK(x) (1 << (x + 16))
289 #define UART_IR_STAT(x) (1 << (x))
290 #define UART_IR_EXTIP 0
291 #define UART_IR_TXUNDER 1
292 #define UART_IR_TXOVER 2
293 #define UART_IR_TXTRESH 3
294 #define UART_IR_TXRDLATCH 4
295 #define UART_IR_TXEMPTY 5
296 #define UART_IR_RXUNDER 6
297 #define UART_IR_RXOVER 7
298 #define UART_IR_RXTIMEOUT 8
299 #define UART_IR_RXFULL 9
300 #define UART_IR_RXTHRESH 10
301 #define UART_IR_RXNOTEMPTY 11
302 #define UART_IR_RXFRAMEERR 12
303 #define UART_IR_RXPARERR 13
304 #define UART_IR_RXBRK 14
305 #define UART_IR_TXDONE 15
307 /* UART Fifo register */
308 #define UART_FIFO_REG 0x14
309 #define UART_FIFO_VALID_SHIFT 0
310 #define UART_FIFO_VALID_MASK 0xff
311 #define UART_FIFO_FRAMEERR_SHIFT 8
312 #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
313 #define UART_FIFO_PARERR_SHIFT 9
314 #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
315 #define UART_FIFO_BRKDET_SHIFT 10
316 #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
317 #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
318 UART_FIFO_PARERR_MASK | \
319 UART_FIFO_BRKDET_MASK)
322 /*************************************************************************
323 * _REG relative to RSET_GPIO
324 *************************************************************************/
327 #define GPIO_CTL_HI_REG 0x0
328 #define GPIO_CTL_LO_REG 0x4
329 #define GPIO_DATA_HI_REG 0x8
330 #define GPIO_DATA_LO_REG 0xC
332 /* GPIO mux registers and constants */
333 #define GPIO_MODE_REG 0x18
335 #define GPIO_MODE_6348_G4_DIAG 0x00090000
336 #define GPIO_MODE_6348_G4_UTOPIA 0x00080000
337 #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000
338 #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000
339 #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000
340 #define GPIO_MODE_6348_G3_DIAG 0x00009000
341 #define GPIO_MODE_6348_G3_UTOPIA 0x00008000
342 #define GPIO_MODE_6348_G3_EXT_MII 0x00007000
343 #define GPIO_MODE_6348_G2_DIAG 0x00000900
344 #define GPIO_MODE_6348_G2_PCI 0x00000500
345 #define GPIO_MODE_6348_G1_DIAG 0x00000090
346 #define GPIO_MODE_6348_G1_UTOPIA 0x00000080
347 #define GPIO_MODE_6348_G1_SPI_UART 0x00000060
348 #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060
349 #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040
350 #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020
351 #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010
352 #define GPIO_MODE_6348_G0_DIAG 0x00000009
353 #define GPIO_MODE_6348_G0_EXT_MII 0x00000007
355 #define GPIO_MODE_6358_EXTRACS (1 << 5)
356 #define GPIO_MODE_6358_UART1 (1 << 6)
357 #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
358 #define GPIO_MODE_6358_SERIAL_LED (1 << 10)
359 #define GPIO_MODE_6358_UTOPIA (1 << 12)
362 /*************************************************************************
363 * _REG relative to RSET_ENET
364 *************************************************************************/
366 /* Receiver Configuration register */
367 #define ENET_RXCFG_REG 0x0
368 #define ENET_RXCFG_ALLMCAST_SHIFT 1
369 #define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT)
370 #define ENET_RXCFG_PROMISC_SHIFT 3
371 #define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT)
372 #define ENET_RXCFG_LOOPBACK_SHIFT 4
373 #define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT)
374 #define ENET_RXCFG_ENFLOW_SHIFT 5
375 #define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT)
377 /* Receive Maximum Length register */
378 #define ENET_RXMAXLEN_REG 0x4
379 #define ENET_RXMAXLEN_SHIFT 0
380 #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT)
382 /* Transmit Maximum Length register */
383 #define ENET_TXMAXLEN_REG 0x8
384 #define ENET_TXMAXLEN_SHIFT 0
385 #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT)
387 /* MII Status/Control register */
388 #define ENET_MIISC_REG 0x10
389 #define ENET_MIISC_MDCFREQDIV_SHIFT 0
390 #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
391 #define ENET_MIISC_PREAMBLEEN_SHIFT 7
392 #define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
394 /* MII Data register */
395 #define ENET_MIIDATA_REG 0x14
396 #define ENET_MIIDATA_DATA_SHIFT 0
397 #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT)
398 #define ENET_MIIDATA_TA_SHIFT 16
399 #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT)
400 #define ENET_MIIDATA_REG_SHIFT 18
401 #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT)
402 #define ENET_MIIDATA_PHYID_SHIFT 23
403 #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT)
404 #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28)
405 #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28)
407 /* Ethernet Interrupt Mask register */
408 #define ENET_IRMASK_REG 0x18
410 /* Ethernet Interrupt register */
411 #define ENET_IR_REG 0x1c
412 #define ENET_IR_MII (1 << 0)
413 #define ENET_IR_MIB (1 << 1)
414 #define ENET_IR_FLOWC (1 << 2)
416 /* Ethernet Control register */
417 #define ENET_CTL_REG 0x2c
418 #define ENET_CTL_ENABLE_SHIFT 0
419 #define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT)
420 #define ENET_CTL_DISABLE_SHIFT 1
421 #define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT)
422 #define ENET_CTL_SRESET_SHIFT 2
423 #define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT)
424 #define ENET_CTL_EPHYSEL_SHIFT 3
425 #define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT)
427 /* Transmit Control register */
428 #define ENET_TXCTL_REG 0x30
429 #define ENET_TXCTL_FD_SHIFT 0
430 #define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT)
432 /* Transmit Watermask register */
433 #define ENET_TXWMARK_REG 0x34
434 #define ENET_TXWMARK_WM_SHIFT 0
435 #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT)
437 /* MIB Control register */
438 #define ENET_MIBCTL_REG 0x38
439 #define ENET_MIBCTL_RDCLEAR_SHIFT 0
440 #define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
442 /* Perfect Match Data Low register */
443 #define ENET_PML_REG(x) (0x58 + (x) * 8)
444 #define ENET_PMH_REG(x) (0x5c + (x) * 8)
445 #define ENET_PMH_DATAVALID_SHIFT 16
446 #define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT)
449 #define ENET_MIB_REG(x) (0x200 + (x) * 4)
450 #define ENET_MIB_REG_COUNT 55
453 /*************************************************************************
454 * _REG relative to RSET_ENETDMA
455 *************************************************************************/
457 /* Controller Configuration Register */
458 #define ENETDMA_CFG_REG (0x0)
459 #define ENETDMA_CFG_EN_SHIFT 0
460 #define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT)
461 #define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
463 /* Flow Control Descriptor Low Threshold register */
464 #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6)
466 /* Flow Control Descriptor High Threshold register */
467 #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6)
469 /* Flow Control Descriptor Buffer Alloca Threshold register */
470 #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6)
471 #define ENETDMA_BUFALLOC_FORCE_SHIFT 31
472 #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
474 /* Channel Configuration register */
475 #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
476 #define ENETDMA_CHANCFG_EN_SHIFT 0
477 #define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
478 #define ENETDMA_CHANCFG_PKTHALT_SHIFT 1
479 #define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
481 /* Interrupt Control/Status register */
482 #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10)
483 #define ENETDMA_IR_BUFDONE_MASK (1 << 0)
484 #define ENETDMA_IR_PKTDONE_MASK (1 << 1)
485 #define ENETDMA_IR_NOTOWNER_MASK (1 << 2)
487 /* Interrupt Mask register */
488 #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10)
490 /* Maximum Burst Length */
491 #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10)
493 /* Ring Start Address register */
494 #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10)
496 /* State Ram Word 2 */
497 #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10)
499 /* State Ram Word 3 */
500 #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10)
502 /* State Ram Word 4 */
503 #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
506 /*************************************************************************
507 * _REG relative to RSET_OHCI_PRIV
508 *************************************************************************/
510 #define OHCI_PRIV_REG 0x0
511 #define OHCI_PRIV_PORT1_HOST_SHIFT 0
512 #define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
513 #define OHCI_PRIV_REG_SWAP_SHIFT 3
514 #define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT)
517 /*************************************************************************
518 * _REG relative to RSET_USBH_PRIV
519 *************************************************************************/
521 #define USBH_PRIV_SWAP_REG 0x0
522 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
523 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
524 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
525 #define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
526 #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1
527 #define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
528 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
529 #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
531 #define USBH_PRIV_TEST_REG 0x24
534 /*************************************************************************
535 * _REG relative to RSET_MPI
536 *************************************************************************/
538 /* well known (hard wired) chip select */
539 #define MPI_CS_PCMCIA_COMMON 4
540 #define MPI_CS_PCMCIA_ATTR 5
541 #define MPI_CS_PCMCIA_IO 6
543 /* Chip select base register */
544 #define MPI_CSBASE_REG(x) (0x0 + (x) * 8)
545 #define MPI_CSBASE_BASE_SHIFT 13
546 #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT)
547 #define MPI_CSBASE_SIZE_SHIFT 0
548 #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT)
550 #define MPI_CSBASE_SIZE_8K 0
551 #define MPI_CSBASE_SIZE_16K 1
552 #define MPI_CSBASE_SIZE_32K 2
553 #define MPI_CSBASE_SIZE_64K 3
554 #define MPI_CSBASE_SIZE_128K 4
555 #define MPI_CSBASE_SIZE_256K 5
556 #define MPI_CSBASE_SIZE_512K 6
557 #define MPI_CSBASE_SIZE_1M 7
558 #define MPI_CSBASE_SIZE_2M 8
559 #define MPI_CSBASE_SIZE_4M 9
560 #define MPI_CSBASE_SIZE_8M 10
561 #define MPI_CSBASE_SIZE_16M 11
562 #define MPI_CSBASE_SIZE_32M 12
563 #define MPI_CSBASE_SIZE_64M 13
564 #define MPI_CSBASE_SIZE_128M 14
565 #define MPI_CSBASE_SIZE_256M 15
567 /* Chip select control register */
568 #define MPI_CSCTL_REG(x) (0x4 + (x) * 8)
569 #define MPI_CSCTL_ENABLE_MASK (1 << 0)
570 #define MPI_CSCTL_WAIT_SHIFT 1
571 #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT)
572 #define MPI_CSCTL_DATA16_MASK (1 << 4)
573 #define MPI_CSCTL_SYNCMODE_MASK (1 << 7)
574 #define MPI_CSCTL_TSIZE_MASK (1 << 8)
575 #define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10)
576 #define MPI_CSCTL_SETUP_SHIFT 16
577 #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT)
578 #define MPI_CSCTL_HOLD_SHIFT 20
579 #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT)
582 #define MPI_SP0_RANGE_REG 0x100
583 #define MPI_SP0_REMAP_REG 0x104
584 #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
585 #define MPI_SP1_RANGE_REG 0x10C
586 #define MPI_SP1_REMAP_REG 0x110
587 #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
589 #define MPI_L2PCFG_REG 0x11C
590 #define MPI_L2PCFG_CFG_TYPE_SHIFT 0
591 #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
592 #define MPI_L2PCFG_REG_SHIFT 2
593 #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
594 #define MPI_L2PCFG_FUNC_SHIFT 8
595 #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
596 #define MPI_L2PCFG_DEVNUM_SHIFT 11
597 #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
598 #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
599 #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
601 #define MPI_L2PMEMRANGE1_REG 0x120
602 #define MPI_L2PMEMBASE1_REG 0x124
603 #define MPI_L2PMEMREMAP1_REG 0x128
604 #define MPI_L2PMEMRANGE2_REG 0x12C
605 #define MPI_L2PMEMBASE2_REG 0x130
606 #define MPI_L2PMEMREMAP2_REG 0x134
607 #define MPI_L2PIORANGE_REG 0x138
608 #define MPI_L2PIOBASE_REG 0x13C
609 #define MPI_L2PIOREMAP_REG 0x140
610 #define MPI_L2P_BASE_MASK (0xffff8000)
611 #define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
612 #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
614 #define MPI_PCIMODESEL_REG 0x144
615 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
616 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
617 #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
618 #define MPI_PCIMODESEL_PREFETCH_SHIFT 4
619 #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
621 #define MPI_LOCBUSCTL_REG 0x14C
622 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
623 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
625 #define MPI_LOCINT_REG 0x150
626 #define MPI_LOCINT_MASK(x) (1 << (x + 16))
627 #define MPI_LOCINT_STAT(x) (1 << (x))
628 #define MPI_LOCINT_DIR_FAILED 6
629 #define MPI_LOCINT_EXT_PCI_INT 7
630 #define MPI_LOCINT_SERR 8
631 #define MPI_LOCINT_CSERR 9
633 #define MPI_PCICFGCTL_REG 0x178
634 #define MPI_PCICFGCTL_CFGADDR_SHIFT 2
635 #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
636 #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
638 #define MPI_PCICFGDATA_REG 0x17C
640 /* PCI host bridge custom register */
641 #define BCMPCI_REG_TIMERS 0x40
642 #define REG_TIMER_TRDY_SHIFT 0
643 #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
644 #define REG_TIMER_RETRY_SHIFT 8
645 #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
648 /*************************************************************************
649 * _REG relative to RSET_PCMCIA
650 *************************************************************************/
652 #define PCMCIA_C1_REG 0x0
653 #define PCMCIA_C1_CD1_MASK (1 << 0)
654 #define PCMCIA_C1_CD2_MASK (1 << 1)
655 #define PCMCIA_C1_VS1_MASK (1 << 2)
656 #define PCMCIA_C1_VS2_MASK (1 << 3)
657 #define PCMCIA_C1_VS1OE_MASK (1 << 6)
658 #define PCMCIA_C1_VS2OE_MASK (1 << 7)
659 #define PCMCIA_C1_CBIDSEL_SHIFT (8)
660 #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
661 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
662 #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
663 #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
664 #define PCMCIA_C1_RESET_MASK (1 << 18)
666 #define PCMCIA_C2_REG 0x8
667 #define PCMCIA_C2_DATA16_MASK (1 << 0)
668 #define PCMCIA_C2_BYTESWAP_MASK (1 << 1)
669 #define PCMCIA_C2_RWCOUNT_SHIFT 2
670 #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
671 #define PCMCIA_C2_INACTIVE_SHIFT 8
672 #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
673 #define PCMCIA_C2_SETUP_SHIFT 16
674 #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT)
675 #define PCMCIA_C2_HOLD_SHIFT 24
676 #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT)
679 /*************************************************************************
680 * _REG relative to RSET_SDRAM
681 *************************************************************************/
683 #define SDRAM_CFG_REG 0x0
684 #define SDRAM_CFG_ROW_SHIFT 4
685 #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
686 #define SDRAM_CFG_COL_SHIFT 6
687 #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
688 #define SDRAM_CFG_32B_SHIFT 10
689 #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
690 #define SDRAM_CFG_BANK_SHIFT 13
691 #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
693 #define SDRAM_PRIO_REG 0x2C
694 #define SDRAM_PRIO_MIPS_SHIFT 29
695 #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
696 #define SDRAM_PRIO_ADSL_SHIFT 30
697 #define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT)
698 #define SDRAM_PRIO_EN_SHIFT 31
699 #define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT)
702 /*************************************************************************
703 * _REG relative to RSET_MEMC
704 *************************************************************************/
706 #define MEMC_CFG_REG 0x4
707 #define MEMC_CFG_32B_SHIFT 1
708 #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
709 #define MEMC_CFG_COL_SHIFT 3
710 #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
711 #define MEMC_CFG_ROW_SHIFT 6
712 #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
715 /*************************************************************************
716 * _REG relative to RSET_DDR
717 *************************************************************************/
719 #define DDR_DMIPSPLLCFG_REG 0x18
720 #define DMIPSPLLCFG_M1_SHIFT 0
721 #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
722 #define DMIPSPLLCFG_N1_SHIFT 23
723 #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT)
724 #define DMIPSPLLCFG_N2_SHIFT 29
725 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
727 /*************************************************************************
728 * _REG relative to RSET_SPI
729 *************************************************************************/
731 #define SPI_MSG_CTL 0x00
735 #define SPI_MSG_TYPE_SHIFT 14
736 #define SPI_BYTE_CNT_SHIFT 0
738 #define SPI_MSG_DATA 0x02
739 #define SPI_MSG_DATA_SIZE 0x21e
741 #define SPI_RX_FIFO 0x400
742 #define SPI_RX_FIFO_SIZE 0x220
744 #define SPI_CMD 0x700
745 #define SPI_CMD_NOOP 0
746 #define SPI_CMD_SOFT_RESET 1
747 #define SPI_CMD_HARD_RESET 2
748 #define SPI_CMD_START_IMMEDIATE 3
749 #define SPI_CMD_COMMAND_SHIFT 0
750 #define SPI_CMD_COMMAND_MASK 0x000f
751 #define SPI_CMD_DEVICE_ID_SHIFT 4
752 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
753 #define SPI_CMD_ONE_BYTE_SHIFT 11
754 #define SPI_CMD_ONE_WIRE_SHIFT 12
755 #define SPI_DEV_ID_0 0
756 #define SPI_DEV_ID_1 1
757 #define SPI_DEV_ID_2 2
758 #define SPI_DEV_ID_3 3
760 #define SPI_INT_STATUS 0x702
761 #define SPI_MASK_INT_STATUS 0x703
763 #define SPI_INT_MASK 0x704
764 #define SPI_INTR_CMD_DONE 0x01
765 #define SPI_INTR_RX_OVERFLOW 0x02
766 #define SPI_INTR_INTR_TX_UNDERFLOW 0x04
767 #define SPI_INTR_TX_OVERFLOW 0x08
768 #define SPI_INTR_RX_UNDERFLOW 0x10
769 #define SPI_INTR_CLEAR_ALL 0x1f
771 #define SPI_STATUS 0x705
772 #define SPI_RX_EMPTY 0x02
773 #define SPI_CMD_BUSY 0x04
774 #define SPI_SERIAL_BUSY 0x08
776 #define SPI_CLK_CFG 0x706
777 #define SPI_CLK_0_391MHZ 1
778 #define SPI_CLK_0_781MHZ 2 /* default */
779 #define SPI_CLK_1_563MHZ 3
780 #define SPI_CLK_3_125MHZ 4
781 #define SPI_CLK_6_250MHZ 5
782 #define SPI_CLK_12_50MHZ 6
783 #define SPI_CLK_MASK 0x07
784 #define SPI_SSOFFTIME_MASK 0x38
785 #define SPI_SSOFFTIME_SHIFT 3
786 #define SPI_BYTE_SWAP 0x80
788 #define SPI_FILL_BYTE 0x707
789 #define SPI_MSG_TAIL 0x709
790 #define SPI_RX_TAIL 0x70B
792 #endif /* BCM63XX_REGS_H_ */
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