target/linux/brcm47xx/patches-3.8/700-ssb-gigabit-ethernet-driver.patch

   1 --- a/drivers/net/ethernet/broadcom/tg3.c
   2 +++ b/drivers/net/ethernet/broadcom/tg3.c
   3 @@ -44,6 +44,7 @@
   4  #include <linux/prefetch.h>
   5  #include <linux/dma-mapping.h>
   6  #include <linux/firmware.h>
   7 +#include <linux/ssb/ssb_driver_gige.h>
   8  #include <linux/hwmon.h>
   9  #include <linux/hwmon-sysfs.h>
  10
  11 @@ -263,6 +264,7 @@ static DEFINE_PCI_DEVICE_TABLE(tg3_pci_t
  12                         TG3_DRV_DATA_FLAG_5705_10_100},
  13         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
  14         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
  15 +       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
  16         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
  17         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
  18         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
  19 @@ -570,7 +572,9 @@ static void _tw32_flush(struct tg3 *tp,
  20  static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
  21  {
  22         tp->write32_mbox(tp, off, val);
  23 -       if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
  24 +       if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
  25 +           (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
  26 +            !tg3_flag(tp, ICH_WORKAROUND)))
  27                 tp->read32_mbox(tp, off);
  28  }
  29
  30 @@ -580,7 +584,8 @@ static void tg3_write32_tx_mbox(struct t
  31         writel(val, mbox);
  32         if (tg3_flag(tp, TXD_MBOX_HWBUG))
  33                 writel(val, mbox);
  34 -       if (tg3_flag(tp, MBOX_WRITE_REORDER))
  35 +       if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
  36 +           tg3_flag(tp, FLUSH_POSTED_WRITES))
  37                 readl(mbox);
  38  }
  39
  40 @@ -1088,7 +1093,8 @@ static void tg3_switch_clocks(struct tg3
  41
  42  #define PHY_BUSY_LOOPS 5000
  43
  44 -static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  45 +static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
  46 +                        u32 *val)
  47  {
  48         u32 frame_val;
  49         unsigned int loops;
  50 @@ -1104,7 +1110,7 @@ static int tg3_readphy(struct tg3 *tp, i
  51
  52         *val = 0x0;
  53
  54 -       frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  55 +       frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  56                       MI_COM_PHY_ADDR_MASK);
  57         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  58                       MI_COM_REG_ADDR_MASK);
  59 @@ -1141,7 +1147,13 @@ static int tg3_readphy(struct tg3 *tp, i
  60         return ret;
  61  }
  62
  63 -static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  64 +static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  65 +{
  66 +       return __tg3_readphy(tp, tp->phy_addr, reg, val);
  67 +}
  68 +
  69 +static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
  70 +                         u32 val)
  71  {
  72         u32 frame_val;
  73         unsigned int loops;
  74 @@ -1159,7 +1171,7 @@ static int tg3_writephy(struct tg3 *tp,
  75
  76         tg3_ape_lock(tp, tp->phy_ape_lock);
  77
  78 -       frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  79 +       frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  80                       MI_COM_PHY_ADDR_MASK);
  81         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  82                       MI_COM_REG_ADDR_MASK);
  83 @@ -1194,6 +1206,11 @@ static int tg3_writephy(struct tg3 *tp,
  84         return ret;
  85  }
  86
  87 +static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  88 +{
  89 +       return __tg3_writephy(tp, tp->phy_addr, reg, val);
  90 +}
  91 +
  92  static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
  93  {
  94         int err;
  95 @@ -1778,6 +1795,11 @@ static int tg3_poll_fw(struct tg3 *tp)
  96         int i;
  97         u32 val;
  98
  99 +       if (tg3_flag(tp, IS_SSB_CORE)) {
 100 +               /* We don't use firmware. */
 101 +               return 0;
 102 +       }
 103 +
 104         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 105                 /* Wait up to 20ms for init done. */
 106                 for (i = 0; i < 200; i++) {
 107 @@ -3443,6 +3465,13 @@ static int tg3_halt_cpu(struct tg3 *tp,
 108                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
 109                 udelay(10);
 110         } else {
 111 +               /*
 112 +                * There is only an Rx CPU for the 5750 derivative in the
 113 +                * BCM4785.
 114 +                */
 115 +               if (tg3_flag(tp, IS_SSB_CORE))
 116 +                       return 0;
 117 +
 118                 for (i = 0; i < 10000; i++) {
 119                         tw32(offset + CPU_STATE, 0xffffffff);
 120                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
 121 @@ -3910,8 +3939,9 @@ static int tg3_power_down_prepare(struct
 122         tg3_frob_aux_power(tp, true);
 123
 124         /* Workaround for unstable PLL clock */
 125 -       if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
 126 -           (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
 127 +       if ((!tg3_flag(tp, IS_SSB_CORE)) &&
 128 +           ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
 129 +            (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
 130                 u32 val = tr32(0x7d00);
 131
 132                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
 133 @@ -4439,6 +4469,15 @@ relink:
 134         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
 135                 tg3_phy_copper_begin(tp);
 136
 137 +               if (tg3_flag(tp, ROBOSWITCH)) {
 138 +                       current_link_up = 1;
 139 +                       /* FIXME: when BCM5325 switch is used use 100 MBit/s */
 140 +                       current_speed = SPEED_1000;
 141 +                       current_duplex = DUPLEX_FULL;
 142 +                       tp->link_config.active_speed = current_speed;
 143 +                       tp->link_config.active_duplex = current_duplex;
 144 +               }
 145 +
 146                 tg3_readphy(tp, MII_BMSR, &bmsr);
 147                 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
 148                     (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
 149 @@ -4457,6 +4496,26 @@ relink:
 150         else
 151                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
 152
 153 +       /* In order for the 5750 core in BCM4785 chip to work properly
 154 +        * in RGMII mode, the Led Control Register must be set up.
 155 +        */
 156 +       if (tg3_flag(tp, RGMII_MODE)) {
 157 +               u32 led_ctrl = tr32(MAC_LED_CTRL);
 158 +               led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
 159 +
 160 +               if (tp->link_config.active_speed == SPEED_10)
 161 +                       led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
 162 +               else if (tp->link_config.active_speed == SPEED_100)
 163 +                       led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
 164 +                                    LED_CTRL_100MBPS_ON);
 165 +               else if (tp->link_config.active_speed == SPEED_1000)
 166 +                       led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
 167 +                                    LED_CTRL_1000MBPS_ON);
 168 +
 169 +               tw32(MAC_LED_CTRL, led_ctrl);
 170 +               udelay(40);
 171 +       }
 172 +
 173         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
 174         if (tp->link_config.active_duplex == DUPLEX_HALF)
 175                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
 176 @@ -8435,6 +8494,16 @@ static int tg3_chip_reset(struct tg3 *tp
 177                 tw32(0x5000, 0x400);
 178         }
 179
 180 +       if (tg3_flag(tp, IS_SSB_CORE)) {
 181 +               /*
 182 +                * BCM4785: In order to avoid repercussions from using
 183 +                * potentially defective internal ROM, stop the Rx RISC CPU,
 184 +                * which is not required.
 185 +                */
 186 +               tg3_stop_fw(tp);
 187 +               tg3_halt_cpu(tp, RX_CPU_BASE);
 188 +       }
 189 +
 190         tw32(GRC_MODE, tp->grc_mode);
 191
 192         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
 193 @@ -10068,6 +10137,11 @@ static void tg3_timer(unsigned long __op
 194             tg3_flag(tp, 57765_CLASS))
 195                 tg3_chk_missed_msi(tp);
 196
 197 +       if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
 198 +               /* BCM4785: Flush posted writes from GbE to host memory. */
 199 +               tr32(HOSTCC_MODE);
 200 +       }
 201 +
 202         if (!tg3_flag(tp, TAGGED_STATUS)) {
 203                 /* All of this garbage is because when using non-tagged
 204                  * IRQ status the mailbox/status_block protocol the chip
 205 @@ -12941,7 +13015,8 @@ static int tg3_ioctl(struct net_device *
 206                         return -EAGAIN;
 207
 208                 spin_lock_bh(&tp->lock);
 209 -               err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
 210 +               err = __tg3_readphy(tp, data->phy_id & 0x1f,
 211 +                                   data->reg_num & 0x1f, &mii_regval);
 212                 spin_unlock_bh(&tp->lock);
 213
 214                 data->val_out = mii_regval;
 215 @@ -12957,7 +13032,8 @@ static int tg3_ioctl(struct net_device *
 216                         return -EAGAIN;
 217
 218                 spin_lock_bh(&tp->lock);
 219 -               err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
 220 +               err = __tg3_writephy(tp, data->phy_id & 0x1f,
 221 +                                    data->reg_num & 0x1f, data->val_in);
 222                 spin_unlock_bh(&tp->lock);
 223
 224                 return err;
 225 @@ -13810,6 +13886,14 @@ static void tg3_get_5720_nvram_info(stru
 226  /* Chips other than 5700/5701 use the NVRAM for fetching info. */
 227  static void tg3_nvram_init(struct tg3 *tp)
 228  {
 229 +       if (tg3_flag(tp, IS_SSB_CORE)) {
 230 +               /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
 231 +               tg3_flag_clear(tp, NVRAM);
 232 +               tg3_flag_clear(tp, NVRAM_BUFFERED);
 233 +               tg3_flag_set(tp, NO_NVRAM);
 234 +               return;
 235 +       }
 236 +
 237         tw32_f(GRC_EEPROM_ADDR,
 238              (EEPROM_ADDR_FSM_RESET |
 239               (EEPROM_DEFAULT_CLOCK_PERIOD <<
 240 @@ -14302,10 +14386,19 @@ static int tg3_phy_probe(struct tg3 *tp)
 241                          * subsys device table.
 242                          */
 243                         p = tg3_lookup_by_subsys(tp);
 244 -                       if (!p)
 245 +                       if (p) {
 246 +                               tp->phy_id = p->phy_id;
 247 +                       } else if (!tg3_flag(tp, IS_SSB_CORE)) {
 248 +                               /* For now we saw the IDs 0xbc050cd0,
 249 +                                * 0xbc050f80 and 0xbc050c30 on devices
 250 +                                * connected to an BCM4785 and there are
 251 +                                * probably more. Just assume that the phy is
 252 +                                * supported when it is connected to a SSB core
 253 +                                * for now.
 254 +                                */
 255                                 return -ENODEV;
 256 +                       }
 257
 258 -                       tp->phy_id = p->phy_id;
 259                         if (!tp->phy_id ||
 260                             tp->phy_id == TG3_PHY_ID_BCM8002)
 261                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
 262 @@ -15353,6 +15446,11 @@ static int tg3_get_invariants(struct tg3
 263                 }
 264         }
 265
 266 +       if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
 267 +               tp->write32_tx_mbox = tg3_write_flush_reg32;
 268 +               tp->write32_rx_mbox = tg3_write_flush_reg32;
 269 +       }
 270 +
 271         /* Get eeprom hw config before calling tg3_set_power_state().
 272          * In particular, the TG3_FLAG_IS_NIC flag must be
 273          * determined before calling tg3_set_power_state() so that
 274 @@ -15686,12 +15784,19 @@ static int tg3_get_device_address(struct
 275         struct net_device *dev = tp->dev;
 276         u32 hi, lo, mac_offset;
 277         int addr_ok = 0;
 278 +       int err;
 279
 280  #ifdef CONFIG_SPARC
 281         if (!tg3_get_macaddr_sparc(tp))
 282                 return 0;
 283  #endif
 284
 285 +       if (tg3_flag(tp, IS_SSB_CORE)) {
 286 +               err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
 287 +               if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
 288 +                       return 0;
 289 +       }
 290 +
 291         mac_offset = 0x7c;
 292         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 293             tg3_flag(tp, 5780_CLASS)) {
 294 @@ -16052,6 +16157,8 @@ static int tg3_test_dma(struct tg3 *tp)
 295                         tp->dma_rwctrl |= 0x001b000f;
 296                 }
 297         }
 298 +       if (tg3_flag(tp, ONE_DMA_AT_ONCE))
 299 +               tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
 300
 301         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 302             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
 303 @@ -16396,6 +16503,18 @@ static int tg3_init_one(struct pci_dev *
 304         else
 305                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
 306
 307 +       if (pdev_is_ssb_gige_core(pdev)) {
 308 +               tg3_flag_set(tp, IS_SSB_CORE);
 309 +               if (ssb_gige_must_flush_posted_writes(pdev))
 310 +                       tg3_flag_set(tp, FLUSH_POSTED_WRITES);
 311 +               if (ssb_gige_one_dma_at_once(pdev))
 312 +                       tg3_flag_set(tp, ONE_DMA_AT_ONCE);
 313 +               if (ssb_gige_have_roboswitch(pdev))
 314 +                       tg3_flag_set(tp, ROBOSWITCH);
 315 +               if (ssb_gige_is_rgmii(pdev))
 316 +                       tg3_flag_set(tp, RGMII_MODE);
 317 +       }
 318 +
 319         /* The word/byte swap controls here control register access byte
 320          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
 321          * setting below.
 322 --- a/drivers/net/ethernet/broadcom/tg3.h
 323 +++ b/drivers/net/ethernet/broadcom/tg3.h
 324 @@ -3030,6 +3030,11 @@ enum TG3_FLAGS {
 325         TG3_FLAG_57765_PLUS,
 326         TG3_FLAG_57765_CLASS,
 327         TG3_FLAG_5717_PLUS,
 328 +       TG3_FLAG_IS_SSB_CORE,
 329 +       TG3_FLAG_FLUSH_POSTED_WRITES,
 330 +       TG3_FLAG_ROBOSWITCH,
 331 +       TG3_FLAG_ONE_DMA_AT_ONCE,
 332 +       TG3_FLAG_RGMII_MODE,
 333
 334         /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
 335         TG3_FLAG_NUMBER_OF_FLAGS,       /* Last entry in enum TG3_FLAGS */
 336 --- a/include/linux/pci_ids.h
 337 +++ b/include/linux/pci_ids.h
 338 @@ -2127,6 +2127,7 @@
 339  #define PCI_DEVICE_ID_TIGON3_5754M     0x1672
 340  #define PCI_DEVICE_ID_TIGON3_5755M     0x1673
 341  #define PCI_DEVICE_ID_TIGON3_5756      0x1674
 342 +#define PCI_DEVICE_ID_TIGON3_5750      0x1676
 343  #define PCI_DEVICE_ID_TIGON3_5751      0x1677
 344  #define PCI_DEVICE_ID_TIGON3_5715      0x1678
 345  #define PCI_DEVICE_ID_TIGON3_5715S     0x1679
 346 --- a/include/linux/ssb/ssb_driver_gige.h
 347 +++ b/include/linux/ssb/ssb_driver_gige.h
 348 @@ -97,21 +97,16 @@ static inline bool ssb_gige_must_flush_p
 349         return 0;
 350  }
 351
 352 -#ifdef CONFIG_BCM47XX
 353 -#include <bcm47xx_nvram.h>
 354  /* Get the device MAC address */
 355 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
 356 -{
 357 -       char buf[20];
 358 -       if (bcm47xx_nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
 359 -               return;
 360 -       bcm47xx_nvram_parse_macaddr(buf, macaddr);
 361 -}
 362 -#else
 363 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
 364 +static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
 365  {
 366 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
 367 +       if (!dev)
 368 +               return -ENODEV;
 369 +
 370 +       memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
 371 +       return 0;
 372  }
 373 -#endif
 374
 375  extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
 376                                           struct pci_dev *pdev);
 377 @@ -175,6 +170,10 @@ static inline bool ssb_gige_must_flush_p
 378  {
 379         return 0;
 380  }
 381 +static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
 382 +{
 383 +       return -ENODEV;
 384 +}
 385
 386  #endif /* CONFIG_SSB_DRIVER_GIGE */
 387  #endif /* LINUX_SSB_DRIVER_GIGE_H_ */