target/linux/brcm47xx/patches-3.3/030-bcm47xx-bcma-nandflash.patch

   1 --- a/arch/mips/bcm47xx/Kconfig
   2 +++ b/arch/mips/bcm47xx/Kconfig
   3 @@ -24,6 +24,7 @@ config BCM47XX_BCMA
   4         select BCMA_DRIVER_MIPS
   5         select BCMA_DRIVER_PCI_HOSTMODE if PCI
   6         select BCMA_SFLASH
   7 +       select BCMA_NFLASH
   8         default y
   9         help
  10          Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus.
  11 --- a/arch/mips/bcm47xx/bus.c
  12 +++ b/arch/mips/bcm47xx/bus.c
  13 @@ -2,6 +2,7 @@
  14   * BCM947xx nvram variable access
  15   *
  16   * Copyright (C) 2011 Hauke Mehrtens <hauke@hauke-m.de>
  17 + * Copyright (C) 2011-2012 Tathagata Das <tathagata@alumnux.com>
  18   *
  19   * This program is free software; you can redistribute  it and/or modify it
  20   * under  the terms of  the GNU General  Public License as published by the
  21 @@ -80,3 +81,9 @@ void bcm47xx_sflash_struct_ssb_init(stru
  22         sflash->numblocks = scc->sflash.numblocks;
  23         sflash->size = scc->sflash.size;
  24  }
  25 +
  26 +void bcm47xx_nflash_struct_bcma_init(struct bcm47xx_nflash *nflash, struct bcma_drv_cc *bcc)
  27 +{
  28 +       nflash->nflash_type = BCM47XX_BUS_TYPE_BCMA;
  29 +       nflash->bcc = bcc;
  30 +}
  31 --- a/arch/mips/bcm47xx/nvram.c
  32 +++ b/arch/mips/bcm47xx/nvram.c
  33 @@ -4,6 +4,7 @@
  34   * Copyright (C) 2005 Broadcom Corporation
  35   * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
  36   * Copyright (C) 2010-2011 Hauke Mehrtens <hauke@hauke-m.de>
  37 + * Copyright (C) 2011-2012 Tathagata Das <tathagata@alumnux.com>
  38   *
  39   * This program is free software; you can redistribute  it and/or modify it
  40   * under  the terms of  the GNU General  Public License as published by the
  41 @@ -21,6 +22,7 @@
  42  #include <asm/mach-bcm47xx/nvram.h>
  43  #include <asm/mach-bcm47xx/bcm47xx.h>
  44  #include <asm/mach-bcm47xx/bus.h>
  45 +#include <linux/mtd/bcm47xx_nand.h>
  46
  47  static char nvram_buf[NVRAM_SPACE];
  48
  49 @@ -139,6 +141,51 @@ static int early_nvram_init_sflash(void)
  50         return 0;
  51  }
  52
  53 +static int early_nvram_init_nflash(void)
  54 +{
  55 +       struct nvram_header *header;
  56 +       u32 off;
  57 +       int ret;
  58 +       int len;
  59 +       u32 flash_size = bcm47xx_nflash.size;
  60 +       u8 tmpbuf[NFL_SECTOR_SIZE];
  61 +       int i;
  62 +       u32 *src, *dst;
  63 +
  64 +       /* check if the struct is already initilized */
  65 +       if (!flash_size)
  66 +               return -1;
  67 +
  68 +       cfe_env = 0;
  69 +
  70 +       off = FLASH_MIN;
  71 +       while (off <= flash_size) {
  72 +               ret = bcma_nflash_read(bcm47xx_nflash.bcc, off, NFL_SECTOR_SIZE, tmpbuf);
  73 +               if (ret != NFL_SECTOR_SIZE)
  74 +                       goto done;
  75 +               header = (struct nvram_header *)tmpbuf;
  76 +               if (header->magic == NVRAM_HEADER)
  77 +                       goto found;
  78 +               off <<= 1;
  79 +       }
  80 +
  81 +       ret = -1;
  82 +       goto done;
  83 +
  84 +found:
  85 +       len = header->len;
  86 +       header = (struct nvram_header *) KSEG1ADDR(NAND_FLASH1 + off);
  87 +       src = (u32 *) header;
  88 +       dst = (u32 *) nvram_buf;
  89 +       for (i = 0; i < sizeof(struct nvram_header); i += 4)
  90 +               *dst++ = *src++;
  91 +       for (; i < len && i < NVRAM_SPACE; i += 4)
  92 +               *dst++ = *src++;
  93 +       ret = 0;
  94 +done:
  95 +       return ret;
  96 +}
  97 +
  98  #ifdef CONFIG_BCM47XX_SSB
  99  static void early_nvram_init_ssb(void)
 100  {
 101 @@ -173,6 +220,11 @@ static void early_nvram_init_bcma(void)
 102                 if (err < 0)
 103                         printk(KERN_WARNING "can not read from flash: %i\n", err);
 104                 break;
 105 +       case BCMA_NFLASH:
 106 +               err = early_nvram_init_nflash();
 107 +               if (err < 0)
 108 +                       printk(KERN_WARNING "can not read from nflash: %i\n", err);
 109 +               break;
 110         default:
 111                 printk(KERN_WARNING "unknow flash type\n");
 112         }
 113 --- a/arch/mips/bcm47xx/setup.c
 114 +++ b/arch/mips/bcm47xx/setup.c
 115 @@ -4,6 +4,7 @@
 116   *  Copyright (C) 2006 Michael Buesch <m@bues.ch>
 117   *  Copyright (C) 2010 Waldemar Brodkorb <wbx@openadk.org>
 118   *  Copyright (C) 2010-2011 Hauke Mehrtens <hauke@hauke-m.de>
 119 + *  Copyright (C) 2011-2012 Tathagata Das <tathagata@alumnux.com>
 120   *
 121   *  This program is free software; you can redistribute  it and/or modify it
 122   *  under  the terms of  the GNU General  Public License as published by the
 123 @@ -46,6 +47,7 @@ enum bcm47xx_bus_type bcm47xx_bus_type;
 124  EXPORT_SYMBOL(bcm47xx_bus_type);
 125
 126  struct bcm47xx_sflash bcm47xx_sflash;
 127 +struct bcm47xx_nflash bcm47xx_nflash;
 128
 129  static struct resource bcm47xx_pflash_resource = {
 130         .name   = "bcm47xx_pflash",
 131 @@ -73,6 +75,19 @@ static struct platform_device bcm47xx_sf
 132         .num_resources  = 1,
 133  };
 134
 135 +static struct resource bcm47xx_nflash_resource = {
 136 +       .name   = "bcm47xx_nflash",
 137 +       .start  = 0,
 138 +       .end    = 0,
 139 +       .flags  = 0,
 140 +};
 141 +
 142 +static struct platform_device bcm47xx_nflash_dev = {
 143 +       .name           = "bcm47xx_nflash",
 144 +       .resource       = &bcm47xx_nflash_resource,
 145 +       .num_resources  = 1,
 146 +};
 147 +
 148  static void bcm47xx_machine_restart(char *command)
 149  {
 150         printk(KERN_ALERT "Please stand by while rebooting the system...\n");
 151 @@ -369,6 +384,9 @@ static void __init bcm47xx_register_bcma
 152
 153         if (bcm47xx_bus.bcma.bus.drv_cc.flash_type == BCMA_SFLASH)
 154                 bcm47xx_sflash_struct_bcma_init(&bcm47xx_sflash, &bcm47xx_bus.bcma.bus.drv_cc);
 155 +
 156 +       if (bcm47xx_bus.bcma.bus.drv_cc.flash_type == BCMA_NFLASH)
 157 +               bcm47xx_nflash_struct_bcma_init(&bcm47xx_nflash, &bcm47xx_bus.bcma.bus.drv_cc);
 158  }
 159
 160  static int __init bcm47xx_register_flash_bcma(void)
 161 @@ -383,6 +401,9 @@ static int __init bcm47xx_register_flash
 162         case BCMA_SFLASH:
 163                 bcm47xx_sflash_dev.dev.platform_data = &bcm47xx_sflash;
 164                 return platform_device_register(&bcm47xx_sflash_dev);
 165 +       case BCMA_NFLASH:
 166 +               bcm47xx_nflash_dev.dev.platform_data = &bcm47xx_nflash;
 167 +               return platform_device_register(&bcm47xx_nflash_dev);
 168         default:
 169                 printk(KERN_ERR "No flash device found\n");
 170                 return -1;
 171 --- a/arch/mips/include/asm/mach-bcm47xx/bus.h
 172 +++ b/arch/mips/include/asm/mach-bcm47xx/bus.h
 173 @@ -2,6 +2,7 @@
 174   * BCM947xx nvram variable access
 175   *
 176   * Copyright (C) 2011 Hauke Mehrtens <hauke@hauke-m.de>
 177 + * Copyright (C) 2011-2012 Tathagata Das <tathagata@alumnux.com>
 178   *
 179   * This program is free software; you can redistribute  it and/or modify it
 180   * under  the terms of  the GNU General  Public License as published by the
 181 @@ -13,6 +14,7 @@
 182  #include <linux/bcma/bcma.h>
 183  #include <linux/mtd/mtd.h>
 184  #include <bcm47xx.h>
 185 +#include <linux/mtd/nand.h>
 186
 187  struct bcm47xx_sflash {
 188         enum bcm47xx_bus_type sflash_type;
 189 @@ -29,11 +31,24 @@ struct bcm47xx_sflash {
 190         u32 blocksize;          /* Block size */
 191         u32 numblocks;          /* Number of blocks */
 192         u32 size;               /* Total size in bytes */
 193 -
 194 -       struct mtd_info *mtd;
 195  };
 196
 197  void bcm47xx_sflash_struct_bcma_init(struct bcm47xx_sflash *sflash, struct bcma_drv_cc *bcc);
 198  void bcm47xx_sflash_struct_ssb_init(struct bcm47xx_sflash *sflash, struct ssb_chipcommon *scc);
 199
 200  extern struct bcm47xx_sflash bcm47xx_sflash;
 201 +
 202 +struct bcm47xx_nflash {
 203 +       enum bcm47xx_bus_type nflash_type;
 204 +       struct bcma_drv_cc *bcc;
 205 +
 206 +       u32 size;               /* Total size in bytes */
 207 +       u32 next_opcode; /* Next expected command from upper NAND layer */
 208 +
 209 +       struct mtd_info mtd;
 210 +       struct nand_chip nand;
 211 +};
 212 +
 213 +void bcm47xx_nflash_struct_bcma_init(struct bcm47xx_nflash *nflash, struct bcma_drv_cc *bcc);
 214 +
 215 +extern struct bcm47xx_nflash bcm47xx_nflash;
 216 --- a/drivers/bcma/Kconfig
 217 +++ b/drivers/bcma/Kconfig
 218 @@ -43,6 +43,11 @@ config BCMA_SFLASH
 219         depends on BCMA_DRIVER_MIPS
 220         default y
 221
 222 +config BCMA_NFLASH
 223 +       bool
 224 +       depends on BCMA_DRIVER_MIPS
 225 +       default y
 226 +
 227  config BCMA_DRIVER_MIPS
 228         bool "BCMA Broadcom MIPS core driver"
 229         depends on BCMA && MIPS
 230 --- a/drivers/bcma/Makefile
 231 +++ b/drivers/bcma/Makefile
 232 @@ -1,6 +1,7 @@
 233  bcma-y                                 += main.o scan.o core.o sprom.o
 234  bcma-y                                 += driver_chipcommon.o driver_chipcommon_pmu.o
 235  bcma-$(CONFIG_BCMA_SFLASH)             += driver_chipcommon_sflash.o
 236 +bcma-$(CONFIG_BCMA_NFLASH)             += driver_chipcommon_nflash.o
 237  bcma-y                                 += driver_pci.o
 238  bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE)        += driver_pci_host.o
 239  bcma-$(CONFIG_BCMA_DRIVER_MIPS)                += driver_mips.o
 240 --- a/drivers/bcma/bcma_private.h
 241 +++ b/drivers/bcma/bcma_private.h
 242 @@ -47,6 +47,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
 243  int bcma_sflash_init(struct bcma_drv_cc *cc);
 244  #endif /* CONFIG_BCMA_SFLASH */
 245
 246 +#ifdef CONFIG_BCMA_NFLASH
 247 +/* driver_chipcommon_nflash.c */
 248 +int bcma_nflash_init(struct bcma_drv_cc *cc);
 249 +#endif /* CONFIG_BCMA_NFLASH */
 250 +
 251  #ifdef CONFIG_BCMA_HOST_PCI
 252  /* host_pci.c */
 253  extern int __init bcma_host_pci_init(void);
 254 --- /dev/null
 255 +++ b/drivers/bcma/driver_chipcommon_nflash.c
 256 @@ -0,0 +1,154 @@
 257 +/*
 258 + * BCMA nand flash interface
 259 + *
 260 + * Copyright 2011, Tathagata Das <tathagata@alumnux.com>
 261 + * Copyright 2010, Broadcom Corporation
 262 + *
 263 + * Licensed under the GNU/GPL. See COPYING for details.
 264 + */
 265 +
 266 +#include <linux/bcma/bcma.h>
 267 +#include <linux/bcma/bcma_driver_chipcommon.h>
 268 +#include <linux/delay.h>
 269 +#include <linux/mtd/bcm47xx_nand.h>
 270 +#include <linux/mtd/nand.h>
 271 +
 272 +#include "bcma_private.h"
 273 +
 274 +/* Issue a nand flash command */
 275 +static inline void bcma_nflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
 276 +{
 277 +       bcma_cc_write32(cc, NAND_CMD_START, opcode);
 278 +       bcma_cc_read32(cc,  NAND_CMD_START);
 279 +}
 280 +
 281 +/* Check offset and length */
 282 +static int bcma_nflash_offset_is_valid(struct bcma_drv_cc *cc, u32 offset, u32 len, u32 mask)
 283 +{
 284 +       if ((offset & mask) != 0 || (len & mask) != 0) {
 285 +               pr_err("%s(): Address is not aligned. offset: %x, len: %x, mask: %x\n", __func__, offset, len, mask);
 286 +               return 1;
 287 +       }
 288 +
 289 +       if ((((offset + len) >> 20) >= cc->nflash.size) &&
 290 +               (((offset + len) & ((1 << 20) - 1)) != 0)) {
 291 +               pr_err("%s(): Address is outside Flash memory region. offset: %x, len: %x, mask: %x\n", __func__, offset, len, mask);
 292 +               return 1;
 293 +       }
 294 +
 295 +       return 0;
 296 +}
 297 +
 298 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
 299 +int bcma_nflash_read(struct bcma_drv_cc *cc, u32 offset, u32 len, u8 *buf)
 300 +{
 301 +       u32 mask;
 302 +       int i;
 303 +       u32 *to, val, res;
 304 +
 305 +       mask = NFL_SECTOR_SIZE - 1;
 306 +       if (bcma_nflash_offset_is_valid(cc, offset, len, mask))
 307 +               return 0;
 308 +
 309 +       to = (u32 *)buf;
 310 +       res = len;
 311 +       while (res > 0) {
 312 +               bcma_cc_write32(cc, NAND_CMD_ADDR, offset);
 313 +               bcma_nflash_cmd(cc, NCMD_PAGE_RD);
 314 +               if (bcma_nflash_poll(cc) < 0)
 315 +                       break;
 316 +               val = bcma_cc_read32(cc, NAND_INTFC_STATUS);
 317 +               if ((val & NIST_CACHE_VALID) == 0)
 318 +                       break;
 319 +               bcma_cc_write32(cc, NAND_CACHE_ADDR, 0);
 320 +               for (i = 0; i < NFL_SECTOR_SIZE; i += 4, to++) {
 321 +                       *to = bcma_cc_read32(cc, NAND_CACHE_DATA);
 322 +               }
 323 +               res -= NFL_SECTOR_SIZE;
 324 +               offset += NFL_SECTOR_SIZE;
 325 +       }
 326 +       return (len - res);
 327 +}
 328 +
 329 +#define NF_RETRIES   1000000
 330 +
 331 +/* Poll for command completion. Returns zero when complete. */
 332 +int bcma_nflash_poll(struct bcma_drv_cc *cc)
 333 +{
 334 +       u32 retries = NF_RETRIES;
 335 +       u32 pollmask = NIST_CTRL_READY|NIST_FLASH_READY;
 336 +       u32 mask;
 337 +
 338 +       while (retries--) {
 339 +               mask = bcma_cc_read32(cc, NAND_INTFC_STATUS) & pollmask;
 340 +               if (mask == pollmask)
 341 +                       return 0;
 342 +               cpu_relax();
 343 +       }
 344 +
 345 +       if (!retries) {
 346 +               pr_err("bcma_nflash_poll: not ready\n");
 347 +               return -1;
 348 +       }
 349 +
 350 +       return 0;
 351 +}
 352 +
 353 +/* Write len bytes starting at offset into buf. Returns success (0) or failure (!0).
 354 + * Should poll for completion.
 355 + */
 356 +int bcma_nflash_write(struct bcma_drv_cc *cc, u32 offset, u32 len,
 357 +                           const u8 *buf)
 358 +{
 359 +       u32 mask;
 360 +       int i;
 361 +       u32 *from, res, reg;
 362 +
 363 +       mask = cc->nflash.pagesize - 1;
 364 +       if (bcma_nflash_offset_is_valid(cc, offset, len, mask))
 365 +               return 1;
 366 +
 367 +       /* disable partial page enable */
 368 +       reg = bcma_cc_read32(cc, NAND_ACC_CONTROL);
 369 +       reg &= ~NAC_PARTIAL_PAGE_EN;
 370 +       bcma_cc_write32(cc, NAND_ACC_CONTROL, reg);
 371 +
 372 +       from = (u32 *)buf;
 373 +       res = len;
 374 +       while (res > 0) {
 375 +               bcma_cc_write32(cc, NAND_CACHE_ADDR, 0);
 376 +               for (i = 0; i < cc->nflash.pagesize; i += 4, from++) {
 377 +                       if (i % 512 == 0)
 378 +                               bcma_cc_write32(cc, NAND_CMD_ADDR, i);
 379 +                       bcma_cc_write32(cc, NAND_CACHE_DATA, *from);
 380 +               }
 381 +               bcma_cc_write32(cc, NAND_CMD_ADDR, offset + cc->nflash.pagesize - 512);
 382 +               bcma_nflash_cmd(cc, NCMD_PAGE_PROG);
 383 +               if (bcma_nflash_poll(cc) < 0)
 384 +                       break;
 385 +               res -= cc->nflash.pagesize;
 386 +               offset += cc->nflash.pagesize;
 387 +       }
 388 +
 389 +       if (res <= 0)
 390 +               return 0;
 391 +       else
 392 +               return (len - res);
 393 +}
 394 +
 395 +/* Erase a region. Returns success (0) or failure (-1).
 396 + * Poll for completion.
 397 + */
 398 +int bcma_nflash_erase(struct bcma_drv_cc *cc, u32 offset)
 399 +{
 400 +       if ((offset >> 20) >= cc->nflash.size)
 401 +               return -1;
 402 +       if ((offset & (cc->nflash.blocksize - 1)) != 0)
 403 +               return -1;
 404 +
 405 +       bcma_cc_write32(cc, NAND_CMD_ADDR, offset);
 406 +       bcma_nflash_cmd(cc, NCMD_BLOCK_ERASE);
 407 +       if (bcma_nflash_poll(cc) < 0)
 408 +               return -1;
 409 +       return 0;
 410 +}
 411 --- a/drivers/bcma/driver_mips.c
 412 +++ b/drivers/bcma/driver_mips.c
 413 @@ -6,6 +6,7 @@
 414   * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
 415   * Copyright 2010, Bernhard Loos <bernhardloos@googlemail.com>
 416   * Copyright 2011, Hauke Mehrtens <hauke@hauke-m.de>
 417 + * Copyright (C) 2011-2012 Tathagata Das <tathagata@alumnux.com>
 418   *
 419   * Licensed under the GNU/GPL. See COPYING for details.
 420   */
 421 @@ -182,6 +183,17 @@ static void bcma_core_mips_flash_detect(
 422  {
 423         struct bcma_bus *bus = mcore->core->bus;
 424
 425 +       if (bus->drv_cc.core->id.rev == 38
 426 +               && (bus->drv_cc.status & (1 << 4)) != 0) {
 427 +#ifdef CONFIG_BCMA_NFLASH
 428 +               pr_info("found nand flash.\n");
 429 +               bus->drv_cc.flash_type = BCMA_NFLASH;
 430 +#else
 431 +               pr_info("NAND flash not supported.\n");
 432 +#endif
 433 +               return;
 434 +       }
 435 +
 436         switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
 437         case BCMA_CC_FLASHT_STSER:
 438         case BCMA_CC_FLASHT_ATSER:
 439 --- a/drivers/mtd/nand/Kconfig
 440 +++ b/drivers/mtd/nand/Kconfig
 441 @@ -536,4 +536,12 @@ config MTD_NAND_FSMC
 442           Enables support for NAND Flash chips on the ST Microelectronics
 443           Flexible Static Memory Controller (FSMC)
 444
 445 +config MTD_NAND_BCM47XX
 446 +       tristate "bcm47xx nand flash support"
 447 +       default y
 448 +       depends on BCM47XX
 449 +       select MTD_PARTITIONS
 450 +       help
 451 +         Support for bcm47xx nand flash
 452 +
 453  endif # MTD_NAND
 454 --- a/drivers/mtd/nand/Makefile
 455 +++ b/drivers/mtd/nand/Makefile
 456 @@ -49,5 +49,6 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC)    += mp
 457  obj-$(CONFIG_MTD_NAND_RICOH)           += r852.o
 458  obj-$(CONFIG_MTD_NAND_JZ4740)          += jz4740_nand.o
 459  obj-$(CONFIG_MTD_NAND_GPMI_NAND)       += gpmi-nand/
 460 +obj-$(CONFIG_MTD_NAND_BCM47XX)         += bcm47xx_nand.o
 461
 462  nand-objs := nand_base.o nand_bbt.o
 463 --- /dev/null
 464 +++ b/drivers/mtd/nand/bcm47xx_nand.c
 465 @@ -0,0 +1,506 @@
 466 +/*
 467 + * BCMA nand flash interface
 468 + *
 469 + * Copyright (C) 2011-2012 Tathagata Das <tathagata@alumnux.com>
 470 + * Copyright 2010, Broadcom Corporation
 471 + *
 472 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
 473 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
 474 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
 475 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
 476 + *
 477 + */
 478 +
 479 +#define pr_fmt(fmt) "bcm47xx_nflash: " fmt
 480 +#include <linux/module.h>
 481 +#include <linux/slab.h>
 482 +#include <linux/ioport.h>
 483 +#include <linux/sched.h>
 484 +#include <linux/mtd/mtd.h>
 485 +#include <linux/mtd/map.h>
 486 +#include <linux/mtd/partitions.h>
 487 +#include <linux/errno.h>
 488 +#include <linux/delay.h>
 489 +#include <linux/platform_device.h>
 490 +#include <bcm47xx.h>
 491 +#include <bus.h>
 492 +#include <linux/cramfs_fs.h>
 493 +#include <linux/romfs_fs.h>
 494 +#include <linux/magic.h>
 495 +#include <linux/byteorder/generic.h>
 496 +#include <linux/mtd/bcm47xx_nand.h>
 497 +#include <linux/mtd/nand.h>
 498 +
 499 +static int bcm47xx_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip);
 500 +static int bcm47xx_erase(struct mtd_info *mtd, unsigned int addr, unsigned int len);
 501 +
 502 +/* Private Global variable */
 503 +static u32 read_offset = 0;
 504 +static u32 write_offset;
 505 +
 506 +static int
 507 +nflash_mtd_poll(struct bcm47xx_nflash *nflash, unsigned int offset, int timeout)
 508 +{
 509 +       unsigned long now = jiffies;
 510 +       int ret = 0;
 511 +
 512 +       for (;;) {
 513 +               if (!bcma_nflash_poll(nflash->bcc)) {
 514 +                       ret = 0;
 515 +                       break;
 516 +               }
 517 +               if (time_after(jiffies, now + timeout)) {
 518 +                       pr_err("timeout while polling\n");
 519 +                       ret = -ETIMEDOUT;
 520 +                       break;
 521 +               }
 522 +               udelay(1);
 523 +       }
 524 +
 525 +       return ret;
 526 +}
 527 +
 528 +static int
 529 +bcm47xx_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
 530 +{
 531 +       struct nand_chip *nchip = (struct nand_chip *)mtd->priv;
 532 +       struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
 533 +       int bytes, ret = 0;
 534 +       u32 extra = 0;
 535 +       u8 *tmpbuf = NULL;
 536 +       int size;
 537 +       u32 offset, blocksize, mask, off;
 538 +       u32 skip_bytes = 0;
 539 +       int need_copy = 0;
 540 +       u8 *ptr = NULL;
 541 +
 542 +       /* Check address range */
 543 +       if (!len)
 544 +               return 0;
 545 +       if ((from + len) > mtd->size)
 546 +               return -EINVAL;
 547 +       offset = from;
 548 +       if ((offset & (NFL_SECTOR_SIZE - 1)) != 0) {
 549 +               extra = offset & (NFL_SECTOR_SIZE - 1);
 550 +               offset -= extra;
 551 +               len += extra;
 552 +               need_copy = 1;
 553 +       }
 554 +       size = (len + (NFL_SECTOR_SIZE - 1)) & ~(NFL_SECTOR_SIZE - 1);
 555 +       if (size != len) {
 556 +               need_copy = 1;
 557 +       }
 558 +       if (!need_copy) {
 559 +               ptr = buf;
 560 +       } else {
 561 +               tmpbuf = (u8 *)kmalloc(size, GFP_KERNEL);
 562 +               ptr = tmpbuf;
 563 +       }
 564 +
 565 +       blocksize = mtd->erasesize;
 566 +       mask = blocksize - 1;
 567 +       *retlen = 0;
 568 +       while (len > 0) {
 569 +               off = offset + skip_bytes;
 570 +               if ((bytes = bcma_nflash_read(nflash->bcc, off, NFL_SECTOR_SIZE, ptr)) < 0) {
 571 +                       ret = bytes;
 572 +                       goto done;
 573 +               }
 574 +               if (bytes > len)
 575 +                       bytes = len;
 576 +               offset += bytes;
 577 +               len -= bytes;
 578 +               ptr += bytes;
 579 +               *retlen += bytes;
 580 +       }
 581 +
 582 +done:
 583 +       if (tmpbuf) {
 584 +               *retlen -= extra;
 585 +               memcpy(buf, tmpbuf+extra, *retlen);
 586 +               kfree(tmpbuf);
 587 +       }
 588 +
 589 +       return ret;
 590 +}
 591 +
 592 +static void bcm47xx_write(struct mtd_info *mtd, u32 to, const u_char *buf, u32 len)
 593 +{
 594 +       struct nand_chip *nchip = (struct nand_chip *)mtd->priv;
 595 +       struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
 596 +       u32 offset, blocksize, mask, off;
 597 +       int read_len;
 598 +       u32 copy_len, write_len, from;
 599 +       u_char *write_ptr, *block;
 600 +       const u_char *ptr;
 601 +       int ret, bytes;
 602 +
 603 +       /* Check address range */
 604 +       if (!len) {
 605 +               pr_err("Error: Attempted to write too small data\n");
 606 +               return;
 607 +       }
 608 +
 609 +       if (!to)
 610 +               return;
 611 +
 612 +       if ((to + len) > mtd->size) {
 613 +               pr_err("Error: Attempted to write too large data\n");
 614 +               return;
 615 +       }
 616 +
 617 +       ptr = buf;
 618 +       block = NULL;
 619 +       offset = to;
 620 +       blocksize = mtd->erasesize;
 621 +       if (!(block = kmalloc(blocksize, GFP_KERNEL)))
 622 +               return;
 623 +       mask = blocksize - 1;
 624 +       while (len) {
 625 +               /* Align offset */
 626 +               from = offset & ~mask;
 627 +               /* Copy existing data into holding block if necessary */
 628 +               if (((offset & (blocksize-1)) != 0) || (len < blocksize)) {
 629 +                       if ((ret = bcm47xx_read(mtd, from, blocksize, &read_len, block)))
 630 +                               goto done;
 631 +                       if (read_len != blocksize) {
 632 +                               ret = -EINVAL;
 633 +                               goto done;
 634 +                       }
 635 +               }
 636 +
 637 +               /* Copy input data into holding block */
 638 +               copy_len = min(len, blocksize - (offset & mask));
 639 +               memcpy(block + (offset & mask), ptr, copy_len);
 640 +               off = (uint) from;
 641 +               /* Erase block */
 642 +               if ((ret = bcm47xx_erase(mtd, off, blocksize)) < 0)
 643 +                       goto done;
 644 +               /* Write holding block */
 645 +               write_ptr = block;
 646 +               write_len = blocksize;
 647 +               if ((bytes = bcma_nflash_write(nflash->bcc, (uint)from, (uint)write_len, (u8 *) write_ptr)) != 0) {
 648 +                       ret = bytes;
 649 +                       goto done;
 650 +               }
 651 +               offset += copy_len;
 652 +               if (len < copy_len)
 653 +                       len = 0;
 654 +               else
 655 +                       len -= copy_len;
 656 +               ptr += copy_len;
 657 +       }
 658 +
 659 +done:
 660 +       if (block)
 661 +               kfree(block);
 662 +       return;
 663 +}
 664 +
 665 +static int bcm47xx_erase(struct mtd_info *mtd, unsigned int addr, unsigned int len)
 666 +{
 667 +       struct nand_chip *nchip = (struct nand_chip *)mtd->priv;
 668 +       struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
 669 +
 670 +       /* Check address range */
 671 +       if (!len)
 672 +               return 1;
 673 +       if ((addr + len) > mtd->size)
 674 +               return 1;
 675 +
 676 +       if (bcma_nflash_erase(nflash->bcc, addr)) {
 677 +               pr_err("ERASE: nflash erase error\n");
 678 +               return 1;
 679 +       }
 680 +
 681 +       if (nflash_mtd_poll(nflash, addr, 10 * HZ)) {
 682 +               pr_err("ERASE: nflash_mtd_poll error\n");
 683 +               return 1;
 684 +       }
 685 +
 686 +       return 0;
 687 +}
 688 +
 689 +/* This functions is used by upper layer to checks if device is ready */
 690 +static int bcm47xx_dev_ready(struct mtd_info *mtd)
 691 +{
 692 +       return 1;
 693 +}
 694 +
 695 +/* Issue a nand flash command */
 696 +static inline void bcm47xx_nflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
 697 +{
 698 +       bcma_cc_write32(cc, NAND_CMD_START, opcode);
 699 +       bcma_cc_read32(cc,  NAND_CMD_START);
 700 +}
 701 +
 702 +static void bcm47xx_command(struct mtd_info *mtd, unsigned command,
 703 +                               int column, int page_addr)
 704 +{
 705 +       struct nand_chip *nchip = (struct nand_chip *)mtd->priv;
 706 +       struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
 707 +       u32 pagesize = 1 << nchip->page_shift;
 708 +
 709 +       /* Command pre-processing step */
 710 +       switch (command) {
 711 +       case NAND_CMD_RESET:
 712 +               bcm47xx_nflash_cmd(nflash->bcc, NCMD_FLASH_RESET);
 713 +               break;
 714 +
 715 +       case NAND_CMD_STATUS:
 716 +               nflash->next_opcode = NAND_CMD_STATUS;
 717 +               read_offset = 0;
 718 +               write_offset = 0;
 719 +               break;
 720 +
 721 +       case NAND_CMD_READ0:
 722 +               read_offset = page_addr * pagesize;
 723 +               nflash->next_opcode = 0;
 724 +               break;
 725 +
 726 +       case NAND_CMD_READOOB:
 727 +               read_offset = page_addr * pagesize;
 728 +               nflash->next_opcode = 0;
 729 +               break;
 730 +
 731 +       case NAND_CMD_SEQIN:
 732 +               write_offset = page_addr * pagesize;
 733 +               nflash->next_opcode = 0;
 734 +               break;
 735 +
 736 +       case NAND_CMD_PAGEPROG:
 737 +               nflash->next_opcode = 0;
 738 +               break;
 739 +
 740 +       case NAND_CMD_READID:
 741 +               read_offset = column;
 742 +               bcm47xx_nflash_cmd(nflash->bcc, NCMD_ID_RD);
 743 +               nflash->next_opcode = NAND_DEVID;
 744 +               break;
 745 +
 746 +       case NAND_CMD_ERASE1:
 747 +               nflash->next_opcode = 0;
 748 +               bcm47xx_erase(mtd, page_addr*pagesize, pagesize);
 749 +               break;
 750 +
 751 +       case NAND_CMD_ERASE2:
 752 +               break;
 753 +
 754 +       case NAND_CMD_RNDOUT:
 755 +               if (column > mtd->writesize)
 756 +                       read_offset += (column - mtd->writesize);
 757 +               else
 758 +                       read_offset += column;
 759 +               break;
 760 +
 761 +       default:
 762 +               pr_err("COMMAND not supported %x\n", command);
 763 +               nflash->next_opcode = 0;
 764 +               break;
 765 +       }
 766 +}
 767 +
 768 +/* This function is used by upper layer for select and
 769 + * deselect of the NAND chip.
 770 + * It is dummy function. */
 771 +static void bcm47xx_select_chip(struct mtd_info *mtd, int chip)
 772 +{
 773 +}
 774 +
 775 +static u_char bcm47xx_read_byte(struct mtd_info *mtd)
 776 +{
 777 +       struct nand_chip *nchip = mtd->priv;
 778 +       struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
 779 +       uint8_t ret = 0;
 780 +       static u32 id;
 781 +
 782 +       if (nflash->next_opcode == 0)
 783 +               return ret;
 784 +
 785 +       if (nflash->next_opcode == NAND_CMD_STATUS)
 786 +               return NAND_STATUS_WP;
 787 +
 788 +       id = bcma_cc_read32(nflash->bcc, nflash->next_opcode);
 789 +
 790 +       if (nflash->next_opcode == NAND_DEVID) {
 791 +               ret = (id >> (8*read_offset)) & 0xff;
 792 +               read_offset++;
 793 +       }
 794 +
 795 +       return ret;
 796 +}
 797 +
 798 +static uint16_t bcm47xx_read_word(struct mtd_info *mtd)
 799 +{
 800 +       loff_t from = read_offset;
 801 +       uint16_t buf = 0;
 802 +       int bytes;
 803 +
 804 +       bcm47xx_read(mtd, from, sizeof(buf), &bytes, (u_char *)&buf);
 805 +       return buf;
 806 +}
 807 +
 808 +/* Write data of length len to buffer buf. The data to be
 809 + * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 810 + * Operation by the NFC, the data is written to NAND Flash */
 811 +static void bcm47xx_write_buf(struct mtd_info *mtd,
 812 +                               const u_char *buf, int len)
 813 +{
 814 +       bcm47xx_write(mtd, write_offset, buf, len);
 815 +}
 816 +
 817 +/* Read the data buffer from the NAND Flash. To read the data from NAND
 818 + * Flash first the data output cycle is initiated by the NFC, which copies
 819 + * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 820 + */
 821 +static void bcm47xx_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 822 +{
 823 +       loff_t from = read_offset;
 824 +       int bytes;
 825 +
 826 +       bcm47xx_read(mtd, from, len, &bytes, buf);
 827 +}
 828 +
 829 +/* Used by the upper layer to verify the data in NAND Flash
 830 + * with the data in the buf. */
 831 +static int bcm47xx_verify_buf(struct mtd_info *mtd,
 832 +                               const u_char *buf, int len)
 833 +{
 834 +       return -EFAULT;
 835 +}
 836 +
 837 +static int bcm47xx_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 838 +{
 839 +       struct nand_chip *nchip = mtd->priv;
 840 +       struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
 841 +       int i;
 842 +       uint off;
 843 +       u32 pagesize = 1 << nchip->page_shift;
 844 +       u32 blocksize = mtd->erasesize;
 845 +
 846 +       if ((ofs >> 20) >= nflash->size)
 847 +               return 1;
 848 +       if ((ofs & (blocksize - 1)) != 0)
 849 +               return 1;
 850 +
 851 +       for (i = 0; i < 2; i++) {
 852 +               off = ofs + pagesize;
 853 +               bcma_cc_write32(nflash->bcc, NAND_CMD_ADDR, off);
 854 +               bcm47xx_nflash_cmd(nflash->bcc, NCMD_SPARE_RD);
 855 +               if (bcma_nflash_poll(nflash->bcc) < 0)
 856 +                       break;
 857 +               if ((bcma_cc_read32(nflash->bcc, NAND_INTFC_STATUS) & NIST_SPARE_VALID) != NIST_SPARE_VALID)
 858 +                       return 1;
 859 +               if ((bcma_cc_read32(nflash->bcc, NAND_SPARE_RD0) & 0xff) != 0xff)
 860 +                       return 1;
 861 +       }
 862 +       return 0;
 863 +}
 864 +
 865 +const char *part_probes[] = { "cmdlinepart", NULL };
 866 +static int bcm47xx_probe(struct platform_device *pdev)
 867 +{
 868 +       struct nand_chip *nchip;
 869 +       struct mtd_info *mtd;
 870 +       struct bcm47xx_nflash *nflash = dev_get_platdata(&pdev->dev);
 871 +       int ret = 0;
 872 +
 873 +       mtd = &nflash->mtd;
 874 +       nchip = &nflash->nand;
 875 +
 876 +       /* Register with MTD */
 877 +       mtd->priv = nchip;
 878 +       mtd->owner = THIS_MODULE;
 879 +       mtd->dev.parent = &pdev->dev;
 880 +
 881 +       /* 50 us command delay time */
 882 +       nchip->chip_delay = 50;
 883 +
 884 +       nchip->priv = nflash;
 885 +       nchip->dev_ready = bcm47xx_dev_ready;
 886 +       nchip->cmdfunc = bcm47xx_command;
 887 +       nchip->select_chip = bcm47xx_select_chip;
 888 +       nchip->read_byte = bcm47xx_read_byte;
 889 +       nchip->read_word = bcm47xx_read_word;
 890 +       nchip->write_buf = bcm47xx_write_buf;
 891 +       nchip->read_buf = bcm47xx_read_buf;
 892 +       nchip->verify_buf = bcm47xx_verify_buf;
 893 +       nchip->block_bad = bcm47xx_block_bad;
 894 +       nchip->options = NAND_SKIP_BBTSCAN;
 895 +
 896 +       /* Not known */
 897 +       nchip->ecc.mode = NAND_ECC_NONE;
 898 +
 899 +       /* first scan to find the device and get the page size */
 900 +       if (nand_scan_ident(mtd, 1, NULL)) {
 901 +               pr_err("nand_scan_ident failed\n");
 902 +               ret = -ENXIO;
 903 +               goto done;
 904 +       }
 905 +       nflash->bcc->nflash.size = mtd->size;
 906 +       nflash->bcc->nflash.pagesize = 1 << nchip->page_shift;
 907 +       nflash->bcc->nflash.blocksize = mtd->erasesize;
 908 +       bcm47xx_nflash.size = mtd->size;
 909 +
 910 +       /* second phase scan */
 911 +       if (nand_scan_tail(mtd)) {
 912 +               pr_err("nand_scan_tail failed\n");
 913 +               ret = -ENXIO;
 914 +               goto done;
 915 +       }
 916 +
 917 +       mtd->name = "bcm47xx-nflash";
 918 +       mtd->flags |= MTD_WRITEABLE;
 919 +       ret = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
 920 +
 921 +       if (ret) {
 922 +               pr_err("mtd_device_register failed\n");
 923 +               return ret;
 924 +       }
 925 +
 926 +       return 0;
 927 +
 928 +done:
 929 +       return ret;
 930 +}
 931 +
 932 +static int __devexit bcm47xx_remove(struct platform_device *pdev)
 933 +{
 934 +       struct bcm47xx_nflash *nflash = dev_get_platdata(&pdev->dev);
 935 +       struct mtd_info *mtd = &nflash->mtd;
 936 +
 937 +       if (nflash) {
 938 +               /* Release resources, unregister device */
 939 +               nand_release(mtd);
 940 +       }
 941 +
 942 +       return 0;
 943 +}
 944 +
 945 +static struct platform_driver bcm47xx_driver = {
 946 +       .remove = __devexit_p(bcm47xx_remove),
 947 +       .driver = {
 948 +               .name = "bcm47xx_nflash",
 949 +               .owner = THIS_MODULE,
 950 +       },
 951 +};
 952 +
 953 +static int __init init_bcm47xx_nflash(void)
 954 +{
 955 +       int ret = platform_driver_probe(&bcm47xx_driver, bcm47xx_probe);
 956 +
 957 +       if (ret)
 958 +               pr_err("error registering platform driver: %i\n", ret);
 959 +       return ret;
 960 +}
 961 +
 962 +static void __exit exit_bcm47xx_nflash(void)
 963 +{
 964 +       platform_driver_unregister(&bcm47xx_driver);
 965 +}
 966 +
 967 +module_init(init_bcm47xx_nflash);
 968 +module_exit(exit_bcm47xx_nflash);
 969 +
 970 +MODULE_LICENSE("GPL");
 971 +MODULE_DESCRIPTION("BCM47XX NAND flash driver");
 972 --- a/include/linux/bcma/bcma_driver_chipcommon.h
 973 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
 974 @@ -422,6 +422,7 @@ struct bcma_chipcommon_pmu {
 975  enum bcma_flash_type {
 976         BCMA_PFLASH,
 977         BCMA_SFLASH,
 978 +       BCMA_NFLASH,
 979  };
 980
 981  struct bcma_pflash {
 982 @@ -438,6 +439,14 @@ struct bcma_sflash {
 983  };
 984  #endif /* CONFIG_BCMA_SFLASH */
 985
 986 +#ifdef CONFIG_BCMA_NFLASH
 987 +struct bcma_nflash {
 988 +       u32 blocksize;          /* Block size */
 989 +       u32 pagesize;           /* Page size */
 990 +       u32 size;               /* Total size in bytes */
 991 +};
 992 +#endif
 993 +
 994  struct bcma_serial_port {
 995         void *regs;
 996         unsigned long clockspeed;
 997 @@ -463,6 +472,9 @@ struct bcma_drv_cc {
 998  #ifdef CONFIG_BCMA_SFLASH
 999                 struct bcma_sflash sflash;
1000  #endif /* CONFIG_BCMA_SFLASH */
1001 +#ifdef CONFIG_BCMA_NFLASH
1002 +               struct bcma_nflash nflash;
1003 +#endif
1004         };
1005
1006         int nr_serial_ports;
1007 @@ -528,4 +540,13 @@ int bcma_sflash_write(struct bcma_drv_cc
1008  int bcma_sflash_erase(struct bcma_drv_cc *cc, u32 offset);
1009  #endif /* CONFIG_BCMA_SFLASH */
1010
1011 +#ifdef CONFIG_BCMA_NFLASH
1012 +/* Chipcommon nflash support. */
1013 +int bcma_nflash_read(struct bcma_drv_cc *cc, u32 offset, u32 len, u8 *buf);
1014 +int bcma_nflash_poll(struct bcma_drv_cc *cc);
1015 +int bcma_nflash_write(struct bcma_drv_cc *cc, u32 offset, u32 len, const u8 *buf);
1016 +int bcma_nflash_erase(struct bcma_drv_cc *cc, u32 offset);
1017 +int bcma_nflash_commit(struct bcma_drv_cc *cc, u32 offset, u32 len, const u8 *buf);
1018 +#endif
1019 +
1020  #endif /* LINUX_BCMA_DRIVER_CC_H_ */
1021 --- /dev/null
1022 +++ b/include/linux/mtd/bcm47xx_nand.h
1023 @@ -0,0 +1,134 @@
1024 +/*
1025 + * Broadcom chipcommon NAND flash interface
1026 + *
1027 + * Copyright (C) 2011-2012 Tathagata Das <tathagata@alumnux.com>
1028 + * Copyright (C) 2009, Broadcom Corporation
1029 + * All Rights Reserved.
1030 + *
1031 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1032 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1033 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1034 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1035 + *
1036 + */
1037 +
1038 +#ifndef _nflash_h_
1039 +#define _nflash_h_
1040 +
1041 +#define  NAND_FLASH1                                           0x1fc00000  /* MIPS Flash Region 1 */
1042 +
1043 +/* nand_cmd_start commands */
1044 +#define        NCMD_NULL                                               0
1045 +#define        NCMD_PAGE_RD                                    1
1046 +#define        NCMD_SPARE_RD                                   2
1047 +#define        NCMD_STATUS_RD                                  3
1048 +#define        NCMD_PAGE_PROG                                  4
1049 +#define        NCMD_SPARE_PROG                         5
1050 +#define        NCMD_COPY_BACK                                  6
1051 +#define        NCMD_ID_RD                                              7
1052 +#define        NCMD_BLOCK_ERASE                                8
1053 +#define        NCMD_FLASH_RESET                                9
1054 +#define        NCMD_LOCK                                               0xa
1055 +#define        NCMD_LOCK_DOWN                                  0xb
1056 +#define        NCMD_UNLOCK                                             0xc
1057 +#define        NCMD_LOCK_STATUS                                0xd
1058 +
1059 +/* nand_acc_control */
1060 +#define        NAC_RD_ECC_EN                                   0x80000000
1061 +#define        NAC_WR_ECC_EN                                   0x40000000
1062 +#define        NAC_RD_ECC_BLK0_EN                      0x20000000
1063 +#define        NAC_FAST_PGM_RDIN                               0x10000000
1064 +#define        NAC_RD_ERASED_ECC_EN                    0x08000000
1065 +#define        NAC_PARTIAL_PAGE_EN                     0x04000000
1066 +#define        NAC_PAGE_HIT_EN                         0x01000000
1067 +#define        NAC_ECC_LEVEL0                                  0x00f00000
1068 +#define        NAC_ECC_LEVEL                                   0x000f0000
1069 +#define        NAC_SPARE_SIZE0                         0x00003f00
1070 +#define        NAC_SPARE_SIZE                                  0x0000003f
1071 +
1072 +/* nand_config */
1073 +#define        NCF_CONFIG_LOCK                         0x80000000
1074 +#define        NCF_BLOCK_SIZE_MASK                     0x70000000
1075 +#define        NCF_BLOCK_SIZE_SHIFT                    28
1076 +#define        NCF_DEVICE_SIZE_MASK                    0x0f000000
1077 +#define        NCF_DEVICE_SIZE_SHIFT           24
1078 +#define        NCF_DEVICE_WIDTH                                0x00800000
1079 +#define        NCF_PAGE_SIZE_MASK                      0x00300000
1080 +#define        NCF_PAGE_SIZE_SHIFT                     20
1081 +#define        NCF_FULL_ADDR_BYTES_MASK        0x00070000
1082 +#define        NCF_FULL_ADDR_BYTES_SHIFT       16
1083 +#define        NCF_COL_ADDR_BYTES_MASK         0x00007000
1084 +#define        NCF_COL_ADDR_BYTES_SHIFT        12
1085 +#define        NCF_BLK_ADDR_BYTES_MASK         0x00000700
1086 +#define        NCF_BLK_ADDR_BYTES_SHIFT        8
1087 +
1088 +/* nand_intfc_status */
1089 +#define        NIST_CTRL_READY                         0x80000000
1090 +#define        NIST_FLASH_READY                                0x40000000
1091 +#define        NIST_CACHE_VALID                                0x20000000
1092 +#define        NIST_SPARE_VALID                                0x10000000
1093 +#define        NIST_ERASED                                             0x08000000
1094 +#define        NIST_STATUS                                             0x000000ff
1095 +
1096 +#define        NFL_SECTOR_SIZE                         512
1097 +
1098 +#define        NFL_TABLE_END                                   0xffffffff
1099 +#define        NFL_BOOT_SIZE                                   0x200000
1100 +#define        NFL_BOOT_OS_SIZE                                0x2000000
1101 +
1102 +/* Nand flash MLC controller registers (corerev >= 38) */
1103 +#define        NAND_REVISION                                   0xC00
1104 +#define        NAND_CMD_START                                  0xC04
1105 +#define        NAND_CMD_ADDR_X                         0xC08
1106 +#define        NAND_CMD_ADDR                                   0xC0C
1107 +#define        NAND_CMD_END_ADDR                               0xC10
1108 +#define        NAND_CS_NAND_SELECT                     0xC14
1109 +#define        NAND_CS_NAND_XOR                                0xC18
1110 +#define        NAND_SPARE_RD0                                  0xC20
1111 +#define        NAND_SPARE_RD4                                  0xC24
1112 +#define        NAND_SPARE_RD8                                  0xC28
1113 +#define        NAND_SPARE_RD12                         0xC2C
1114 +#define        NAND_SPARE_WR0                                  0xC30
1115 +#define        NAND_SPARE_WR4                                  0xC34
1116 +#define        NAND_SPARE_WR8                                  0xC38
1117 +#define        NAND_SPARE_WR12                         0xC3C
1118 +#define        NAND_ACC_CONTROL                                0xC40
1119 +#define        NAND_CONFIG                                             0xC48
1120 +#define        NAND_TIMING_1                                   0xC50
1121 +#define        NAND_TIMING_2                                   0xC54
1122 +#define        NAND_SEMAPHORE                                  0xC58
1123 +#define        NAND_DEVID                                              0xC60
1124 +#define        NAND_DEVID_X                                    0xC64
1125 +#define        NAND_BLOCK_LOCK_STATUS          0xC68
1126 +#define        NAND_INTFC_STATUS                               0xC6C
1127 +#define        NAND_ECC_CORR_ADDR_X                    0xC70
1128 +#define        NAND_ECC_CORR_ADDR                      0xC74
1129 +#define        NAND_ECC_UNC_ADDR_X                     0xC78
1130 +#define        NAND_ECC_UNC_ADDR                               0xC7C
1131 +#define        NAND_READ_ERROR_COUNT           0xC80
1132 +#define        NAND_CORR_STAT_THRESHOLD        0xC84
1133 +#define        NAND_READ_ADDR_X                                0xC90
1134 +#define        NAND_READ_ADDR                                  0xC94
1135 +#define        NAND_PAGE_PROGRAM_ADDR_X        0xC98
1136 +#define        NAND_PAGE_PROGRAM_ADDR          0xC9C
1137 +#define        NAND_COPY_BACK_ADDR_X           0xCA0
1138 +#define        NAND_COPY_BACK_ADDR                     0xCA4
1139 +#define        NAND_BLOCK_ERASE_ADDR_X         0xCA8
1140 +#define        NAND_BLOCK_ERASE_ADDR           0xCAC
1141 +#define        NAND_INV_READ_ADDR_X                    0xCB0
1142 +#define        NAND_INV_READ_ADDR                      0xCB4
1143 +#define        NAND_BLK_WR_PROTECT                     0xCC0
1144 +#define        NAND_ACC_CONTROL_CS1                    0xCD0
1145 +#define        NAND_CONFIG_CS1                         0xCD4
1146 +#define        NAND_TIMING_1_CS1                               0xCD8
1147 +#define        NAND_TIMING_2_CS1                               0xCDC
1148 +#define        NAND_SPARE_RD16                         0xD30
1149 +#define        NAND_SPARE_RD20                         0xD34
1150 +#define        NAND_SPARE_RD24                         0xD38
1151 +#define        NAND_SPARE_RD28                         0xD3C
1152 +#define        NAND_CACHE_ADDR                         0xD40
1153 +#define        NAND_CACHE_DATA                         0xD44
1154 +#define        NAND_CTRL_CONFIG                                0xD48
1155 +#define        NAND_CTRL_STATUS                                0xD4C
1156 +
1157 +#endif /* _nflash_h_ */