target/linux/brcm47xx/patches-3.14/159-cpu_fixes.patch

   1 --- a/arch/mips/include/asm/r4kcache.h
   2 +++ b/arch/mips/include/asm/r4kcache.h
   3 @@ -18,6 +18,20 @@
   4  #include <asm/cpu-type.h>
   5  #include <asm/mipsmtregs.h>
   6
   7 +#ifdef CONFIG_BCM47XX
   8 +#include <asm/paccess.h>
   9 +#include <linux/ssb/ssb.h>
  10 +#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE)))
  11 +
  12 +#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
  13 +#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
  14 +#else
  15 +#define BCM4710_DUMMY_RREG()
  16 +
  17 +#define BCM4710_FILL_TLB(addr)
  18 +#define BCM4710_PROTECTED_FILL_TLB(addr)
  19 +#endif
  20 +
  21  /*
  22   * This macro return a properly sign-extended address suitable as base address
  23   * for indexed cache operations.  Two issues here:
  24 @@ -151,6 +165,7 @@ static inline void flush_icache_line_ind
  25  static inline void flush_dcache_line_indexed(unsigned long addr)
  26  {
  27         __dflush_prologue
  28 +       BCM4710_DUMMY_RREG();
  29         cache_op(Index_Writeback_Inv_D, addr);
  30         __dflush_epilogue
  31  }
  32 @@ -178,6 +193,7 @@ static inline void flush_icache_line(uns
  33  static inline void flush_dcache_line(unsigned long addr)
  34  {
  35         __dflush_prologue
  36 +       BCM4710_DUMMY_RREG();
  37         cache_op(Hit_Writeback_Inv_D, addr);
  38         __dflush_epilogue
  39  }
  40 @@ -185,6 +201,7 @@ static inline void flush_dcache_line(uns
  41  static inline void invalidate_dcache_line(unsigned long addr)
  42  {
  43         __dflush_prologue
  44 +       BCM4710_DUMMY_RREG();
  45         cache_op(Hit_Invalidate_D, addr);
  46         __dflush_epilogue
  47  }
  48 @@ -223,6 +240,7 @@ static inline void protected_flush_icach
  49                 break;
  50
  51         default:
  52 +               BCM4710_DUMMY_RREG();
  53                 protected_cache_op(Hit_Invalidate_I, addr);
  54                 break;
  55         }
  56 @@ -236,6 +254,7 @@ static inline void protected_flush_icach
  57   */
  58  static inline void protected_writeback_dcache_line(unsigned long addr)
  59  {
  60 +       BCM4710_DUMMY_RREG();
  61         protected_cache_op(Hit_Writeback_Inv_D, addr);
  62  }
  63
  64 @@ -356,8 +375,51 @@ static inline void invalidate_tcache_pag
  65                 : "r" (base),                                           \
  66                   "i" (op));
  67
  68 +static inline void blast_dcache(void)
  69 +{
  70 +       unsigned long start = KSEG0;
  71 +       unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
  72 +       unsigned long end = (start + dcache_size);
  73 +
  74 +       do {
  75 +               BCM4710_DUMMY_RREG();
  76 +               cache_op(Index_Writeback_Inv_D, start);
  77 +               start += current_cpu_data.dcache.linesz;
  78 +       } while(start < end);
  79 +}
  80 +
  81 +static inline void blast_dcache_page(unsigned long page)
  82 +{
  83 +       unsigned long start = page;
  84 +       unsigned long end = start + PAGE_SIZE;
  85 +
  86 +       BCM4710_FILL_TLB(start);
  87 +       do {
  88 +               BCM4710_DUMMY_RREG();
  89 +               cache_op(Hit_Writeback_Inv_D, start);
  90 +               start += current_cpu_data.dcache.linesz;
  91 +       } while(start < end);
  92 +}
  93 +
  94 +static inline void blast_dcache_page_indexed(unsigned long page)
  95 +{
  96 +       unsigned long start = page;
  97 +       unsigned long end = start + PAGE_SIZE;
  98 +       unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
  99 +       unsigned long ws_end = current_cpu_data.dcache.ways <<
 100 +                              current_cpu_data.dcache.waybit;
 101 +       unsigned long ws, addr;
 102 +       for (ws = 0; ws < ws_end; ws += ws_inc) {
 103 +               start = page + ws;
 104 +               for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
 105 +                       BCM4710_DUMMY_RREG();
 106 +                       cache_op(Index_Writeback_Inv_D, addr);
 107 +               }
 108 +       }
 109 +}
 110 +
 111  /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
 112 -#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra)   \
 113 +#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \
 114  static inline void extra##blast_##pfx##cache##lsize(void)              \
 115  {                                                                      \
 116         unsigned long start = INDEX_BASE;                               \
 117 @@ -369,6 +431,7 @@ static inline void extra##blast_##pfx##c
 118                                                                         \
 119         __##pfx##flush_prologue                                         \
 120                                                                         \
 121 +       war                                                             \
 122         for (ws = 0; ws < ws_end; ws += ws_inc)                         \
 123                 for (addr = start; addr < end; addr += lsize * 32)      \
 124                         cache##lsize##_unroll32(addr|ws, indexop);      \
 125 @@ -383,6 +446,7 @@ static inline void extra##blast_##pfx##c
 126                                                                         \
 127         __##pfx##flush_prologue                                         \
 128                                                                         \
 129 +       war                                                             \
 130         do {                                                            \
 131                 cache##lsize##_unroll32(start, hitop);                  \
 132                 start += lsize * 32;                                    \
 133 @@ -401,6 +465,8 @@ static inline void extra##blast_##pfx##c
 134                                current_cpu_data.desc.waybit;            \
 135         unsigned long ws, addr;                                         \
 136                                                                         \
 137 +       war                                                             \
 138 +                                                                       \
 139         __##pfx##flush_prologue                                         \
 140                                                                         \
 141         for (ws = 0; ws < ws_end; ws += ws_inc)                         \
 142 @@ -410,37 +476,40 @@ static inline void extra##blast_##pfx##c
 143         __##pfx##flush_epilogue                                         \
 144  }
 145
 146 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
 147 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
 148 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
 149 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
 150 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
 151 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
 152 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
 153 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
 154 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
 155 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
 156 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
 157 -
 158 -__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
 159 -__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
 160 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
 161 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
 162 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
 163 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
 164 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , )
 165 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);)
 166 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , )
 167 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, , )
 168 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, , BCM4710_FILL_TLB(start);)
 169 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_, BCM4710_FILL_TLB(start);)
 170 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, , )
 171 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, , )
 172 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, , BCM4710_FILL_TLB(start);)
 173 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, , )
 174 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , )
 175 +
 176 +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , )
 177 +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , )
 178 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , )
 179 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, , )
 180 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , )
 181 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , )
 182 +
 183
 184  /* build blast_xxx_range, protected_blast_xxx_range */
 185 -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra)       \
 186 +#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra, war, war2)    \
 187  static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
 188                                                     unsigned long end)  \
 189  {                                                                      \
 190         unsigned long lsize = cpu_##desc##_line_size();                 \
 191         unsigned long addr = start & ~(lsize - 1);                      \
 192         unsigned long aend = (end - 1) & ~(lsize - 1);                  \
 193 +       war                                                             \
 194                                                                         \
 195         __##pfx##flush_prologue                                         \
 196                                                                         \
 197         while (1) {                                                     \
 198 +               war2                                            \
 199                 prot##cache_op(hitop, addr);                            \
 200                 if (addr == aend)                                       \
 201                         break;                                          \
 202 @@ -450,15 +519,15 @@ static inline void prot##extra##blast_##
 203         __##pfx##flush_epilogue                                         \
 204  }
 205
 206 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
 207 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
 208 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
 209 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
 210 +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , )
 211 +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , )
 212  __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
 213 -       protected_, loongson2_)
 214 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
 215 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
 216 +       protected_, loongson2_, , )
 217 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
 218 +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , , , )
 219  /* blast_inv_dcache_range */
 220 -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
 221 -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
 222 +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();)
 223 +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , )
 224
 225  #endif /* _ASM_R4KCACHE_H */
 226 --- a/arch/mips/include/asm/stackframe.h
 227 +++ b/arch/mips/include/asm/stackframe.h
 228 @@ -436,6 +436,10 @@
 229                 .macro  RESTORE_SP_AND_RET
 230                 LONG_L  sp, PT_R29(sp)
 231                 .set    mips3
 232 +#ifdef CONFIG_BCM47XX
 233 +               nop
 234 +               nop
 235 +#endif
 236                 eret
 237                 .set    mips0
 238                 .endm
 239 --- a/arch/mips/kernel/genex.S
 240 +++ b/arch/mips/kernel/genex.S
 241 @@ -46,6 +46,10 @@
 242  NESTED(except_vec3_generic, 0, sp)
 243         .set    push
 244         .set    noat
 245 +#ifdef CONFIG_BCM47XX
 246 +       nop
 247 +       nop
 248 +#endif
 249  #if R5432_CP0_INTERRUPT_WAR
 250         mfc0    k0, CP0_INDEX
 251  #endif
 252 --- a/arch/mips/mm/c-r4k.c
 253 +++ b/arch/mips/mm/c-r4k.c
 254 @@ -37,6 +37,9 @@
 255  #include <asm/traps.h>
 256  #include <asm/dma-coherence.h>
 257
 258 +/* For enabling BCM4710 cache workarounds */
 259 +int bcm4710 = 0;
 260 +
 261  /*
 262   * Special Variant of smp_call_function for use by cache functions:
 263   *
 264 @@ -113,6 +116,9 @@ static void r4k_blast_dcache_page_setup(
 265  {
 266         unsigned long  dc_lsize = cpu_dcache_line_size();
 267
 268 +       if (bcm4710)
 269 +               r4k_blast_dcache_page = blast_dcache_page;
 270 +       else
 271         if (dc_lsize == 0)
 272                 r4k_blast_dcache_page = (void *)cache_noop;
 273         else if (dc_lsize == 16)
 274 @@ -129,6 +135,9 @@ static void r4k_blast_dcache_page_indexe
 275  {
 276         unsigned long dc_lsize = cpu_dcache_line_size();
 277
 278 +       if (bcm4710)
 279 +               r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
 280 +       else
 281         if (dc_lsize == 0)
 282                 r4k_blast_dcache_page_indexed = (void *)cache_noop;
 283         else if (dc_lsize == 16)
 284 @@ -146,6 +155,9 @@ static void r4k_blast_dcache_setup(void)
 285  {
 286         unsigned long dc_lsize = cpu_dcache_line_size();
 287
 288 +       if (bcm4710)
 289 +               r4k_blast_dcache = blast_dcache;
 290 +       else
 291         if (dc_lsize == 0)
 292                 r4k_blast_dcache = (void *)cache_noop;
 293         else if (dc_lsize == 16)
 294 @@ -703,6 +715,8 @@ static void local_r4k_flush_cache_sigtra
 295         unsigned long addr = (unsigned long) arg;
 296
 297         R4600_HIT_CACHEOP_WAR_IMPL;
 298 +       BCM4710_PROTECTED_FILL_TLB(addr);
 299 +       BCM4710_PROTECTED_FILL_TLB(addr + 4);
 300         if (dc_lsize)
 301                 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 302         if (!cpu_icache_snoops_remote_store && scache_size)
 303 @@ -1403,6 +1417,17 @@ static void coherency_setup(void)
 304          * silly idea of putting something else there ...
 305          */
 306         switch (current_cpu_type()) {
 307 +       case CPU_BMIPS3300:
 308 +               {
 309 +                       u32 cm;
 310 +                       cm = read_c0_diag();
 311 +                       /* Enable icache */
 312 +                       cm |= (1 << 31);
 313 +                       /* Enable dcache */
 314 +                       cm |= (1 << 30);
 315 +                       write_c0_diag(cm);
 316 +               }
 317 +               break;
 318         case CPU_R4000PC:
 319         case CPU_R4000SC:
 320         case CPU_R4000MC:
 321 @@ -1449,6 +1474,15 @@ void r4k_cache_init(void)
 322         extern void build_copy_page(void);
 323         struct cpuinfo_mips *c = &current_cpu_data;
 324
 325 +       /* Check if special workarounds are required */
 326 +#ifdef CONFIG_BCM47XX
 327 +       if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
 328 +               printk("Enabling BCM4710A0 cache workarounds.\n");
 329 +               bcm4710 = 1;
 330 +       } else
 331 +#endif
 332 +               bcm4710 = 0;
 333 +
 334         probe_pcache();
 335         setup_scache();
 336
 337 @@ -1514,6 +1548,14 @@ void r4k_cache_init(void)
 338          */
 339         local_r4k___flush_cache_all(NULL);
 340
 341 +#ifdef CONFIG_BCM47XX
 342 +       {
 343 +               static void (*_coherency_setup)(void);
 344 +               _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
 345 +               _coherency_setup();
 346 +       }
 347 +#else
 348         coherency_setup();
 349 +#endif
 350         board_cache_error_setup = r4k_cache_error_setup;
 351  }
 352 --- a/arch/mips/mm/tlbex.c
 353 +++ b/arch/mips/mm/tlbex.c
 354 @@ -1280,6 +1280,9 @@ static void build_r4000_tlb_refill_handl
 355                         /* No need for uasm_i_nop */
 356                 }
 357
 358 +#ifdef CONFIG_BCM47XX
 359 +               uasm_i_nop(&p);
 360 +#endif
 361  #ifdef CONFIG_64BIT
 362                 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
 363  #else
 364 @@ -1840,6 +1843,9 @@ build_r4000_tlbchange_handler_head(u32 *
 365  {
 366         struct work_registers wr = build_get_work_registers(p);
 367
 368 +#ifdef CONFIG_BCM47XX
 369 +       uasm_i_nop(p);
 370 +#endif
 371  #ifdef CONFIG_64BIT
 372         build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
 373  #else