target/linux/brcm47xx/patches-3.0/0015-ssb-add-serial-flash-support.patch

   1 From 980da78179592a3f5f99168bc5af415835aa8c13 Mon Sep 17 00:00:00 2001
   2 From: Hauke Mehrtens <hauke@hauke-m.de>
   3 Date: Sun, 24 Jul 2011 20:20:36 +0200
   4 Subject: [PATCH 15/26] ssb: add serial flash support
   5
   6
   7 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
   8 ---
   9  drivers/ssb/Kconfig                       |    6 +
  10  drivers/ssb/Makefile                      |    1 +
  11  drivers/ssb/driver_chipcommon_sflash.c    |  556 +++++++++++++++++++++++++++++
  12  drivers/ssb/driver_mipscore.c             |    6 +
  13  drivers/ssb/ssb_private.h                 |    4 +
  14  include/linux/ssb/ssb_driver_chipcommon.h |   30 ++-
  15  6 files changed, 601 insertions(+), 2 deletions(-)
  16  create mode 100644 drivers/ssb/driver_chipcommon_sflash.c
  17
  18 --- a/drivers/ssb/Kconfig
  19 +++ b/drivers/ssb/Kconfig
  20 @@ -137,6 +137,12 @@ config SSB_DRIVER_MIPS
  21
  22           If unsure, say N
  23
  24 +config SSB_SFLASH
  25 +       bool
  26 +       depends on SSB_DRIVER_MIPS
  27 +       default y
  28 +
  29 +
  30  # Assumption: We are on embedded, if we compile the MIPS core.
  31  config SSB_EMBEDDED
  32         bool
  33 --- a/drivers/ssb/Makefile
  34 +++ b/drivers/ssb/Makefile
  35 @@ -11,6 +11,7 @@ ssb-$(CONFIG_SSB_SDIOHOST)            += sdio.o
  36  # built-in drivers
  37  ssb-y                                  += driver_chipcommon.o
  38  ssb-y                                  += driver_chipcommon_pmu.o
  39 +ssb-$(CONFIG_SSB_SFLASH)               += driver_chipcommon_sflash.o
  40  ssb-$(CONFIG_SSB_DRIVER_MIPS)          += driver_mipscore.o
  41  ssb-$(CONFIG_SSB_DRIVER_EXTIF)         += driver_extif.o
  42  ssb-$(CONFIG_SSB_DRIVER_PCICORE)       += driver_pcicore.o
  43 --- /dev/null
  44 +++ b/drivers/ssb/driver_chipcommon_sflash.c
  45 @@ -0,0 +1,556 @@
  46 +/*
  47 + * Broadcom SiliconBackplane chipcommon serial flash interface
  48 + *
  49 + * Copyright 2011, Jonas Gorski <jonas.gorski@gmail.com>
  50 + * Copyright 2010, Broadcom Corporation
  51 + *
  52 + * Licensed under the GNU/GPL. See COPYING for details.
  53 + */
  54 +
  55 +#include <linux/ssb/ssb.h>
  56 +#include <linux/ssb/ssb_driver_chipcommon.h>
  57 +#include <linux/delay.h>
  58 +
  59 +#include "ssb_private.h"
  60 +
  61 +#define NUM_RETRIES    3
  62 +
  63 +
  64 +/* Issue a serial flash command */
  65 +static inline void ssb_sflash_cmd(struct ssb_chipcommon *cc, u32 opcode)
  66 +{
  67 +       chipco_write32(cc, SSB_CHIPCO_FLASHCTL,
  68 +                       SSB_CHIPCO_FLASHCTL_START | opcode);
  69 +       while (chipco_read32(cc, SSB_CHIPCO_FLASHCTL)
  70 +                       & SSB_CHIPCO_FLASHCTL_BUSY)
  71 +               ;
  72 +}
  73 +
  74 +
  75 +static inline void ssb_sflash_write_u8(struct ssb_chipcommon *cc,
  76 +                                             u32 offset, u8 byte)
  77 +{
  78 +       chipco_write32(cc, SSB_CHIPCO_FLASHADDR, offset);
  79 +       chipco_write32(cc, SSB_CHIPCO_FLASHDATA, byte);
  80 +}
  81 +
  82 +/* Initialize serial flash access */
  83 +int ssb_sflash_init(struct ssb_chipcommon *cc)
  84 +{
  85 +       u32 id, id2;
  86 +
  87 +       memset(&cc->sflash, 0, sizeof(struct ssb_sflash));
  88 +
  89 +       switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
  90 +       case SSB_CHIPCO_FLASHT_STSER:
  91 +               /* Probe for ST chips */
  92 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_DP);
  93 +               chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 0);
  94 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
  95 +               id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
  96 +               cc->sflash.blocksize = 64 * 1024;
  97 +               switch (id) {
  98 +               case 0x11:
  99 +                       /* ST M25P20 2 Mbit Serial Flash */
 100 +                       cc->sflash.numblocks = 4;
 101 +                       break;
 102 +               case 0x12:
 103 +                       /* ST M25P40 4 Mbit Serial Flash */
 104 +                       cc->sflash.numblocks = 8;
 105 +                       break;
 106 +               case 0x13:
 107 +                       /* ST M25P80 8 Mbit Serial Flash */
 108 +                       cc->sflash.numblocks = 16;
 109 +                       break;
 110 +               case 0x14:
 111 +                       /* ST M25P16 16 Mbit Serial Flash */
 112 +                       cc->sflash.numblocks = 32;
 113 +                       break;
 114 +               case 0x15:
 115 +                       /* ST M25P32 32 Mbit Serial Flash */
 116 +                       cc->sflash.numblocks = 64;
 117 +                       break;
 118 +               case 0x16:
 119 +                       /* ST M25P64 64 Mbit Serial Flash */
 120 +                       cc->sflash.numblocks = 128;
 121 +                       break;
 122 +               case 0x17:
 123 +                       /* ST M25FL128 128 Mbit Serial Flash */
 124 +                       cc->sflash.numblocks = 256;
 125 +                       break;
 126 +               case 0xbf:
 127 +                       /* All of the following flashes are SST with
 128 +                        * 4KB subsectors. Others should be added but
 129 +                        * We'll have to revamp the way we identify them
 130 +                        * since RES is not eough to disambiguate them.
 131 +                        */
 132 +                       cc->sflash.blocksize = 4 * 1024;
 133 +                       chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 1);
 134 +                       ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
 135 +                       id2 = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
 136 +                       switch (id2) {
 137 +                       case 1:
 138 +                               /* SST25WF512 512 Kbit Serial Flash */
 139 +                       case 0x48:
 140 +                               /* SST25VF512 512 Kbit Serial Flash */
 141 +                               cc->sflash.numblocks = 16;
 142 +                               break;
 143 +                       case 2:
 144 +                               /* SST25WF010 1 Mbit Serial Flash */
 145 +                       case 0x49:
 146 +                               /* SST25VF010 1 Mbit Serial Flash */
 147 +                               cc->sflash.numblocks = 32;
 148 +                               break;
 149 +                       case 3:
 150 +                               /* SST25WF020 2 Mbit Serial Flash */
 151 +                       case 0x43:
 152 +                               /* SST25VF020 2 Mbit Serial Flash */
 153 +                               cc->sflash.numblocks = 64;
 154 +                               break;
 155 +                       case 4:
 156 +                               /* SST25WF040 4 Mbit Serial Flash */
 157 +                       case 0x44:
 158 +                               /* SST25VF040 4 Mbit Serial Flash */
 159 +                       case 0x8d:
 160 +                               /* SST25VF040B 4 Mbit Serial Flash */
 161 +                               cc->sflash.numblocks = 128;
 162 +                               break;
 163 +                       case 5:
 164 +                               /* SST25WF080 8 Mbit Serial Flash */
 165 +                       case 0x8e:
 166 +                               /* SST25VF080B 8 Mbit Serial Flash */
 167 +                               cc->sflash.numblocks = 256;
 168 +                               break;
 169 +                       case 0x41:
 170 +                               /* SST25VF016 16 Mbit Serial Flash */
 171 +                               cc->sflash.numblocks = 512;
 172 +                               break;
 173 +                       case 0x4a:
 174 +                               /* SST25VF032 32 Mbit Serial Flash */
 175 +                               cc->sflash.numblocks = 1024;
 176 +                               break;
 177 +                       case 0x4b:
 178 +                               /* SST25VF064 64 Mbit Serial Flash */
 179 +                               cc->sflash.numblocks = 2048;
 180 +                               break;
 181 +                       }
 182 +                       break;
 183 +               }
 184 +               break;
 185 +
 186 +       case SSB_CHIPCO_FLASHT_ATSER:
 187 +               /* Probe for Atmel chips */
 188 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_STATUS);
 189 +               id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA) & 0x3c;
 190 +               switch (id) {
 191 +               case 0xc:
 192 +                       /* Atmel AT45DB011 1Mbit Serial Flash */
 193 +                       cc->sflash.blocksize = 256;
 194 +                       cc->sflash.numblocks = 512;
 195 +                       break;
 196 +               case 0x14:
 197 +                       /* Atmel AT45DB021 2Mbit Serial Flash */
 198 +                       cc->sflash.blocksize = 256;
 199 +                       cc->sflash.numblocks = 1024;
 200 +                       break;
 201 +               case 0x1c:
 202 +                       /* Atmel AT45DB041 4Mbit Serial Flash */
 203 +                       cc->sflash.blocksize = 256;
 204 +                       cc->sflash.numblocks = 2048;
 205 +                       break;
 206 +               case 0x24:
 207 +                       /* Atmel AT45DB081 8Mbit Serial Flash */
 208 +                       cc->sflash.blocksize = 256;
 209 +                       cc->sflash.numblocks = 4096;
 210 +                       break;
 211 +               case 0x2c:
 212 +                       /* Atmel AT45DB161 16Mbit Serial Flash */
 213 +                       cc->sflash.blocksize = 512;
 214 +                       cc->sflash.numblocks = 4096;
 215 +                       break;
 216 +               case 0x34:
 217 +                       /* Atmel AT45DB321 32Mbit Serial Flash */
 218 +                       cc->sflash.blocksize = 512;
 219 +                       cc->sflash.numblocks = 8192;
 220 +                       break;
 221 +               case 0x3c:
 222 +                       /* Atmel AT45DB642 64Mbit Serial Flash */
 223 +                       cc->sflash.blocksize = 1024;
 224 +                       cc->sflash.numblocks = 8192;
 225 +                       break;
 226 +               }
 227 +               break;
 228 +       }
 229 +
 230 +       cc->sflash.size = cc->sflash.blocksize * cc->sflash.numblocks;
 231 +
 232 +       return cc->sflash.size ? 0 : -ENODEV;
 233 +}
 234 +
 235 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
 236 +int ssb_sflash_read(struct ssb_chipcommon *cc, u32 offset, u32 len,
 237 +                          u8 *buf)
 238 +{
 239 +       u8 *from, *to;
 240 +       u32 cnt, i;
 241 +
 242 +       if (!len)
 243 +               return 0;
 244 +
 245 +       if ((offset + len) > cc->sflash.size)
 246 +               return -EINVAL;
 247 +
 248 +       if ((len >= 4) && (offset & 3))
 249 +               cnt = 4 - (offset & 3);
 250 +       else if ((len >= 4) && ((u32)buf & 3))
 251 +               cnt = 4 - ((u32)buf & 3);
 252 +       else
 253 +               cnt = len;
 254 +
 255 +
 256 +       if (cc->dev->id.revision == 12)
 257 +               from = (u8 *)KSEG1ADDR(SSB_FLASH2 + offset);
 258 +       else
 259 +               from = (u8 *)KSEG0ADDR(SSB_FLASH2 + offset);
 260 +
 261 +       to = (u8 *)buf;
 262 +
 263 +       if (cnt < 4) {
 264 +               for (i = 0; i < cnt; i++) {
 265 +                       *to = readb(from);
 266 +                       from++;
 267 +                       to++;
 268 +               }
 269 +               return cnt;
 270 +       }
 271 +
 272 +       while (cnt >= 4) {
 273 +               *(u32 *)to = readl(from);
 274 +               from += 4;
 275 +               to += 4;
 276 +               cnt -= 4;
 277 +       }
 278 +
 279 +       return len - cnt;
 280 +}
 281 +
 282 +/* Poll for command completion. Returns zero when complete. */
 283 +int ssb_sflash_poll(struct ssb_chipcommon *cc, u32 offset)
 284 +{
 285 +       if (offset >= cc->sflash.size)
 286 +               return -22;
 287 +
 288 +       switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
 289 +       case SSB_CHIPCO_FLASHT_STSER:
 290 +               /* Check for ST Write In Progress bit */
 291 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RDSR);
 292 +               return chipco_read32(cc, SSB_CHIPCO_FLASHDATA)
 293 +                               & SSB_CHIPCO_FLASHSTA_ST_WIP;
 294 +       case SSB_CHIPCO_FLASHT_ATSER:
 295 +               /* Check for Atmel Ready bit */
 296 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_STATUS);
 297 +               return !(chipco_read32(cc, SSB_CHIPCO_FLASHDATA)
 298 +                               & SSB_CHIPCO_FLASHSTA_AT_READY);
 299 +       }
 300 +
 301 +       return 0;
 302 +}
 303 +
 304 +
 305 +static int sflash_st_write(struct ssb_chipcommon *cc, u32 offset, u32 len,
 306 +                          const u8 *buf)
 307 +{
 308 +       struct ssb_bus *bus = cc->dev->bus;
 309 +       int ret = 0;
 310 +       bool is4712b0 = (bus->chip_id == 0x4712) && (bus->chip_rev == 3);
 311 +       u32 mask;
 312 +
 313 +
 314 +       /* Enable writes */
 315 +       ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_WREN);
 316 +       if (is4712b0) {
 317 +               mask = 1 << 14;
 318 +               ssb_sflash_write_u8(cc, offset, *buf++);
 319 +               /* Set chip select */
 320 +               chipco_set32(cc, SSB_CHIPCO_GPIOOUT, mask);
 321 +               /* Issue a page program with the first byte */
 322 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_PP);
 323 +               ret = 1;
 324 +               offset++;
 325 +               len--;
 326 +               while (len > 0) {
 327 +                       if ((offset & 255) == 0) {
 328 +                               /* Page boundary, drop cs and return */
 329 +                               chipco_mask32(cc, SSB_CHIPCO_GPIOOUT, ~mask);
 330 +                               udelay(1);
 331 +                               if (!ssb_sflash_poll(cc, offset)) {
 332 +                                       /* Flash rejected command */
 333 +                                       return -EAGAIN;
 334 +                               }
 335 +                               return ret;
 336 +                       } else {
 337 +                               /* Write single byte */
 338 +                               ssb_sflash_cmd(cc, *buf++);
 339 +                       }
 340 +                       ret++;
 341 +                       offset++;
 342 +                       len--;
 343 +               }
 344 +               /* All done, drop cs */
 345 +               chipco_mask32(cc, SSB_CHIPCO_GPIOOUT, ~mask);
 346 +               udelay(1);
 347 +               if (!ssb_sflash_poll(cc, offset)) {
 348 +                       /* Flash rejected command */
 349 +                       return -EAGAIN;
 350 +               }
 351 +       } else if (cc->dev->id.revision >= 20) {
 352 +               ssb_sflash_write_u8(cc, offset, *buf++);
 353 +               /* Issue a page program with CSA bit set */
 354 +               ssb_sflash_cmd(cc,
 355 +                               SSB_CHIPCO_FLASHCTL_ST_CSA |
 356 +                               SSB_CHIPCO_FLASHCTL_ST_PP);
 357 +               ret = 1;
 358 +               offset++;
 359 +               len--;
 360 +               while (len > 0) {
 361 +                       if ((offset & 255) == 0) {
 362 +                               /* Page boundary, poll droping cs and return */
 363 +                               chipco_write32(cc, SSB_CHIPCO_FLASHCTL, 0);
 364 +                               udelay(1);
 365 +                               if (!ssb_sflash_poll(cc, offset)) {
 366 +                                       /* Flash rejected command */
 367 +                                       return -EAGAIN;
 368 +                               }
 369 +                               return ret;
 370 +                       } else {
 371 +                               /* Write single byte */
 372 +                               ssb_sflash_cmd(cc,
 373 +                                               SSB_CHIPCO_FLASHCTL_ST_CSA |
 374 +                                               *buf++);
 375 +                       }
 376 +                       ret++;
 377 +                       offset++;
 378 +                       len--;
 379 +               }
 380 +               /* All done, drop cs & poll */
 381 +               chipco_write32(cc, SSB_CHIPCO_FLASHCTL, 0);
 382 +               udelay(1);
 383 +               if (!ssb_sflash_poll(cc, offset)) {
 384 +                       /* Flash rejected command */
 385 +                       return -EAGAIN;
 386 +               }
 387 +       } else {
 388 +               ret = 1;
 389 +               ssb_sflash_write_u8(cc, offset, *buf);
 390 +               /* Page program */
 391 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_PP);
 392 +       }
 393 +       return ret;
 394 +}
 395 +
 396 +static int sflash_at_write(struct ssb_chipcommon *cc, u32 offset, u32 len,
 397 +                          const u8 *buf)
 398 +{
 399 +       struct ssb_sflash *sfl = &cc->sflash;
 400 +       u32 page, byte, mask;
 401 +       int ret = 0;
 402 +       mask = sfl->blocksize - 1;
 403 +       page = (offset & ~mask) << 1;
 404 +       byte = offset & mask;
 405 +       /* Read main memory page into buffer 1 */
 406 +       if (byte || (len < sfl->blocksize)) {
 407 +               int i = 100;
 408 +               chipco_write32(cc, SSB_CHIPCO_FLASHADDR, page);
 409 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD);
 410 +               /* 250 us for AT45DB321B */
 411 +               while (i > 0 && ssb_sflash_poll(cc, offset)) {
 412 +                       udelay(10);
 413 +                       i--;
 414 +               }
 415 +               BUG_ON(!ssb_sflash_poll(cc, offset));
 416 +       }
 417 +       /* Write into buffer 1 */
 418 +       for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) {
 419 +               ssb_sflash_write_u8(cc, byte++, *buf++);
 420 +               ssb_sflash_cmd(cc,
 421 +                               SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE);
 422 +       }
 423 +       /* Write buffer 1 into main memory page */
 424 +       chipco_write32(cc, SSB_CHIPCO_FLASHADDR, page);
 425 +       ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM);
 426 +
 427 +       return ret;
 428 +}
 429 +
 430 +/* Write len bytes starting at offset into buf. Returns number of bytes
 431 + * written. Caller should poll for completion.
 432 + */
 433 +int ssb_sflash_write(struct ssb_chipcommon *cc, u32 offset, u32 len,
 434 +                           const u8 *buf)
 435 +{
 436 +       struct ssb_sflash *sfl;
 437 +       int ret = 0, tries = NUM_RETRIES;
 438 +
 439 +       if (!len)
 440 +               return 0;
 441 +
 442 +       if ((offset + len) > cc->sflash.size)
 443 +               return -EINVAL;
 444 +
 445 +       sfl = &cc->sflash;
 446 +       switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
 447 +       case SSB_CHIPCO_FLASHT_STSER:
 448 +               do {
 449 +                       ret = sflash_st_write(cc, offset, len, buf);
 450 +                       tries--;
 451 +               } while (ret == -EAGAIN && tries > 0);
 452 +
 453 +               if (ret == -EAGAIN && tries == 0) {
 454 +                       pr_info("ST Flash rejected write\n");
 455 +                       ret = -EIO;
 456 +               }
 457 +               break;
 458 +       case SSB_CHIPCO_FLASHT_ATSER:
 459 +               ret = sflash_at_write(cc, offset, len, buf);
 460 +               break;
 461 +       }
 462 +
 463 +       return ret;
 464 +}
 465 +
 466 +/* Erase a region. Returns number of bytes scheduled for erasure.
 467 + * Caller should poll for completion.
 468 + */
 469 +int ssb_sflash_erase(struct ssb_chipcommon *cc, u32 offset)
 470 +{
 471 +       struct ssb_sflash *sfl;
 472 +
 473 +       if (offset >= cc->sflash.size)
 474 +               return -EINVAL;
 475 +
 476 +       sfl = &cc->sflash;
 477 +       switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
 478 +       case SSB_CHIPCO_FLASHT_STSER:
 479 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_WREN);
 480 +               chipco_write32(cc, SSB_CHIPCO_FLASHADDR, offset);
 481 +               /* Newer flashes have "sub-sectors" which can be erased independently
 482 +                * with a new command: ST_SSE. The ST_SE command erases 64KB just as
 483 +                * before.
 484 +                */
 485 +               ssb_sflash_cmd(cc, (sfl->blocksize < (64 * 1024)) ? SSB_CHIPCO_FLASHCTL_ST_SSE : SSB_CHIPCO_FLASHCTL_ST_SE);
 486 +               return sfl->blocksize;
 487 +       case SSB_CHIPCO_FLASHT_ATSER:
 488 +               chipco_write32(cc, SSB_CHIPCO_FLASHADDR, offset << 1);
 489 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE);
 490 +               return sfl->blocksize;
 491 +       }
 492 +
 493 +       return 0;
 494 +}
 495 +
 496 +/*
 497 + * writes the appropriate range of flash, a NULL buf simply erases
 498 + * the region of flash
 499 + */
 500 +int ssb_sflash_commit(struct ssb_chipcommon *cc, u32 offset, u32 len,
 501 +                            const u8 *buf)
 502 +{
 503 +       struct ssb_sflash *sfl;
 504 +       u8 *block = NULL, *cur_ptr, *blk_ptr;
 505 +       u32 blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
 506 +       u32 blk_offset, blk_len, copied;
 507 +       int bytes, ret = 0;
 508 +
 509 +       /* Check address range */
 510 +       if (len <= 0)
 511 +               return 0;
 512 +
 513 +       sfl = &cc->sflash;
 514 +       if ((offset + len) > sfl->size)
 515 +               return -EINVAL;
 516 +
 517 +       blocksize = sfl->blocksize;
 518 +       mask = blocksize - 1;
 519 +
 520 +       /* Allocate a block of mem */
 521 +       block = kmalloc(blocksize, GFP_KERNEL);
 522 +       if (!block)
 523 +               return -ENOMEM;
 524 +
 525 +       while (len) {
 526 +               /* Align offset */
 527 +               cur_offset = offset & ~mask;
 528 +               cur_length = blocksize;
 529 +               cur_ptr = block;
 530 +
 531 +               remainder = blocksize - (offset & mask);
 532 +               if (len < remainder)
 533 +                       cur_retlen = len;
 534 +               else
 535 +                       cur_retlen = remainder;
 536 +
 537 +               /* buf == NULL means erase only */
 538 +               if (buf) {
 539 +                       /* Copy existing data into holding block if necessary */
 540 +                       if ((offset & mask) || (len < blocksize)) {
 541 +                               blk_offset = cur_offset;
 542 +                               blk_len = cur_length;
 543 +                               blk_ptr = cur_ptr;
 544 +
 545 +                               /* Copy entire block */
 546 +                               while (blk_len) {
 547 +                                       copied = ssb_sflash_read(cc,
 548 +                                                       blk_offset,
 549 +                                                       blk_len, blk_ptr);
 550 +                                       blk_offset += copied;
 551 +                                       blk_len -= copied;
 552 +                                       blk_ptr += copied;
 553 +                               }
 554 +                       }
 555 +
 556 +                       /* Copy input data into holding block */
 557 +                       memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
 558 +               }
 559 +
 560 +               /* Erase block */
 561 +               ret = ssb_sflash_erase(cc, cur_offset);
 562 +               if (ret < 0)
 563 +                       goto done;
 564 +
 565 +               while (ssb_sflash_poll(cc, cur_offset));
 566 +
 567 +               /* buf == NULL means erase only */
 568 +               if (!buf) {
 569 +                       offset += cur_retlen;
 570 +                       len -= cur_retlen;
 571 +                       continue;
 572 +               }
 573 +
 574 +               /* Write holding block */
 575 +               while (cur_length > 0) {
 576 +                       bytes = ssb_sflash_write(cc, cur_offset,
 577 +                                       cur_length, cur_ptr);
 578 +
 579 +                       if (bytes < 0) {
 580 +                               ret = bytes;
 581 +                               goto done;
 582 +                       }
 583 +
 584 +                       while (ssb_sflash_poll(cc, cur_offset))
 585 +                               ;
 586 +
 587 +                       cur_offset += bytes;
 588 +                       cur_length -= bytes;
 589 +                       cur_ptr += bytes;
 590 +               }
 591 +
 592 +               offset += cur_retlen;
 593 +               len -= cur_retlen;
 594 +               buf += cur_retlen;
 595 +       }
 596 +
 597 +       ret = len;
 598 +done:
 599 +       kfree(block);
 600 +       return ret;
 601 +}
 602 --- a/drivers/ssb/driver_mipscore.c
 603 +++ b/drivers/ssb/driver_mipscore.c
 604 @@ -203,7 +203,13 @@ static void ssb_mips_flash_detect(struct
 605         switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
 606         case SSB_CHIPCO_FLASHT_STSER:
 607         case SSB_CHIPCO_FLASHT_ATSER:
 608 +#ifdef CONFIG_SSB_SFLASH
 609 +               pr_info("found serial flash.\n");
 610 +               bus->chipco.flash_type = SSB_SFLASH;
 611 +               ssb_sflash_init(&bus->chipco);
 612 +#else
 613                 pr_info("serial flash not supported.\n");
 614 +#endif /* CONFIG_SSB_SFLASH */
 615                 break;
 616         case SSB_CHIPCO_FLASHT_PARA:
 617                 pr_info("found parallel flash.\n");
 618 --- a/drivers/ssb/ssb_private.h
 619 +++ b/drivers/ssb/ssb_private.h
 620 @@ -192,6 +192,10 @@ extern int ssb_devices_freeze(struct ssb
 621  extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
 622
 623
 624 +#ifdef CONFIG_SSB_SFLASH
 625 +/* driver_chipcommon_sflash.c */
 626 +int ssb_sflash_init(struct ssb_chipcommon *cc);
 627 +#endif /* CONFIG_SSB_SFLASH */
 628
 629  /* b43_pci_bridge.c */
 630  #ifdef CONFIG_SSB_B43_PCI_BRIDGE
 631 --- a/include/linux/ssb/ssb_driver_chipcommon.h
 632 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
 633 @@ -503,8 +503,10 @@
 634  #define SSB_CHIPCO_FLASHCTL_ST_PP      0x0302          /* Page Program */
 635  #define SSB_CHIPCO_FLASHCTL_ST_SE      0x02D8          /* Sector Erase */
 636  #define SSB_CHIPCO_FLASHCTL_ST_BE      0x00C7          /* Bulk Erase */
 637 -#define SSB_CHIPCO_FLASHCTL_ST_DP      0x00B9          /* Deep Power-down */
 638 -#define SSB_CHIPCO_FLASHCTL_ST_RSIG    0x03AB          /* Read Electronic Signature */
 639 +#define SSB_CHIPCO_FLASHCTL_ST_DP      0x00D9          /* Deep Power-down */
 640 +#define SSB_CHIPCO_FLASHCTL_ST_RES     0x03AB          /* Read Electronic Signature */
 641 +#define SSB_CHIPCO_FLASHCTL_ST_CSA     0x1000          /* Keep chip select asserted */
 642 +#define SSB_CHIPCO_FLASHCTL_ST_SSE     0x0220          /* Sub-sector Erase */
 643
 644  /* Status register bits for ST flashes */
 645  #define SSB_CHIPCO_FLASHSTA_ST_WIP     0x01            /* Write In Progress */
 646 @@ -585,6 +587,7 @@ struct ssb_chipcommon_pmu {
 647  #ifdef CONFIG_SSB_DRIVER_MIPS
 648  enum ssb_flash_type {
 649         SSB_PFLASH,
 650 +       SSB_SFLASH,
 651  };
 652
 653  struct ssb_pflash {
 654 @@ -592,6 +595,14 @@ struct ssb_pflash {
 655         u32 window;
 656         u32 window_size;
 657  };
 658 +
 659 +#ifdef CONFIG_SSB_SFLASH
 660 +struct ssb_sflash {
 661 +       u32 blocksize;          /* Block size */
 662 +       u32 numblocks;          /* Number of blocks */
 663 +       u32 size;               /* Total size in bytes */
 664 +};
 665 +#endif /* CONFIG_SSB_SFLASH */
 666  #endif /* CONFIG_SSB_DRIVER_MIPS */
 667
 668  struct ssb_chipcommon {
 669 @@ -605,6 +616,9 @@ struct ssb_chipcommon {
 670         enum ssb_flash_type flash_type;
 671         union {
 672                 struct ssb_pflash pflash;
 673 +#ifdef CONFIG_SSB_SFLASH
 674 +               struct ssb_sflash sflash;
 675 +#endif /* CONFIG_SSB_SFLASH */
 676         };
 677  #endif /* CONFIG_SSB_DRIVER_MIPS */
 678  };
 679 @@ -666,6 +680,18 @@ extern int ssb_chipco_serial_init(struct
 680                                   struct ssb_serial_port *ports);
 681  #endif /* CONFIG_SSB_SERIAL */
 682
 683 +#ifdef CONFIG_SSB_SFLASH
 684 +/* Chipcommon sflash support. */
 685 +int ssb_sflash_read(struct ssb_chipcommon *cc, u32 offset, u32 len,
 686 +                          u8 *buf);
 687 +int ssb_sflash_poll(struct ssb_chipcommon *cc, u32 offset);
 688 +int ssb_sflash_write(struct ssb_chipcommon *cc, u32 offset, u32 len,
 689 +                           const u8 *buf);
 690 +int ssb_sflash_erase(struct ssb_chipcommon *cc, u32 offset);
 691 +int ssb_sflash_commit(struct ssb_chipcommon *cc, u32 offset, u32 len,
 692 +                            const u8 *buf);
 693 +#endif /* CONFIG_SSB_SFLASH */
 694 +
 695  /* PMU support */
 696  extern void ssb_pmu_init(struct ssb_chipcommon *cc);
 697