target/linux/brcm47xx/patches-2.6.25/700-ssb-gigabit-ethernet-driver.patch

   1 Index: linux-2.6.23.16/drivers/ssb/Kconfig
   2 ===================================================================
   3 --- linux-2.6.23.16.orig/drivers/ssb/Kconfig    2008-03-19 11:16:18.000000000 +0100
   4 +++ linux-2.6.23.16/drivers/ssb/Kconfig 2008-03-19 11:16:18.000000000 +0100
   5 @@ -120,4 +120,13 @@ config SSB_DRIVER_EXTIF
   6
   7           If unsure, say N
   8
   9 +config SSB_DRIVER_GIGE
  10 +       bool "SSB Broadcom Gigabit Ethernet driver"
  11 +       depends on SSB_PCIHOST_POSSIBLE && SSB_EMBEDDED && MIPS
  12 +       help
  13 +         Driver for the Sonics Silicon Backplane attached
  14 +         Broadcom Gigabit Ethernet.
  15 +
  16 +         If unsure, say N
  17 +
  18  endmenu
  19 Index: linux-2.6.23.16/drivers/ssb/Makefile
  20 ===================================================================
  21 --- linux-2.6.23.16.orig/drivers/ssb/Makefile   2008-03-19 11:16:18.000000000 +0100
  22 +++ linux-2.6.23.16/drivers/ssb/Makefile        2008-03-19 11:16:18.000000000 +0100
  23 @@ -11,6 +11,7 @@ ssb-y                                 += driver_chipcommon.o
  24  ssb-$(CONFIG_SSB_DRIVER_MIPS)          += driver_mipscore.o
  25  ssb-$(CONFIG_SSB_DRIVER_EXTIF)         += driver_extif.o
  26  ssb-$(CONFIG_SSB_DRIVER_PCICORE)       += driver_pcicore.o
  27 +ssb-$(CONFIG_SSB_DRIVER_GIGE)          += driver_gige.o
  28
  29  # b43 pci-ssb-bridge driver
  30  # Not strictly a part of SSB, but kept here for convenience
  31 Index: linux-2.6.23.16/drivers/ssb/driver_gige.c
  32 ===================================================================
  33 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  34 +++ linux-2.6.23.16/drivers/ssb/driver_gige.c   2008-03-19 11:16:18.000000000 +0100
  35 @@ -0,0 +1,294 @@
  36 +/*
  37 + * Sonics Silicon Backplane
  38 + * Broadcom Gigabit Ethernet core driver
  39 + *
  40 + * Copyright 2008, Broadcom Corporation
  41 + * Copyright 2008, Michael Buesch <mb@bu3sch.de>
  42 + *
  43 + * Licensed under the GNU/GPL. See COPYING for details.
  44 + */
  45 +
  46 +#include <linux/ssb/ssb.h>
  47 +#include <linux/ssb/ssb_driver_gige.h>
  48 +#include <linux/pci.h>
  49 +#include <linux/pci_regs.h>
  50 +
  51 +
  52 +/*
  53 +MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
  54 +MODULE_AUTHOR("Michael Buesch");
  55 +MODULE_LICENSE("GPL");
  56 +*/
  57 +
  58 +static const struct ssb_device_id ssb_gige_tbl[] = {
  59 +       SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
  60 +       SSB_DEVTABLE_END
  61 +};
  62 +/* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
  63 +
  64 +
  65 +static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
  66 +{
  67 +       return ssb_read8(dev->dev, offset);
  68 +}
  69 +
  70 +static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
  71 +{
  72 +       return ssb_read16(dev->dev, offset);
  73 +}
  74 +
  75 +static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
  76 +{
  77 +       return ssb_read32(dev->dev, offset);
  78 +}
  79 +
  80 +static inline void gige_write8(struct ssb_gige *dev,
  81 +                              u16 offset, u8 value)
  82 +{
  83 +       ssb_write8(dev->dev, offset, value);
  84 +}
  85 +
  86 +static inline void gige_write16(struct ssb_gige *dev,
  87 +                               u16 offset, u16 value)
  88 +{
  89 +       ssb_write16(dev->dev, offset, value);
  90 +}
  91 +
  92 +static inline void gige_write32(struct ssb_gige *dev,
  93 +                               u16 offset, u32 value)
  94 +{
  95 +       ssb_write32(dev->dev, offset, value);
  96 +}
  97 +
  98 +static inline
  99 +u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
 100 +{
 101 +       BUG_ON(offset >= 256);
 102 +       return gige_read8(dev, SSB_GIGE_PCICFG + offset);
 103 +}
 104 +
 105 +static inline
 106 +u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
 107 +{
 108 +       BUG_ON(offset >= 256);
 109 +       return gige_read16(dev, SSB_GIGE_PCICFG + offset);
 110 +}
 111 +
 112 +static inline
 113 +u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
 114 +{
 115 +       BUG_ON(offset >= 256);
 116 +       return gige_read32(dev, SSB_GIGE_PCICFG + offset);
 117 +}
 118 +
 119 +static inline
 120 +void gige_pcicfg_write8(struct ssb_gige *dev,
 121 +                       unsigned int offset, u8 value)
 122 +{
 123 +       BUG_ON(offset >= 256);
 124 +       gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
 125 +}
 126 +
 127 +static inline
 128 +void gige_pcicfg_write16(struct ssb_gige *dev,
 129 +                        unsigned int offset, u16 value)
 130 +{
 131 +       BUG_ON(offset >= 256);
 132 +       gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
 133 +}
 134 +
 135 +static inline
 136 +void gige_pcicfg_write32(struct ssb_gige *dev,
 137 +                        unsigned int offset, u32 value)
 138 +{
 139 +       BUG_ON(offset >= 256);
 140 +       gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
 141 +}
 142 +
 143 +static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 144 +                                   int reg, int size, u32 *val)
 145 +{
 146 +       struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
 147 +       unsigned long flags;
 148 +
 149 +       if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
 150 +               return PCIBIOS_DEVICE_NOT_FOUND;
 151 +       if (reg >= 256)
 152 +               return PCIBIOS_DEVICE_NOT_FOUND;
 153 +
 154 +       spin_lock_irqsave(&dev->lock, flags);
 155 +       switch (size) {
 156 +       case 1:
 157 +               *val = gige_pcicfg_read8(dev, reg);
 158 +               break;
 159 +       case 2:
 160 +               *val = gige_pcicfg_read16(dev, reg);
 161 +               break;
 162 +       case 4:
 163 +               *val = gige_pcicfg_read32(dev, reg);
 164 +               break;
 165 +       default:
 166 +               WARN_ON(1);
 167 +       }
 168 +       spin_unlock_irqrestore(&dev->lock, flags);
 169 +
 170 +       return PCIBIOS_SUCCESSFUL;
 171 +}
 172 +
 173 +static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 174 +                                    int reg, int size, u32 val)
 175 +{
 176 +       struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
 177 +       unsigned long flags;
 178 +
 179 +       if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
 180 +               return PCIBIOS_DEVICE_NOT_FOUND;
 181 +       if (reg >= 256)
 182 +               return PCIBIOS_DEVICE_NOT_FOUND;
 183 +
 184 +       spin_lock_irqsave(&dev->lock, flags);
 185 +       switch (size) {
 186 +       case 1:
 187 +               gige_pcicfg_write8(dev, reg, val);
 188 +               break;
 189 +       case 2:
 190 +               gige_pcicfg_write16(dev, reg, val);
 191 +               break;
 192 +       case 4:
 193 +               gige_pcicfg_write32(dev, reg, val);
 194 +               break;
 195 +       default:
 196 +               WARN_ON(1);
 197 +       }
 198 +       spin_unlock_irqrestore(&dev->lock, flags);
 199 +
 200 +       return PCIBIOS_SUCCESSFUL;
 201 +}
 202 +
 203 +static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
 204 +{
 205 +       struct ssb_gige *dev;
 206 +       u32 base, tmslow, tmshigh;
 207 +
 208 +       dev = kzalloc(sizeof(*dev), GFP_KERNEL);
 209 +       if (!dev)
 210 +               return -ENOMEM;
 211 +       dev->dev = sdev;
 212 +
 213 +       spin_lock_init(&dev->lock);
 214 +       dev->pci_controller.pci_ops = &dev->pci_ops;
 215 +       dev->pci_controller.io_resource = &dev->io_resource;
 216 +       dev->pci_controller.mem_resource = &dev->mem_resource;
 217 +       dev->pci_controller.io_map_base = 0x800;
 218 +       dev->pci_ops.read = ssb_gige_pci_read_config;
 219 +       dev->pci_ops.write = ssb_gige_pci_write_config;
 220 +
 221 +       dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
 222 +       dev->io_resource.start = 0x800;
 223 +       dev->io_resource.end = 0x8FF;
 224 +       dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
 225 +
 226 +       if (!ssb_device_is_enabled(sdev))
 227 +               ssb_device_enable(sdev, 0);
 228 +
 229 +       /* Setup BAR0. This is a 64k MMIO region. */
 230 +       base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
 231 +       gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
 232 +       gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
 233 +
 234 +       dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
 235 +       dev->mem_resource.start = base;
 236 +       dev->mem_resource.end = base + 0x10000 - 1;
 237 +       dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
 238 +
 239 +       /* Enable the memory region. */
 240 +       gige_pcicfg_write16(dev, PCI_COMMAND,
 241 +                           gige_pcicfg_read16(dev, PCI_COMMAND)
 242 +                           | PCI_COMMAND_MEMORY);
 243 +
 244 +       /* Write flushing is controlled by the Flush Status Control register.
 245 +        * We want to flush every register write with a timeout and we want
 246 +        * to disable the IRQ mask while flushing to avoid concurrency.
 247 +        * Note that automatic write flushing does _not_ work from
 248 +        * an IRQ handler. The driver must flush manually by reading a register.
 249 +        */
 250 +       gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
 251 +
 252 +       /* Check if we have an RGMII or GMII PHY-bus.
 253 +        * On RGMII do not bypass the DLLs */
 254 +       tmslow = ssb_read32(sdev, SSB_TMSLOW);
 255 +       tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
 256 +       if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
 257 +               tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
 258 +               tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
 259 +               dev->has_rgmii = 1;
 260 +       } else {
 261 +               tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
 262 +               tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
 263 +               dev->has_rgmii = 0;
 264 +       }
 265 +       tmslow |= SSB_GIGE_TMSLOW_DLLEN;
 266 +       ssb_write32(sdev, SSB_TMSLOW, tmslow);
 267 +
 268 +       ssb_set_drvdata(sdev, dev);
 269 +       register_pci_controller(&dev->pci_controller);
 270 +
 271 +       return 0;
 272 +}
 273 +
 274 +bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
 275 +{
 276 +       if (!pdev->resource[0].name)
 277 +               return 0;
 278 +       return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
 279 +}
 280 +EXPORT_SYMBOL(pdev_is_ssb_gige_core);
 281 +
 282 +int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
 283 +                                  struct pci_dev *pdev)
 284 +{
 285 +       struct ssb_gige *dev = ssb_get_drvdata(sdev);
 286 +       struct resource *res;
 287 +
 288 +       if (pdev->bus->ops != &dev->pci_ops) {
 289 +               /* The PCI device is not on this SSB GigE bridge device. */
 290 +               return -ENODEV;
 291 +       }
 292 +
 293 +       /* Fixup the PCI resources. */
 294 +       res = &(pdev->resource[0]);
 295 +       res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
 296 +       res->name = dev->mem_resource.name;
 297 +       res->start = dev->mem_resource.start;
 298 +       res->end = dev->mem_resource.end;
 299 +
 300 +       /* Fixup interrupt lines. */
 301 +       pdev->irq = ssb_mips_irq(sdev) + 2;
 302 +       pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
 303 +
 304 +       return 0;
 305 +}
 306 +
 307 +int ssb_gige_map_irq(struct ssb_device *sdev,
 308 +                    const struct pci_dev *pdev)
 309 +{
 310 +       struct ssb_gige *dev = ssb_get_drvdata(sdev);
 311 +
 312 +       if (pdev->bus->ops != &dev->pci_ops) {
 313 +               /* The PCI device is not on this SSB GigE bridge device. */
 314 +               return -ENODEV;
 315 +       }
 316 +
 317 +       return ssb_mips_irq(sdev) + 2;
 318 +}
 319 +
 320 +static struct ssb_driver ssb_gige_driver = {
 321 +       .name           = "BCM-GigE",
 322 +       .id_table       = ssb_gige_tbl,
 323 +       .probe          = ssb_gige_probe,
 324 +};
 325 +
 326 +int ssb_gige_init(void)
 327 +{
 328 +       return ssb_driver_register(&ssb_gige_driver);
 329 +}
 330 Index: linux-2.6.23.16/include/linux/ssb/ssb_driver_gige.h
 331 ===================================================================
 332 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 333 +++ linux-2.6.23.16/include/linux/ssb/ssb_driver_gige.h 2008-03-19 11:16:18.000000000 +0100
 334 @@ -0,0 +1,174 @@
 335 +#ifndef LINUX_SSB_DRIVER_GIGE_H_
 336 +#define LINUX_SSB_DRIVER_GIGE_H_
 337 +
 338 +#include <linux/ssb/ssb.h>
 339 +#include <linux/pci.h>
 340 +#include <linux/spinlock.h>
 341 +
 342 +
 343 +#ifdef CONFIG_SSB_DRIVER_GIGE
 344 +
 345 +
 346 +#define SSB_GIGE_PCIIO                 0x0000 /* PCI I/O Registers (1024 bytes) */
 347 +#define SSB_GIGE_RESERVED              0x0400 /* Reserved (1024 bytes) */
 348 +#define SSB_GIGE_PCICFG                        0x0800 /* PCI config space (256 bytes) */
 349 +#define SSB_GIGE_SHIM_FLUSHSTAT                0x0C00 /* PCI to OCP: Flush status control (32bit) */
 350 +#define SSB_GIGE_SHIM_FLUSHRDA         0x0C04 /* PCI to OCP: Flush read address (32bit) */
 351 +#define SSB_GIGE_SHIM_FLUSHTO          0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
 352 +#define SSB_GIGE_SHIM_BARRIER          0x0C0C /* PCI to OCP: Barrier register (32bit) */
 353 +#define SSB_GIGE_SHIM_MAOCPSI          0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
 354 +#define SSB_GIGE_SHIM_SIOCPMA          0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
 355 +
 356 +/* TM Status High flags */
 357 +#define SSB_GIGE_TMSHIGH_RGMII         0x00010000 /* Have an RGMII PHY-bus */
 358 +/* TM Status Low flags */
 359 +#define SSB_GIGE_TMSLOW_TXBYPASS       0x00080000 /* TX bypass (no delay) */
 360 +#define SSB_GIGE_TMSLOW_RXBYPASS       0x00100000 /* RX bypass (no delay) */
 361 +#define SSB_GIGE_TMSLOW_DLLEN          0x01000000 /* Enable DLL controls */
 362 +
 363 +/* Boardflags (low) */
 364 +#define SSB_GIGE_BFL_ROBOSWITCH                0x0010
 365 +
 366 +
 367 +#define SSB_GIGE_MEM_RES_NAME          "SSB Broadcom 47xx GigE memory"
 368 +#define SSB_GIGE_IO_RES_NAME           "SSB Broadcom 47xx GigE I/O"
 369 +
 370 +struct ssb_gige {
 371 +       struct ssb_device *dev;
 372 +
 373 +       spinlock_t lock;
 374 +
 375 +       /* True, if the device has an RGMII bus.
 376 +        * False, if the device has a GMII bus. */
 377 +       bool has_rgmii;
 378 +
 379 +       /* The PCI controller device. */
 380 +       struct pci_controller pci_controller;
 381 +       struct pci_ops pci_ops;
 382 +       struct resource mem_resource;
 383 +       struct resource io_resource;
 384 +};
 385 +
 386 +/* Check whether a PCI device is a SSB Gigabit Ethernet core. */
 387 +extern bool pdev_is_ssb_gige_core(struct pci_dev *pdev);
 388 +
 389 +/* Convert a pci_dev pointer to a ssb_gige pointer. */
 390 +static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
 391 +{
 392 +       if (!pdev_is_ssb_gige_core(pdev))
 393 +               return NULL;
 394 +       return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);
 395 +}
 396 +
 397 +/* Returns whether the PHY is connected by an RGMII bus. */
 398 +static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
 399 +{
 400 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
 401 +       return (dev ? dev->has_rgmii : 0);
 402 +}
 403 +
 404 +/* Returns whether we have a Roboswitch. */
 405 +static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
 406 +{
 407 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
 408 +       if (dev)
 409 +               return !!(dev->dev->bus->sprom.boardflags_lo &
 410 +                         SSB_GIGE_BFL_ROBOSWITCH);
 411 +       return 0;
 412 +}
 413 +
 414 +/* Returns whether we can only do one DMA at once. */
 415 +static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
 416 +{
 417 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
 418 +       if (dev)
 419 +               return ((dev->dev->bus->chip_id == 0x4785) &&
 420 +                       (dev->dev->bus->chip_rev < 2));
 421 +       return 0;
 422 +}
 423 +
 424 +/* Returns whether we must flush posted writes. */
 425 +static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
 426 +{
 427 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
 428 +       if (dev)
 429 +               return (dev->dev->bus->chip_id == 0x4785);
 430 +       return 0;
 431 +}
 432 +
 433 +extern char * nvram_get(const char *name);
 434 +/* Get the device MAC address */
 435 +static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
 436 +{
 437 +#ifdef CONFIG_BCM947XX
 438 +       char *res = nvram_get("et0macaddr");
 439 +       if (res)
 440 +               memcpy(macaddr, res, 6);
 441 +#endif
 442 +}
 443 +
 444 +extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
 445 +                                         struct pci_dev *pdev);
 446 +extern int ssb_gige_map_irq(struct ssb_device *sdev,
 447 +                           const struct pci_dev *pdev);
 448 +
 449 +/* The GigE driver is not a standalone module, because we don't have support
 450 + * for unregistering the driver. So we could not unload the module anyway. */
 451 +extern int ssb_gige_init(void);
 452 +static inline void ssb_gige_exit(void)
 453 +{
 454 +       /* Currently we can not unregister the GigE driver,
 455 +        * because we can not unregister the PCI bridge. */
 456 +       BUG();
 457 +}
 458 +
 459 +
 460 +#else /* CONFIG_SSB_DRIVER_GIGE */
 461 +/* Gigabit Ethernet driver disabled */
 462 +
 463 +
 464 +static inline int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
 465 +                                                struct pci_dev *pdev)
 466 +{
 467 +       return -ENOSYS;
 468 +}
 469 +static inline int ssb_gige_map_irq(struct ssb_device *sdev,
 470 +                                  const struct pci_dev *pdev)
 471 +{
 472 +       return -ENOSYS;
 473 +}
 474 +static inline int ssb_gige_init(void)
 475 +{
 476 +       return 0;
 477 +}
 478 +static inline void ssb_gige_exit(void)
 479 +{
 480 +}
 481 +
 482 +static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
 483 +{
 484 +       return 0;
 485 +}
 486 +static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
 487 +{
 488 +       return NULL;
 489 +}
 490 +static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
 491 +{
 492 +       return 0;
 493 +}
 494 +static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
 495 +{
 496 +       return 0;
 497 +}
 498 +static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
 499 +{
 500 +       return 0;
 501 +}
 502 +static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
 503 +{
 504 +       return 0;
 505 +}
 506 +
 507 +#endif /* CONFIG_SSB_DRIVER_GIGE */
 508 +#endif /* LINUX_SSB_DRIVER_GIGE_H_ */
 509 Index: linux-2.6.23.16/drivers/ssb/driver_pcicore.c
 510 ===================================================================
 511 --- linux-2.6.23.16.orig/drivers/ssb/driver_pcicore.c   2008-03-19 11:16:18.000000000 +0100
 512 +++ linux-2.6.23.16/drivers/ssb/driver_pcicore.c        2008-03-19 11:16:18.000000000 +0100
 513 @@ -60,74 +60,6 @@ static DEFINE_SPINLOCK(cfgspace_lock);
 514  /* Core to access the external PCI config space. Can only have one. */
 515  static struct ssb_pcicore *extpci_core;
 516
 517 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
 518 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
 519 -
 520 -int pcibios_plat_dev_init(struct pci_dev *d)
 521 -{
 522 -       struct resource *res;
 523 -       int pos, size;
 524 -       u32 *base;
 525 -
 526 -       ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
 527 -                  pci_name(d));
 528 -
 529 -       /* Fix up resource bases */
 530 -       for (pos = 0; pos < 6; pos++) {
 531 -               res = &d->resource[pos];
 532 -               if (res->flags & IORESOURCE_IO)
 533 -                       base = &ssb_pcicore_pcibus_iobase;
 534 -               else
 535 -                       base = &ssb_pcicore_pcibus_membase;
 536 -               res->flags |= IORESOURCE_PCI_FIXED;
 537 -               if (res->end) {
 538 -                       size = res->end - res->start + 1;
 539 -                       if (*base & (size - 1))
 540 -                               *base = (*base + size) & ~(size - 1);
 541 -                       res->start = *base;
 542 -                       res->end = res->start + size - 1;
 543 -                       *base += size;
 544 -                       pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
 545 -               }
 546 -               /* Fix up PCI bridge BAR0 only */
 547 -               if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
 548 -                       break;
 549 -       }
 550 -       /* Fix up interrupt lines */
 551 -       d->irq = ssb_mips_irq(extpci_core->dev) + 2;
 552 -       pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
 553 -
 554 -       return 0;
 555 -}
 556 -
 557 -static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
 558 -{
 559 -       u8 lat;
 560 -
 561 -       if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
 562 -               return;
 563 -
 564 -       ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
 565 -
 566 -       /* Enable PCI bridge bus mastering and memory space */
 567 -       pci_set_master(dev);
 568 -       pcibios_enable_device(dev, ~0);
 569 -
 570 -       /* Enable PCI bridge BAR1 prefetch and burst */
 571 -       pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
 572 -
 573 -       /* Make sure our latency is high enough to handle the devices behind us */
 574 -       lat = 168;
 575 -       ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
 576 -                  pci_name(dev), lat);
 577 -       pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 578 -}
 579 -DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
 580 -
 581 -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 582 -{
 583 -       return ssb_mips_irq(extpci_core->dev) + 2;
 584 -}
 585
 586  static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
 587                              unsigned int bus, unsigned int dev,
 588 @@ -317,6 +249,92 @@ static struct pci_controller ssb_pcicore
 589         .mem_offset     = 0x24000000,
 590  };
 591
 592 +static u32 ssb_pcicore_pcibus_iobase = 0x100;
 593 +static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
 594 +
 595 +/* This function is called when doing a pci_enable_device().
 596 + * We must first check if the device is a device on the PCI-core bridge. */
 597 +int ssb_pcicore_plat_dev_init(struct pci_dev *d)
 598 +{
 599 +       struct resource *res;
 600 +       int pos, size;
 601 +       u32 *base;
 602 +
 603 +       if (d->bus->ops != &ssb_pcicore_pciops) {
 604 +               /* This is not a device on the PCI-core bridge. */
 605 +               return -ENODEV;
 606 +       }
 607 +
 608 +       ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
 609 +                  pci_name(d));
 610 +
 611 +       /* Fix up resource bases */
 612 +       for (pos = 0; pos < 6; pos++) {
 613 +               res = &d->resource[pos];
 614 +               if (res->flags & IORESOURCE_IO)
 615 +                       base = &ssb_pcicore_pcibus_iobase;
 616 +               else
 617 +                       base = &ssb_pcicore_pcibus_membase;
 618 +               res->flags |= IORESOURCE_PCI_FIXED;
 619 +               if (res->end) {
 620 +                       size = res->end - res->start + 1;
 621 +                       if (*base & (size - 1))
 622 +                               *base = (*base + size) & ~(size - 1);
 623 +                       res->start = *base;
 624 +                       res->end = res->start + size - 1;
 625 +                       *base += size;
 626 +                       pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
 627 +               }
 628 +               /* Fix up PCI bridge BAR0 only */
 629 +               if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
 630 +                       break;
 631 +       }
 632 +       /* Fix up interrupt lines */
 633 +       d->irq = ssb_mips_irq(extpci_core->dev) + 2;
 634 +       pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
 635 +
 636 +       return 0;
 637 +}
 638 +
 639 +/* Early PCI fixup for a device on the PCI-core bridge. */
 640 +static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
 641 +{
 642 +       u8 lat;
 643 +
 644 +       if (dev->bus->ops != &ssb_pcicore_pciops) {
 645 +               /* This is not a device on the PCI-core bridge. */
 646 +               return;
 647 +       }
 648 +       if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
 649 +               return;
 650 +
 651 +       ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
 652 +
 653 +       /* Enable PCI bridge bus mastering and memory space */
 654 +       pci_set_master(dev);
 655 +       pcibios_enable_device(dev, ~0);
 656 +
 657 +       /* Enable PCI bridge BAR1 prefetch and burst */
 658 +       pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
 659 +
 660 +       /* Make sure our latency is high enough to handle the devices behind us */
 661 +       lat = 168;
 662 +       ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
 663 +                  pci_name(dev), lat);
 664 +       pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 665 +}
 666 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
 667 +
 668 +/* PCI device IRQ mapping. */
 669 +int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 670 +{
 671 +       if (dev->bus->ops != &ssb_pcicore_pciops) {
 672 +               /* This is not a device on the PCI-core bridge. */
 673 +               return -ENODEV;
 674 +       }
 675 +       return ssb_mips_irq(extpci_core->dev) + 2;
 676 +}
 677 +
 678  static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
 679  {
 680         u32 val;
 681 Index: linux-2.6.23.16/drivers/ssb/embedded.c
 682 ===================================================================
 683 --- linux-2.6.23.16.orig/drivers/ssb/embedded.c 2008-03-19 11:16:18.000000000 +0100
 684 +++ linux-2.6.23.16/drivers/ssb/embedded.c      2008-03-19 11:16:18.000000000 +0100
 685 @@ -10,6 +10,9 @@
 686
 687  #include <linux/ssb/ssb.h>
 688  #include <linux/ssb/ssb_embedded.h>
 689 +#include <linux/ssb/ssb_driver_pci.h>
 690 +#include <linux/ssb/ssb_driver_gige.h>
 691 +#include <linux/pci.h>
 692
 693  #include "ssb_private.h"
 694
 695 @@ -130,3 +133,90 @@ u32 ssb_gpio_polarity(struct ssb_bus *bu
 696         return res;
 697  }
 698  EXPORT_SYMBOL(ssb_gpio_polarity);
 699 +
 700 +#ifdef CONFIG_SSB_DRIVER_GIGE
 701 +static int gige_pci_init_callback(struct ssb_bus *bus, unsigned long data)
 702 +{
 703 +       struct pci_dev *pdev = (struct pci_dev *)data;
 704 +       struct ssb_device *dev;
 705 +       unsigned int i;
 706 +       int res;
 707 +
 708 +       for (i = 0; i < bus->nr_devices; i++) {
 709 +               dev = &(bus->devices[i]);
 710 +               if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
 711 +                       continue;
 712 +               if (!dev->dev ||
 713 +                   !dev->dev->driver ||
 714 +                   !device_is_registered(dev->dev))
 715 +                       continue;
 716 +               res = ssb_gige_pcibios_plat_dev_init(dev, pdev);
 717 +               if (res >= 0)
 718 +                       return res;
 719 +       }
 720 +
 721 +       return -ENODEV;
 722 +}
 723 +#endif /* CONFIG_SSB_DRIVER_GIGE */
 724 +
 725 +int ssb_pcibios_plat_dev_init(struct pci_dev *dev)
 726 +{
 727 +       int err;
 728 +
 729 +       err = ssb_pcicore_plat_dev_init(dev);
 730 +       if (!err)
 731 +               return 0;
 732 +#ifdef CONFIG_SSB_DRIVER_GIGE
 733 +       err = ssb_for_each_bus_call((unsigned long)dev, gige_pci_init_callback);
 734 +       if (err >= 0)
 735 +               return err;
 736 +#endif
 737 +       /* This is not a PCI device on any SSB device. */
 738 +
 739 +       return -ENODEV;
 740 +}
 741 +
 742 +#ifdef CONFIG_SSB_DRIVER_GIGE
 743 +static int gige_map_irq_callback(struct ssb_bus *bus, unsigned long data)
 744 +{
 745 +       const struct pci_dev *pdev = (const struct pci_dev *)data;
 746 +       struct ssb_device *dev;
 747 +       unsigned int i;
 748 +       int res;
 749 +
 750 +       for (i = 0; i < bus->nr_devices; i++) {
 751 +               dev = &(bus->devices[i]);
 752 +               if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
 753 +                       continue;
 754 +               if (!dev->dev ||
 755 +                   !dev->dev->driver ||
 756 +                   !device_is_registered(dev->dev))
 757 +                       continue;
 758 +               res = ssb_gige_map_irq(dev, pdev);
 759 +               if (res >= 0)
 760 +                       return res;
 761 +       }
 762 +
 763 +       return -ENODEV;
 764 +}
 765 +#endif /* CONFIG_SSB_DRIVER_GIGE */
 766 +
 767 +int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 768 +{
 769 +       int res;
 770 +
 771 +       /* Check if this PCI device is a device on a SSB bus or device
 772 +        * and return the IRQ number for it. */
 773 +
 774 +       res = ssb_pcicore_pcibios_map_irq(dev, slot, pin);
 775 +       if (res >= 0)
 776 +               return res;
 777 +#ifdef CONFIG_SSB_DRIVER_GIGE
 778 +       res = ssb_for_each_bus_call((unsigned long)dev, gige_map_irq_callback);
 779 +       if (res >= 0)
 780 +               return res;
 781 +#endif
 782 +       /* This is not a PCI device on any SSB device. */
 783 +
 784 +       return -ENODEV;
 785 +}
 786 Index: linux-2.6.23.16/include/linux/ssb/ssb.h
 787 ===================================================================
 788 --- linux-2.6.23.16.orig/include/linux/ssb/ssb.h        2008-03-19 11:16:18.000000000 +0100
 789 +++ linux-2.6.23.16/include/linux/ssb/ssb.h     2008-03-19 11:16:18.000000000 +0100
 790 @@ -422,5 +422,12 @@ extern int ssb_bus_powerup(struct ssb_bu
 791  extern u32 ssb_admatch_base(u32 adm);
 792  extern u32 ssb_admatch_size(u32 adm);
 793
 794 +/* PCI device mapping and fixup routines.
 795 + * Called from the architecture pcibios init code.
 796 + * These are only available on SSB_EMBEDDED configurations. */
 797 +#ifdef CONFIG_SSB_EMBEDDED
 798 +int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
 799 +int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 800 +#endif /* CONFIG_SSB_EMBEDDED */
 801
 802  #endif /* LINUX_SSB_H_ */
 803 Index: linux-2.6.23.16/include/linux/ssb/ssb_driver_pci.h
 804 ===================================================================
 805 --- linux-2.6.23.16.orig/include/linux/ssb/ssb_driver_pci.h     2008-03-19 11:16:18.000000000 +0100
 806 +++ linux-2.6.23.16/include/linux/ssb/ssb_driver_pci.h  2008-03-19 11:16:18.000000000 +0100
 807 @@ -1,6 +1,11 @@
 808  #ifndef LINUX_SSB_PCICORE_H_
 809  #define LINUX_SSB_PCICORE_H_
 810
 811 +#include <linux/types.h>
 812 +
 813 +struct pci_dev;
 814 +
 815 +
 816  #ifdef CONFIG_SSB_DRIVER_PCICORE
 817
 818  /* PCI core registers. */
 819 @@ -88,6 +93,9 @@ extern void ssb_pcicore_init(struct ssb_
 820  extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
 821                                           struct ssb_device *dev);
 822
 823 +int ssb_pcicore_plat_dev_init(struct pci_dev *d);
 824 +int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 825 +
 826
 827  #else /* CONFIG_SSB_DRIVER_PCICORE */
 828
 829 @@ -107,5 +115,16 @@ int ssb_pcicore_dev_irqvecs_enable(struc
 830         return 0;
 831  }
 832
 833 +static inline
 834 +int ssb_pcicore_plat_dev_init(struct pci_dev *d)
 835 +{
 836 +       return -ENODEV;
 837 +}
 838 +static inline
 839 +int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 840 +{
 841 +       return -ENODEV;
 842 +}
 843 +
 844  #endif /* CONFIG_SSB_DRIVER_PCICORE */
 845  #endif /* LINUX_SSB_PCICORE_H_ */
 846 Index: linux-2.6.23.16/drivers/ssb/main.c
 847 ===================================================================
 848 --- linux-2.6.23.16.orig/drivers/ssb/main.c     2008-03-19 11:16:18.000000000 +0100
 849 +++ linux-2.6.23.16/drivers/ssb/main.c  2008-03-19 11:16:18.000000000 +0100
 850 @@ -14,6 +14,7 @@
 851  #include <linux/io.h>
 852  #include <linux/ssb/ssb.h>
 853  #include <linux/ssb/ssb_regs.h>
 854 +#include <linux/ssb/ssb_driver_gige.h>
 855  #include <linux/dma-mapping.h>
 856  #include <linux/pci.h>
 857
 858 @@ -68,6 +69,25 @@ found:
 859  }
 860  #endif /* CONFIG_SSB_PCIHOST */
 861
 862 +int ssb_for_each_bus_call(unsigned long data,
 863 +                         int (*func)(struct ssb_bus *bus, unsigned long data))
 864 +{
 865 +       struct ssb_bus *bus;
 866 +       int res;
 867 +
 868 +       ssb_buses_lock();
 869 +       list_for_each_entry(bus, &buses, list) {
 870 +               res = func(bus, data);
 871 +               if (res >= 0) {
 872 +                       ssb_buses_unlock();
 873 +                       return res;
 874 +               }
 875 +       }
 876 +       ssb_buses_unlock();
 877 +
 878 +       return -ENODEV;
 879 +}
 880 +
 881  static struct ssb_device *ssb_device_get(struct ssb_device *dev)
 882  {
 883         if (dev)
 884 @@ -1175,7 +1195,14 @@ static int __init ssb_modinit(void)
 885         err = b43_pci_ssb_bridge_init();
 886         if (err) {
 887                 ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
 888 -                          "initialization failed");
 889 +                          "initialization failed\n");
 890 +               /* don't fail SSB init because of this */
 891 +               err = 0;
 892 +       }
 893 +       err = ssb_gige_init();
 894 +       if (err) {
 895 +               ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
 896 +                          "driver initialization failed\n");
 897                 /* don't fail SSB init because of this */
 898                 err = 0;
 899         }
 900 @@ -1189,6 +1216,7 @@ fs_initcall(ssb_modinit);
 901
 902  static void __exit ssb_modexit(void)
 903  {
 904 +       ssb_gige_exit();
 905         b43_pci_ssb_bridge_exit();
 906         bus_unregister(&ssb_bustype);
 907  }
 908 Index: linux-2.6.23.16/drivers/ssb/ssb_private.h
 909 ===================================================================
 910 --- linux-2.6.23.16.orig/drivers/ssb/ssb_private.h      2008-03-19 11:16:15.000000000 +0100
 911 +++ linux-2.6.23.16/drivers/ssb/ssb_private.h   2008-03-19 11:16:18.000000000 +0100
 912 @@ -118,6 +118,8 @@ extern u32 ssb_calc_clock_rate(u32 pllty
 913  extern int ssb_devices_freeze(struct ssb_bus *bus);
 914  extern int ssb_devices_thaw(struct ssb_bus *bus);
 915  extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
 916 +int ssb_for_each_bus_call(unsigned long data,
 917 +                         int (*func)(struct ssb_bus *bus, unsigned long data));
 918
 919  /* b43_pci_bridge.c */
 920  #ifdef CONFIG_SSB_PCIHOST
 921 Index: linux-2.6.23.16/drivers/net/tg3.c
 922 ===================================================================
 923 --- linux-2.6.23.16.orig/drivers/net/tg3.c      2008-03-19 11:16:15.000000000 +0100
 924 +++ linux-2.6.23.16/drivers/net/tg3.c   2008-03-19 11:16:18.000000000 +0100
 925 @@ -38,6 +38,7 @@
 926  #include <linux/workqueue.h>
 927  #include <linux/prefetch.h>
 928  #include <linux/dma-mapping.h>
 929 +#include <linux/ssb/ssb_driver_gige.h>
 930
 931  #include <net/checksum.h>
 932  #include <net/ip.h>
 933 @@ -410,8 +411,9 @@ static void _tw32_flush(struct tg3 *tp,
 934  static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 935  {
 936         tp->write32_mbox(tp, off, val);
 937 -       if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 938 -           !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 939 +       if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
 940 +           (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 941 +            !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
 942                 tp->read32_mbox(tp, off);
 943  }
 944
 945 @@ -623,7 +625,7 @@ static void tg3_switch_clocks(struct tg3
 946
 947  #define PHY_BUSY_LOOPS 5000
 948
 949 -static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 950 +static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
 951  {
 952         u32 frame_val;
 953         unsigned int loops;
 954 @@ -637,7 +639,7 @@ static int tg3_readphy(struct tg3 *tp, i
 955
 956         *val = 0x0;
 957
 958 -       frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 959 +       frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 960                       MI_COM_PHY_ADDR_MASK);
 961         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 962                       MI_COM_REG_ADDR_MASK);
 963 @@ -672,7 +674,12 @@ static int tg3_readphy(struct tg3 *tp, i
 964         return ret;
 965  }
 966
 967 -static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 968 +static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 969 +{
 970 +       return __tg3_readphy(tp, PHY_ADDR, reg, val);
 971 +}
 972 +
 973 +static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
 974  {
 975         u32 frame_val;
 976         unsigned int loops;
 977 @@ -688,7 +695,7 @@ static int tg3_writephy(struct tg3 *tp,
 978                 udelay(80);
 979         }
 980
 981 -       frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 982 +       frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 983                       MI_COM_PHY_ADDR_MASK);
 984         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 985                       MI_COM_REG_ADDR_MASK);
 986 @@ -721,6 +728,11 @@ static int tg3_writephy(struct tg3 *tp,
 987         return ret;
 988  }
 989
 990 +static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 991 +{
 992 +       return __tg3_writephy(tp, PHY_ADDR, reg, val);
 993 +}
 994 +
 995  static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
 996  {
 997         u32 phy;
 998 @@ -1988,6 +2000,14 @@ static int tg3_setup_copper_phy(struct t
 999                 tp->link_config.active_duplex = current_duplex;
1000         }
1001
1002 +       if (tp->tg3_flags3 & TG3_FLG3_ROBOSWITCH) {
1003 +               current_link_up = 1;
1004 +               current_speed = SPEED_1000; //FIXME
1005 +               current_duplex = DUPLEX_FULL;
1006 +               tp->link_config.active_speed = current_speed;
1007 +               tp->link_config.active_duplex = current_duplex;
1008 +       }
1009 +
1010         if (current_link_up == 1 &&
1011             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1012             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1013 @@ -4813,6 +4833,11 @@ static int tg3_poll_fw(struct tg3 *tp)
1014         int i;
1015         u32 val;
1016
1017 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1018 +               /* We don't use firmware. */
1019 +               return 0;
1020 +       }
1021 +
1022         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1023                 /* Wait up to 20ms for init done. */
1024                 for (i = 0; i < 200; i++) {
1025 @@ -5040,6 +5065,14 @@ static int tg3_chip_reset(struct tg3 *tp
1026                 tw32(0x5000, 0x400);
1027         }
1028
1029 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1030 +               /* BCM4785: In order to avoid repercussions from using potentially
1031 +                * defective internal ROM, stop the Rx RISC CPU, which is not
1032 +                * required. */
1033 +               tg3_stop_fw(tp);
1034 +               tg3_halt_cpu(tp, RX_CPU_BASE);
1035 +       }
1036 +
1037         tw32(GRC_MODE, tp->grc_mode);
1038
1039         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
1040 @@ -5308,9 +5341,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
1041                 return -ENODEV;
1042         }
1043
1044 -       /* Clear firmware's nvram arbitration. */
1045 -       if (tp->tg3_flags & TG3_FLAG_NVRAM)
1046 -               tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1047 +       if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
1048 +               /* Clear firmware's nvram arbitration. */
1049 +               if (tp->tg3_flags & TG3_FLAG_NVRAM)
1050 +                       tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1051 +       }
1052 +
1053         return 0;
1054  }
1055
1056 @@ -5391,6 +5427,11 @@ static int tg3_load_5701_a0_firmware_fix
1057         struct fw_info info;
1058         int err, i;
1059
1060 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1061 +               /* We don't use firmware. */
1062 +               return 0;
1063 +       }
1064 +
1065         info.text_base = TG3_FW_TEXT_ADDR;
1066         info.text_len = TG3_FW_TEXT_LEN;
1067         info.text_data = &tg3FwText[0];
1068 @@ -5949,6 +5990,11 @@ static int tg3_load_tso_firmware(struct
1069         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
1070         int err, i;
1071
1072 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1073 +               /* We don't use firmware. */
1074 +               return 0;
1075 +       }
1076 +
1077         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
1078                 return 0;
1079
1080 @@ -6850,6 +6896,11 @@ static void tg3_timer(unsigned long __op
1081
1082         spin_lock(&tp->lock);
1083
1084 +       if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
1085 +               /* BCM4785: Flush posted writes from GbE to host memory. */
1086 +               tr32(HOSTCC_MODE);
1087 +       }
1088 +
1089         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
1090                 /* All of this garbage is because when using non-tagged
1091                  * IRQ status the mailbox/status_block protocol the chip
1092 @@ -8432,6 +8483,11 @@ static int tg3_test_nvram(struct tg3 *tp
1093         u32 *buf, csum, magic;
1094         int i, j, err = 0, size;
1095
1096 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1097 +               /* We don't have NVRAM. */
1098 +               return 0;
1099 +       }
1100 +
1101         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1102                 return -EIO;
1103
1104 @@ -9154,7 +9210,7 @@ static int tg3_ioctl(struct net_device *
1105                         return -EAGAIN;
1106
1107                 spin_lock_bh(&tp->lock);
1108 -               err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
1109 +               err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
1110                 spin_unlock_bh(&tp->lock);
1111
1112                 data->val_out = mii_regval;
1113 @@ -9173,7 +9229,7 @@ static int tg3_ioctl(struct net_device *
1114                         return -EAGAIN;
1115
1116                 spin_lock_bh(&tp->lock);
1117 -               err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
1118 +               err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1119                 spin_unlock_bh(&tp->lock);
1120
1121                 return err;
1122 @@ -9571,6 +9627,12 @@ static void __devinit tg3_get_5906_nvram
1123  /* Chips other than 5700/5701 use the NVRAM for fetching info. */
1124  static void __devinit tg3_nvram_init(struct tg3 *tp)
1125  {
1126 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1127 +               /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
1128 +               tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
1129 +               return;
1130 +       }
1131 +
1132         tw32_f(GRC_EEPROM_ADDR,
1133              (EEPROM_ADDR_FSM_RESET |
1134               (EEPROM_DEFAULT_CLOCK_PERIOD <<
1135 @@ -9706,6 +9768,9 @@ static int tg3_nvram_read(struct tg3 *tp
1136  {
1137         int ret;
1138
1139 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
1140 +               return -ENODEV;
1141 +
1142         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
1143                 return tg3_nvram_read_using_eeprom(tp, offset, val);
1144
1145 @@ -9938,6 +10003,9 @@ static int tg3_nvram_write_block(struct
1146  {
1147         int ret;
1148
1149 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
1150 +               return -ENODEV;
1151 +
1152         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
1153                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
1154                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
1155 @@ -10804,7 +10872,6 @@ static int __devinit tg3_get_invariants(
1156                 tp->write32 = tg3_write_flush_reg32;
1157         }
1158
1159 -
1160         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
1161             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
1162                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
1163 @@ -10840,6 +10907,11 @@ static int __devinit tg3_get_invariants(
1164               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
1165                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
1166
1167 +       if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
1168 +               tp->write32_tx_mbox = tg3_write_flush_reg32;
1169 +               tp->write32_rx_mbox = tg3_write_flush_reg32;
1170 +       }
1171 +
1172         /* Get eeprom hw config before calling tg3_set_power_state().
1173          * In particular, the TG3_FLG2_IS_NIC flag must be
1174          * determined before calling tg3_set_power_state() so that
1175 @@ -11184,6 +11256,10 @@ static int __devinit tg3_get_device_addr
1176         }
1177
1178         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
1179 +               if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
1180 +                       ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
1181 +       }
1182 +       if (!is_valid_ether_addr(&dev->dev_addr[0])) {
1183  #ifdef CONFIG_SPARC64
1184                 if (!tg3_get_default_macaddr_sparc(tp))
1185                         return 0;
1186 @@ -11675,6 +11751,7 @@ static char * __devinit tg3_phy_string(s
1187         case PHY_ID_BCM5704:    return "5704";
1188         case PHY_ID_BCM5705:    return "5705";
1189         case PHY_ID_BCM5750:    return "5750";
1190 +       case PHY_ID_BCM5750_2:  return "5750-2";
1191         case PHY_ID_BCM5752:    return "5752";
1192         case PHY_ID_BCM5714:    return "5714";
1193         case PHY_ID_BCM5780:    return "5780";
1194 @@ -11859,6 +11936,13 @@ static int __devinit tg3_init_one(struct
1195                 tp->msg_enable = tg3_debug;
1196         else
1197                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
1198 +       if (pdev_is_ssb_gige_core(pdev)) {
1199 +               tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
1200 +               if (ssb_gige_must_flush_posted_writes(pdev))
1201 +                       tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
1202 +               if (ssb_gige_have_roboswitch(pdev))
1203 +                       tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
1204 +       }
1205
1206         /* The word/byte swap controls here control register access byte
1207          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
1208 Index: linux-2.6.23.16/drivers/net/tg3.h
1209 ===================================================================
1210 --- linux-2.6.23.16.orig/drivers/net/tg3.h      2008-03-19 11:16:15.000000000 +0100
1211 +++ linux-2.6.23.16/drivers/net/tg3.h   2008-03-19 11:16:18.000000000 +0100
1212 @@ -2279,6 +2279,10 @@ struct tg3 {
1213  #define TG3_FLG2_PHY_JITTER_BUG                0x20000000
1214  #define TG3_FLG2_NO_FWARE_REPORTED     0x40000000
1215  #define TG3_FLG2_PHY_ADJUST_TRIM       0x80000000
1216 +       u32                             tg3_flags3;
1217 +#define TG3_FLG3_IS_SSB_CORE           0x00000001
1218 +#define TG3_FLG3_FLUSH_POSTED_WRITES   0x00000002
1219 +#define TG3_FLG3_ROBOSWITCH            0x00000004
1220
1221         struct timer_list               timer;
1222         u16                             timer_counter;
1223 @@ -2333,6 +2337,7 @@ struct tg3 {
1224  #define PHY_ID_BCM5714                 0x60008340
1225  #define PHY_ID_BCM5780                 0x60008350
1226  #define PHY_ID_BCM5755                 0xbc050cc0
1227 +#define PHY_ID_BCM5750_2               0xbc050cd0
1228  #define PHY_ID_BCM5787                 0xbc050ce0
1229  #define PHY_ID_BCM5756                 0xbc050ed0
1230  #define PHY_ID_BCM5906                 0xdc00ac40
1231 @@ -2364,7 +2369,8 @@ struct tg3 {
1232          (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
1233          (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
1234          (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
1235 -        (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM8002)
1236 +        (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM8002 || \
1237 +        (X) == PHY_ID_BCM5750_2)
1238
1239         struct tg3_hw_stats             *hw_stats;
1240         dma_addr_t                      stats_mapping;
1241 Index: linux-2.6.23.16/drivers/ssb/driver_mipscore.c
1242 ===================================================================
1243 --- linux-2.6.23.16.orig/drivers/ssb/driver_mipscore.c  2008-03-19 11:16:18.000000000 +0100
1244 +++ linux-2.6.23.16/drivers/ssb/driver_mipscore.c       2008-03-19 11:16:18.000000000 +0100
1245 @@ -211,6 +211,7 @@ void ssb_mipscore_init(struct ssb_mipsco
1246                         /* fallthrough */
1247                 case SSB_DEV_PCI:
1248                 case SSB_DEV_ETHERNET:
1249 +               case SSB_DEV_ETHERNET_GBIT:
1250                 case SSB_DEV_80211:
1251                 case SSB_DEV_USB20_HOST:
1252                         /* These devices get their own IRQ line if available, the rest goes on IRQ0 */