target/linux/brcm47xx/patches-2.6.25/602-ssb-fix-serial-on-new-devices.patch

   1 Index: linux-2.6.23.16/drivers/ssb/driver_chipcommon.c
   2 ===================================================================
   3 --- linux-2.6.23.16.orig/drivers/ssb/driver_chipcommon.c        2008-02-19 14:37:26.000000000 +0100
   4 +++ linux-2.6.23.16/drivers/ssb/driver_chipcommon.c     2008-02-19 14:37:27.000000000 +0100
   5 @@ -403,6 +403,7 @@ int ssb_chipco_serial_init(struct ssb_ch
   6         unsigned int irq;
   7         u32 baud_base, div;
   8         u32 i, n;
   9 +       unsigned int ccrev = cc->dev->id.revision;
  10
  11         plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
  12         irq = ssb_mips_irq(cc->dev);
  13 @@ -414,14 +415,39 @@ int ssb_chipco_serial_init(struct ssb_ch
  14                                                 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
  15                 div = 1;
  16         } else {
  17 -               if (cc->dev->id.revision >= 11) {
  18 +               if (ccrev == 20) {
  19 +                       /* BCM5354 uses constant 25MHz clock */
  20 +                       baud_base = 25000000;
  21 +                       div = 48;
  22 +                       /* Set the override bit so we don't divide it */
  23 +                       chipco_write32(cc, SSB_CHIPCO_CORECTL,
  24 +                                      chipco_read32(cc, SSB_CHIPCO_CORECTL)
  25 +                                      | SSB_CHIPCO_CORECTL_UARTCLK0);
  26 +               } else if ((ccrev >= 11) && (ccrev != 15)) {
  27                         /* Fixed ALP clock */
  28                         baud_base = 20000000;
  29 +                       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
  30 +                               /* FIXME: baud_base is different for devices with a PMU */
  31 +                               SSB_WARN_ON(1);
  32 +                       }
  33                         div = 1;
  34 +                       if (ccrev >= 21) {
  35 +                               /* Turn off UART clock before switching clocksource. */
  36 +                               chipco_write32(cc, SSB_CHIPCO_CORECTL,
  37 +                                              chipco_read32(cc, SSB_CHIPCO_CORECTL)
  38 +                                              & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
  39 +                       }
  40                         /* Set the override bit so we don't divide it */
  41                         chipco_write32(cc, SSB_CHIPCO_CORECTL,
  42 -                                      SSB_CHIPCO_CORECTL_UARTCLK0);
  43 -               } else if (cc->dev->id.revision >= 3) {
  44 +                                      chipco_read32(cc, SSB_CHIPCO_CORECTL)
  45 +                                      | SSB_CHIPCO_CORECTL_UARTCLK0);
  46 +                       if (ccrev >= 21) {
  47 +                               /* Re-enable the UART clock. */
  48 +                               chipco_write32(cc, SSB_CHIPCO_CORECTL,
  49 +                                              chipco_read32(cc, SSB_CHIPCO_CORECTL)
  50 +                                              | SSB_CHIPCO_CORECTL_UARTCLKEN);
  51 +                       }
  52 +               } else if (ccrev >= 3) {
  53                         /* Internal backplane clock */
  54                         baud_base = ssb_clockspeed(bus);
  55                         div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
  56 @@ -433,7 +459,7 @@ int ssb_chipco_serial_init(struct ssb_ch
  57                 }
  58
  59                 /* Clock source depends on strapping if UartClkOverride is unset */
  60 -               if ((cc->dev->id.revision > 0) &&
  61 +               if ((ccrev > 0) &&
  62                     !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
  63                         if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
  64                             SSB_CHIPCO_CAP_UARTCLK_INT) {
  65 @@ -455,7 +481,7 @@ int ssb_chipco_serial_init(struct ssb_ch
  66                 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
  67                 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
  68                 /* Offset changed at after rev 0 */
  69 -               if (cc->dev->id.revision == 0)
  70 +               if (ccrev == 0)
  71                         uart_regs += (i * 8);
  72                 else
  73                         uart_regs += (i * 256);
  74 Index: linux-2.6.23.16/include/linux/ssb/ssb_driver_chipcommon.h
  75 ===================================================================
  76 --- linux-2.6.23.16.orig/include/linux/ssb/ssb_driver_chipcommon.h      2008-02-19 14:37:26.000000000 +0100
  77 +++ linux-2.6.23.16/include/linux/ssb/ssb_driver_chipcommon.h   2008-02-19 14:37:27.000000000 +0100
  78 @@ -51,9 +51,12 @@
  79  #define  SSB_CHIPCO_CAP_JTAGM          0x00400000      /* JTAG master present */
  80  #define  SSB_CHIPCO_CAP_BROM           0x00800000      /* Internal boot ROM active */
  81  #define  SSB_CHIPCO_CAP_64BIT          0x08000000      /* 64-bit Backplane */
  82 +#define  SSB_CHIPCO_CAP_PMU            0x10000000      /* PMU available (rev >= 20) */
  83 +#define  SSB_CHIPCO_CAP_ECI            0x20000000      /* ECI available (rev >= 20) */
  84  #define SSB_CHIPCO_CORECTL             0x0008
  85  #define  SSB_CHIPCO_CORECTL_UARTCLK0   0x00000001      /* Drive UART with internal clock */
  86  #define         SSB_CHIPCO_CORECTL_SE          0x00000002      /* sync clk out enable (corerev >= 3) */
  87 +#define  SSB_CHIPCO_CORECTL_UARTCLKEN  0x00000008      /* UART clock enable (rev >= 21) */
  88  #define SSB_CHIPCO_BIST                        0x000C
  89  #define SSB_CHIPCO_OTPS                        0x0010          /* OTP status */
  90  #define         SSB_CHIPCO_OTPS_PROGFAIL       0x80000000