target/linux/brcm47xx/patches-2.6.25/250-ohci-ssb-usb2.patch

   1 --- a/drivers/usb/host/ohci-ssb.c
   2 +++ b/drivers/usb/host/ohci-ssb.c
   3 @@ -142,10 +142,59 @@ static int ssb_ohci_attach(struct ssb_de
   4         int err = -ENOMEM;
   5         u32 tmp, flags = 0;
   6
   7 -       if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV)
   8 +       /*
   9 +        * THE FOLLOWING COMMENTS PRESERVED FROM GPL SOURCE RELEASE
  10 +        *
  11 +        * The USB core requires a special bit to be set during core
  12 +        * reset to enable host (OHCI) mode. Resetting the SB core in
  13 +        * pcibios_enable_device() is a hack for compatibility with
  14 +        * vanilla usb-ohci so that it does not have to know about
  15 +        * SB. A driver that wants to use the USB core in device mode
  16 +        * should know about SB and should reset the bit back to 0
  17 +        * after calling pcibios_enable_device().
  18 +        */
  19 +
  20 +       if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) {
  21                 flags |= SSB_OHCI_TMSLOW_HOSTMODE;
  22 +               ssb_device_enable(dev, flags);
  23 +       }
  24 +
  25 +       /*
  26 +        * USB 2.0 special considerations:
  27 +        *
  28 +        * 1. Since the core supports both OHCI and EHCI functions, it must
  29 +        *    only be reset once.
  30 +        *
  31 +        * 2. In addition to the standard SB reset sequence, the Host Control
  32 +        *    Register must be programmed to bring the USB core and various
  33 +        *    phy components out of reset.
  34 +        */
  35 +
  36 +       else if (dev->id.coreid == SSB_DEV_USB20_HOST) {
  37 +#warning FIX ME need test for core being up & exit
  38 +               ssb_device_enable(dev, 0);
  39 +               ssb_write32(dev, 0x200, 0x7ff);
  40 +               udelay(1);
  41 +               if (dev->id.revision == 1) { // bug in rev 1
  42 +
  43 +                       /* Change Flush control reg */
  44 +                       tmp = ssb_read32(dev, 0x400);
  45 +                       tmp &= ~8;
  46 +                       ssb_write32(dev, 0x400, tmp);
  47 +                       tmp = ssb_read32(dev, 0x400);
  48 +                       printk("USB20H fcr: 0x%0x\n", tmp);
  49 +
  50 +                       /* Change Shim control reg */
  51 +                       tmp = ssb_read32(dev, 0x304);
  52 +                       tmp &= ~0x100;
  53 +                       ssb_write32(dev, 0x304, tmp);
  54 +                       tmp = ssb_read32(dev, 0x304);
  55 +                       printk("USB20H shim: 0x%0x\n", tmp);
  56 +               }
  57 +       }
  58 +       else
  59 +               ssb_device_enable(dev, 0);
  60
  61 -       ssb_device_enable(dev, flags);
  62
  63         hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
  64                         dev->dev->bus_id);
  65 @@ -236,6 +285,7 @@ static int ssb_ohci_resume(struct ssb_de
  66  static const struct ssb_device_id ssb_ohci_table[] = {
  67         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV),
  68         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV),
  69 +       SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV),
  70         SSB_DEVTABLE_END
  71  };
  72  MODULE_DEVICE_TABLE(ssb, ssb_ohci_table);