target/linux/brcm2708/patches-3.3/0002-Main-bcm2708-linux-port.patch

   1 From d5ef856b4628a4531c1627dec100eeff15e8b31e Mon Sep 17 00:00:00 2001
   2 From: popcornmix <popcornmix@gmail.com>
   3 Date: Tue, 17 Jan 2012 19:20:11 +0000
   4 Subject: [PATCH 2/7] Main bcm2708 linux port
   5
   6 Signed-off-by: popcornmix <popcornmix@gmail.com>
   7 ---
   8  arch/arm/Kconfig                                   |   14 +
   9  arch/arm/Makefile                                  |    1 +
  10  arch/arm/boot/compressed/Makefile                  |    8 +-
  11  arch/arm/boot/compressed/divdi3.c                  |  338 +++++
  12  arch/arm/boot/compressed/longlong.h                |  151 ++
  13  arch/arm/configs/bcmrpi_cutdown_defconfig          | 1558 ++++++++++++++++++++
  14  arch/arm/kernel/armksyms.c                         |    4 +
  15  arch/arm/lib/Makefile                              |    3 +-
  16  arch/arm/lib/divdi3.c                              |  338 +++++
  17  arch/arm/lib/lib1funcs.S                           |   27 +
  18  arch/arm/lib/longlong.h                            |  151 ++
  19  arch/arm/mach-bcm2708/Kconfig                      |   25 +
  20  arch/arm/mach-bcm2708/Makefile                     |    8 +
  21  arch/arm/mach-bcm2708/Makefile.boot                |    3 +
  22  arch/arm/mach-bcm2708/armctrl.c                    |  399 +++++
  23  arch/arm/mach-bcm2708/armctrl.h                    |   27 +
  24  arch/arm/mach-bcm2708/bcm2708.c                    |  658 +++++++++
  25  arch/arm/mach-bcm2708/bcm2708.h                    |   51 +
  26  arch/arm/mach-bcm2708/bcm2708_gpio.c               |  323 ++++
  27  arch/arm/mach-bcm2708/clock.c                      |   61 +
  28  arch/arm/mach-bcm2708/clock.h                      |   24 +
  29  arch/arm/mach-bcm2708/dma.c                        |  397 +++++
  30  arch/arm/mach-bcm2708/include/mach/arm_control.h   |  419 ++++++
  31  arch/arm/mach-bcm2708/include/mach/arm_power.h     |   60 +
  32  arch/arm/mach-bcm2708/include/mach/clkdev.h        |    7 +
  33  arch/arm/mach-bcm2708/include/mach/debug-macro.S   |   24 +
  34  arch/arm/mach-bcm2708/include/mach/dma.h           |   84 ++
  35  arch/arm/mach-bcm2708/include/mach/entry-macro.S   |   69 +
  36  arch/arm/mach-bcm2708/include/mach/frc.h           |   38 +
  37  arch/arm/mach-bcm2708/include/mach/gpio.h          |   48 +
  38  arch/arm/mach-bcm2708/include/mach/hardware.h      |   28 +
  39  arch/arm/mach-bcm2708/include/mach/io.h            |   28 +
  40  arch/arm/mach-bcm2708/include/mach/irqs.h          |  190 +++
  41  arch/arm/mach-bcm2708/include/mach/irqs.h.orig     |  185 +++
  42  arch/arm/mach-bcm2708/include/mach/memory.h        |   59 +
  43  arch/arm/mach-bcm2708/include/mach/platform.h      |  210 +++
  44  arch/arm/mach-bcm2708/include/mach/platform.h.orig |  210 +++
  45  arch/arm/mach-bcm2708/include/mach/power.h         |   26 +
  46  arch/arm/mach-bcm2708/include/mach/system.h        |   53 +
  47  arch/arm/mach-bcm2708/include/mach/timex.h         |   23 +
  48  arch/arm/mach-bcm2708/include/mach/uncompress.h    |   49 +
  49  arch/arm/mach-bcm2708/include/mach/vc_mem.h        |   34 +
  50  arch/arm/mach-bcm2708/include/mach/vcio.h          |   42 +
  51  arch/arm/mach-bcm2708/include/mach/vmalloc.h       |   20 +
  52  arch/arm/mach-bcm2708/power.c                      |  193 +++
  53  arch/arm/mach-bcm2708/vc_mem.c                     |  467 ++++++
  54  arch/arm/mach-bcm2708/vcio.c                       |  309 ++++
  55  arch/arm/mm/Kconfig                                |    2 +-
  56  arch/arm/mm/alignment.c                            |    6 +-
  57  arch/arm/mm/proc-v6.S                              |   15 +-
  58  drivers/mmc/host/Kconfig                           |   29 +
  59  drivers/mmc/host/Makefile                          |    2 +
  60  drivers/mmc/host/bcm2708_mci.c                     |  889 +++++++++++
  61  drivers/mmc/host/bcm2708_mci.h                     |  101 ++
  62  drivers/mmc/host/sdhci-bcm2708.c                   | 1461 ++++++++++++++++++
  63  drivers/mmc/host/sdhci.c                           |  623 ++++++---
  64  drivers/mmc/host/sdhci.h                           |   46 +
  65  include/linux/mmc/host.h                           |   29 +
  66  include/linux/mmc/sdhci.h                          |   10 +
  67  59 files changed, 10481 insertions(+), 176 deletions(-)
  68  create mode 100644 arch/arm/boot/compressed/divdi3.c
  69  create mode 100644 arch/arm/boot/compressed/longlong.h
  70  create mode 100644 arch/arm/configs/bcmrpi_cutdown_defconfig
  71  create mode 100644 arch/arm/lib/divdi3.c
  72  create mode 100644 arch/arm/lib/longlong.h
  73  create mode 100644 arch/arm/mach-bcm2708/Kconfig
  74  create mode 100644 arch/arm/mach-bcm2708/Makefile
  75  create mode 100644 arch/arm/mach-bcm2708/Makefile.boot
  76  create mode 100644 arch/arm/mach-bcm2708/armctrl.c
  77  create mode 100644 arch/arm/mach-bcm2708/armctrl.h
  78  create mode 100644 arch/arm/mach-bcm2708/bcm2708.c
  79  create mode 100644 arch/arm/mach-bcm2708/bcm2708.h
  80  create mode 100644 arch/arm/mach-bcm2708/bcm2708_gpio.c
  81  create mode 100644 arch/arm/mach-bcm2708/clock.c
  82  create mode 100644 arch/arm/mach-bcm2708/clock.h
  83  create mode 100644 arch/arm/mach-bcm2708/dma.c
  84  create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_control.h
  85  create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_power.h
  86  create mode 100644 arch/arm/mach-bcm2708/include/mach/clkdev.h
  87  create mode 100644 arch/arm/mach-bcm2708/include/mach/debug-macro.S
  88  create mode 100644 arch/arm/mach-bcm2708/include/mach/dma.h
  89  create mode 100644 arch/arm/mach-bcm2708/include/mach/entry-macro.S
  90  create mode 100644 arch/arm/mach-bcm2708/include/mach/frc.h
  91  create mode 100644 arch/arm/mach-bcm2708/include/mach/gpio.h
  92  create mode 100644 arch/arm/mach-bcm2708/include/mach/hardware.h
  93  create mode 100644 arch/arm/mach-bcm2708/include/mach/io.h
  94  create mode 100644 arch/arm/mach-bcm2708/include/mach/irqs.h
  95  create mode 100644 arch/arm/mach-bcm2708/include/mach/irqs.h.orig
  96  create mode 100644 arch/arm/mach-bcm2708/include/mach/memory.h
  97  create mode 100644 arch/arm/mach-bcm2708/include/mach/platform.h
  98  create mode 100644 arch/arm/mach-bcm2708/include/mach/platform.h.orig
  99  create mode 100644 arch/arm/mach-bcm2708/include/mach/power.h
 100  create mode 100644 arch/arm/mach-bcm2708/include/mach/system.h
 101  create mode 100644 arch/arm/mach-bcm2708/include/mach/timex.h
 102  create mode 100644 arch/arm/mach-bcm2708/include/mach/uncompress.h
 103  create mode 100644 arch/arm/mach-bcm2708/include/mach/vc_mem.h
 104  create mode 100644 arch/arm/mach-bcm2708/include/mach/vcio.h
 105  create mode 100644 arch/arm/mach-bcm2708/include/mach/vmalloc.h
 106  create mode 100644 arch/arm/mach-bcm2708/power.c
 107  create mode 100644 arch/arm/mach-bcm2708/vc_mem.c
 108  create mode 100644 arch/arm/mach-bcm2708/vcio.c
 109  create mode 100644 drivers/mmc/host/bcm2708_mci.c
 110  create mode 100644 drivers/mmc/host/bcm2708_mci.h
 111  create mode 100644 drivers/mmc/host/sdhci-bcm2708.c
 112
 113 --- a/arch/arm/Kconfig
 114 +++ b/arch/arm/Kconfig
 115 @@ -961,6 +961,20 @@ config PLAT_SPEAR
 116         help
 117           Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 118
 119 +config ARCH_BCM2708
 120 +       bool "Broadcom BCM2708 family"
 121 +       select CPU_V6
 122 +       select ARM_AMBA
 123 +       select HAVE_CLK
 124 +       select CLKDEV_LOOKUP
 125 +       select GENERIC_CLOCKEVENTS
 126 +       select ARM_ERRATA_411920
 127 +       select MACH_BCM2708
 128 +       select VC4
 129 +       select NEED_MACH_MEMORY_H
 130 +       help
 131 +         This enables support for Broadcom BCM2708 boards.
 132 +
 133  config ARCH_VT8500
 134         bool "VIA/WonderMedia 85xx"
 135         select CPU_ARM926T
 136 @@ -1103,6 +1117,7 @@ source "arch/arm/plat-versatile/Kconfig"
 137  source "arch/arm/mach-vt8500/Kconfig"
 138
 139  source "arch/arm/mach-w90x900/Kconfig"
 140 +source "arch/arm/mach-bcm2708/Kconfig"
 141
 142  # Definitions to make life easier
 143  config ARCH_ACORN
 144 --- a/arch/arm/Makefile
 145 +++ b/arch/arm/Makefile
 146 @@ -196,6 +196,7 @@ machine-$(CONFIG_MACH_SPEAR310)             := spea
 147  machine-$(CONFIG_MACH_SPEAR320)                := spear3xx
 148  machine-$(CONFIG_MACH_SPEAR600)                := spear6xx
 149  machine-$(CONFIG_ARCH_ZYNQ)            := zynq
 150 +machine-$(CONFIG_ARCH_BCM2708)         := bcm2708
 151
 152  # Platform directory name.  This list is sorted alphanumerically
 153  # by CONFIG_* macro name.
 154 --- a/arch/arm/boot/compressed/Makefile
 155 +++ b/arch/arm/boot/compressed/Makefile
 156 @@ -147,11 +147,17 @@ LDFLAGS_vmlinux += -X
 157  LDFLAGS_vmlinux += -T
 158
 159  # For __aeabi_uidivmod
 160 -lib1funcs = $(obj)/lib1funcs.o
 161 +lib1funcs = $(obj)/lib1funcs.o $(obj)/divdi3.o
 162
 163  $(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S
 164         $(call cmd,shipped)
 165
 166 +$(obj)/longlong.h: $(srctree)/arch/$(SRCARCH)/lib/longlong.h FORCE
 167 +       $(call cmd,shipped)
 168 +
 169 +$(obj)/divdi3.c: $(srctree)/arch/$(SRCARCH)/lib/divdi3.c $(obj)/longlong.h FORCE
 170 +       $(call cmd,shipped)
 171 +
 172  # We need to prevent any GOTOFF relocs being used with references
 173  # to symbols in the .bss section since we cannot relocate them
 174  # independently from the rest at run time.  This can be achieved by
 175 --- /dev/null
 176 +++ b/arch/arm/boot/compressed/divdi3.c
 177 @@ -0,0 +1,338 @@
 178 +/* 64-bit multiplication and division
 179 +   Copyright (C) 1989, 1992-1999, 2000, 2001, 2002, 2003
 180 +   Free Software Foundation, Inc.
 181 +   This file is part of the GNU C Library.
 182 +
 183 +   The GNU C Library is free software; you can redistribute it and/or
 184 +   modify it under the terms of the GNU Lesser General Public
 185 +   License as published by the Free Software Foundation; either
 186 +   version 2.1 of the License, or (at your option) any later version.
 187 +
 188 +   The GNU C Library is distributed in the hope that it will be useful,
 189 +   but WITHOUT ANY WARRANTY; without even the implied warranty of
 190 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 191 +   Lesser General Public License for more details.
 192 +
 193 +   You should have received a copy of the GNU Lesser General Public
 194 +   License along with the GNU C Library; if not, write to the Free
 195 +   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
 196 +   02111-1307 USA.  */
 197 +
 198 +#include "longlong.h"
 199 +
 200 +#define W_TYPE_SIZE (sizeof(long))
 201 +
 202 +#ifdef __ARMEB__
 203 +struct DWstruct { long high, low;};
 204 +#else
 205 +struct DWstruct { long low, high;};
 206 +#endif
 207 +
 208 +typedef union { struct DWstruct s; long long ll; } DWunion;
 209 +
 210 +/* Prototypes of exported functions.  */
 211 +long long __divdi3 (long long u, long long v);
 212 +long long __moddi3 (long long u, long long v);
 213 +unsigned long long __udivdi3 (unsigned long long u, unsigned long long v);
 214 +unsigned long long __umoddi3 (unsigned long long u, unsigned long long v);
 215 +
 216 +static unsigned long long
 217 +__udivmoddi4 (unsigned long long n, unsigned long long d, unsigned long long *rp)
 218 +{
 219 +  DWunion ww;
 220 +  DWunion nn, dd;
 221 +  DWunion rr;
 222 +  unsigned long d0, d1, n0, n1, n2;
 223 +  unsigned long q0, q1;
 224 +  unsigned long b, bm;
 225 +
 226 +  nn.ll = n;
 227 +  dd.ll = d;
 228 +
 229 +  d0 = dd.s.low;
 230 +  d1 = dd.s.high;
 231 +  n0 = nn.s.low;
 232 +  n1 = nn.s.high;
 233 +
 234 +#if !UDIV_NEEDS_NORMALIZATION
 235 +  if (d1 == 0)
 236 +    {
 237 +      if (d0 > n1)
 238 +       {
 239 +         /* 0q = nn / 0D */
 240 +
 241 +         udiv_qrnnd (q0, n0, n1, n0, d0);
 242 +         q1 = 0;
 243 +
 244 +         /* Remainder in n0.  */
 245 +       }
 246 +      else
 247 +       {
 248 +         /* qq = NN / 0d */
 249 +
 250 +         if (d0 == 0)
 251 +           d0 = 1 / d0;        /* Divide intentionally by zero.  */
 252 +
 253 +         udiv_qrnnd (q1, n1, 0, n1, d0);
 254 +         udiv_qrnnd (q0, n0, n1, n0, d0);
 255 +
 256 +         /* Remainder in n0.  */
 257 +       }
 258 +
 259 +      if (rp != 0)
 260 +       {
 261 +         rr.s.low = n0;
 262 +         rr.s.high = 0;
 263 +         *rp = rr.ll;
 264 +       }
 265 +    }
 266 +
 267 +#else /* UDIV_NEEDS_NORMALIZATION */
 268 +
 269 +  if (d1 == 0)
 270 +    {
 271 +      if (d0 > n1)
 272 +       {
 273 +         /* 0q = nn / 0D */
 274 +
 275 +         count_leading_zeros (bm, d0);
 276 +
 277 +         if (bm != 0)
 278 +           {
 279 +             /* Normalize, i.e. make the most significant bit of the
 280 +                denominator set.  */
 281 +
 282 +             d0 = d0 << bm;
 283 +             n1 = (n1 << bm) | (n0 >> (W_TYPE_SIZE - bm));
 284 +             n0 = n0 << bm;
 285 +           }
 286 +
 287 +         udiv_qrnnd (q0, n0, n1, n0, d0);
 288 +         q1 = 0;
 289 +
 290 +         /* Remainder in n0 >> bm.  */
 291 +       }
 292 +      else
 293 +       {
 294 +         /* qq = NN / 0d */
 295 +
 296 +         if (d0 == 0)
 297 +           d0 = 1 / d0;        /* Divide intentionally by zero.  */
 298 +
 299 +         count_leading_zeros (bm, d0);
 300 +
 301 +         if (bm == 0)
 302 +           {
 303 +             /* From (n1 >= d0) /\ (the most significant bit of d0 is set),
 304 +                conclude (the most significant bit of n1 is set) /\ (the
 305 +                leading quotient digit q1 = 1).
 306 +
 307 +                This special case is necessary, not an optimization.
 308 +                (Shifts counts of W_TYPE_SIZE are undefined.)  */
 309 +
 310 +             n1 -= d0;
 311 +             q1 = 1;
 312 +           }
 313 +         else
 314 +           {
 315 +             /* Normalize.  */
 316 +
 317 +             b = W_TYPE_SIZE - bm;
 318 +
 319 +             d0 = d0 << bm;
 320 +             n2 = n1 >> b;
 321 +             n1 = (n1 << bm) | (n0 >> b);
 322 +             n0 = n0 << bm;
 323 +
 324 +             udiv_qrnnd (q1, n1, n2, n1, d0);
 325 +           }
 326 +
 327 +         /* n1 != d0...  */
 328 +
 329 +         udiv_qrnnd (q0, n0, n1, n0, d0);
 330 +
 331 +         /* Remainder in n0 >> bm.  */
 332 +       }
 333 +
 334 +      if (rp != 0)
 335 +       {
 336 +         rr.s.low = n0 >> bm;
 337 +         rr.s.high = 0;
 338 +         *rp = rr.ll;
 339 +       }
 340 +    }
 341 +#endif /* UDIV_NEEDS_NORMALIZATION */
 342 +
 343 +  else
 344 +    {
 345 +      if (d1 > n1)
 346 +       {
 347 +         /* 00 = nn / DD */
 348 +
 349 +         q0 = 0;
 350 +         q1 = 0;
 351 +
 352 +         /* Remainder in n1n0.  */
 353 +         if (rp != 0)
 354 +           {
 355 +             rr.s.low = n0;
 356 +             rr.s.high = n1;
 357 +             *rp = rr.ll;
 358 +           }
 359 +       }
 360 +      else
 361 +       {
 362 +         /* 0q = NN / dd */
 363 +
 364 +         count_leading_zeros (bm, d1);
 365 +         if (bm == 0)
 366 +           {
 367 +             /* From (n1 >= d1) /\ (the most significant bit of d1 is set),
 368 +                conclude (the most significant bit of n1 is set) /\ (the
 369 +                quotient digit q0 = 0 or 1).
 370 +
 371 +                This special case is necessary, not an optimization.  */
 372 +
 373 +             /* The condition on the next line takes advantage of that
 374 +                n1 >= d1 (true due to program flow).  */
 375 +             if (n1 > d1 || n0 >= d0)
 376 +               {
 377 +                 q0 = 1;
 378 +                 sub_ddmmss (n1, n0, n1, n0, d1, d0);
 379 +               }
 380 +             else
 381 +               q0 = 0;
 382 +
 383 +             q1 = 0;
 384 +
 385 +             if (rp != 0)
 386 +               {
 387 +                 rr.s.low = n0;
 388 +                 rr.s.high = n1;
 389 +                 *rp = rr.ll;
 390 +               }
 391 +           }
 392 +         else
 393 +           {
 394 +             unsigned long m1, m0;
 395 +             /* Normalize.  */
 396 +
 397 +             b = W_TYPE_SIZE - bm;
 398 +
 399 +             d1 = (d1 << bm) | (d0 >> b);
 400 +             d0 = d0 << bm;
 401 +             n2 = n1 >> b;
 402 +             n1 = (n1 << bm) | (n0 >> b);
 403 +             n0 = n0 << bm;
 404 +
 405 +             udiv_qrnnd (q0, n1, n2, n1, d1);
 406 +             umul_ppmm (m1, m0, q0, d0);
 407 +
 408 +             if (m1 > n1 || (m1 == n1 && m0 > n0))
 409 +               {
 410 +                 q0--;
 411 +                 sub_ddmmss (m1, m0, m1, m0, d1, d0);
 412 +               }
 413 +
 414 +             q1 = 0;
 415 +
 416 +             /* Remainder in (n1n0 - m1m0) >> bm.  */
 417 +             if (rp != 0)
 418 +               {
 419 +                 sub_ddmmss (n1, n0, n1, n0, m1, m0);
 420 +                 rr.s.low = (n1 << b) | (n0 >> bm);
 421 +                 rr.s.high = n1 >> bm;
 422 +                 *rp = rr.ll;
 423 +               }
 424 +           }
 425 +       }
 426 +    }
 427 +
 428 +  ww.s.low = q0;
 429 +  ww.s.high = q1;
 430 +  return ww.ll;
 431 +}
 432 +
 433 +long long
 434 +__divdi3 (long long u, long long v)
 435 +{
 436 +  long c = 0;
 437 +  long long w;
 438 +
 439 +  if (u < 0)
 440 +    {
 441 +      c = ~c;
 442 +      u = -u;
 443 +    }
 444 +  if (v < 0)
 445 +    {
 446 +      c = ~c;
 447 +      v = -v;
 448 +    }
 449 +  w = __udivmoddi4 (u, v, 0);
 450 +  if (c)
 451 +    w = -w;
 452 +  return w;
 453 +}
 454 +
 455 +long long
 456 +__moddi3 (long long u, long long v)
 457 +{
 458 +  long c = 0;
 459 +  long long w;
 460 +
 461 +  if (u < 0)
 462 +    {
 463 +      c = ~c;
 464 +      u = -u;
 465 +    }
 466 +  if (v < 0)
 467 +    v = -v;
 468 +  __udivmoddi4 (u, v, &w);
 469 +  if (c)
 470 +    w = -w;
 471 +  return w;
 472 +}
 473 +
 474 +unsigned long long
 475 +__udivdi3 (unsigned long long u, unsigned long long v)
 476 +{
 477 +  return __udivmoddi4 (u, v, 0);
 478 +}
 479 +
 480 +unsigned long long
 481 +__umoddi3 (unsigned long long u, unsigned long long v)
 482 +{
 483 +  unsigned long long w;
 484 +
 485 +  __udivmoddi4 (u, v, &w);
 486 +  return w;
 487 +}
 488 +
 489 +long long
 490 +__gnu_ldivmod_helper (long long a,
 491 +
 492 +                     long long b,
 493 +                     long long *remainder)
 494 +{
 495 +  long long quotient;
 496 +
 497 +  quotient = __divdi3 (a, b);
 498 +  *remainder = a - b * quotient;
 499 +
 500 +  return quotient;
 501 +}
 502 +
 503 +unsigned long long
 504 +
 505 +__gnu_uldivmod_helper (unsigned long long a,
 506 +
 507 +                      unsigned long long b,
 508 +                      unsigned long long *remainder)
 509 +{
 510 +  unsigned long long quotient;
 511 +
 512 +  quotient = __udivdi3 (a, b);
 513 +  *remainder = a - b * quotient;
 514 +  return quotient;
 515 +}
 516 --- /dev/null
 517 +++ b/arch/arm/boot/compressed/longlong.h
 518 @@ -0,0 +1,151 @@
 519 +/* longlong.h -- based on code from gcc-2.95.3
 520 +
 521 +   definitions for mixed size 32/64 bit arithmetic.
 522 +   Copyright (C) 1991, 92, 94, 95, 96, 1997, 1998 Free Software Foundation, Inc.
 523 +
 524 +   This definition file is free software; you can redistribute it
 525 +   and/or modify it under the terms of the GNU General Public
 526 +   License as published by the Free Software Foundation; either
 527 +   version 2, or (at your option) any later version.
 528 +
 529 +   This definition file is distributed in the hope that it will be
 530 +   useful, but WITHOUT ANY WARRANTY; without even the implied
 531 +   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 532 +   See the GNU General Public License for more details.
 533 +
 534 +   You should have received a copy of the GNU General Public License
 535 +   along with this program; if not, write to the Free Software
 536 +   Foundation, Inc., 59 Temple Place - Suite 330,
 537 +   Boston, MA 02111-1307, USA.  */
 538 +
 539 +/* Borrowed from GCC 2.95.3, I Molton 29/07/01 */
 540 +
 541 +#define USItype unsigned long
 542 +#define SI_TYPE_SIZE sizeof(USItype)
 543 +
 544 +#define __BITS4 (SI_TYPE_SIZE / 4)
 545 +#define __ll_B (1L << (SI_TYPE_SIZE / 2))
 546 +#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
 547 +#define __ll_highpart(t) ((USItype) (t) / __ll_B)
 548 +
 549 +/* Define auxiliary asm macros.
 550 +
 551 +   1) umul_ppmm(high_prod, low_prod, multipler, multiplicand)
 552 +   multiplies two USItype integers MULTIPLER and MULTIPLICAND,
 553 +   and generates a two-part USItype product in HIGH_PROD and
 554 +   LOW_PROD.
 555 +
 556 +   2) __umulsidi3(a,b) multiplies two USItype integers A and B,
 557 +   and returns a UDItype product.  This is just a variant of umul_ppmm.
 558 +
 559 +   3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
 560 +   denominator) divides a two-word unsigned integer, composed by the
 561 +   integers HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and
 562 +   places the quotient in QUOTIENT and the remainder in REMAINDER.
 563 +   HIGH_NUMERATOR must be less than DENOMINATOR for correct operation.
 564 +   If, in addition, the most significant bit of DENOMINATOR must be 1,
 565 +   then the pre-processor symbol UDIV_NEEDS_NORMALIZATION is defined to 1.
 566 +
 567 +   4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
 568 +   denominator).  Like udiv_qrnnd but the numbers are signed.  The
 569 +   quotient is rounded towards 0.
 570 +
 571 +   5) count_leading_zeros(count, x) counts the number of zero-bits from
 572 +   the msb to the first non-zero bit.  This is the number of steps X
 573 +   needs to be shifted left to set the msb.  Undefined for X == 0.
 574 +
 575 +   6) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
 576 +   high_addend_2, low_addend_2) adds two two-word unsigned integers,
 577 +   composed by HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and
 578 +   LOW_ADDEND_2 respectively.  The result is placed in HIGH_SUM and
 579 +   LOW_SUM.  Overflow (i.e. carry out) is not stored anywhere, and is
 580 +   lost.
 581 +
 582 +   7) sub_ddmmss(high_difference, low_difference, high_minuend,
 583 +   low_minuend, high_subtrahend, low_subtrahend) subtracts two
 584 +   two-word unsigned integers, composed by HIGH_MINUEND_1 and
 585 +   LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and LOW_SUBTRAHEND_2
 586 +   respectively.  The result is placed in HIGH_DIFFERENCE and
 587 +   LOW_DIFFERENCE.  Overflow (i.e. carry out) is not stored anywhere,
 588 +   and is lost.
 589 +
 590 +   If any of these macros are left undefined for a particular CPU,
 591 +   C macros are used.  */
 592 +
 593 +#if defined (__arm__)
 594 +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
 595 +  __asm__ ("adds       %1, %4, %5                                      \n\
 596 +       adc     %0, %2, %3"                                             \
 597 +          : "=r" ((USItype) (sh)),                                     \
 598 +            "=&r" ((USItype) (sl))                                     \
 599 +          : "%r" ((USItype) (ah)),                                     \
 600 +            "rI" ((USItype) (bh)),                                     \
 601 +            "%r" ((USItype) (al)),                                     \
 602 +            "rI" ((USItype) (bl)))
 603 +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
 604 +  __asm__ ("subs       %1, %4, %5                                      \n\
 605 +       sbc     %0, %2, %3"                                             \
 606 +          : "=r" ((USItype) (sh)),                                     \
 607 +            "=&r" ((USItype) (sl))                                     \
 608 +          : "r" ((USItype) (ah)),                                      \
 609 +            "rI" ((USItype) (bh)),                                     \
 610 +            "r" ((USItype) (al)),                                      \
 611 +            "rI" ((USItype) (bl)))
 612 +#define umul_ppmm(xh, xl, a, b)                                         \
 613 +  __asm__ ("%@ Inlined umul_ppmm\n"                                     \
 614 +           "umull %r1, %r0, %r2, %r3"                                   \
 615 +                   : "=&r" ((USItype)(xh)),                             \
 616 +                     "=r" ((USItype)(xl))                               \
 617 +                   : "r" ((USItype)(a)),                                \
 618 +                     "r" ((USItype)(b))                                 \
 619 +                   : "r0", "r1")
 620 +#define count_leading_zeros(count, x)                                   \
 621 +  __asm__ ("clz %0, %1" : "=r"(count) : "r"(x))
 622 +#define UMUL_TIME 20
 623 +#define UDIV_TIME 100
 624 +#endif /* __arm__ */
 625 +
 626 +#define __umulsidi3(u, v) \
 627 +  ({DIunion __w;                                                       \
 628 +    umul_ppmm (__w.s.high, __w.s.low, u, v);                           \
 629 +    __w.ll; })
 630 +
 631 +#define __udiv_qrnnd_c(q, r, n1, n0, d) \
 632 +  do {                                                                 \
 633 +    USItype __d1, __d0, __q1, __q0;                                    \
 634 +    USItype __r1, __r0, __m;                                           \
 635 +    __d1 = __ll_highpart (d);                                          \
 636 +    __d0 = __ll_lowpart (d);                                           \
 637 +                                                                       \
 638 +    __r1 = (n1) % __d1;                                                        \
 639 +    __q1 = (n1) / __d1;                                                        \
 640 +    __m = (USItype) __q1 * __d0;                                       \
 641 +    __r1 = __r1 * __ll_B | __ll_highpart (n0);                         \
 642 +    if (__r1 < __m)                                                    \
 643 +      {                                                                        \
 644 +       __q1--, __r1 += (d);                                            \
 645 +       if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
 646 +         if (__r1 < __m)                                               \
 647 +           __q1--, __r1 += (d);                                        \
 648 +      }                                                                        \
 649 +    __r1 -= __m;                                                       \
 650 +                                                                       \
 651 +    __r0 = __r1 % __d1;                                                        \
 652 +    __q0 = __r1 / __d1;                                                        \
 653 +    __m = (USItype) __q0 * __d0;                                       \
 654 +    __r0 = __r0 * __ll_B | __ll_lowpart (n0);                          \
 655 +    if (__r0 < __m)                                                    \
 656 +      {                                                                        \
 657 +       __q0--, __r0 += (d);                                            \
 658 +       if (__r0 >= (d))                                                \
 659 +         if (__r0 < __m)                                               \
 660 +           __q0--, __r0 += (d);                                        \
 661 +      }                                                                        \
 662 +    __r0 -= __m;                                                       \
 663 +                                                                       \
 664 +    (q) = (USItype) __q1 * __ll_B | __q0;                              \
 665 +    (r) = __r0;                                                                \
 666 +  } while (0)
 667 +
 668 +#define UDIV_NEEDS_NORMALIZATION 1
 669 +#define udiv_qrnnd __udiv_qrnnd_c
 670 --- /dev/null
 671 +++ b/arch/arm/configs/bcmrpi_cutdown_defconfig
 672 @@ -0,0 +1,1558 @@
 673 +#
 674 +# Automatically generated file; DO NOT EDIT.
 675 +# Linux/arm 3.1.9 Kernel Configuration
 676 +#
 677 +CONFIG_ARM=y
 678 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 679 +CONFIG_GENERIC_GPIO=y
 680 +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
 681 +CONFIG_GENERIC_CLOCKEVENTS=y
 682 +CONFIG_KTIME_SCALAR=y
 683 +CONFIG_HAVE_PROC_CPU=y
 684 +CONFIG_STACKTRACE_SUPPORT=y
 685 +CONFIG_HAVE_LATENCYTOP_SUPPORT=y
 686 +CONFIG_LOCKDEP_SUPPORT=y
 687 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 688 +CONFIG_HARDIRQS_SW_RESEND=y
 689 +CONFIG_GENERIC_IRQ_PROBE=y
 690 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
 691 +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
 692 +CONFIG_GENERIC_HWEIGHT=y
 693 +CONFIG_GENERIC_CALIBRATE_DELAY=y
 694 +CONFIG_NEED_DMA_MAP_STATE=y
 695 +CONFIG_VECTORS_BASE=0xffff0000
 696 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set
 697 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 698 +CONFIG_HAVE_IRQ_WORK=y
 699 +
 700 +#
 701 +# General setup
 702 +#
 703 +CONFIG_EXPERIMENTAL=y
 704 +CONFIG_BROKEN_ON_SMP=y
 705 +CONFIG_INIT_ENV_ARG_LIMIT=32
 706 +CONFIG_CROSS_COMPILE=""
 707 +CONFIG_LOCALVERSION=""
 708 +# CONFIG_LOCALVERSION_AUTO is not set
 709 +CONFIG_HAVE_KERNEL_GZIP=y
 710 +CONFIG_HAVE_KERNEL_LZMA=y
 711 +CONFIG_HAVE_KERNEL_LZO=y
 712 +CONFIG_KERNEL_GZIP=y
 713 +# CONFIG_KERNEL_LZMA is not set
 714 +# CONFIG_KERNEL_LZO is not set
 715 +CONFIG_DEFAULT_HOSTNAME="(none)"
 716 +CONFIG_SWAP=y
 717 +CONFIG_SYSVIPC=y
 718 +CONFIG_SYSVIPC_SYSCTL=y
 719 +CONFIG_POSIX_MQUEUE=y
 720 +CONFIG_POSIX_MQUEUE_SYSCTL=y
 721 +# CONFIG_BSD_PROCESS_ACCT is not set
 722 +# CONFIG_FHANDLE is not set
 723 +# CONFIG_TASKSTATS is not set
 724 +# CONFIG_AUDIT is not set
 725 +CONFIG_HAVE_GENERIC_HARDIRQS=y
 726 +
 727 +#
 728 +# IRQ subsystem
 729 +#
 730 +CONFIG_GENERIC_HARDIRQS=y
 731 +CONFIG_HAVE_SPARSE_IRQ=y
 732 +CONFIG_GENERIC_IRQ_SHOW=y
 733 +# CONFIG_SPARSE_IRQ is not set
 734 +
 735 +#
 736 +# RCU Subsystem
 737 +#
 738 +CONFIG_TINY_RCU=y
 739 +# CONFIG_PREEMPT_RCU is not set
 740 +# CONFIG_RCU_TRACE is not set
 741 +# CONFIG_TREE_RCU_TRACE is not set
 742 +CONFIG_IKCONFIG=y
 743 +CONFIG_IKCONFIG_PROC=y
 744 +CONFIG_LOG_BUF_SHIFT=17
 745 +# CONFIG_CGROUPS is not set
 746 +# CONFIG_NAMESPACES is not set
 747 +# CONFIG_SCHED_AUTOGROUP is not set
 748 +# CONFIG_SYSFS_DEPRECATED is not set
 749 +# CONFIG_RELAY is not set
 750 +# CONFIG_BLK_DEV_INITRD is not set
 751 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 752 +CONFIG_SYSCTL=y
 753 +CONFIG_ANON_INODES=y
 754 +CONFIG_EXPERT=y
 755 +# CONFIG_UID16 is not set
 756 +CONFIG_SYSCTL_SYSCALL=y
 757 +# CONFIG_KALLSYMS is not set
 758 +CONFIG_HOTPLUG=y
 759 +CONFIG_PRINTK=y
 760 +CONFIG_BUG=y
 761 +# CONFIG_ELF_CORE is not set
 762 +CONFIG_BASE_FULL=y
 763 +CONFIG_FUTEX=y
 764 +CONFIG_EPOLL=y
 765 +CONFIG_SIGNALFD=y
 766 +CONFIG_TIMERFD=y
 767 +CONFIG_EVENTFD=y
 768 +CONFIG_SHMEM=y
 769 +CONFIG_AIO=y
 770 +CONFIG_EMBEDDED=y
 771 +CONFIG_HAVE_PERF_EVENTS=y
 772 +CONFIG_PERF_USE_VMALLOC=y
 773 +
 774 +#
 775 +# Kernel Performance Events And Counters
 776 +#
 777 +# CONFIG_PERF_EVENTS is not set
 778 +# CONFIG_PERF_COUNTERS is not set
 779 +# CONFIG_VM_EVENT_COUNTERS is not set
 780 +# CONFIG_COMPAT_BRK is not set
 781 +CONFIG_SLAB=y
 782 +# CONFIG_SLUB is not set
 783 +# CONFIG_SLOB is not set
 784 +# CONFIG_PROFILING is not set
 785 +CONFIG_HAVE_OPROFILE=y
 786 +# CONFIG_KPROBES is not set
 787 +CONFIG_HAVE_KPROBES=y
 788 +CONFIG_HAVE_KRETPROBES=y
 789 +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
 790 +CONFIG_HAVE_CLK=y
 791 +CONFIG_HAVE_DMA_API_DEBUG=y
 792 +
 793 +#
 794 +# GCOV-based kernel profiling
 795 +#
 796 +CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 797 +CONFIG_SLABINFO=y
 798 +CONFIG_RT_MUTEXES=y
 799 +CONFIG_BASE_SMALL=0
 800 +CONFIG_MODULES=y
 801 +# CONFIG_MODULE_FORCE_LOAD is not set
 802 +CONFIG_MODULE_UNLOAD=y
 803 +# CONFIG_MODULE_FORCE_UNLOAD is not set
 804 +CONFIG_MODVERSIONS=y
 805 +CONFIG_MODULE_SRCVERSION_ALL=y
 806 +CONFIG_BLOCK=y
 807 +CONFIG_LBDAF=y
 808 +# CONFIG_BLK_DEV_BSG is not set
 809 +# CONFIG_BLK_DEV_BSGLIB is not set
 810 +# CONFIG_BLK_DEV_INTEGRITY is not set
 811 +
 812 +#
 813 +# IO Schedulers
 814 +#
 815 +CONFIG_IOSCHED_NOOP=y
 816 +CONFIG_IOSCHED_DEADLINE=y
 817 +CONFIG_IOSCHED_CFQ=y
 818 +# CONFIG_DEFAULT_DEADLINE is not set
 819 +CONFIG_DEFAULT_CFQ=y
 820 +# CONFIG_DEFAULT_NOOP is not set
 821 +CONFIG_DEFAULT_IOSCHED="cfq"
 822 +# CONFIG_INLINE_SPIN_TRYLOCK is not set
 823 +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
 824 +# CONFIG_INLINE_SPIN_LOCK is not set
 825 +# CONFIG_INLINE_SPIN_LOCK_BH is not set
 826 +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
 827 +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
 828 +CONFIG_INLINE_SPIN_UNLOCK=y
 829 +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
 830 +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
 831 +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
 832 +# CONFIG_INLINE_READ_TRYLOCK is not set
 833 +# CONFIG_INLINE_READ_LOCK is not set
 834 +# CONFIG_INLINE_READ_LOCK_BH is not set
 835 +# CONFIG_INLINE_READ_LOCK_IRQ is not set
 836 +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
 837 +CONFIG_INLINE_READ_UNLOCK=y
 838 +# CONFIG_INLINE_READ_UNLOCK_BH is not set
 839 +CONFIG_INLINE_READ_UNLOCK_IRQ=y
 840 +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
 841 +# CONFIG_INLINE_WRITE_TRYLOCK is not set
 842 +# CONFIG_INLINE_WRITE_LOCK is not set
 843 +# CONFIG_INLINE_WRITE_LOCK_BH is not set
 844 +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
 845 +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
 846 +CONFIG_INLINE_WRITE_UNLOCK=y
 847 +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
 848 +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
 849 +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
 850 +# CONFIG_MUTEX_SPIN_ON_OWNER is not set
 851 +CONFIG_FREEZER=y
 852 +
 853 +#
 854 +# System Type
 855 +#
 856 +CONFIG_MMU=y
 857 +# CONFIG_ARCH_INTEGRATOR is not set
 858 +# CONFIG_ARCH_REALVIEW is not set
 859 +# CONFIG_ARCH_VERSATILE is not set
 860 +# CONFIG_ARCH_VEXPRESS is not set
 861 +# CONFIG_ARCH_AT91 is not set
 862 +# CONFIG_ARCH_BCMRING is not set
 863 +# CONFIG_ARCH_CLPS711X is not set
 864 +# CONFIG_ARCH_CNS3XXX is not set
 865 +# CONFIG_ARCH_GEMINI is not set
 866 +# CONFIG_ARCH_PRIMA2 is not set
 867 +# CONFIG_ARCH_EBSA110 is not set
 868 +# CONFIG_ARCH_EP93XX is not set
 869 +# CONFIG_ARCH_FOOTBRIDGE is not set
 870 +# CONFIG_ARCH_MXC is not set
 871 +# CONFIG_ARCH_MXS is not set
 872 +# CONFIG_ARCH_NETX is not set
 873 +# CONFIG_ARCH_H720X is not set
 874 +# CONFIG_ARCH_IOP13XX is not set
 875 +# CONFIG_ARCH_IOP32X is not set
 876 +# CONFIG_ARCH_IOP33X is not set
 877 +# CONFIG_ARCH_IXP23XX is not set
 878 +# CONFIG_ARCH_IXP2000 is not set
 879 +# CONFIG_ARCH_IXP4XX is not set
 880 +# CONFIG_ARCH_DOVE is not set
 881 +# CONFIG_ARCH_KIRKWOOD is not set
 882 +# CONFIG_ARCH_LPC32XX is not set
 883 +# CONFIG_ARCH_MV78XX0 is not set
 884 +# CONFIG_ARCH_ORION5X is not set
 885 +# CONFIG_ARCH_MMP is not set
 886 +# CONFIG_ARCH_KS8695 is not set
 887 +# CONFIG_ARCH_W90X900 is not set
 888 +# CONFIG_ARCH_NUC93X is not set
 889 +# CONFIG_ARCH_TEGRA is not set
 890 +# CONFIG_ARCH_PNX4008 is not set
 891 +# CONFIG_ARCH_PXA is not set
 892 +# CONFIG_ARCH_MSM is not set
 893 +# CONFIG_ARCH_SHMOBILE is not set
 894 +# CONFIG_ARCH_RPC is not set
 895 +# CONFIG_ARCH_SA1100 is not set
 896 +# CONFIG_ARCH_S3C2410 is not set
 897 +# CONFIG_ARCH_S3C64XX is not set
 898 +# CONFIG_ARCH_S5P64X0 is not set
 899 +# CONFIG_ARCH_S5PC100 is not set
 900 +# CONFIG_ARCH_S5PV210 is not set
 901 +# CONFIG_ARCH_EXYNOS4 is not set
 902 +# CONFIG_ARCH_SHARK is not set
 903 +# CONFIG_ARCH_TCC_926 is not set
 904 +# CONFIG_ARCH_U300 is not set
 905 +# CONFIG_ARCH_U8500 is not set
 906 +# CONFIG_ARCH_NOMADIK is not set
 907 +# CONFIG_ARCH_DAVINCI is not set
 908 +# CONFIG_ARCH_OMAP is not set
 909 +# CONFIG_PLAT_SPEAR is not set
 910 +CONFIG_ARCH_BCM2708=y
 911 +# CONFIG_ARCH_VT8500 is not set
 912 +# CONFIG_ARCH_ZYNQ is not set
 913 +
 914 +#
 915 +# System MMU
 916 +#
 917 +
 918 +#
 919 +# Broadcom BCM2708 Implementations
 920 +#
 921 +CONFIG_MACH_BCM2708=y
 922 +CONFIG_BCM2708_GPIO=y
 923 +CONFIG_BCM2708_VCMEM=y
 924 +
 925 +#
 926 +# Processor Type
 927 +#
 928 +CONFIG_CPU_V6=y
 929 +CONFIG_CPU_32v6=y
 930 +CONFIG_CPU_ABRT_EV6=y
 931 +CONFIG_CPU_PABRT_V6=y
 932 +CONFIG_CPU_CACHE_V6=y
 933 +CONFIG_CPU_CACHE_VIPT=y
 934 +CONFIG_CPU_COPY_V6=y
 935 +CONFIG_CPU_TLB_V6=y
 936 +CONFIG_CPU_HAS_ASID=y
 937 +CONFIG_CPU_CP15=y
 938 +CONFIG_CPU_CP15_MMU=y
 939 +CONFIG_CPU_USE_DOMAINS=y
 940 +
 941 +#
 942 +# Processor Features
 943 +#
 944 +CONFIG_ARM_THUMB=y
 945 +# CONFIG_CPU_ICACHE_DISABLE is not set
 946 +# CONFIG_CPU_DCACHE_DISABLE is not set
 947 +# CONFIG_CPU_BPREDICT_DISABLE is not set
 948 +CONFIG_ARM_L1_CACHE_SHIFT=5
 949 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y
 950 +CONFIG_CPU_HAS_PMU=y
 951 +CONFIG_ARM_ERRATA_411920=y
 952 +# CONFIG_ARM_ERRATA_364296 is not set
 953 +
 954 +#
 955 +# Bus support
 956 +#
 957 +CONFIG_ARM_AMBA=y
 958 +# CONFIG_PCI_SYSCALL is not set
 959 +# CONFIG_ARCH_SUPPORTS_MSI is not set
 960 +# CONFIG_PCCARD is not set
 961 +
 962 +#
 963 +# Kernel Features
 964 +#
 965 +CONFIG_TICK_ONESHOT=y
 966 +CONFIG_NO_HZ=y
 967 +# CONFIG_HIGH_RES_TIMERS is not set
 968 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 969 +CONFIG_VMSPLIT_3G=y
 970 +# CONFIG_VMSPLIT_2G is not set
 971 +# CONFIG_VMSPLIT_1G is not set
 972 +CONFIG_PAGE_OFFSET=0xC0000000
 973 +CONFIG_PREEMPT_NONE=y
 974 +# CONFIG_PREEMPT_VOLUNTARY is not set
 975 +# CONFIG_PREEMPT is not set
 976 +CONFIG_HZ=100
 977 +CONFIG_AEABI=y
 978 +CONFIG_OABI_COMPAT=y
 979 +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 980 +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 981 +CONFIG_HAVE_ARCH_PFN_VALID=y
 982 +# CONFIG_HIGHMEM is not set
 983 +CONFIG_SELECT_MEMORY_MODEL=y
 984 +CONFIG_FLATMEM_MANUAL=y
 985 +CONFIG_FLATMEM=y
 986 +CONFIG_FLAT_NODE_MEM_MAP=y
 987 +CONFIG_HAVE_MEMBLOCK=y
 988 +CONFIG_PAGEFLAGS_EXTENDED=y
 989 +CONFIG_SPLIT_PTLOCK_CPUS=4
 990 +# CONFIG_COMPACTION is not set
 991 +# CONFIG_PHYS_ADDR_T_64BIT is not set
 992 +CONFIG_ZONE_DMA_FLAG=0
 993 +CONFIG_VIRT_TO_BUS=y
 994 +# CONFIG_KSM is not set
 995 +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 996 +CONFIG_NEED_PER_CPU_KM=y
 997 +# CONFIG_CLEANCACHE is not set
 998 +CONFIG_FORCE_MAX_ZONEORDER=11
 999 +CONFIG_ALIGNMENT_TRAP=y
1000 +# CONFIG_UACCESS_WITH_MEMCPY is not set
1001 +# CONFIG_SECCOMP is not set
1002 +# CONFIG_CC_STACKPROTECTOR is not set
1003 +# CONFIG_DEPRECATED_PARAM_STRUCT is not set
1004 +
1005 +#
1006 +# Boot options
1007 +#
1008 +# CONFIG_USE_OF is not set
1009 +CONFIG_ZBOOT_ROM_TEXT=0x0
1010 +CONFIG_ZBOOT_ROM_BSS=0x0
1011 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
1012 +CONFIG_CMDLINE_FROM_BOOTLOADER=y
1013 +# CONFIG_CMDLINE_EXTEND is not set
1014 +# CONFIG_CMDLINE_FORCE is not set
1015 +# CONFIG_XIP_KERNEL is not set
1016 +# CONFIG_KEXEC is not set
1017 +# CONFIG_CRASH_DUMP is not set
1018 +# CONFIG_AUTO_ZRELADDR is not set
1019 +
1020 +#
1021 +# CPU Power Management
1022 +#
1023 +CONFIG_CPU_IDLE=y
1024 +CONFIG_CPU_IDLE_GOV_LADDER=y
1025 +CONFIG_CPU_IDLE_GOV_MENU=y
1026 +
1027 +#
1028 +# Floating point emulation
1029 +#
1030 +
1031 +#
1032 +# At least one emulation must be selected
1033 +#
1034 +# CONFIG_FPE_NWFPE is not set
1035 +# CONFIG_FPE_FASTFPE is not set
1036 +CONFIG_VFP=y
1037 +
1038 +#
1039 +# Userspace binary formats
1040 +#
1041 +CONFIG_BINFMT_ELF=y
1042 +CONFIG_HAVE_AOUT=y
1043 +# CONFIG_BINFMT_AOUT is not set
1044 +# CONFIG_BINFMT_MISC is not set
1045 +
1046 +#
1047 +# Power management options
1048 +#
1049 +CONFIG_SUSPEND=y
1050 +CONFIG_SUSPEND_FREEZER=y
1051 +CONFIG_PM_SLEEP=y
1052 +# CONFIG_PM_RUNTIME is not set
1053 +CONFIG_PM=y
1054 +# CONFIG_PM_DEBUG is not set
1055 +# CONFIG_APM_EMULATION is not set
1056 +CONFIG_PM_CLK=y
1057 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
1058 +CONFIG_NET=y
1059 +
1060 +#
1061 +# Networking options
1062 +#
1063 +CONFIG_PACKET=y
1064 +CONFIG_UNIX=y
1065 +CONFIG_XFRM=y
1066 +CONFIG_XFRM_USER=y
1067 +# CONFIG_XFRM_SUB_POLICY is not set
1068 +# CONFIG_XFRM_MIGRATE is not set
1069 +# CONFIG_XFRM_STATISTICS is not set
1070 +CONFIG_NET_KEY=m
1071 +# CONFIG_NET_KEY_MIGRATE is not set
1072 +CONFIG_INET=y
1073 +CONFIG_IP_MULTICAST=y
1074 +# CONFIG_IP_ADVANCED_ROUTER is not set
1075 +CONFIG_IP_PNP=y
1076 +CONFIG_IP_PNP_DHCP=y
1077 +# CONFIG_IP_PNP_BOOTP is not set
1078 +CONFIG_IP_PNP_RARP=y
1079 +# CONFIG_NET_IPIP is not set
1080 +# CONFIG_NET_IPGRE_DEMUX is not set
1081 +# CONFIG_IP_MROUTE is not set
1082 +# CONFIG_ARPD is not set
1083 +CONFIG_SYN_COOKIES=y
1084 +# CONFIG_INET_AH is not set
1085 +# CONFIG_INET_ESP is not set
1086 +# CONFIG_INET_IPCOMP is not set
1087 +# CONFIG_INET_XFRM_TUNNEL is not set
1088 +# CONFIG_INET_TUNNEL is not set
1089 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
1090 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
1091 +# CONFIG_INET_XFRM_MODE_BEET is not set
1092 +# CONFIG_INET_LRO is not set
1093 +# CONFIG_INET_DIAG is not set
1094 +# CONFIG_TCP_CONG_ADVANCED is not set
1095 +CONFIG_TCP_CONG_CUBIC=y
1096 +CONFIG_DEFAULT_TCP_CONG="cubic"
1097 +# CONFIG_TCP_MD5SIG is not set
1098 +# CONFIG_IPV6 is not set
1099 +# CONFIG_NETWORK_SECMARK is not set
1100 +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
1101 +# CONFIG_NETFILTER is not set
1102 +# CONFIG_IP_DCCP is not set
1103 +# CONFIG_IP_SCTP is not set
1104 +# CONFIG_RDS is not set
1105 +# CONFIG_TIPC is not set
1106 +# CONFIG_ATM is not set
1107 +# CONFIG_L2TP is not set
1108 +# CONFIG_BRIDGE is not set
1109 +# CONFIG_NET_DSA is not set
1110 +# CONFIG_VLAN_8021Q is not set
1111 +# CONFIG_DECNET is not set
1112 +# CONFIG_LLC2 is not set
1113 +# CONFIG_IPX is not set
1114 +# CONFIG_ATALK is not set
1115 +# CONFIG_X25 is not set
1116 +# CONFIG_LAPB is not set
1117 +# CONFIG_ECONET is not set
1118 +# CONFIG_WAN_ROUTER is not set
1119 +# CONFIG_PHONET is not set
1120 +# CONFIG_IEEE802154 is not set
1121 +# CONFIG_NET_SCHED is not set
1122 +# CONFIG_DCB is not set
1123 +CONFIG_DNS_RESOLVER=y
1124 +# CONFIG_BATMAN_ADV is not set
1125 +
1126 +#
1127 +# Network testing
1128 +#
1129 +CONFIG_NET_PKTGEN=m
1130 +# CONFIG_HAMRADIO is not set
1131 +# CONFIG_CAN is not set
1132 +# CONFIG_IRDA is not set
1133 +# CONFIG_BT is not set
1134 +# CONFIG_AF_RXRPC is not set
1135 +CONFIG_WIRELESS=y
1136 +CONFIG_WEXT_CORE=y
1137 +CONFIG_WEXT_PROC=y
1138 +CONFIG_CFG80211=y
1139 +# CONFIG_NL80211_TESTMODE is not set
1140 +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
1141 +# CONFIG_CFG80211_REG_DEBUG is not set
1142 +CONFIG_CFG80211_DEFAULT_PS=y
1143 +# CONFIG_CFG80211_INTERNAL_REGDB is not set
1144 +CONFIG_CFG80211_WEXT=y
1145 +CONFIG_WIRELESS_EXT_SYSFS=y
1146 +# CONFIG_LIB80211 is not set
1147 +# CONFIG_MAC80211 is not set
1148 +# CONFIG_WIMAX is not set
1149 +# CONFIG_RFKILL is not set
1150 +# CONFIG_NET_9P is not set
1151 +# CONFIG_CAIF is not set
1152 +# CONFIG_CEPH_LIB is not set
1153 +# CONFIG_NFC is not set
1154 +
1155 +#
1156 +# Device Drivers
1157 +#
1158 +
1159 +#
1160 +# Generic Driver Options
1161 +#
1162 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
1163 +# CONFIG_DEVTMPFS is not set
1164 +CONFIG_STANDALONE=y
1165 +CONFIG_PREVENT_FIRMWARE_BUILD=y
1166 +CONFIG_FW_LOADER=y
1167 +CONFIG_FIRMWARE_IN_KERNEL=y
1168 +CONFIG_EXTRA_FIRMWARE=""
1169 +# CONFIG_DEBUG_DRIVER is not set
1170 +# CONFIG_DEBUG_DEVRES is not set
1171 +# CONFIG_SYS_HYPERVISOR is not set
1172 +# CONFIG_CONNECTOR is not set
1173 +# CONFIG_MTD is not set
1174 +# CONFIG_PARPORT is not set
1175 +CONFIG_BLK_DEV=y
1176 +# CONFIG_BLK_DEV_COW_COMMON is not set
1177 +CONFIG_BLK_DEV_LOOP=y
1178 +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
1179 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
1180 +
1181 +#
1182 +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
1183 +#
1184 +# CONFIG_BLK_DEV_NBD is not set
1185 +# CONFIG_BLK_DEV_UB is not set
1186 +CONFIG_BLK_DEV_RAM=y
1187 +CONFIG_BLK_DEV_RAM_COUNT=16
1188 +CONFIG_BLK_DEV_RAM_SIZE=4096
1189 +# CONFIG_BLK_DEV_XIP is not set
1190 +# CONFIG_CDROM_PKTCDVD is not set
1191 +# CONFIG_ATA_OVER_ETH is not set
1192 +# CONFIG_MG_DISK is not set
1193 +# CONFIG_BLK_DEV_RBD is not set
1194 +# CONFIG_SENSORS_LIS3LV02D is not set
1195 +CONFIG_MISC_DEVICES=y
1196 +# CONFIG_ENCLOSURE_SERVICES is not set
1197 +# CONFIG_C2PORT is not set
1198 +
1199 +#
1200 +# EEPROM support
1201 +#
1202 +# CONFIG_EEPROM_93CX6 is not set
1203 +# CONFIG_IWMC3200TOP is not set
1204 +
1205 +#
1206 +# Texas Instruments shared transport line discipline
1207 +#
1208 +# CONFIG_TI_ST is not set
1209 +CONFIG_BCM2708_VCHIQ=y
1210 +CONFIG_HAVE_IDE=y
1211 +# CONFIG_IDE is not set
1212 +
1213 +#
1214 +# SCSI device support
1215 +#
1216 +CONFIG_SCSI_MOD=y
1217 +# CONFIG_RAID_ATTRS is not set
1218 +CONFIG_SCSI=y
1219 +CONFIG_SCSI_DMA=y
1220 +# CONFIG_SCSI_TGT is not set
1221 +# CONFIG_SCSI_NETLINK is not set
1222 +# CONFIG_SCSI_PROC_FS is not set
1223 +
1224 +#
1225 +# SCSI support type (disk, tape, CD-ROM)
1226 +#
1227 +CONFIG_BLK_DEV_SD=m
1228 +# CONFIG_CHR_DEV_ST is not set
1229 +# CONFIG_CHR_DEV_OSST is not set
1230 +CONFIG_BLK_DEV_SR=m
1231 +# CONFIG_BLK_DEV_SR_VENDOR is not set
1232 +# CONFIG_CHR_DEV_SG is not set
1233 +# CONFIG_CHR_DEV_SCH is not set
1234 +CONFIG_SCSI_MULTI_LUN=y
1235 +# CONFIG_SCSI_CONSTANTS is not set
1236 +# CONFIG_SCSI_LOGGING is not set
1237 +# CONFIG_SCSI_SCAN_ASYNC is not set
1238 +CONFIG_SCSI_WAIT_SCAN=m
1239 +
1240 +#
1241 +# SCSI Transports
1242 +#
1243 +# CONFIG_SCSI_SPI_ATTRS is not set
1244 +# CONFIG_SCSI_FC_ATTRS is not set
1245 +# CONFIG_SCSI_ISCSI_ATTRS is not set
1246 +# CONFIG_SCSI_SAS_ATTRS is not set
1247 +# CONFIG_SCSI_SAS_LIBSAS is not set
1248 +# CONFIG_SCSI_SRP_ATTRS is not set
1249 +# CONFIG_SCSI_LOWLEVEL is not set
1250 +# CONFIG_SCSI_DH is not set
1251 +# CONFIG_SCSI_OSD_INITIATOR is not set
1252 +# CONFIG_ATA is not set
1253 +# CONFIG_MD is not set
1254 +# CONFIG_TARGET_CORE is not set
1255 +CONFIG_NETDEVICES=y
1256 +# CONFIG_DUMMY is not set
1257 +# CONFIG_BONDING is not set
1258 +# CONFIG_MACVLAN is not set
1259 +# CONFIG_EQUALIZER is not set
1260 +CONFIG_TUN=m
1261 +# CONFIG_VETH is not set
1262 +CONFIG_MII=y
1263 +CONFIG_PHYLIB=m
1264 +
1265 +#
1266 +# MII PHY device drivers
1267 +#
1268 +# CONFIG_MARVELL_PHY is not set
1269 +# CONFIG_DAVICOM_PHY is not set
1270 +# CONFIG_QSEMI_PHY is not set
1271 +# CONFIG_LXT_PHY is not set
1272 +# CONFIG_CICADA_PHY is not set
1273 +# CONFIG_VITESSE_PHY is not set
1274 +# CONFIG_SMSC_PHY is not set
1275 +# CONFIG_BROADCOM_PHY is not set
1276 +# CONFIG_ICPLUS_PHY is not set
1277 +# CONFIG_REALTEK_PHY is not set
1278 +# CONFIG_NATIONAL_PHY is not set
1279 +# CONFIG_STE10XP is not set
1280 +# CONFIG_LSI_ET1011C_PHY is not set
1281 +# CONFIG_MICREL_PHY is not set
1282 +CONFIG_MDIO_BITBANG=m
1283 +# CONFIG_MDIO_GPIO is not set
1284 +CONFIG_NET_ETHERNET=y
1285 +CONFIG_AX88796=m
1286 +# CONFIG_AX88796_93CX6 is not set
1287 +# CONFIG_SMC91X is not set
1288 +# CONFIG_DM9000 is not set
1289 +# CONFIG_ETHOC is not set
1290 +# CONFIG_SMC911X is not set
1291 +# CONFIG_SMSC911X is not set
1292 +# CONFIG_DNET is not set
1293 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
1294 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
1295 +# CONFIG_IBM_NEW_EMAC_TAH is not set
1296 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
1297 +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
1298 +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
1299 +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
1300 +# CONFIG_B44 is not set
1301 +# CONFIG_KS8851_MLL is not set
1302 +# CONFIG_FTMAC100 is not set
1303 +# CONFIG_NETDEV_1000 is not set
1304 +# CONFIG_NETDEV_10000 is not set
1305 +# CONFIG_WLAN is not set
1306 +
1307 +#
1308 +# Enable WiMAX (Networking options) to see the WiMAX drivers
1309 +#
1310 +
1311 +#
1312 +# USB Network Adapters
1313 +#
1314 +# CONFIG_USB_CATC is not set
1315 +# CONFIG_USB_KAWETH is not set
1316 +# CONFIG_USB_PEGASUS is not set
1317 +# CONFIG_USB_RTL8150 is not set
1318 +CONFIG_USB_USBNET=y
1319 +CONFIG_USB_NET_AX8817X=m
1320 +# CONFIG_USB_NET_CDCETHER is not set
1321 +# CONFIG_USB_NET_CDC_EEM is not set
1322 +CONFIG_USB_NET_CDC_NCM=y
1323 +# CONFIG_USB_NET_DM9601 is not set
1324 +# CONFIG_USB_NET_SMSC75XX is not set
1325 +CONFIG_USB_NET_SMSC95XX=y
1326 +# CONFIG_USB_NET_GL620A is not set
1327 +# CONFIG_USB_NET_NET1080 is not set
1328 +# CONFIG_USB_NET_PLUSB is not set
1329 +# CONFIG_USB_NET_MCS7830 is not set
1330 +# CONFIG_USB_NET_RNDIS_HOST is not set
1331 +# CONFIG_USB_NET_CDC_SUBSET is not set
1332 +# CONFIG_USB_NET_ZAURUS is not set
1333 +# CONFIG_USB_NET_CX82310_ETH is not set
1334 +# CONFIG_USB_NET_KALMIA is not set
1335 +# CONFIG_USB_NET_INT51X1 is not set
1336 +# CONFIG_USB_IPHETH is not set
1337 +# CONFIG_USB_SIERRA_NET is not set
1338 +# CONFIG_WAN is not set
1339 +
1340 +#
1341 +# CAIF transport drivers
1342 +#
1343 +# CONFIG_PPP is not set
1344 +# CONFIG_SLIP is not set
1345 +# CONFIG_NETCONSOLE is not set
1346 +# CONFIG_NETPOLL is not set
1347 +# CONFIG_NET_POLL_CONTROLLER is not set
1348 +# CONFIG_ISDN is not set
1349 +# CONFIG_PHONE is not set
1350 +
1351 +#
1352 +# Input device support
1353 +#
1354 +CONFIG_INPUT=y
1355 +# CONFIG_INPUT_FF_MEMLESS is not set
1356 +# CONFIG_INPUT_POLLDEV is not set
1357 +# CONFIG_INPUT_SPARSEKMAP is not set
1358 +
1359 +#
1360 +# Userland interfaces
1361 +#
1362 +CONFIG_INPUT_MOUSEDEV=y
1363 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1364 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
1365 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
1366 +# CONFIG_INPUT_JOYDEV is not set
1367 +CONFIG_INPUT_EVDEV=m
1368 +# CONFIG_INPUT_EVBUG is not set
1369 +
1370 +#
1371 +# Input Device Drivers
1372 +#
1373 +# CONFIG_INPUT_KEYBOARD is not set
1374 +# CONFIG_INPUT_MOUSE is not set
1375 +# CONFIG_INPUT_JOYSTICK is not set
1376 +# CONFIG_INPUT_TABLET is not set
1377 +# CONFIG_INPUT_TOUCHSCREEN is not set
1378 +CONFIG_INPUT_MISC=y
1379 +# CONFIG_INPUT_AD714X is not set
1380 +# CONFIG_INPUT_ATI_REMOTE is not set
1381 +# CONFIG_INPUT_ATI_REMOTE2 is not set
1382 +# CONFIG_INPUT_KEYSPAN_REMOTE is not set
1383 +# CONFIG_INPUT_POWERMATE is not set
1384 +# CONFIG_INPUT_YEALINK is not set
1385 +# CONFIG_INPUT_CM109 is not set
1386 +CONFIG_INPUT_UINPUT=m
1387 +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
1388 +# CONFIG_INPUT_ADXL34X is not set
1389 +# CONFIG_INPUT_CMA3000 is not set
1390 +
1391 +#
1392 +# Hardware I/O ports
1393 +#
1394 +CONFIG_SERIO=m
1395 +CONFIG_SERIO_SERPORT=m
1396 +# CONFIG_SERIO_AMBAKMI is not set
1397 +# CONFIG_SERIO_LIBPS2 is not set
1398 +CONFIG_SERIO_RAW=m
1399 +# CONFIG_SERIO_ALTERA_PS2 is not set
1400 +# CONFIG_SERIO_PS2MULT is not set
1401 +CONFIG_GAMEPORT=m
1402 +CONFIG_GAMEPORT_NS558=m
1403 +CONFIG_GAMEPORT_L4=m
1404 +
1405 +#
1406 +# Character devices
1407 +#
1408 +CONFIG_VT=y
1409 +CONFIG_CONSOLE_TRANSLATIONS=y
1410 +CONFIG_VT_CONSOLE=y
1411 +CONFIG_HW_CONSOLE=y
1412 +CONFIG_VT_HW_CONSOLE_BINDING=y
1413 +CONFIG_UNIX98_PTYS=y
1414 +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
1415 +# CONFIG_LEGACY_PTYS is not set
1416 +# CONFIG_SERIAL_NONSTANDARD is not set
1417 +# CONFIG_N_GSM is not set
1418 +# CONFIG_TRACE_SINK is not set
1419 +# CONFIG_DEVKMEM is not set
1420 +
1421 +#
1422 +# Serial drivers
1423 +#
1424 +# CONFIG_SERIAL_8250 is not set
1425 +
1426 +#
1427 +# Non-8250 serial port support
1428 +#
1429 +# CONFIG_SERIAL_AMBA_PL010 is not set
1430 +CONFIG_SERIAL_AMBA_PL011=y
1431 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1432 +CONFIG_SERIAL_CORE=y
1433 +CONFIG_SERIAL_CORE_CONSOLE=y
1434 +# CONFIG_SERIAL_TIMBERDALE is not set
1435 +# CONFIG_SERIAL_ALTERA_JTAGUART is not set
1436 +# CONFIG_SERIAL_ALTERA_UART is not set
1437 +# CONFIG_SERIAL_XILINX_PS_UART is not set
1438 +# CONFIG_TTY_PRINTK is not set
1439 +# CONFIG_HVC_DCC is not set
1440 +# CONFIG_IPMI_HANDLER is not set
1441 +# CONFIG_HW_RANDOM is not set
1442 +# CONFIG_R3964 is not set
1443 +CONFIG_RAW_DRIVER=y
1444 +CONFIG_MAX_RAW_DEVS=256
1445 +# CONFIG_TCG_TPM is not set
1446 +# CONFIG_RAMOOPS is not set
1447 +# CONFIG_I2C is not set
1448 +# CONFIG_SPI is not set
1449 +
1450 +#
1451 +# PPS support
1452 +#
1453 +# CONFIG_PPS is not set
1454 +
1455 +#
1456 +# PPS generators support
1457 +#
1458 +
1459 +#
1460 +# PTP clock support
1461 +#
1462 +
1463 +#
1464 +# Enable Device Drivers -> PPS to see the PTP clock options.
1465 +#
1466 +CONFIG_ARCH_REQUIRE_GPIOLIB=y
1467 +CONFIG_GPIOLIB=y
1468 +# CONFIG_DEBUG_GPIO is not set
1469 +CONFIG_GPIO_SYSFS=y
1470 +
1471 +#
1472 +# Memory mapped GPIO drivers:
1473 +#
1474 +# CONFIG_GPIO_GENERIC_PLATFORM is not set
1475 +# CONFIG_GPIO_IT8761E is not set
1476 +# CONFIG_GPIO_PL061 is not set
1477 +
1478 +#
1479 +# I2C GPIO expanders:
1480 +#
1481 +
1482 +#
1483 +# PCI GPIO expanders:
1484 +#
1485 +
1486 +#
1487 +# SPI GPIO expanders:
1488 +#
1489 +
1490 +#
1491 +# AC97 GPIO expanders:
1492 +#
1493 +
1494 +#
1495 +# MODULbus GPIO expanders:
1496 +#
1497 +# CONFIG_W1 is not set
1498 +# CONFIG_POWER_SUPPLY is not set
1499 +# CONFIG_HWMON is not set
1500 +# CONFIG_THERMAL is not set
1501 +# CONFIG_WATCHDOG is not set
1502 +CONFIG_SSB_POSSIBLE=y
1503 +
1504 +#
1505 +# Sonics Silicon Backplane
1506 +#
1507 +# CONFIG_SSB is not set
1508 +CONFIG_BCMA_POSSIBLE=y
1509 +
1510 +#
1511 +# Broadcom specific AMBA
1512 +#
1513 +# CONFIG_BCMA is not set
1514 +# CONFIG_MFD_SUPPORT is not set
1515 +# CONFIG_REGULATOR is not set
1516 +# CONFIG_MEDIA_SUPPORT is not set
1517 +
1518 +#
1519 +# Graphics support
1520 +#
1521 +# CONFIG_DRM is not set
1522 +# CONFIG_VGASTATE is not set
1523 +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
1524 +CONFIG_FB=y
1525 +# CONFIG_FIRMWARE_EDID is not set
1526 +# CONFIG_FB_DDC is not set
1527 +# CONFIG_FB_BOOT_VESA_SUPPORT is not set
1528 +CONFIG_FB_CFB_FILLRECT=y
1529 +CONFIG_FB_CFB_COPYAREA=y
1530 +CONFIG_FB_CFB_IMAGEBLIT=y
1531 +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
1532 +# CONFIG_FB_SYS_FILLRECT is not set
1533 +# CONFIG_FB_SYS_COPYAREA is not set
1534 +# CONFIG_FB_SYS_IMAGEBLIT is not set
1535 +# CONFIG_FB_FOREIGN_ENDIAN is not set
1536 +# CONFIG_FB_SYS_FOPS is not set
1537 +# CONFIG_FB_WMT_GE_ROPS is not set
1538 +# CONFIG_FB_SVGALIB is not set
1539 +# CONFIG_FB_MACMODES is not set
1540 +# CONFIG_FB_BACKLIGHT is not set
1541 +# CONFIG_FB_MODE_HELPERS is not set
1542 +# CONFIG_FB_TILEBLITTING is not set
1543 +
1544 +#
1545 +# Frame buffer hardware drivers
1546 +#
1547 +CONFIG_FB_BCM2708=y
1548 +# CONFIG_FB_ARMCLCD is not set
1549 +# CONFIG_FB_S1D13XXX is not set
1550 +# CONFIG_FB_UDL is not set
1551 +# CONFIG_FB_VIRTUAL is not set
1552 +# CONFIG_FB_METRONOME is not set
1553 +# CONFIG_FB_BROADSHEET is not set
1554 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1555 +
1556 +#
1557 +# Display device support
1558 +#
1559 +# CONFIG_DISPLAY_SUPPORT is not set
1560 +
1561 +#
1562 +# Console display driver support
1563 +#
1564 +CONFIG_DUMMY_CONSOLE=y
1565 +CONFIG_FRAMEBUFFER_CONSOLE=y
1566 +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
1567 +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
1568 +# CONFIG_FONTS is not set
1569 +CONFIG_FONT_8x8=y
1570 +CONFIG_FONT_8x16=y
1571 +CONFIG_LOGO=y
1572 +# CONFIG_LOGO_LINUX_MONO is not set
1573 +# CONFIG_LOGO_LINUX_VGA16 is not set
1574 +CONFIG_LOGO_LINUX_CLUT224=y
1575 +# CONFIG_SOUND is not set
1576 +CONFIG_HID_SUPPORT=y
1577 +CONFIG_HID=y
1578 +# CONFIG_HIDRAW is not set
1579 +
1580 +#
1581 +# USB Input Devices
1582 +#
1583 +CONFIG_USB_HID=y
1584 +CONFIG_HID_PID=y
1585 +CONFIG_USB_HIDDEV=y
1586 +
1587 +#
1588 +# Special HID drivers
1589 +#
1590 +CONFIG_HID_A4TECH=m
1591 +# CONFIG_HID_ACRUX is not set
1592 +CONFIG_HID_APPLE=m
1593 +CONFIG_HID_BELKIN=m
1594 +CONFIG_HID_CHERRY=m
1595 +CONFIG_HID_CHICONY=m
1596 +CONFIG_HID_CYPRESS=m
1597 +CONFIG_HID_DRAGONRISE=m
1598 +# CONFIG_DRAGONRISE_FF is not set
1599 +# CONFIG_HID_EMS_FF is not set
1600 +CONFIG_HID_EZKEY=m
1601 +# CONFIG_HID_HOLTEK is not set
1602 +# CONFIG_HID_KEYTOUCH is not set
1603 +CONFIG_HID_KYE=m
1604 +# CONFIG_HID_UCLOGIC is not set
1605 +# CONFIG_HID_WALTOP is not set
1606 +CONFIG_HID_GYRATION=m
1607 +CONFIG_HID_TWINHAN=m
1608 +CONFIG_HID_KENSINGTON=m
1609 +# CONFIG_HID_LCPOWER is not set
1610 +CONFIG_HID_LOGITECH=m
1611 +# CONFIG_LOGITECH_FF is not set
1612 +# CONFIG_LOGIRUMBLEPAD2_FF is not set
1613 +# CONFIG_LOGIG940_FF is not set
1614 +# CONFIG_LOGIWII_FF is not set
1615 +CONFIG_HID_MICROSOFT=m
1616 +CONFIG_HID_MONTEREY=m
1617 +# CONFIG_HID_MULTITOUCH is not set
1618 +# CONFIG_HID_NTRIG is not set
1619 +CONFIG_HID_ORTEK=m
1620 +CONFIG_HID_PANTHERLORD=m
1621 +# CONFIG_PANTHERLORD_FF is not set
1622 +CONFIG_HID_PETALYNX=m
1623 +# CONFIG_HID_PICOLCD is not set
1624 +# CONFIG_HID_QUANTA is not set
1625 +# CONFIG_HID_ROCCAT is not set
1626 +CONFIG_HID_SAMSUNG=m
1627 +CONFIG_HID_SONY=m
1628 +# CONFIG_HID_SPEEDLINK is not set
1629 +CONFIG_HID_SUNPLUS=m
1630 +CONFIG_HID_GREENASIA=m
1631 +# CONFIG_GREENASIA_FF is not set
1632 +CONFIG_HID_SMARTJOYPLUS=m
1633 +# CONFIG_SMARTJOYPLUS_FF is not set
1634 +CONFIG_HID_TOPSEED=m
1635 +CONFIG_HID_THRUSTMASTER=m
1636 +# CONFIG_THRUSTMASTER_FF is not set
1637 +CONFIG_HID_ZEROPLUS=m
1638 +# CONFIG_ZEROPLUS_FF is not set
1639 +# CONFIG_HID_ZYDACRON is not set
1640 +CONFIG_USB_SUPPORT=y
1641 +CONFIG_USB_ARCH_HAS_HCD=y
1642 +# CONFIG_USB_ARCH_HAS_OHCI is not set
1643 +# CONFIG_USB_ARCH_HAS_EHCI is not set
1644 +CONFIG_USB=y
1645 +# CONFIG_USB_DEBUG is not set
1646 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1647 +
1648 +#
1649 +# Miscellaneous USB options
1650 +#
1651 +# CONFIG_USB_DEVICEFS is not set
1652 +CONFIG_USB_DEVICE_CLASS=y
1653 +# CONFIG_USB_DYNAMIC_MINORS is not set
1654 +# CONFIG_USB_OTG_WHITELIST is not set
1655 +# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1656 +CONFIG_USB_MON=m
1657 +# CONFIG_USB_WUSB is not set
1658 +# CONFIG_USB_WUSB_CBAF is not set
1659 +
1660 +#
1661 +# USB Host Controller Drivers
1662 +#
1663 +# CONFIG_USB_C67X00_HCD is not set
1664 +# CONFIG_USB_OXU210HP_HCD is not set
1665 +# CONFIG_USB_ISP116X_HCD is not set
1666 +# CONFIG_USB_ISP1760_HCD is not set
1667 +# CONFIG_USB_ISP1362_HCD is not set
1668 +# CONFIG_USB_SL811_HCD is not set
1669 +# CONFIG_USB_R8A66597_HCD is not set
1670 +# CONFIG_USB_HWA_HCD is not set
1671 +CONFIG_USB_DWCOTG=y
1672 +
1673 +#
1674 +# USB Device Class drivers
1675 +#
1676 +# CONFIG_USB_ACM is not set
1677 +# CONFIG_USB_PRINTER is not set
1678 +# CONFIG_USB_WDM is not set
1679 +# CONFIG_USB_TMC is not set
1680 +
1681 +#
1682 +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1683 +#
1684 +
1685 +#
1686 +# also be needed; see USB_STORAGE Help for more info
1687 +#
1688 +CONFIG_USB_STORAGE=y
1689 +# CONFIG_USB_STORAGE_DEBUG is not set
1690 +# CONFIG_USB_STORAGE_REALTEK is not set
1691 +# CONFIG_USB_STORAGE_DATAFAB is not set
1692 +# CONFIG_USB_STORAGE_FREECOM is not set
1693 +# CONFIG_USB_STORAGE_ISD200 is not set
1694 +# CONFIG_USB_STORAGE_USBAT is not set
1695 +# CONFIG_USB_STORAGE_SDDR09 is not set
1696 +# CONFIG_USB_STORAGE_SDDR55 is not set
1697 +# CONFIG_USB_STORAGE_JUMPSHOT is not set
1698 +# CONFIG_USB_STORAGE_ALAUDA is not set
1699 +# CONFIG_USB_STORAGE_ONETOUCH is not set
1700 +# CONFIG_USB_STORAGE_KARMA is not set
1701 +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1702 +# CONFIG_USB_STORAGE_ENE_UB6250 is not set
1703 +# CONFIG_USB_UAS is not set
1704 +CONFIG_USB_LIBUSUAL=y
1705 +
1706 +#
1707 +# USB Imaging devices
1708 +#
1709 +# CONFIG_USB_MDC800 is not set
1710 +# CONFIG_USB_MICROTEK is not set
1711 +
1712 +#
1713 +# USB port drivers
1714 +#
1715 +# CONFIG_USB_SERIAL is not set
1716 +
1717 +#
1718 +# USB Miscellaneous drivers
1719 +#
1720 +# CONFIG_USB_EMI62 is not set
1721 +# CONFIG_USB_EMI26 is not set
1722 +# CONFIG_USB_ADUTUX is not set
1723 +# CONFIG_USB_SEVSEG is not set
1724 +# CONFIG_USB_RIO500 is not set
1725 +# CONFIG_USB_LEGOTOWER is not set
1726 +# CONFIG_USB_LCD is not set
1727 +# CONFIG_USB_LED is not set
1728 +# CONFIG_USB_CYPRESS_CY7C63 is not set
1729 +# CONFIG_USB_CYTHERM is not set
1730 +# CONFIG_USB_IDMOUSE is not set
1731 +# CONFIG_USB_FTDI_ELAN is not set
1732 +# CONFIG_USB_APPLEDISPLAY is not set
1733 +# CONFIG_USB_LD is not set
1734 +# CONFIG_USB_TRANCEVIBRATOR is not set
1735 +# CONFIG_USB_IOWARRIOR is not set
1736 +# CONFIG_USB_TEST is not set
1737 +# CONFIG_USB_ISIGHTFW is not set
1738 +# CONFIG_USB_YUREX is not set
1739 +# CONFIG_USB_GADGET is not set
1740 +
1741 +#
1742 +# OTG and related infrastructure
1743 +#
1744 +# CONFIG_USB_GPIO_VBUS is not set
1745 +# CONFIG_USB_ULPI is not set
1746 +# CONFIG_NOP_USB_XCEIV is not set
1747 +CONFIG_MMC=y
1748 +# CONFIG_MMC_DEBUG is not set
1749 +# CONFIG_MMC_UNSAFE_RESUME is not set
1750 +# CONFIG_MMC_CLKGATE is not set
1751 +
1752 +#
1753 +# MMC/SD/SDIO Card Drivers
1754 +#
1755 +CONFIG_MMC_BLOCK=y
1756 +CONFIG_MMC_BLOCK_MINORS=8
1757 +CONFIG_MMC_BLOCK_BOUNCE=y
1758 +# CONFIG_SDIO_UART is not set
1759 +# CONFIG_MMC_TEST is not set
1760 +
1761 +#
1762 +# MMC/SD/SDIO Host Controller Drivers
1763 +#
1764 +# CONFIG_MMC_ARMMMCI is not set
1765 +CONFIG_MMC_SDHCI=y
1766 +CONFIG_MMC_SDHCI_IO_ACCESSORS=y
1767 +CONFIG_MMC_SDHCI_PLTFM=y
1768 +# CONFIG_MMC_SDHCI_PXAV3 is not set
1769 +# CONFIG_MMC_SDHCI_PXAV2 is not set
1770 +CONFIG_MMC_SDHCI_BCM2708=y
1771 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1772 +# CONFIG_MMC_BCM2708 is not set
1773 +# CONFIG_MMC_DW is not set
1774 +# CONFIG_MMC_VUB300 is not set
1775 +# CONFIG_MMC_USHC is not set
1776 +# CONFIG_MEMSTICK is not set
1777 +CONFIG_NEW_LEDS=y
1778 +CONFIG_LEDS_CLASS=y
1779 +
1780 +#
1781 +# LED drivers
1782 +#
1783 +CONFIG_LEDS_GPIO=y
1784 +# CONFIG_LEDS_LT3593 is not set
1785 +CONFIG_LEDS_TRIGGERS=y
1786 +
1787 +#
1788 +# LED Triggers
1789 +#
1790 +CONFIG_LEDS_TRIGGER_TIMER=m
1791 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1792 +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
1793 +# CONFIG_LEDS_TRIGGER_GPIO is not set
1794 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
1795 +
1796 +#
1797 +# iptables trigger is under Netfilter config (LED target)
1798 +#
1799 +# CONFIG_ACCESSIBILITY is not set
1800 +CONFIG_RTC_LIB=y
1801 +# CONFIG_RTC_CLASS is not set
1802 +# CONFIG_DMADEVICES is not set
1803 +# CONFIG_AUXDISPLAY is not set
1804 +# CONFIG_UIO is not set
1805 +
1806 +#
1807 +# Virtio drivers
1808 +#
1809 +# CONFIG_VIRTIO_BALLOON is not set
1810 +# CONFIG_STAGING is not set
1811 +CONFIG_CLKDEV_LOOKUP=y
1812 +# CONFIG_IOMMU_SUPPORT is not set
1813 +# CONFIG_VIRT_DRIVERS is not set
1814 +
1815 +#
1816 +# File systems
1817 +#
1818 +CONFIG_EXT2_FS=m
1819 +CONFIG_EXT2_FS_XATTR=y
1820 +CONFIG_EXT2_FS_POSIX_ACL=y
1821 +CONFIG_EXT2_FS_SECURITY=y
1822 +CONFIG_EXT2_FS_XIP=y
1823 +CONFIG_EXT3_FS=y
1824 +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1825 +CONFIG_EXT3_FS_XATTR=y
1826 +CONFIG_EXT3_FS_POSIX_ACL=y
1827 +CONFIG_EXT3_FS_SECURITY=y
1828 +CONFIG_EXT4_FS=m
1829 +CONFIG_EXT4_FS_XATTR=y
1830 +CONFIG_EXT4_FS_POSIX_ACL=y
1831 +CONFIG_EXT4_FS_SECURITY=y
1832 +# CONFIG_EXT4_DEBUG is not set
1833 +CONFIG_FS_XIP=y
1834 +CONFIG_JBD=y
1835 +CONFIG_JBD2=m
1836 +CONFIG_FS_MBCACHE=y
1837 +# CONFIG_REISERFS_FS is not set
1838 +# CONFIG_JFS_FS is not set
1839 +# CONFIG_XFS_FS is not set
1840 +# CONFIG_GFS2_FS is not set
1841 +# CONFIG_OCFS2_FS is not set
1842 +# CONFIG_BTRFS_FS is not set
1843 +# CONFIG_NILFS2_FS is not set
1844 +CONFIG_FS_POSIX_ACL=y
1845 +CONFIG_FILE_LOCKING=y
1846 +CONFIG_FSNOTIFY=y
1847 +CONFIG_DNOTIFY=y
1848 +CONFIG_INOTIFY_USER=y
1849 +# CONFIG_FANOTIFY is not set
1850 +# CONFIG_QUOTA is not set
1851 +# CONFIG_QUOTACTL is not set
1852 +CONFIG_AUTOFS4_FS=y
1853 +CONFIG_FUSE_FS=m
1854 +CONFIG_CUSE=m
1855 +
1856 +#
1857 +# Caches
1858 +#
1859 +CONFIG_FSCACHE=y
1860 +# CONFIG_FSCACHE_STATS is not set
1861 +# CONFIG_FSCACHE_HISTOGRAM is not set
1862 +# CONFIG_FSCACHE_DEBUG is not set
1863 +# CONFIG_FSCACHE_OBJECT_LIST is not set
1864 +CONFIG_CACHEFILES=y
1865 +# CONFIG_CACHEFILES_DEBUG is not set
1866 +# CONFIG_CACHEFILES_HISTOGRAM is not set
1867 +
1868 +#
1869 +# CD-ROM/DVD Filesystems
1870 +#
1871 +CONFIG_ISO9660_FS=m
1872 +CONFIG_JOLIET=y
1873 +CONFIG_ZISOFS=y
1874 +CONFIG_UDF_FS=m
1875 +CONFIG_UDF_NLS=y
1876 +
1877 +#
1878 +# DOS/FAT/NT Filesystems
1879 +#
1880 +CONFIG_FAT_FS=y
1881 +CONFIG_MSDOS_FS=y
1882 +CONFIG_VFAT_FS=y
1883 +CONFIG_FAT_DEFAULT_CODEPAGE=437
1884 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1885 +CONFIG_NTFS_FS=m
1886 +# CONFIG_NTFS_DEBUG is not set
1887 +# CONFIG_NTFS_RW is not set
1888 +
1889 +#
1890 +# Pseudo filesystems
1891 +#
1892 +CONFIG_PROC_FS=y
1893 +CONFIG_PROC_SYSCTL=y
1894 +CONFIG_PROC_PAGE_MONITOR=y
1895 +CONFIG_SYSFS=y
1896 +CONFIG_TMPFS=y
1897 +# CONFIG_TMPFS_POSIX_ACL is not set
1898 +# CONFIG_TMPFS_XATTR is not set
1899 +# CONFIG_HUGETLB_PAGE is not set
1900 +CONFIG_CONFIGFS_FS=y
1901 +CONFIG_MISC_FILESYSTEMS=y
1902 +# CONFIG_ADFS_FS is not set
1903 +# CONFIG_AFFS_FS is not set
1904 +# CONFIG_ECRYPT_FS is not set
1905 +# CONFIG_HFS_FS is not set
1906 +# CONFIG_HFSPLUS_FS is not set
1907 +# CONFIG_BEFS_FS is not set
1908 +# CONFIG_BFS_FS is not set
1909 +# CONFIG_EFS_FS is not set
1910 +# CONFIG_LOGFS is not set
1911 +# CONFIG_CRAMFS is not set
1912 +# CONFIG_SQUASHFS is not set
1913 +# CONFIG_VXFS_FS is not set
1914 +# CONFIG_MINIX_FS is not set
1915 +# CONFIG_OMFS_FS is not set
1916 +# CONFIG_HPFS_FS is not set
1917 +# CONFIG_QNX4FS_FS is not set
1918 +# CONFIG_ROMFS_FS is not set
1919 +# CONFIG_PSTORE is not set
1920 +# CONFIG_SYSV_FS is not set
1921 +# CONFIG_UFS_FS is not set
1922 +CONFIG_NETWORK_FILESYSTEMS=y
1923 +CONFIG_NFS_FS=y
1924 +CONFIG_NFS_V3=y
1925 +CONFIG_NFS_V3_ACL=y
1926 +CONFIG_NFS_V4=y
1927 +# CONFIG_NFS_V4_1 is not set
1928 +CONFIG_ROOT_NFS=y
1929 +CONFIG_NFS_FSCACHE=y
1930 +# CONFIG_NFS_USE_LEGACY_DNS is not set
1931 +CONFIG_NFS_USE_KERNEL_DNS=y
1932 +# CONFIG_NFS_USE_NEW_IDMAPPER is not set
1933 +# CONFIG_NFSD is not set
1934 +CONFIG_LOCKD=y
1935 +CONFIG_LOCKD_V4=y
1936 +CONFIG_NFS_ACL_SUPPORT=y
1937 +CONFIG_NFS_COMMON=y
1938 +CONFIG_SUNRPC=y
1939 +CONFIG_SUNRPC_GSS=y
1940 +# CONFIG_CEPH_FS is not set
1941 +CONFIG_CIFS=m
1942 +# CONFIG_CIFS_STATS is not set
1943 +CONFIG_CIFS_WEAK_PW_HASH=y
1944 +# CONFIG_CIFS_UPCALL is not set
1945 +CONFIG_CIFS_XATTR=y
1946 +CONFIG_CIFS_POSIX=y
1947 +# CONFIG_CIFS_DEBUG2 is not set
1948 +# CONFIG_CIFS_DFS_UPCALL is not set
1949 +# CONFIG_CIFS_FSCACHE is not set
1950 +# CONFIG_CIFS_ACL is not set
1951 +# CONFIG_NCP_FS is not set
1952 +# CONFIG_CODA_FS is not set
1953 +# CONFIG_AFS_FS is not set
1954 +
1955 +#
1956 +# Partition Types
1957 +#
1958 +CONFIG_PARTITION_ADVANCED=y
1959 +# CONFIG_ACORN_PARTITION is not set
1960 +# CONFIG_OSF_PARTITION is not set
1961 +# CONFIG_AMIGA_PARTITION is not set
1962 +# CONFIG_ATARI_PARTITION is not set
1963 +CONFIG_MAC_PARTITION=y
1964 +CONFIG_MSDOS_PARTITION=y
1965 +# CONFIG_BSD_DISKLABEL is not set
1966 +# CONFIG_MINIX_SUBPARTITION is not set
1967 +# CONFIG_SOLARIS_X86_PARTITION is not set
1968 +# CONFIG_UNIXWARE_DISKLABEL is not set
1969 +# CONFIG_LDM_PARTITION is not set
1970 +# CONFIG_SGI_PARTITION is not set
1971 +# CONFIG_ULTRIX_PARTITION is not set
1972 +# CONFIG_SUN_PARTITION is not set
1973 +# CONFIG_KARMA_PARTITION is not set
1974 +CONFIG_EFI_PARTITION=y
1975 +# CONFIG_SYSV68_PARTITION is not set
1976 +CONFIG_NLS=y
1977 +CONFIG_NLS_DEFAULT="utf8"
1978 +CONFIG_NLS_CODEPAGE_437=y
1979 +CONFIG_NLS_CODEPAGE_737=m
1980 +CONFIG_NLS_CODEPAGE_775=m
1981 +CONFIG_NLS_CODEPAGE_850=m
1982 +CONFIG_NLS_CODEPAGE_852=m
1983 +CONFIG_NLS_CODEPAGE_855=m
1984 +CONFIG_NLS_CODEPAGE_857=m
1985 +CONFIG_NLS_CODEPAGE_860=m
1986 +CONFIG_NLS_CODEPAGE_861=m
1987 +CONFIG_NLS_CODEPAGE_862=m
1988 +CONFIG_NLS_CODEPAGE_863=m
1989 +CONFIG_NLS_CODEPAGE_864=m
1990 +CONFIG_NLS_CODEPAGE_865=m
1991 +CONFIG_NLS_CODEPAGE_866=m
1992 +CONFIG_NLS_CODEPAGE_869=m
1993 +CONFIG_NLS_CODEPAGE_936=m
1994 +CONFIG_NLS_CODEPAGE_950=m
1995 +CONFIG_NLS_CODEPAGE_932=m
1996 +CONFIG_NLS_CODEPAGE_949=m
1997 +CONFIG_NLS_CODEPAGE_874=m
1998 +CONFIG_NLS_ISO8859_8=m
1999 +CONFIG_NLS_CODEPAGE_1250=m
2000 +CONFIG_NLS_CODEPAGE_1251=m
2001 +CONFIG_NLS_ASCII=y
2002 +CONFIG_NLS_ISO8859_1=m
2003 +CONFIG_NLS_ISO8859_2=m
2004 +CONFIG_NLS_ISO8859_3=m
2005 +CONFIG_NLS_ISO8859_4=m
2006 +CONFIG_NLS_ISO8859_5=m
2007 +CONFIG_NLS_ISO8859_6=m
2008 +CONFIG_NLS_ISO8859_7=m
2009 +CONFIG_NLS_ISO8859_9=m
2010 +CONFIG_NLS_ISO8859_13=m
2011 +CONFIG_NLS_ISO8859_14=m
2012 +CONFIG_NLS_ISO8859_15=m
2013 +CONFIG_NLS_KOI8_R=m
2014 +CONFIG_NLS_KOI8_U=m
2015 +CONFIG_NLS_UTF8=m
2016 +# CONFIG_DLM is not set
2017 +
2018 +#
2019 +# Kernel hacking
2020 +#
2021 +# CONFIG_PRINTK_TIME is not set
2022 +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
2023 +CONFIG_ENABLE_WARN_DEPRECATED=y
2024 +CONFIG_ENABLE_MUST_CHECK=y
2025 +CONFIG_FRAME_WARN=1024
2026 +# CONFIG_MAGIC_SYSRQ is not set
2027 +# CONFIG_STRIP_ASM_SYMS is not set
2028 +# CONFIG_UNUSED_SYMBOLS is not set
2029 +# CONFIG_DEBUG_FS is not set
2030 +# CONFIG_HEADERS_CHECK is not set
2031 +# CONFIG_DEBUG_SECTION_MISMATCH is not set
2032 +CONFIG_DEBUG_KERNEL=y
2033 +# CONFIG_DEBUG_SHIRQ is not set
2034 +# CONFIG_LOCKUP_DETECTOR is not set
2035 +# CONFIG_HARDLOCKUP_DETECTOR is not set
2036 +# CONFIG_DETECT_HUNG_TASK is not set
2037 +# CONFIG_SCHED_DEBUG is not set
2038 +# CONFIG_SCHEDSTATS is not set
2039 +# CONFIG_TIMER_STATS is not set
2040 +# CONFIG_DEBUG_OBJECTS is not set
2041 +# CONFIG_DEBUG_SLAB is not set
2042 +# CONFIG_DEBUG_KMEMLEAK is not set
2043 +# CONFIG_DEBUG_RT_MUTEXES is not set
2044 +# CONFIG_RT_MUTEX_TESTER is not set
2045 +# CONFIG_DEBUG_SPINLOCK is not set
2046 +# CONFIG_DEBUG_MUTEXES is not set
2047 +# CONFIG_DEBUG_LOCK_ALLOC is not set
2048 +# CONFIG_PROVE_LOCKING is not set
2049 +# CONFIG_SPARSE_RCU_POINTER is not set
2050 +# CONFIG_LOCK_STAT is not set
2051 +# CONFIG_DEBUG_ATOMIC_SLEEP is not set
2052 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
2053 +# CONFIG_DEBUG_STACK_USAGE is not set
2054 +# CONFIG_DEBUG_KOBJECT is not set
2055 +# CONFIG_DEBUG_BUGVERBOSE is not set
2056 +# CONFIG_DEBUG_INFO is not set
2057 +# CONFIG_DEBUG_VM is not set
2058 +# CONFIG_DEBUG_WRITECOUNT is not set
2059 +# CONFIG_DEBUG_MEMORY_INIT is not set
2060 +# CONFIG_DEBUG_LIST is not set
2061 +# CONFIG_TEST_LIST_SORT is not set
2062 +# CONFIG_DEBUG_SG is not set
2063 +# CONFIG_DEBUG_NOTIFIERS is not set
2064 +# CONFIG_DEBUG_CREDENTIALS is not set
2065 +CONFIG_FRAME_POINTER=y
2066 +# CONFIG_BOOT_PRINTK_DELAY is not set
2067 +# CONFIG_RCU_TORTURE_TEST is not set
2068 +# CONFIG_BACKTRACE_SELF_TEST is not set
2069 +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
2070 +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
2071 +# CONFIG_FAULT_INJECTION is not set
2072 +# CONFIG_LATENCYTOP is not set
2073 +# CONFIG_SYSCTL_SYSCALL_CHECK is not set
2074 +# CONFIG_DEBUG_PAGEALLOC is not set
2075 +CONFIG_HAVE_FUNCTION_TRACER=y
2076 +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
2077 +CONFIG_HAVE_DYNAMIC_FTRACE=y
2078 +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
2079 +CONFIG_HAVE_C_RECORDMCOUNT=y
2080 +CONFIG_TRACING_SUPPORT=y
2081 +# CONFIG_FTRACE is not set
2082 +# CONFIG_DMA_API_DEBUG is not set
2083 +# CONFIG_ATOMIC64_SELFTEST is not set
2084 +# CONFIG_SAMPLES is not set
2085 +CONFIG_HAVE_ARCH_KGDB=y
2086 +# CONFIG_KGDB is not set
2087 +# CONFIG_TEST_KSTRTOX is not set
2088 +# CONFIG_STRICT_DEVMEM is not set
2089 +# CONFIG_ARM_UNWIND is not set
2090 +# CONFIG_DEBUG_USER is not set
2091 +# CONFIG_DEBUG_LL is not set
2092 +# CONFIG_OC_ETM is not set
2093 +
2094 +#
2095 +# Security options
2096 +#
2097 +CONFIG_KEYS=y
2098 +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
2099 +# CONFIG_SECURITY_DMESG_RESTRICT is not set
2100 +# CONFIG_SECURITY is not set
2101 +# CONFIG_SECURITYFS is not set
2102 +CONFIG_DEFAULT_SECURITY_DAC=y
2103 +CONFIG_DEFAULT_SECURITY=""
2104 +CONFIG_CRYPTO=y
2105 +
2106 +#
2107 +# Crypto core or helper
2108 +#
2109 +CONFIG_CRYPTO_ALGAPI=y
2110 +CONFIG_CRYPTO_ALGAPI2=y
2111 +CONFIG_CRYPTO_AEAD=m
2112 +CONFIG_CRYPTO_AEAD2=y
2113 +CONFIG_CRYPTO_BLKCIPHER=y
2114 +CONFIG_CRYPTO_BLKCIPHER2=y
2115 +CONFIG_CRYPTO_HASH=y
2116 +CONFIG_CRYPTO_HASH2=y
2117 +CONFIG_CRYPTO_RNG=m
2118 +CONFIG_CRYPTO_RNG2=y
2119 +CONFIG_CRYPTO_PCOMP2=y
2120 +CONFIG_CRYPTO_MANAGER=y
2121 +CONFIG_CRYPTO_MANAGER2=y
2122 +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
2123 +# CONFIG_CRYPTO_GF128MUL is not set
2124 +# CONFIG_CRYPTO_NULL is not set
2125 +CONFIG_CRYPTO_WORKQUEUE=y
2126 +# CONFIG_CRYPTO_CRYPTD is not set
2127 +CONFIG_CRYPTO_AUTHENC=m
2128 +# CONFIG_CRYPTO_TEST is not set
2129 +
2130 +#
2131 +# Authenticated Encryption with Associated Data
2132 +#
2133 +# CONFIG_CRYPTO_CCM is not set
2134 +# CONFIG_CRYPTO_GCM is not set
2135 +CONFIG_CRYPTO_SEQIV=m
2136 +
2137 +#
2138 +# Block modes
2139 +#
2140 +CONFIG_CRYPTO_CBC=y
2141 +# CONFIG_CRYPTO_CTR is not set
2142 +# CONFIG_CRYPTO_CTS is not set
2143 +CONFIG_CRYPTO_ECB=m
2144 +# CONFIG_CRYPTO_LRW is not set
2145 +# CONFIG_CRYPTO_PCBC is not set
2146 +# CONFIG_CRYPTO_XTS is not set
2147 +
2148 +#
2149 +# Hash modes
2150 +#
2151 +CONFIG_CRYPTO_HMAC=y
2152 +CONFIG_CRYPTO_XCBC=m
2153 +# CONFIG_CRYPTO_VMAC is not set
2154 +
2155 +#
2156 +# Digest
2157 +#
2158 +CONFIG_CRYPTO_CRC32C=y
2159 +# CONFIG_CRYPTO_GHASH is not set
2160 +CONFIG_CRYPTO_MD4=m
2161 +CONFIG_CRYPTO_MD5=y
2162 +CONFIG_CRYPTO_MICHAEL_MIC=m
2163 +# CONFIG_CRYPTO_RMD128 is not set
2164 +# CONFIG_CRYPTO_RMD160 is not set
2165 +# CONFIG_CRYPTO_RMD256 is not set
2166 +# CONFIG_CRYPTO_RMD320 is not set
2167 +CONFIG_CRYPTO_SHA1=y
2168 +CONFIG_CRYPTO_SHA256=m
2169 +CONFIG_CRYPTO_SHA512=m
2170 +CONFIG_CRYPTO_TGR192=m
2171 +CONFIG_CRYPTO_WP512=m
2172 +
2173 +#
2174 +# Ciphers
2175 +#
2176 +# CONFIG_CRYPTO_AES is not set
2177 +# CONFIG_CRYPTO_ANUBIS is not set
2178 +CONFIG_CRYPTO_ARC4=m
2179 +# CONFIG_CRYPTO_BLOWFISH is not set
2180 +# CONFIG_CRYPTO_CAMELLIA is not set
2181 +CONFIG_CRYPTO_CAST5=m
2182 +# CONFIG_CRYPTO_CAST6 is not set
2183 +CONFIG_CRYPTO_DES=y
2184 +# CONFIG_CRYPTO_FCRYPT is not set
2185 +# CONFIG_CRYPTO_KHAZAD is not set
2186 +# CONFIG_CRYPTO_SALSA20 is not set
2187 +# CONFIG_CRYPTO_SEED is not set
2188 +# CONFIG_CRYPTO_SERPENT is not set
2189 +# CONFIG_CRYPTO_TEA is not set
2190 +# CONFIG_CRYPTO_TWOFISH is not set
2191 +
2192 +#
2193 +# Compression
2194 +#
2195 +CONFIG_CRYPTO_DEFLATE=m
2196 +# CONFIG_CRYPTO_ZLIB is not set
2197 +# CONFIG_CRYPTO_LZO is not set
2198 +
2199 +#
2200 +# Random Number Generation
2201 +#
2202 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
2203 +# CONFIG_CRYPTO_USER_API_HASH is not set
2204 +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
2205 +# CONFIG_CRYPTO_HW is not set
2206 +# CONFIG_BINARY_PRINTF is not set
2207 +
2208 +#
2209 +# Library routines
2210 +#
2211 +CONFIG_BITREVERSE=y
2212 +CONFIG_CRC_CCITT=m
2213 +CONFIG_CRC16=y
2214 +# CONFIG_CRC_T10DIF is not set
2215 +CONFIG_CRC_ITU_T=y
2216 +CONFIG_CRC32=y
2217 +# CONFIG_CRC7 is not set
2218 +CONFIG_LIBCRC32C=y
2219 +# CONFIG_CRC8 is not set
2220 +CONFIG_ZLIB_INFLATE=m
2221 +CONFIG_ZLIB_DEFLATE=m
2222 +# CONFIG_XZ_DEC is not set
2223 +# CONFIG_XZ_DEC_BCJ is not set
2224 +CONFIG_HAS_IOMEM=y
2225 +CONFIG_HAS_IOPORT=y
2226 +CONFIG_HAS_DMA=y
2227 +CONFIG_NLATTR=y
2228 +CONFIG_GENERIC_ATOMIC64=y
2229 +# CONFIG_AVERAGE is not set
2230 +# CONFIG_CORDIC is not set
2231 --- a/arch/arm/kernel/armksyms.c
2232 +++ b/arch/arm/kernel/armksyms.c
2233 @@ -46,6 +46,8 @@ extern void __aeabi_lmul(void);
2234  extern void __aeabi_uidiv(void);
2235  extern void __aeabi_uidivmod(void);
2236  extern void __aeabi_ulcmp(void);
2237 +extern void __aeabi_ldivmod(void);
2238 +extern void __aeabi_uldivmod(void);
2239
2240  extern void fpundefinstr(void);
2241
2242 @@ -131,6 +133,8 @@ EXPORT_SYMBOL(__aeabi_lmul);
2243  EXPORT_SYMBOL(__aeabi_uidiv);
2244  EXPORT_SYMBOL(__aeabi_uidivmod);
2245  EXPORT_SYMBOL(__aeabi_ulcmp);
2246 +EXPORT_SYMBOL(__aeabi_ldivmod);
2247 +EXPORT_SYMBOL(__aeabi_uldivmod);
2248  #endif
2249
2250         /* bitops */
2251 --- /dev/null
2252 +++ b/arch/arm/lib/divdi3.c
2253 @@ -0,0 +1,338 @@
2254 +/* 64-bit multiplication and division
2255 +   Copyright (C) 1989, 1992-1999, 2000, 2001, 2002, 2003
2256 +   Free Software Foundation, Inc.
2257 +   This file is part of the GNU C Library.
2258 +
2259 +   The GNU C Library is free software; you can redistribute it and/or
2260 +   modify it under the terms of the GNU Lesser General Public
2261 +   License as published by the Free Software Foundation; either
2262 +   version 2.1 of the License, or (at your option) any later version.
2263 +
2264 +   The GNU C Library is distributed in the hope that it will be useful,
2265 +   but WITHOUT ANY WARRANTY; without even the implied warranty of
2266 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
2267 +   Lesser General Public License for more details.
2268 +
2269 +   You should have received a copy of the GNU Lesser General Public
2270 +   License along with the GNU C Library; if not, write to the Free
2271 +   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
2272 +   02111-1307 USA.  */
2273 +
2274 +#include "longlong.h"
2275 +
2276 +#define W_TYPE_SIZE (sizeof(long))
2277 +
2278 +#ifdef __ARMEB__
2279 +struct DWstruct { long high, low;};
2280 +#else
2281 +struct DWstruct { long low, high;};
2282 +#endif
2283 +
2284 +typedef union { struct DWstruct s; long long ll; } DWunion;
2285 +
2286 +/* Prototypes of exported functions.  */
2287 +long long __divdi3 (long long u, long long v);
2288 +long long __moddi3 (long long u, long long v);
2289 +unsigned long long __udivdi3 (unsigned long long u, unsigned long long v);
2290 +unsigned long long __umoddi3 (unsigned long long u, unsigned long long v);
2291 +
2292 +static unsigned long long
2293 +__udivmoddi4 (unsigned long long n, unsigned long long d, unsigned long long *rp)
2294 +{
2295 +  DWunion ww;
2296 +  DWunion nn, dd;
2297 +  DWunion rr;
2298 +  unsigned long d0, d1, n0, n1, n2;
2299 +  unsigned long q0, q1;
2300 +  unsigned long b, bm;
2301 +
2302 +  nn.ll = n;
2303 +  dd.ll = d;
2304 +
2305 +  d0 = dd.s.low;
2306 +  d1 = dd.s.high;
2307 +  n0 = nn.s.low;
2308 +  n1 = nn.s.high;
2309 +
2310 +#if !UDIV_NEEDS_NORMALIZATION
2311 +  if (d1 == 0)
2312 +    {
2313 +      if (d0 > n1)
2314 +       {
2315 +         /* 0q = nn / 0D */
2316 +
2317 +         udiv_qrnnd (q0, n0, n1, n0, d0);
2318 +         q1 = 0;
2319 +
2320 +         /* Remainder in n0.  */
2321 +       }
2322 +      else
2323 +       {
2324 +         /* qq = NN / 0d */
2325 +
2326 +         if (d0 == 0)
2327 +           d0 = 1 / d0;        /* Divide intentionally by zero.  */
2328 +
2329 +         udiv_qrnnd (q1, n1, 0, n1, d0);
2330 +         udiv_qrnnd (q0, n0, n1, n0, d0);
2331 +
2332 +         /* Remainder in n0.  */
2333 +       }
2334 +
2335 +      if (rp != 0)
2336 +       {
2337 +         rr.s.low = n0;
2338 +         rr.s.high = 0;
2339 +         *rp = rr.ll;
2340 +       }
2341 +    }
2342 +
2343 +#else /* UDIV_NEEDS_NORMALIZATION */
2344 +
2345 +  if (d1 == 0)
2346 +    {
2347 +      if (d0 > n1)
2348 +       {
2349 +         /* 0q = nn / 0D */
2350 +
2351 +         count_leading_zeros (bm, d0);
2352 +
2353 +         if (bm != 0)
2354 +           {
2355 +             /* Normalize, i.e. make the most significant bit of the
2356 +                denominator set.  */
2357 +
2358 +             d0 = d0 << bm;
2359 +             n1 = (n1 << bm) | (n0 >> (W_TYPE_SIZE - bm));
2360 +             n0 = n0 << bm;
2361 +           }
2362 +
2363 +         udiv_qrnnd (q0, n0, n1, n0, d0);
2364 +         q1 = 0;
2365 +
2366 +         /* Remainder in n0 >> bm.  */
2367 +       }
2368 +      else
2369 +       {
2370 +         /* qq = NN / 0d */
2371 +
2372 +         if (d0 == 0)
2373 +           d0 = 1 / d0;        /* Divide intentionally by zero.  */
2374 +
2375 +         count_leading_zeros (bm, d0);
2376 +
2377 +         if (bm == 0)
2378 +           {
2379 +             /* From (n1 >= d0) /\ (the most significant bit of d0 is set),
2380 +                conclude (the most significant bit of n1 is set) /\ (the
2381 +                leading quotient digit q1 = 1).
2382 +
2383 +                This special case is necessary, not an optimization.
2384 +                (Shifts counts of W_TYPE_SIZE are undefined.)  */
2385 +
2386 +             n1 -= d0;
2387 +             q1 = 1;
2388 +           }
2389 +         else
2390 +           {
2391 +             /* Normalize.  */
2392 +
2393 +             b = W_TYPE_SIZE - bm;
2394 +
2395 +             d0 = d0 << bm;
2396 +             n2 = n1 >> b;
2397 +             n1 = (n1 << bm) | (n0 >> b);
2398 +             n0 = n0 << bm;
2399 +
2400 +             udiv_qrnnd (q1, n1, n2, n1, d0);
2401 +           }
2402 +
2403 +         /* n1 != d0...  */
2404 +
2405 +         udiv_qrnnd (q0, n0, n1, n0, d0);
2406 +
2407 +         /* Remainder in n0 >> bm.  */
2408 +       }
2409 +
2410 +      if (rp != 0)
2411 +       {
2412 +         rr.s.low = n0 >> bm;
2413 +         rr.s.high = 0;
2414 +         *rp = rr.ll;
2415 +       }
2416 +    }
2417 +#endif /* UDIV_NEEDS_NORMALIZATION */
2418 +
2419 +  else
2420 +    {
2421 +      if (d1 > n1)
2422 +       {
2423 +         /* 00 = nn / DD */
2424 +
2425 +         q0 = 0;
2426 +         q1 = 0;
2427 +
2428 +         /* Remainder in n1n0.  */
2429 +         if (rp != 0)
2430 +           {
2431 +             rr.s.low = n0;
2432 +             rr.s.high = n1;
2433 +             *rp = rr.ll;
2434 +           }
2435 +       }
2436 +      else
2437 +       {
2438 +         /* 0q = NN / dd */
2439 +
2440 +         count_leading_zeros (bm, d1);
2441 +         if (bm == 0)
2442 +           {
2443 +             /* From (n1 >= d1) /\ (the most significant bit of d1 is set),
2444 +                conclude (the most significant bit of n1 is set) /\ (the
2445 +                quotient digit q0 = 0 or 1).
2446 +
2447 +                This special case is necessary, not an optimization.  */
2448 +
2449 +             /* The condition on the next line takes advantage of that
2450 +                n1 >= d1 (true due to program flow).  */
2451 +             if (n1 > d1 || n0 >= d0)
2452 +               {
2453 +                 q0 = 1;
2454 +                 sub_ddmmss (n1, n0, n1, n0, d1, d0);
2455 +               }
2456 +             else
2457 +               q0 = 0;
2458 +
2459 +             q1 = 0;
2460 +
2461 +             if (rp != 0)
2462 +               {
2463 +                 rr.s.low = n0;
2464 +                 rr.s.high = n1;
2465 +                 *rp = rr.ll;
2466 +               }
2467 +           }
2468 +         else
2469 +           {
2470 +             unsigned long m1, m0;
2471 +             /* Normalize.  */
2472 +
2473 +             b = W_TYPE_SIZE - bm;
2474 +
2475 +             d1 = (d1 << bm) | (d0 >> b);
2476 +             d0 = d0 << bm;
2477 +             n2 = n1 >> b;
2478 +             n1 = (n1 << bm) | (n0 >> b);
2479 +             n0 = n0 << bm;
2480 +
2481 +             udiv_qrnnd (q0, n1, n2, n1, d1);
2482 +             umul_ppmm (m1, m0, q0, d0);
2483 +
2484 +             if (m1 > n1 || (m1 == n1 && m0 > n0))
2485 +               {
2486 +                 q0--;
2487 +                 sub_ddmmss (m1, m0, m1, m0, d1, d0);
2488 +               }
2489 +
2490 +             q1 = 0;
2491 +
2492 +             /* Remainder in (n1n0 - m1m0) >> bm.  */
2493 +             if (rp != 0)
2494 +               {
2495 +                 sub_ddmmss (n1, n0, n1, n0, m1, m0);
2496 +                 rr.s.low = (n1 << b) | (n0 >> bm);
2497 +                 rr.s.high = n1 >> bm;
2498 +                 *rp = rr.ll;
2499 +               }
2500 +           }
2501 +       }
2502 +    }
2503 +
2504 +  ww.s.low = q0;
2505 +  ww.s.high = q1;
2506 +  return ww.ll;
2507 +}
2508 +
2509 +long long
2510 +__divdi3 (long long u, long long v)
2511 +{
2512 +  long c = 0;
2513 +  long long w;
2514 +
2515 +  if (u < 0)
2516 +    {
2517 +      c = ~c;
2518 +      u = -u;
2519 +    }
2520 +  if (v < 0)
2521 +    {
2522 +      c = ~c;
2523 +      v = -v;
2524 +    }
2525 +  w = __udivmoddi4 (u, v, 0);
2526 +  if (c)
2527 +    w = -w;
2528 +  return w;
2529 +}
2530 +
2531 +long long
2532 +__moddi3 (long long u, long long v)
2533 +{
2534 +  long c = 0;
2535 +  long long w;
2536 +
2537 +  if (u < 0)
2538 +    {
2539 +      c = ~c;
2540 +      u = -u;
2541 +    }
2542 +  if (v < 0)
2543 +    v = -v;
2544 +  __udivmoddi4 (u, v, &w);
2545 +  if (c)
2546 +    w = -w;
2547 +  return w;
2548 +}
2549 +
2550 +unsigned long long
2551 +__udivdi3 (unsigned long long u, unsigned long long v)
2552 +{
2553 +  return __udivmoddi4 (u, v, 0);
2554 +}
2555 +
2556 +unsigned long long
2557 +__umoddi3 (unsigned long long u, unsigned long long v)
2558 +{
2559 +  unsigned long long w;
2560 +
2561 +  __udivmoddi4 (u, v, &w);
2562 +  return w;
2563 +}
2564 +
2565 +long long
2566 +__gnu_ldivmod_helper (long long a,
2567 +
2568 +                     long long b,
2569 +                     long long *remainder)
2570 +{
2571 +  long long quotient;
2572 +
2573 +  quotient = __divdi3 (a, b);
2574 +  *remainder = a - b * quotient;
2575 +
2576 +  return quotient;
2577 +}
2578 +
2579 +unsigned long long
2580 +
2581 +__gnu_uldivmod_helper (unsigned long long a,
2582 +
2583 +                      unsigned long long b,
2584 +                      unsigned long long *remainder)
2585 +{
2586 +  unsigned long long quotient;
2587 +
2588 +  quotient = __udivdi3 (a, b);
2589 +  *remainder = a - b * quotient;
2590 +  return quotient;
2591 +}
2592 --- a/arch/arm/lib/lib1funcs.S
2593 +++ b/arch/arm/lib/lib1funcs.S
2594 @@ -349,6 +349,33 @@ UNWIND(.save {r0, r1, ip, lr}      )
2595  UNWIND(.fnend)
2596  ENDPROC(__aeabi_idivmod)
2597
2598 +/* Added 64x64 bit division for use with OTG USB driver - multi-precision
2599 + * arithmetic for RSA encyrption.
2600 + */
2601 +ENTRY(__aeabi_ldivmod)
2602 +
2603 +        sub     sp, sp, #8
2604 +        stmfd   sp!, {sp, lr}
2605 +        bl      __gnu_ldivmod_helper
2606 +        ldr     lr, [sp, #4]
2607 +        add     sp, sp, #8
2608 +        ldmfd   sp!, {r2, r3}
2609 +        mov     pc, lr
2610 +
2611 +ENDPROC(__aeabi_ldivmod)
2612 +
2613 +ENTRY(__aeabi_uldivmod)
2614 +
2615 +        sub     sp, sp, #8
2616 +        stmfd   sp!, {sp, lr}
2617 +        bl      __gnu_uldivmod_helper
2618 +        ldr     lr, [sp, #4]
2619 +        add     sp, sp, #8
2620 +        ldmfd   sp!, {r2, r3}
2621 +        mov     pc, lr
2622 +
2623 +ENDPROC(__aeabi_uldivmod)
2624 +
2625  #endif
2626
2627  Ldiv0:
2628 --- /dev/null
2629 +++ b/arch/arm/lib/longlong.h
2630 @@ -0,0 +1,151 @@
2631 +/* longlong.h -- based on code from gcc-2.95.3
2632 +
2633 +   definitions for mixed size 32/64 bit arithmetic.
2634 +   Copyright (C) 1991, 92, 94, 95, 96, 1997, 1998 Free Software Foundation, Inc.
2635 +
2636 +   This definition file is free software; you can redistribute it
2637 +   and/or modify it under the terms of the GNU General Public
2638 +   License as published by the Free Software Foundation; either
2639 +   version 2, or (at your option) any later version.
2640 +
2641 +   This definition file is distributed in the hope that it will be
2642 +   useful, but WITHOUT ANY WARRANTY; without even the implied
2643 +   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
2644 +   See the GNU General Public License for more details.
2645 +
2646 +   You should have received a copy of the GNU General Public License
2647 +   along with this program; if not, write to the Free Software
2648 +   Foundation, Inc., 59 Temple Place - Suite 330,
2649 +   Boston, MA 02111-1307, USA.  */
2650 +
2651 +/* Borrowed from GCC 2.95.3, I Molton 29/07/01 */
2652 +
2653 +#define USItype unsigned long
2654 +#define SI_TYPE_SIZE sizeof(USItype)
2655 +
2656 +#define __BITS4 (SI_TYPE_SIZE / 4)
2657 +#define __ll_B (1L << (SI_TYPE_SIZE / 2))
2658 +#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
2659 +#define __ll_highpart(t) ((USItype) (t) / __ll_B)
2660 +
2661 +/* Define auxiliary asm macros.
2662 +
2663 +   1) umul_ppmm(high_prod, low_prod, multipler, multiplicand)
2664 +   multiplies two USItype integers MULTIPLER and MULTIPLICAND,
2665 +   and generates a two-part USItype product in HIGH_PROD and
2666 +   LOW_PROD.
2667 +
2668 +   2) __umulsidi3(a,b) multiplies two USItype integers A and B,
2669 +   and returns a UDItype product.  This is just a variant of umul_ppmm.
2670 +
2671 +   3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
2672 +   denominator) divides a two-word unsigned integer, composed by the
2673 +   integers HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and
2674 +   places the quotient in QUOTIENT and the remainder in REMAINDER.
2675 +   HIGH_NUMERATOR must be less than DENOMINATOR for correct operation.
2676 +   If, in addition, the most significant bit of DENOMINATOR must be 1,
2677 +   then the pre-processor symbol UDIV_NEEDS_NORMALIZATION is defined to 1.
2678 +
2679 +   4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
2680 +   denominator).  Like udiv_qrnnd but the numbers are signed.  The
2681 +   quotient is rounded towards 0.
2682 +
2683 +   5) count_leading_zeros(count, x) counts the number of zero-bits from
2684 +   the msb to the first non-zero bit.  This is the number of steps X
2685 +   needs to be shifted left to set the msb.  Undefined for X == 0.
2686 +
2687 +   6) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
2688 +   high_addend_2, low_addend_2) adds two two-word unsigned integers,
2689 +   composed by HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and
2690 +   LOW_ADDEND_2 respectively.  The result is placed in HIGH_SUM and
2691 +   LOW_SUM.  Overflow (i.e. carry out) is not stored anywhere, and is
2692 +   lost.
2693 +
2694 +   7) sub_ddmmss(high_difference, low_difference, high_minuend,
2695 +   low_minuend, high_subtrahend, low_subtrahend) subtracts two
2696 +   two-word unsigned integers, composed by HIGH_MINUEND_1 and
2697 +   LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and LOW_SUBTRAHEND_2
2698 +   respectively.  The result is placed in HIGH_DIFFERENCE and
2699 +   LOW_DIFFERENCE.  Overflow (i.e. carry out) is not stored anywhere,
2700 +   and is lost.
2701 +
2702 +   If any of these macros are left undefined for a particular CPU,
2703 +   C macros are used.  */
2704 +
2705 +#if defined (__arm__)
2706 +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
2707 +  __asm__ ("adds       %1, %4, %5                                      \n\
2708 +       adc     %0, %2, %3"                                             \
2709 +          : "=r" ((USItype) (sh)),                                     \
2710 +            "=&r" ((USItype) (sl))                                     \
2711 +          : "%r" ((USItype) (ah)),                                     \
2712 +            "rI" ((USItype) (bh)),                                     \
2713 +            "%r" ((USItype) (al)),                                     \
2714 +            "rI" ((USItype) (bl)))
2715 +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
2716 +  __asm__ ("subs       %1, %4, %5                                      \n\
2717 +       sbc     %0, %2, %3"                                             \
2718 +          : "=r" ((USItype) (sh)),                                     \
2719 +            "=&r" ((USItype) (sl))                                     \
2720 +          : "r" ((USItype) (ah)),                                      \
2721 +            "rI" ((USItype) (bh)),                                     \
2722 +            "r" ((USItype) (al)),                                      \
2723 +            "rI" ((USItype) (bl)))
2724 +#define umul_ppmm(xh, xl, a, b)                                         \
2725 +  __asm__ ("%@ Inlined umul_ppmm\n"                                     \
2726 +           "umull %r1, %r0, %r2, %r3"                                   \
2727 +                   : "=&r" ((USItype)(xh)),                             \
2728 +                     "=r" ((USItype)(xl))                               \
2729 +                   : "r" ((USItype)(a)),                                \
2730 +                     "r" ((USItype)(b))                                 \
2731 +                   : "r0", "r1")
2732 +#define count_leading_zeros(count, x)                                   \
2733 +  __asm__ ("clz %0, %1" : "=r"(count) : "r"(x))
2734 +#define UMUL_TIME 20
2735 +#define UDIV_TIME 100
2736 +#endif /* __arm__ */
2737 +
2738 +#define __umulsidi3(u, v) \
2739 +  ({DIunion __w;                                                       \
2740 +    umul_ppmm (__w.s.high, __w.s.low, u, v);                           \
2741 +    __w.ll; })
2742 +
2743 +#define __udiv_qrnnd_c(q, r, n1, n0, d) \
2744 +  do {                                                                 \
2745 +    USItype __d1, __d0, __q1, __q0;                                    \
2746 +    USItype __r1, __r0, __m;                                           \
2747 +    __d1 = __ll_highpart (d);                                          \
2748 +    __d0 = __ll_lowpart (d);                                           \
2749 +                                                                       \
2750 +    __r1 = (n1) % __d1;                                                        \
2751 +    __q1 = (n1) / __d1;                                                        \
2752 +    __m = (USItype) __q1 * __d0;                                       \
2753 +    __r1 = __r1 * __ll_B | __ll_highpart (n0);                         \
2754 +    if (__r1 < __m)                                                    \
2755 +      {                                                                        \
2756 +       __q1--, __r1 += (d);                                            \
2757 +       if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
2758 +         if (__r1 < __m)                                               \
2759 +           __q1--, __r1 += (d);                                        \
2760 +      }                                                                        \
2761 +    __r1 -= __m;                                                       \
2762 +                                                                       \
2763 +    __r0 = __r1 % __d1;                                                        \
2764 +    __q0 = __r1 / __d1;                                                        \
2765 +    __m = (USItype) __q0 * __d0;                                       \
2766 +    __r0 = __r0 * __ll_B | __ll_lowpart (n0);                          \
2767 +    if (__r0 < __m)                                                    \
2768 +      {                                                                        \
2769 +       __q0--, __r0 += (d);                                            \
2770 +       if (__r0 >= (d))                                                \
2771 +         if (__r0 < __m)                                               \
2772 +           __q0--, __r0 += (d);                                        \
2773 +      }                                                                        \
2774 +    __r0 -= __m;                                                       \
2775 +                                                                       \
2776 +    (q) = (USItype) __q1 * __ll_B | __q0;                              \
2777 +    (r) = __r0;                                                                \
2778 +  } while (0)
2779 +
2780 +#define UDIV_NEEDS_NORMALIZATION 1
2781 +#define udiv_qrnnd __udiv_qrnnd_c
2782 --- /dev/null
2783 +++ b/arch/arm/mach-bcm2708/Kconfig
2784 @@ -0,0 +1,25 @@
2785 +menu "Broadcom BCM2708 Implementations"
2786 +       depends on ARCH_BCM2708
2787 +
2788 +config MACH_BCM2708
2789 +       bool "Broadcom BCM2708 Development Platform"
2790 +       select CPU_V6
2791 +       help
2792 +         Include support for the Broadcom(R) BCM2708 platform.
2793 +
2794 +config BCM2708_GPIO
2795 +       bool "BCM2708 gpio support"
2796 +       depends on MACH_BCM2708
2797 +       select ARCH_REQUIRE_GPIOLIB
2798 +        default y
2799 +       help
2800 +         Include support for the Broadcom(R) BCM2708 gpio.
2801 +
2802 +config BCM2708_VCMEM
2803 +       bool "Videocore Memory"
2804 +       depends on MACH_BCM2708
2805 +        default y
2806 +        help
2807 +          Helper for videocore memory access and total size allocation.
2808 +
2809 +endmenu
2810 --- /dev/null
2811 +++ b/arch/arm/mach-bcm2708/Makefile
2812 @@ -0,0 +1,8 @@
2813 +#
2814 +# Makefile for the linux kernel.
2815 +#
2816 +
2817 +obj-$(CONFIG_MACH_BCM2708)     += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o
2818 +obj-$(CONFIG_BCM2708_GPIO)     += bcm2708_gpio.o
2819 +obj-$(CONFIG_BCM2708_VCMEM)    += vc_mem.o
2820 +
2821 --- /dev/null
2822 +++ b/arch/arm/mach-bcm2708/Makefile.boot
2823 @@ -0,0 +1,3 @@
2824 +   zreladdr-y  := 0x00008000
2825 +params_phys-y  := 0x00000100
2826 +initrd_phys-y  := 0x00800000
2827 --- /dev/null
2828 +++ b/arch/arm/mach-bcm2708/armctrl.c
2829 @@ -0,0 +1,399 @@
2830 +/*
2831 + *  linux/arch/arm/mach-bcm2708/armctrl.c
2832 + *
2833 + *  Copyright (C) 2010 Broadcom
2834 + *
2835 + * This program is free software; you can redistribute it and/or modify
2836 + * it under the terms of the GNU General Public License as published by
2837 + * the Free Software Foundation; either version 2 of the License, or
2838 + * (at your option) any later version.
2839 + *
2840 + * This program is distributed in the hope that it will be useful,
2841 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2842 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2843 + * GNU General Public License for more details.
2844 + *
2845 + * You should have received a copy of the GNU General Public License
2846 + * along with this program; if not, write to the Free Software
2847 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2848 + */
2849 +#include <linux/init.h>
2850 +#include <linux/list.h>
2851 +#include <linux/io.h>
2852 +#include <linux/version.h>
2853 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,39)
2854 +#include <linux/syscore_ops.h>
2855 +#else
2856 +#include <linux/sysdev.h>
2857 +#endif
2858 +#include <linux/interrupt.h>
2859 +
2860 +#include <asm/mach/irq.h>
2861 +#include <mach/hardware.h>
2862 +#include "armctrl.h"
2863 +
2864 +/* For support of kernels >= 3.0 assume only one VIC for now*/
2865 +static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
2866 +       INTERRUPT_VC_JPEG,
2867 +       INTERRUPT_VC_USB,
2868 +       INTERRUPT_VC_3D,
2869 +       INTERRUPT_VC_DMA2,
2870 +       INTERRUPT_VC_DMA3,
2871 +       INTERRUPT_VC_I2C,
2872 +       INTERRUPT_VC_SPI,
2873 +       INTERRUPT_VC_I2SPCM,
2874 +       INTERRUPT_VC_SDIO,
2875 +       INTERRUPT_VC_UART,
2876 +       INTERRUPT_VC_ARASANSDIO
2877 +};
2878 +
2879 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
2880 +static void armctrl_mask_irq(struct irq_data *d)
2881 +#else
2882 +static void armctrl_mask_irq(unsigned int irq)
2883 +#endif
2884 +{
2885 +       static const unsigned int disables[4] = {
2886 +               IO_ADDRESS(ARM_IRQ_DIBL1),
2887 +               IO_ADDRESS(ARM_IRQ_DIBL2),
2888 +               IO_ADDRESS(ARM_IRQ_DIBL3),
2889 +               0
2890 +       };
2891 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
2892 +       unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
2893 +#else
2894 +       unsigned int data = (unsigned int)get_irq_chip_data(irq);
2895 +#endif
2896 +       writel(1 << (data & 0x1f), __io(disables[(data >> 5) & 0x3]));
2897 +}
2898 +
2899 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
2900 +static void armctrl_unmask_irq(struct irq_data *d)
2901 +#else
2902 +static void armctrl_unmask_irq(unsigned int irq)
2903 +#endif
2904 +{
2905 +       static const unsigned int enables[4] = {
2906 +               IO_ADDRESS(ARM_IRQ_ENBL1),
2907 +               IO_ADDRESS(ARM_IRQ_ENBL2),
2908 +               IO_ADDRESS(ARM_IRQ_ENBL3),
2909 +               0
2910 +       };
2911 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
2912 +       unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
2913 +#else
2914 +       unsigned int data = (unsigned int)get_irq_chip_data(irq);
2915 +#endif
2916 +       writel(1 << (data & 0x1f), __io(enables[(data >> 5) & 0x3]));
2917 +}
2918 +
2919 +#if defined(CONFIG_PM)
2920 +
2921 +/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
2922 +
2923 +/* Static defines
2924 + * struct armctrl_device - VIC PM device (< 3.xx)
2925 + * @sysdev: The system device which is registered. (< 3.xx)
2926 + * @irq: The IRQ number for the base of the VIC.
2927 + * @base: The register base for the VIC.
2928 + * @resume_sources: A bitmask of interrupts for resume.
2929 + * @resume_irqs: The IRQs enabled for resume.
2930 + * @int_select: Save for VIC_INT_SELECT.
2931 + * @int_enable: Save for VIC_INT_ENABLE.
2932 + * @soft_int: Save for VIC_INT_SOFT.
2933 + * @protect: Save for VIC_PROTECT.
2934 + */
2935 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,39)
2936 +struct armctrl_device {
2937 +       struct sys_device sysdev;
2938 +#else
2939 +       struct armctrl_info {
2940 +#endif
2941 +               void __iomem *base;
2942 +               int irq;
2943 +               u32 resume_sources;
2944 +               u32 resume_irqs;
2945 +               u32 int_select;
2946 +               u32 int_enable;
2947 +               u32 soft_int;
2948 +               u32 protect;
2949 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,39)
2950 +};
2951 +#else
2952 +       } armctrl;
2953 +#endif
2954 +
2955 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,39)
2956 +
2957 +static struct armctrl_device armctrl_devices[1];
2958 +
2959 +static inline struct armctrl_device *to_vic(struct sys_device *sys)
2960 +{
2961 +       return container_of(sys, struct armctrl_device, sysdev);
2962 +}
2963 +
2964 +static int armctrl_id;
2965 +
2966 +static int armctrl_class_resume(struct sys_device *dev)
2967 +{
2968 +#if 0  // FIXME
2969 +       struct armctrl_device *armctrl = to_vic(dev);
2970 +       void __iomem *base = armctrl->base;
2971 +
2972 +       printk(KERN_DEBUG "%s: resuming armctrl at %p\n", __func__, base);
2973 +
2974 +       writel(armctrl->int_select, base + VIC_INT_SELECT);
2975 +       writel(armctrl->protect, base + VIC_PROTECT);
2976 +
2977 +       /* set the enabled ints and then clear the non-enabled */
2978 +       writel(armctrl->int_enable, base + VIC_INT_ENABLE);
2979 +       writel(~armctrl->int_enable, base + VIC_INT_ENABLE_CLEAR);
2980 +
2981 +       /* and the same for the soft-int register */
2982 +
2983 +       writel(armctrl->soft_int, base + VIC_INT_SOFT);
2984 +       writel(~armctrl->soft_int, base + VIC_INT_SOFT_CLEAR);
2985 +#endif
2986 +       return 0;
2987 +}
2988 +
2989 +static int armctrl_class_suspend(struct sys_device *dev, pm_message_t state)
2990 +{
2991 +#if 0                          // FIXME
2992 +       struct armctrl_device *armctrl = to_vic(dev);
2993 +       void __iomem *base = armctrl->base;
2994 +
2995 +       printk(KERN_DEBUG "%s: suspending armctrl at %p\n", __func__, base);
2996 +
2997 +       armctrl->int_select = readl(base + VIC_INT_SELECT);
2998 +       armctrl->int_enable = readl(base + VIC_INT_ENABLE);
2999 +       armctrl->soft_int = readl(base + VIC_INT_SOFT);
3000 +       armctrl->protect = readl(base + VIC_PROTECT);
3001 +
3002 +       /* set the interrupts (if any) that are used for
3003 +        * resuming the system */
3004 +
3005 +       writel(armctrl->resume_irqs, base + VIC_INT_ENABLE);
3006 +       writel(~armctrl->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
3007 +#endif
3008 +       return 0;
3009 +}
3010 +
3011 +struct sysdev_class armctrl_class = {
3012 +       .name = "armctrl",
3013 +       .suspend = armctrl_class_suspend,
3014 +       .resume = armctrl_class_resume,
3015 +};
3016 +
3017 +#endif // < 2.6.39
3018 +
3019 +static int armctrl_suspend(void)
3020 +{
3021 +       return 0;
3022 +}
3023 +
3024 +static void armctrl_resume(void)
3025 +{
3026 +       return;
3027 +}
3028 +
3029 +
3030 +/**
3031 + * armctrl_pm_register - Register a VIC for later power management control
3032 + * @base: The base address of the VIC.
3033 + * @irq: The base IRQ for the VIC.
3034 + * @resume_sources: bitmask of interrupts allowed for resume sources.
3035 + *
3036 + * For older kernels (< 3.xx) do -
3037 + * Register the VIC with the system device tree so that it can be notified
3038 + * of suspend and resume requests and ensure that the correct actions are
3039 + * taken to re-instate the settings on resume.
3040 + */
3041 +static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
3042 +                                      u32 resume_sources)
3043 +{
3044 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,39)
3045 +       struct armctrl_device *v;
3046 +
3047 +       if (armctrl_id >= ARRAY_SIZE(armctrl_devices))
3048 +               printk(KERN_ERR
3049 +                      "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n",
3050 +                      __func__);
3051 +       else {
3052 +               v = &armctrl_devices[armctrl_id];
3053 +               v->base = base;
3054 +               v->resume_sources = resume_sources;
3055 +               v->irq = irq;
3056 +               armctrl_id++;
3057 +       }
3058 +#else
3059 +       armctrl.base = base;
3060 +       armctrl.resume_sources = resume_sources;
3061 +       armctrl.irq = irq;
3062 +#endif
3063 +}
3064 +
3065 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,39)
3066 +
3067 +/**
3068 + * armctrl_pm_init - initicall to register VIC pm
3069 + *
3070 + * This is called via late_initcall() to register
3071 + * the resources for the VICs due to the early
3072 + * nature of the VIC's registration.
3073 +*/
3074 +static int __init armctrl_pm_init(void)
3075 +{
3076 +       struct armctrl_device *dev = armctrl_devices;
3077 +       int err;
3078 +       int id;
3079 +
3080 +       if (armctrl_id == 0)
3081 +               return 0;
3082 +
3083 +       err = sysdev_class_register(&armctrl_class);
3084 +       if (err) {
3085 +               printk(KERN_ERR "%s: cannot register class\n", __func__);
3086 +               return err;
3087 +       }
3088 +
3089 +       for (id = 0; id < armctrl_id; id++, dev++) {
3090 +               dev->sysdev.id = id;
3091 +               dev->sysdev.cls = &armctrl_class;
3092 +
3093 +               err = sysdev_register(&dev->sysdev);
3094 +               if (err) {
3095 +                       printk(KERN_ERR "%s: failed to register device\n",
3096 +                              __func__);
3097 +                       return err;
3098 +               }
3099 +       }
3100 +
3101 +       return 0;
3102 +}
3103 +
3104 +late_initcall(armctrl_pm_init);
3105 +
3106 +#endif // VERSION check
3107 +
3108 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
3109 +static int armctrl_set_wake(struct irq_data *d, unsigned int on)
3110 +#else
3111 +static int armctrl_set_wake(unsigned int irq, unsigned int on)
3112 +#endif
3113 +{
3114 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,39)
3115 +       struct armctrl_device *armctrl = &armctrl_devices[0];
3116 +#endif
3117 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
3118 +       unsigned int off = d->irq & 31;
3119 +#else
3120 +       unsigned int off = irq & 31;
3121 +#endif
3122 +       u32 bit = 1 << off;
3123 +
3124 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,39)
3125 +       if (!armctrl)
3126 +               return -EINVAL;
3127 +
3128 +       if (!(bit & armctrl->resume_sources))
3129 +               return -EINVAL;
3130 +
3131 +       if (on)
3132 +               armctrl->resume_irqs |= bit;
3133 +       else
3134 +               armctrl->resume_irqs &= ~bit;
3135 +#else
3136 +       if (!(bit & armctrl.resume_sources))
3137 +               return -EINVAL;
3138 +
3139 +       if (on)
3140 +               armctrl.resume_irqs |= bit;
3141 +       else
3142 +               armctrl.resume_irqs &= ~bit;
3143 +#endif
3144 +
3145 +       return 0;
3146 +}
3147 +
3148 +#else
3149 +static inline void armctrl_pm_register(void __iomem *base, unsigned int irq,
3150 +                                      u32 arg1)
3151 +{
3152 +}
3153 +#define armctrl_suspend NULL
3154 +#define armctrl_resume NULL
3155 +#define armctrl_set_wake NULL
3156 +#endif /* CONFIG_PM */
3157 +
3158 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,39)
3159 +
3160 +static struct syscore_ops armctrl_syscore_ops = {
3161 +       .suspend = armctrl_suspend,
3162 +        .resume = armctrl_resume,
3163 +};
3164 +
3165 +/**
3166 + * armctrl_syscore_init - initicall to register VIC pm functions
3167 + *
3168 + * This is called via late_initcall() to register
3169 + * the resources for the VICs due to the early
3170 + * nature of the VIC's registration.
3171 +*/
3172 +static int __init armctrl_syscore_init(void)
3173 +{
3174 +       register_syscore_ops(&armctrl_syscore_ops);
3175 +       return 0;
3176 +}
3177 +
3178 +late_initcall(armctrl_syscore_init);
3179 +
3180 +#endif
3181 +
3182 +static struct irq_chip armctrl_chip = {
3183 +       .name = "ARMCTRL",
3184 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
3185 +       .irq_ack = armctrl_mask_irq,
3186 +       .irq_mask = armctrl_mask_irq,
3187 +       .irq_unmask = armctrl_unmask_irq,
3188 +       .irq_set_wake = armctrl_set_wake,
3189 +#else
3190 +       .ack = armctrl_mask_irq,
3191 +       .mask = armctrl_mask_irq,
3192 +       .unmask = armctrl_unmask_irq,
3193 +       .set_wake = armctrl_set_wake,
3194 +#endif
3195 +};
3196 +
3197 +/**
3198 + * armctrl_init - initialise a vectored interrupt controller
3199 + * @base: iomem base address
3200 + * @irq_start: starting interrupt number, must be muliple of 32
3201 + * @armctrl_sources: bitmask of interrupt sources to allow
3202 + * @resume_sources: bitmask of interrupt sources to allow for resume
3203 + */
3204 +int __init armctrl_init(void __iomem * base, unsigned int irq_start,
3205 +                       u32 armctrl_sources, u32 resume_sources)
3206 +{
3207 +       unsigned int irq;
3208 +
3209 +       for (irq = 0; irq < NR_IRQS; irq++) {
3210 +               unsigned int data = irq;
3211 +               if (irq >= INTERRUPT_JPEG)
3212 +                       data = remap_irqs[irq - INTERRUPT_JPEG];
3213 +
3214 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
3215 +               irq_set_chip(irq, &armctrl_chip);
3216 +               irq_set_chip_data(irq, (void *)data);
3217 +               irq_set_handler(irq, handle_level_irq);
3218 +#else
3219 +               set_irq_chip(irq, &armctrl_chip);
3220 +               set_irq_chip_data(irq, (void *)data);
3221 +               set_irq_handler(irq, handle_level_irq);
3222 +#endif
3223 +               set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED);
3224 +       }
3225 +
3226 +       armctrl_pm_register(base, irq_start, resume_sources);
3227 +       return 0;
3228 +}
3229 --- /dev/null
3230 +++ b/arch/arm/mach-bcm2708/armctrl.h
3231 @@ -0,0 +1,27 @@
3232 +/*
3233 + *  linux/arch/arm/mach-bcm2708/armctrl.h
3234 + *
3235 + *  Copyright (C) 2010 Broadcom
3236 + *
3237 + * This program is free software; you can redistribute it and/or modify
3238 + * it under the terms of the GNU General Public License as published by
3239 + * the Free Software Foundation; either version 2 of the License, or
3240 + * (at your option) any later version.
3241 + *
3242 + * This program is distributed in the hope that it will be useful,
3243 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3244 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3245 + * GNU General Public License for more details.
3246 + *
3247 + * You should have received a copy of the GNU General Public License
3248 + * along with this program; if not, write to the Free Software
3249 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
3250 + */
3251 +
3252 +#ifndef __BCM2708_ARMCTRL_H
3253 +#define __BCM2708_ARMCTRL_H
3254 +
3255 +extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
3256 +                              u32 armctrl_sources, u32 resume_sources);
3257 +
3258 +#endif
3259 --- /dev/null
3260 +++ b/arch/arm/mach-bcm2708/bcm2708.c
3261 @@ -0,0 +1,657 @@
3262 +/*
3263 + *  linux/arch/arm/mach-bcm2708/bcm2708.c
3264 + *
3265 + *  Copyright (C) 2010 Broadcom
3266 + *
3267 + * This program is free software; you can redistribute it and/or modify
3268 + * it under the terms of the GNU General Public License as published by
3269 + * the Free Software Foundation; either version 2 of the License, or
3270 + * (at your option) any later version.
3271 + *
3272 + * This program is distributed in the hope that it will be useful,
3273 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3274 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3275 + * GNU General Public License for more details.
3276 + *
3277 + * You should have received a copy of the GNU General Public License
3278 + * along with this program; if not, write to the Free Software
3279 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
3280 + */
3281 +
3282 +#include <linux/init.h>
3283 +#include <linux/device.h>
3284 +#include <linux/dma-mapping.h>
3285 +#include <linux/serial_8250.h>
3286 +#include <linux/platform_device.h>
3287 +#include <linux/interrupt.h>
3288 +#include <linux/amba/bus.h>
3289 +#include <linux/amba/clcd.h>
3290 +#include <linux/clockchips.h>
3291 +#include <linux/cnt32_to_63.h>
3292 +#include <linux/io.h>
3293 +
3294 +#include <linux/version.h>
3295 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
3296 +#include <linux/clkdev.h>
3297 +#else
3298 +#include <asm/clkdev.h>
3299 +#endif
3300 +#include <asm/system.h>
3301 +#include <mach/hardware.h>
3302 +#include <asm/irq.h>
3303 +#include <linux/leds.h>
3304 +#include <asm/mach-types.h>
3305 +
3306 +#include <asm/mach/arch.h>
3307 +#include <asm/mach/flash.h>
3308 +#include <asm/mach/irq.h>
3309 +#include <asm/mach/time.h>
3310 +#include <asm/mach/map.h>
3311 +
3312 +#include <mach/timex.h>
3313 +#include <mach/dma.h>
3314 +#include <mach/vcio.h>
3315 +
3316 +#include "bcm2708.h"
3317 +#include "armctrl.h"
3318 +#include "clock.h"
3319 +
3320 +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
3321 + * give us IO access only to 64Mbytes of physical memory (26 bits).  We could
3322 + * represent this window by setting our dmamasks to 26 bits but, in fact
3323 + * we're not going to use addresses outside this range (they're not in real
3324 + * memory) so we don't bother.
3325 + *
3326 + * In the future we might include code to use this IOMMU to remap other
3327 + * physical addresses onto VideoCore memory then the use of 32-bits would be
3328 + * more legitimate.
3329 + */
3330 +#define DMA_MASK_BITS_COMMON 32
3331 +
3332 +static void __init bcm2708_init_led(void);
3333 +
3334 +void __init bcm2708_init_irq(void)
3335 +{
3336 +       armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
3337 +}
3338 +
3339 +static struct map_desc bcm2708_io_desc[] __initdata = {
3340 +       {
3341 +               .virtual        = IO_ADDRESS(ARMCTRL_BASE),
3342 +               .pfn            = __phys_to_pfn(ARMCTRL_BASE),
3343 +               .length         = SZ_4K,
3344 +               .type           = MT_DEVICE
3345 +       }, {
3346 +               .virtual        = IO_ADDRESS(UART0_BASE),
3347 +               .pfn            = __phys_to_pfn(UART0_BASE),
3348 +               .length         = SZ_4K,
3349 +               .type           = MT_DEVICE
3350 +       }, {
3351 +               .virtual        = IO_ADDRESS(UART1_BASE),
3352 +               .pfn            = __phys_to_pfn(UART1_BASE),
3353 +               .length         = SZ_4K,
3354 +               .type           = MT_DEVICE
3355 +       }, {
3356 +#ifdef CONFIG_MMC_BCM2708 /* broadcom legacy SD */
3357 +               .virtual        = IO_ADDRESS(MMCI0_BASE),
3358 +               .pfn            = __phys_to_pfn(MMCI0_BASE),
3359 +               .length         = SZ_4K,
3360 +               .type           = MT_DEVICE
3361 +       }, {
3362 +#endif
3363 +               .virtual        = IO_ADDRESS(DMA_BASE),
3364 +               .pfn            = __phys_to_pfn(DMA_BASE),
3365 +               .length         = SZ_4K,
3366 +               .type           = MT_DEVICE
3367 +       }, {
3368 +               .virtual        = IO_ADDRESS(MCORE_BASE),
3369 +               .pfn            = __phys_to_pfn(MCORE_BASE),
3370 +               .length         = SZ_4K,
3371 +               .type           = MT_DEVICE
3372 +       }, {
3373 +               .virtual        = IO_ADDRESS(ST_BASE),
3374 +               .pfn            = __phys_to_pfn(ST_BASE),
3375 +               .length         = SZ_4K,
3376 +               .type           = MT_DEVICE
3377 +        }, {
3378 +               .virtual        = IO_ADDRESS(USB_BASE),
3379 +               .pfn            = __phys_to_pfn(USB_BASE),
3380 +               .length         = SZ_128K,
3381 +               .type           = MT_DEVICE
3382 +        }, {
3383 +               .virtual        = IO_ADDRESS(PM_BASE),
3384 +               .pfn            = __phys_to_pfn(PM_BASE),
3385 +               .length         = SZ_4K,
3386 +               .type           = MT_DEVICE
3387 +       }, {
3388 +               .virtual        = IO_ADDRESS(GPIO_BASE),
3389 +               .pfn            = __phys_to_pfn(GPIO_BASE),
3390 +               .length         = SZ_4K,
3391 +               .type           = MT_DEVICE
3392 +        }
3393 +};
3394 +
3395 +void __init bcm2708_map_io(void)
3396 +{
3397 +       iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
3398 +}
3399 +
3400 +unsigned long frc_clock_ticks32(void)
3401 +{
3402 +       /* STC: a free running counter that increments at the rate of 1MHz */
3403 +       return readl(__io_address(ST_BASE+0x04));
3404 +}
3405 +
3406 +unsigned long long frc_clock_ticks63(void)
3407 +{
3408 +       unsigned long t = frc_clock_ticks32();
3409 +       /* For cnt32_to_63 to work correctly we MUST call this routine
3410 +        * at least once every half-32-bit-wraparound period - that's once
3411 +        * every 35minutes or so - using it in sched_clock() should ensure this
3412 +        */
3413 +       return cnt32_to_63(t);
3414 +}
3415 +
3416 +unsigned long long sched_clock(void)
3417 +{
3418 +       return 1000ull * frc_clock_ticks63();
3419 +}
3420 +
3421 +/*
3422 + * These are fixed clocks.
3423 + */
3424 +static struct clk ref24_clk = {
3425 +       .rate   = 3000000,  /* The UART is clocked at 3MHz via APB_CLK */
3426 +};
3427 +static struct clk osc_clk = {
3428 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
3429 +       .rate   = 27000000,
3430 +#else
3431 +       .rate   = 500000000,  /* ARM clock is set from the VideoCore booter */
3432 +#endif
3433 +};
3434 +/* warning - the USB needs a clock > 34MHz */
3435 +
3436 +#ifdef CONFIG_MMC_BCM2708
3437 +static struct clk sdhost_clk = {
3438 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
3439 +       .rate   =   4000000, /* 4MHz */
3440 +#else
3441 +       .rate   = 250000000, /* 250MHz */
3442 +#endif
3443 +};
3444 +#endif
3445 +
3446 +static struct clk_lookup lookups[] = {
3447 +       {       /* UART0 */
3448 +               .dev_id         = "dev:f1",
3449 +               .clk            = &ref24_clk,
3450 +       },
3451 +       {       /* USB */
3452 +               .dev_id         = "bcm2708_usb",
3453 +               .clk            = &osc_clk,
3454 +#ifdef CONFIG_MMC_BCM2708
3455 +       },
3456 +       {       /* MCI */
3457 +               .dev_id         = "bcm2708_mci.0",
3458 +               .clk            = &sdhost_clk,
3459 +#endif
3460 +       }
3461 +};
3462 +
3463 +
3464 +#define UART0_IRQ      { IRQ_UART, NO_IRQ }
3465 +#define UART0_DMA      { 15, 14 }
3466 +
3467 +AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
3468 +
3469 +static struct amba_device *amba_devs[] __initdata = {
3470 +       &uart0_device,
3471 +};
3472 +
3473 +static struct resource bcm2708_dmaman_resources[] = {
3474 +       {
3475 +               .start                  = DMA_BASE,
3476 +               .end                    = DMA_BASE + SZ_4K - 1,
3477 +               .flags                  = IORESOURCE_MEM,
3478 +       }
3479 +};
3480 +
3481 +static struct platform_device bcm2708_dmaman_device = {
3482 +   .name                       = BCM_DMAMAN_DRIVER_NAME,
3483 +       .id                     = 0, /* first bcm2708_dma */
3484 +       .resource               = bcm2708_dmaman_resources,
3485 +       .num_resources          = ARRAY_SIZE(bcm2708_dmaman_resources),
3486 +};
3487 +
3488 +#ifdef CONFIG_MMC_BCM2708
3489 +static struct resource bcm2708_mci_resources[] = {
3490 +       {
3491 +               .start                  = MMCI0_BASE,
3492 +               .end                    = MMCI0_BASE + SZ_4K - 1,
3493 +               .flags                  = IORESOURCE_MEM,
3494 +       }, {
3495 +               .start                  = IRQ_SDIO,
3496 +               .end                    = IRQ_SDIO,
3497 +               .flags                  = IORESOURCE_IRQ,
3498 +       }
3499 +};
3500 +
3501 +
3502 +static struct platform_device bcm2708_mci_device = {
3503 +       .name                   = "bcm2708_mci",
3504 +       .id                     = 0, /* first bcm2708_mci */
3505 +       .resource               = bcm2708_mci_resources,
3506 +       .num_resources          = ARRAY_SIZE(bcm2708_mci_resources),
3507 +       .dev                    = {
3508 +       .coherent_dma_mask      = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3509 +       },
3510 +};
3511 +#endif /* CONFIG_MMC_BCM2708 */
3512 +
3513 +
3514 +static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3515 +
3516 +static struct platform_device bcm2708_fb_device = {
3517 +       .name                   = "bcm2708_fb",
3518 +       .id                     = -1,  /* only one bcm2708_fb */
3519 +       .resource               = NULL,
3520 +       .num_resources          = 0,
3521 +       .dev                    = {
3522 +               .dma_mask               = &fb_dmamask,
3523 +               .coherent_dma_mask      = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3524 +       },
3525 +};
3526 +
3527 +static struct plat_serial8250_port bcm2708_uart1_platform_data[] = {
3528 +       {
3529 +               .mapbase        = UART1_BASE + 0x40,
3530 +               .irq            = IRQ_AUX,
3531 +               .uartclk        = 125000000,
3532 +               .regshift       = 2,
3533 +               .iotype         = UPIO_MEM,
3534 +               .flags          = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST,
3535 +               .type           = PORT_8250,
3536 +       },
3537 +       { },
3538 +};
3539 +
3540 +static struct platform_device bcm2708_uart1_device = {
3541 +       .name                   = "serial8250",
3542 +       .id                     = PLAT8250_DEV_PLATFORM,
3543 +       .dev                    = {
3544 +               .platform_data  = bcm2708_uart1_platform_data,
3545 +       },
3546 +};
3547 +
3548 +static struct resource bcm2708_usb_resources[] = {
3549 +       [0] =   {
3550 +               .start                  = USB_BASE,
3551 +               .end                    = USB_BASE + SZ_128K - 1,
3552 +               .flags                  = IORESOURCE_MEM,
3553 +               },
3554 +       [1] =   {
3555 +               .start                  = IRQ_USB,
3556 +               .end                    = IRQ_USB,
3557 +               .flags                  = IORESOURCE_IRQ,
3558 +               },
3559 +};
3560 +
3561 +static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3562 +
3563 +static struct platform_device bcm2708_usb_device = {
3564 +       .name                   = "bcm2708_usb",
3565 +       .id                     = -1, /* only one bcm2708_usb */
3566 +       .resource               = bcm2708_usb_resources,
3567 +       .num_resources          = ARRAY_SIZE(bcm2708_usb_resources),
3568 +       .dev                    = {
3569 +               .dma_mask               = &usb_dmamask,
3570 +               .coherent_dma_mask      = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3571 +       },
3572 +};
3573 +
3574 +static struct resource bcm2708_vcio_resources[] = {
3575 +       [0] =   {                       /* mailbox/semaphore/doorbell access */
3576 +               .start                  = MCORE_BASE,
3577 +               .end                    = MCORE_BASE + SZ_4K - 1,
3578 +               .flags                  = IORESOURCE_MEM,
3579 +       },
3580 +};
3581 +
3582 +static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3583 +
3584 +static struct platform_device bcm2708_vcio_device = {
3585 +       .name                   = BCM_VCIO_DRIVER_NAME,
3586 +       .id                     = -1, /* only one VideoCore I/O area */
3587 +       .resource               = bcm2708_vcio_resources,
3588 +       .num_resources          = ARRAY_SIZE(bcm2708_vcio_resources),
3589 +       .dev                    = {
3590 +               .dma_mask               = &vcio_dmamask,
3591 +               .coherent_dma_mask      = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3592 +       },
3593 +};
3594 +
3595 +#ifdef CONFIG_BCM2708_GPIO
3596 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
3597 +
3598 +static struct resource bcm2708_gpio_resources[] = {
3599 +       [0] =   {                       /* general purpose I/O */
3600 +               .start                  = GPIO_BASE,
3601 +               .end                    = GPIO_BASE + SZ_4K - 1,
3602 +               .flags                  = IORESOURCE_MEM,
3603 +       },
3604 +};
3605 +
3606 +static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3607 +
3608 +static struct platform_device bcm2708_gpio_device = {
3609 +       .name                   = BCM_GPIO_DRIVER_NAME,
3610 +       .id                     = -1, /* only one VideoCore I/O area */
3611 +       .resource               = bcm2708_gpio_resources,
3612 +       .num_resources          = ARRAY_SIZE(bcm2708_gpio_resources),
3613 +       .dev                    = {
3614 +               .dma_mask               = &gpio_dmamask,
3615 +               .coherent_dma_mask      = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3616 +       },
3617 +};
3618 +#endif
3619 +
3620 +#ifdef CONFIG_BCM2708_BUTTONS
3621 +static struct resource bcm2708_vcbuttons_resources[] = {
3622 +};
3623 +
3624 +static u64 vcbuttons_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3625 +
3626 +static struct platform_device bcm2708_vcbuttons_device = {
3627 +       .name                   = "bcm2708_vcbuttons",
3628 +       .id                     = -1, /* only one VideoCore I/O area */
3629 +       .resource               = bcm2708_vcbuttons_resources,
3630 +       .num_resources          = ARRAY_SIZE(bcm2708_vcbuttons_resources),
3631 +       .dev                    = {
3632 +               .dma_mask               = &vcbuttons_dmamask,
3633 +               .coherent_dma_mask      = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3634 +       },
3635 +};
3636 +#endif
3637 +
3638 +#ifdef CONFIG_BCM2708_TOUCHSCREEN
3639 +static struct resource bcm2708_vctouch_resources[] = {
3640 +};
3641 +
3642 +static u64 vctouch_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3643 +
3644 +static struct platform_device bcm2708_vctouch_device = {
3645 +       .name                   = "bcm2708_vctouch",
3646 +       .id                     = -1, /* only one VideoCore I/O area */
3647 +       .resource               = bcm2708_vctouch_resources,
3648 +       .num_resources          = ARRAY_SIZE(bcm2708_vctouch_resources),
3649 +       .dev                    = {
3650 +               .dma_mask               = &vctouch_dmamask,
3651 +               .coherent_dma_mask      = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3652 +       },
3653 +};
3654 +#endif
3655 +
3656 +static struct resource bcm2708_systemtimer_resources[] = {
3657 +       [0] =   {                       /* system timer access */
3658 +               .start                  = ST_BASE,
3659 +               .end                    = ST_BASE + SZ_4K - 1,
3660 +               .flags                  = IORESOURCE_MEM,
3661 +       }, {
3662 +               .start                  = IRQ_TIMER3,
3663 +               .end                    = IRQ_TIMER3,
3664 +               .flags                  = IORESOURCE_IRQ,
3665 +       }
3666 +
3667 +
3668 +};
3669 +
3670 +static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3671 +
3672 +static struct platform_device bcm2708_systemtimer_device = {
3673 +       .name                   = "bcm2708_systemtimer",
3674 +       .id                     = -1, /* only one VideoCore I/O area */
3675 +       .resource               = bcm2708_systemtimer_resources,
3676 +       .num_resources          = ARRAY_SIZE(bcm2708_systemtimer_resources),
3677 +       .dev                    = {
3678 +               .dma_mask               = &systemtimer_dmamask,
3679 +               .coherent_dma_mask      = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3680 +       },
3681 +};
3682 +
3683 +#ifdef CONFIG_MMC_SDHCI_BCM2708 /* Arasan emmc SD */
3684 +static struct resource bcm2708_emmc_resources[] = {
3685 +       [0] = {
3686 +               .start = EMMC_BASE,
3687 +               .end   = EMMC_BASE + SZ_256 - 1, /* we only need this area */
3688 +               /* the memory map actually makes SZ_4K available  */
3689 +               .flags = IORESOURCE_MEM,
3690 +       },
3691 +       [1] = {
3692 +               .start = IRQ_ARASANSDIO,
3693 +               .end   = IRQ_ARASANSDIO,
3694 +               .flags = IORESOURCE_IRQ,
3695 +       },
3696 +};
3697 +
3698 +static u64 bcm2708_emmc_dmamask = 0xffffffffUL;
3699 +
3700 +struct platform_device bcm2708_emmc_device = {
3701 +       .name           = "bcm2708_sdhci",
3702 +       .id             = 0,
3703 +       .num_resources  = ARRAY_SIZE(bcm2708_emmc_resources),
3704 +       .resource       = bcm2708_emmc_resources,
3705 +       .dev            = {
3706 +               .dma_mask               = &bcm2708_emmc_dmamask,
3707 +               .coherent_dma_mask      = 0xffffffffUL
3708 +       },
3709 +};
3710 +#endif /* CONFIG_MMC_SDHCI_BCM2708 */
3711 +
3712 +static struct resource bcm2708_powerman_resources[] = {
3713 +       [0] = {
3714 +               .start = PM_BASE,
3715 +               .end   = PM_BASE + SZ_256 - 1,
3716 +               .flags = IORESOURCE_MEM,
3717 +       },
3718 +};
3719 +
3720 +static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3721 +
3722 +struct platform_device bcm2708_powerman_device = {
3723 +       .name           = "bcm2708_powerman",
3724 +       .id             = 0,
3725 +       .num_resources  = ARRAY_SIZE(bcm2708_powerman_resources),
3726 +       .resource       = bcm2708_powerman_resources,
3727 +       .dev            = {
3728 +               .dma_mask     = &powerman_dmamask,
3729 +               .coherent_dma_mask = 0xffffffffUL
3730 +       },
3731 +};
3732 +
3733 +int __init bcm_register_device(struct platform_device *pdev)
3734 +{
3735 +       int ret;
3736 +
3737 +       ret = platform_device_register(pdev);
3738 +       if (ret)
3739 +               pr_debug("Unable to register platform device '%s': %d\n",
3740 +                        pdev->name, ret);
3741 +
3742 +       return ret;
3743 +}
3744 +
3745 +void __init bcm2708_init(void)
3746 +{
3747 +       int i;
3748 +
3749 +       for (i = 0; i < ARRAY_SIZE(lookups); i++)
3750 +               clkdev_add(&lookups[i]);
3751 +
3752 +       bcm_register_device(&bcm2708_dmaman_device);
3753 +       bcm_register_device(&bcm2708_vcio_device);
3754 +#ifdef CONFIG_BCM2708_GPIO
3755 +       bcm_register_device(&bcm2708_gpio_device);
3756 +#endif
3757 +       bcm_register_device(&bcm2708_systemtimer_device);
3758 +#ifdef CONFIG_MMC_BCM2708
3759 +       bcm_register_device(&bcm2708_mci_device);
3760 +#endif
3761 +       bcm_register_device(&bcm2708_fb_device);
3762 +       bcm_register_device(&bcm2708_usb_device);
3763 +       bcm_register_device(&bcm2708_uart1_device);
3764 +#ifdef CONFIG_BCM2708_BUTTONS
3765 +       bcm_register_device(&bcm2708_vcbuttons_device);
3766 +#endif
3767 +#ifdef CONFIG_BCM2708_TOUCHSCREEN
3768 +       bcm_register_device(&bcm2708_vctouch_device);
3769 +#endif
3770 +       bcm_register_device(&bcm2708_powerman_device);
3771 +#ifdef CONFIG_MMC_SDHCI_BCM2708
3772 +       bcm_register_device(&bcm2708_emmc_device);
3773 +#endif
3774 +        bcm2708_init_led();
3775 +#ifdef CONFIG_BCM2708_VCMEM
3776 +{
3777 +       extern void vc_mem_connected_init(void);
3778 +        vc_mem_connected_init();
3779 +}
3780 +#endif
3781 +       for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
3782 +               struct amba_device *d = amba_devs[i];
3783 +               amba_device_register(d, &iomem_resource);
3784 +       }
3785 +}
3786 +
3787 +#define TIMER_PERIOD 10000 /* HZ in microsecs */
3788 +
3789 +static void timer_set_mode(enum clock_event_mode mode,
3790 +                          struct clock_event_device *clk)
3791 +{
3792 +       unsigned long stc;
3793 +
3794 +       switch (mode) {
3795 +       case CLOCK_EVT_MODE_PERIODIC:
3796 +               stc = readl(__io_address(ST_BASE+0x04));
3797 +               writel(stc + TIMER_PERIOD,
3798 +                       __io_address(ST_BASE+0x18));/* stc3 */
3799 +               break;
3800 +       case CLOCK_EVT_MODE_ONESHOT:
3801 +       case CLOCK_EVT_MODE_UNUSED:
3802 +       case CLOCK_EVT_MODE_SHUTDOWN:
3803 +       default:
3804 +               printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
3805 +                       (int)mode);
3806 +               break;
3807 +       }
3808 +
3809 +}
3810 +
3811 +static int timer_set_next_event(unsigned long evt,
3812 +                               struct clock_event_device *unused)
3813 +{
3814 +       unsigned long stc;
3815 +
3816 +        stc = readl(__io_address(ST_BASE + 0x04));
3817 +        writel(stc + TIMER_PERIOD, __io_address(ST_BASE+0x18)); /* stc3 */
3818 +       return 0;
3819 +}
3820 +
3821 +static struct clock_event_device timer0_clockevent =    {
3822 +       .name           = "timer0",
3823 +       .shift          = 32,
3824 +       .features       = CLOCK_EVT_FEAT_ONESHOT,
3825 +       .set_mode       = timer_set_mode,
3826 +       .set_next_event = timer_set_next_event,
3827 +};
3828 +
3829 +/*
3830 + * IRQ handler for the timer
3831 + */
3832 +static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id)
3833 +{
3834 +       struct clock_event_device *evt = &timer0_clockevent;
3835 +
3836 +       writel(1<<3, __io_address(ST_BASE+0x00)); /* stcs clear timer int */
3837 +
3838 +       evt->event_handler(evt);
3839 +
3840 +       return IRQ_HANDLED;
3841 +}
3842 +
3843 +static struct irqaction bcm2708_timer_irq = {
3844 +       .name           = "BCM2708 Timer Tick",
3845 +       .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
3846 +       .handler        = bcm2708_timer_interrupt,
3847 +};
3848 +
3849 +/*
3850 + * Set up timer interrupt, and return the current time in seconds.
3851 + */
3852 +static void __init bcm2708_timer_init(void)
3853 +{
3854 +       /*
3855 +        * Initialise to a known state (all timers off)
3856 +        */
3857 +       writel(0, __io_address(ARM_T_CONTROL));
3858 +       /*
3859 +        * Make irqs happen for the system timer
3860 +        */
3861 +       setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
3862 +
3863 +       timer0_clockevent.mult =
3864 +               div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
3865 +       timer0_clockevent.max_delta_ns =
3866 +               clockevent_delta2ns(0xffffffff, &timer0_clockevent);
3867 +       timer0_clockevent.min_delta_ns =
3868 +               clockevent_delta2ns(0xf, &timer0_clockevent);
3869 +
3870 +       timer0_clockevent.cpumask = cpumask_of(0);
3871 +       clockevents_register_device(&timer0_clockevent);
3872 +}
3873 +
3874 +struct sys_timer bcm2708_timer = {
3875 +       .init           = bcm2708_timer_init,
3876 +};
3877 +
3878 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
3879 +#include <linux/leds.h>
3880 +
3881 +static struct gpio_led bcm2708_leds[] = {
3882 +       [0] = {
3883 +               .gpio                   = 16,
3884 +               .name                   = "led0",
3885 +               .default_trigger        = "mmc0",
3886 +               .active_low             = 0,
3887 +       },
3888 +};
3889 +
3890 +static struct gpio_led_platform_data bcm2708_led_pdata = {
3891 +       .num_leds       = ARRAY_SIZE(bcm2708_leds),
3892 +       .leds           = bcm2708_leds,
3893 +};
3894 +
3895 +static struct platform_device bcm2708_led_device = {
3896 +       .name           = "leds-gpio",
3897 +       .id             = -1,
3898 +       .dev            = {
3899 +               .platform_data  = &bcm2708_led_pdata,
3900 +       },
3901 +};
3902 +
3903 +static void __init bcm2708_init_led(void)
3904 +{
3905 +       platform_device_register(&bcm2708_led_device);
3906 +}
3907 +#else
3908 +static inline void bcm2708_init_led(void) {}
3909 +#endif
3910 +
3911 +
3912 +MACHINE_START(BCM2708, "BCM2708")
3913 +       /* Maintainer: Broadcom Europe Ltd. */
3914 +       .map_io         = bcm2708_map_io,
3915 +       .init_irq       = bcm2708_init_irq,
3916 +       .timer          = &bcm2708_timer,
3917 +       .init_machine   = bcm2708_init,
3918 +MACHINE_END
3919 --- /dev/null
3920 +++ b/arch/arm/mach-bcm2708/bcm2708.h
3921 @@ -0,0 +1,51 @@
3922 +/*
3923 + * linux/arch/arm/mach-bcm2708/bcm2708.h
3924 + *
3925 + * BCM2708 machine support header
3926 + *
3927 + *  Copyright (C) 2010 Broadcom
3928 + *
3929 + * This program is free software; you can redistribute it and/or modify
3930 + * it under the terms of the GNU General Public License as published by
3931 + * the Free Software Foundation; either version 2 of the License, or
3932 + * (at your option) any later version.
3933 + *
3934 + * This program is distributed in the hope that it will be useful,
3935 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3936 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3937 + * GNU General Public License for more details.
3938 + *
3939 + * You should have received a copy of the GNU General Public License
3940 + * along with this program; if not, write to the Free Software
3941 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
3942 + */
3943 +
3944 +#ifndef __BCM2708_BCM2708_H
3945 +#define __BCM2708_BCM2708_H
3946 +
3947 +#include <linux/amba/bus.h>
3948 +
3949 +extern void __init bcm2708_init(void);
3950 +extern void __init bcm2708_init_irq(void);
3951 +extern void __init bcm2708_map_io(void);
3952 +extern struct sys_timer bcm2708_timer;
3953 +extern unsigned int mmc_status(struct device *dev);
3954 +
3955 +#define AMBA_DEVICE(name, busid, base, plat)                   \
3956 +static struct amba_device name##_device = {                    \
3957 +       .dev            = {                                     \
3958 +               .coherent_dma_mask = ~0,                        \
3959 +               .init_name = busid,                             \
3960 +               .platform_data = plat,                          \
3961 +       },                                                      \
3962 +       .res            = {                                     \
3963 +               .start  = base##_BASE,          \
3964 +               .end    = (base##_BASE) + SZ_4K - 1,\
3965 +               .flags  = IORESOURCE_MEM,                       \
3966 +       },                                                      \
3967 +       .dma_mask       = ~0,                                   \
3968 +       .irq            = base##_IRQ,                           \
3969 +       /* .dma         = base##_DMA,*/                         \
3970 +}
3971 +
3972 +#endif
3973 --- /dev/null
3974 +++ b/arch/arm/mach-bcm2708/bcm2708_gpio.c
3975 @@ -0,0 +1,323 @@
3976 +/*
3977 + *  linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
3978 + *
3979 + *  Copyright (C) 2010 Broadcom
3980 + *
3981 + * This program is free software; you can redistribute it and/or modify
3982 + * it under the terms of the GNU General Public License version 2 as
3983 + * published by the Free Software Foundation.
3984 + *
3985 + */
3986 +
3987 +#include <linux/spinlock.h>
3988 +#include <linux/module.h>
3989 +#include <linux/list.h>
3990 +#include <linux/io.h>
3991 +#include <linux/irq.h>
3992 +#include <linux/slab.h>
3993 +#include <linux/gpio.h>
3994 +#include <linux/platform_device.h>
3995 +#include <mach/platform.h>
3996 +#include <mach/gpio.h>
3997 +
3998 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
3999 +#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
4000 +#define BCM_GPIO_USE_IRQ 0
4001 +
4002 +#define GPIOFSEL(x)  (0x00+(x)*4)
4003 +#define GPIOSET(x)   (0x1c+(x)*4)
4004 +#define GPIOCLR(x)   (0x28+(x)*4)
4005 +#define GPIOLEV(x)   (0x34+(x)*4)
4006 +#define GPIOEDS(x)   (0x40+(x)*4)
4007 +#define GPIOREN(x)   (0x4c+(x)*4)
4008 +#define GPIOFEN(x)   (0x58+(x)*4)
4009 +#define GPIOHEN(x)   (0x64+(x)*4)
4010 +#define GPIOLEN(x)   (0x70+(x)*4)
4011 +#define GPIOAREN(x)  (0x7c+(x)*4)
4012 +#define GPIOAFEN(x)  (0x88+(x)*4)
4013 +#define GPIOUD(x)    (0x94+(x)*4)
4014 +#define GPIOUDCLK(x) (0x98+(x)*4)
4015 +
4016 +enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
4017 +       GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
4018 +       GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
4019 +       GPIO_FSEL_ALT2, GPIO_FSEL_ALT3, };
4020 +
4021 +       /* Each of the two spinlocks protects a different set of hardware
4022 +        * regiters and data structurs. This decouples the code of the IRQ from
4023 +        * the GPIO code. This also makes the case of a GPIO routine call from
4024 +        * the IRQ code simpler.
4025 +        */
4026 +static DEFINE_SPINLOCK(lock);          /* GPIO registers */
4027 +static DEFINE_SPINLOCK(irq_lock);      /* IRQ registers */
4028 +
4029 +
4030 +struct bcm2708_gpio {
4031 +       /* We use a list of bcm2708_gpio structs for each trigger IRQ in the main
4032 +        * interrupts controller of the system. We need this to support systems
4033 +        * in which more that one bcm2708s are connected to the same IRQ. The ISR
4034 +        * interates through this list to find the source of the interrupt.
4035 +        */
4036 +       struct list_head        list;
4037 +
4038 +       void __iomem            *base;
4039 +       unsigned                irq_base;
4040 +        struct gpio_chip        gc;
4041 +};
4042 +
4043 +static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset, int function)
4044 +{
4045 +       struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
4046 +       unsigned long flags;
4047 +       unsigned gpiodir;
4048 +        unsigned gpio_bank = offset/10;
4049 +        unsigned gpio_field_offset = (offset - 10*gpio_bank) * 3;
4050 +
4051 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
4052 +       if (offset >= ARCH_NR_GPIOS)
4053 +               return -EINVAL;
4054 +
4055 +       spin_lock_irqsave(&lock, flags);
4056 +
4057 +       gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
4058 +       gpiodir &= ~(7 << gpio_field_offset);
4059 +        gpiodir |= function << gpio_field_offset;
4060 +       writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
4061 +       spin_unlock_irqrestore(&lock, flags);
4062 +       gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
4063 +
4064 +       return 0;
4065 +}
4066 +
4067 +
4068 +static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
4069 +{
4070 +       return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
4071 +}
4072 +
4073 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
4074 +static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset, int value)
4075 +{
4076 +       int ret;
4077 +        ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
4078 +        if (ret >= 0)
4079 +           bcm2708_gpio_set(gc, offset, value);
4080 +       return ret;
4081 +}
4082 +
4083 +static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
4084 +{
4085 +       struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
4086 +        unsigned gpio_bank = offset/32;
4087 +       unsigned gpio_field_offset = (offset - 32*gpio_bank);
4088 +        unsigned lev;
4089 +
4090 +       if (offset >= ARCH_NR_GPIOS)
4091 +               return 0;
4092 +        lev = readl(gpio->base + GPIOLEV(gpio_bank));
4093 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
4094 +       return 0x1 & (lev>>gpio_field_offset);
4095 +}
4096 +
4097 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
4098 +{
4099 +       struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
4100 +        unsigned gpio_bank = offset/32;
4101 +       unsigned gpio_field_offset = (offset - 32*gpio_bank);
4102 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
4103 +       if (offset >= ARCH_NR_GPIOS)
4104 +               return;
4105 +       if (value)
4106 +               writel(1<<gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
4107 +       else
4108 +               writel(1<<gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
4109 +}
4110 +
4111 +/*
4112 + * bcm2708 GPIO IRQ
4113 + */
4114 +
4115 +#if BCM_GPIO_USE_IRQ
4116 +static void bcm2708_irq_disable(unsigned irq)
4117 +{
4118 +       struct bcm2708_gpio *chip = get_irq_chip_data(irq);
4119 +       //int offset = irq - gpio->irq_base;
4120 +       unsigned long flags;
4121 +
4122 +       spin_lock_irqsave(&chip->irq_lock, flags);
4123 +        // disable gpio interrupts here
4124 +       spin_unlock_irqrestore(&chip->irq_lock, flags);
4125 +}
4126 +
4127 +static void bcm2708_irq_enable(unsigned irq)
4128 +{
4129 +       struct bcm2708_gpio *chip = get_irq_chip_data(irq);
4130 +       //int offset = irq - chip->irq_base;
4131 +       unsigned long flags;
4132 +
4133 +       spin_lock_irqsave(&chip->irq_lock, flags);
4134 +        // enable gpio interrupts here
4135 +       spin_unlock_irqrestore(&chip->irq_lock, flags);
4136 +}
4137 +
4138 +static int bcm2708_irq_type(unsigned irq, unsigned trigger)
4139 +{
4140 +       struct bcm2708_gpio *chip = get_irq_chip_data(irq);
4141 +       int offset = irq - chip->irq_base;
4142 +       unsigned long flags;
4143 +        unsigned gpio_bank = offset/32;
4144 +       unsigned gpio_field_offset = (offset - 32*gpio_bank);
4145 +       unsigned gpioren, gpiofen, gpiohen, gpiolen;
4146 +
4147 +       if (offset < 0 || offset >= ARCH_NR_GPIOS)
4148 +               return -EINVAL;
4149 +
4150 +       spin_lock_irqsave(&chip->irq_lock, flags);
4151 +
4152 +       gpioren = readl(chip->base + GPIOREN(gpio_bank));
4153 +       gpiofen = readl(chip->base + GPIOFEN(gpio_bank));
4154 +       gpiohen = readl(chip->base + GPIOHEN(gpio_bank));
4155 +       gpiolen = readl(chip->base + GPIOLEN(gpio_bank));
4156 +
4157 +       if (trigger & (IRQ_TYPE_EDGE_RISING))
4158 +               gpioren |=  (1<<gpio_field_offset);
4159 +       else
4160 +               gpioren &= ~(1<<gpio_field_offset);
4161 +       if (trigger & (IRQ_TYPE_EDGE_FALLING))
4162 +               gpiofen |=  (1<<gpio_field_offset);
4163 +       else
4164 +               gpiofen &= ~(1<<gpio_field_offset);
4165 +       if (trigger & (IRQ_TYPE_LEVEL_HIGH))
4166 +               gpiohen |=  (1<<gpio_field_offset);
4167 +       else
4168 +               gpiohen &= ~(1<<gpio_field_offset);
4169 +       if (trigger & (IRQ_TYPE_LEVEL_LOW))
4170 +               gpiolen |=  (1<<gpio_field_offset);
4171 +       else
4172 +               gpiolen &= ~(1<<gpio_field_offset);
4173 +
4174 +       writel(gpioren, chip->base + GPIOREN(gpio_bank));
4175 +       writel(gpiofen, chip->base + GPIOFEN(gpio_bank));
4176 +       writel(gpiohen, chip->base + GPIOHEN(gpio_bank));
4177 +       writel(gpiolen, chip->base + GPIOLEN(gpio_bank));
4178 +
4179 +       spin_unlock_irqrestore(&chip->irq_lock, flags);
4180 +
4181 +       return 0;
4182 +}
4183 +
4184 +static struct irq_chip bcm2708_irqchip = {
4185 +       .name           = "GPIO",
4186 +       .enable         = bcm2708_irq_enable,
4187 +       .disable        = bcm2708_irq_disable,
4188 +       .set_type       = bcm2708_irq_type,
4189 +};
4190 +
4191 +static void bcm2708_irq_handler(unsigned irq, struct irq_desc *desc)
4192 +{
4193 +       struct list_head *chip_list = get_irq_data(irq);
4194 +       struct list_head *ptr;
4195 +       struct bcm2708_gpio *chip;
4196 +       unsigned gpio_bank;
4197 +
4198 +       desc->chip->ack(irq);
4199 +       list_for_each(ptr, chip_list) {
4200 +               unsigned long pending;
4201 +               int offset;
4202 +
4203 +               chip = list_entry(ptr, struct bcm2708_gpio, list);
4204 +               for (gpio_bank = 0; gpio_bank < ARCH_NR_GPIOS/32; gpio_bank++) {
4205 +                       pending = readl(chip->base + GPIOEDS(gpio_bank));
4206 +                       writel(pending, chip->base + GPIOEDS(gpio_bank));
4207 +
4208 +                       if (pending == 0)
4209 +                               continue;
4210 +
4211 +                       for_each_set_bit(offset, &pending, ARCH_NR_GPIOS)
4212 +                               generic_handle_irq(gpio_to_irq(offset+32*gpio_bank));
4213 +               }
4214 +       }
4215 +       desc->chip->unmask(irq);
4216 +}
4217 +#endif /* #if BCM_GPIO_USE_IRQ */
4218 +
4219 +static int bcm2708_gpio_probe(struct platform_device *dev)
4220 +{
4221 +       struct bcm2708_gpio *ucb;
4222 +       struct resource *res;
4223 +       int err = 0;
4224 +
4225 +        printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
4226 +
4227 +       ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
4228 +       if (NULL == ucb) {
4229 +               printk(KERN_ERR DRIVER_NAME ": failed to allocate "
4230 +                      "mailbox memory\n");
4231 +               err = -ENOMEM;
4232 +               goto err;
4233 +       }
4234 +
4235 +       res = platform_get_resource(dev, IORESOURCE_MEM, 0);
4236 +
4237 +       platform_set_drvdata(dev, ucb);
4238 +        ucb->base = __io_address(GPIO_BASE);
4239 +
4240 +       ucb->gc.label = "bcm2708_gpio";
4241 +       ucb->gc.base = 0;
4242 +       ucb->gc.ngpio = ARCH_NR_GPIOS;
4243 +       ucb->gc.owner = THIS_MODULE;
4244 +
4245 +       ucb->gc.direction_input = bcm2708_gpio_dir_in;
4246 +       ucb->gc.direction_output = bcm2708_gpio_dir_out;
4247 +       ucb->gc.get = bcm2708_gpio_get;
4248 +       ucb->gc.set = bcm2708_gpio_set;
4249 +       ucb->gc.can_sleep = 0;
4250 +
4251 +       err = gpiochip_add(&ucb->gc);
4252 +       if (err)
4253 +               goto err;
4254 +
4255 +err:
4256 +       return err;
4257 +
4258 +}
4259 +
4260 +static int bcm2708_gpio_remove(struct platform_device *dev)
4261 +{
4262 +       int err = 0;
4263 +       struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
4264 +
4265 +       printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
4266 +
4267 +       err = gpiochip_remove(&ucb->gc);
4268 +
4269 +       platform_set_drvdata(dev, NULL);
4270 +       kfree(ucb);
4271 +
4272 +       return err;
4273 +}
4274 +
4275 +static struct platform_driver bcm2708_gpio_driver = {
4276 +       .probe  = bcm2708_gpio_probe,
4277 +       .remove = bcm2708_gpio_remove,
4278 +       .driver = {
4279 +               .name   = "bcm2708_gpio"
4280 +       },
4281 +};
4282 +
4283 +static int __init bcm2708_gpio_init(void)
4284 +{
4285 +       return platform_driver_register(&bcm2708_gpio_driver);
4286 +}
4287 +
4288 +static void __exit bcm2708_gpio_exit(void)
4289 +{
4290 +       platform_driver_unregister(&bcm2708_gpio_driver);
4291 +}
4292 +
4293 +module_init(bcm2708_gpio_init);
4294 +module_exit(bcm2708_gpio_exit);
4295 +
4296 +MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
4297 +MODULE_LICENSE("GPL");
4298 +
4299 --- /dev/null
4300 +++ b/arch/arm/mach-bcm2708/clock.c
4301 @@ -0,0 +1,61 @@
4302 +/*
4303 + *  linux/arch/arm/mach-bcm2708/clock.c
4304 + *
4305 + *  Copyright (C) 2010 Broadcom
4306 + *
4307 + * This program is free software; you can redistribute it and/or modify
4308 + * it under the terms of the GNU General Public License as published by
4309 + * the Free Software Foundation; either version 2 of the License, or
4310 + * (at your option) any later version.
4311 + *
4312 + * This program is distributed in the hope that it will be useful,
4313 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4314 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4315 + * GNU General Public License for more details.
4316 + *
4317 + * You should have received a copy of the GNU General Public License
4318 + * along with this program; if not, write to the Free Software
4319 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
4320 + */
4321 +#include <linux/module.h>
4322 +#include <linux/kernel.h>
4323 +#include <linux/device.h>
4324 +#include <linux/list.h>
4325 +#include <linux/errno.h>
4326 +#include <linux/err.h>
4327 +#include <linux/string.h>
4328 +#include <linux/clk.h>
4329 +#include <linux/mutex.h>
4330 +
4331 +#include <asm/clkdev.h>
4332 +
4333 +#include "clock.h"
4334 +
4335 +int clk_enable(struct clk *clk)
4336 +{
4337 +       return 0;
4338 +}
4339 +EXPORT_SYMBOL(clk_enable);
4340 +
4341 +void clk_disable(struct clk *clk)
4342 +{
4343 +}
4344 +EXPORT_SYMBOL(clk_disable);
4345 +
4346 +unsigned long clk_get_rate(struct clk *clk)
4347 +{
4348 +       return clk->rate;
4349 +}
4350 +EXPORT_SYMBOL(clk_get_rate);
4351 +
4352 +long clk_round_rate(struct clk *clk, unsigned long rate)
4353 +{
4354 +       return clk->rate;
4355 +}
4356 +EXPORT_SYMBOL(clk_round_rate);
4357 +
4358 +int clk_set_rate(struct clk *clk, unsigned long rate)
4359 +{
4360 +       return -EIO;
4361 +}
4362 +EXPORT_SYMBOL(clk_set_rate);
4363 --- /dev/null
4364 +++ b/arch/arm/mach-bcm2708/clock.h
4365 @@ -0,0 +1,24 @@
4366 +/*
4367 + *  linux/arch/arm/mach-bcm2708/clock.h
4368 + *
4369 + *  Copyright (C) 2010 Broadcom
4370 + *
4371 + * This program is free software; you can redistribute it and/or modify
4372 + * it under the terms of the GNU General Public License as published by
4373 + * the Free Software Foundation; either version 2 of the License, or
4374 + * (at your option) any later version.
4375 + *
4376 + * This program is distributed in the hope that it will be useful,
4377 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4378 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4379 + * GNU General Public License for more details.
4380 + *
4381 + * You should have received a copy of the GNU General Public License
4382 + * along with this program; if not, write to the Free Software
4383 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
4384 + */
4385 +struct module;
4386 +
4387 +struct clk {
4388 +       unsigned long           rate;
4389 +};
4390 --- /dev/null
4391 +++ b/arch/arm/mach-bcm2708/dma.c
4392 @@ -0,0 +1,397 @@
4393 +/*
4394 + *  linux/arch/arm/mach-bcm2708/dma.c
4395 + *
4396 + *  Copyright (C) 2010 Broadcom
4397 + *
4398 + * This program is free software; you can redistribute it and/or modify
4399 + * it under the terms of the GNU General Public License version 2 as
4400 + * published by the Free Software Foundation.
4401 + */
4402 +
4403 +#include <linux/slab.h>
4404 +#include <linux/device.h>
4405 +#include <linux/platform_device.h>
4406 +#include <linux/module.h>
4407 +#include <linux/scatterlist.h>
4408 +
4409 +#include <mach/dma.h>
4410 +#include <mach/irqs.h>
4411 +
4412 +/*****************************************************************************\
4413 + *                                                                          *
4414 + * Configuration                                                            *
4415 + *                                                                          *
4416 +\*****************************************************************************/
4417 +
4418 +#define CACHE_LINE_MASK 31
4419 +#define DRIVER_NAME BCM_DMAMAN_DRIVER_NAME
4420 +#define DEFAULT_DMACHAN_BITMAP 0x10  /* channel 4 only */
4421 +
4422 +/* valid only for channels 0 - 14, 15 has its own base address */
4423 +#define BCM2708_DMA_CHAN(n)    ((n)<<8) /* base address */
4424 +#define BCM2708_DMA_CHANIO(dma_base, n) \
4425 +   ((void __iomem *)((char *)(dma_base)+BCM2708_DMA_CHAN(n)))
4426 +
4427 +
4428 +/*****************************************************************************\
4429 + *                                                                          *
4430 + * DMA Auxilliary Functions                                                 *
4431 + *                                                                          *
4432 +\*****************************************************************************/
4433 +
4434 +/* A DMA buffer on an arbitrary boundary may separate a cache line into a
4435 +   section inside the DMA buffer and another section outside it.
4436 +   Even if we flush DMA buffers from the cache there is always the chance that
4437 +   during a DMA someone will access the part of a cache line that is outside
4438 +   the DMA buffer - which will then bring in unwelcome data.
4439 +   Without being able to dictate our own buffer pools we must insist that
4440 +   DMA buffers consist of a whole number of cache lines.
4441 +*/
4442 +
4443 +extern int
4444 +bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
4445 +{
4446 +       int i;
4447 +
4448 +       for (i = 0; i < sg_len; i++) {
4449 +               if (sg_ptr[i].offset & CACHE_LINE_MASK ||
4450 +                   sg_ptr[i].length & CACHE_LINE_MASK)
4451 +                       return 0;
4452 +       }
4453 +
4454 +       return 1;
4455 +}
4456 +EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
4457 +
4458 +extern void
4459 +bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block)
4460 +{
4461 +       dsb();  /* ARM data synchronization (push) operation */
4462 +
4463 +       writel(control_block,        dma_chan_base + BCM2708_DMA_ADDR);
4464 +       writel(BCM2708_DMA_ACTIVE,   dma_chan_base + BCM2708_DMA_CS);
4465 +}
4466 +
4467 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
4468 +{
4469 +  dsb();
4470 +
4471 +  /* ugly busy wait only option for now */
4472 +  while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE);
4473 +}
4474 +
4475 +EXPORT_SYMBOL_GPL(bcm_dma_start);
4476 +
4477 +/* Complete an ongoing DMA (assuming its results are to be ignored)
4478 +   Does nothing if there is no DMA in progress.
4479 +   This routine waits for the current AXI transfer to complete before
4480 +   terminating the current DMA.         If the current transfer is hung on a DREQ used
4481 +   by an uncooperative peripheral the AXI transfer may never complete. In this
4482 +   case the routine times out and return a non-zero error code.
4483 +   Use of this routine doesn't guarantee that the ongoing or aborted DMA
4484 +   does not produce an interrupt.
4485 +*/
4486 +extern int
4487 +bcm_dma_abort(void __iomem *dma_chan_base)
4488 +{
4489 +       unsigned long int cs;
4490 +       int rc = 0;
4491 +
4492 +       cs = readl(dma_chan_base + BCM2708_DMA_CS);
4493 +
4494 +       if (BCM2708_DMA_ACTIVE & cs) {
4495 +               long int timeout = 10000;
4496 +
4497 +               /* write 0 to the active bit - pause the DMA */
4498 +               writel(0, dma_chan_base + BCM2708_DMA_CS);
4499 +
4500 +               /* wait for any current AXI transfer to complete */
4501 +               while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
4502 +                       cs = readl(dma_chan_base + BCM2708_DMA_CS);
4503 +
4504 +               if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
4505 +                       /* we'll un-pause when we set of our next DMA */
4506 +                       rc = -ETIMEDOUT;
4507 +
4508 +               } else if (BCM2708_DMA_ACTIVE & cs) {
4509 +                       /* terminate the control block chain */
4510 +                       writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
4511 +
4512 +                       /* abort the whole DMA */
4513 +                       writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
4514 +                              dma_chan_base + BCM2708_DMA_CS);
4515 +               }
4516 +       }
4517 +
4518 +       return rc;
4519 +}
4520 +EXPORT_SYMBOL_GPL(bcm_dma_abort);
4521 +
4522 +
4523 +/***************************************************************************** \
4524 + *                                                                          *
4525 + * DMA Manager Device Methods                                               *
4526 + *                                                                          *
4527 +\*****************************************************************************/
4528 +
4529 +struct vc_dmaman {
4530 +       void __iomem *dma_base;
4531 +       u32 chan_available; /* bitmap of available channels */
4532 +       u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
4533 +};
4534 +
4535 +static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
4536 +                          u32 chans_available)
4537 +{
4538 +       dmaman->dma_base = dma_base;
4539 +       dmaman->chan_available = chans_available;
4540 +       dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c;  /* chans 2 & 3 */
4541 +}
4542 +
4543 +static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
4544 +                               unsigned preferred_feature_set)
4545 +{
4546 +       u32 chans;
4547 +       int feature;
4548 +
4549 +       chans = dmaman->chan_available;
4550 +       for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
4551 +               /* select the subset of available channels with the desired
4552 +                  feature so long as some of the candidate channels have that
4553 +                  feature */
4554 +               if ((preferred_feature_set & (1 << feature)) &&
4555 +                   (chans & dmaman->has_feature[feature]))
4556 +                       chans &= dmaman->has_feature[feature];
4557 +
4558 +       if (chans) {
4559 +               int chan = 0;
4560 +               /* return the ordinal of the first channel in the bitmap */
4561 +               while (chans != 0 && (chans & 1) == 0) {
4562 +                       chans >>= 1;
4563 +                       chan++;
4564 +               }
4565 +               /* claim the channel */
4566 +               dmaman->chan_available &= ~(1 << chan);
4567 +               return chan;
4568 +       } else
4569 +               return -ENOMEM;
4570 +}
4571 +
4572 +static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
4573 +{
4574 +       if (chan < 0)
4575 +               return -EINVAL;
4576 +       else if ((1 << chan) & dmaman->chan_available)
4577 +               return -EIDRM;
4578 +       else {
4579 +               dmaman->chan_available |= (1 << chan);
4580 +               return 0;
4581 +       }
4582 +}
4583 +
4584 +/*****************************************************************************\
4585 + *                                                                          *
4586 + * DMA IRQs                                                                 *
4587 + *                                                                          *
4588 +\*****************************************************************************/
4589 +
4590 +static unsigned char bcm_dma_irqs[] = {
4591 +       IRQ_DMA0,
4592 +       IRQ_DMA1,
4593 +       IRQ_DMA2,
4594 +       IRQ_DMA3,
4595 +       IRQ_DMA4,
4596 +       IRQ_DMA5,
4597 +       IRQ_DMA6,
4598 +       IRQ_DMA7,
4599 +       IRQ_DMA8,
4600 +       IRQ_DMA9,
4601 +       IRQ_DMA10,
4602 +       IRQ_DMA11,
4603 +       IRQ_DMA12
4604 +};
4605 +
4606 +
4607 +/***************************************************************************** \
4608 + *                                                                          *
4609 + * DMA Manager Monitor                                                      *
4610 + *                                                                          *
4611 +\*****************************************************************************/
4612 +
4613 +static struct device *dmaman_dev;      /* we assume there's only one! */
4614 +
4615 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
4616 +                             void __iomem **out_dma_base, int *out_dma_irq)
4617 +{
4618 +       if (!dmaman_dev)
4619 +               return -ENODEV;
4620 +       else {
4621 +               struct vc_dmaman *dmaman  = dev_get_drvdata(dmaman_dev);
4622 +               int rc;
4623 +
4624 +               device_lock(dmaman_dev);
4625 +               rc = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
4626 +               if (rc >= 0) {
4627 +                       *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base,
4628 +                                                          rc);
4629 +                       *out_dma_irq = bcm_dma_irqs[rc];
4630 +               }
4631 +               device_unlock(dmaman_dev);
4632 +
4633 +               return rc;
4634 +       }
4635 +}
4636 +EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
4637 +
4638 +extern int bcm_dma_chan_free(int channel)
4639 +{
4640 +       if (dmaman_dev) {
4641 +               struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
4642 +               int rc;
4643 +
4644 +               device_lock(dmaman_dev);
4645 +               rc = vc_dmaman_chan_free(dmaman, channel);
4646 +               device_unlock(dmaman_dev);
4647 +
4648 +               return rc;
4649 +       } else
4650 +               return -ENODEV;
4651 +}
4652 +EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
4653 +
4654 +static int dev_dmaman_register(const char *dev_name, struct device *dev)
4655 +{
4656 +       int rc = dmaman_dev ? -EINVAL : 0;
4657 +       dmaman_dev = dev;
4658 +       return rc;
4659 +}
4660 +
4661 +static void dev_dmaman_deregister(const char *dev_name, struct device *dev)
4662 +{
4663 +       dmaman_dev = NULL;
4664 +}
4665 +
4666 +/*****************************************************************************\
4667 + *                                                                          *
4668 + * DMA Device                                                               *
4669 + *                                                                          *
4670 +\*****************************************************************************/
4671 +
4672 +static int dmachans = -1; /* module parameter */
4673 +
4674 +static int bcm_dmaman_probe(struct platform_device *pdev)
4675 +{
4676 +       int ret = 0;
4677 +       struct vc_dmaman *dmaman;
4678 +       struct resource *dma_res = NULL;
4679 +       void __iomem *dma_base = NULL;
4680 +       int have_dma_region = 0;
4681 +
4682 +       dmaman = kzalloc(sizeof(*dmaman), GFP_KERNEL);
4683 +       if (NULL == dmaman) {
4684 +               printk(KERN_ERR DRIVER_NAME ": failed to allocate "
4685 +                      "DMA management memory\n");
4686 +               ret = -ENOMEM;
4687 +       } else {
4688 +
4689 +               dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4690 +               if (dma_res == NULL) {
4691 +                       printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
4692 +                              "resource\n");
4693 +                       ret = -ENODEV;
4694 +               } else if (!request_mem_region(dma_res->start,
4695 +                                              resource_size(dma_res),
4696 +                                              DRIVER_NAME)) {
4697 +                       dev_err(&pdev->dev, "cannot obtain DMA region\n");
4698 +                       ret = -EBUSY;
4699 +               } else {
4700 +                       have_dma_region = 1;
4701 +                       dma_base = ioremap(dma_res->start,
4702 +                                          resource_size(dma_res));
4703 +                       if (!dma_base) {
4704 +                               dev_err(&pdev->dev, "cannot map DMA region\n");
4705 +                               ret = -ENOMEM;
4706 +                       } else {
4707 +                               /* use module parameter if one was provided */
4708 +                               if (dmachans > 0)
4709 +                                       vc_dmaman_init(dmaman, dma_base,
4710 +                                                      dmachans);
4711 +                               else
4712 +                                       vc_dmaman_init(dmaman, dma_base,
4713 +                                                      DEFAULT_DMACHAN_BITMAP);
4714 +
4715 +                               platform_set_drvdata(pdev, dmaman);
4716 +                               dev_dmaman_register(DRIVER_NAME, &pdev->dev);
4717 +
4718 +                               printk(KERN_INFO DRIVER_NAME ": DMA manager "
4719 +                                      "at %p\n", dma_base);
4720 +                       }
4721 +               }
4722 +       }
4723 +       if (ret != 0) {
4724 +               if (dma_base)
4725 +                       iounmap(dma_base);
4726 +               if (dma_res && have_dma_region)
4727 +                       release_mem_region(dma_res->start,
4728 +                                          resource_size(dma_res));
4729 +               if (dmaman)
4730 +                       kfree(dmaman);
4731 +       }
4732 +       return ret;
4733 +}
4734 +
4735 +static int bcm_dmaman_remove(struct platform_device *pdev)
4736 +{
4737 +       struct vc_dmaman *dmaman = platform_get_drvdata(pdev);
4738 +
4739 +       platform_set_drvdata(pdev, NULL);
4740 +       dev_dmaman_deregister(DRIVER_NAME, &pdev->dev);
4741 +       kfree(dmaman);
4742 +
4743 +       return 0;
4744 +}
4745 +
4746 +static struct platform_driver bcm_dmaman_driver = {
4747 +       .probe = bcm_dmaman_probe,
4748 +       .remove = bcm_dmaman_remove,
4749 +
4750 +       .driver = {
4751 +                  .name = DRIVER_NAME,
4752 +                  .owner = THIS_MODULE,
4753 +                  },
4754 +};
4755 +
4756 +/*****************************************************************************\
4757 + *                                                                          *
4758 + * Driver init/exit                                                         *
4759 + *                                                                          *
4760 +\*****************************************************************************/
4761 +
4762 +static int __init bcm_dmaman_drv_init(void)
4763 +{
4764 +       int ret;
4765 +
4766 +       ret = platform_driver_register(&bcm_dmaman_driver);
4767 +       if (ret != 0) {
4768 +               printk(KERN_ERR DRIVER_NAME ": failed to register "
4769 +                      "on platform\n");
4770 +       }
4771 +
4772 +       return ret;
4773 +}
4774 +
4775 +static void __exit bcm_dmaman_drv_exit(void)
4776 +{
4777 +       platform_driver_unregister(&bcm_dmaman_driver);
4778 +}
4779 +
4780 +module_init(bcm_dmaman_drv_init);
4781 +module_exit(bcm_dmaman_drv_exit);
4782 +
4783 +module_param(dmachans, int, 0644);
4784 +
4785 +MODULE_AUTHOR("Gray Girling <grayg@broadcom.com>");
4786 +MODULE_DESCRIPTION("DMA channel manager driver");
4787 +MODULE_LICENSE("GPL");
4788 +
4789 +MODULE_PARM_DESC(dmachans, "Bitmap of DMA channels available to the ARM");
4790 --- /dev/null
4791 +++ b/arch/arm/mach-bcm2708/include/mach/arm_control.h
4792 @@ -0,0 +1,419 @@
4793 +/*
4794 + *  linux/arch/arm/mach-bcm2708/arm_control.h
4795 + *
4796 + *  Copyright (C) 2010 Broadcom
4797 + *
4798 + * This program is free software; you can redistribute it and/or modify
4799 + * it under the terms of the GNU General Public License as published by
4800 + * the Free Software Foundation; either version 2 of the License, or
4801 + * (at your option) any later version.
4802 + *
4803 + * This program is distributed in the hope that it will be useful,
4804 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4805 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4806 + * GNU General Public License for more details.
4807 + *
4808 + * You should have received a copy of the GNU General Public License
4809 + * along with this program; if not, write to the Free Software
4810 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
4811 + */
4812 +
4813 +#ifndef __BCM2708_ARM_CONTROL_H
4814 +#define __BCM2708_ARM_CONTROL_H
4815 +
4816 +/*
4817 + * Definitions and addresses for the ARM CONTROL logic
4818 + * This file is manually generated.
4819 + */
4820 +
4821 +#define ARM_BASE  0x7E00B000
4822 +
4823 +/* Basic configuration */
4824 +#define ARM_CONTROL0  HW_REGISTER_RW(ARM_BASE+0x000)
4825 +#define ARM_C0_SIZ128M   0x00000000
4826 +#define ARM_C0_SIZ256M   0x00000001
4827 +#define ARM_C0_SIZ512M   0x00000002
4828 +#define ARM_C0_SIZ1G     0x00000003
4829 +#define ARM_C0_BRESP0    0x00000000
4830 +#define ARM_C0_BRESP1    0x00000004
4831 +#define ARM_C0_BRESP2    0x00000008
4832 +#define ARM_C0_BOOTHI    0x00000010
4833 +#define ARM_C0_UNUSED05  0x00000020 /* free */
4834 +#define ARM_C0_FULLPERI  0x00000040
4835 +#define ARM_C0_UNUSED78  0x00000180 /* free */
4836 +#define ARM_C0_JTAGMASK  0x00000E00
4837 +#define ARM_C0_JTAGOFF   0x00000000
4838 +#define ARM_C0_JTAGBASH  0x00000800 /* Debug on GPIO off */
4839 +#define ARM_C0_JTAGGPIO  0x00000C00 /* Debug on GPIO on */
4840 +#define ARM_C0_APROTMSK  0x0000F000
4841 +#define ARM_C0_DBG0SYNC  0x00010000 /* VPU0 halt sync */
4842 +#define ARM_C0_DBG1SYNC  0x00020000 /* VPU1 halt sync */
4843 +#define ARM_C0_SWDBGREQ  0x00040000 /* HW debug request */
4844 +#define ARM_C0_PASSHALT  0x00080000 /* ARM halt passed to debugger */
4845 +#define ARM_C0_PRIO_PER  0x00F00000 /* per priority mask */
4846 +#define ARM_C0_PRIO_L2   0x0F000000
4847 +#define ARM_C0_PRIO_UC   0xF0000000
4848 +
4849 +#define ARM_C0_APROTPASS  0x0000A000 /* Translate 1:1 */
4850 +#define ARM_C0_APROTUSER  0x00000000 /* Only user mode */
4851 +#define ARM_C0_APROTSYST  0x0000F000 /* Only system mode */
4852 +
4853 +
4854 +#define ARM_CONTROL1  HW_REGISTER_RW(ARM_BASE+0x440)
4855 +#define ARM_C1_TIMER     0x00000001 /* re-route timer IRQ  to VC */
4856 +#define ARM_C1_MAIL      0x00000002 /* re-route Mail IRQ   to VC */
4857 +#define ARM_C1_BELL0     0x00000004 /* re-route Doorbell 0 to VC */
4858 +#define ARM_C1_BELL1     0x00000008 /* re-route Doorbell 1 to VC */
4859 +#define ARM_C1_PERSON    0x00000100 /* peripherals on */
4860 +#define ARM_C1_REQSTOP   0x00000200 /* ASYNC bridge request stop */
4861 +
4862 +#define ARM_STATUS    HW_REGISTER_RW(ARM_BASE+0x444)
4863 +#define ARM_S_ACKSTOP    0x80000000 /* Bridge stopped */
4864 +#define ARM_S_READPEND   0x000003FF /* pending reads counter */
4865 +#define ARM_S_WRITPEND   0x000FFC00 /* pending writes counter */
4866 +
4867 +#define ARM_ERRHALT   HW_REGISTER_RW(ARM_BASE+0x448)
4868 +#define ARM_EH_PERIBURST  0x00000001 /* Burst write seen on peri bus */
4869 +#define ARM_EH_ILLADDRS1  0x00000002 /* Address bits 25-27 error */
4870 +#define ARM_EH_ILLADDRS2  0x00000004 /* Address bits 31-28 error */
4871 +#define ARM_EH_VPU0HALT   0x00000008 /* VPU0 halted & in debug mode */
4872 +#define ARM_EH_VPU1HALT   0x00000010 /* VPU1 halted & in debug mode */
4873 +#define ARM_EH_ARMHALT    0x00000020 /* ARM in halted debug mode */
4874 +
4875 +#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
4876 +#define ARM_ID        HW_REGISTER_RW(ARM_BASE+0x44C)
4877 +#define ARM_IDVAL        0x364D5241
4878 +
4879 +/* Translation memory */
4880 +#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
4881 +/* 32 locations: 0x100.. 0x17F */
4882 +/* 32 spare means we CAN go to 64 pages.... */
4883 +
4884 +
4885 +/* Interrupts */
4886 +#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200)        /* Top IRQ bits */
4887 +#define ARM_I0_TIMER    0x00000001 /* timer IRQ */
4888 +#define ARM_I0_MAIL     0x00000002 /* Mail IRQ */
4889 +#define ARM_I0_BELL0    0x00000004 /* Doorbell 0 */
4890 +#define ARM_I0_BELL1    0x00000008 /* Doorbell 1 */
4891 +#define ARM_I0_BANK1    0x00000100 /* Bank1 IRQ */
4892 +#define ARM_I0_BANK2    0x00000200 /* Bank2 IRQ */
4893 +
4894 +#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
4895 +/* todo: all I1_interrupt sources */
4896 +#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
4897 +/* todo: all I2_interrupt sources */
4898 +
4899 +#define ARM_IRQ_FAST  HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
4900 +#define ARM_IF_INDEX    0x0000007F     /* FIQ select */
4901 +#define ARM_IF_ENABLE   0x00000080     /* FIQ enable */
4902 +#define ARM_IF_VCMASK   0x0000003F     /* FIQ = (index from VC source) */
4903 +#define ARM_IF_TIMER    0x00000040     /* FIQ = ARM timer */
4904 +#define ARM_IF_MAIL     0x00000041     /* FIQ = ARM Mail */
4905 +#define ARM_IF_BELL0    0x00000042     /* FIQ = ARM Doorbell 0 */
4906 +#define ARM_IF_BELL1    0x00000043     /* FIQ = ARM Doorbell 1 */
4907 +#define ARM_IF_VP0HALT  0x00000044     /* FIQ = VPU0 Halt seen */
4908 +#define ARM_IF_VP1HALT  0x00000045     /* FIQ = VPU1 Halt seen */
4909 +#define ARM_IF_ILLEGAL  0x00000046     /* FIQ = Illegal access seen */
4910 +
4911 +#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
4912 +#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
4913 +#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
4914 +#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
4915 +#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
4916 +#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
4917 +#define ARM_IE_TIMER    0x00000001     /* Timer IRQ */
4918 +#define ARM_IE_MAIL     0x00000002     /* Mail IRQ */
4919 +#define ARM_IE_BELL0    0x00000004     /* Doorbell 0 */
4920 +#define ARM_IE_BELL1    0x00000008     /* Doorbell 1 */
4921 +#define ARM_IE_VP0HALT  0x00000010     /* VPU0 Halt */
4922 +#define ARM_IE_VP1HALT  0x00000020     /* VPU1 Halt */
4923 +#define ARM_IE_ILLEGAL  0x00000040     /* Illegal access seen */
4924 +
4925 +/* Timer */
4926 +/* For reg. fields see sp804 spec. */
4927 +#define ARM_T_LOAD    HW_REGISTER_RW(ARM_BASE+0x400)
4928 +#define ARM_T_VALUE   HW_REGISTER_RW(ARM_BASE+0x404)
4929 +#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
4930 +#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
4931 +#define ARM_T_RAWIRQ  HW_REGISTER_RW(ARM_BASE+0x410)
4932 +#define ARM_T_MSKIRQ  HW_REGISTER_RW(ARM_BASE+0x414)
4933 +#define ARM_T_RELOAD  HW_REGISTER_RW(ARM_BASE+0x418)
4934 +#define ARM_T_PREDIV  HW_REGISTER_RW(ARM_BASE+0x41c)
4935 +#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
4936 +
4937 +#define TIMER_CTRL_ONESHOT  (1 << 0)
4938 +#define TIMER_CTRL_32BIT    (1 << 1)
4939 +#define TIMER_CTRL_DIV1     (0 << 2)
4940 +#define TIMER_CTRL_DIV16    (1 << 2)
4941 +#define TIMER_CTRL_DIV256   (2 << 2)
4942 +#define TIMER_CTRL_IE       (1 << 5)
4943 +#define TIMER_CTRL_PERIODIC (1 << 6)
4944 +#define TIMER_CTRL_ENABLE   (1 << 7)
4945 +#define TIMER_CTRL_DBGHALT  (1 << 8)
4946 +#define TIMER_CTRL_ENAFREE  (1 << 9)
4947 +#define TIMER_CTRL_FREEDIV_SHIFT 16)
4948 +#define TIMER_CTRL_FREEDIV_MASK  0xff
4949 +
4950 +/* Semaphores, Doorbells, Mailboxes */
4951 +#define ARM_SBM_OWN0  (ARM_BASE+0x800)
4952 +#define ARM_SBM_OWN1  (ARM_BASE+0x900)
4953 +#define ARM_SBM_OWN2  (ARM_BASE+0xA00)
4954 +#define ARM_SBM_OWN3  (ARM_BASE+0xB00)
4955 +
4956 +/* MAILBOXES
4957 + * Register flags are common across all
4958 + * owner registers. See end of this section
4959 + *
4960 + * Semaphores, Doorbells, Mailboxes Owner 0
4961 + *
4962 + */
4963 +
4964 +#define ARM_0_SEMS       HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
4965 +#define ARM_0_SEM0       HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
4966 +#define ARM_0_SEM1       HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
4967 +#define ARM_0_SEM2       HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
4968 +#define ARM_0_SEM3       HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
4969 +#define ARM_0_SEM4       HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
4970 +#define ARM_0_SEM5       HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
4971 +#define ARM_0_SEM6       HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
4972 +#define ARM_0_SEM7       HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
4973 +#define ARM_0_BELL0      HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
4974 +#define ARM_0_BELL1      HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
4975 +#define ARM_0_BELL2      HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
4976 +#define ARM_0_BELL3      HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
4977 +/* MAILBOX 0 access in Owner 0 area */
4978 +/* Some addresses should ONLY be used by owner 0 */
4979 +#define ARM_0_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN0+0x80)  /* .. 0x8C (4 locations) */
4980 +#define ARM_0_MAIL0_RD   HW_REGISTER_RW(ARM_SBM_OWN0+0x80)  /* .. 0x8C (4 locations) Normal read */
4981 +#define ARM_0_MAIL0_POL  HW_REGISTER_RW(ARM_SBM_OWN0+0x90)  /* none-pop read */
4982 +#define ARM_0_MAIL0_SND  HW_REGISTER_RW(ARM_SBM_OWN0+0x94)  /* Sender read (only LS 2 bits) */
4983 +#define ARM_0_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN0+0x98)  /* Status read */
4984 +#define ARM_0_MAIL0_CNF  HW_REGISTER_RW(ARM_SBM_OWN0+0x9C)  /* Config read/write */
4985 +/* MAILBOX 1 access in Owner 0 area */
4986 +/* Owner 0 should only WRITE to this mailbox */
4987 +#define ARM_0_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN0+0xA0)   /* .. 0xAC (4 locations) */
4988 +/*#define ARM_0_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
4989 +/*#define ARM_0_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
4990 +/*#define ARM_0_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
4991 +#define ARM_0_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN0+0xB8)   /* Status read */
4992 +/*#define ARM_0_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
4993 +/* General SEM, BELL, MAIL config/status */
4994 +#define ARM_0_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN0+0xE0)  /* semaphore clear/debug register */
4995 +#define ARM_0_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN0+0xE4)  /* Doorbells clear/debug register */
4996 +#define ARM_0_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN0+0xF8)  /* ALL interrupts */
4997 +#define ARM_0_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN0+0xFC)  /* IRQS pending for owner 0 */
4998 +
4999 +/* Semaphores, Doorbells, Mailboxes Owner 1 */
5000 +#define ARM_1_SEMS       HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
5001 +#define ARM_1_SEM0       HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
5002 +#define ARM_1_SEM1       HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
5003 +#define ARM_1_SEM2       HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
5004 +#define ARM_1_SEM3       HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
5005 +#define ARM_1_SEM4       HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
5006 +#define ARM_1_SEM5       HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
5007 +#define ARM_1_SEM6       HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
5008 +#define ARM_1_SEM7       HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
5009 +#define ARM_1_BELL0      HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
5010 +#define ARM_1_BELL1      HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
5011 +#define ARM_1_BELL2      HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
5012 +#define ARM_1_BELL3      HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
5013 +/* MAILBOX 0 access in Owner 0 area */
5014 +/* Owner 1 should only WRITE to this mailbox */
5015 +#define ARM_1_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN1+0x80)  /* .. 0x8C (4 locations) */
5016 +/*#define ARM_1_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
5017 +/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
5018 +/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
5019 +#define ARM_1_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN1+0x98)  /* Status read */
5020 +/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
5021 +/* MAILBOX 1 access in Owner 0 area */
5022 +#define ARM_1_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN1+0xA0)  /* .. 0xAC (4 locations) */
5023 +#define ARM_1_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN1+0xA0)  /* .. 0xAC (4 locations) Normal read */
5024 +#define ARM_1_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN1+0xB0)  /* none-pop read */
5025 +#define ARM_1_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN1+0xB4)  /* Sender read (only LS 2 bits) */
5026 +#define ARM_1_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN1+0xB8)  /* Status read */
5027 +#define ARM_1_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
5028 +/* General SEM, BELL, MAIL config/status */
5029 +#define ARM_1_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN1+0xE0)  /* semaphore clear/debug register */
5030 +#define ARM_1_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN1+0xE4)  /* Doorbells clear/debug register */
5031 +#define ARM_1_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN1+0xFC)  /* IRQS pending for owner 1 */
5032 +#define ARM_1_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN1+0xF8)  /* ALL interrupts */
5033 +
5034 +/* Semaphores, Doorbells, Mailboxes Owner 2 */
5035 +#define ARM_2_SEMS       HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
5036 +#define ARM_2_SEM0       HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
5037 +#define ARM_2_SEM1       HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
5038 +#define ARM_2_SEM2       HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
5039 +#define ARM_2_SEM3       HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
5040 +#define ARM_2_SEM4       HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
5041 +#define ARM_2_SEM5       HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
5042 +#define ARM_2_SEM6       HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
5043 +#define ARM_2_SEM7       HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
5044 +#define ARM_2_BELL0      HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
5045 +#define ARM_2_BELL1      HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
5046 +#define ARM_2_BELL2      HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
5047 +#define ARM_2_BELL3      HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
5048 +/* MAILBOX 0 access in Owner 2 area */
5049 +/* Owner 2 should only WRITE to this mailbox */
5050 +#define ARM_2_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN2+0x80)   /* .. 0x8C (4 locations) */
5051 +/*#define ARM_2_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN2+0x80)  */ /* DO NOT USE THIS !!!!! */
5052 +/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90)  */ /* DO NOT USE THIS !!!!! */
5053 +/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94)  */ /* DO NOT USE THIS !!!!! */
5054 +#define ARM_2_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN2+0x98)   /* Status read */
5055 +/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C)  */ /* DO NOT USE THIS !!!!! */
5056 +/* MAILBOX 1 access in Owner 2 area */
5057 +/* Owner 2 should only WRITE to this mailbox */
5058 +#define ARM_2_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN2+0xA0)   /* .. 0xAC (4 locations) */
5059 +/*#define ARM_2_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
5060 +/*#define ARM_2_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
5061 +/*#define ARM_2_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
5062 +#define ARM_2_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN2+0xB8)   /* Status read */
5063 +/*#define ARM_2_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
5064 +/* General SEM, BELL, MAIL config/status */
5065 +#define ARM_2_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN2+0xE0)  /* semaphore clear/debug register */
5066 +#define ARM_2_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN2+0xE4)  /* Doorbells clear/debug register */
5067 +#define ARM_2_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN2+0xFC)  /* IRQS pending for owner 2 */
5068 +#define ARM_2_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN2+0xF8)  /* ALL interrupts */
5069 +
5070 +/* Semaphores, Doorbells, Mailboxes Owner 3 */
5071 +#define ARM_3_SEMS       HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
5072 +#define ARM_3_SEM0       HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
5073 +#define ARM_3_SEM1       HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
5074 +#define ARM_3_SEM2       HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
5075 +#define ARM_3_SEM3       HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
5076 +#define ARM_3_SEM4       HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
5077 +#define ARM_3_SEM5       HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
5078 +#define ARM_3_SEM6       HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
5079 +#define ARM_3_SEM7       HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
5080 +#define ARM_3_BELL0      HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
5081 +#define ARM_3_BELL1      HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
5082 +#define ARM_3_BELL2      HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
5083 +#define ARM_3_BELL3      HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
5084 +/* MAILBOX 0 access in Owner 3 area */
5085 +/* Owner 3 should only WRITE to this mailbox */
5086 +#define ARM_3_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN3+0x80)   /* .. 0x8C (4 locations) */
5087 +/*#define ARM_3_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN3+0x80)  */ /* DO NOT USE THIS !!!!! */
5088 +/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90)  */ /* DO NOT USE THIS !!!!! */
5089 +/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94)  */ /* DO NOT USE THIS !!!!! */
5090 +#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98)    /* Status read */
5091 +/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C)  */ /* DO NOT USE THIS !!!!! */
5092 +/* MAILBOX 1 access in Owner 3 area */
5093 +/* Owner 3 should only WRITE to this mailbox */
5094 +#define ARM_3_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN3+0xA0)   /* .. 0xAC (4 locations) */
5095 +/*#define ARM_3_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
5096 +/*#define ARM_3_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
5097 +/*#define ARM_3_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
5098 +#define ARM_3_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN3+0xB8)   /* Status read */
5099 +/*#define ARM_3_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
5100 +/* General SEM, BELL, MAIL config/status */
5101 +#define ARM_3_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN3+0xE0)  /* semaphore clear/debug register */
5102 +#define ARM_3_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN3+0xE4)  /* Doorbells clear/debug register */
5103 +#define ARM_3_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN3+0xFC)  /* IRQS pending for owner 3 */
5104 +#define ARM_3_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN3+0xF8)  /* ALL interrupts */
5105 +
5106 +
5107 +
5108 +/*  Mailbox flags. Valid for all owners */
5109 +
5110 +/* Mailbox status register (...0x98) */
5111 +#define ARM_MS_FULL       0x80000000
5112 +#define ARM_MS_EMPTY      0x40000000
5113 +#define ARM_MS_LEVEL      0x400000FF /* Max. value depdnds on mailbox depth parameter */
5114 +
5115 +/* MAILBOX config/status register (...0x9C) */
5116 +/* ANY write to this register clears the error bits! */
5117 +#define ARM_MC_IHAVEDATAIRQEN    0x00000001 /* mailbox irq enable:  has data */
5118 +#define ARM_MC_IHAVESPACEIRQEN   0x00000002 /* mailbox irq enable:  has space */
5119 +#define ARM_MC_OPPISEMPTYIRQEN   0x00000004 /* mailbox irq enable: Opp. is empty */
5120 +#define ARM_MC_MAIL_CLEAR        0x00000008 /* mailbox clear write 1, then  0 */
5121 +#define ARM_MC_IHAVEDATAIRQPEND  0x00000010 /* mailbox irq pending:  has space */
5122 +#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
5123 +#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
5124 +/* Bit 7 is unused */
5125 +#define ARM_MC_ERRNOOWN   0x00000100 /* error : none owner read from mailbox */
5126 +#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
5127 +#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
5128 +
5129 +/* Semaphore clear/debug register (...0xE0) */
5130 +#define ARM_SD_OWN0      0x00000003  /* Owner of sem 0 */
5131 +#define ARM_SD_OWN1      0x0000000C  /* Owner of sem 1 */
5132 +#define ARM_SD_OWN2      0x00000030  /* Owner of sem 2 */
5133 +#define ARM_SD_OWN3      0x000000C0  /* Owner of sem 3 */
5134 +#define ARM_SD_OWN4      0x00000300  /* Owner of sem 4 */
5135 +#define ARM_SD_OWN5      0x00000C00  /* Owner of sem 5 */
5136 +#define ARM_SD_OWN6      0x00003000  /* Owner of sem 6 */
5137 +#define ARM_SD_OWN7      0x0000C000  /* Owner of sem 7 */
5138 +#define ARM_SD_SEM0      0x00010000  /* Status of sem 0 */
5139 +#define ARM_SD_SEM1      0x00020000  /* Status of sem 1 */
5140 +#define ARM_SD_SEM2      0x00040000  /* Status of sem 2 */
5141 +#define ARM_SD_SEM3      0x00080000  /* Status of sem 3 */
5142 +#define ARM_SD_SEM4      0x00100000  /* Status of sem 4 */
5143 +#define ARM_SD_SEM5      0x00200000  /* Status of sem 5 */
5144 +#define ARM_SD_SEM6      0x00400000  /* Status of sem 6 */
5145 +#define ARM_SD_SEM7      0x00800000  /* Status of sem 7 */
5146 +
5147 +/* Doorbells clear/debug register (...0xE4) */
5148 +#define ARM_BD_OWN0      0x00000003  /* Owner of doorbell 0 */
5149 +#define ARM_BD_OWN1      0x0000000C  /* Owner of doorbell 1 */
5150 +#define ARM_BD_OWN2      0x00000030  /* Owner of doorbell 2 */
5151 +#define ARM_BD_OWN3      0x000000C0  /* Owner of doorbell 3 */
5152 +#define ARM_BD_BELL0     0x00000100  /* Status of doorbell 0 */
5153 +#define ARM_BD_BELL1     0x00000200  /* Status of doorbell 1 */
5154 +#define ARM_BD_BELL2     0x00000400  /* Status of doorbell 2 */
5155 +#define ARM_BD_BELL3     0x00000800  /* Status of doorbell 3 */
5156 +
5157 +/* MY IRQS register (...0xF8) */
5158 +#define ARM_MYIRQ_BELL   0x00000001  /* This owner has a doorbell IRQ */
5159 +#define ARM_MYIRQ_MAIL   0x00000002  /* This owner has a mailbox  IRQ */
5160 +
5161 +/* ALL IRQS register (...0xF8) */
5162 +#define ARM_AIS_BELL0 0x00000001  /* Doorbell 0 IRQ pending */
5163 +#define ARM_AIS_BELL1 0x00000002  /* Doorbell 1 IRQ pending */
5164 +#define ARM_AIS_BELL2 0x00000004  /* Doorbell 2 IRQ pending */
5165 +#define ARM_AIS_BELL3 0x00000008  /* Doorbell 3 IRQ pending */
5166 +#define ARM_AIS0_HAVEDATA 0x00000010  /* MAIL 0 has data IRQ pending */
5167 +#define ARM_AIS0_HAVESPAC 0x00000020  /* MAIL 0 has space IRQ pending */
5168 +#define ARM_AIS0_OPPEMPTY 0x00000040  /* MAIL 0 opposite is empty IRQ */
5169 +#define ARM_AIS1_HAVEDATA 0x00000080  /* MAIL 1 has data IRQ pending */
5170 +#define ARM_AIS1_HAVESPAC 0x00000100  /* MAIL 1 has space IRQ pending */
5171 +#define ARM_AIS1_OPPEMPTY 0x00000200  /* MAIL 1 opposite is empty IRQ */
5172 +/* Note   that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
5173 +/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
5174 +/* */
5175 +/* ARM JTAG BASH */
5176 +/* */
5177 +#define AJB_BASE 0x7e2000c0
5178 +
5179 +#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
5180 +#define   AJB_BITS0    0x000000
5181 +#define   AJB_BITS4    0x000004
5182 +#define   AJB_BITS8    0x000008
5183 +#define   AJB_BITS12   0x00000C
5184 +#define   AJB_BITS16   0x000010
5185 +#define   AJB_BITS20   0x000014
5186 +#define   AJB_BITS24   0x000018
5187 +#define   AJB_BITS28   0x00001C
5188 +#define   AJB_BITS32   0x000020
5189 +#define   AJB_BITS34   0x000022
5190 +#define   AJB_OUT_MS   0x000040
5191 +#define   AJB_OUT_LS   0x000000
5192 +#define   AJB_INV_CLK  0x000080
5193 +#define   AJB_D0_RISE  0x000100
5194 +#define   AJB_D0_FALL  0x000000
5195 +#define   AJB_D1_RISE  0x000200
5196 +#define   AJB_D1_FALL  0x000000
5197 +#define   AJB_IN_RISE  0x000400
5198 +#define   AJB_IN_FALL  0x000000
5199 +#define   AJB_ENABLE   0x000800
5200 +#define   AJB_HOLD0    0x000000
5201 +#define   AJB_HOLD1    0x001000
5202 +#define   AJB_HOLD2    0x002000
5203 +#define   AJB_HOLD3    0x003000
5204 +#define   AJB_RESETN   0x004000
5205 +#define   AJB_CLKSHFT  16
5206 +#define   AJB_BUSY     0x80000000
5207 +#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
5208 +#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
5209 +#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
5210 +
5211 +#endif
5212 --- /dev/null
5213 +++ b/arch/arm/mach-bcm2708/include/mach/arm_power.h
5214 @@ -0,0 +1,60 @@
5215 +/*
5216 + *  linux/arch/arm/mach-bcm2708/include/mach/arm_power.h
5217 + *
5218 + *  Copyright (C) 2010 Broadcom
5219 + *
5220 + * This program is free software; you can redistribute it and/or modify
5221 + * it under the terms of the GNU General Public License as published by
5222 + * the Free Software Foundation; either version 2 of the License, or
5223 + * (at your option) any later version.
5224 + *
5225 + * This program is distributed in the hope that it will be useful,
5226 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5227 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5228 + * GNU General Public License for more details.
5229 + *
5230 + * You should have received a copy of the GNU General Public License
5231 + * along with this program; if not, write to the Free Software
5232 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5233 + */
5234 +
5235 +#ifndef _ARM_POWER_H
5236 +#define _ARM_POWER_H
5237 +
5238 +/* Use meaningful names on each side */
5239 +#ifdef __VIDEOCORE__
5240 +#define PREFIX(x) ARM_##x
5241 +#else
5242 +#define PREFIX(x) BCM_##x
5243 +#endif
5244 +
5245 +enum {
5246 +       PREFIX(POWER_SDCARD_BIT),
5247 +       PREFIX(POWER_UART_BIT),
5248 +       PREFIX(POWER_MINIUART_BIT),
5249 +       PREFIX(POWER_USB_BIT),
5250 +       PREFIX(POWER_I2C0_BIT),
5251 +       PREFIX(POWER_I2C1_BIT),
5252 +       PREFIX(POWER_I2C2_BIT),
5253 +       PREFIX(POWER_SPI_BIT),
5254 +       PREFIX(POWER_CCP2TX_BIT),
5255 +
5256 +       PREFIX(POWER_MAX)
5257 +};
5258 +
5259 +enum {
5260 +       PREFIX(POWER_SDCARD) = (1 << PREFIX(POWER_SDCARD_BIT)),
5261 +       PREFIX(POWER_UART) = (1 << PREFIX(POWER_UART_BIT)),
5262 +       PREFIX(POWER_MINIUART) = (1 << PREFIX(POWER_MINIUART_BIT)),
5263 +       PREFIX(POWER_USB) = (1 << PREFIX(POWER_USB_BIT)),
5264 +       PREFIX(POWER_I2C0) = (1 << PREFIX(POWER_I2C0_BIT)),
5265 +       PREFIX(POWER_I2C1_MASK) = (1 << PREFIX(POWER_I2C1_BIT)),
5266 +       PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)),
5267 +       PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)),
5268 +       PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)),
5269 +
5270 +       PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1,
5271 +       PREFIX(POWER_NONE) = 0
5272 +};
5273 +
5274 +#endif
5275 --- /dev/null
5276 +++ b/arch/arm/mach-bcm2708/include/mach/clkdev.h
5277 @@ -0,0 +1,7 @@
5278 +#ifndef __ASM_MACH_CLKDEV_H
5279 +#define __ASM_MACH_CLKDEV_H
5280 +
5281 +#define __clk_get(clk) ({ 1; })
5282 +#define __clk_put(clk) do { } while (0)
5283 +
5284 +#endif
5285 --- /dev/null
5286 +++ b/arch/arm/mach-bcm2708/include/mach/debug-macro.S
5287 @@ -0,0 +1,24 @@
5288 +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
5289 + *
5290 + * Debugging macro include header
5291 + *
5292 + *  Copyright (C) 2010 Broadcom
5293 + *  Copyright (C) 1994-1999 Russell King
5294 + *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
5295 + *
5296 + * This program is free software; you can redistribute it and/or modify
5297 + * it under the terms of the GNU General Public License version 2 as
5298 + * published by the Free Software Foundation.
5299 + *
5300 +*/
5301 +
5302 +               .macro  addruart, rx, tmp
5303 +               mrc     p15, 0, \rx, c1, c0
5304 +               tst     \rx, #1                 @ MMU enabled?
5305 +               moveq   \rx,      #0x08000000
5306 +               movne   \rx,      #0xf8000000   @ virtual base
5307 +               orr     \rx, \rx, #0x00200000
5308 +               orr     \rx, \rx, #0x00001000
5309 +               .endm
5310 +
5311 +#include <asm/hardware/debug-pl01x.S>
5312 --- /dev/null
5313 +++ b/arch/arm/mach-bcm2708/include/mach/dma.h
5314 @@ -0,0 +1,84 @@
5315 +/*
5316 + *  linux/arch/arm/mach-bcm2708/include/mach/dma.h
5317 + *
5318 + *  Copyright (C) 2010 Broadcom
5319 + *
5320 + * This program is free software; you can redistribute it and/or modify
5321 + * it under the terms of the GNU General Public License version 2 as
5322 + * published by the Free Software Foundation.
5323 + */
5324 +
5325 +
5326 +#ifndef _MACH_BCM2708_DMA_H
5327 +#define _MACH_BCM2708_DMA_H
5328 +
5329 +#define BCM_DMAMAN_DRIVER_NAME "bcm2708_dma"
5330 +
5331 +/* DMA CS Control and Status bits */
5332 +#define BCM2708_DMA_ACTIVE     (1 << 0)
5333 +#define BCM2708_DMA_INT                (1 << 2)
5334 +#define BCM2708_DMA_ISPAUSED   (1 << 4)  /* Pause requested or not active */
5335 +#define BCM2708_DMA_ISHELD     (1 << 5)  /* Is held by DREQ flow control */
5336 +#define BCM2708_DMA_ERR                (1 << 8)
5337 +#define BCM2708_DMA_ABORT      (1 << 30) /* stop current CB, go to next, WO */
5338 +#define BCM2708_DMA_RESET      (1 << 31) /* WO, self clearing */
5339 +
5340 +/* DMA control block "info" field bits */
5341 +#define BCM2708_DMA_INT_EN     (1 << 0)
5342 +#define BCM2708_DMA_TDMODE     (1 << 1)
5343 +#define BCM2708_DMA_WAIT_RESP  (1 << 3)
5344 +#define BCM2708_DMA_D_INC      (1 << 4)
5345 +#define BCM2708_DMA_D_WIDTH    (1 << 5)
5346 +#define BCM2708_DMA_D_DREQ     (1 << 6)
5347 +#define BCM2708_DMA_S_INC      (1 << 8)
5348 +#define BCM2708_DMA_S_WIDTH    (1 << 9)
5349 +#define BCM2708_DMA_S_DREQ     (1 << 10)
5350 +
5351 +#define        BCM2708_DMA_BURST(x)    (((x)&0xf) << 12)
5352 +#define        BCM2708_DMA_PER_MAP(x)  ((x) << 16)
5353 +#define        BCM2708_DMA_WAITS(x)    (((x)&0x1f) << 21)
5354 +
5355 +#define BCM2708_DMA_DREQ_EMMC  11
5356 +#define BCM2708_DMA_DREQ_SDHOST        13
5357 +
5358 +#define BCM2708_DMA_CS         0x00 /* Control and Status */
5359 +#define BCM2708_DMA_ADDR       0x04
5360 +/* the current control block appears in the following registers - read only */
5361 +#define BCM2708_DMA_INFO       0x08
5362 +#define BCM2708_DMA_NEXTCB     0x1C
5363 +#define BCM2708_DMA_DEBUG      0x20
5364 +
5365 +#define BCM2708_DMA4_CS                (BCM2708_DMA_CHAN(4)+BCM2708_DMA_CS)
5366 +#define BCM2708_DMA4_ADDR      (BCM2708_DMA_CHAN(4)+BCM2708_DMA_ADDR)
5367 +
5368 +#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
5369 +
5370 +struct bcm2708_dma_cb {
5371 +       unsigned long info;
5372 +       unsigned long src;
5373 +       unsigned long dst;
5374 +       unsigned long length;
5375 +       unsigned long stride;
5376 +       unsigned long next;
5377 +       unsigned long pad[2];
5378 +};
5379 +
5380 +extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
5381 +extern void bcm_dma_start(void __iomem *dma_chan_base,
5382 +                         dma_addr_t control_block);
5383 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base);
5384 +extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base);
5385 +
5386 +/* When listing features we can ask for when allocating DMA channels give
5387 +   those with higher priority smaller ordinal numbers */
5388 +#define BCM_DMA_FEATURE_FAST_ORD 0
5389 +#define BCM_DMA_FEATURE_FAST    (1<<BCM_DMA_FEATURE_FAST_ORD)
5390 +#define BCM_DMA_FEATURE_COUNT   1
5391 +
5392 +/* return channel no or -ve error */
5393 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
5394 +                             void __iomem **out_dma_base, int *out_dma_irq);
5395 +extern int bcm_dma_chan_free(int channel);
5396 +
5397 +
5398 +#endif /* _MACH_BCM2708_DMA_H */
5399 --- /dev/null
5400 +++ b/arch/arm/mach-bcm2708/include/mach/entry-macro.S
5401 @@ -0,0 +1,69 @@
5402 +/*
5403 + * arch/arm/mach-bcm2708/include/mach/entry-macro.S
5404 + *
5405 + * Low-level IRQ helper macros for BCM2708 platforms
5406 + *
5407 + *  Copyright (C) 2010 Broadcom
5408 + *
5409 + * This program is free software; you can redistribute it and/or modify
5410 + * it under the terms of the GNU General Public License as published by
5411 + * the Free Software Foundation; either version 2 of the License, or
5412 + * (at your option) any later version.
5413 + *
5414 + * This program is distributed in the hope that it will be useful,
5415 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5416 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5417 + * GNU General Public License for more details.
5418 + *
5419 + * You should have received a copy of the GNU General Public License
5420 + * along with this program; if not, write to the Free Software
5421 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5422 + */
5423 +#include <mach/hardware.h>
5424 +
5425 +               .macro  disable_fiq
5426 +               .endm
5427 +
5428 +               .macro  get_irqnr_preamble, base, tmp
5429 +               ldr     \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
5430 +               .endm
5431 +
5432 +               .macro  arch_ret_to_user, tmp1, tmp2
5433 +               .endm
5434 +
5435 +               .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
5436 +               /* get masked status */
5437 +               ldr     \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
5438 +               mov     \irqnr, #(ARM_IRQ0_BASE + 31)
5439 +               and     \tmp, \irqstat, #0x300           @ save bits 8 and 9
5440 +               /* clear bits 8 and 9, and test */
5441 +               bics    \irqstat, \irqstat, #0x300
5442 +               bne     1010f
5443 +
5444 +               tst     \tmp, #0x100
5445 +               ldrne   \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
5446 +               movne \irqnr, #(ARM_IRQ1_BASE + 31)
5447 +               @ Mask out the interrupts also present in PEND0 - see SW-5809
5448 +               bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
5449 +               bicne \irqstat, #((1<<18) | (1<<19))
5450 +               bne     1010f
5451 +
5452 +               tst     \tmp, #0x200
5453 +               ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
5454 +               movne \irqnr, #(ARM_IRQ2_BASE + 31)
5455 +               @ Mask out the interrupts also present in PEND0 - see SW-5809
5456 +               bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
5457 +               bicne \irqstat, #((1<<30))
5458 +               beq 1020f
5459 +
5460 +1010:
5461 +               @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
5462 +               @ N.B. CLZ is an ARM5 instruction.
5463 +               sub     \tmp, \irqstat, #1
5464 +               eor     \irqstat, \irqstat, \tmp
5465 +               clz     \tmp, \irqstat
5466 +               sub     \irqnr, \tmp
5467 +
5468 +1020:  @ EQ will be set if no irqs pending
5469 +
5470 +               .endm
5471 --- /dev/null
5472 +++ b/arch/arm/mach-bcm2708/include/mach/frc.h
5473 @@ -0,0 +1,38 @@
5474 +/*
5475 + *  arch/arm/mach-bcm2708/include/mach/timex.h
5476 + *
5477 + *  BCM2708 free running counter (timer)
5478 + *
5479 + *  Copyright (C) 2010 Broadcom
5480 + *
5481 + * This program is free software; you can redistribute it and/or modify
5482 + * it under the terms of the GNU General Public License as published by
5483 + * the Free Software Foundation; either version 2 of the License, or
5484 + * (at your option) any later version.
5485 + *
5486 + * This program is distributed in the hope that it will be useful,
5487 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5488 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5489 + * GNU General Public License for more details.
5490 + *
5491 + * You should have received a copy of the GNU General Public License
5492 + * along with this program; if not, write to the Free Software
5493 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5494 + */
5495 +
5496 +#ifndef _MACH_FRC_H
5497 +#define _MACH_FRC_H
5498 +
5499 +#define FRC_TICK_RATE          (1000000)
5500 +
5501 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
5502 +    (slightly faster than frc_clock_ticks63()
5503 + */
5504 +extern unsigned long frc_clock_ticks32(void);
5505 +
5506 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
5507 + *  Note - top bit should be ignored (see cnt32_to_63)
5508 + */
5509 +extern unsigned long long frc_clock_ticks63(void);
5510 +
5511 +#endif
5512 --- /dev/null
5513 +++ b/arch/arm/mach-bcm2708/include/mach/gpio.h
5514 @@ -0,0 +1,48 @@
5515 +/*
5516 + * arch/arm/mach-bcm2708/include/mach/gpio.h
5517 + *
5518 + * This file is licensed under the terms of the GNU General Public
5519 + * License version 2.  This program is licensed "as is" without any
5520 + * warranty of any kind, whether express or implied.
5521 + */
5522 +
5523 +#ifndef __ASM_ARCH_GPIO_H
5524 +#define __ASM_ARCH_GPIO_H
5525 +
5526 +#define ARCH_NR_GPIOS 54 // number of gpio lines
5527 +
5528 +#include <asm-generic/gpio.h>
5529 +
5530 +
5531 +#ifdef CONFIG_GPIOLIB
5532 +
5533 +static inline int gpio_get_value(unsigned gpio)
5534 +{
5535 +        return __gpio_get_value(gpio);
5536 +}
5537 +
5538 +static inline void gpio_set_value(unsigned gpio, int value)
5539 +{
5540 +        __gpio_set_value(gpio, value);
5541 +}
5542 +
5543 +static inline int gpio_cansleep(unsigned gpio)
5544 +{
5545 +        return __gpio_cansleep(gpio);
5546 +}
5547 +
5548 +static inline int gpio_to_irq(unsigned gpio)
5549 +{
5550 +        WARN_ON(1);
5551 +        return -ENOSYS;
5552 +}
5553 +
5554 +static inline int irq_to_gpio(unsigned int irq)
5555 +{
5556 +        WARN_ON(1);
5557 +        return -EINVAL;
5558 +}
5559 +
5560 +#endif /* CONFIG_GPIOLIB */
5561 +
5562 +#endif
5563 --- /dev/null
5564 +++ b/arch/arm/mach-bcm2708/include/mach/hardware.h
5565 @@ -0,0 +1,28 @@
5566 +/*
5567 + *  arch/arm/mach-bcm2708/include/mach/hardware.h
5568 + *
5569 + *  This file contains the hardware definitions of the BCM2708 devices.
5570 + *
5571 + *  Copyright (C) 2010 Broadcom
5572 + *
5573 + * This program is free software; you can redistribute it and/or modify
5574 + * it under the terms of the GNU General Public License as published by
5575 + * the Free Software Foundation; either version 2 of the License, or
5576 + * (at your option) any later version.
5577 + *
5578 + * This program is distributed in the hope that it will be useful,
5579 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5580 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5581 + * GNU General Public License for more details.
5582 + *
5583 + * You should have received a copy of the GNU General Public License
5584 + * along with this program; if not, write to the Free Software
5585 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5586 + */
5587 +#ifndef __ASM_ARCH_HARDWARE_H
5588 +#define __ASM_ARCH_HARDWARE_H
5589 +
5590 +#include <asm/sizes.h>
5591 +#include <mach/platform.h>
5592 +
5593 +#endif
5594 --- /dev/null
5595 +++ b/arch/arm/mach-bcm2708/include/mach/io.h
5596 @@ -0,0 +1,28 @@
5597 +/*
5598 + *  arch/arm/mach-bcm2708/include/mach/io.h
5599 + *
5600 + *  Copyright (C) 2003 ARM Limited
5601 + *
5602 + * This program is free software; you can redistribute it and/or modify
5603 + * it under the terms of the GNU General Public License as published by
5604 + * the Free Software Foundation; either version 2 of the License, or
5605 + * (at your option) any later version.
5606 + *
5607 + * This program is distributed in the hope that it will be useful,
5608 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5609 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5610 + * GNU General Public License for more details.
5611 + *
5612 + * You should have received a copy of the GNU General Public License
5613 + * along with this program; if not, write to the Free Software
5614 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5615 + */
5616 +#ifndef __ASM_ARM_ARCH_IO_H
5617 +#define __ASM_ARM_ARCH_IO_H
5618 +
5619 +#define IO_SPACE_LIMIT 0xffffffff
5620 +
5621 +#define __io(a)                __typesafe_io(a)
5622 +#define __mem_pci(a)   (a)
5623 +
5624 +#endif
5625 --- /dev/null
5626 +++ b/arch/arm/mach-bcm2708/include/mach/irqs.h
5627 @@ -0,0 +1,190 @@
5628 +/*
5629 + *  arch/arm/mach-bcm2708/include/mach/irqs.h
5630 + *
5631 + *  Copyright (C) 2010 Broadcom
5632 + *  Copyright (C) 2003 ARM Limited
5633 + *  Copyright (C) 2000 Deep Blue Solutions Ltd.
5634 + *
5635 + * This program is free software; you can redistribute it and/or modify
5636 + * it under the terms of the GNU General Public License as published by
5637 + * the Free Software Foundation; either version 2 of the License, or
5638 + * (at your option) any later version.
5639 + *
5640 + * This program is distributed in the hope that it will be useful,
5641 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5642 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5643 + * GNU General Public License for more details.
5644 + *
5645 + * You should have received a copy of the GNU General Public License
5646 + * along with this program; if not, write to the Free Software
5647 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5648 + */
5649 +
5650 +#ifndef _BCM2708_IRQS_H_
5651 +#define _BCM2708_IRQS_H_
5652 +
5653 +#include <mach/platform.h>
5654 +
5655 +/*
5656 + *  IRQ interrupts definitions are the same as the INT definitions
5657 + *  held within platform.h
5658 + */
5659 +#define IRQ_ARMCTRL_START     0
5660 +#define IRQ_TIMER0            (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
5661 +#define IRQ_TIMER1            (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
5662 +#define IRQ_TIMER2            (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
5663 +#define IRQ_TIMER3            (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
5664 +#define IRQ_CODEC0            (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
5665 +#define IRQ_CODEC1            (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
5666 +#define IRQ_CODEC2            (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
5667 +#define IRQ_JPEG              (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
5668 +#define IRQ_ISP               (IRQ_ARMCTRL_START + INTERRUPT_ISP)
5669 +#define IRQ_USB               (IRQ_ARMCTRL_START + INTERRUPT_USB)
5670 +#define IRQ_3D                (IRQ_ARMCTRL_START + INTERRUPT_3D)
5671 +#define IRQ_TRANSPOSER        (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
5672 +#define IRQ_MULTICORESYNC0    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
5673 +#define IRQ_MULTICORESYNC1    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
5674 +#define IRQ_MULTICORESYNC2    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
5675 +#define IRQ_MULTICORESYNC3    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
5676 +#define IRQ_DMA0              (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
5677 +#define IRQ_DMA1              (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
5678 +#define IRQ_DMA2              (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
5679 +#define IRQ_DMA3              (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
5680 +#define IRQ_DMA4              (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
5681 +#define IRQ_DMA5              (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
5682 +#define IRQ_DMA6              (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
5683 +#define IRQ_DMA7              (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
5684 +#define IRQ_DMA8              (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
5685 +#define IRQ_DMA9              (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
5686 +#define IRQ_DMA10             (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
5687 +#define IRQ_DMA11             (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
5688 +#define IRQ_DMA12             (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
5689 +#define IRQ_AUX               (IRQ_ARMCTRL_START + INTERRUPT_AUX)
5690 +#define IRQ_ARM               (IRQ_ARMCTRL_START + INTERRUPT_ARM)
5691 +#define IRQ_VPUDMA            (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
5692 +#define IRQ_HOSTPORT          (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
5693 +#define IRQ_VIDEOSCALER       (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
5694 +#define IRQ_CCP2TX            (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
5695 +#define IRQ_SDC               (IRQ_ARMCTRL_START + INTERRUPT_SDC)
5696 +#define IRQ_DSI0              (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
5697 +#define IRQ_AVE               (IRQ_ARMCTRL_START + INTERRUPT_AVE)
5698 +#define IRQ_CAM0              (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
5699 +#define IRQ_CAM1              (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
5700 +#define IRQ_HDMI0             (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
5701 +#define IRQ_HDMI1             (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
5702 +#define IRQ_PIXELVALVE1       (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
5703 +#define IRQ_I2CSPISLV         (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
5704 +#define IRQ_DSI1              (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
5705 +#define IRQ_PWA0              (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
5706 +#define IRQ_PWA1              (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
5707 +#define IRQ_CPR               (IRQ_ARMCTRL_START + INTERRUPT_CPR)
5708 +#define IRQ_SMI               (IRQ_ARMCTRL_START + INTERRUPT_SMI)
5709 +#define IRQ_GPIO0             (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
5710 +#define IRQ_GPIO1             (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
5711 +#define IRQ_GPIO2             (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
5712 +#define IRQ_GPIO3             (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
5713 +#define IRQ_I2C               (IRQ_ARMCTRL_START + INTERRUPT_I2C)
5714 +#define IRQ_SPI               (IRQ_ARMCTRL_START + INTERRUPT_SPI)
5715 +#define IRQ_I2SPCM            (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
5716 +#define IRQ_SDIO              (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
5717 +#define IRQ_UART              (IRQ_ARMCTRL_START + INTERRUPT_UART)
5718 +#define IRQ_SLIMBUS           (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
5719 +#define IRQ_VEC               (IRQ_ARMCTRL_START + INTERRUPT_VEC)
5720 +#define IRQ_CPG               (IRQ_ARMCTRL_START + INTERRUPT_CPG)
5721 +#define IRQ_RNG               (IRQ_ARMCTRL_START + INTERRUPT_RNG)
5722 +#define IRQ_ARASANSDIO        (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
5723 +#define IRQ_AVSPMON           (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
5724 +
5725 +#define IRQ_ARM_TIMER         (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
5726 +#define IRQ_ARM_MAILBOX       (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
5727 +#define IRQ_ARM_DOORBELL_0    (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
5728 +#define IRQ_ARM_DOORBELL_1    (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
5729 +#define IRQ_VPU0_HALTED       (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
5730 +#define IRQ_VPU1_HALTED       (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
5731 +#define IRQ_ILLEGAL_TYPE0     (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
5732 +#define IRQ_ILLEGAL_TYPE1     (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
5733 +#define IRQ_PENDING1          (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
5734 +#define IRQ_PENDING2          (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
5735 +
5736 +/*
5737 + *  FIQ interrupts definitions are the same as the INT definitions.
5738 + */
5739 +#define FIQ_TIMER0            INT_TIMER0
5740 +#define FIQ_TIMER1            INT_TIMER1
5741 +#define FIQ_TIMER2            INT_TIMER2
5742 +#define FIQ_TIMER3            INT_TIMER3
5743 +#define FIQ_CODEC0            INT_CODEC0
5744 +#define FIQ_CODEC1            INT_CODEC1
5745 +#define FIQ_CODEC2            INT_CODEC2
5746 +#define FIQ_JPEG              INT_JPEG
5747 +#define FIQ_ISP               INT_ISP
5748 +#define FIQ_USB               INT_USB
5749 +#define FIQ_3D                INT_3D
5750 +#define FIQ_TRANSPOSER        INT_TRANSPOSER
5751 +#define FIQ_MULTICORESYNC0    INT_MULTICORESYNC0
5752 +#define FIQ_MULTICORESYNC1    INT_MULTICORESYNC1
5753 +#define FIQ_MULTICORESYNC2    INT_MULTICORESYNC2
5754 +#define FIQ_MULTICORESYNC3    INT_MULTICORESYNC3
5755 +#define FIQ_DMA0              INT_DMA0
5756 +#define FIQ_DMA1              INT_DMA1
5757 +#define FIQ_DMA2              INT_DMA2
5758 +#define FIQ_DMA3              INT_DMA3
5759 +#define FIQ_DMA4              INT_DMA4
5760 +#define FIQ_DMA5              INT_DMA5
5761 +#define FIQ_DMA6              INT_DMA6
5762 +#define FIQ_DMA7              INT_DMA7
5763 +#define FIQ_DMA8              INT_DMA8
5764 +#define FIQ_DMA9              INT_DMA9
5765 +#define FIQ_DMA10             INT_DMA10
5766 +#define FIQ_DMA11             INT_DMA11
5767 +#define FIQ_DMA12             INT_DMA12
5768 +#define FIQ_AUX               INT_AUX
5769 +#define FIQ_ARM               INT_ARM
5770 +#define FIQ_VPUDMA            INT_VPUDMA
5771 +#define FIQ_HOSTPORT          INT_HOSTPORT
5772 +#define FIQ_VIDEOSCALER       INT_VIDEOSCALER
5773 +#define FIQ_CCP2TX            INT_CCP2TX
5774 +#define FIQ_SDC               INT_SDC
5775 +#define FIQ_DSI0              INT_DSI0
5776 +#define FIQ_AVE               INT_AVE
5777 +#define FIQ_CAM0              INT_CAM0
5778 +#define FIQ_CAM1              INT_CAM1
5779 +#define FIQ_HDMI0             INT_HDMI0
5780 +#define FIQ_HDMI1             INT_HDMI1
5781 +#define FIQ_PIXELVALVE1       INT_PIXELVALVE1
5782 +#define FIQ_I2CSPISLV         INT_I2CSPISLV
5783 +#define FIQ_DSI1              INT_DSI1
5784 +#define FIQ_PWA0              INT_PWA0
5785 +#define FIQ_PWA1              INT_PWA1
5786 +#define FIQ_CPR               INT_CPR
5787 +#define FIQ_SMI               INT_SMI
5788 +#define FIQ_GPIO0             INT_GPIO0
5789 +#define FIQ_GPIO1             INT_GPIO1
5790 +#define FIQ_GPIO2             INT_GPIO2
5791 +#define FIQ_GPIO3             INT_GPIO3
5792 +#define FIQ_I2C               INT_I2C
5793 +#define FIQ_SPI               INT_SPI
5794 +#define FIQ_I2SPCM            INT_I2SPCM
5795 +#define FIQ_SDIO              INT_SDIO
5796 +#define FIQ_UART              INT_UART
5797 +#define FIQ_SLIMBUS           INT_SLIMBUS
5798 +#define FIQ_VEC               INT_VEC
5799 +#define FIQ_CPG               INT_CPG
5800 +#define FIQ_RNG               INT_RNG
5801 +#define FIQ_ARASANSDIO        INT_ARASANSDIO
5802 +#define FIQ_AVSPMON           INT_AVSPMON
5803 +
5804 +#define FIQ_ARM_TIMER         INT_ARM_TIMER
5805 +#define FIQ_ARM_MAILBOX       INT_ARM_MAILBOX
5806 +#define FIQ_ARM_DOORBELL_0    INT_ARM_DOORBELL_0
5807 +#define FIQ_ARM_DOORBELL_1    INT_ARM_DOORBELL_1
5808 +#define FIQ_VPU0_HALTED       INT_VPU0_HALTED
5809 +#define FIQ_VPU1_HALTED       INT_VPU1_HALTED
5810 +#define FIQ_ILLEGAL_TYPE0     INT_ILLEGAL_TYPE0
5811 +#define FIQ_ILLEGAL_TYPE1     INT_ILLEGAL_TYPE1
5812 +#define FIQ_PENDING1          INT_PENDING1
5813 +#define FIQ_PENDING2          INT_PENDING2
5814 +
5815 +#define NR_IRQS                              (64 + 21)
5816 +
5817 +#endif /* _BCM2708_IRQS_H_ */
5818 --- /dev/null
5819 +++ b/arch/arm/mach-bcm2708/include/mach/irqs.h.orig
5820 @@ -0,0 +1,185 @@
5821 +/*
5822 + *  arch/arm/mach-bcm2708/include/mach/irqs.h
5823 + *
5824 + *  Copyright (C) 2010 Broadcom
5825 + *  Copyright (C) 2003 ARM Limited
5826 + *  Copyright (C) 2000 Deep Blue Solutions Ltd.
5827 + *
5828 + * This program is free software; you can redistribute it and/or modify
5829 + * it under the terms of the GNU General Public License as published by
5830 + * the Free Software Foundation; either version 2 of the License, or
5831 + * (at your option) any later version.
5832 + *
5833 + * This program is distributed in the hope that it will be useful,
5834 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5835 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5836 + * GNU General Public License for more details.
5837 + *
5838 + * You should have received a copy of the GNU General Public License
5839 + * along with this program; if not, write to the Free Software
5840 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5841 + */
5842 +
5843 +#include <mach/platform.h>
5844 +
5845 +/*
5846 + *  IRQ interrupts definitions are the same as the INT definitions
5847 + *  held within platform.h
5848 + */
5849 +#define IRQ_ARMCTRL_START     0
5850 +#define IRQ_TIMER0            (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
5851 +#define IRQ_TIMER1            (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
5852 +#define IRQ_TIMER2            (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
5853 +#define IRQ_TIMER3            (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
5854 +#define IRQ_CODEC0            (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
5855 +#define IRQ_CODEC1            (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
5856 +#define IRQ_CODEC2            (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
5857 +#define IRQ_JPEG              (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
5858 +#define IRQ_ISP               (IRQ_ARMCTRL_START + INTERRUPT_ISP)
5859 +#define IRQ_USB               (IRQ_ARMCTRL_START + INTERRUPT_USB)
5860 +#define IRQ_3D                (IRQ_ARMCTRL_START + INTERRUPT_3D)
5861 +#define IRQ_TRANSPOSER        (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
5862 +#define IRQ_MULTICORESYNC0    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
5863 +#define IRQ_MULTICORESYNC1    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
5864 +#define IRQ_MULTICORESYNC2    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
5865 +#define IRQ_MULTICORESYNC3    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
5866 +#define IRQ_DMA0              (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
5867 +#define IRQ_DMA1              (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
5868 +#define IRQ_DMA2              (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
5869 +#define IRQ_DMA3              (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
5870 +#define IRQ_DMA4              (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
5871 +#define IRQ_DMA5              (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
5872 +#define IRQ_DMA6              (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
5873 +#define IRQ_DMA7              (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
5874 +#define IRQ_DMA8              (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
5875 +#define IRQ_DMA9              (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
5876 +#define IRQ_DMA10             (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
5877 +#define IRQ_DMA11             (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
5878 +#define IRQ_DMA12             (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
5879 +#define IRQ_AUX               (IRQ_ARMCTRL_START + INTERRUPT_AUX)
5880 +#define IRQ_ARM               (IRQ_ARMCTRL_START + INTERRUPT_ARM)
5881 +#define IRQ_VPUDMA            (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
5882 +#define IRQ_HOSTPORT          (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
5883 +#define IRQ_VIDEOSCALER       (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
5884 +#define IRQ_CCP2TX            (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
5885 +#define IRQ_SDC               (IRQ_ARMCTRL_START + INTERRUPT_SDC)
5886 +#define IRQ_DSI0              (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
5887 +#define IRQ_AVE               (IRQ_ARMCTRL_START + INTERRUPT_AVE)
5888 +#define IRQ_CAM0              (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
5889 +#define IRQ_CAM1              (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
5890 +#define IRQ_HDMI0             (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
5891 +#define IRQ_HDMI1             (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
5892 +#define IRQ_PIXELVALVE1       (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
5893 +#define IRQ_I2CSPISLV         (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
5894 +#define IRQ_DSI1              (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
5895 +#define IRQ_PWA0              (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
5896 +#define IRQ_PWA1              (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
5897 +#define IRQ_CPR               (IRQ_ARMCTRL_START + INTERRUPT_CPR)
5898 +#define IRQ_SMI               (IRQ_ARMCTRL_START + INTERRUPT_SMI)
5899 +#define IRQ_GPIO0             (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
5900 +#define IRQ_GPIO1             (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
5901 +#define IRQ_GPIO2             (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
5902 +#define IRQ_GPIO3             (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
5903 +#define IRQ_I2C               (IRQ_ARMCTRL_START + INTERRUPT_I2C)
5904 +#define IRQ_SPI               (IRQ_ARMCTRL_START + INTERRUPT_SPI)
5905 +#define IRQ_I2SPCM            (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
5906 +#define IRQ_SDIO              (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
5907 +#define IRQ_UART              (IRQ_ARMCTRL_START + INTERRUPT_UART)
5908 +#define IRQ_SLIMBUS           (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
5909 +#define IRQ_VEC               (IRQ_ARMCTRL_START + INTERRUPT_VEC)
5910 +#define IRQ_CPG               (IRQ_ARMCTRL_START + INTERRUPT_CPG)
5911 +#define IRQ_RNG               (IRQ_ARMCTRL_START + INTERRUPT_RNG)
5912 +#define IRQ_ARASANSDIO        (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
5913 +#define IRQ_AVSPMON           (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
5914 +
5915 +#define IRQ_ARM_TIMER         (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
5916 +#define IRQ_ARM_MAILBOX       (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
5917 +#define IRQ_ARM_DOORBELL_0    (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
5918 +#define IRQ_ARM_DOORBELL_1    (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
5919 +#define IRQ_VPU0_HALTED       (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
5920 +#define IRQ_VPU1_HALTED       (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
5921 +#define IRQ_ILLEGAL_TYPE0     (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
5922 +#define IRQ_ILLEGAL_TYPE1     (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
5923 +#define IRQ_PENDING1          (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
5924 +#define IRQ_PENDING2          (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
5925 +
5926 +/*
5927 + *  FIQ interrupts definitions are the same as the INT definitions.
5928 + */
5929 +#define FIQ_TIMER0            INT_TIMER0
5930 +#define FIQ_TIMER1            INT_TIMER1
5931 +#define FIQ_TIMER2            INT_TIMER2
5932 +#define FIQ_TIMER3            INT_TIMER3
5933 +#define FIQ_CODEC0            INT_CODEC0
5934 +#define FIQ_CODEC1            INT_CODEC1
5935 +#define FIQ_CODEC2            INT_CODEC2
5936 +#define FIQ_JPEG              INT_JPEG
5937 +#define FIQ_ISP               INT_ISP
5938 +#define FIQ_USB               INT_USB
5939 +#define FIQ_3D                INT_3D
5940 +#define FIQ_TRANSPOSER        INT_TRANSPOSER
5941 +#define FIQ_MULTICORESYNC0    INT_MULTICORESYNC0
5942 +#define FIQ_MULTICORESYNC1    INT_MULTICORESYNC1
5943 +#define FIQ_MULTICORESYNC2    INT_MULTICORESYNC2
5944 +#define FIQ_MULTICORESYNC3    INT_MULTICORESYNC3
5945 +#define FIQ_DMA0              INT_DMA0
5946 +#define FIQ_DMA1              INT_DMA1
5947 +#define FIQ_DMA2              INT_DMA2
5948 +#define FIQ_DMA3              INT_DMA3
5949 +#define FIQ_DMA4              INT_DMA4
5950 +#define FIQ_DMA5              INT_DMA5
5951 +#define FIQ_DMA6              INT_DMA6
5952 +#define FIQ_DMA7              INT_DMA7
5953 +#define FIQ_DMA8              INT_DMA8
5954 +#define FIQ_DMA9              INT_DMA9
5955 +#define FIQ_DMA10             INT_DMA10
5956 +#define FIQ_DMA11             INT_DMA11
5957 +#define FIQ_DMA12             INT_DMA12
5958 +#define FIQ_AUX               INT_AUX
5959 +#define FIQ_ARM               INT_ARM
5960 +#define FIQ_VPUDMA            INT_VPUDMA
5961 +#define FIQ_HOSTPORT          INT_HOSTPORT
5962 +#define FIQ_VIDEOSCALER       INT_VIDEOSCALER
5963 +#define FIQ_CCP2TX            INT_CCP2TX
5964 +#define FIQ_SDC               INT_SDC
5965 +#define FIQ_DSI0              INT_DSI0
5966 +#define FIQ_AVE               INT_AVE
5967 +#define FIQ_CAM0              INT_CAM0
5968 +#define FIQ_CAM1              INT_CAM1
5969 +#define FIQ_HDMI0             INT_HDMI0
5970 +#define FIQ_HDMI1             INT_HDMI1
5971 +#define FIQ_PIXELVALVE1       INT_PIXELVALVE1
5972 +#define FIQ_I2CSPISLV         INT_I2CSPISLV
5973 +#define FIQ_DSI1              INT_DSI1
5974 +#define FIQ_PWA0              INT_PWA0
5975 +#define FIQ_PWA1              INT_PWA1
5976 +#define FIQ_CPR               INT_CPR
5977 +#define FIQ_SMI               INT_SMI
5978 +#define FIQ_GPIO0             INT_GPIO0
5979 +#define FIQ_GPIO1             INT_GPIO1
5980 +#define FIQ_GPIO2             INT_GPIO2
5981 +#define FIQ_GPIO3             INT_GPIO3
5982 +#define FIQ_I2C               INT_I2C
5983 +#define FIQ_SPI               INT_SPI
5984 +#define FIQ_I2SPCM            INT_I2SPCM
5985 +#define FIQ_SDIO              INT_SDIO
5986 +#define FIQ_UART              INT_UART
5987 +#define FIQ_SLIMBUS           INT_SLIMBUS
5988 +#define FIQ_VEC               INT_VEC
5989 +#define FIQ_CPG               INT_CPG
5990 +#define FIQ_RNG               INT_RNG
5991 +#define FIQ_ARASANSDIO        INT_ARASANSDIO
5992 +#define FIQ_AVSPMON           INT_AVSPMON
5993 +
5994 +#define FIQ_ARM_TIMER         INT_ARM_TIMER
5995 +#define FIQ_ARM_MAILBOX       INT_ARM_MAILBOX
5996 +#define FIQ_ARM_DOORBELL_0    INT_ARM_DOORBELL_0
5997 +#define FIQ_ARM_DOORBELL_1    INT_ARM_DOORBELL_1
5998 +#define FIQ_VPU0_HALTED       INT_VPU0_HALTED
5999 +#define FIQ_VPU1_HALTED       INT_VPU1_HALTED
6000 +#define FIQ_ILLEGAL_TYPE0     INT_ILLEGAL_TYPE0
6001 +#define FIQ_ILLEGAL_TYPE1     INT_ILLEGAL_TYPE1
6002 +#define FIQ_PENDING1          INT_PENDING1
6003 +#define FIQ_PENDING2          INT_PENDING2
6004 +
6005 +#define NR_IRQS                              (64 + 21)
6006 --- /dev/null
6007 +++ b/arch/arm/mach-bcm2708/include/mach/memory.h
6008 @@ -0,0 +1,59 @@
6009 +/*
6010 + *  arch/arm/mach-bcm2708/include/mach/memory.h
6011 + *
6012 + *  Copyright (C) 2010 Broadcom
6013 + *
6014 + * This program is free software; you can redistribute it and/or modify
6015 + * it under the terms of the GNU General Public License as published by
6016 + * the Free Software Foundation; either version 2 of the License, or
6017 + * (at your option) any later version.
6018 + *
6019 + * This program is distributed in the hope that it will be useful,
6020 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6021 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6022 + * GNU General Public License for more details.
6023 + *
6024 + * You should have received a copy of the GNU General Public License
6025 + * along with this program; if not, write to the Free Software
6026 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6027 + */
6028 +#ifndef __ASM_ARCH_MEMORY_H
6029 +#define __ASM_ARCH_MEMORY_H
6030 +
6031 +/* Memory overview:
6032 +
6033 +   [ARMcore] <--virtual addr-->
6034 +   [ARMmmu] <--physical addr-->
6035 +   [GERTmap] <--bus add-->
6036 +   [VCperiph]
6037 +
6038 +*/
6039 +
6040 +/*
6041 + * Physical DRAM offset.
6042 + */
6043 +#define PHYS_OFFSET     UL(0x00000000)
6044 +#define ARMMEM_OFFSET    UL(0x00000000)   /* offset in VC of ARM memory */
6045 +#define _REAL_BUS_OFFSET UL(0xC0000000)   /* don't use L1 or L2 caches */
6046 +
6047 +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
6048 + * will provide the offset into this area as well as setting the bits that
6049 + * stop the L1 and L2 cache from being used
6050 + *
6051 + * WARNING: this only works because the ARM is given memory at a fixed location
6052 + *          (ARMMEM_OFFSET)
6053 + */
6054 +#define BUS_OFFSET          (ARMMEM_OFFSET + _REAL_BUS_OFFSET)
6055 +#define __virt_to_bus(x)    ((x) + (BUS_OFFSET - PAGE_OFFSET))
6056 +#define __bus_to_virt(x)    ((x) - (BUS_OFFSET - PAGE_OFFSET))
6057 +#define __pfn_to_bus(x)     (__pfn_to_phys(x) + (BUS_OFFSET - PHYS_OFFSET))
6058 +#define __bus_to_pfn(x)     __phys_to_pfn((x) - (BUS_OFFSET - PHYS_OFFSET))
6059 +
6060 +/*
6061 + * Consistent DMA area set to 2M. Framebuffer now allocated on host
6062 + */
6063 +
6064 +
6065 +#define CONSISTENT_DMA_SIZE 0x00200000
6066 +
6067 +#endif
6068 --- /dev/null
6069 +++ b/arch/arm/mach-bcm2708/include/mach/platform.h
6070 @@ -0,0 +1,210 @@
6071 +/*
6072 + * arch/arm/mach-bcm2708/include/mach/platform.h
6073 + *
6074 + * Copyright (C) 2010 Broadcom
6075 + *
6076 + * This program is free software; you can redistribute it and/or modify
6077 + * it under the terms of the GNU General Public License as published by
6078 + * the Free Software Foundation; either version 2 of the License, or
6079 + * (at your option) any later version.
6080 + *
6081 + * This program is distributed in the hope that it will be useful,
6082 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6083 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6084 + * GNU General Public License for more details.
6085 + *
6086 + * You should have received a copy of the GNU General Public License
6087 + * along with this program; if not, write to the Free Software
6088 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6089 + */
6090 +
6091 +#ifndef _BCM2708_PLATFORM_H
6092 +#define _BCM2708_PLATFORM_H
6093 +
6094 +
6095 +/* macros to get at IO space when running virtually */
6096 +#define IO_ADDRESS(x)  (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
6097 +
6098 +#define __io_address(a)     __io(IO_ADDRESS(a))
6099 +
6100 +
6101 +/*
6102 + *  SDRAM
6103 + */
6104 +#define BCM2708_SDRAM_BASE           0x00000000
6105 +
6106 +/*
6107 + *  Logic expansion modules
6108 + *
6109 + */
6110 +
6111 +
6112 +/* ------------------------------------------------------------------------
6113 + *  BCM2708 ARMCTRL Registers
6114 + * ------------------------------------------------------------------------
6115 + */
6116 +
6117 +#define HW_REGISTER_RW(addr) (addr)
6118 +#define HW_REGISTER_RO(addr) (addr)
6119 +
6120 +#include "arm_control.h"
6121 +#undef ARM_BASE
6122 +
6123 +/*
6124 + * Definitions and addresses for the ARM CONTROL logic
6125 + * This file is manually generated.
6126 + */
6127 +
6128 +#define BCM2708_PERI_BASE        0x20000000
6129 +#define ST_BASE                  (BCM2708_PERI_BASE + 0x3000)   /* System Timer */
6130 +#define DMA_BASE                (BCM2708_PERI_BASE + 0x7000)   /* DMA controller */
6131 +#define ARM_BASE                 (BCM2708_PERI_BASE + 0xB000)   /* BCM2708 ARM control block */
6132 +#define PM_BASE                         (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
6133 +#define GPIO_BASE                (BCM2708_PERI_BASE + 0x200000) /* GPIO */
6134 +#define UART0_BASE               (BCM2708_PERI_BASE + 0x201000)        /* Uart 0 */
6135 +#define MMCI0_BASE               (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
6136 +#define UART1_BASE               (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
6137 +#define EMMC_BASE                (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
6138 +#define SMI_BASE                (BCM2708_PERI_BASE + 0x600000) /* SMI */
6139 +#define USB_BASE                 (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
6140 +#define MCORE_BASE               (BCM2708_PERI_BASE + 0x0000)   /* Fake frame buffer device (actually the multicore sync block*/
6141 +
6142 +#define ARMCTRL_BASE             (ARM_BASE + 0x000)
6143 +#define ARMCTRL_IC_BASE          (ARM_BASE + 0x200)           /* ARM interrupt controller */
6144 +#define ARMCTRL_TIMER0_1_BASE    (ARM_BASE + 0x400)           /* Timer 0 and 1 */
6145 +#define ARMCTRL_0_SBM_BASE       (ARM_BASE + 0x800)           /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
6146 +
6147 +
6148 +/*
6149 + * Interrupt assignments
6150 + */
6151 +
6152 +#define ARM_IRQ1_BASE                  0
6153 +#define INTERRUPT_TIMER0               (ARM_IRQ1_BASE + 0)
6154 +#define INTERRUPT_TIMER1               (ARM_IRQ1_BASE + 1)
6155 +#define INTERRUPT_TIMER2               (ARM_IRQ1_BASE + 2)
6156 +#define INTERRUPT_TIMER3               (ARM_IRQ1_BASE + 3)
6157 +#define INTERRUPT_CODEC0               (ARM_IRQ1_BASE + 4)
6158 +#define INTERRUPT_CODEC1               (ARM_IRQ1_BASE + 5)
6159 +#define INTERRUPT_CODEC2               (ARM_IRQ1_BASE + 6)
6160 +#define INTERRUPT_VC_JPEG              (ARM_IRQ1_BASE + 7)
6161 +#define INTERRUPT_ISP                  (ARM_IRQ1_BASE + 8)
6162 +#define INTERRUPT_VC_USB               (ARM_IRQ1_BASE + 9)
6163 +#define INTERRUPT_VC_3D                (ARM_IRQ1_BASE + 10)
6164 +#define INTERRUPT_TRANSPOSER           (ARM_IRQ1_BASE + 11)
6165 +#define INTERRUPT_MULTICORESYNC0       (ARM_IRQ1_BASE + 12)
6166 +#define INTERRUPT_MULTICORESYNC1       (ARM_IRQ1_BASE + 13)
6167 +#define INTERRUPT_MULTICORESYNC2       (ARM_IRQ1_BASE + 14)
6168 +#define INTERRUPT_MULTICORESYNC3       (ARM_IRQ1_BASE + 15)
6169 +#define INTERRUPT_DMA0                 (ARM_IRQ1_BASE + 16)
6170 +#define INTERRUPT_DMA1                 (ARM_IRQ1_BASE + 17)
6171 +#define INTERRUPT_VC_DMA2              (ARM_IRQ1_BASE + 18)
6172 +#define INTERRUPT_VC_DMA3              (ARM_IRQ1_BASE + 19)
6173 +#define INTERRUPT_DMA4                 (ARM_IRQ1_BASE + 20)
6174 +#define INTERRUPT_DMA5                 (ARM_IRQ1_BASE + 21)
6175 +#define INTERRUPT_DMA6                 (ARM_IRQ1_BASE + 22)
6176 +#define INTERRUPT_DMA7                 (ARM_IRQ1_BASE + 23)
6177 +#define INTERRUPT_DMA8                 (ARM_IRQ1_BASE + 24)
6178 +#define INTERRUPT_DMA9                 (ARM_IRQ1_BASE + 25)
6179 +#define INTERRUPT_DMA10                (ARM_IRQ1_BASE + 26)
6180 +#define INTERRUPT_DMA11                (ARM_IRQ1_BASE + 27)
6181 +#define INTERRUPT_DMA12                (ARM_IRQ1_BASE + 28)
6182 +#define INTERRUPT_AUX                (ARM_IRQ1_BASE + 29)
6183 +#define INTERRUPT_ARM                  (ARM_IRQ1_BASE + 30)
6184 +#define INTERRUPT_VPUDMA               (ARM_IRQ1_BASE + 31)
6185 +
6186 +#define ARM_IRQ2_BASE                  32
6187 +#define INTERRUPT_HOSTPORT             (ARM_IRQ2_BASE + 0)
6188 +#define INTERRUPT_VIDEOSCALER          (ARM_IRQ2_BASE + 1)
6189 +#define INTERRUPT_CCP2TX               (ARM_IRQ2_BASE + 2)
6190 +#define INTERRUPT_SDC                  (ARM_IRQ2_BASE + 3)
6191 +#define INTERRUPT_DSI0                 (ARM_IRQ2_BASE + 4)
6192 +#define INTERRUPT_AVE                  (ARM_IRQ2_BASE + 5)
6193 +#define INTERRUPT_CAM0                 (ARM_IRQ2_BASE + 6)
6194 +#define INTERRUPT_CAM1                 (ARM_IRQ2_BASE + 7)
6195 +#define INTERRUPT_HDMI0                (ARM_IRQ2_BASE + 8)
6196 +#define INTERRUPT_HDMI1                (ARM_IRQ2_BASE + 9)
6197 +#define INTERRUPT_PIXELVALVE1          (ARM_IRQ2_BASE + 10)
6198 +#define INTERRUPT_I2CSPISLV            (ARM_IRQ2_BASE + 11)
6199 +#define INTERRUPT_DSI1                 (ARM_IRQ2_BASE + 12)
6200 +#define INTERRUPT_PWA0                 (ARM_IRQ2_BASE + 13)
6201 +#define INTERRUPT_PWA1                 (ARM_IRQ2_BASE + 14)
6202 +#define INTERRUPT_CPR                  (ARM_IRQ2_BASE + 15)
6203 +#define INTERRUPT_SMI                  (ARM_IRQ2_BASE + 16)
6204 +#define INTERRUPT_GPIO0                (ARM_IRQ2_BASE + 17)
6205 +#define INTERRUPT_GPIO1                (ARM_IRQ2_BASE + 18)
6206 +#define INTERRUPT_GPIO2                (ARM_IRQ2_BASE + 19)
6207 +#define INTERRUPT_GPIO3                (ARM_IRQ2_BASE + 20)
6208 +#define INTERRUPT_VC_I2C               (ARM_IRQ2_BASE + 21)
6209 +#define INTERRUPT_VC_SPI               (ARM_IRQ2_BASE + 22)
6210 +#define INTERRUPT_VC_I2SPCM            (ARM_IRQ2_BASE + 23)
6211 +#define INTERRUPT_VC_SDIO              (ARM_IRQ2_BASE + 24)
6212 +#define INTERRUPT_VC_UART              (ARM_IRQ2_BASE + 25)
6213 +#define INTERRUPT_SLIMBUS              (ARM_IRQ2_BASE + 26)
6214 +#define INTERRUPT_VEC                  (ARM_IRQ2_BASE + 27)
6215 +#define INTERRUPT_CPG                  (ARM_IRQ2_BASE + 28)
6216 +#define INTERRUPT_RNG                  (ARM_IRQ2_BASE + 29)
6217 +#define INTERRUPT_VC_ARASANSDIO        (ARM_IRQ2_BASE + 30)
6218 +#define INTERRUPT_AVSPMON              (ARM_IRQ2_BASE + 31)
6219 +
6220 +#define ARM_IRQ0_BASE                  64
6221 +#define INTERRUPT_ARM_TIMER            (ARM_IRQ0_BASE + 0)
6222 +#define INTERRUPT_ARM_MAILBOX          (ARM_IRQ0_BASE + 1)
6223 +#define INTERRUPT_ARM_DOORBELL_0       (ARM_IRQ0_BASE + 2)
6224 +#define INTERRUPT_ARM_DOORBELL_1       (ARM_IRQ0_BASE + 3)
6225 +#define INTERRUPT_VPU0_HALTED          (ARM_IRQ0_BASE + 4)
6226 +#define INTERRUPT_VPU1_HALTED          (ARM_IRQ0_BASE + 5)
6227 +#define INTERRUPT_ILLEGAL_TYPE0        (ARM_IRQ0_BASE + 6)
6228 +#define INTERRUPT_ILLEGAL_TYPE1        (ARM_IRQ0_BASE + 7)
6229 +#define INTERRUPT_PENDING1             (ARM_IRQ0_BASE + 8)
6230 +#define INTERRUPT_PENDING2             (ARM_IRQ0_BASE + 9)
6231 +#define INTERRUPT_JPEG                 (ARM_IRQ0_BASE + 10)
6232 +#define INTERRUPT_USB                  (ARM_IRQ0_BASE + 11)
6233 +#define INTERRUPT_3D                   (ARM_IRQ0_BASE + 12)
6234 +#define INTERRUPT_DMA2                 (ARM_IRQ0_BASE + 13)
6235 +#define INTERRUPT_DMA3                 (ARM_IRQ0_BASE + 14)
6236 +#define INTERRUPT_I2C                  (ARM_IRQ0_BASE + 15)
6237 +#define INTERRUPT_SPI                  (ARM_IRQ0_BASE + 16)
6238 +#define INTERRUPT_I2SPCM               (ARM_IRQ0_BASE + 17)
6239 +#define INTERRUPT_SDIO                 (ARM_IRQ0_BASE + 18)
6240 +#define INTERRUPT_UART                 (ARM_IRQ0_BASE + 19)
6241 +#define INTERRUPT_ARASANSDIO           (ARM_IRQ0_BASE + 20)
6242 +
6243 +#define MAXIRQNUM                      (32 + 32 + 20)
6244 +#define MAXFIQNUM                      (32 + 32 + 20)
6245 +
6246 +#define MAX_TIMER                       2
6247 +#define MAX_PERIOD                      699050
6248 +#define TICKS_PER_uSEC                  1
6249 +
6250 +/*
6251 + *  These are useconds NOT ticks.
6252 + *
6253 + */
6254 +#define mSEC_1                          1000
6255 +#define mSEC_5                          (mSEC_1 * 5)
6256 +#define mSEC_10                         (mSEC_1 * 10)
6257 +#define mSEC_25                         (mSEC_1 * 25)
6258 +#define SEC_1                           (mSEC_1 * 1000)
6259 +
6260 +/*
6261 + * Watchdog
6262 + */
6263 +#define PM_RSTC                               (PM_BASE+0x1c)
6264 +#define PM_WDOG                               (PM_BASE+0x24)
6265 +
6266 +#define PM_WDOG_RESET                                         0000000000
6267 +#define PM_PASSWORD                   0x5a000000
6268 +#define PM_WDOG_TIME_SET              0x000fffff
6269 +#define PM_RSTC_WRCFG_CLR              0xffffffcf
6270 +#define PM_RSTC_WRCFG_SET              0x00000030
6271 +#define PM_RSTC_WRCFG_FULL_RESET       0x00000020
6272 +#define PM_RSTC_RESET                  0x00000102
6273 +
6274 +
6275 +
6276 +
6277 +
6278 +#endif
6279 +
6280 +/* END */
6281 --- /dev/null
6282 +++ b/arch/arm/mach-bcm2708/include/mach/platform.h.orig
6283 @@ -0,0 +1,210 @@
6284 +/*
6285 + * arch/arm/mach-bcm2708/include/mach/platform.h
6286 + *
6287 + * Copyright (C) 2010 Broadcom
6288 + *
6289 + * This program is free software; you can redistribute it and/or modify
6290 + * it under the terms of the GNU General Public License as published by
6291 + * the Free Software Foundation; either version 2 of the License, or
6292 + * (at your option) any later version.
6293 + *
6294 + * This program is distributed in the hope that it will be useful,
6295 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6296 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6297 + * GNU General Public License for more details.
6298 + *
6299 + * You should have received a copy of the GNU General Public License
6300 + * along with this program; if not, write to the Free Software
6301 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6302 + */
6303 +
6304 +#ifndef _BCM2708_PLATFORM_H
6305 +#define _BCM2708_PLATFORM_H
6306 +
6307 +
6308 +/* macros to get at IO space when running virtually */
6309 +#define IO_ADDRESS(x)  (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
6310 +
6311 +#define __io_address(a)     __io(IO_ADDRESS(a))
6312 +
6313 +
6314 +/*
6315 + *  SDRAM
6316 + */
6317 +#define BCM2708_SDRAM_BASE           0x00000000
6318 +
6319 +/*
6320 + *  Logic expansion modules
6321 + *
6322 + */
6323 +
6324 +
6325 +/* ------------------------------------------------------------------------
6326 + *  BCM2708 ARMCTRL Registers
6327 + * ------------------------------------------------------------------------
6328 + */
6329 +
6330 +#define HW_REGISTER_RW(addr) (addr)
6331 +#define HW_REGISTER_RO(addr) (addr)
6332 +
6333 +#include "arm_control.h"
6334 +#undef ARM_BASE
6335 +
6336 +/*
6337 + * Definitions and addresses for the ARM CONTROL logic
6338 + * This file is manually generated.
6339 + */
6340 +
6341 +#define BCM2708_PERI_BASE        0x20000000
6342 +#define ST_BASE                  (BCM2708_PERI_BASE + 0x3000)   /* System Timer */
6343 +#define DMA_BASE                (BCM2708_PERI_BASE + 0x7000)   /* DMA controller */
6344 +#define ARM_BASE                 (BCM2708_PERI_BASE + 0xB000)   /* BCM2708 ARM control block */
6345 +#define PM_BASE                         (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
6346 +#define GPIO_BASE                (BCM2708_PERI_BASE + 0x200000) /* GPIO */
6347 +#define UART0_BASE               (BCM2708_PERI_BASE + 0x201000)        /* Uart 0 */
6348 +#define MMCI0_BASE               (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
6349 +#define UART1_BASE               (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
6350 +#define EMMC_BASE                (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
6351 +#define SMI_BASE                (BCM2708_PERI_BASE + 0x600000) /* SMI */
6352 +#define USB_BASE                 (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
6353 +
6354 +
6355 +#define ARMCTRL_BASE             (ARM_BASE + 0x000)
6356 +#define ARMCTRL_IC_BASE          (ARM_BASE + 0x200)           /* ARM interrupt controller */
6357 +#define ARMCTRL_TIMER0_1_BASE    (ARM_BASE + 0x400)           /* Timer 0 and 1 */
6358 +#define ARMCTRL_0_SBM_BASE       (ARM_BASE + 0x800)           /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
6359 +
6360 +
6361 +/*
6362 + * Interrupt assignments
6363 + */
6364 +
6365 +#define ARM_IRQ1_BASE                  0
6366 +#define INTERRUPT_TIMER0               (ARM_IRQ1_BASE + 0)
6367 +#define INTERRUPT_TIMER1               (ARM_IRQ1_BASE + 1)
6368 +#define INTERRUPT_TIMER2               (ARM_IRQ1_BASE + 2)
6369 +#define INTERRUPT_TIMER3               (ARM_IRQ1_BASE + 3)
6370 +#define INTERRUPT_CODEC0               (ARM_IRQ1_BASE + 4)
6371 +#define INTERRUPT_CODEC1               (ARM_IRQ1_BASE + 5)
6372 +#define INTERRUPT_CODEC2               (ARM_IRQ1_BASE + 6)
6373 +#define INTERRUPT_VC_JPEG              (ARM_IRQ1_BASE + 7)
6374 +#define INTERRUPT_ISP                  (ARM_IRQ1_BASE + 8)
6375 +#define INTERRUPT_VC_USB               (ARM_IRQ1_BASE + 9)
6376 +#define INTERRUPT_VC_3D                (ARM_IRQ1_BASE + 10)
6377 +#define INTERRUPT_TRANSPOSER           (ARM_IRQ1_BASE + 11)
6378 +#define INTERRUPT_MULTICORESYNC0       (ARM_IRQ1_BASE + 12)
6379 +#define INTERRUPT_MULTICORESYNC1       (ARM_IRQ1_BASE + 13)
6380 +#define INTERRUPT_MULTICORESYNC2       (ARM_IRQ1_BASE + 14)
6381 +#define INTERRUPT_MULTICORESYNC3       (ARM_IRQ1_BASE + 15)
6382 +#define INTERRUPT_DMA0                 (ARM_IRQ1_BASE + 16)
6383 +#define INTERRUPT_DMA1                 (ARM_IRQ1_BASE + 17)
6384 +#define INTERRUPT_VC_DMA2              (ARM_IRQ1_BASE + 18)
6385 +#define INTERRUPT_VC_DMA3              (ARM_IRQ1_BASE + 19)
6386 +#define INTERRUPT_DMA4                 (ARM_IRQ1_BASE + 20)
6387 +#define INTERRUPT_DMA5                 (ARM_IRQ1_BASE + 21)
6388 +#define INTERRUPT_DMA6                 (ARM_IRQ1_BASE + 22)
6389 +#define INTERRUPT_DMA7                 (ARM_IRQ1_BASE + 23)
6390 +#define INTERRUPT_DMA8                 (ARM_IRQ1_BASE + 24)
6391 +#define INTERRUPT_DMA9                 (ARM_IRQ1_BASE + 25)
6392 +#define INTERRUPT_DMA10                (ARM_IRQ1_BASE + 26)
6393 +#define INTERRUPT_DMA11                (ARM_IRQ1_BASE + 27)
6394 +#define INTERRUPT_DMA12                (ARM_IRQ1_BASE + 28)
6395 +#define INTERRUPT_AUX                (ARM_IRQ1_BASE + 29)
6396 +#define INTERRUPT_ARM                  (ARM_IRQ1_BASE + 30)
6397 +#define INTERRUPT_VPUDMA               (ARM_IRQ1_BASE + 31)
6398 +
6399 +#define ARM_IRQ2_BASE                  32
6400 +#define INTERRUPT_HOSTPORT             (ARM_IRQ2_BASE + 0)
6401 +#define INTERRUPT_VIDEOSCALER          (ARM_IRQ2_BASE + 1)
6402 +#define INTERRUPT_CCP2TX               (ARM_IRQ2_BASE + 2)
6403 +#define INTERRUPT_SDC                  (ARM_IRQ2_BASE + 3)
6404 +#define INTERRUPT_DSI0                 (ARM_IRQ2_BASE + 4)
6405 +#define INTERRUPT_AVE                  (ARM_IRQ2_BASE + 5)
6406 +#define INTERRUPT_CAM0                 (ARM_IRQ2_BASE + 6)
6407 +#define INTERRUPT_CAM1                 (ARM_IRQ2_BASE + 7)
6408 +#define INTERRUPT_HDMI0                (ARM_IRQ2_BASE + 8)
6409 +#define INTERRUPT_HDMI1                (ARM_IRQ2_BASE + 9)
6410 +#define INTERRUPT_PIXELVALVE1          (ARM_IRQ2_BASE + 10)
6411 +#define INTERRUPT_I2CSPISLV            (ARM_IRQ2_BASE + 11)
6412 +#define INTERRUPT_DSI1                 (ARM_IRQ2_BASE + 12)
6413 +#define INTERRUPT_PWA0                 (ARM_IRQ2_BASE + 13)
6414 +#define INTERRUPT_PWA1                 (ARM_IRQ2_BASE + 14)
6415 +#define INTERRUPT_CPR                  (ARM_IRQ2_BASE + 15)
6416 +#define INTERRUPT_SMI                  (ARM_IRQ2_BASE + 16)
6417 +#define INTERRUPT_GPIO0                (ARM_IRQ2_BASE + 17)
6418 +#define INTERRUPT_GPIO1                (ARM_IRQ2_BASE + 18)
6419 +#define INTERRUPT_GPIO2                (ARM_IRQ2_BASE + 19)
6420 +#define INTERRUPT_GPIO3                (ARM_IRQ2_BASE + 20)
6421 +#define INTERRUPT_VC_I2C               (ARM_IRQ2_BASE + 21)
6422 +#define INTERRUPT_VC_SPI               (ARM_IRQ2_BASE + 22)
6423 +#define INTERRUPT_VC_I2SPCM            (ARM_IRQ2_BASE + 23)
6424 +#define INTERRUPT_VC_SDIO              (ARM_IRQ2_BASE + 24)
6425 +#define INTERRUPT_VC_UART              (ARM_IRQ2_BASE + 25)
6426 +#define INTERRUPT_SLIMBUS              (ARM_IRQ2_BASE + 26)
6427 +#define INTERRUPT_VEC                  (ARM_IRQ2_BASE + 27)
6428 +#define INTERRUPT_CPG                  (ARM_IRQ2_BASE + 28)
6429 +#define INTERRUPT_RNG                  (ARM_IRQ2_BASE + 29)
6430 +#define INTERRUPT_VC_ARASANSDIO        (ARM_IRQ2_BASE + 30)
6431 +#define INTERRUPT_AVSPMON              (ARM_IRQ2_BASE + 31)
6432 +
6433 +#define ARM_IRQ0_BASE                  64
6434 +#define INTERRUPT_ARM_TIMER            (ARM_IRQ0_BASE + 0)
6435 +#define INTERRUPT_ARM_MAILBOX          (ARM_IRQ0_BASE + 1)
6436 +#define INTERRUPT_ARM_DOORBELL_0       (ARM_IRQ0_BASE + 2)
6437 +#define INTERRUPT_ARM_DOORBELL_1       (ARM_IRQ0_BASE + 3)
6438 +#define INTERRUPT_VPU0_HALTED          (ARM_IRQ0_BASE + 4)
6439 +#define INTERRUPT_VPU1_HALTED          (ARM_IRQ0_BASE + 5)
6440 +#define INTERRUPT_ILLEGAL_TYPE0        (ARM_IRQ0_BASE + 6)
6441 +#define INTERRUPT_ILLEGAL_TYPE1        (ARM_IRQ0_BASE + 7)
6442 +#define INTERRUPT_PENDING1             (ARM_IRQ0_BASE + 8)
6443 +#define INTERRUPT_PENDING2             (ARM_IRQ0_BASE + 9)
6444 +#define INTERRUPT_JPEG                 (ARM_IRQ0_BASE + 10)
6445 +#define INTERRUPT_USB                  (ARM_IRQ0_BASE + 11)
6446 +#define INTERRUPT_3D                   (ARM_IRQ0_BASE + 12)
6447 +#define INTERRUPT_DMA2                 (ARM_IRQ0_BASE + 13)
6448 +#define INTERRUPT_DMA3                 (ARM_IRQ0_BASE + 14)
6449 +#define INTERRUPT_I2C                  (ARM_IRQ0_BASE + 15)
6450 +#define INTERRUPT_SPI                  (ARM_IRQ0_BASE + 16)
6451 +#define INTERRUPT_I2SPCM               (ARM_IRQ0_BASE + 17)
6452 +#define INTERRUPT_SDIO                 (ARM_IRQ0_BASE + 18)
6453 +#define INTERRUPT_UART                 (ARM_IRQ0_BASE + 19)
6454 +#define INTERRUPT_ARASANSDIO           (ARM_IRQ0_BASE + 20)
6455 +
6456 +#define MAXIRQNUM                      (32 + 32 + 20)
6457 +#define MAXFIQNUM                      (32 + 32 + 20)
6458 +
6459 +#define MAX_TIMER                       2
6460 +#define MAX_PERIOD                      699050
6461 +#define TICKS_PER_uSEC                  1
6462 +
6463 +/*
6464 + *  These are useconds NOT ticks.
6465 + *
6466 + */
6467 +#define mSEC_1                          1000
6468 +#define mSEC_5                          (mSEC_1 * 5)
6469 +#define mSEC_10                         (mSEC_1 * 10)
6470 +#define mSEC_25                         (mSEC_1 * 25)
6471 +#define SEC_1                           (mSEC_1 * 1000)
6472 +
6473 +/*
6474 + * Watchdog
6475 + */
6476 +#define PM_RSTC                               (PM_BASE+0x1c)
6477 +#define PM_WDOG                               (PM_BASE+0x24)
6478 +
6479 +#define PM_WDOG_RESET                                         0000000000
6480 +#define PM_PASSWORD                   0x5a000000
6481 +#define PM_WDOG_TIME_SET              0x000fffff
6482 +#define PM_RSTC_WRCFG_CLR              0xffffffcf
6483 +#define PM_RSTC_WRCFG_SET              0x00000030
6484 +#define PM_RSTC_WRCFG_FULL_RESET       0x00000020
6485 +#define PM_RSTC_RESET                  0x00000102
6486 +
6487 +
6488 +
6489 +
6490 +
6491 +#endif
6492 +
6493 +/* END */
6494 --- /dev/null
6495 +++ b/arch/arm/mach-bcm2708/include/mach/power.h
6496 @@ -0,0 +1,26 @@
6497 +/*
6498 + *  linux/arch/arm/mach-bcm2708/power.h
6499 + *
6500 + *  Copyright (C) 2010 Broadcom
6501 + *
6502 + * This program is free software; you can redistribute it and/or modify
6503 + * it under the terms of the GNU General Public License version 2 as
6504 + * published by the Free Software Foundation.
6505 + *
6506 + * This device provides a shared mechanism for controlling the power to
6507 + * VideoCore subsystems.
6508 + */
6509 +
6510 +#ifndef _MACH_BCM2708_POWER_H
6511 +#define _MACH_BCM2708_POWER_H
6512 +
6513 +#include <linux/types.h>
6514 +#include <mach/arm_power.h>
6515 +
6516 +typedef unsigned int BCM_POWER_HANDLE_T;
6517 +
6518 +extern int bcm_power_open(BCM_POWER_HANDLE_T *handle);
6519 +extern int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request);
6520 +extern int bcm_power_close(BCM_POWER_HANDLE_T handle);
6521 +
6522 +#endif
6523 --- /dev/null
6524 +++ b/arch/arm/mach-bcm2708/include/mach/system.h
6525 @@ -0,0 +1,53 @@
6526 +/*
6527 + *  arch/arm/mach-bcm2708/include/mach/system.h
6528 + *
6529 + *  Copyright (C) 2010 Broadcom
6530 + *  Copyright (C) 2003 ARM Limited
6531 + *  Copyright (C) 2000 Deep Blue Solutions Ltd
6532 + *
6533 + * This program is free software; you can redistribute it and/or modify
6534 + * it under the terms of the GNU General Public License as published by
6535 + * the Free Software Foundation; either version 2 of the License, or
6536 + * (at your option) any later version.
6537 + *
6538 + * This program is distributed in the hope that it will be useful,
6539 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6540 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6541 + * GNU General Public License for more details.
6542 + *
6543 + * You should have received a copy of the GNU General Public License
6544 + * along with this program; if not, write to the Free Software
6545 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6546 + */
6547 +#ifndef __ASM_ARCH_SYSTEM_H
6548 +#define __ASM_ARCH_SYSTEM_H
6549 +
6550 +#include <linux/io.h>
6551 +#include <mach/hardware.h>
6552 +#include <mach/platform.h>
6553 +
6554 +static inline void arch_idle(void)
6555 +{
6556 +       /*
6557 +        * This should do all the clock switching
6558 +        * and wait for interrupt tricks
6559 +        */
6560 +       cpu_do_idle();
6561 +}
6562 +
6563 +static inline void arch_reset(char mode, const char *cmd)
6564 +{
6565 +       uint32_t pm_rstc, pm_wdog;
6566 +       uint32_t timeout = 10;
6567 +
6568 +       /* Setup watchdog for reset */
6569 +       pm_rstc = readl(IO_ADDRESS(PM_RSTC));
6570 +
6571 +       pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
6572 +       pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
6573 +
6574 +       writel(pm_wdog, IO_ADDRESS(PM_WDOG));
6575 +       writel(pm_rstc, IO_ADDRESS(PM_RSTC));
6576 +}
6577 +
6578 +#endif
6579 --- /dev/null
6580 +++ b/arch/arm/mach-bcm2708/include/mach/timex.h
6581 @@ -0,0 +1,23 @@
6582 +/*
6583 + *  arch/arm/mach-bcm2708/include/mach/timex.h
6584 + *
6585 + *  BCM2708 sysem clock frequency
6586 + *
6587 + *  Copyright (C) 2010 Broadcom
6588 + *
6589 + * This program is free software; you can redistribute it and/or modify
6590 + * it under the terms of the GNU General Public License as published by
6591 + * the Free Software Foundation; either version 2 of the License, or
6592 + * (at your option) any later version.
6593 + *
6594 + * This program is distributed in the hope that it will be useful,
6595 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6596 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6597 + * GNU General Public License for more details.
6598 + *
6599 + * You should have received a copy of the GNU General Public License
6600 + * along with this program; if not, write to the Free Software
6601 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6602 + */
6603 +
6604 +#define CLOCK_TICK_RATE                (1000000)
6605 --- /dev/null
6606 +++ b/arch/arm/mach-bcm2708/include/mach/uncompress.h
6607 @@ -0,0 +1,49 @@
6608 +/*
6609 + *  arch/arm/mach-bcn2708/include/mach/uncompress.h
6610 + *
6611 + *  Copyright (C) 2010 Broadcom
6612 + *  Copyright (C) 2003 ARM Limited
6613 + *
6614 + * This program is free software; you can redistribute it and/or modify
6615 + * it under the terms of the GNU General Public License as published by
6616 + * the Free Software Foundation; either version 2 of the License, or
6617 + * (at your option) any later version.
6618 + *
6619 + * This program is distributed in the hope that it will be useful,
6620 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6621 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6622 + * GNU General Public License for more details.
6623 + *
6624 + * You should have received a copy of the GNU General Public License
6625 + * along with this program; if not, write to the Free Software
6626 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6627 + */
6628 +
6629 +#include <linux/io.h>
6630 +#include <mach/hardware.h>
6631 +
6632 +#define BCM2708_UART_DR        __io_address(UART0_BASE + 0x00)
6633 +#define BCM2708_UART_FR        __io_address(UART0_BASE + 0x18)
6634 +
6635 +/*
6636 + * This does not append a newline
6637 + */
6638 +static inline void putc(int c)
6639 +{
6640 +       while (readl(BCM2708_UART_FR) & (1 << 5))
6641 +               barrier();
6642 +
6643 +       writel(c, BCM2708_UART_DR);
6644 +}
6645 +
6646 +static inline void flush(void)
6647 +{
6648 +       while (readl(BCM2708_UART_FR) & (1 << 3))
6649 +               barrier();
6650 +}
6651 +
6652 +/*
6653 + * nothing to do
6654 + */
6655 +#define arch_decomp_setup()
6656 +#define arch_decomp_wdog()
6657 --- /dev/null
6658 +++ b/arch/arm/mach-bcm2708/include/mach/vc_mem.h
6659 @@ -0,0 +1,34 @@
6660 +/*****************************************************************************
6661 +* Copyright 2010 - 2011 Broadcom Corporation.  All rights reserved.
6662 +*
6663 +* Unless you and Broadcom execute a separate written software license
6664 +* agreement governing use of this software, this software is licensed to you
6665 +* under the terms of the GNU General Public License version 2, available at
6666 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
6667 +*
6668 +* Notwithstanding the above, under no circumstances may you combine this
6669 +* software in any way with any other Broadcom software provided under a
6670 +* license other than the GPL, without Broadcom's express prior written
6671 +* consent.
6672 +*****************************************************************************/
6673 +
6674 +#if !defined( VC_MEM_H )
6675 +#define VC_MEM_H
6676 +
6677 +#include <linux/ioctl.h>
6678 +
6679 +#define VC_MEM_IOC_MAGIC  'v'
6680 +
6681 +#define VC_MEM_IOC_MEM_PHYS_ADDR    _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
6682 +#define VC_MEM_IOC_MEM_SIZE         _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
6683 +
6684 +#if defined( __KERNEL__ )
6685 +#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
6686 +
6687 +extern unsigned long mm_vc_mem_phys_addr;
6688 +extern unsigned int  mm_vc_mem_size;
6689 +extern int vc_mem_get_current_size( void );
6690 +#endif
6691 +
6692 +#endif  /* VC_MEM_H */
6693 +
6694 --- /dev/null
6695 +++ b/arch/arm/mach-bcm2708/include/mach/vcio.h
6696 @@ -0,0 +1,42 @@
6697 +/*
6698 + *  arch/arm/mach-bcm2708/include/mach/vcio.h
6699 + *
6700 + *  Copyright (C) 2010 Broadcom
6701 + *
6702 + * This program is free software; you can redistribute it and/or modify
6703 + * it under the terms of the GNU General Public License as published by
6704 + * the Free Software Foundation; either version 2 of the License, or
6705 + * (at your option) any later version.
6706 + *
6707 + * This program is distributed in the hope that it will be useful,
6708 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6709 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6710 + * GNU General Public License for more details.
6711 + *
6712 + * You should have received a copy of the GNU General Public License
6713 + * along with this program; if not, write to the Free Software
6714 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6715 + */
6716 +#ifndef _MACH_BCM2708_VCIO_H
6717 +#define _MACH_BCM2708_VCIO_H
6718 +
6719 +/* Routines to handle I/O via the VideoCore "ARM control" registers
6720 + * (semaphores, doorbells, mailboxes)
6721 + */
6722 +
6723 +#define BCM_VCIO_DRIVER_NAME "bcm2708_vcio"
6724 +
6725 +/* Constants shared with the ARM identifying separate mailbox channels */
6726 +#define MBOX_CHAN_POWER   0 /* for use by the power management interface */
6727 +#define MBOX_CHAN_FB      1 /* for use by the frame buffer */
6728 +#define MBOX_CHAN_VUART   2 /* for use by the virtual UART */
6729 +#define MBOX_CHAN_VCHIQ   3 /* for use by the VCHIQ interface */
6730 +#define MBOX_CHAN_LEDS    4 /* for use by the leds interface */
6731 +#define MBOX_CHAN_BUTTONS 5 /* for use by the buttons interface */
6732 +#define MBOX_CHAN_TOUCH   6 /* for use by the touchscreen interface */
6733 +#define MBOX_CHAN_COUNT   7
6734 +
6735 +extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28);
6736 +extern int /*rc*/ bcm_mailbox_write(unsigned chan, uint32_t data28);
6737 +
6738 +#endif
6739 --- /dev/null
6740 +++ b/arch/arm/mach-bcm2708/include/mach/vmalloc.h
6741 @@ -0,0 +1,20 @@
6742 +/*
6743 + *  arch/arm/mach-bcm2708/include/mach/vmalloc.h
6744 + *
6745 + *  Copyright (C) 2010 Broadcom
6746 + *
6747 + * This program is free software; you can redistribute it and/or modify
6748 + * it under the terms of the GNU General Public License as published by
6749 + * the Free Software Foundation; either version 2 of the License, or
6750 + * (at your option) any later version.
6751 + *
6752 + * This program is distributed in the hope that it will be useful,
6753 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6754 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6755 + * GNU General Public License for more details.
6756 + *
6757 + * You should have received a copy of the GNU General Public License
6758 + * along with this program; if not, write to the Free Software
6759 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6760 + */
6761 +#define VMALLOC_END            (0xd8000000)
6762 --- /dev/null
6763 +++ b/arch/arm/mach-bcm2708/power.c
6764 @@ -0,0 +1,193 @@
6765 +/*
6766 + *      linux/arch/arm/mach-bcm2708/power.c
6767 + *
6768 + *      Copyright (C) 2010 Broadcom
6769 + *
6770 + * This program is free software; you can redistribute it and/or modify
6771 + * it under the terms of the GNU General Public License version 2 as
6772 + * published by the Free Software Foundation.
6773 + *
6774 + * This device provides a shared mechanism for controlling the power to
6775 + * VideoCore subsystems.
6776 + */
6777 +
6778 +#include <linux/module.h>
6779 +#include <linux/semaphore.h>
6780 +#include <linux/bug.h>
6781 +#include <mach/power.h>
6782 +#include <mach/vcio.h>
6783 +#include <mach/arm_power.h>
6784 +
6785 +#define DRIVER_NAME "bcm2708_power"
6786 +
6787 +#define BCM_POWER_MAXCLIENTS 4
6788 +#define BCM_POWER_NOCLIENT (1<<31)
6789 +
6790 +/* Some drivers expect there devices to be permanently powered */
6791 +#define BCM_POWER_ALWAYS_ON (BCM_POWER_USB)
6792 +
6793 +#if 1
6794 +#define DPRINTK printk
6795 +#else
6796 +#define DPRINTK if (0) printk
6797 +#endif
6798 +
6799 +struct state_struct {
6800 +       uint32_t global_request;
6801 +       uint32_t client_request[BCM_POWER_MAXCLIENTS];
6802 +       struct semaphore client_mutex;
6803 +       struct semaphore mutex;
6804 +} g_state;
6805 +
6806 +int bcm_power_open(BCM_POWER_HANDLE_T *handle)
6807 +{
6808 +       BCM_POWER_HANDLE_T i;
6809 +       int ret = -EBUSY;
6810 +
6811 +       down(&g_state.client_mutex);
6812 +
6813 +       for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
6814 +               if (g_state.client_request[i] == BCM_POWER_NOCLIENT) {
6815 +                       g_state.client_request[i] = BCM_POWER_NONE;
6816 +                       *handle = i;
6817 +                       ret = 0;
6818 +                       break;
6819 +               }
6820 +       }
6821 +
6822 +       up(&g_state.client_mutex);
6823 +
6824 +       DPRINTK("bcm_power_open() -> %d\n", *handle);
6825 +
6826 +       return ret;
6827 +}
6828 +EXPORT_SYMBOL_GPL(bcm_power_open);
6829 +
6830 +int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request)
6831 +{
6832 +       int rc = 0;
6833 +
6834 +       DPRINTK("bcm_power_request(%d, %x)\n", handle, request);
6835 +
6836 +       if ((handle < BCM_POWER_MAXCLIENTS) &&
6837 +           (g_state.client_request[handle] != BCM_POWER_NOCLIENT)) {
6838 +               if (down_interruptible(&g_state.mutex) != 0) {
6839 +                       DPRINTK("bcm_power_request -> interrupted\n");
6840 +                       return -EINTR;
6841 +               }
6842 +
6843 +               if (request != g_state.client_request[handle]) {
6844 +                       uint32_t others_request = 0;
6845 +                       uint32_t global_request;
6846 +                       BCM_POWER_HANDLE_T i;
6847 +
6848 +                       for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
6849 +                               if (i != handle)
6850 +                                       others_request |=
6851 +                                           g_state.client_request[i];
6852 +                       }
6853 +                       others_request &= ~BCM_POWER_NOCLIENT;
6854 +
6855 +                       global_request = request | others_request;
6856 +                       if (global_request != g_state.global_request) {
6857 +                               uint32_t actual;
6858 +
6859 +                               /* Send a request to VideoCore */
6860 +                               bcm_mailbox_write(MBOX_CHAN_POWER,
6861 +                                                 global_request << 4);
6862 +
6863 +                               /* Wait for a response during power-up */
6864 +                               if (global_request & ~g_state.global_request) {
6865 +                                       rc = bcm_mailbox_read(MBOX_CHAN_POWER,
6866 +                                                             &actual);
6867 +                                       DPRINTK
6868 +                                           ("bcm_mailbox_read -> %08x, %d\n",
6869 +                                            actual, rc);
6870 +                                       actual >>= 4;
6871 +                               } else {
6872 +                                       rc = 0;
6873 +                                       actual = global_request;
6874 +                               }
6875 +
6876 +                               if (rc == 0) {
6877 +                                       if (actual != global_request) {
6878 +                                               printk(KERN_ERR
6879 +                                                    "%s: prev global %x, new global %x, actual %x, request %x, others_request %x\n",
6880 +                                                    __func__,
6881 +                                                    g_state.global_request,
6882 +                                                    global_request, actual, request, others_request);
6883 +                                               /* A failure */
6884 +                                               BUG_ON((others_request & actual)
6885 +                                                      != others_request);
6886 +                                               request &= actual;
6887 +                                               rc = -EIO;
6888 +                                       }
6889 +
6890 +                                       g_state.global_request = actual;
6891 +                                       g_state.client_request[handle] =
6892 +                                           request;
6893 +                               }
6894 +                       }
6895 +               }
6896 +               up(&g_state.mutex);
6897 +       } else {
6898 +               rc = -EINVAL;
6899 +       }
6900 +       DPRINTK("bcm_power_request -> %d\n", rc);
6901 +       return rc;
6902 +}
6903 +EXPORT_SYMBOL_GPL(bcm_power_request);
6904 +
6905 +int bcm_power_close(BCM_POWER_HANDLE_T handle)
6906 +{
6907 +       int rc;
6908 +
6909 +       DPRINTK("bcm_power_close(%d)\n", handle);
6910 +
6911 +       rc = bcm_power_request(handle, BCM_POWER_NONE);
6912 +       if (rc == 0)
6913 +               g_state.client_request[handle] = BCM_POWER_NOCLIENT;
6914 +
6915 +       return rc;
6916 +}
6917 +EXPORT_SYMBOL_GPL(bcm_power_close);
6918 +
6919 +static int __init bcm_power_init(void)
6920 +{
6921 +#if defined(BCM_POWER_ALWAYS_ON)
6922 +       BCM_POWER_HANDLE_T always_on_handle;
6923 +#endif
6924 +       int rc = 0;
6925 +       int i;
6926 +
6927 +       printk(KERN_INFO "bcm_power: Broadcom power driver\n");
6928 +
6929 +       for (i = 0; i < BCM_POWER_MAXCLIENTS; i++)
6930 +               g_state.client_request[i] = BCM_POWER_NOCLIENT;
6931 +
6932 +       sema_init(&g_state.client_mutex, 1);
6933 +       sema_init(&g_state.mutex, 1);
6934 +
6935 +       g_state.global_request = 0;
6936 +
6937 +#if defined(BCM_POWER_ALWAYS_ON)
6938 +       if (BCM_POWER_ALWAYS_ON) {
6939 +               bcm_power_open(&always_on_handle);
6940 +               bcm_power_request(always_on_handle, BCM_POWER_ALWAYS_ON);
6941 +       }
6942 +#endif
6943 +
6944 +       return rc;
6945 +}
6946 +
6947 +static void __exit bcm_power_exit(void)
6948 +{
6949 +       bcm_mailbox_write(MBOX_CHAN_POWER, 0);
6950 +}
6951 +
6952 +arch_initcall(bcm_power_init); /* Initialize early */
6953 +module_exit(bcm_power_exit);
6954 +
6955 +MODULE_AUTHOR("Phil Elwell");
6956 +MODULE_DESCRIPTION("Interface to BCM2708 power management");
6957 +MODULE_LICENSE("GPL");
6958 --- /dev/null
6959 +++ b/arch/arm/mach-bcm2708/vc_mem.c
6960 @@ -0,0 +1,467 @@
6961 +/*****************************************************************************
6962 +* Copyright 2010 - 2011 Broadcom Corporation.  All rights reserved.
6963 +*
6964 +* Unless you and Broadcom execute a separate written software license
6965 +* agreement governing use of this software, this software is licensed to you
6966 +* under the terms of the GNU General Public License version 2, available at
6967 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
6968 +*
6969 +* Notwithstanding the above, under no circumstances may you combine this
6970 +* software in any way with any other Broadcom software provided under a
6971 +* license other than the GPL, without Broadcom's express prior written
6972 +* consent.
6973 +*****************************************************************************/
6974 +
6975 +#include <linux/kernel.h>
6976 +#include <linux/module.h>
6977 +#include <linux/fs.h>
6978 +#include <linux/device.h>
6979 +#include <linux/cdev.h>
6980 +#include <linux/mm.h>
6981 +#include <linux/slab.h>
6982 +#include <linux/proc_fs.h>
6983 +#include <asm/uaccess.h>
6984 +
6985 +#ifdef CONFIG_ARCH_KONA
6986 +#include <chal/chal_ipc.h>
6987 +#elif CONFIG_ARCH_BCM2708
6988 +#else
6989 +#include <csp/chal_ipc.h>
6990 +#endif
6991 +
6992 +#include "mach/vc_mem.h"
6993 +//#include "interface/vchiq_arm/vchiq_connected.h"
6994 +
6995 +#define DRIVER_NAME  "vc-mem"
6996 +
6997 +// Uncomment to enable debug logging
6998 +//#define ENABLE_DBG
6999 +
7000 +#if defined(ENABLE_DBG)
7001 +#define LOG_DBG( fmt, ... )  printk( KERN_INFO fmt "\n", ##__VA_ARGS__ )
7002 +#else
7003 +#define LOG_DBG( fmt, ... )
7004 +#endif
7005 +#define LOG_ERR( fmt, ... )  printk( KERN_ERR fmt "\n", ##__VA_ARGS__ )
7006 +
7007 +// Device (/dev) related variables
7008 +static dev_t vc_mem_devnum = 0;
7009 +static struct class *vc_mem_class = NULL;
7010 +static struct cdev vc_mem_cdev;
7011 +static int vc_mem_inited = 0;
7012 +
7013 +// Proc entry
7014 +static struct proc_dir_entry *vc_mem_proc_entry;
7015 +
7016 +/*
7017 + * Videocore memory addresses and size
7018 + *
7019 + * Drivers that wish to know the videocore memory addresses and sizes should
7020 + * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
7021 + * headers. This allows the other drivers to not be tied down to a a certain
7022 + * address/size at compile time.
7023 + *
7024 + * In the future, the goal is to have the videocore memory virtual address and
7025 + * size be calculated at boot time rather than at compile time. The decision of
7026 + * where the videocore memory resides and its size would be in the hands of the
7027 + * bootloader (and/or kernel). When that happens, the values of these variables
7028 + * would be calculated and assigned in the init function.
7029 + */
7030 +#ifdef CONFIG_ARCH_KONA
7031 +
7032 +#include <mach/io_map.h>
7033 +unsigned long mm_vc_mem_phys_addr = VC_EMI;
7034 +
7035 +#elif CONFIG_ARCH_BCM2708
7036 +
7037 +// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
7038 +unsigned long mm_vc_mem_phys_addr = 0x00000000;
7039 +
7040 +#else
7041 +
7042 +#include <mach/csp/mm_io.h>
7043 +unsigned long mm_vc_mem_phys_addr = MM_ADDR_IO_VC_EMI;
7044 +
7045 +#endif
7046 +
7047 +unsigned int mm_vc_mem_size = 0;
7048 +
7049 +EXPORT_SYMBOL(mm_vc_mem_phys_addr);
7050 +EXPORT_SYMBOL(mm_vc_mem_size);
7051 +
7052 +/****************************************************************************
7053 +*
7054 +*   vc_mem_open
7055 +*
7056 +***************************************************************************/
7057 +
7058 +static int
7059 +vc_mem_open(struct inode *inode, struct file *file)
7060 +{
7061 +       (void) inode;
7062 +       (void) file;
7063 +
7064 +       LOG_DBG("%s: called file = 0x%p", __func__, file);
7065 +
7066 +       return 0;
7067 +}
7068 +
7069 +/****************************************************************************
7070 +*
7071 +*   vc_mem_release
7072 +*
7073 +***************************************************************************/
7074 +
7075 +static int
7076 +vc_mem_release(struct inode *inode, struct file *file)
7077 +{
7078 +       (void) inode;
7079 +       (void) file;
7080 +
7081 +       LOG_DBG("%s: called file = 0x%p", __func__, file);
7082 +
7083 +       return 0;
7084 +}
7085 +
7086 +/****************************************************************************
7087 +*
7088 +*   vc_mem_get_size
7089 +*
7090 +***************************************************************************/
7091 +
7092 +static void
7093 +vc_mem_get_size(void)
7094 +{
7095 +#ifdef CONFIG_ARCH_BCM2708
7096 +       mm_vc_mem_size = 256 * 1024 * 1024;     // Static for now
7097 +#else
7098 +       CHAL_IPC_HANDLE ipc_handle;
7099 +       uint32_t wakeup_register;
7100 +
7101 +       // Get the videocore memory size from the IPC mailbox if not yet
7102 +       // assigned.
7103 +       if (mm_vc_mem_size == 0) {
7104 +               ipc_handle = chal_ipc_config(NULL);
7105 +               if (ipc_handle == NULL) {
7106 +                       LOG_ERR("%s: failed to get IPC handlle", __func__);
7107 +                       return;
7108 +               }
7109 +
7110 +               chal_ipc_query_wakeup_vc(ipc_handle, &wakeup_register);
7111 +               if ((wakeup_register & ~1) == 0) {
7112 +                       LOG_DBG("%s: videocore not yet loaded, skipping...",
7113 +                               __func__);
7114 +               } else {
7115 +                       if (chal_ipc_read_mailbox(ipc_handle,
7116 +                                                 IPC_MAILBOX_ID_0,
7117 +                                                 &mm_vc_mem_size) !=
7118 +                           BCM_SUCCESS) {
7119 +                               LOG_ERR("%s: failed to read from IPC mailbox",
7120 +                                       __func__);
7121 +                       }
7122 +               }
7123 +       }
7124 +#endif
7125 +}
7126 +
7127 +/****************************************************************************
7128 +*
7129 +*   vc_mem_get_current_size
7130 +*
7131 +***************************************************************************/
7132 +
7133 +int
7134 +vc_mem_get_current_size(void)
7135 +{
7136 +       vc_mem_get_size();
7137 +       return mm_vc_mem_size;
7138 +}
7139 +
7140 +EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
7141 +
7142 +/****************************************************************************
7143 +*
7144 +*   vc_mem_ioctl
7145 +*
7146 +***************************************************************************/
7147 +
7148 +static long
7149 +vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
7150 +{
7151 +       int rc = 0;
7152 +
7153 +       (void) cmd;
7154 +       (void) arg;
7155 +
7156 +       LOG_DBG("%s: called file = 0x%p", __func__, file);
7157 +
7158 +       switch (cmd) {
7159 +       case VC_MEM_IOC_MEM_PHYS_ADDR:
7160 +               {
7161 +                       LOG_DBG("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p",
7162 +                               __func__, (void *) mm_vc_mem_phys_addr);
7163 +
7164 +                       if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
7165 +                                        sizeof (mm_vc_mem_phys_addr)) != 0) {
7166 +                               rc = -EFAULT;
7167 +                       }
7168 +                       break;
7169 +               }
7170 +       case VC_MEM_IOC_MEM_SIZE:
7171 +               {
7172 +                       // Get the videocore memory size first
7173 +                       vc_mem_get_size();
7174 +
7175 +                       LOG_DBG("%s: VC_MEM_IOC_MEM_SIZE=%u", __func__,
7176 +                               mm_vc_mem_size);
7177 +
7178 +                       if (copy_to_user((void *) arg, &mm_vc_mem_size,
7179 +                                        sizeof (mm_vc_mem_size)) != 0) {
7180 +                               rc = -EFAULT;
7181 +                       }
7182 +                       break;
7183 +               }
7184 +       default:
7185 +               {
7186 +                       return -ENOTTY;
7187 +               }
7188 +       }
7189 +       LOG_DBG("%s: file = 0x%p returning %d", __func__, file, rc);
7190 +
7191 +       return rc;
7192 +}
7193 +
7194 +/****************************************************************************
7195 +*
7196 +*   vc_mem_mmap
7197 +*
7198 +***************************************************************************/
7199 +
7200 +static int
7201 +vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
7202 +{
7203 +       int rc = 0;
7204 +       unsigned long length = vma->vm_end - vma->vm_start;
7205 +       unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
7206 +
7207 +       LOG_DBG("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx",
7208 +               __func__, (long) vma->vm_start, (long) vma->vm_end,
7209 +               (long) vma->vm_pgoff);
7210 +
7211 +       if (offset + length > mm_vc_mem_size) {
7212 +               LOG_ERR("%s: length %ld is too big", __func__, length);
7213 +               return -EINVAL;
7214 +       }
7215 +       // Do not cache the memory map
7216 +       vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
7217 +
7218 +       rc = remap_pfn_range(vma, vma->vm_start,
7219 +                            (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
7220 +                            vma->vm_pgoff, length, vma->vm_page_prot);
7221 +       if (rc != 0) {
7222 +               LOG_ERR("%s: remap_pfn_range failed (rc=%d)", __func__, rc);
7223 +       }
7224 +
7225 +       return rc;
7226 +}
7227 +
7228 +/****************************************************************************
7229 +*
7230 +*   File Operations for the driver.
7231 +*
7232 +***************************************************************************/
7233 +
7234 +static const struct file_operations vc_mem_fops = {
7235 +       .owner = THIS_MODULE,
7236 +       .open = vc_mem_open,
7237 +       .release = vc_mem_release,
7238 +       .unlocked_ioctl = vc_mem_ioctl,
7239 +       .mmap = vc_mem_mmap,
7240 +};
7241 +
7242 +/****************************************************************************
7243 +*
7244 +*   vc_mem_proc_read
7245 +*
7246 +***************************************************************************/
7247 +
7248 +static int
7249 +vc_mem_proc_read(char *buf, char **start, off_t offset, int count, int *eof,
7250 +                void *data)
7251 +{
7252 +       char *p = buf;
7253 +
7254 +       (void) start;
7255 +       (void) count;
7256 +       (void) data;
7257 +
7258 +       if (offset > 0) {
7259 +               *eof = 1;
7260 +               return 0;
7261 +       }
7262 +       // Get the videocore memory size first
7263 +       vc_mem_get_size();
7264 +
7265 +       p += sprintf(p, "Videocore memory:\n");
7266 +       if (mm_vc_mem_phys_addr != 0)
7267 +               p += sprintf(p, "   Physical address: 0x%p\n",
7268 +                            (void *) mm_vc_mem_phys_addr);
7269 +       else
7270 +               p += sprintf(p, "   Physical address: 0x00000000\n");
7271 +       p += sprintf(p, "   Length (bytes):   %u\n", mm_vc_mem_size);
7272 +
7273 +       *eof = 1;
7274 +       return p - buf;
7275 +}
7276 +
7277 +/****************************************************************************
7278 +*
7279 +*   vc_mem_proc_write
7280 +*
7281 +***************************************************************************/
7282 +
7283 +static int
7284 +vc_mem_proc_write(struct file *file, const char __user * buffer,
7285 +                 unsigned long count, void *data)
7286 +{
7287 +       int rc = -EFAULT;
7288 +       char input_str[10];
7289 +
7290 +       memset(input_str, 0, sizeof (input_str));
7291 +
7292 +       if (count > sizeof (input_str)) {
7293 +               LOG_ERR("%s: input string length too long", __func__);
7294 +               goto out;
7295 +       }
7296 +
7297 +       if (copy_from_user(input_str, buffer, count - 1)) {
7298 +               LOG_ERR("%s: failed to get input string", __func__);
7299 +               goto out;
7300 +       }
7301 +
7302 +       if (strncmp(input_str, "connect", strlen("connect")) == 0) {
7303 +               // Get the videocore memory size from the videocore
7304 +               vc_mem_get_size();
7305 +       }
7306 +
7307 +      out:
7308 +       return rc;
7309 +}
7310 +
7311 +/****************************************************************************
7312 +*
7313 +*   vc_mem_connected_init
7314 +*
7315 +*   This function is called once the videocore has been connected.
7316 +*
7317 +***************************************************************************/
7318 +
7319 +void
7320 +vc_mem_connected_init(void)
7321 +{
7322 +       int rc = -EFAULT;
7323 +       struct device *dev;
7324 +
7325 +       LOG_DBG("%s: called", __func__);
7326 +
7327 +       vc_mem_get_size();
7328 +
7329 +       printk("vc-mem: mm_vc_mem_phys_addr = 0x%08lx\n", mm_vc_mem_phys_addr);
7330 +       printk("vc-mem: mm_vc_mem_size      = 0x%08x (%u MiB)\n",
7331 +              mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
7332 +
7333 +       if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
7334 +               LOG_ERR("%s: alloc_chrdev_region failed (rc=%d)", __func__, rc);
7335 +               goto out_err;
7336 +       }
7337 +
7338 +       cdev_init(&vc_mem_cdev, &vc_mem_fops);
7339 +       if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
7340 +               LOG_ERR("%s: cdev_add failed (rc=%d)", __func__, rc);
7341 +               goto out_unregister;
7342 +       }
7343 +
7344 +       vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
7345 +       if (IS_ERR(vc_mem_class)) {
7346 +               rc = PTR_ERR(vc_mem_class);
7347 +               LOG_ERR("%s: class_create failed (rc=%d)", __func__, rc);
7348 +               goto out_cdev_del;
7349 +       }
7350 +
7351 +       dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
7352 +                           DRIVER_NAME);
7353 +       if (IS_ERR(dev)) {
7354 +               rc = PTR_ERR(dev);
7355 +               LOG_ERR("%s: device_create failed (rc=%d)", __func__, rc);
7356 +               goto out_class_destroy;
7357 +       }
7358 +
7359 +       vc_mem_proc_entry = create_proc_entry(DRIVER_NAME, 0444, NULL);
7360 +       if (vc_mem_proc_entry == NULL) {
7361 +               rc = -EFAULT;
7362 +               LOG_ERR("%s: create_proc_entry failed", __func__);
7363 +               goto out_device_destroy;
7364 +       }
7365 +       vc_mem_proc_entry->read_proc = vc_mem_proc_read;
7366 +       vc_mem_proc_entry->write_proc = vc_mem_proc_write;
7367 +
7368 +       vc_mem_inited = 1;
7369 +       return;
7370 +
7371 +      out_device_destroy:
7372 +       device_destroy(vc_mem_class, vc_mem_devnum);
7373 +
7374 +      out_class_destroy:
7375 +       class_destroy(vc_mem_class);
7376 +       vc_mem_class = NULL;
7377 +
7378 +      out_cdev_del:
7379 +       cdev_del(&vc_mem_cdev);
7380 +
7381 +      out_unregister:
7382 +       unregister_chrdev_region(vc_mem_devnum, 1);
7383 +
7384 +      out_err:
7385 +       return;
7386 +}
7387 +
7388 +/****************************************************************************
7389 +*
7390 +*   vc_mem_init
7391 +*
7392 +***************************************************************************/
7393 +
7394 +static int __init
7395 +vc_mem_init(void)
7396 +{
7397 +       printk(KERN_INFO "vc-mem: Videocore memory driver\n");
7398 +
7399 +       //vchiq_add_connected_callback(vc_mem_connected_init);
7400 +
7401 +       return 0;
7402 +}
7403 +
7404 +/****************************************************************************
7405 +*
7406 +*   vc_mem_exit
7407 +*
7408 +***************************************************************************/
7409 +
7410 +static void __exit
7411 +vc_mem_exit(void)
7412 +{
7413 +       LOG_DBG("%s: called", __func__);
7414 +
7415 +       if (vc_mem_inited) {
7416 +               remove_proc_entry(vc_mem_proc_entry->name, NULL);
7417 +               device_destroy(vc_mem_class, vc_mem_devnum);
7418 +               class_destroy(vc_mem_class);
7419 +               cdev_del(&vc_mem_cdev);
7420 +               unregister_chrdev_region(vc_mem_devnum, 1);
7421 +       }
7422 +}
7423 +
7424 +module_init(vc_mem_init);
7425 +module_exit(vc_mem_exit);
7426 +MODULE_LICENSE("GPL");
7427 +MODULE_AUTHOR("Broadcom Corporation");
7428 --- /dev/null
7429 +++ b/arch/arm/mach-bcm2708/vcio.c
7430 @@ -0,0 +1,309 @@
7431 +/*
7432 + *  linux/arch/arm/mach-bcm2708/vcio.c
7433 + *
7434 + *  Copyright (C) 2010 Broadcom
7435 + *
7436 + * This program is free software; you can redistribute it and/or modify
7437 + * it under the terms of the GNU General Public License version 2 as
7438 + * published by the Free Software Foundation.
7439 + *
7440 + * This device provides a shared mechanism for writing to the mailboxes,
7441 + * semaphores, doorbells etc. that are shared between the ARM and the
7442 + * VideoCore processor
7443 + */
7444 +
7445 +#if defined(CONFIG_SERIAL_BCM_MBOX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
7446 +#define SUPPORT_SYSRQ
7447 +#endif
7448 +
7449 +#include <linux/module.h>
7450 +#include <linux/console.h>
7451 +#include <linux/serial_core.h>
7452 +#include <linux/serial.h>
7453 +#include <linux/errno.h>
7454 +#include <linux/device.h>
7455 +#include <linux/init.h>
7456 +#include <linux/mm.h>
7457 +#include <linux/dma-mapping.h>
7458 +#include <linux/platform_device.h>
7459 +#include <linux/sysrq.h>
7460 +#include <linux/delay.h>
7461 +#include <linux/slab.h>
7462 +#include <linux/interrupt.h>
7463 +#include <linux/irq.h>
7464 +
7465 +#include <linux/io.h>
7466 +
7467 +#include <mach/vcio.h>
7468 +#include <mach/platform.h>
7469 +
7470 +#define DRIVER_NAME BCM_VCIO_DRIVER_NAME
7471 +
7472 +/* ----------------------------------------------------------------------
7473 + *     Mailbox
7474 + * -------------------------------------------------------------------- */
7475 +
7476 +/* offsets from a mail box base address */
7477 +#define MAIL_WRT       0x00    /* write - and next 4 words */
7478 +#define MAIL_RD                0x00    /* read - and next 4 words */
7479 +#define MAIL_POL       0x10    /* read without popping the fifo */
7480 +#define MAIL_SND       0x14    /* sender ID (bottom two bits) */
7481 +#define MAIL_STA       0x18    /* status */
7482 +#define MAIL_CNF       0x1C    /* configuration */
7483 +
7484 +#define MBOX_MSG(chan, data28)         (((data28) & ~0xf) | ((chan) & 0xf))
7485 +#define MBOX_MSG_LSB(chan, data28) (((data28) << 4) | ((chan) & 0xf))
7486 +#define MBOX_CHAN(msg)                 ((msg) & 0xf)
7487 +#define MBOX_DATA28(msg)               ((msg) & ~0xf)
7488 +#define MBOX_DATA28_LSB(msg)           (((uint32_t)msg) >> 4)
7489 +
7490 +#define MBOX_MAGIC 0xd0d0c0de
7491 +
7492 +struct vc_mailbox {
7493 +       struct device *dev;     /* parent device */
7494 +       void __iomem *status;
7495 +       void __iomem *config;
7496 +       void __iomem *read;
7497 +       void __iomem *write;
7498 +       uint32_t msg[MBOX_CHAN_COUNT];
7499 +       struct semaphore sema[MBOX_CHAN_COUNT];
7500 +       uint32_t magic;
7501 +};
7502 +
7503 +static void mbox_init(struct vc_mailbox *mbox_out, struct device *dev,
7504 +                     uint32_t addr_mbox)
7505 +{
7506 +       int i;
7507 +
7508 +       mbox_out->dev = dev;
7509 +       mbox_out->status = __io_address(addr_mbox + MAIL_STA);
7510 +       mbox_out->config = __io_address(addr_mbox + MAIL_CNF);
7511 +       mbox_out->read = __io_address(addr_mbox + MAIL_RD);
7512 +       /* Write to the other mailbox */
7513 +       mbox_out->write =
7514 +           __io_address((addr_mbox ^ ARM_0_MAIL0_WRT ^ ARM_0_MAIL1_WRT) +
7515 +                        MAIL_WRT);
7516 +
7517 +       for (i = 0; i < MBOX_CHAN_COUNT; i++) {
7518 +               mbox_out->msg[i] = 0;
7519 +               sema_init(&mbox_out->sema[i], 0);
7520 +       }
7521 +
7522 +       /* Enable the interrupt on data reception */
7523 +       writel(ARM_MC_IHAVEDATAIRQEN, mbox_out->config);
7524 +
7525 +       mbox_out->magic = MBOX_MAGIC;
7526 +}
7527 +
7528 +static int mbox_write(struct vc_mailbox *mbox, unsigned chan, uint32_t data28)
7529 +{
7530 +       int rc;
7531 +
7532 +       if (mbox->magic != MBOX_MAGIC)
7533 +               rc = -EINVAL;
7534 +       else {
7535 +               /* wait for the mailbox FIFO to have some space in it */
7536 +               while (0 != (readl(mbox->status) & ARM_MS_FULL))
7537 +                       cpu_relax();
7538 +
7539 +               writel(MBOX_MSG(chan, data28), mbox->write);
7540 +               rc = 0;
7541 +       }
7542 +       return rc;
7543 +}
7544 +
7545 +static int mbox_read(struct vc_mailbox *mbox, unsigned chan, uint32_t *data28)
7546 +{
7547 +       int rc;
7548 +
7549 +       if (mbox->magic != MBOX_MAGIC)
7550 +               rc = -EINVAL;
7551 +       else {
7552 +               if (mbox->msg[chan] ||
7553 +                   (down_interruptible(&mbox->sema[chan]) == 0)) {
7554 +                       *data28 = MBOX_DATA28(mbox->msg[chan]);
7555 +                       mbox->msg[chan] = 0;
7556 +                       rc = 0;
7557 +               } else {
7558 +                       /* The wait was interrupted */
7559 +                       rc = -EINTR;
7560 +               }
7561 +       }
7562 +       return rc;
7563 +}
7564 +
7565 +static irqreturn_t mbox_irq(int irq, void *dev_id)
7566 +{
7567 +       /* wait for the mailbox FIFO to have some data in it */
7568 +       struct vc_mailbox *mbox = (struct vc_mailbox *) dev_id;
7569 +       int status = readl(mbox->status);
7570 +       int ret = IRQ_NONE;
7571 +
7572 +       while (!(status & ARM_MS_EMPTY)) {
7573 +               uint32_t msg = readl(mbox->read);
7574 +               int chan = MBOX_CHAN(msg);
7575 +               if (chan < MBOX_CHAN_COUNT) {
7576 +                       if (mbox->msg[chan]) {
7577 +                               /* Overflow */
7578 +                               printk(KERN_ERR DRIVER_NAME
7579 +                                      ": mbox chan %d overflow - drop %08x\n",
7580 +                                      chan, msg);
7581 +                       } else {
7582 +                               mbox->msg[chan] = (msg | 0xf);
7583 +                               up(&mbox->sema[chan]);
7584 +                       }
7585 +               } else {
7586 +                       printk(KERN_ERR DRIVER_NAME
7587 +                              ": invalid channel selector (msg %08x)\n", msg);
7588 +               }
7589 +               ret = IRQ_HANDLED;
7590 +               status = readl(mbox->status);
7591 +       }
7592 +       return ret;
7593 +}
7594 +
7595 +static struct irqaction mbox_irqaction = {
7596 +       .name = "ARM Mailbox IRQ",
7597 +       .flags = IRQF_DISABLED | IRQF_IRQPOLL,
7598 +       .handler = mbox_irq,
7599 +};
7600 +
7601 +/* ----------------------------------------------------------------------
7602 + *     Mailbox Methods
7603 + * -------------------------------------------------------------------- */
7604 +
7605 +static struct device *mbox_dev;        /* we assume there's only one! */
7606 +
7607 +static int dev_mbox_write(struct device *dev, unsigned chan, uint32_t data28)
7608 +{
7609 +       int rc;
7610 +
7611 +       struct vc_mailbox *mailbox = dev_get_drvdata(dev);
7612 +       device_lock(dev);
7613 +       rc = mbox_write(mailbox, chan, data28);
7614 +       device_unlock(dev);
7615 +
7616 +       return rc;
7617 +}
7618 +
7619 +static int dev_mbox_read(struct device *dev, unsigned chan, uint32_t *data28)
7620 +{
7621 +       int rc;
7622 +
7623 +       struct vc_mailbox *mailbox = dev_get_drvdata(dev);
7624 +       device_lock(dev);
7625 +       rc = mbox_read(mailbox, chan, data28);
7626 +       device_unlock(dev);
7627 +
7628 +       return rc;
7629 +}
7630 +
7631 +extern int bcm_mailbox_write(unsigned chan, uint32_t data28)
7632 +{
7633 +       if (mbox_dev)
7634 +               return dev_mbox_write(mbox_dev, chan, data28);
7635 +       else
7636 +               return -ENODEV;
7637 +}
7638 +EXPORT_SYMBOL_GPL(bcm_mailbox_write);
7639 +
7640 +extern int bcm_mailbox_read(unsigned chan, uint32_t *data28)
7641 +{
7642 +       if (mbox_dev)
7643 +               return dev_mbox_read(mbox_dev, chan, data28);
7644 +       else
7645 +               return -ENODEV;
7646 +}
7647 +EXPORT_SYMBOL_GPL(bcm_mailbox_read);
7648 +
7649 +static void dev_mbox_register(const char *dev_name, struct device *dev)
7650 +{
7651 +       mbox_dev = dev;
7652 +}
7653 +
7654 +/* ----------------------------------------------------------------------
7655 + *     Platform Device for Mailbox
7656 + * -------------------------------------------------------------------- */
7657 +
7658 +static int bcm_vcio_probe(struct platform_device *pdev)
7659 +{
7660 +       int ret = 0;
7661 +       struct vc_mailbox *mailbox;
7662 +
7663 +       mailbox = kzalloc(sizeof(*mailbox), GFP_KERNEL);
7664 +       if (NULL == mailbox) {
7665 +               printk(KERN_ERR DRIVER_NAME ": failed to allocate "
7666 +                      "mailbox memory\n");
7667 +               ret = -ENOMEM;
7668 +       } else {
7669 +               struct resource *res;
7670 +
7671 +               res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7672 +               if (res == NULL) {
7673 +                       printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
7674 +                              "resource\n");
7675 +                       ret = -ENODEV;
7676 +                       kfree(mailbox);
7677 +               } else {
7678 +                       /* should be based on the registers from res really */
7679 +                       mbox_init(mailbox, &pdev->dev, ARM_0_MAIL0_RD);
7680 +
7681 +                       platform_set_drvdata(pdev, mailbox);
7682 +                       dev_mbox_register(DRIVER_NAME, &pdev->dev);
7683 +
7684 +                       mbox_irqaction.dev_id = mailbox;
7685 +                       setup_irq(IRQ_ARM_MAILBOX, &mbox_irqaction);
7686 +                       printk(KERN_INFO DRIVER_NAME ": mailbox at %p\n",
7687 +                              __io_address(ARM_0_MAIL0_RD));
7688 +               }
7689 +       }
7690 +       return ret;
7691 +}
7692 +
7693 +static int bcm_vcio_remove(struct platform_device *pdev)
7694 +{
7695 +       struct vc_mailbox *mailbox = platform_get_drvdata(pdev);
7696 +
7697 +       platform_set_drvdata(pdev, NULL);
7698 +       kfree(mailbox);
7699 +
7700 +       return 0;
7701 +}
7702 +
7703 +static struct platform_driver bcm_mbox_driver = {
7704 +       .probe = bcm_vcio_probe,
7705 +       .remove = bcm_vcio_remove,
7706 +
7707 +       .driver = {
7708 +                  .name = DRIVER_NAME,
7709 +                  .owner = THIS_MODULE,
7710 +                  },
7711 +};
7712 +
7713 +static int __init bcm_mbox_init(void)
7714 +{
7715 +       int ret;
7716 +
7717 +       printk(KERN_INFO "mailbox: Broadcom VideoCore Mailbox driver\n");
7718 +
7719 +       ret = platform_driver_register(&bcm_mbox_driver);
7720 +       if (ret != 0) {
7721 +               printk(KERN_ERR DRIVER_NAME ": failed to register "
7722 +                      "on platform\n");
7723 +       }
7724 +
7725 +       return ret;
7726 +}
7727 +
7728 +static void __exit bcm_mbox_exit(void)
7729 +{
7730 +       platform_driver_unregister(&bcm_mbox_driver);
7731 +}
7732 +
7733 +arch_initcall(bcm_mbox_init);  /* Initialize early */
7734 +module_exit(bcm_mbox_exit);
7735 +
7736 +MODULE_AUTHOR("Gray Girling");
7737 +MODULE_DESCRIPTION("ARM I/O to VideoCore processor");
7738 +MODULE_LICENSE("GPL");
7739 +MODULE_ALIAS("platform:bcm-mbox");
7740 --- a/arch/arm/mm/Kconfig
7741 +++ b/arch/arm/mm/Kconfig
7742 @@ -390,7 +390,7 @@ config CPU_PJ4
7743
7744  # ARMv6
7745  config CPU_V6
7746 -       bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
7747 +       bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708
7748         select CPU_32v6
7749         select CPU_ABRT_EV6
7750         select CPU_PABRT_V6
7751 --- a/arch/arm/mm/alignment.c
7752 +++ b/arch/arm/mm/alignment.c
7753 @@ -855,9 +855,11 @@ do_alignment(unsigned long addr, unsigne
7754         case 0x08000000:        /* ldm or stm, or thumb-2 32bit instruction */
7755                 if (thumb2_32b)
7756                         handler = do_alignment_t32_to_handler(&instr, regs, &offset);
7757 -               else
7758 +               else {
7759 +                        offset.un = 0; /* to keep compiler happy */
7760                         handler = do_alignment_ldmstm;
7761 -               break;
7762 +               }
7763 +                break;
7764
7765         default:
7766                 goto bad;
7767 --- a/arch/arm/mm/proc-v6.S
7768 +++ b/arch/arm/mm/proc-v6.S
7769 @@ -73,10 +73,19 @@ ENDPROC(cpu_v6_reset)
7770   *
7771   *     IRQs are already disabled.
7772   */
7773 +
7774 +/* See jira SW-5991 for details of this workaround */
7775  ENTRY(cpu_v6_do_idle)
7776 -       mov     r1, #0
7777 -       mcr     p15, 0, r1, c7, c10, 4          @ DWB - WFI may enter a low-power mode
7778 -       mcr     p15, 0, r1, c7, c0, 4           @ wait for interrupt
7779 +       .align 5
7780 +       mov     r1, #2
7781 +1:     subs    r1, #1
7782 +       nop
7783 +       mcreq   p15, 0, r1, c7, c10, 4          @ DWB - WFI may enter a low-power mode
7784 +       mcreq   p15, 0, r1, c7, c0, 4           @ wait for interrupt
7785 +       nop
7786 +       nop
7787 +       nop
7788 +       bne 1b
7789         mov     pc, lr
7790
7791  ENTRY(cpu_v6_dcache_clean_area)
7792 --- a/drivers/mmc/host/Kconfig
7793 +++ b/drivers/mmc/host/Kconfig
7794 @@ -229,6 +229,27 @@ config MMC_SDHCI_S3C_DMA
7795
7796           YMMV.
7797
7798 +config MMC_SDHCI_BCM2708
7799 +       tristate "SDHCI support on BCM2708"
7800 +       depends on MMC_SDHCI && MACH_BCM2708
7801 +       select MMC_SDHCI_IO_ACCESSORS
7802 +       help
7803 +         This selects the Secure Digital Host Controller Interface (SDHCI)
7804 +         often referrered to as the eMMC block.
7805 +
7806 +         If you have a controller with this interface, say Y or M here.
7807 +
7808 +         If unsure, say N.
7809 +
7810 +config MMC_SDHCI_BCM2708_DMA
7811 +       bool "DMA support on BCM2708 Arasan controller"
7812 +       depends on MMC_SDHCI_BCM2708 && EXPERIMENTAL
7813 +       help
7814 +         Enable DMA support on the Arasan SDHCI controller in Broadcom 2708
7815 +          based chips.
7816 +
7817 +          If unsure, say N.
7818 +
7819  config MMC_OMAP
7820         tristate "TI OMAP Multimedia Card Interface support"
7821         depends on ARCH_OMAP
7822 @@ -296,6 +317,14 @@ config MMC_ATMELMCI
7823           If unsure, say N.
7824
7825  endchoice
7826 +config MMC_BCM2708
7827 +       tristate "BCM2708 Multimedia Card Interface support"
7828 +       help
7829 +         This selects the BCM2708 Multimedia Card Interface driver. If
7830 +         you have a BCM2708 platform with a Multimedia Card
7831 +         slot, say Y or M here.
7832 +
7833 +         If unsure, say N.
7834
7835  config MMC_ATMELMCI_DMA
7836         bool "Atmel MCI DMA support"
7837 --- a/drivers/mmc/host/Makefile
7838 +++ b/drivers/mmc/host/Makefile
7839 @@ -14,6 +14,7 @@ obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-p
7840  obj-$(CONFIG_MMC_SDHCI_PXAV2)  += sdhci-pxav2.o
7841  obj-$(CONFIG_MMC_SDHCI_S3C)    += sdhci-s3c.o
7842  obj-$(CONFIG_MMC_SDHCI_SPEAR)  += sdhci-spear.o
7843 +obj-$(CONFIG_MMC_SDHCI_BCM2708)        += sdhci-bcm2708.o
7844  obj-$(CONFIG_MMC_WBSD)         += wbsd.o
7845  obj-$(CONFIG_MMC_AU1X)         += au1xmmc.o
7846  obj-$(CONFIG_MMC_OMAP)         += omap.o
7847 @@ -53,6 +54,8 @@ obj-$(CONFIG_MMC_SDHCI_TEGRA)         += sdhci-
7848  obj-$(CONFIG_MMC_SDHCI_OF_ESDHC)       += sdhci-of-esdhc.o
7849  obj-$(CONFIG_MMC_SDHCI_OF_HLWD)                += sdhci-of-hlwd.o
7850
7851 +obj-$(CONFIG_MMC_BCM2708)       += bcm2708_mci.o
7852 +
7853  ifeq ($(CONFIG_CB710_DEBUG),y)
7854         CFLAGS-cb710-mmc        += -DDEBUG
7855  endif
7856 --- /dev/null
7857 +++ b/drivers/mmc/host/bcm2708_mci.c
7858 @@ -0,0 +1,889 @@
7859 +/*
7860 + *  linux/drivers/mmc/host/bcm2708_mci.c - Broadcom BCM2708 MCI driver
7861 + *
7862 + *  Copyright (C) 2010 Broadcom, All Rights Reserved.
7863 + *
7864 + * This program is free software; you can redistribute it and/or modify
7865 + * it under the terms of the GNU General Public License version 2 as
7866 + * published by the Free Software Foundation.
7867 + */
7868 +
7869 +#include <linux/slab.h>
7870 +#include <linux/module.h>
7871 +#include <linux/moduleparam.h>
7872 +#include <linux/init.h>
7873 +#include <linux/ioport.h>
7874 +#include <linux/device.h>
7875 +#include <linux/interrupt.h>
7876 +#include <linux/delay.h>
7877 +#include <linux/err.h>
7878 +#include <linux/highmem.h>
7879 +#include <linux/log2.h>
7880 +#include <linux/mmc/host.h>
7881 +#include <linux/mmc/mmc.h>
7882 +#include <linux/mmc/sd.h>
7883 +#include <linux/platform_device.h>
7884 +#include <linux/clk.h>
7885 +#include <linux/scatterlist.h>
7886 +#include <linux/dma-mapping.h>
7887 +
7888 +#include <asm/cacheflush.h>
7889 +#include <asm/div64.h>
7890 +#include <asm/io.h>
7891 +#include <asm/sizes.h>
7892 +//#include <asm/mach/mmc.h>
7893 +
7894 +#include <mach/gpio.h>
7895 +
7896 +#include "bcm2708_mci.h"
7897 +
7898 +#define DRIVER_NAME "bcm2708_mci"
7899 +
7900 +//#define PIO_DEBUG
7901 +#ifdef PIO_DEBUG
7902 +#define DBG(host,fmt,args...)  \
7903 +       printk(KERN_ERR"%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
7904 +#else
7905 +#define DBG(host,fmt,args...)  \
7906 +       pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
7907 +#endif
7908 +
7909 +#define USE_DMA
7910 +#define USE_DMA_IRQ
7911 +
7912 +#ifdef USE_DMA
7913 +#define SDHOST_DMA_CHANNEL 5
7914 +#endif
7915 +
7916 +#define BCM2708_DMA_ACTIVE     (1 << 0)
7917 +#define BCM2708_DMA_INT                (1 << 2)
7918 +
7919 +#define BCM2708_DMA_INT_EN     (1 << 0)
7920 +#define BCM2708_DMA_D_INC      (1 << 4)
7921 +#define BCM2708_DMA_D_WIDTH    (1 << 5)
7922 +#define BCM2708_DMA_D_DREQ     (1 << 6)
7923 +#define BCM2708_DMA_S_INC      (1 << 8)
7924 +#define BCM2708_DMA_S_WIDTH    (1 << 9)
7925 +#define BCM2708_DMA_S_DREQ     (1 << 10)
7926 +
7927 +#define        BCM2708_DMA_PER_MAP(x)  ((x) << 16)
7928 +
7929 +#define BCM2708_DMA_DREQ_SDHOST        13
7930 +
7931 +#define BCM2708_DMA_CS         0x00
7932 +#define BCM2708_DMA_ADDR       0x04
7933 +
7934 +static void dump_sd_regs(void * mmc_base );
7935 +static int bcm2708_mci_reset(struct bcm2708_mci_host *host);
7936 +
7937 +static void do_command(void __iomem *base, u32 c, u32 a)
7938 +{
7939 +       u32 cmdsts = 0;
7940 +       writel(a, base + BCM2708_MCI_ARGUMENT);
7941 +       writel(c | BCM2708_MCI_ENABLE, base + BCM2708_MCI_COMMAND);
7942 +
7943 +       /* check for error and command done */
7944 +       cmdsts = readl(base + BCM2708_MCI_COMMAND);
7945 +       while ((cmdsts & BCM2708_MCI_ENABLE) && (!(cmdsts & BCM2708_MCI_FAIL_FLAG)))
7946 +               cmdsts = readl(base + BCM2708_MCI_COMMAND);
7947 +       if (cmdsts & BCM2708_MCI_FAIL_FLAG) {
7948 +               printk(KERN_DEBUG"%s: Command %d failed with arg %d\n", __func__, c, a);
7949 +               dump_sd_regs(base);
7950 +       }
7951 +}
7952 +
7953 +//static void discard_words(void __iomem *base, int words)
7954 +//{
7955 +//     int i;
7956 +//     for (i = 0; i < words; i++) {
7957 +//             while (!(readl(base + BCM2708_MCI_STATUS) & BCM2708_MCI_DATAFLAG));
7958 +//             readl(base + BCM2708_MCI_DATA);
7959 +//     }
7960 +//}
7961 +
7962 +#define CACHE_LINE_MASK 31
7963 +
7964 +static int suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
7965 +{
7966 +       int i;
7967 +
7968 +       for (i = 0; i < sg_len; i++) {
7969 +               if (sg_ptr[i].offset & CACHE_LINE_MASK || sg_ptr[i].length & CACHE_LINE_MASK)
7970 +                       return 0;
7971 +       }
7972 +
7973 +       return 1;
7974 +}
7975 +
7976 +static void wait_for_complete(struct bcm2708_mci_host *host,
7977 +                             void __iomem *mmc_base)
7978 +{
7979 +#ifdef USE_SDHOST_IRQ
7980 +#error not implemented yet
7981 +#else
7982 +       while ((readl(mmc_base + BCM2708_MCI_STATUS) &
7983 +               (BCM2708_MCI_HSTS_BUSY | BCM2708_MCI_HSTS_BLOCK)) == 0)
7984 +               continue;
7985 +
7986 +       writel(BCM2708_MCI_HSTS_BUSY | BCM2708_MCI_HSTS_BLOCK,
7987 +              mmc_base + BCM2708_MCI_STATUS);
7988 +#endif
7989 +}
7990 +
7991 +static void dump_sd_regs(void * mmc_base )
7992 +{
7993 +       printk(KERN_DEBUG"Registers:\n");
7994 +       printk(KERN_DEBUG"SDCMD:0x%x\n", readl(mmc_base + BCM2708_MCI_COMMAND));
7995 +       printk(KERN_DEBUG"SDARG:0x%x\n", readl(mmc_base + BCM2708_MCI_ARGUMENT));
7996 +       printk(KERN_DEBUG"SDTOUT:0x%x\n", readl(mmc_base + BCM2708_MCI_TIMEOUT));
7997 +       printk(KERN_DEBUG"SDCDIV:0x%x\n", readl(mmc_base + BCM2708_MCI_CLKDIV));
7998 +       printk(KERN_DEBUG"SDRSP0:0x%x\n", readl(mmc_base + BCM2708_MCI_RESPONSE0));
7999 +       printk(KERN_DEBUG"SDRSP1:0x%x\n", readl(mmc_base + BCM2708_MCI_RESPONSE1));
8000 +       printk(KERN_DEBUG"SDRSP2:0x%x\n", readl(mmc_base + BCM2708_MCI_RESPONSE2));
8001 +       printk(KERN_DEBUG"SDRSP3:0x%x\n", readl(mmc_base + BCM2708_MCI_RESPONSE3));
8002 +       printk(KERN_DEBUG"SDHSTS:0x%x\n", readl(mmc_base + BCM2708_MCI_STATUS));
8003 +       printk(KERN_DEBUG"SDPO:0x%x\n", readl(mmc_base + BCM2708_MCI_VDD));
8004 +       printk(KERN_DEBUG"SDEDM:0x%x\n", readl(mmc_base + BCM2708_MCI_EDM));
8005 +       printk(KERN_DEBUG"SDHCFG:0x%x\n", readl(mmc_base + BCM2708_MCI_HOSTCONFIG));
8006 +       printk(KERN_DEBUG"SDHBCT:0x%x\n", readl(mmc_base + BCM2708_MCI_HBCT));
8007 +       //printk(KERN_ERR"SDDATA:0x%x\n", readl(mmc_base + BCM2708_MCI_DATA));
8008 +       printk(KERN_DEBUG"SDHBLC:0x%x\n", readl(mmc_base + BCM2708_MCI_HBLC));
8009 +}
8010 +
8011 +
8012 +static void
8013 +bcm2708_mci_start_command(struct bcm2708_mci_host *host, struct mmc_command *cmd, struct mmc_data *data)
8014 +{
8015 +       void __iomem *mmc_base = host->mmc_base;
8016 +       void __iomem *dma_base = host->dma_base;
8017 +       u32 status;
8018 +       u32 c;
8019 +       int redo = 0;
8020 +
8021 +       DBG(host, "op %02x arg %08x flags %08x\n",
8022 +           cmd->opcode, cmd->arg, cmd->flags);
8023 +
8024 +back:
8025 +
8026 +       /*
8027 +        * clear the controller status register
8028 +        */
8029 +
8030 +       writel(-1, mmc_base + BCM2708_MCI_STATUS);
8031 +
8032 +       /*
8033 +        * build the command register write, incorporating no
8034 +         * response, long response, busy, read and write flags
8035 +        */
8036 +
8037 +       c = cmd->opcode;
8038 +       if (cmd->flags & MMC_RSP_PRESENT) {
8039 +               if (cmd->flags & MMC_RSP_136)
8040 +                       c |= BCM2708_MCI_LONGRESP;
8041 +       } else
8042 +               c |= BCM2708_MCI_NORESP;
8043 +       if (cmd->flags & MMC_RSP_BUSY)
8044 +               c |= BCM2708_MCI_BUSY;
8045 +
8046 +       if (data) {
8047 +               if (data->flags & MMC_DATA_READ)
8048 +                       c |= BCM2708_MCI_READ;
8049 +               else
8050 +                       c |= BCM2708_MCI_WRITE;
8051 +
8052 +               DBG(host, "BYTECOUT %d BLOCKCOUNT %d .. ",readl(mmc_base + BCM2708_MCI_HBCT), readl(mmc_base + BCM2708_MCI_HBLC));
8053 +               DBG(host, "set blocksize to %d\n", data->blksz);
8054 +               DBG(host, "set blockcnt to %d\n", data->blocks);
8055 +               writel( data->blksz, mmc_base + BCM2708_MCI_HBCT);
8056 +               writel(data->blocks, mmc_base + BCM2708_MCI_HBLC);
8057 +       }
8058 +
8059 +       /*
8060 +         * run the command and wait for it to complete
8061 +        */
8062 +
8063 +       DBG(host, "executing command=%d\n", cmd->opcode);
8064 +
8065 +       do_command(mmc_base, c, cmd->arg);
8066 +
8067 +       DBG(host, "done cmd=%d\n", cmd->opcode);
8068 +
8069 +       if (c & BCM2708_MCI_BUSY) {
8070 +
8071 +               DBG(host, "waiting for command(%d) to complete\n", cmd->opcode);
8072 +               wait_for_complete(host, mmc_base);
8073 +               DBG(host, "done waiting for command(%d)\n", cmd->opcode);
8074 +       }
8075 +
8076 +       /*
8077 +        * retrieve the response and error (if any)
8078 +        */
8079 +
8080 +       status = readl(mmc_base + BCM2708_MCI_STATUS);
8081 +
8082 +       if (cmd->flags & MMC_RSP_136) {
8083 +               cmd->resp[3] = readl(mmc_base + BCM2708_MCI_RESPONSE0);
8084 +               cmd->resp[2] = readl(mmc_base + BCM2708_MCI_RESPONSE1);
8085 +               cmd->resp[1] = readl(mmc_base + BCM2708_MCI_RESPONSE2);
8086 +               cmd->resp[0] = readl(mmc_base + BCM2708_MCI_RESPONSE3);
8087 +       } else {
8088 +               cmd->resp[0] = readl(mmc_base + BCM2708_MCI_RESPONSE0);
8089 +       }
8090 +
8091 +       if (status & BCM2708_MCI_CMDTIMEOUT) {
8092 +               printk(KERN_DEBUG "mmc driver saw timeout with opcode = %d, data = 0x%08x, timeout = %d", cmd->opcode, (unsigned int)data, readl(mmc_base + BCM2708_MCI_TIMEOUT));
8093 +               if (data)
8094 +                       printk(KERN_DEBUG " data->sg_len = %d\n", data->sg_len);
8095 +               else
8096 +                       printk(KERN_DEBUG "\n");
8097 +               if (!redo) {
8098 +                       printk(KERN_DEBUG "redo\n");
8099 +                       redo = 1;
8100 +                       goto back;
8101 +               } else
8102 +                       cmd->error = -ETIMEDOUT;
8103 +       }
8104 +
8105 +       /*
8106 +        * pump data if necessary
8107 +        */
8108 +
8109 +       if (data) {
8110 +               unsigned int sg_len = data->sg_len;
8111 +               struct scatterlist *sg_ptr = data->sg;
8112 +
8113 +               data->bytes_xfered = 0;
8114 +
8115 +#ifdef USE_DMA
8116 +               if (suitable_for_dma(sg_ptr, sg_len)) {
8117 +                       int i, count = dma_map_sg(&host->dev->dev, sg_ptr, sg_len, data->flags & MMC_DATA_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
8118 +
8119 +                       for (i = 0; i < count; i++) {
8120 +                               BCM2708_DMA_CB_T *cb = &host->cb_base[i];
8121 +
8122 +                               if (data->flags & MMC_DATA_READ) {
8123 +                                       cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_SDHOST)|BCM2708_DMA_S_DREQ|BCM2708_DMA_D_WIDTH|BCM2708_DMA_D_INC;
8124 +                                       cb->src = 0x7e202040;
8125 +                                       cb->dst = sg_dma_address(&sg_ptr[i]);
8126 +                               } else {
8127 +                                       cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_SDHOST)|BCM2708_DMA_S_WIDTH|BCM2708_DMA_S_INC|BCM2708_DMA_D_DREQ;
8128 +                                       cb->src = sg_dma_address(&sg_ptr[i]);
8129 +                                       cb->dst = 0x7e202040;
8130 +                               }
8131 +
8132 +                               cb->length = sg_dma_len(&sg_ptr[i]);
8133 +                               cb->stride = 0;
8134 +
8135 +                               if (i == count - 1) {
8136 +#ifdef USE_DMA_IRQ
8137 +                                       cb->info |= BCM2708_DMA_INT_EN;
8138 +#endif
8139 +                                       cb->next = 0;
8140 +                               } else
8141 +                                       cb->next = host->cb_handle + (i + 1) * sizeof(BCM2708_DMA_CB_T);
8142 +
8143 +                               cb->pad[0] = 0;
8144 +                               cb->pad[1] = 0;
8145 +
8146 +                               data->bytes_xfered += sg_ptr[i].length;
8147 +                       }
8148 +
8149 +                       dsb();  // data barrier operation
8150 +
8151 +                       writel(host->cb_handle, dma_base + BCM2708_DMA_ADDR);
8152 +                       writel(BCM2708_DMA_ACTIVE, dma_base + BCM2708_DMA_CS);
8153 +
8154 +#ifdef USE_DMA_IRQ
8155 +                       down(&host->sem);
8156 +#else
8157 +                       while ((readl(dma_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE));
8158 +#endif
8159 +                       dma_unmap_sg(&host->dev->dev, sg_ptr, sg_len, data->flags & MMC_DATA_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
8160 +               } else
8161 +#endif
8162 +               while (sg_len) {
8163 +                       unsigned long flags;
8164 +                       char *buffer;
8165 +                       u32 *ptr, *lim;
8166 +
8167 +                       DBG(host, "sg_len=%d sg_ptr=%p len=%d\n", sg_len, sg_ptr, sg_ptr->length);
8168 +
8169 +                       /*
8170 +                        * map the current scatter buffer
8171 +                        */
8172 +
8173 +                       buffer = bcm2708_mci_kmap_atomic(sg_ptr, &flags);
8174 +
8175 +                       /*
8176 +                        * pump the data
8177 +                        */
8178 +
8179 +                       ptr = (u32 *)(buffer);
8180 +                       lim = (u32 *)(buffer + sg_ptr->length);
8181 +
8182 +                       while (ptr < lim)
8183 +                       {
8184 +#ifdef PIO_DEBUG
8185 +                               unsigned int wait_count = 1;
8186 +#endif
8187 +                               while (!(readl(mmc_base + BCM2708_MCI_STATUS) & BCM2708_MCI_DATAFLAG))
8188 +                               {
8189 +#ifdef PIO_DEBUG
8190 +                                       wait_count++;
8191 +                                       if ( 0 == (wait_count % 20000) ) {
8192 +
8193 +                                               printk(KERN_ERR"Timeout waiting for data flag\n");
8194 +                                               dump_sd_regs(mmc_base);
8195 +                                       }
8196 +#endif
8197 +                               }
8198 +
8199 +                               if (data->flags & MMC_DATA_READ)
8200 +                                       *ptr++ = readl(mmc_base + BCM2708_MCI_DATA);
8201 +                               else
8202 +                               {
8203 +#ifdef PIO_DEBUG
8204 +                                       uint32_t fifo_bytes, fifo_wait_count = 1;
8205 +
8206 +                                       fifo_bytes = readl(mmc_base + BCM2708_MCI_EDM);
8207 +                                       fifo_bytes = (fifo_bytes >> 4)  & 0xf;
8208 +
8209 +                                       while(fifo_bytes > 3)
8210 +                                       {
8211 +                                               fifo_wait_count++;
8212 +                                               if ( 0 == (fifo_wait_count % 20000) ) {
8213 +                                                       printk(KERN_ERR"waiting for fifo_bytes < 3\n");
8214 +                                                       dump_sd_regs(mmc_base);
8215 +                                               }
8216 +
8217 +                                               fifo_bytes = readl(mmc_base + BCM2708_MCI_EDM);
8218 +                                               fifo_bytes = (fifo_bytes >> 4)  & 0xf;
8219 +                                       }
8220 +
8221 +                                       BUG_ON(fifo_bytes > 3);
8222 +#endif
8223 +                                       writel(*ptr++, mmc_base + BCM2708_MCI_DATA);
8224 +                               }
8225 +                       }
8226 +
8227 +                       DBG(host, "done reading/writing %d bytes from mmc\n", sg_ptr->length);
8228 +
8229 +
8230 +                       /*
8231 +                        * unmap the buffer
8232 +                        */
8233 +
8234 +                       bcm2708_mci_kunmap_atomic(buffer, &flags);
8235 +
8236 +                       /*
8237 +                        * if we were reading, and we have completed this
8238 +                        * page, ensure that the data cache is coherent
8239 +                        */
8240 +
8241 +                       if (data->flags & MMC_DATA_READ)
8242 +                               flush_dcache_page(sg_page(sg_ptr));
8243 +
8244 +                       data->bytes_xfered += sg_ptr->length;
8245 +
8246 +                       sg_ptr++;
8247 +                       sg_len--;
8248 +               }
8249 +
8250 +//             if (host->is_acmd && cmd->opcode == SD_APP_SEND_SCR)
8251 +//                     discard_words(mmc_base, 126);
8252 +//             if (host->is_acmd && cmd->opcode == SD_APP_SEND_NUM_WR_BLKS)
8253 +//                     discard_words(mmc_base, 127);
8254 +//             if (!host->is_acmd && cmd->opcode == SD_SWITCH)
8255 +//                     discard_words(mmc_base, 112);
8256 +
8257 +               if (data->stop) {
8258 +
8259 +                       DBG(host, "sending stop command %p\n", data->stop);
8260 +                       bcm2708_mci_start_command(host, data->stop, 0);
8261 +
8262 +                       while ((readl(mmc_base + BCM2708_MCI_STATUS) &
8263 +                                        BCM2708_MCI_DATAFLAG))
8264 +                       {
8265 +                               DBG(host, "error data flag still set read=%d bytes\n", sg_ptr->length);
8266 +                               printk(KERN_ERR"SDDATA:0x%x\n", readl(mmc_base + BCM2708_MCI_DATA));
8267 +                               dump_sd_regs(mmc_base);
8268 +                       }
8269 +               }
8270 +       }
8271 +       /*
8272 +        * remember if we're an application command
8273 +        */
8274 +       host->is_acmd = cmd->opcode == MMC_APP_CMD;
8275 +}
8276 +
8277 +static void bcm2708_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
8278 +{
8279 +       struct bcm2708_mci_host *host = mmc_priv(mmc);
8280 +
8281 +       if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
8282 +               printk(KERN_ERR "%s: Unsupported block size (%d bytes)\n",
8283 +                       mmc_hostname(mmc), mrq->data->blksz);
8284 +               mrq->cmd->error = -EINVAL;
8285 +               mmc_request_done(mmc, mrq);
8286 +               return;
8287 +       }
8288 +
8289 +       bcm2708_mci_start_command(host, mrq->cmd, mrq->data);
8290 +
8291 +       mmc_request_done(host->mmc, mrq);
8292 +}
8293 +
8294 +static void bcm2708_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
8295 +{
8296 +
8297 +       struct bcm2708_mci_host *host = mmc_priv(mmc);
8298 +       void *mmc_base = host->mmc_base;
8299 +
8300 +
8301 +       printk(KERN_DEBUG"%s: Want to set clock: %d width: %d\n", mmc_hostname(mmc),
8302 +                       ios->clock, ios->bus_width);
8303 +
8304 +       if (ios->clock == 25000000 || ios->clock == 26000000) {
8305 +               printk(KERN_DEBUG"%s setting clock div to 10 (8+2)\n", mmc_hostname(mmc));
8306 +               writel(0x8, mmc_base + BCM2708_MCI_CLKDIV);
8307 +       } else if (ios->clock == 50000000 || ios->clock == 52000000) {
8308 +               printk(KERN_DEBUG"%s setting clock div to 5 (3+2)\n", mmc_hostname(mmc));
8309 +               writel(0x3, mmc_base + BCM2708_MCI_CLKDIV);
8310 +       } else {
8311 +               // On init or unknown clock, we set the clock really low
8312 +               printk(KERN_DEBUG"%s Setting clock div to 0x4e0\n", mmc_hostname(mmc));
8313 +               writel(0x4e0, mmc_base + BCM2708_MCI_CLKDIV);
8314 +       }
8315 +
8316 +       if (ios->bus_width) {
8317 +               uint32_t hcfg;
8318 +               hcfg = readl(mmc_base + BCM2708_MCI_HOSTCONFIG);
8319 +               printk(KERN_DEBUG"%s setting bus width to %d\n", mmc_hostname(mmc), ios->bus_width);
8320 +
8321 +               hcfg &= BCM2708_MCI_HOSTCONFIG_WIDEEXT_CLR;
8322 +               hcfg |= (ios->bus_width == MMC_BUS_WIDTH_4) ? BCM2708_MCI_HOSTCONFIG_WIDEEXT_4BIT : 0;
8323 +
8324 +               writel(hcfg, mmc_base + BCM2708_MCI_HOSTCONFIG);
8325 +       }
8326 +}
8327 +
8328 +static int bcm2708_mci_get_cd(struct mmc_host *mmc)
8329 +{
8330 +       int present = -ENOSYS;
8331 +
8332 +       struct bcm2708_mci_host *host = mmc_priv(mmc);
8333 +       void *gpio_base = host->gpio_base;
8334 +
8335 +       present = readl( (gpio_base + GP_LEV0) );
8336 +
8337 +       if ((present & (1<<29))==(1<<29))
8338 +               present = 0;
8339 +       else
8340 +               present = 1;
8341 +
8342 +       printk(KERN_DEBUG"***sdcard present***=%d\n", present);
8343 +
8344 +       // FIXME - For now force SD card present for 2835DK
8345 +       present = 1;
8346 +       return present;
8347 +}
8348 +
8349 +/*
8350 + * Handle completion of command and data transfers.
8351 + */
8352 +
8353 +//static irqreturn_t bcm2708_mci_command_irq(int irq, void *dev_id)
8354 +//{
8355 +//     struct bcm2708_mci_host *host = dev_id;
8356 +//
8357 +//     writel(BCM2708_DMA_INT, host->dma_base + BCM2708_DMA_CS);
8358 +//
8359 +//     printk(KERN_ERR "irq\n");
8360 +//
8361 +//     return IRQ_RETVAL(0);
8362 +//}
8363 +
8364 +static irqreturn_t bcm2708_mci_sddet_irq(int irq, void *dev_id)
8365 +{
8366 +       struct bcm2708_mci_host *host = dev_id;
8367 +       irqreturn_t handled = IRQ_NONE;
8368 +       int present;
8369 +
8370 +       present = bcm2708_mci_get_cd(host->mmc);
8371 +
8372 +       if (present!=host->present)
8373 +       {
8374 +               host->present = present;
8375 +               printk(KERN_DEBUG "SDDET IRQ: sdcard present: %d\n",present);
8376 +               bcm2708_mci_reset(host);
8377 +               mmc_detect_change(host->mmc, msecs_to_jiffies(500));
8378 +       }
8379 +
8380 +       return IRQ_RETVAL(handled);
8381 +}
8382 +
8383 +#ifdef USE_DMA_IRQ
8384 +static irqreturn_t bcm2708_mci_data_irq(int irq, void *dev_id)
8385 +{
8386 +       struct bcm2708_mci_host *host = dev_id;
8387 +        irqreturn_t handled = IRQ_NONE;
8388 +
8389 +       if (0 != (BCM2708_DMA_INT & readl(host->dma_base + BCM2708_DMA_CS))) {
8390 +               writel(BCM2708_DMA_INT, host->dma_base + BCM2708_DMA_CS);
8391 +               dsb();
8392 +               handled = IRQ_HANDLED;
8393 +               up(&host->sem);
8394 +       } else {
8395 +               printk(KERN_ERR"bcm2708_mci irq check failed !!\n");
8396 +       }
8397 +
8398 +       return IRQ_RETVAL(handled);
8399 +}
8400 +#endif
8401 +
8402 +static const struct mmc_host_ops bcm2708_mci_ops = {
8403 +       .request        = bcm2708_mci_request,
8404 +       .set_ios        = bcm2708_mci_set_ios,
8405 +       .get_cd         = bcm2708_mci_get_cd,
8406 +};
8407 +
8408 +static int bcm2708_mci_reset(struct bcm2708_mci_host *host)
8409 +{
8410 +
8411 +       void *mmc_base = host->mmc_base;
8412 +
8413 +       // pin muxing/gpios is done by vcloader
8414 +
8415 +       printk(KERN_DEBUG"%s:Resetting BCM2708 MCI Controller.\n", __func__ );
8416 +
8417 +       writel(0, mmc_base + BCM2708_MCI_COMMAND);
8418 +       writel(0, mmc_base + BCM2708_MCI_ARGUMENT);
8419 +       writel(0x00F00000, mmc_base + BCM2708_MCI_TIMEOUT);
8420 +       writel(0, mmc_base + BCM2708_MCI_CLKDIV);
8421 +       writel(0, mmc_base + BCM2708_MCI_STATUS);
8422 +       writel(0, mmc_base + BCM2708_MCI_VDD);
8423 +       writel(0, mmc_base + BCM2708_MCI_HOSTCONFIG);
8424 +       writel(0, mmc_base + BCM2708_MCI_HBCT);
8425 +       writel(0, mmc_base + BCM2708_MCI_HBLC);
8426 +
8427 +       writel( BCM2708_MCI_HOSTCONFIG_SLOW_CARD | BCM2708_MCI_HOSTCONFIG_BUSY_IRPT_EN |
8428 +                       BCM2708_MCI_HOSTCONFIG_BLOCK_IRPT_EN | BCM2708_MCI_HOSTCONFIG_WIDE_INT_BUS,
8429 +                       mmc_base + BCM2708_MCI_HOSTCONFIG);
8430 +
8431 +       // On A0 silicon it has been observed that the following must hold
8432 +       // WRITE_THRESHOLD<=5 and READ_THRESHOLD<=WRITE_THRESHOLD+1
8433 +       // with the chip running at 150MHz (with the interface running @ 150/22 = 6.8 MHz)
8434 +       // the second requirement suggests that the verilog does not properly separate the read / write FIFOs
8435 +       // On V3XDS Read=2 & Write=6
8436 +
8437 +#define READ_THRESHOLD  3
8438 +#define WRITE_THRESHOLD 3
8439 +#if 1 // !!! This is still required, without it we get CRC16 errors in data.
8440 +       {
8441 +               uint32_t temp;
8442 +               temp = readl(mmc_base + BCM2708_MCI_EDM);
8443 +               temp &= ~((0x1F<<14) | (0x1F<<9));
8444 +               temp  |= (WRITE_THRESHOLD << 9) | (READ_THRESHOLD << 14);
8445 +               writel(temp, mmc_base + BCM2708_MCI_EDM);
8446 +       }
8447 +#endif
8448 +
8449 +       // Power on delay
8450 +       mdelay(10);
8451 +       writel(BCM2708_MCI_VDD_ENABLE, mmc_base + BCM2708_MCI_VDD);
8452 +       mdelay(10);
8453 +
8454 +       return 0;
8455 +}
8456 +
8457 +
8458 +static int __devinit bcm2708_mci_probe(struct platform_device *pdev)
8459 +{
8460 +       struct mmc_host *mmc;
8461 +       struct bcm2708_mci_host *host;
8462 +       struct resource *mmc_res;
8463 +       struct resource *dma_res;
8464 +       struct resource *gpio_res;
8465 +       struct resource *dat_res;
8466 +       struct resource *sddet_res;
8467 +       int ret;
8468 +
8469 +       mmc = mmc_alloc_host(sizeof(struct bcm2708_mci_host), &pdev->dev);
8470 +       if (!mmc) {
8471 +               ret = -ENOMEM;
8472 +               dev_dbg(&pdev->dev, "couldn't allocate mmc host\n");
8473 +               goto fail0;
8474 +       }
8475 +
8476 +       host = mmc_priv(mmc);
8477 +       host->mmc = mmc;
8478 +
8479 +       host->dev = pdev;
8480 +
8481 +       sema_init(&host->sem, 0);
8482 +
8483 +#ifdef USE_DMA
8484 +       host->cb_base = dma_alloc_writecombine(&pdev->dev, SZ_4K, &host->cb_handle, GFP_KERNEL);
8485 +       if (!host->cb_base) {
8486 +               ret = -ENOMEM;
8487 +               dev_dbg(&pdev->dev, "couldn't allocate dma base\n");
8488 +               goto fail1;
8489 +       }
8490 +#endif
8491 +
8492 +       mmc_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8493 +       if (!mmc_res) {
8494 +               ret = -ENXIO;
8495 +               dev_dbg(&pdev->dev, "couldn't allocate mmc memory resource 0\n");
8496 +               goto fail2;
8497 +       }
8498 +
8499 +       if (!request_mem_region(mmc_res->start, mmc_res->end - mmc_res->start + 1, DRIVER_NAME)) {
8500 +               ret = -EBUSY;
8501 +               goto fail2;
8502 +       }
8503 +
8504 +       dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
8505 +       if (!dma_res) {
8506 +               ret = -ENXIO;
8507 +               dev_dbg(&pdev->dev, "couldn't allocate dma memory resource 1\n");
8508 +               goto fail3;
8509 +       }
8510 +
8511 +       /*
8512 +        * Map I/O regions
8513 +        */
8514 +
8515 +       host->mmc_base = ioremap(mmc_res->start, resource_size(mmc_res));
8516 +       if (!host->mmc_base) {
8517 +               ret = -ENOMEM;
8518 +               goto fail3;
8519 +       }
8520 +
8521 +       gpio_res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
8522 +       if (!gpio_res) {
8523 +               ret = -ENXIO;
8524 +               dev_dbg(&pdev->dev, "couldn't allocate gpio resource\n");
8525 +               goto fail4;
8526 +       }
8527 +
8528 +       /*
8529 +        * Map I/O regions
8530 +        */
8531 +
8532 +       host->gpio_base = ioremap(gpio_res->start, resource_size(gpio_res));
8533 +       if (!host->gpio_base) {
8534 +               ret = -ENOMEM;
8535 +               goto fail4;
8536 +       }
8537 +
8538 +#ifdef USE_DMA
8539 +       host->dma_base = __io_address(dma_res->start);
8540 +
8541 +       if (!host->dma_base) {
8542 +               ret = -ENOMEM;
8543 +               goto fail5;
8544 +       }
8545 +
8546 +       // USE DMA5 channel
8547 +       host->dma_base = (void __iomem *)((char *) host->dma_base + (SDHOST_DMA_CHANNEL * 0x100));
8548 +
8549 +       dev_dbg(&pdev->dev, "%s: using dma channel %d for sdhost\n", __func__, SDHOST_DMA_CHANNEL);
8550 +
8551 +       /*
8552 +        * Grab interrupts.
8553 +        */
8554 +#ifdef USE_DMA_IRQ
8555 +       dat_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
8556 +       if (!dat_res) {
8557 +               ret = -ENXIO;
8558 +               dev_dbg(&pdev->dev, "couldn't allocate irq for dma\n");
8559 +               goto fail5;
8560 +       }
8561 +
8562 +       ret = request_irq(dat_res->start, bcm2708_mci_data_irq, 0, DRIVER_NAME " (dat)", host);
8563 +       if (ret) {
8564 +               goto fail5;
8565 +       }
8566 +       dev_dbg(&pdev->dev, "%s: using dma interrupt number %d for sdhost\n", __func__, dat_res->start);
8567 +
8568 +#endif
8569 +#endif
8570 +
8571 +       host->present = bcm2708_mci_get_cd(host->mmc);
8572 +
8573 +       sddet_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
8574 +       if (!sddet_res) {
8575 +               ret = -ENXIO;
8576 +               dev_dbg(&pdev->dev, "couldn't allocate irq for sd detect\n");
8577 +               goto fail6;
8578 +       }
8579 +
8580 +       ret = request_irq(sddet_res->start, bcm2708_mci_sddet_irq, 0, DRIVER_NAME " (cmd)", host);
8581 +       if (ret) {
8582 +               goto fail6;
8583 +       }
8584 +
8585 +       host->is_acmd = 0;
8586 +
8587 +       mmc->ops = &bcm2708_mci_ops;
8588 +       mmc->f_min = 200000;
8589 +       mmc->f_max = 52000000;
8590 +       mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
8591 +
8592 +       /*
8593 +        * We can do SGIO
8594 +        */
8595 +       mmc->max_segs = NR_SG;
8596 +
8597 +       /*
8598 +        * Since we only have a 16-bit data length register, we must
8599 +        * ensure that we don't exceed 2^16-1 bytes in a single request.
8600 +        */
8601 +       mmc->max_req_size = 65535;
8602 +
8603 +       /*
8604 +        * Set the maximum segment size.  Since we aren't doing DMA
8605 +        * (yet) we are only limited by the data length register.
8606 +        */
8607 +       mmc->max_seg_size = mmc->max_req_size;
8608 +
8609 +       /*
8610 +        * Block size can be up to 2048 bytes, but must be a power of two.
8611 +        */
8612 +       mmc->max_blk_size = 2048;
8613 +
8614 +       /*
8615 +        * No limit on the number of blocks transferred.
8616 +        */
8617 +       mmc->max_blk_count = mmc->max_req_size;
8618 +
8619 +       /*
8620 +        * We support 4-bit data (at least on the DB)
8621 +        */
8622 +
8623 +       mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED) ;
8624 +
8625 +       bcm2708_mci_reset(host);
8626 +
8627 +       mmc_add_host(mmc);
8628 +
8629 +       printk(KERN_INFO "%s: BCM2708 SD host at 0x%08llx 0x%08llx\n",
8630 +               mmc_hostname(mmc),
8631 +               (unsigned long long)mmc_res->start, (unsigned long long)dma_res->start);
8632 +
8633 +       return 0;
8634 +
8635 +fail6:
8636 +#ifdef USE_DMA_IRQ
8637 +       free_irq(dat_res->start, host);
8638 +#endif
8639 +fail5:
8640 +       iounmap(host->gpio_base);
8641 +fail4:
8642 +       iounmap(host->mmc_base);
8643 +fail3:
8644 +       release_mem_region(mmc_res->start, mmc_res->end - mmc_res->start + 1);
8645 +fail2:
8646 +       dma_free_writecombine(&pdev->dev, SZ_4K, host->cb_base, host->cb_handle);
8647 +fail1:
8648 +       mmc_free_host(mmc);
8649 +fail0:
8650 +       dev_err(&pdev->dev, "probe failed, err %d\n", ret);
8651 +       return ret;
8652 +}
8653 +
8654 +static int __devexit bcm2708_mci_remove(struct platform_device *pdev)
8655 +{
8656 +       struct mmc_host *mmc = platform_get_drvdata(pdev);
8657 +
8658 +       if (mmc) {
8659 +               struct bcm2708_mci_host *host = mmc_priv(mmc);
8660 +               struct resource *res;
8661 +               struct resource *res2;
8662 +
8663 +               mmc_remove_host(mmc);
8664 +#ifdef USE_DMA
8665 +#ifdef USE_DMA_IRQ
8666 +               res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
8667 +               free_irq(res->start, host);
8668 +#endif
8669 +#endif
8670 +
8671 +               res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
8672 +               free_irq(res2->start, host);
8673 +
8674 +               iounmap(host->mmc_base);
8675 +               iounmap(host->gpio_base);
8676 +               iounmap(host->dma_base);
8677 +
8678 +               res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8679 +               release_mem_region(res->start, resource_size(res));
8680 +#ifdef USE_DMA
8681 +               dma_free_writecombine(&pdev->dev, SZ_4K, host->cb_base, host->cb_handle);
8682 +#endif
8683 +
8684 +               mmc_free_host(mmc);
8685 +               platform_set_drvdata(pdev, NULL);
8686 +
8687 +               return 0;
8688 +       } else
8689 +               return -1;
8690 +}
8691 +
8692 +#ifdef CONFIG_PM
8693 +static int bcm2708_mci_suspend(struct platform_device *dev, pm_message_t state)
8694 +{
8695 +       struct mmc_host *mmc = platform_get_drvdata(dev);
8696 +       int ret = 0;
8697 +
8698 +       if (mmc) {
8699 +               ret = mmc_suspend_host(mmc);
8700 +       }
8701 +
8702 +       return ret;
8703 +}
8704 +
8705 +static int bcm2708_mci_resume(struct platform_device *dev)
8706 +{
8707 +       struct mmc_host *mmc = platform_get_drvdata(dev);
8708 +       int ret = 0;
8709 +
8710 +       if (mmc) {
8711 +               ret = mmc_resume_host(mmc);
8712 +       }
8713 +
8714 +       return ret;
8715 +}
8716 +#else
8717 +#define bcm2708_mci_suspend    NULL
8718 +#define bcm2708_mci_resume     NULL
8719 +#endif
8720 +
8721 +static struct platform_driver bcm2708_mci_driver = {
8722 +       .probe          = bcm2708_mci_probe,
8723 +       .remove         = bcm2708_mci_remove,
8724 +       .suspend        = bcm2708_mci_suspend,
8725 +       .resume         = bcm2708_mci_resume,
8726 +       .driver         = {
8727 +               .name   = DRIVER_NAME,
8728 +               .owner  = THIS_MODULE,
8729 +       },
8730 +};
8731 +
8732 +static int __init bcm2708_mci_init(void)
8733 +{
8734 +       return platform_driver_register(&bcm2708_mci_driver);
8735 +}
8736 +
8737 +static void __exit bcm2708_mci_exit(void)
8738 +{
8739 +       platform_driver_unregister(&bcm2708_mci_driver);
8740 +}
8741 +
8742 +module_init(bcm2708_mci_init);
8743 +module_exit(bcm2708_mci_exit);
8744 +
8745 +MODULE_DESCRIPTION("BCM2708 Multimedia Card Interface driver");
8746 +MODULE_LICENSE("GPL");
8747 +MODULE_ALIAS("platform:bcm2708_mci");
8748 --- /dev/null
8749 +++ b/drivers/mmc/host/bcm2708_mci.h
8750 @@ -0,0 +1,101 @@
8751 +/*
8752 + *  linux/drivers/mmc/host/bcm2708_mci.c - Broadcom BCM2708 MCI driver
8753 + *
8754 + *  Copyright (C) 2010 Broadcom, All Rights Reserved.
8755 + *
8756 + * This program is free software; you can redistribute it and/or modify
8757 + * it under the terms of the GNU General Public License version 2 as
8758 + * published by the Free Software Foundation.
8759 + */
8760 +
8761 +struct clk;
8762 +
8763 +#define BCM2708_MCI_COMMAND    0x00
8764 +
8765 +#define BCM2708_MCI_READ       (1 << 6)
8766 +#define BCM2708_MCI_WRITE      (1 << 7)
8767 +#define BCM2708_MCI_LONGRESP   (1 << 9)
8768 +#define BCM2708_MCI_NORESP     (1 << 10)
8769 +#define BCM2708_MCI_BUSY       (1 << 11)
8770 +#define BCM2708_MCI_FAIL_FLAG  (1 << 14)
8771 +#define BCM2708_MCI_ENABLE     (1 << 15)
8772 +
8773 +#define BCM2708_MCI_ARGUMENT   0x04
8774 +
8775 +#define BCM2708_MCI_TIMEOUT    0x08
8776 +#define BCM2708_MCI_CLKDIV     0x0c
8777 +
8778 +
8779 +#define BCM2708_MCI_RESPONSE0  0x10
8780 +#define BCM2708_MCI_RESPONSE1  0x14
8781 +#define BCM2708_MCI_RESPONSE2  0x18
8782 +#define BCM2708_MCI_RESPONSE3  0x1c
8783 +
8784 +#define BCM2708_MCI_STATUS     0x20
8785 +
8786 +#define BCM2708_MCI_VDD        0x30
8787 +#define BCM2708_MCI_VDD_ENABLE (1 << 0)
8788 +
8789 +#define BCM2708_MCI_EDM        0x34
8790 +
8791 +#define BCM2708_MCI_HOSTCONFIG 0x38
8792 +
8793 +#define BCM2708_MCI_HOSTCONFIG_WIDE_INT_BUS 0x2
8794 +#define BCM2708_MCI_HOSTCONFIG_WIDEEXT_4BIT 0x4
8795 +#define BCM2708_MCI_HOSTCONFIG_SLOW_CARD 0x8
8796 +#define BCM2708_MCI_HOSTCONFIG_BLOCK_IRPT_EN (1<<8)
8797 +#define BCM2708_MCI_HOSTCONFIG_BUSY_IRPT_EN (1<<10)
8798 +#define BCM2708_MCI_HOSTCONFIG_WIDEEXT_CLR 0xFFFFFFFB
8799 +
8800 +
8801 +#define BCM2708_MCI_DATAFLAG   (1 << 0)
8802 +#define BCM2708_MCI_CMDTIMEOUT (1 << 6)
8803 +#define BCM2708_MCI_HSTS_BLOCK (1 << 9)        /**< block flag in status reg */
8804 +#define BCM2708_MCI_HSTS_BUSY  (1 << 10)       /**< Busy flag in status reg */
8805 +
8806 +#define BCM2708_MCI_HBCT       0x3c
8807 +#define BCM2708_MCI_DATA       0x40
8808 +#define BCM2708_MCI_HBLC       0x50
8809 +
8810 +#define NR_SG          16
8811 +
8812 +typedef struct bulk_data_struct
8813 +{
8814 +   unsigned long info;
8815 +   unsigned long src;
8816 +   unsigned long dst;
8817 +   unsigned long length;
8818 +   unsigned long stride;
8819 +   unsigned long next;
8820 +   unsigned long pad[2];
8821 +} BCM2708_DMA_CB_T;
8822 +
8823 +struct bcm2708_mci_host {
8824 +       struct platform_device  *dev;
8825 +
8826 +       void __iomem            *mmc_base;
8827 +       void __iomem            *dma_base;
8828 +       void __iomem            *gpio_base;
8829 +
8830 +       BCM2708_DMA_CB_T        *cb_base;
8831 +       dma_addr_t              cb_handle;
8832 +
8833 +       struct mmc_host         *mmc;
8834 +
8835 +       struct semaphore        sem;
8836 +
8837 +       int is_acmd;
8838 +       int present;
8839 +};
8840 +
8841 +static inline char *bcm2708_mci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
8842 +{
8843 +//     local_irq_save(*flags);
8844 +       return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
8845 +}
8846 +
8847 +static inline void bcm2708_mci_kunmap_atomic(void *buffer, unsigned long *flags)
8848 +{
8849 +       kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
8850 +//     local_irq_restore(*flags);
8851 +}
8852 --- /dev/null
8853 +++ b/drivers/mmc/host/sdhci-bcm2708.c
8854 @@ -0,0 +1,1461 @@
8855 +/*
8856 + * sdhci-bcm2708.c Support for SDHCI device on BCM2708
8857 + * Copyright (c) 2010 Broadcom
8858 + *
8859 + * This program is free software; you can redistribute it and/or modify
8860 + * it under the terms of the GNU General Public License version 2 as
8861 + * published by the Free Software Foundation.
8862 + *
8863 + * This program is distributed in the hope that it will be useful,
8864 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8865 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
8866 + * GNU General Public License for more details.
8867 + *
8868 + * You should have received a copy of the GNU General Public License
8869 + * along with this program; if not, write to the Free Software
8870 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
8871 + */
8872 +
8873 +/* Supports:
8874 + * SDHCI platform device - Arasan SD controller in BCM2708
8875 + *
8876 + * Inspired by sdhci-pci.c, by Pierre Ossman
8877 + */
8878 +
8879 +#include <linux/delay.h>
8880 +#include <linux/highmem.h>
8881 +#include <linux/platform_device.h>
8882 +#include <linux/module.h>
8883 +#include <linux/mmc/host.h>
8884 +
8885 +#include <linux/io.h>
8886 +#include <linux/dma-mapping.h>
8887 +#include <mach/dma.h>
8888 +#include <mach/power.h>
8889 +
8890 +#include "sdhci.h"
8891 +
8892 +/*****************************************************************************\
8893 + *                                                                          *
8894 + * Configuration                                                            *
8895 + *                                                                          *
8896 +\*****************************************************************************/
8897 +
8898 +#define DRIVER_NAME "bcm2708_sdhci"
8899 +
8900 +/* for the time being insist on DMA mode - PIO seems not to work */
8901 +#ifndef CONFIG_MMC_SDHCI_BCM2708_DMA
8902 +#warning Non-DMA (PIO) version of this driver currently unavailable
8903 +#endif
8904 +#undef CONFIG_MMC_SDHCI_BCM2708_DMA
8905 +#define CONFIG_MMC_SDHCI_BCM2708_DMA y
8906 +
8907 +#define USE_SYNC_AFTER_DMA
8908 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
8909 +/* #define CHECK_DMA_USE */
8910 +#endif
8911 +//#define LOG_REGISTERS
8912 +
8913 +#define USE_SCHED_TIME
8914 +
8915 +#define SDHCI_BCM_DMA_CHAN 4   /* this default is normally overriden */
8916 +#define SDHCI_BCM_DMA_WAITS 0  /* delays slowing DMA transfers: 0-31 */
8917 +/* We are worried that SD card DMA use may be blocking the AXI bus for others */
8918 +
8919 +/*! TODO: obtain these from the physical address */
8920 +#define DMA_SDHCI_BASE  0x7e300000  /* EMMC register block on Videocore */
8921 +#define DMA_SDHCI_BUFFER (DMA_SDHCI_BASE + SDHCI_BUFFER)
8922 +
8923 +#define BCM2708_SDHCI_SLEEP_TIMEOUT 1000   /* msecs */
8924 +
8925 +#define POWER_OFF 0
8926 +#define POWER_LAZY_OFF 1
8927 +#define POWER_ON  2
8928 +
8929 +
8930 +/*****************************************************************************\
8931 + *                                                                          *
8932 + * Debug                                                                    *
8933 + *                                                                          *
8934 +\*****************************************************************************/
8935 +
8936 +
8937 +
8938 +#define DBG(f, x...) \
8939 +       pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
8940 +//     printk(KERN_INFO DRIVER_NAME " [%s()]: " f, __func__,## x)//GRAYG
8941 +
8942 +
8943 +/*****************************************************************************\
8944 + *                                                                          *
8945 + * High Precision Time                                                      *
8946 + *                                                                          *
8947 +\*****************************************************************************/
8948 +
8949 +#ifdef USE_SCHED_TIME
8950 +
8951 +#include <mach/frc.h>
8952 +
8953 +typedef unsigned long hptime_t;
8954 +
8955 +#define FMT_HPT "lu"
8956 +
8957 +static inline hptime_t hptime(void)
8958 +{
8959 +       return frc_clock_ticks32();
8960 +}
8961 +
8962 +#define HPTIME_CLK_NS 1000ul
8963 +
8964 +#else
8965 +
8966 +typedef unsigned long hptime_t;
8967 +
8968 +#define FMT_HPT "lu"
8969 +
8970 +static inline hptime_t hptime(void)
8971 +{
8972 +       return jiffies;
8973 +}
8974 +
8975 +#define HPTIME_CLK_NS (1000000000ul/HZ)
8976 +
8977 +#endif
8978 +
8979 +static inline unsigned long int since_ns(hptime_t t)
8980 +{
8981 +       return (unsigned long)((hptime() - t) * HPTIME_CLK_NS);
8982 +}
8983 +
8984 +#if 0
8985 +static void hptime_test(void)
8986 +{
8987 +       hptime_t now;
8988 +       hptime_t later;
8989 +
8990 +       now = hptime();
8991 +       msleep(10);
8992 +       later = hptime();
8993 +
8994 +       printk(KERN_INFO DRIVER_NAME": 10ms = %"FMT_HPT" clks "
8995 +              "(from %"FMT_HPT" to %"FMT_HPT") = %luns\n",
8996 +              later-now, now, later,
8997 +              (unsigned long)(HPTIME_CLK_NS * (later - now)));
8998 +
8999 +       now = hptime();
9000 +       msleep(1000);
9001 +       later = hptime();
9002 +
9003 +       printk(KERN_INFO DRIVER_NAME": 1s = %"FMT_HPT" clks "
9004 +              "(from %"FMT_HPT" to %"FMT_HPT") = %luns\n",
9005 +              later-now, now, later,
9006 +              (unsigned long)(HPTIME_CLK_NS * (later - now)));
9007 +}
9008 +#endif
9009 +
9010 +/*****************************************************************************\
9011 + *                                                                          *
9012 + * SDHCI core callbacks                                                             *
9013 + *                                                                          *
9014 +\*****************************************************************************/
9015 +
9016 +
9017 +#ifdef CHECK_DMA_USE
9018 +/*#define CHECK_DMA_REG_USE*/
9019 +#endif
9020 +
9021 +#ifdef CHECK_DMA_REG_USE
9022 +/* we don't expect anything to be using these registers during a
9023 +   DMA (except the IRQ status) - so check */
9024 +static void check_dma_reg_use(struct sdhci_host *host, int reg);
9025 +#else
9026 +#define check_dma_reg_use(host, reg)
9027 +#endif
9028 +
9029 +
9030 +static inline u32 sdhci_bcm2708_raw_readl(struct sdhci_host *host, int reg)
9031 +{
9032 +       return readl(host->ioaddr + reg);
9033 +}
9034 +
9035 +u32 sdhci_bcm2708_readl(struct sdhci_host *host, int reg)
9036 +{
9037 +       u32 l = sdhci_bcm2708_raw_readl(host, reg);
9038 +
9039 +#ifdef LOG_REGISTERS
9040 +       printk(KERN_ERR "%s: readl from 0x%02x, value 0x%08x\n",
9041 +              mmc_hostname(host->mmc), reg, l);
9042 +#endif
9043 +       check_dma_reg_use(host, reg);
9044 +
9045 +       return l;
9046 +}
9047 +
9048 +u16 sdhci_bcm2708_readw(struct sdhci_host *host, int reg)
9049 +{
9050 +       u32 l = sdhci_bcm2708_raw_readl(host, reg & ~3);
9051 +       u32 w = l >> (reg << 3 & 0x18) & 0xffff;
9052 +
9053 +#ifdef LOG_REGISTERS
9054 +       printk(KERN_ERR "%s: readw from 0x%02x, value 0x%04x\n",
9055 +              mmc_hostname(host->mmc), reg, w);
9056 +#endif
9057 +       check_dma_reg_use(host, reg);
9058 +
9059 +       return (u16)w;
9060 +}
9061 +
9062 +u8 sdhci_bcm2708_readb(struct sdhci_host *host, int reg)
9063 +{
9064 +       u32 l = sdhci_bcm2708_raw_readl(host, reg & ~3);
9065 +       u32 b = l >> (reg << 3 & 0x18) & 0xff;
9066 +
9067 +#ifdef LOG_REGISTERS
9068 +       printk(KERN_ERR "%s: readb from 0x%02x, value 0x%02x\n",
9069 +              mmc_hostname(host->mmc), reg, b);
9070 +#endif
9071 +       check_dma_reg_use(host, reg);
9072 +
9073 +       return (u8)b;
9074 +}
9075 +
9076 +
9077 +static void sdhci_bcm2708_raw_writel(struct sdhci_host *host, u32 val, int reg)
9078 +{
9079 +       /* The Arasan has a bugette whereby it may lose the content of
9080 +        * successive writes to registers that are within two SD-card clock
9081 +        * cycles of each other (a clock domain crossing problem).
9082 +        * It seems, however, that the data register does not have this problem.
9083 +        * (Which is just as well - otherwise we'd have to nobble the DMA engine
9084 +        * too)
9085 +        */
9086 +#if 1
9087 +       if (reg != SDHCI_BUFFER && host->clock != 0) {
9088 +               /* host->clock is the clock freq in Hz */
9089 +               static hptime_t last_write_hpt;
9090 +               hptime_t now = hptime();
9091 +               unsigned int ns_2clk = 2000000000/host->clock;
9092 +
9093 +               if (now == last_write_hpt || now == last_write_hpt+1) {
9094 +                        /* we can't guarantee any significant time has
9095 +                         * passed - we'll have to wait anyway ! */
9096 +                       udelay((ns_2clk+1000-1)/1000);
9097 +               } else
9098 +               {
9099 +                       /* we must have waited at least this many ns: */
9100 +                       unsigned int ns_wait = HPTIME_CLK_NS *
9101 +                                              (last_write_hpt - now - 1);
9102 +                       if (ns_wait < ns_2clk)
9103 +                               udelay((ns_2clk-ns_wait+500)/1000);
9104 +               }
9105 +               last_write_hpt = now;
9106 +       }
9107 +       writel(val, host->ioaddr + reg);
9108 +#else
9109 +       void __iomem * regaddr = host->ioaddr + reg;
9110 +
9111 +       writel(val, regaddr);
9112 +
9113 +       if (reg != SDHCI_BUFFER && reg != SDHCI_INT_STATUS && host->clock != 0)
9114 +       {
9115 +               int timeout = 100000;
9116 +               while (val != readl(regaddr) && --timeout > 0)
9117 +                  continue;
9118 +
9119 +               if (timeout <= 0)
9120 +                       printk(KERN_ERR "%s: writing 0x%X to reg 0x%X "
9121 +                              "always gives 0x%X\n",
9122 +                              mmc_hostname(host->mmc),
9123 +                              val, reg, readl(regaddr));
9124 +               BUG_ON(timeout <= 0);
9125 +       }
9126 +#endif
9127 +}
9128 +
9129 +
9130 +void sdhci_bcm2708_writel(struct sdhci_host *host, u32 val, int reg)
9131 +{
9132 +#ifdef LOG_REGISTERS
9133 +       printk(KERN_ERR "%s: writel to 0x%02x, value 0x%08x\n",
9134 +              mmc_hostname(host->mmc), reg, val);
9135 +#endif
9136 +       check_dma_reg_use(host, reg);
9137 +
9138 +       sdhci_bcm2708_raw_writel(host, val, reg);
9139 +}
9140 +
9141 +void sdhci_bcm2708_writew(struct sdhci_host *host, u16 val, int reg)
9142 +{
9143 +       static u32 shadow = 0;
9144 +
9145 +       u32 p = reg == SDHCI_COMMAND ? shadow :
9146 +                      sdhci_bcm2708_raw_readl(host, reg & ~3);
9147 +       u32 s = reg << 3 & 0x18;
9148 +       u32 l = val << s;
9149 +       u32 m = 0xffff << s;
9150 +
9151 +#ifdef LOG_REGISTERS
9152 +       printk(KERN_ERR "%s: writew to 0x%02x, value 0x%04x\n",
9153 +              mmc_hostname(host->mmc), reg, val);
9154 +#endif
9155 +
9156 +       if (reg == SDHCI_TRANSFER_MODE)
9157 +               shadow = (p & ~m) | l;
9158 +       else {
9159 +               check_dma_reg_use(host, reg);
9160 +               sdhci_bcm2708_raw_writel(host, (p & ~m) | l, reg & ~3);
9161 +       }
9162 +}
9163 +
9164 +void sdhci_bcm2708_writeb(struct sdhci_host *host, u8 val, int reg)
9165 +{
9166 +       u32 p = sdhci_bcm2708_raw_readl(host, reg & ~3);
9167 +       u32 s = reg << 3 & 0x18;
9168 +       u32 l = val << s;
9169 +       u32 m = 0xff << s;
9170 +
9171 +#ifdef LOG_REGISTERS
9172 +       printk(KERN_ERR "%s: writeb to 0x%02x, value 0x%02x\n",
9173 +              mmc_hostname(host->mmc), reg, val);
9174 +#endif
9175 +
9176 +       check_dma_reg_use(host, reg);
9177 +       sdhci_bcm2708_raw_writel(host, (p & ~m) | l, reg & ~3);
9178 +}
9179 +
9180 +static unsigned int sdhci_bcm2708_get_max_clock(struct sdhci_host *host)
9181 +{
9182 +       return 100000000;       // this value is in Hz (100MHz/4)
9183 +}
9184 +
9185 +static unsigned int sdhci_bcm2708_get_timeout_clock(struct sdhci_host *host)
9186 +{
9187 +       return 100000;          // this value is in kHz (100MHz/4)
9188 +}
9189 +
9190 +/*****************************************************************************\
9191 + *                                                                          *
9192 + * DMA Operation                                                            *
9193 + *                                                                          *
9194 +\*****************************************************************************/
9195 +
9196 +struct sdhci_bcm2708_priv {
9197 +       int                     dma_chan;
9198 +       int                     dma_irq;
9199 +       void __iomem           *dma_chan_base;
9200 +       struct bcm2708_dma_cb  *cb_base;   /* DMA control blocks */
9201 +       dma_addr_t              cb_handle;
9202 +       /* tracking scatter gather progress */
9203 +       unsigned                sg_ix;     /* scatter gather list index */
9204 +       unsigned                sg_done;   /* bytes in current sg_ix done */
9205 +       /* power management */
9206 +       BCM_POWER_HANDLE_T      power_handle;
9207 +       unsigned char           power_state; /* enable/disable power state */
9208 +       unsigned char           power_mode;  /* last set power mode */
9209 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
9210 +       unsigned char           dma_wanted;  /* DMA transfer requested */
9211 +       unsigned char           dma_waits;   /* wait states in DMAs */
9212 +#ifdef CHECK_DMA_USE
9213 +       unsigned char           dmas_pending; /* no of unfinished DMAs */
9214 +       hptime_t                when_started;
9215 +       hptime_t                when_reset;
9216 +       hptime_t                when_stopped;
9217 +#endif
9218 +#endif
9219 +       /* signalling the end of a transfer */
9220 +       void                  (*complete)(struct sdhci_host *);
9221 +};
9222 +
9223 +#define SDHCI_HOST_PRIV(host) \
9224 +       (struct sdhci_bcm2708_priv *)((struct sdhci_host *)(host)+1)
9225 +
9226 +
9227 +
9228 +#ifdef CHECK_DMA_REG_USE
9229 +static void check_dma_reg_use(struct sdhci_host *host, int reg)
9230 +{
9231 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
9232 +       if (host_priv->dma_wanted && reg != SDHCI_INT_STATUS) {
9233 +               printk(KERN_INFO"%s: accessing register 0x%x during DMA\n",
9234 +                      mmc_hostname(host->mmc), reg);
9235 +       }
9236 +}
9237 +#endif
9238 +
9239 +
9240 +
9241 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
9242 +
9243 +static void sdhci_clear_set_irqgen(struct sdhci_host *host, u32 clear, u32 set)
9244 +{
9245 +       u32 ier;
9246 +
9247 +       ier = sdhci_bcm2708_raw_readl(host, SDHCI_SIGNAL_ENABLE);
9248 +       ier &= ~clear;
9249 +       ier |= set;
9250 +       /* change which requests generate IRQs - makes no difference to
9251 +          the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */
9252 +       sdhci_bcm2708_raw_writel(host, ier, SDHCI_SIGNAL_ENABLE);
9253 +}
9254 +
9255 +static void sdhci_signal_irqs(struct sdhci_host *host, u32 irqs)
9256 +{
9257 +       sdhci_clear_set_irqgen(host, 0, irqs);
9258 +}
9259 +
9260 +static void sdhci_unsignal_irqs(struct sdhci_host *host, u32 irqs)
9261 +{
9262 +       sdhci_clear_set_irqgen(host, irqs, 0);
9263 +}
9264 +
9265 +
9266 +
9267 +static void schci_bcm2708_cb_read(struct sdhci_bcm2708_priv *host,
9268 +                                 int ix,
9269 +                                 dma_addr_t dma_addr, unsigned len,
9270 +                                 int /*bool*/ is_last)
9271 +{
9272 +       struct bcm2708_dma_cb *cb = &host->cb_base[ix];
9273 +        unsigned char dmawaits = host->dma_waits;
9274 +
9275 +       cb->info   = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) |
9276 +                    BCM2708_DMA_WAITS(dmawaits) |
9277 +                    BCM2708_DMA_S_DREQ  |
9278 +                    BCM2708_DMA_D_WIDTH |
9279 +                    BCM2708_DMA_D_INC;
9280 +       cb->src    = DMA_SDHCI_BUFFER;  /* DATA register DMA address */
9281 +       cb->dst    = dma_addr;
9282 +       cb->length = len;
9283 +       cb->stride = 0;
9284 +
9285 +       if (is_last) {
9286 +               cb->info |= BCM2708_DMA_INT_EN;
9287 +               cb->next = 0;
9288 +       } else
9289 +               cb->next = host->cb_handle +
9290 +                          (ix+1)*sizeof(struct bcm2708_dma_cb);
9291 +
9292 +       cb->pad[0] = 0;
9293 +       cb->pad[1] = 0;
9294 +}
9295 +
9296 +static void schci_bcm2708_cb_write(struct sdhci_bcm2708_priv *host,
9297 +                                  int ix,
9298 +                                  dma_addr_t dma_addr, unsigned len,
9299 +                                  int /*bool*/ is_last)
9300 +{
9301 +       struct bcm2708_dma_cb *cb = &host->cb_base[ix];
9302 +        unsigned char dmawaits = host->dma_waits;
9303 +
9304 +       /* We can make arbitrarily large writes as long as we specify DREQ to
9305 +          pace the delivery of bytes to the Arasan hardware */
9306 +       cb->info   = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) |
9307 +                    BCM2708_DMA_WAITS(dmawaits) |
9308 +                    BCM2708_DMA_D_DREQ  |
9309 +                    BCM2708_DMA_S_WIDTH |
9310 +                    BCM2708_DMA_S_INC;
9311 +       cb->src    = dma_addr;
9312 +       cb->dst    = DMA_SDHCI_BUFFER;  /* DATA register DMA address */
9313 +       cb->length = len;
9314 +       cb->stride = 0;
9315 +
9316 +       if (is_last) {
9317 +               cb->info |= BCM2708_DMA_INT_EN;
9318 +               cb->next = 0;
9319 +       } else
9320 +               cb->next = host->cb_handle +
9321 +                          (ix+1)*sizeof(struct bcm2708_dma_cb);
9322 +
9323 +       cb->pad[0] = 0;
9324 +       cb->pad[1] = 0;
9325 +}
9326 +
9327 +
9328 +static void schci_bcm2708_dma_go(struct sdhci_host *host)
9329 +{
9330 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
9331 +       void __iomem *dma_chan_base = host_priv->dma_chan_base;
9332 +
9333 +       BUG_ON(host_priv->dma_wanted);
9334 +#ifdef CHECK_DMA_USE
9335 +       if (host_priv->dma_wanted)
9336 +               printk(KERN_ERR "%s: DMA already in progress - "
9337 +                      "now %"FMT_HPT", last started %lu "
9338 +                      "reset %lu stopped %lu\n",
9339 +                      mmc_hostname(host->mmc),
9340 +                      hptime(), since_ns(host_priv->when_started),
9341 +                      since_ns(host_priv->when_reset),
9342 +                      since_ns(host_priv->when_stopped));
9343 +       else if (host_priv->dmas_pending > 0)
9344 +               printk(KERN_INFO "%s: note - new DMA when %d reset DMAs "
9345 +                      "already in progress - "
9346 +                      "now %"FMT_HPT", started %lu reset %lu stopped %lu\n",
9347 +                      mmc_hostname(host->mmc),
9348 +                      host_priv->dmas_pending,
9349 +                      hptime(), since_ns(host_priv->when_started),
9350 +                      since_ns(host_priv->when_reset),
9351 +                      since_ns(host_priv->when_stopped));
9352 +       host_priv->dmas_pending += 1;
9353 +       host_priv->when_started = hptime();
9354 +#endif
9355 +       host_priv->dma_wanted = 1;
9356 +       DBG("PDMA go - base %p handle %08X\n", dma_chan_base,
9357 +           host_priv->cb_handle);
9358 +       bcm_dma_start(dma_chan_base, host_priv->cb_handle);
9359 +}
9360 +
9361 +
9362 +static void
9363 +sdhci_platdma_read(struct sdhci_host *host, dma_addr_t dma_addr, size_t len)
9364 +{
9365 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
9366 +
9367 +       DBG("PDMA to read %d bytes\n", len);
9368 +       host_priv->sg_done += len;
9369 +       schci_bcm2708_cb_read(host_priv, 0, dma_addr, len, 1/*TRUE*/);
9370 +       schci_bcm2708_dma_go(host);
9371 +}
9372 +
9373 +
9374 +static void
9375 +sdhci_platdma_write(struct sdhci_host *host, dma_addr_t dma_addr, size_t len)
9376 +{
9377 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
9378 +
9379 +       DBG("PDMA to write %d bytes\n", len);
9380 +       //BUG_ON(0 != (len & 0x1ff));
9381 +
9382 +       host_priv->sg_done += len;
9383 +       schci_bcm2708_cb_write(host_priv, 0, dma_addr, len, 1/*TRUE*/);
9384 +       schci_bcm2708_dma_go(host);
9385 +}
9386 +
9387 +/*! space is avaiable to receive into or data is available to write
9388 +  Platform DMA exported function
9389 +*/
9390 +void
9391 +sdhci_bcm2708_platdma_avail(struct sdhci_host *host, unsigned int *ref_intmask,
9392 +                           void(*completion_callback)(struct sdhci_host *host))
9393 +{
9394 +       struct mmc_data *data = host->data;
9395 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
9396 +       int sg_ix;
9397 +       size_t bytes;
9398 +       dma_addr_t addr;
9399 +
9400 +       BUG_ON(NULL == data);
9401 +       BUG_ON(0 == data->blksz);
9402 +
9403 +       host_priv->complete = completion_callback;
9404 +
9405 +       sg_ix = host_priv->sg_ix;
9406 +       BUG_ON(sg_ix >= data->sg_len);
9407 +
9408 +       /* we can DMA blocks larger than blksz - it may hang the DMA
9409 +          channel but we are its only user */
9410 +       bytes = sg_dma_len(&data->sg[sg_ix]) - host_priv->sg_done;
9411 +       addr = sg_dma_address(&data->sg[sg_ix]) + host_priv->sg_done;
9412 +
9413 +       if (bytes > 0) {
9414 +               /* We're going to poll for read/write available state until
9415 +                  we finish this DMA
9416 +               */
9417 +
9418 +               if (data->flags & MMC_DATA_READ) {
9419 +                       if (*ref_intmask & SDHCI_INT_DATA_AVAIL)  {
9420 +                               sdhci_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
9421 +                                                   SDHCI_INT_SPACE_AVAIL);
9422 +                               sdhci_platdma_read(host, addr, bytes);
9423 +                       }
9424 +               } else {
9425 +                       if (*ref_intmask & SDHCI_INT_SPACE_AVAIL) {
9426 +                               sdhci_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
9427 +                                                   SDHCI_INT_SPACE_AVAIL);
9428 +                               sdhci_platdma_write(host, addr, bytes);
9429 +                       }
9430 +               }
9431 +       }
9432 +       /* else:
9433 +          we have run out of bytes that need transferring (e.g. we may be in
9434 +          the middle of the last DMA transfer), or
9435 +          it is also possible that we've been called when another IRQ is
9436 +          signalled, even though we've turned off signalling of our own IRQ */
9437 +
9438 +       *ref_intmask &= ~SDHCI_INT_DATA_END;
9439 +       /* don't let the main sdhci driver act on this .. we'll deal with it
9440 +          when we respond to the DMA - if one is currently in progress */
9441 +}
9442 +
9443 +/* is it possible to DMA the given mmc_data structure?
9444 +   Platform DMA exported function
9445 +*/
9446 +int /*bool*/
9447 +sdhci_bcm2708_platdma_dmaable(struct sdhci_host *host, struct mmc_data *data)
9448 +{
9449 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
9450 +       int ok = bcm_sg_suitable_for_dma(data->sg, data->sg_len);
9451 +
9452 +       if (!ok)
9453 +               DBG("Reverting to PIO - bad cache alignment\n");
9454 +
9455 +       else {
9456 +               host_priv->sg_ix = 0;    /* first SG index */
9457 +               host_priv->sg_done = 0;  /* no bytes done */
9458 +       }
9459 +
9460 +       return ok;
9461 +}
9462 +
9463 +#include <mach/arm_control.h> //GRAYG
9464 +/*! the current SD transacton has been abandonned
9465 +  We need to tidy up if we were in the middle of a DMA
9466 +  Platform DMA exported function
9467 +*/
9468 +void
9469 +sdhci_bcm2708_platdma_reset(struct sdhci_host *host, struct mmc_data *data)
9470 +{
9471 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
9472 +       unsigned long flags;
9473 +
9474 +       BUG_ON(NULL == host);
9475 +
9476 +       spin_lock_irqsave(&host->lock, flags);
9477 +
9478 +       if (host_priv->dma_wanted) {
9479 +               if (NULL == data) {
9480 +                       printk(KERN_ERR "%s: ongoing DMA reset - no data!\n",
9481 +                              mmc_hostname(host->mmc));
9482 +                       BUG_ON(NULL == data);
9483 +               } else {
9484 +                       struct scatterlist *sg;
9485 +                       int sg_len;
9486 +                       int sg_todo;
9487 +                       int rc;
9488 +                       unsigned long cs;
9489 +
9490 +                       sg = data->sg;
9491 +                       sg_len = data->sg_len;
9492 +                       sg_todo = sg_dma_len(&sg[host_priv->sg_ix]);
9493 +
9494 +                       cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS);
9495 +
9496 +                       if (!(BCM2708_DMA_ACTIVE & cs))
9497 +                               printk(KERN_INFO "%s: missed completion of "
9498 +                                      "cmd %d DMA (%d/%d [%d]/[%d]) - "
9499 +                                      "ignoring it\n",
9500 +                                      mmc_hostname(host->mmc),
9501 +                                      host->last_cmdop,
9502 +                                      host_priv->sg_done, sg_todo,
9503 +                                      host_priv->sg_ix+1, sg_len);
9504 +                       else
9505 +                               printk(KERN_INFO "%s: resetting ongoing cmd %d"
9506 +                                      "DMA before %d/%d [%d]/[%d] complete\n",
9507 +                                      mmc_hostname(host->mmc),
9508 +                                      host->last_cmdop,
9509 +                                      host_priv->sg_done, sg_todo,
9510 +                                      host_priv->sg_ix+1, sg_len);
9511 +#ifdef CHECK_DMA_USE
9512 +                       printk(KERN_INFO "%s: now %"FMT_HPT" started %lu "
9513 +                              "last reset %lu last stopped %lu\n",
9514 +                              mmc_hostname(host->mmc),
9515 +                              hptime(), since_ns(host_priv->when_started),
9516 +                              since_ns(host_priv->when_reset),
9517 +                              since_ns(host_priv->when_stopped));
9518 +                       {       unsigned long info, debug;
9519 +                               void __iomem *base;
9520 +                               unsigned long pend0, pend1, pend2;
9521 +
9522 +                               base = host_priv->dma_chan_base;
9523 +                               cs = readl(base + BCM2708_DMA_CS);
9524 +                               info = readl(base + BCM2708_DMA_INFO);
9525 +                               debug = readl(base + BCM2708_DMA_DEBUG);
9526 +                               printk(KERN_INFO "%s: DMA%d CS=%08lX TI=%08lX "
9527 +                                      "DEBUG=%08lX\n",
9528 +                                      mmc_hostname(host->mmc),
9529 +                                       host_priv->dma_chan,
9530 +                                      cs, info, debug);
9531 +                               pend0 = readl(__io_address(ARM_IRQ_PEND0));
9532 +                               pend1 = readl(__io_address(ARM_IRQ_PEND1));
9533 +                               pend2 = readl(__io_address(ARM_IRQ_PEND2));
9534 +
9535 +                               printk(KERN_INFO "%s: PEND0=%08lX "
9536 +                                      "PEND1=%08lX PEND2=%08lX\n",
9537 +                                      mmc_hostname(host->mmc),
9538 +                                      pend0, pend1, pend2);
9539 +
9540 +                               //gintsts = readl(__io_address(GINTSTS));
9541 +                               //gintmsk = readl(__io_address(GINTMSK));
9542 +                               //printk(KERN_INFO "%s: USB GINTSTS=%08lX"
9543 +                               //       "GINTMSK=%08lX\n",
9544 +                               //       mmc_hostname(host->mmc), gintsts, gintmsk);
9545 +                       }
9546 +#endif
9547 +                       rc = bcm_dma_abort(host_priv->dma_chan_base);
9548 +                       BUG_ON(rc != 0);
9549 +               }
9550 +               host_priv->dma_wanted = 0;
9551 +#ifdef CHECK_DMA_USE
9552 +               host_priv->when_reset = hptime();
9553 +#endif
9554 +       }
9555 +
9556 +       spin_unlock_irqrestore(&host->lock, flags);
9557 +}
9558 +
9559 +
9560 +static void sdhci_bcm2708_dma_complete_irq(struct sdhci_host *host,
9561 +                                          u32 dma_cs)
9562 +{
9563 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
9564 +       struct mmc_data *data;
9565 +       struct scatterlist *sg;
9566 +       int sg_len;
9567 +       int sg_ix;
9568 +       int sg_todo;
9569 +       unsigned long flags;
9570 +
9571 +       BUG_ON(NULL == host);
9572 +
9573 +       spin_lock_irqsave(&host->lock, flags);
9574 +       data = host->data;
9575 +
9576 +#ifdef CHECK_DMA_USE
9577 +       if (host_priv->dmas_pending <= 0)
9578 +               DBG("on completion no DMA in progress - "
9579 +                   "now %"FMT_HPT" started %lu reset %lu stopped %lu\n",
9580 +                   hptime(), since_ns(host_priv->when_started),
9581 +                   since_ns(host_priv->when_reset),
9582 +                   since_ns(host_priv->when_stopped));
9583 +       else if (host_priv->dmas_pending > 1)
9584 +               DBG("still %d DMA in progress after completion - "
9585 +                   "now %"FMT_HPT" started %lu reset %lu stopped %lu\n",
9586 +                   host_priv->dmas_pending - 1,
9587 +                   hptime(), since_ns(host_priv->when_started),
9588 +                   since_ns(host_priv->when_reset),
9589 +                   since_ns(host_priv->when_stopped));
9590 +       BUG_ON(host_priv->dmas_pending <= 0);
9591 +       host_priv->dmas_pending -= 1;
9592 +       host_priv->when_stopped = hptime();
9593 +#endif
9594 +       host_priv->dma_wanted = 0;
9595 +
9596 +       if (NULL == data) {
9597 +               DBG("PDMA unused completion - status 0x%X\n", dma_cs);
9598 +               spin_unlock_irqrestore(&host->lock, flags);
9599 +               return;
9600 +       }
9601 +       sg = data->sg;
9602 +       sg_len = data->sg_len;
9603 +       sg_todo = sg_dma_len(&sg[host_priv->sg_ix]);
9604 +
9605 +       DBG("PDMA complete %d/%d [%d]/[%d]..\n",
9606 +           host_priv->sg_done, sg_todo,
9607 +           host_priv->sg_ix+1, sg_len);
9608 +
9609 +       BUG_ON(host_priv->sg_done > sg_todo);
9610 +
9611 +       if (host_priv->sg_done >= sg_todo) {
9612 +               host_priv->sg_ix++;
9613 +               host_priv->sg_done = 0;
9614 +       }
9615 +
9616 +       sg_ix = host_priv->sg_ix;
9617 +       if (sg_ix < sg_len) {
9618 +               u32 irq_mask;
9619 +               /* Set off next DMA if we've got the capacity */
9620 +
9621 +               if (data->flags & MMC_DATA_READ)
9622 +                       irq_mask = SDHCI_INT_DATA_AVAIL;
9623 +               else
9624 +                       irq_mask = SDHCI_INT_SPACE_AVAIL;
9625 +
9626 +               /* We have to use the interrupt status register on the BCM2708
9627 +                  rather than the SDHCI_PRESENT_STATE register because latency
9628 +                  in the glue logic means that the information retrieved from
9629 +                  the latter is not always up-to-date w.r.t the DMA engine -
9630 +                  it may not indicate that a read or a write is ready yet */
9631 +               if (sdhci_bcm2708_raw_readl(host, SDHCI_INT_STATUS) &
9632 +                   irq_mask) {
9633 +                       size_t bytes = sg_dma_len(&sg[sg_ix]) -
9634 +                                      host_priv->sg_done;
9635 +                       dma_addr_t addr = sg_dma_address(&data->sg[sg_ix]) +
9636 +                                         host_priv->sg_done;
9637 +
9638 +                       /* acknowledge interrupt */
9639 +                       sdhci_bcm2708_raw_writel(host, irq_mask,
9640 +                                                SDHCI_INT_STATUS);
9641 +
9642 +                       BUG_ON(0 == bytes);
9643 +
9644 +                       if (data->flags & MMC_DATA_READ)
9645 +                               sdhci_platdma_read(host, addr, bytes);
9646 +                       else
9647 +                               sdhci_platdma_write(host, addr, bytes);
9648 +               } else {
9649 +                       DBG("PDMA - wait avail\n");
9650 +                       /* may generate an IRQ if already present */
9651 +                       sdhci_signal_irqs(host, SDHCI_INT_DATA_AVAIL |
9652 +                                               SDHCI_INT_SPACE_AVAIL);
9653 +               }
9654 +       } else {
9655 +#ifdef USE_SYNC_AFTER_DMA
9656 +               /* On the Arasan controller the stop command (which will be
9657 +                  scheduled after this completes) does not seem to work
9658 +                  properly if we allow it to be issued when we are
9659 +                  transferring data to/from the SD card.
9660 +                  We get CRC and DEND errors unless we wait for
9661 +                  the SD controller to finish reading/writing to the card. */
9662 +               u32 state_mask;
9663 +               int timeout=1000000;
9664 +               hptime_t now = hptime();
9665 +
9666 +               DBG("PDMA over - sync card\n");
9667 +               if (data->flags & MMC_DATA_READ)
9668 +                       state_mask = SDHCI_DOING_READ;
9669 +               else
9670 +                       state_mask = SDHCI_DOING_WRITE;
9671 +
9672 +               while (0 != (sdhci_bcm2708_raw_readl(host,
9673 +                                                    SDHCI_PRESENT_STATE) &
9674 +                            state_mask) && --timeout > 0)
9675 +                       continue;
9676 +
9677 +               if (1000000-timeout > 4000) /*ave. is about 3250*/
9678 +                       printk(KERN_INFO "%s: note - long %s sync %luns - "
9679 +                              "%d its.\n",
9680 +                              mmc_hostname(host->mmc),
9681 +                              data->flags & MMC_DATA_READ? "read": "write",
9682 +                              since_ns(now), 1000000-timeout);
9683 +               if (timeout <= 0)
9684 +                       printk(KERN_ERR"%s: final %s to SD card still "
9685 +                              "running\n",
9686 +                              mmc_hostname(host->mmc),
9687 +                              data->flags & MMC_DATA_READ? "read": "write");
9688 +#endif
9689 +               if (host_priv->complete) {
9690 +                       (*host_priv->complete)(host);
9691 +                       DBG("PDMA %s complete\n",
9692 +                           data->flags & MMC_DATA_READ?"read":"write");
9693 +                       sdhci_signal_irqs(host, SDHCI_INT_DATA_AVAIL |
9694 +                                               SDHCI_INT_SPACE_AVAIL);
9695 +               }
9696 +       }
9697 +       spin_unlock_irqrestore(&host->lock, flags);
9698 +}
9699 +
9700 +static irqreturn_t sdhci_bcm2708_dma_irq(int irq, void *dev_id)
9701 +{
9702 +       irqreturn_t result = IRQ_NONE;
9703 +       struct sdhci_host *host = dev_id;
9704 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
9705 +       u32 dma_cs; /* control and status register */
9706 +       unsigned long flags;
9707 +
9708 +       BUG_ON(NULL == dev_id);
9709 +       BUG_ON(NULL == host_priv->dma_chan_base);
9710 +
9711 +       spin_lock_irqsave(&host->lock, flags);
9712 +
9713 +       dma_cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS);
9714 +
9715 +       if (dma_cs & BCM2708_DMA_ERR) {
9716 +               unsigned long debug;
9717 +               debug = readl(host_priv->dma_chan_base +
9718 +                             BCM2708_DMA_DEBUG);
9719 +               printk(KERN_ERR "%s: DMA error - CS %lX DEBUG %lX\n",
9720 +                      mmc_hostname(host->mmc), (unsigned long)dma_cs,
9721 +                      (unsigned long)debug);
9722 +               /* reset error */
9723 +               writel(debug, host_priv->dma_chan_base +
9724 +                      BCM2708_DMA_DEBUG);
9725 +       }
9726 +       if (dma_cs & BCM2708_DMA_INT) {
9727 +               /* acknowledge interrupt */
9728 +               writel(BCM2708_DMA_INT,
9729 +                      host_priv->dma_chan_base + BCM2708_DMA_CS);
9730 +
9731 +               dsb(); /* ARM data synchronization (push) operation */
9732 +
9733 +               if (!host_priv->dma_wanted) {
9734 +                       /* ignore this interrupt - it was reset */
9735 +                       printk(KERN_INFO "%s: DMA IRQ %X ignored - "
9736 +                              "results were reset\n",
9737 +                              mmc_hostname(host->mmc), dma_cs);
9738 +#ifdef CHECK_DMA_USE
9739 +                       printk(KERN_INFO "%s: now %"FMT_HPT
9740 +                              " started %lu reset %lu stopped %lu\n",
9741 +                              mmc_hostname(host->mmc), hptime(),
9742 +                              since_ns(host_priv->when_started),
9743 +                              since_ns(host_priv->when_reset),
9744 +                              since_ns(host_priv->when_stopped));
9745 +                       host_priv->dmas_pending--;
9746 +#endif
9747 +               } else
9748 +                       sdhci_bcm2708_dma_complete_irq(host, dma_cs);
9749 +
9750 +               result = IRQ_HANDLED;
9751 +       }
9752 +
9753 +       spin_unlock_irqrestore(&host->lock, flags);
9754 +
9755 +       return result;
9756 +}
9757 +#endif /* CONFIG_MMC_SDHCI_BCM2708_DMA */
9758 +
9759 +
9760 +/***************************************************************************** \
9761 + *                                                                          *
9762 + * Device Attributes                                                        *
9763 + *                                                                          *
9764 +\*****************************************************************************/
9765 +
9766 +
9767 +/**
9768 + * Show the DMA-using status
9769 + */
9770 +static ssize_t attr_dma_show(struct device *_dev,
9771 +                            struct device_attribute *attr, char *buf)
9772 +{
9773 +       struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
9774 +
9775 +       if (host) {
9776 +               int use_dma = (host->flags & SDHCI_USE_PLATDMA? 1:0);
9777 +               return sprintf(buf, "%d\n", use_dma);
9778 +       } else
9779 +               return -EINVAL;
9780 +}
9781 +
9782 +/**
9783 + * Set the DMA-using status
9784 + */
9785 +static ssize_t attr_dma_store(struct device *_dev,
9786 +                             struct device_attribute *attr,
9787 +                             const char *buf, size_t count)
9788 +{
9789 +       struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
9790 +
9791 +       if (host) {
9792 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
9793 +               int on = simple_strtol(buf, NULL, 0);
9794 +               if (on) {
9795 +                       host->flags |= SDHCI_USE_PLATDMA;
9796 +                       printk(KERN_INFO "%s: DMA enabled\n",
9797 +                              mmc_hostname(host->mmc));
9798 +               } else {
9799 +                       host->flags &= ~(SDHCI_USE_PLATDMA | SDHCI_REQ_USE_DMA);
9800 +                       printk(KERN_INFO "%s: DMA disabled\n",
9801 +                              mmc_hostname(host->mmc));
9802 +               }
9803 +#endif
9804 +               return count;
9805 +       } else
9806 +               return -EINVAL;
9807 +}
9808 +
9809 +static DEVICE_ATTR(use_dma, S_IRUGO | S_IWUGO, attr_dma_show, attr_dma_store);
9810 +
9811 +
9812 +/**
9813 + * Show the DMA wait states used
9814 + */
9815 +static ssize_t attr_dmawait_show(struct device *_dev,
9816 +                                struct device_attribute *attr, char *buf)
9817 +{
9818 +       struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
9819 +
9820 +       if (host) {
9821 +               struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
9822 +               int dmawait = host_priv->dma_waits;
9823 +               return sprintf(buf, "%d\n", dmawait);
9824 +       } else
9825 +               return -EINVAL;
9826 +}
9827 +
9828 +/**
9829 + * Set the DMA wait state used
9830 + */
9831 +static ssize_t attr_dmawait_store(struct device *_dev,
9832 +                                 struct device_attribute *attr,
9833 +                                 const char *buf, size_t count)
9834 +{
9835 +       struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
9836 +
9837 +       if (host) {
9838 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
9839 +               struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
9840 +               int dma_waits = simple_strtol(buf, NULL, 0);
9841 +               if (dma_waits >= 0 && dma_waits < 32)
9842 +                        host_priv->dma_waits = dma_waits;
9843 +               else
9844 +                       printk(KERN_ERR "%s: illegal dma_waits value - %d",
9845 +                              mmc_hostname(host->mmc), dma_waits);
9846 +#endif
9847 +               return count;
9848 +       } else
9849 +               return -EINVAL;
9850 +}
9851 +
9852 +static DEVICE_ATTR(dma_wait, S_IRUGO | S_IWUGO,
9853 +                   attr_dmawait_show, attr_dmawait_store);
9854 +
9855 +
9856 +/**
9857 + * Show the DMA-using status
9858 + */
9859 +static ssize_t attr_status_show(struct device *_dev,
9860 +                               struct device_attribute *attr, char *buf)
9861 +{
9862 +       struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
9863 +
9864 +       if (host) {
9865 +               struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
9866 +               int power_state = host_priv->power_state;
9867 +               return sprintf(buf,
9868 +                              "present: yes\n"
9869 +                              "power: %s\n"
9870 +                              "clock: %u Hz\n"
9871 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
9872 +                              "dma: %s (%d waits)\n",
9873 +#else
9874 +                              "dma: unconfigured\n",
9875 +#endif
9876 +                              power_state == POWER_ON? "on":
9877 +                              power_state == POWER_OFF? "off":
9878 +                              power_state == POWER_LAZY_OFF? "lazy-off":
9879 +                              "<unknown>",
9880 +                              host->clock
9881 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
9882 +                              , (host->flags & SDHCI_USE_PLATDMA)? "on": "off"
9883 +                               , host_priv->dma_waits
9884 +#endif
9885 +                              );
9886 +       } else
9887 +               return -EINVAL;
9888 +}
9889 +
9890 +static DEVICE_ATTR(status, S_IRUGO, attr_status_show, NULL);
9891 +
9892 +/***************************************************************************** \
9893 + *                                                                          *
9894 + * Power Management                                                         *
9895 + *                                                                          *
9896 +\*****************************************************************************/
9897 +
9898 +
9899 +#ifdef CONFIG_PM
9900 +static int sdhci_bcm2708_suspend(struct platform_device *dev, pm_message_t state)
9901 +{
9902 +       struct sdhci_host *host = (struct sdhci_host *)
9903 +                                 platform_get_drvdata(dev);
9904 +       int ret = 0;
9905 +
9906 +       if (host->mmc) {
9907 +               ret = mmc_suspend_host(host->mmc);
9908 +       }
9909 +
9910 +       return ret;
9911 +}
9912 +
9913 +static int sdhci_bcm2708_resume(struct platform_device *dev)
9914 +{
9915 +       struct sdhci_host *host = (struct sdhci_host *)
9916 +                                 platform_get_drvdata(dev);
9917 +       int ret = 0;
9918 +
9919 +       if (host->mmc) {
9920 +               ret = mmc_resume_host(host->mmc);
9921 +       }
9922 +
9923 +       return ret;
9924 +}
9925 +#endif
9926 +
9927 +
9928 +/* Click forwards one step towards fully on */
9929 +static int sdhci_bcm2708_enable(struct sdhci_host *host)
9930 +{
9931 +       int rc;
9932 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
9933 +
9934 +       if (host_priv->power_state == POWER_OFF) {
9935 +               /* warning: may schedule - don't call in irq mode */
9936 +               rc = bcm_power_request(host_priv->power_handle,
9937 +                                      BCM_POWER_SDCARD);
9938 +
9939 +               if (rc == 0) {
9940 +                       mmc_power_restore_host(host->mmc);
9941 +                       host_priv->power_state = POWER_ON;
9942 +               } else if (rc != -EINTR)
9943 +                       printk(KERN_ERR "%s: mmc power up request failed - "
9944 +                              "rc %d\n",
9945 +                              mmc_hostname(host->mmc), rc);
9946 +       } else {
9947 +               host_priv->power_state = POWER_ON;
9948 +               rc = 0;
9949 +       }
9950 +
9951 +       return rc;
9952 +}
9953 +
9954 +/* Click backwards one step towards fully off */
9955 +static int sdhci_bcm2708_disable(struct sdhci_host *host, int lazy)
9956 +{
9957 +       int rc;
9958 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
9959 +
9960 +       if ((host_priv->power_state == POWER_ON) && lazy) {
9961 +               host_priv->power_state = POWER_LAZY_OFF;
9962 +               return BCM2708_SDHCI_SLEEP_TIMEOUT;
9963 +       }
9964 +
9965 +       /* warning: may schedule - don't call in irq mode */
9966 +       rc = bcm_power_request(host_priv->power_handle, BCM_POWER_NONE);
9967 +
9968 +       if (rc == 0)
9969 +               host_priv->power_state = POWER_OFF;
9970 +       else if (rc != -EINTR)
9971 +               printk(KERN_ERR "%s: mmc power down request failed - rc %d\n",
9972 +                      mmc_hostname(host->mmc), rc);
9973 +
9974 +       return rc;
9975 +}
9976 +
9977 +static int sdhci_bcm2708_set_plat_power(struct sdhci_host *host,
9978 +                                       int power_mode)
9979 +{
9980 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
9981 +       int rc;
9982 +
9983 +       do {
9984 +               rc = mmc_host_enable(host->mmc);
9985 +       } while (-EINTR == rc);
9986 +
9987 +       if (rc == 0) do {
9988 +               if (rc == 0 && power_mode != host_priv->power_mode)
9989 +               {
9990 +                       switch (power_mode)
9991 +                       {
9992 +                       case MMC_POWER_OFF:
9993 +                               rc = bcm_power_request(host_priv->power_handle,
9994 +                                                      BCM_POWER_NONE);
9995 +                               break;
9996 +
9997 +                       case MMC_POWER_UP:
9998 +                               rc = bcm_power_request(host_priv->power_handle,
9999 +                                                      BCM_POWER_SDCARD);
10000 +                               /*
10001 +                                * We need an extra 10ms delay of 10ms before we
10002 +                                * can apply clock after applying power
10003 +                                */
10004 +                               if (rc == 0)
10005 +                                   mdelay(10);
10006 +                               break;
10007 +
10008 +                       case MMC_POWER_ON:
10009 +                               mdelay(10);
10010 +                               /* do_send_init_stream = 1; */
10011 +                               break;
10012 +                       }
10013 +
10014 +                       if (rc == 0)
10015 +                           host_priv->power_mode = power_mode;
10016 +               }
10017 +       } while (-EINTR == rc);
10018 +
10019 +       if (rc == 0) do {
10020 +               if (rc == 0) {
10021 +                       if (power_mode == MMC_POWER_OFF)
10022 +                               rc = mmc_host_disable(host->mmc);
10023 +                       else
10024 +                               rc = mmc_host_lazy_disable(host->mmc);
10025 +               }
10026 +
10027 +       } while (-EINTR == rc);
10028 +
10029 +       return rc;
10030 +}
10031 +
10032 +/*****************************************************************************\
10033 + *                                                                           *
10034 + * Device quirk functions. Implemented as local ops because the flags        *
10035 + * field is out of space with newer kernels. This implementation can be      *
10036 + * back ported to older kernels as well.                                     *
10037 +\****************************************************************************/
10038 +static unsigned int sdhci_bcm2708_quirk_extra_ints(struct sdhci_host *host)
10039 +{
10040 +        return 1;
10041 +}
10042 +
10043 +static unsigned int sdhci_bcm2708_quirk_spurious_crc(struct sdhci_host *host)
10044 +{
10045 +        return 1;
10046 +}
10047 +
10048 +static unsigned int sdhci_bcm2708_quirk_voltage_broken(struct sdhci_host *host)
10049 +{
10050 +        return 1;
10051 +}
10052 +
10053 +static unsigned int sdhci_bcm2708_uhs_broken(struct sdhci_host *host)
10054 +{
10055 +        return 1;
10056 +}
10057 +
10058 +/***************************************************************************** \
10059 + *                                                                          *
10060 + * Device ops                                                               *
10061 + *                                                                          *
10062 +\*****************************************************************************/
10063 +
10064 +static struct sdhci_ops sdhci_bcm2708_ops = {
10065 +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
10066 +       .read_l = sdhci_bcm2708_readl,
10067 +       .read_w = sdhci_bcm2708_readw,
10068 +       .read_b = sdhci_bcm2708_readb,
10069 +       .write_l = sdhci_bcm2708_writel,
10070 +       .write_w = sdhci_bcm2708_writew,
10071 +       .write_b = sdhci_bcm2708_writeb,
10072 +#else
10073 +#error The BCM2708 SDHCI driver needs CONFIG_MMC_SDHCI_IO_ACCESSORS to be set
10074 +#endif
10075 +       //.enable_dma = NULL,
10076 +       //.set_clock = NULL,
10077 +       .get_max_clock = sdhci_bcm2708_get_max_clock,
10078 +       //.get_min_clock = NULL,
10079 +       .get_timeout_clock = sdhci_bcm2708_get_timeout_clock,
10080 +
10081 +       .enable = sdhci_bcm2708_enable,
10082 +       .disable = sdhci_bcm2708_disable,
10083 +       .set_plat_power = sdhci_bcm2708_set_plat_power,
10084 +
10085 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
10086 +       // Platform DMA operations
10087 +       .pdma_able  = sdhci_bcm2708_platdma_dmaable,
10088 +       .pdma_avail = sdhci_bcm2708_platdma_avail,
10089 +       .pdma_reset = sdhci_bcm2708_platdma_reset,
10090 +#endif
10091 +       .extra_ints = sdhci_bcm2708_quirk_extra_ints,
10092 +       .spurious_crc_acmd51 = sdhci_bcm2708_quirk_spurious_crc,
10093 +       .voltage_broken = sdhci_bcm2708_quirk_voltage_broken,
10094 +       .uhs_broken = sdhci_bcm2708_uhs_broken,
10095 +};
10096 +
10097 +/*****************************************************************************\
10098 + *                                                                          *
10099 + * Device probing/removal                                                   *
10100 + *                                                                          *
10101 +\*****************************************************************************/
10102 +
10103 +static int __devinit sdhci_bcm2708_probe(struct platform_device *pdev)
10104 +{
10105 +       struct sdhci_host *host;
10106 +       struct resource *iomem;
10107 +       struct sdhci_bcm2708_priv *host_priv;
10108 +       int ret;
10109 +
10110 +       BUG_ON(pdev == NULL);
10111 +
10112 +       iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
10113 +       if (!iomem) {
10114 +               ret = -ENOMEM;
10115 +               goto err;
10116 +       }
10117 +
10118 +       if (resource_size(iomem) != 0x100)
10119 +               dev_err(&pdev->dev, "Invalid iomem size. You may "
10120 +                       "experience problems.\n");
10121 +
10122 +       if (pdev->dev.parent)
10123 +               host = sdhci_alloc_host(pdev->dev.parent,
10124 +                                       sizeof(struct sdhci_bcm2708_priv));
10125 +       else
10126 +               host = sdhci_alloc_host(&pdev->dev,
10127 +                                       sizeof(struct sdhci_bcm2708_priv));
10128 +
10129 +       if (IS_ERR(host)) {
10130 +               ret = PTR_ERR(host);
10131 +               goto err;
10132 +       }
10133 +
10134 +       host->hw_name = "BCM2708_Arasan";
10135 +       host->ops = &sdhci_bcm2708_ops;
10136 +       host->irq = platform_get_irq(pdev, 0);
10137 +
10138 +       host->quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
10139 +                      SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
10140 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
10141 +       host->flags = SDHCI_USE_PLATDMA;
10142 +#endif
10143 +
10144 +       if (!request_mem_region(iomem->start, resource_size(iomem),
10145 +                               mmc_hostname(host->mmc))) {
10146 +               dev_err(&pdev->dev, "cannot request region\n");
10147 +               ret = -EBUSY;
10148 +               goto err_request;
10149 +       }
10150 +
10151 +       host->ioaddr = ioremap(iomem->start, resource_size(iomem));
10152 +       if (!host->ioaddr) {
10153 +               dev_err(&pdev->dev, "failed to remap registers\n");
10154 +               ret = -ENOMEM;
10155 +               goto err_remap;
10156 +       }
10157 +
10158 +       host_priv = SDHCI_HOST_PRIV(host);
10159 +
10160 +       host_priv->power_state = POWER_ON;
10161 +       ret = bcm_power_open(&host_priv->power_handle);
10162 +       if (ret != 0)
10163 +               goto err_power;
10164 +
10165 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
10166 +       host_priv->dma_wanted = 0;
10167 +#ifdef CHECK_DMA_USE
10168 +       host_priv->dmas_pending = 0;
10169 +       host_priv->when_started = 0;
10170 +       host_priv->when_reset = 0;
10171 +       host_priv->when_stopped = 0;
10172 +#endif
10173 +       host_priv->sg_ix = 0;
10174 +       host_priv->sg_done = 0;
10175 +       host_priv->complete = NULL;
10176 +       host_priv->dma_waits = SDHCI_BCM_DMA_WAITS;
10177 +
10178 +       host_priv->cb_base = dma_alloc_writecombine(&pdev->dev, SZ_4K,
10179 +                                                   &host_priv->cb_handle,
10180 +                                                   GFP_KERNEL);
10181 +       if (!host_priv->cb_base) {
10182 +               dev_err(&pdev->dev, "cannot allocate DMA CBs\n");
10183 +               ret = -ENOMEM;
10184 +               goto err_alloc_cb;
10185 +       }
10186 +
10187 +       ret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST,
10188 +                                &host_priv->dma_chan_base,
10189 +                                &host_priv->dma_irq);
10190 +       if (ret < 0) {
10191 +               dev_err(&pdev->dev, "couldn't allocate a DMA channel\n");
10192 +               goto err_add_dma;
10193 +       }
10194 +       host_priv->dma_chan = ret;
10195 +
10196 +       ret = request_irq(host_priv->dma_irq, sdhci_bcm2708_dma_irq,
10197 +                         IRQF_SHARED, DRIVER_NAME " (dma)", host);
10198 +       if (ret) {
10199 +               dev_err(&pdev->dev, "cannot set DMA IRQ\n");
10200 +               goto err_add_dma_irq;
10201 +       }
10202 +       DBG("DMA CBs %p handle %08X DMA%d %p DMA IRQ %d\n",
10203 +           host_priv->cb_base, (unsigned)host_priv->cb_handle,
10204 +           host_priv->dma_chan, host_priv->dma_chan_base,
10205 +           host_priv->dma_irq);
10206 +#endif
10207 +
10208 +       ret = sdhci_add_host(host);
10209 +       if (ret)
10210 +               goto err_add_host;
10211 +
10212 +       platform_set_drvdata(pdev, host);
10213 +       ret = device_create_file(&pdev->dev, &dev_attr_use_dma);
10214 +       ret = device_create_file(&pdev->dev, &dev_attr_dma_wait);
10215 +       ret = device_create_file(&pdev->dev, &dev_attr_status);
10216 +
10217 +       printk(KERN_INFO "%s: BCM2708 SDHC host at 0x%08llx DMA %d IRQ %d\n",
10218 +              mmc_hostname(host->mmc), (unsigned long long)iomem->start,
10219 +              host_priv->dma_chan, host_priv->dma_irq);
10220 +
10221 +       return 0;
10222 +
10223 +err_add_host:
10224 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
10225 +       free_irq(host_priv->dma_irq, host);
10226 +err_add_dma_irq:
10227 +       bcm_dma_chan_free(host_priv->dma_chan);
10228 +err_add_dma:
10229 +       dma_free_writecombine(&pdev->dev, SZ_4K, host_priv->cb_base,
10230 +                             host_priv->cb_handle);
10231 +err_alloc_cb:
10232 +#endif
10233 +       bcm_power_close(host_priv->power_handle);
10234 +err_power:
10235 +       iounmap(host->ioaddr);
10236 +err_remap:
10237 +       release_mem_region(iomem->start, resource_size(iomem));
10238 +err_request:
10239 +       sdhci_free_host(host);
10240 +err:
10241 +       dev_err(&pdev->dev, "probe failed, err %d\n", ret);
10242 +       return ret;
10243 +}
10244 +
10245 +static int __devexit sdhci_bcm2708_remove(struct platform_device *pdev)
10246 +{
10247 +       struct sdhci_host *host = platform_get_drvdata(pdev);
10248 +       struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
10249 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
10250 +       int dead;
10251 +       u32 scratch;
10252 +
10253 +       dead = 0;
10254 +       scratch = sdhci_bcm2708_readl(host, SDHCI_INT_STATUS);
10255 +       if (scratch == (u32)-1)
10256 +               dead = 1;
10257 +
10258 +       device_remove_file(&pdev->dev, &dev_attr_status);
10259 +       device_remove_file(&pdev->dev, &dev_attr_dma_wait);
10260 +       device_remove_file(&pdev->dev, &dev_attr_use_dma);
10261 +
10262 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
10263 +       free_irq(host_priv->dma_irq, host);
10264 +       dma_free_writecombine(&pdev->dev, SZ_4K, host_priv->cb_base,
10265 +                             host_priv->cb_handle);
10266 +#endif
10267 +       bcm_power_close(host_priv->power_handle);
10268 +       sdhci_remove_host(host, dead);
10269 +       iounmap(host->ioaddr);
10270 +       release_mem_region(iomem->start, resource_size(iomem));
10271 +       sdhci_free_host(host);
10272 +       platform_set_drvdata(pdev, NULL);
10273 +
10274 +       return 0;
10275 +}
10276 +
10277 +static struct platform_driver sdhci_bcm2708_driver = {
10278 +       .driver = {
10279 +               .name   = DRIVER_NAME,
10280 +               .owner  = THIS_MODULE,
10281 +       },
10282 +       .probe          = sdhci_bcm2708_probe,
10283 +       .remove         = __devexit_p(sdhci_bcm2708_remove),
10284 +
10285 +#ifdef CONFIG_PM
10286 +       .suspend = sdhci_bcm2708_suspend,
10287 +       .resume = sdhci_bcm2708_resume,
10288 +#endif
10289 +
10290 +};
10291 +
10292 +/*****************************************************************************\
10293 + *                                                                          *
10294 + * Driver init/exit                                                         *
10295 + *                                                                          *
10296 +\*****************************************************************************/
10297 +
10298 +static int __init sdhci_drv_init(void)
10299 +{
10300 +       return platform_driver_register(&sdhci_bcm2708_driver);
10301 +}
10302 +
10303 +static void __exit sdhci_drv_exit(void)
10304 +{
10305 +       platform_driver_unregister(&sdhci_bcm2708_driver);
10306 +}
10307 +
10308 +module_init(sdhci_drv_init);
10309 +module_exit(sdhci_drv_exit);
10310 +
10311 +MODULE_DESCRIPTION("Secure Digital Host Controller Interface platform driver");
10312 +MODULE_AUTHOR("Broadcom <info@broadcom.com>");
10313 +MODULE_LICENSE("GPL v2");
10314 +MODULE_ALIAS("platform:"DRIVER_NAME);
10315 +
10316 --- a/drivers/mmc/host/sdhci.c
10317 +++ b/drivers/mmc/host/sdhci.c
10318 @@ -27,6 +27,7 @@
10319
10320  #include <linux/mmc/mmc.h>
10321  #include <linux/mmc/host.h>
10322 +#include <linux/mmc/sd.h>
10323
10324  #include "sdhci.h"
10325
10326 @@ -66,6 +67,7 @@ static inline int sdhci_runtime_pm_put(s
10327  }
10328  #endif
10329
10330 +
10331  static void sdhci_dumpregs(struct sdhci_host *host)
10332  {
10333         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
10334 @@ -150,6 +152,9 @@ static void sdhci_set_card_detection(str
10335             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
10336                 return;
10337
10338 +       if (host->quirks2 & SDHCI_QUIRK2_OWN_CARD_DETECTION)
10339 +               return;
10340 +
10341         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
10342                               SDHCI_CARD_PRESENT;
10343         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
10344 @@ -299,7 +304,7 @@ static void sdhci_read_block_pio(struct
10345         u32 uninitialized_var(scratch);
10346         u8 *buf;
10347
10348 -       DBG("PIO reading\n");
10349 +       DBG("PIO reading %db\n", host->data->blksz);
10350
10351         blksize = host->data->blksz;
10352         chunk = 0;
10353 @@ -344,7 +349,7 @@ static void sdhci_write_block_pio(struct
10354         u32 scratch;
10355         u8 *buf;
10356
10357 -       DBG("PIO writing\n");
10358 +       DBG("PIO writing %db\n", host->data->blksz);
10359
10360         blksize = host->data->blksz;
10361         chunk = 0;
10362 @@ -383,19 +388,28 @@ static void sdhci_write_block_pio(struct
10363         local_irq_restore(flags);
10364  }
10365
10366 -static void sdhci_transfer_pio(struct sdhci_host *host)
10367 +static void sdhci_transfer_pio(struct sdhci_host *host, u32 intstate)
10368  {
10369         u32 mask;
10370 +       u32 state = 0;
10371 +       u32 intmask;
10372 +       int available;
10373
10374         BUG_ON(!host->data);
10375
10376         if (host->blocks == 0)
10377                 return;
10378
10379 -       if (host->data->flags & MMC_DATA_READ)
10380 +       if (host->data->flags & MMC_DATA_READ) {
10381                 mask = SDHCI_DATA_AVAILABLE;
10382 -       else
10383 +               intmask = SDHCI_INT_DATA_AVAIL;
10384 +       } else {
10385                 mask = SDHCI_SPACE_AVAILABLE;
10386 +               intmask = SDHCI_INT_SPACE_AVAIL;
10387 +       }
10388 +
10389 +       /* initially we can see whether we can procede using intstate */
10390 +       available = (intstate & intmask);
10391
10392         /*
10393          * Some controllers (JMicron JMB38x) mess up the buffer bits
10394 @@ -406,7 +420,7 @@ static void sdhci_transfer_pio(struct sd
10395                 (host->data->blocks == 1))
10396                 mask = ~0;
10397
10398 -       while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
10399 +       while (available) {
10400                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
10401                         udelay(100);
10402
10403 @@ -418,9 +432,11 @@ static void sdhci_transfer_pio(struct sd
10404                 host->blocks--;
10405                 if (host->blocks == 0)
10406                         break;
10407 +               state = sdhci_readl(host, SDHCI_PRESENT_STATE);
10408 +               available = state & mask;
10409         }
10410
10411 -       DBG("PIO transfer complete.\n");
10412 +       DBG("PIO transfer complete - %d blocks left.\n", host->blocks);
10413  }
10414
10415  static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
10416 @@ -693,7 +709,9 @@ static void sdhci_set_transfer_irqs(stru
10417         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
10418         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
10419
10420 -       if (host->flags & SDHCI_REQ_USE_DMA)
10421 +       /* platform DMA will begin on receipt of PIO irqs */
10422 +       if ((host->flags & SDHCI_REQ_USE_DMA) &&
10423 +           !(host->flags & SDHCI_USE_PLATDMA))
10424                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
10425         else
10426                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
10427 @@ -725,44 +743,25 @@ static void sdhci_prepare_data(struct sd
10428         host->data_early = 0;
10429         host->data->bytes_xfered = 0;
10430
10431 -       if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
10432 +       if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA | SDHCI_USE_PLATDMA))
10433                 host->flags |= SDHCI_REQ_USE_DMA;
10434
10435         /*
10436          * FIXME: This doesn't account for merging when mapping the
10437          * scatterlist.
10438          */
10439 -       if (host->flags & SDHCI_REQ_USE_DMA) {
10440 -               int broken, i;
10441 -               struct scatterlist *sg;
10442 -
10443 -               broken = 0;
10444 -               if (host->flags & SDHCI_USE_ADMA) {
10445 -                       if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
10446 -                               broken = 1;
10447 -               } else {
10448 -                       if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
10449 -                               broken = 1;
10450 -               }
10451 -
10452 -               if (unlikely(broken)) {
10453 -                       for_each_sg(data->sg, sg, data->sg_len, i) {
10454 -                               if (sg->length & 0x3) {
10455 -                                       DBG("Reverting to PIO because of "
10456 -                                               "transfer size (%d)\n",
10457 -                                               sg->length);
10458 -                                       host->flags &= ~SDHCI_REQ_USE_DMA;
10459 -                                       break;
10460 -                               }
10461 -                       }
10462 -               }
10463 -       }
10464
10465         /*
10466          * The assumption here being that alignment is the same after
10467          * translation to device address space.
10468          */
10469 -       if (host->flags & SDHCI_REQ_USE_DMA) {
10470 +       if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_PLATDMA)) ==
10471 +           (SDHCI_REQ_USE_DMA | SDHCI_USE_PLATDMA)) {
10472 +
10473 +               if (! sdhci_platdma_dmaable(host, data))
10474 +                       host->flags &= ~SDHCI_REQ_USE_DMA;
10475 +
10476 +       } else if (host->flags & SDHCI_REQ_USE_DMA) {
10477                 int broken, i;
10478                 struct scatterlist *sg;
10479
10480 @@ -821,7 +820,8 @@ static void sdhci_prepare_data(struct sd
10481                                  */
10482                                 WARN_ON(1);
10483                                 host->flags &= ~SDHCI_REQ_USE_DMA;
10484 -                       } else {
10485 +                       } else
10486 +                       if (!(host->flags & SDHCI_USE_PLATDMA)) {
10487                                 WARN_ON(sg_cnt != 1);
10488                                 sdhci_writel(host, sg_dma_address(data->sg),
10489                                         SDHCI_DMA_ADDRESS);
10490 @@ -837,11 +837,13 @@ static void sdhci_prepare_data(struct sd
10491         if (host->version >= SDHCI_SPEC_200) {
10492                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
10493                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
10494 -               if ((host->flags & SDHCI_REQ_USE_DMA) &&
10495 -                       (host->flags & SDHCI_USE_ADMA))
10496 -                       ctrl |= SDHCI_CTRL_ADMA32;
10497 -               else
10498 -                       ctrl |= SDHCI_CTRL_SDMA;
10499 +               if (! (host->flags & SDHCI_USE_PLATDMA)) {
10500 +                       if ((host->flags & SDHCI_REQ_USE_DMA) &&
10501 +                               (host->flags & SDHCI_USE_ADMA))
10502 +                               ctrl |= SDHCI_CTRL_ADMA32;
10503 +                       else
10504 +                               ctrl |= SDHCI_CTRL_SDMA;
10505 +               }
10506                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
10507         }
10508
10509 @@ -893,7 +895,8 @@ static void sdhci_set_transfer_mode(stru
10510
10511         if (data->flags & MMC_DATA_READ)
10512                 mode |= SDHCI_TRNS_READ;
10513 -       if (host->flags & SDHCI_REQ_USE_DMA)
10514 +       if ((host->flags & SDHCI_REQ_USE_DMA) &&
10515 +           !(host->flags & SDHCI_USE_PLATDMA))
10516                 mode |= SDHCI_TRNS_DMA;
10517
10518         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
10519 @@ -909,13 +912,16 @@ static void sdhci_finish_data(struct sdh
10520         host->data = NULL;
10521
10522         if (host->flags & SDHCI_REQ_USE_DMA) {
10523 -               if (host->flags & SDHCI_USE_ADMA)
10524 -                       sdhci_adma_table_post(host, data);
10525 -               else {
10526 +               /* we may have to abandon an ongoing platform DMA */
10527 +               if (host->flags & SDHCI_USE_PLATDMA)
10528 +                       sdhci_platdma_reset(host, data);
10529 +
10530 +               if (host->flags & (SDHCI_USE_PLATDMA | SDHCI_USE_SDMA)) {
10531                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
10532                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
10533                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
10534 -               }
10535 +               } else if (host->flags & SDHCI_USE_ADMA)
10536 +                        sdhci_adma_table_post(host, data);
10537         }
10538
10539         /*
10540 @@ -985,10 +991,16 @@ static void sdhci_send_command(struct sd
10541                 timeout--;
10542                 mdelay(1);
10543         }
10544 +       DBG("send cmd %d - wait 0x%X irq 0x%x\n", cmd->opcode, mask,
10545 +           sdhci_readl(host, SDHCI_INT_STATUS));
10546
10547         mod_timer(&host->timer, jiffies + 10 * HZ);
10548
10549         host->cmd = cmd;
10550 +       if (host->last_cmdop == MMC_APP_CMD)
10551 +               host->last_cmdop = -cmd->opcode;
10552 +       else
10553 +               host->last_cmdop = cmd->opcode;
10554
10555         sdhci_prepare_data(host, cmd);
10556
10557 @@ -1234,6 +1246,35 @@ static int sdhci_set_power(struct sdhci_
10558         return power;
10559  }
10560
10561 +/* Power on or off the circuitary supporting the register set */
10562 +static int sdhci_set_plat_power(struct sdhci_host *host, int power_mode)
10563 +{
10564 +       if (host->ops->set_plat_power)
10565 +               return host->ops->set_plat_power(host, power_mode);
10566 +       else
10567 +               return 0;
10568 +}
10569 +
10570 +/* Click forwards one step towards fully on */
10571 +static int sdhci_enable(struct mmc_host *mmc)
10572 +{
10573 +       struct sdhci_host *host;
10574 +
10575 +       host = mmc_priv(mmc);
10576 +
10577 +       return host->ops->enable? host->ops->enable(host): 0;
10578 +}
10579 +
10580 +/* Click backwards one step towards fully off */
10581 +static int sdhci_disable(struct mmc_host *mmc, int lazy)
10582 +{
10583 +       struct sdhci_host *host;
10584 +
10585 +       host = mmc_priv(mmc);
10586 +
10587 +       return host->ops->disable? host->ops->disable(host, lazy): 0;
10588 +}
10589 +
10590  /*****************************************************************************\
10591   *                                                                           *
10592   * MMC callbacks                                                             *
10593 @@ -1250,6 +1291,8 @@ static void sdhci_request(struct mmc_hos
10594
10595         sdhci_runtime_pm_get(host);
10596
10597 +       sdhci_runtime_pm_get(host);
10598 +
10599         spin_lock_irqsave(&host->lock, flags);
10600
10601         WARN_ON(host->mrq != NULL);
10602 @@ -1314,6 +1357,7 @@ static void sdhci_do_set_ios(struct sdhc
10603  {
10604         unsigned long flags;
10605         int vdd_bit = -1;
10606 +       int rc;
10607         u8 ctrl;
10608
10609         spin_lock_irqsave(&host->lock, flags);
10610 @@ -1383,7 +1427,7 @@ static void sdhci_do_set_ios(struct sdhc
10611         else
10612                 ctrl &= ~SDHCI_CTRL_HISPD;
10613
10614 -       if (host->version >= SDHCI_SPEC_300) {
10615 +       if (host->version >= SDHCI_SPEC_300 && !(host->ops->uhs_broken)) {
10616                 u16 clk, ctrl_2;
10617                 unsigned int clock;
10618
10619 @@ -1474,6 +1518,12 @@ static void sdhci_do_set_ios(struct sdhc
10620
10621         mmiowb();
10622         spin_unlock_irqrestore(&host->lock, flags);
10623 +
10624 +       if (ios->power_mode == MMC_POWER_OFF) {
10625 +               do
10626 +                       rc = sdhci_set_plat_power(host, ios->power_mode);
10627 +               while (rc == -EINTR);
10628 +       }
10629  }
10630
10631  static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
10632 @@ -1934,6 +1984,8 @@ static const struct mmc_host_ops sdhci_o
10633         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
10634         .execute_tuning                 = sdhci_execute_tuning,
10635         .enable_preset_value            = sdhci_enable_preset_value,
10636 +       .enable         = sdhci_enable,
10637 +       .disable        = sdhci_disable,
10638  };
10639
10640  /*****************************************************************************\
10641 @@ -2091,10 +2143,13 @@ static void sdhci_cmd_irq(struct sdhci_h
10642         BUG_ON(intmask == 0);
10643
10644         if (!host->cmd) {
10645 -               pr_err("%s: Got command interrupt 0x%08x even "
10646 -                       "though no command operation was in progress.\n",
10647 -                       mmc_hostname(host->mmc), (unsigned)intmask);
10648 -               sdhci_dumpregs(host);
10649 +               if (!(host->ops->extra_ints)) {
10650 +                       pr_err("%s: Got command interrupt 0x%08x even "
10651 +                               "though no command operation was in progress.\n",
10652 +                               mmc_hostname(host->mmc), (unsigned)intmask);
10653 +                       sdhci_dumpregs(host);
10654 +               } else
10655 +                       DBG("cmd irq 0x%08x cmd complete\n", (unsigned)intmask);
10656                 return;
10657         }
10658
10659 @@ -2164,6 +2219,19 @@ static void sdhci_show_adma_error(struct
10660  static void sdhci_show_adma_error(struct sdhci_host *host) { }
10661  #endif
10662
10663 +static void sdhci_data_end(struct sdhci_host *host)
10664 +{
10665 +       if (host->cmd) {
10666 +               /*
10667 +                * Data managed to finish before the
10668 +                * command completed. Make sure we do
10669 +                * things in the proper order.
10670 +                */
10671 +               host->data_early = 1;
10672 +       } else
10673 +               sdhci_finish_data(host);
10674 +}
10675 +
10676  static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
10677  {
10678         u32 command;
10679 @@ -2192,35 +2260,57 @@ static void sdhci_data_irq(struct sdhci_
10680                                 return;
10681                         }
10682                 }
10683 -
10684 -               pr_err("%s: Got data interrupt 0x%08x even "
10685 -                       "though no data operation was in progress.\n",
10686 -                       mmc_hostname(host->mmc), (unsigned)intmask);
10687 -               sdhci_dumpregs(host);
10688 -
10689 -               return;
10690 -       }
10691 -
10692 -       if (intmask & SDHCI_INT_DATA_TIMEOUT)
10693 -               host->data->error = -ETIMEDOUT;
10694 -       else if (intmask & SDHCI_INT_DATA_END_BIT)
10695 -               host->data->error = -EILSEQ;
10696 -       else if ((intmask & SDHCI_INT_DATA_CRC) &&
10697 -               SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
10698 -                       != MMC_BUS_TEST_R)
10699 -               host->data->error = -EILSEQ;
10700 -       else if (intmask & SDHCI_INT_ADMA_ERROR) {
10701 +
10702 +               if (!(host->ops->extra_ints)) {
10703 +                       pr_err("%s: Got data interrupt 0x%08x even "
10704 +                               "though no data operation was in progress.\n",
10705 +                               mmc_hostname(host->mmc), (unsigned)intmask);
10706 +                       sdhci_dumpregs(host);
10707 +               } else
10708 +                       DBG("data irq 0x%08x but no data\n", (unsigned)intmask);
10709 +
10710 +               return;
10711 +       }
10712 +
10713 +       if (intmask & SDHCI_INT_DATA_TIMEOUT)
10714 +               host->data->error = -ETIMEDOUT;
10715 +       else if (intmask & SDHCI_INT_DATA_END_BIT) {
10716 +               DBG("end error in cmd %d\n", host->last_cmdop);
10717 +               if (host->ops->spurious_crc_acmd51 &&
10718 +                   host->last_cmdop == -SD_APP_SEND_SCR) {
10719 +                       DBG("ignoring spurious data_end_bit error\n");
10720 +                       intmask = SDHCI_INT_DATA_AVAIL|SDHCI_INT_DATA_END;
10721 +               } else
10722 +                       host->data->error = -EILSEQ;
10723 +       } else if ((intmask & SDHCI_INT_DATA_CRC) &&
10724 +               SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
10725 +                       != MMC_BUS_TEST_R) {
10726 +               DBG("crc error in cmd %d\n", host->last_cmdop);
10727 +               if (host->ops->spurious_crc_acmd51 &&
10728 +                   host->last_cmdop == -SD_APP_SEND_SCR) {
10729 +                       DBG("ignoring spurious data_crc_bit error\n");
10730 +                       intmask = SDHCI_INT_DATA_AVAIL|SDHCI_INT_DATA_END;
10731 +               } else
10732 +                       host->data->error = -EILSEQ;
10733 +       } else if (intmask & SDHCI_INT_ADMA_ERROR) {
10734                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
10735 -               sdhci_show_adma_error(host);
10736 -               host->data->error = -EIO;
10737 -       }
10738 -
10739 -       if (host->data->error)
10740 -               sdhci_finish_data(host);
10741 -       else {
10742 -               if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
10743 -                       sdhci_transfer_pio(host);
10744 -
10745 +               sdhci_show_adma_error(host);
10746 +               host->data->error = -EIO;
10747 +       }
10748 +
10749 +       if (host->data->error) {
10750 +               DBG("finish request early on error %d\n", host->data->error);
10751 +               sdhci_finish_data(host);
10752 +       } else {
10753 +               if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
10754 +                       if (host->flags & SDHCI_REQ_USE_DMA) {
10755 +                               /* possible only in PLATDMA mode */
10756 +                               sdhci_platdma_avail(host, &intmask,
10757 +                                               &sdhci_data_end);
10758 +                       } else
10759 +                               sdhci_transfer_pio(host, intmask);
10760 +               }
10761 +
10762                 /*
10763                  * We currently don't do anything fancy with DMA
10764                  * boundaries, but as we can't disable the feature
10765 @@ -2249,16 +2339,7 @@ static void sdhci_data_irq(struct sdhci_
10766                 }
10767
10768                 if (intmask & SDHCI_INT_DATA_END) {
10769 -                       if (host->cmd) {
10770 -                               /*
10771 -                                * Data managed to finish before the
10772 -                                * command completed. Make sure we do
10773 -                                * things in the proper order.
10774 -                                */
10775 -                               host->data_early = 1;
10776 -                       } else {
10777 -                               sdhci_finish_data(host);
10778 -                       }
10779 +                       sdhci_data_end(host);
10780                 }
10781         }
10782  }
10783 @@ -2314,6 +2395,22 @@ static irqreturn_t sdhci_irq(int irq, vo
10784                 tasklet_schedule(&host->card_tasklet);
10785         }
10786
10787 +       if (intmask & SDHCI_INT_ERROR_MASK & ~SDHCI_INT_ERROR)
10788 +               DBG("controller reports error 0x%x -"
10789 +                               "%s%s%s%s%s%s%s%s%s%s",
10790 +                               intmask,
10791 +                               intmask & SDHCI_INT_TIMEOUT? " timeout": "",
10792 +                               intmask & SDHCI_INT_CRC     ? " crc": "",
10793 +                               intmask & SDHCI_INT_END_BIT? " endbit": "",
10794 +                               intmask & SDHCI_INT_INDEX? " index": "",
10795 +                               intmask & SDHCI_INT_DATA_TIMEOUT? " data_timeout": "",
10796 +                               intmask & SDHCI_INT_DATA_CRC? " data_crc": "",
10797 +                               intmask & SDHCI_INT_DATA_END_BIT? " data_endbit": "",
10798 +                               intmask & SDHCI_INT_BUS_POWER? " buspower": "",
10799 +                               intmask & SDHCI_INT_ACMD12ERR? " acmd12": "",
10800 +                               intmask & SDHCI_INT_ADMA_ERROR? " adma": ""
10801 +                  );
10802 +
10803         if (intmask & SDHCI_INT_CMD_MASK) {
10804                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
10805                         SDHCI_INT_STATUS);
10806 @@ -2535,6 +2632,90 @@ EXPORT_SYMBOL_GPL(sdhci_runtime_resume_h
10807
10808  #endif
10809
10810 +#ifdef CONFIG_PM_RUNTIME
10811 +
10812 +static int sdhci_runtime_pm_get(struct sdhci_host *host)
10813 +{
10814 +       return pm_runtime_get_sync(host->mmc->parent);
10815 +}
10816 +
10817 +static int sdhci_runtime_pm_put(struct sdhci_host *host)
10818 +{
10819 +       pm_runtime_mark_last_busy(host->mmc->parent);
10820 +       return pm_runtime_put_autosuspend(host->mmc->parent);
10821 +}
10822 +
10823 +int sdhci_runtime_suspend_host(struct sdhci_host *host)
10824 +{
10825 +       unsigned long flags;
10826 +       int ret = 0;
10827 +
10828 +       /* Disable tuning since we are suspending */
10829 +       if (host->version >= SDHCI_SPEC_300 &&
10830 +           host->tuning_mode == SDHCI_TUNING_MODE_1) {
10831 +               del_timer_sync(&host->tuning_timer);
10832 +               host->flags &= ~SDHCI_NEEDS_RETUNING;
10833 +       }
10834 +
10835 +       spin_lock_irqsave(&host->lock, flags);
10836 +       sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
10837 +       spin_unlock_irqrestore(&host->lock, flags);
10838 +
10839 +       synchronize_irq(host->irq);
10840 +
10841 +       spin_lock_irqsave(&host->lock, flags);
10842 +       host->runtime_suspended = true;
10843 +       spin_unlock_irqrestore(&host->lock, flags);
10844 +
10845 +       return ret;
10846 +}
10847 +EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
10848 +
10849 +int sdhci_runtime_resume_host(struct sdhci_host *host)
10850 +{
10851 +       unsigned long flags;
10852 +       int ret = 0, host_flags = host->flags;
10853 +
10854 +       if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
10855 +               if (host->ops->enable_dma)
10856 +                       host->ops->enable_dma(host);
10857 +       }
10858 +
10859 +       sdhci_init(host, 0);
10860 +
10861 +       /* Force clock and power re-program */
10862 +       host->pwr = 0;
10863 +       host->clock = 0;
10864 +       sdhci_do_set_ios(host, &host->mmc->ios);
10865 +
10866 +       sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
10867 +       if (host_flags & SDHCI_PV_ENABLED)
10868 +               sdhci_do_enable_preset_value(host, true);
10869 +
10870 +       /* Set the re-tuning expiration flag */
10871 +       if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
10872 +           (host->tuning_mode == SDHCI_TUNING_MODE_1))
10873 +               host->flags |= SDHCI_NEEDS_RETUNING;
10874 +
10875 +       spin_lock_irqsave(&host->lock, flags);
10876 +
10877 +       host->runtime_suspended = false;
10878 +
10879 +       /* Enable SDIO IRQ */
10880 +       if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
10881 +               sdhci_enable_sdio_irq_nolock(host, true);
10882 +
10883 +       /* Enable Card Detection */
10884 +       sdhci_enable_card_detection(host);
10885 +
10886 +       spin_unlock_irqrestore(&host->lock, flags);
10887 +
10888 +       return ret;
10889 +}
10890 +EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
10891 +
10892 +#endif
10893 +
10894  /*****************************************************************************\
10895   *                                                                           *
10896   * Device allocation/registration                                            *
10897 @@ -2738,7 +2919,7 @@ int sdhci_add_host(struct sdhci_host *ho
10898         /* Auto-CMD23 stuff only works in ADMA or PIO. */
10899         if ((host->version >= SDHCI_SPEC_300) &&
10900             ((host->flags & SDHCI_USE_ADMA) ||
10901 -            !(host->flags & SDHCI_USE_SDMA))) {
10902 +            !(host->flags & SDHCI_USE_SDMA) )) {
10903                 host->flags |= SDHCI_AUTO_CMD23;
10904                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
10905         } else {
10906 @@ -2800,6 +2981,15 @@ int sdhci_add_host(struct sdhci_host *ho
10907         else
10908                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
10909
10910 +       /*
10911 +        * If Power Off Notify capability is enabled by the host,
10912 +        * set notify to short power off notify timeout value.
10913 +        */
10914 +       if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
10915 +               mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
10916 +       else
10917 +               mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
10918 +
10919         /* Initial value for re-tuning timer count */
10920         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
10921                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
10922 @@ -2875,6 +3065,9 @@ int sdhci_add_host(struct sdhci_host *ho
10923                         mmc->caps |= MMC_CAP_MAX_CURRENT_200;
10924         }
10925
10926 +       if(host->ops->voltage_broken)
10927 +               ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
10928 +
10929         mmc->ocr_avail = ocr_avail;
10930         mmc->ocr_avail_sdio = ocr_avail;
10931         if (host->ocr_avail_sdio)
10932 --- a/drivers/mmc/host/sdhci.h
10933 +++ b/drivers/mmc/host/sdhci.h
10934 @@ -274,6 +274,24 @@ struct sdhci_ops {
10935         void    (*platform_reset_enter)(struct sdhci_host *host, u8 mask);
10936         void    (*platform_reset_exit)(struct sdhci_host *host, u8 mask);
10937         int     (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
10938 +
10939 +       int             (*enable)(struct sdhci_host *mmc);
10940 +       int             (*disable)(struct sdhci_host *mmc, int lazy);
10941 +       int             (*set_plat_power)(struct sdhci_host *mmc,
10942 +                                         int power_mode);
10943 +
10944 +       int             (*pdma_able)(struct sdhci_host *host,
10945 +                                    struct mmc_data *data);
10946 +       void            (*pdma_avail)(struct sdhci_host *host,
10947 +                                     unsigned int *ref_intmask,
10948 +                                     void(*complete)(struct sdhci_host *));
10949 +       void            (*pdma_reset)(struct sdhci_host *host,
10950 +                                     struct mmc_data *data);
10951 +       unsigned int    (*extra_ints)(struct sdhci_host *host);
10952 +       unsigned int    (*spurious_crc_acmd51)(struct sdhci_host *host);
10953 +       unsigned int    (*voltage_broken)(struct sdhci_host *host);
10954 +       unsigned int    (*uhs_broken)(struct sdhci_host *host);
10955 +
10956         void    (*hw_reset)(struct sdhci_host *host);
10957  };
10958
10959 @@ -383,6 +401,34 @@ extern void sdhci_enable_irq_wakeups(str
10960  #ifdef CONFIG_PM_RUNTIME
10961  extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
10962  extern int sdhci_runtime_resume_host(struct sdhci_host *host);
10963 +#endif
10964 +
10965 +static inline int /*bool*/
10966 +sdhci_platdma_dmaable(struct sdhci_host *host, struct mmc_data *data)
10967 +{
10968 +       if (host->ops->pdma_able)
10969 +               return host->ops->pdma_able(host, data);
10970 +       else
10971 +               return 1;
10972 +}
10973 +static inline void
10974 +sdhci_platdma_avail(struct sdhci_host *host, unsigned int *ref_intmask,
10975 +               void(*completion_callback)(struct sdhci_host *))
10976 +{
10977 +       if (host->ops->pdma_avail)
10978 +               host->ops->pdma_avail(host, ref_intmask, completion_callback);
10979 +}
10980 +
10981 +static inline void
10982 +sdhci_platdma_reset(struct sdhci_host *host, struct mmc_data *data)
10983 +{
10984 +       if (host->ops->pdma_reset)
10985 +               host->ops->pdma_reset(host, data);
10986 +}
10987 +
10988 +#ifdef CONFIG_PM_RUNTIME
10989 +extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
10990 +extern int sdhci_runtime_resume_host(struct sdhci_host *host);
10991  #endif
10992
10993  #endif /* __SDHCI_HW_H */
10994 --- a/include/linux/mmc/sdhci.h
10995 +++ b/include/linux/mmc/sdhci.h
10996 @@ -90,6 +90,8 @@ struct sdhci_host {
10997
10998         unsigned int quirks2;   /* More deviations from spec. */
10999
11000 +#define SDHCI_QUIRK2_OWN_CARD_DETECTION                        (1<<0)
11001 +
11002         int irq;                /* Device IRQ */
11003         void __iomem *ioaddr;   /* Mapped address */
11004
11005 @@ -120,6 +122,7 @@ struct sdhci_host {
11006  #define SDHCI_PV_ENABLED       (1<<8)  /* Preset value enabled */
11007  #define SDHCI_SDIO_IRQ_ENABLED (1<<9)  /* SDIO irq enabled */
11008  #define SDHCI_HS200_NEEDS_TUNING (1<<10)       /* HS200 needs tuning */
11009 +#define SDHCI_USE_PLATDMA      (1<<11) /* Host uses 3rd party DMA */
11010
11011         unsigned int version;   /* SDHCI spec. version */
11012
11013 @@ -131,9 +134,9 @@ struct sdhci_host {
11014         u8 pwr;                 /* Current voltage */
11015
11016         bool runtime_suspended; /* Host is runtime suspended */
11017 -
11018         struct mmc_request *mrq;        /* Current request */
11019         struct mmc_command *cmd;        /* Current command */
11020 +       int     last_cmdop;     /* Opcode of last cmd sent */
11021         struct mmc_data *data;  /* Current data request */
11022         unsigned int data_early:1;      /* Data finished before cmd */
11023