target/linux/brcm2708/patches-3.10/002-Main-bcm2708-linux-port.patch

   1 diff -urN linux-3.10/arch/arm/configs/bcmrpi_cutdown_defconfig linux-rpi-3.10.y/arch/arm/configs/bcmrpi_cutdown_defconfig
   2 --- linux-3.10/arch/arm/configs/bcmrpi_cutdown_defconfig        1970-01-01 01:00:00.000000000 +0100
   3 +++ linux-rpi-3.10.y/arch/arm/configs/bcmrpi_cutdown_defconfig  2013-07-06 15:25:50.000000000 +0100
   4 @@ -0,0 +1,504 @@
   5 +CONFIG_EXPERIMENTAL=y
   6 +# CONFIG_LOCALVERSION_AUTO is not set
   7 +CONFIG_SYSVIPC=y
   8 +CONFIG_POSIX_MQUEUE=y
   9 +CONFIG_IKCONFIG=y
  10 +CONFIG_IKCONFIG_PROC=y
  11 +# CONFIG_UID16 is not set
  12 +# CONFIG_KALLSYMS is not set
  13 +CONFIG_EMBEDDED=y
  14 +# CONFIG_VM_EVENT_COUNTERS is not set
  15 +# CONFIG_COMPAT_BRK is not set
  16 +CONFIG_SLAB=y
  17 +CONFIG_MODULES=y
  18 +CONFIG_MODULE_UNLOAD=y
  19 +CONFIG_MODVERSIONS=y
  20 +CONFIG_MODULE_SRCVERSION_ALL=y
  21 +# CONFIG_BLK_DEV_BSG is not set
  22 +CONFIG_ARCH_BCM2708=y
  23 +CONFIG_NO_HZ=y
  24 +CONFIG_HIGH_RES_TIMERS=y
  25 +CONFIG_AEABI=y
  26 +CONFIG_ZBOOT_ROM_TEXT=0x0
  27 +CONFIG_ZBOOT_ROM_BSS=0x0
  28 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
  29 +CONFIG_CPU_IDLE=y
  30 +CONFIG_VFP=y
  31 +CONFIG_BINFMT_MISC=m
  32 +CONFIG_NET=y
  33 +CONFIG_PACKET=y
  34 +CONFIG_UNIX=y
  35 +CONFIG_XFRM_USER=y
  36 +CONFIG_NET_KEY=m
  37 +CONFIG_INET=y
  38 +CONFIG_IP_MULTICAST=y
  39 +CONFIG_IP_PNP=y
  40 +CONFIG_IP_PNP_DHCP=y
  41 +CONFIG_IP_PNP_RARP=y
  42 +CONFIG_SYN_COOKIES=y
  43 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
  44 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
  45 +# CONFIG_INET_XFRM_MODE_BEET is not set
  46 +# CONFIG_INET_LRO is not set
  47 +# CONFIG_INET_DIAG is not set
  48 +# CONFIG_IPV6 is not set
  49 +CONFIG_NET_PKTGEN=m
  50 +CONFIG_IRDA=m
  51 +CONFIG_IRLAN=m
  52 +CONFIG_IRCOMM=m
  53 +CONFIG_IRDA_ULTRA=y
  54 +CONFIG_IRDA_CACHE_LAST_LSAP=y
  55 +CONFIG_IRDA_FAST_RR=y
  56 +CONFIG_IRTTY_SIR=m
  57 +CONFIG_KINGSUN_DONGLE=m
  58 +CONFIG_KSDAZZLE_DONGLE=m
  59 +CONFIG_KS959_DONGLE=m
  60 +CONFIG_USB_IRDA=m
  61 +CONFIG_SIGMATEL_FIR=m
  62 +CONFIG_MCS_FIR=m
  63 +CONFIG_BT=m
  64 +CONFIG_BT_L2CAP=y
  65 +CONFIG_BT_SCO=y
  66 +CONFIG_BT_RFCOMM=m
  67 +CONFIG_BT_RFCOMM_TTY=y
  68 +CONFIG_BT_BNEP=m
  69 +CONFIG_BT_BNEP_MC_FILTER=y
  70 +CONFIG_BT_BNEP_PROTO_FILTER=y
  71 +CONFIG_BT_HIDP=m
  72 +CONFIG_BT_HCIBTUSB=m
  73 +CONFIG_BT_HCIBCM203X=m
  74 +CONFIG_BT_HCIBPA10X=m
  75 +CONFIG_BT_HCIBFUSB=m
  76 +CONFIG_BT_HCIVHCI=m
  77 +CONFIG_BT_MRVL=m
  78 +CONFIG_BT_MRVL_SDIO=m
  79 +CONFIG_BT_ATH3K=m
  80 +CONFIG_CFG80211=m
  81 +CONFIG_MAC80211=m
  82 +CONFIG_MAC80211_RC_PID=y
  83 +CONFIG_MAC80211_MESH=y
  84 +CONFIG_WIMAX=m
  85 +CONFIG_NET_9P=m
  86 +CONFIG_NFC=m
  87 +CONFIG_NFC_PN533=m
  88 +CONFIG_DEVTMPFS=y
  89 +CONFIG_BLK_DEV_LOOP=y
  90 +CONFIG_BLK_DEV_CRYPTOLOOP=m
  91 +CONFIG_BLK_DEV_NBD=m
  92 +CONFIG_BLK_DEV_RAM=y
  93 +CONFIG_CDROM_PKTCDVD=m
  94 +CONFIG_MISC_DEVICES=y
  95 +CONFIG_SCSI=y
  96 +# CONFIG_SCSI_PROC_FS is not set
  97 +CONFIG_BLK_DEV_SD=m
  98 +CONFIG_BLK_DEV_SR=m
  99 +CONFIG_SCSI_MULTI_LUN=y
 100 +# CONFIG_SCSI_LOWLEVEL is not set
 101 +CONFIG_NETDEVICES=y
 102 +CONFIG_TUN=m
 103 +CONFIG_PHYLIB=m
 104 +CONFIG_MDIO_BITBANG=m
 105 +CONFIG_NET_ETHERNET=y
 106 +# CONFIG_NETDEV_1000 is not set
 107 +# CONFIG_NETDEV_10000 is not set
 108 +CONFIG_LIBERTAS_THINFIRM=m
 109 +CONFIG_LIBERTAS_THINFIRM_USB=m
 110 +CONFIG_AT76C50X_USB=m
 111 +CONFIG_USB_ZD1201=m
 112 +CONFIG_USB_NET_RNDIS_WLAN=m
 113 +CONFIG_RTL8187=m
 114 +CONFIG_MAC80211_HWSIM=m
 115 +CONFIG_ATH_COMMON=m
 116 +CONFIG_ATH9K=m
 117 +CONFIG_ATH9K_HTC=m
 118 +CONFIG_CARL9170=m
 119 +CONFIG_B43=m
 120 +CONFIG_B43LEGACY=m
 121 +CONFIG_HOSTAP=m
 122 +CONFIG_IWM=m
 123 +CONFIG_LIBERTAS=m
 124 +CONFIG_LIBERTAS_USB=m
 125 +CONFIG_LIBERTAS_SDIO=m
 126 +CONFIG_P54_COMMON=m
 127 +CONFIG_P54_USB=m
 128 +CONFIG_RT2X00=m
 129 +CONFIG_RT2500USB=m
 130 +CONFIG_RT73USB=m
 131 +CONFIG_RT2800USB=m
 132 +CONFIG_RT2800USB_RT53XX=y
 133 +CONFIG_RTL8192CU=m
 134 +CONFIG_WL1251=m
 135 +CONFIG_WL12XX_MENU=m
 136 +CONFIG_ZD1211RW=m
 137 +CONFIG_MWIFIEX=m
 138 +CONFIG_MWIFIEX_SDIO=m
 139 +CONFIG_WIMAX_I2400M_USB=m
 140 +CONFIG_USB_CATC=m
 141 +CONFIG_USB_KAWETH=m
 142 +CONFIG_USB_PEGASUS=m
 143 +CONFIG_USB_RTL8150=m
 144 +CONFIG_USB_USBNET=y
 145 +CONFIG_USB_NET_AX8817X=m
 146 +CONFIG_USB_NET_CDCETHER=m
 147 +CONFIG_USB_NET_CDC_EEM=m
 148 +CONFIG_USB_NET_DM9601=m
 149 +CONFIG_USB_NET_SMSC75XX=m
 150 +CONFIG_USB_NET_SMSC95XX=y
 151 +CONFIG_USB_NET_GL620A=m
 152 +CONFIG_USB_NET_NET1080=m
 153 +CONFIG_USB_NET_PLUSB=m
 154 +CONFIG_USB_NET_MCS7830=m
 155 +CONFIG_USB_NET_CDC_SUBSET=m
 156 +CONFIG_USB_ALI_M5632=y
 157 +CONFIG_USB_AN2720=y
 158 +CONFIG_USB_KC2190=y
 159 +# CONFIG_USB_NET_ZAURUS is not set
 160 +CONFIG_USB_NET_CX82310_ETH=m
 161 +CONFIG_USB_NET_KALMIA=m
 162 +CONFIG_USB_NET_INT51X1=m
 163 +CONFIG_USB_IPHETH=m
 164 +CONFIG_USB_SIERRA_NET=m
 165 +CONFIG_USB_VL600=m
 166 +CONFIG_PPP=m
 167 +CONFIG_PPP_ASYNC=m
 168 +CONFIG_PPP_SYNC_TTY=m
 169 +CONFIG_PPP_DEFLATE=m
 170 +CONFIG_PPP_BSDCOMP=m
 171 +CONFIG_SLIP=m
 172 +CONFIG_SLIP_COMPRESSED=y
 173 +CONFIG_NETCONSOLE=m
 174 +CONFIG_INPUT_POLLDEV=m
 175 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 176 +CONFIG_INPUT_JOYDEV=m
 177 +CONFIG_INPUT_EVDEV=m
 178 +# CONFIG_INPUT_KEYBOARD is not set
 179 +# CONFIG_INPUT_MOUSE is not set
 180 +CONFIG_INPUT_MISC=y
 181 +CONFIG_INPUT_AD714X=m
 182 +CONFIG_INPUT_ATI_REMOTE=m
 183 +CONFIG_INPUT_ATI_REMOTE2=m
 184 +CONFIG_INPUT_KEYSPAN_REMOTE=m
 185 +CONFIG_INPUT_POWERMATE=m
 186 +CONFIG_INPUT_YEALINK=m
 187 +CONFIG_INPUT_CM109=m
 188 +CONFIG_INPUT_UINPUT=m
 189 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
 190 +CONFIG_INPUT_ADXL34X=m
 191 +CONFIG_INPUT_CMA3000=m
 192 +CONFIG_SERIO=m
 193 +CONFIG_SERIO_RAW=m
 194 +CONFIG_GAMEPORT=m
 195 +CONFIG_GAMEPORT_NS558=m
 196 +CONFIG_GAMEPORT_L4=m
 197 +CONFIG_VT_HW_CONSOLE_BINDING=y
 198 +# CONFIG_LEGACY_PTYS is not set
 199 +# CONFIG_DEVKMEM is not set
 200 +CONFIG_SERIAL_AMBA_PL011=y
 201 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 202 +# CONFIG_HW_RANDOM is not set
 203 +CONFIG_RAW_DRIVER=y
 204 +CONFIG_GPIO_SYSFS=y
 205 +# CONFIG_HWMON is not set
 206 +CONFIG_WATCHDOG=y
 207 +CONFIG_BCM2708_WDT=m
 208 +# CONFIG_MFD_SUPPORT is not set
 209 +CONFIG_FB=y
 210 +CONFIG_FB_BCM2708=y
 211 +CONFIG_FRAMEBUFFER_CONSOLE=y
 212 +CONFIG_LOGO=y
 213 +# CONFIG_LOGO_LINUX_MONO is not set
 214 +# CONFIG_LOGO_LINUX_VGA16 is not set
 215 +CONFIG_SOUND=y
 216 +CONFIG_SND=m
 217 +CONFIG_SND_SEQUENCER=m
 218 +CONFIG_SND_SEQ_DUMMY=m
 219 +CONFIG_SND_MIXER_OSS=m
 220 +CONFIG_SND_PCM_OSS=m
 221 +CONFIG_SND_SEQUENCER_OSS=y
 222 +CONFIG_SND_HRTIMER=m
 223 +CONFIG_SND_DUMMY=m
 224 +CONFIG_SND_ALOOP=m
 225 +CONFIG_SND_VIRMIDI=m
 226 +CONFIG_SND_MTPAV=m
 227 +CONFIG_SND_SERIAL_U16550=m
 228 +CONFIG_SND_MPU401=m
 229 +CONFIG_SND_BCM2835=m
 230 +CONFIG_SND_USB_AUDIO=m
 231 +CONFIG_SND_USB_UA101=m
 232 +CONFIG_SND_USB_CAIAQ=m
 233 +CONFIG_SND_USB_6FIRE=m
 234 +CONFIG_SOUND_PRIME=m
 235 +CONFIG_HID_PID=y
 236 +CONFIG_USB_HIDDEV=y
 237 +CONFIG_HID_A4TECH=m
 238 +CONFIG_HID_ACRUX=m
 239 +CONFIG_HID_APPLE=m
 240 +CONFIG_HID_BELKIN=m
 241 +CONFIG_HID_CHERRY=m
 242 +CONFIG_HID_CHICONY=m
 243 +CONFIG_HID_CYPRESS=m
 244 +CONFIG_HID_DRAGONRISE=m
 245 +CONFIG_HID_EMS_FF=m
 246 +CONFIG_HID_ELECOM=m
 247 +CONFIG_HID_EZKEY=m
 248 +CONFIG_HID_HOLTEK=m
 249 +CONFIG_HID_KEYTOUCH=m
 250 +CONFIG_HID_KYE=m
 251 +CONFIG_HID_UCLOGIC=m
 252 +CONFIG_HID_WALTOP=m
 253 +CONFIG_HID_GYRATION=m
 254 +CONFIG_HID_TWINHAN=m
 255 +CONFIG_HID_KENSINGTON=m
 256 +CONFIG_HID_LCPOWER=m
 257 +CONFIG_HID_LOGITECH=m
 258 +CONFIG_HID_MAGICMOUSE=m
 259 +CONFIG_HID_MICROSOFT=m
 260 +CONFIG_HID_MONTEREY=m
 261 +CONFIG_HID_MULTITOUCH=m
 262 +CONFIG_HID_NTRIG=m
 263 +CONFIG_HID_ORTEK=m
 264 +CONFIG_HID_PANTHERLORD=m
 265 +CONFIG_HID_PETALYNX=m
 266 +CONFIG_HID_PICOLCD=m
 267 +CONFIG_HID_QUANTA=m
 268 +CONFIG_HID_ROCCAT=m
 269 +CONFIG_HID_SAMSUNG=m
 270 +CONFIG_HID_SONY=m
 271 +CONFIG_HID_SPEEDLINK=m
 272 +CONFIG_HID_SUNPLUS=m
 273 +CONFIG_HID_GREENASIA=m
 274 +CONFIG_HID_SMARTJOYPLUS=m
 275 +CONFIG_HID_TOPSEED=m
 276 +CONFIG_HID_THRUSTMASTER=m
 277 +CONFIG_HID_WACOM=m
 278 +CONFIG_HID_WIIMOTE=m
 279 +CONFIG_HID_ZEROPLUS=m
 280 +CONFIG_HID_ZYDACRON=m
 281 +CONFIG_USB=y
 282 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 283 +CONFIG_USB_MON=m
 284 +CONFIG_USB_DWCOTG=y
 285 +CONFIG_USB_STORAGE=y
 286 +CONFIG_USB_STORAGE_REALTEK=m
 287 +CONFIG_USB_STORAGE_DATAFAB=m
 288 +CONFIG_USB_STORAGE_FREECOM=m
 289 +CONFIG_USB_STORAGE_ISD200=m
 290 +CONFIG_USB_STORAGE_USBAT=m
 291 +CONFIG_USB_STORAGE_SDDR09=m
 292 +CONFIG_USB_STORAGE_SDDR55=m
 293 +CONFIG_USB_STORAGE_JUMPSHOT=m
 294 +CONFIG_USB_STORAGE_ALAUDA=m
 295 +CONFIG_USB_STORAGE_ONETOUCH=m
 296 +CONFIG_USB_STORAGE_KARMA=m
 297 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
 298 +CONFIG_USB_STORAGE_ENE_UB6250=m
 299 +CONFIG_USB_UAS=m
 300 +CONFIG_USB_LIBUSUAL=y
 301 +CONFIG_USB_MDC800=m
 302 +CONFIG_USB_MICROTEK=m
 303 +CONFIG_USB_SERIAL=m
 304 +CONFIG_USB_SERIAL_GENERIC=y
 305 +CONFIG_USB_SERIAL_AIRCABLE=m
 306 +CONFIG_USB_SERIAL_ARK3116=m
 307 +CONFIG_USB_SERIAL_BELKIN=m
 308 +CONFIG_USB_SERIAL_CH341=m
 309 +CONFIG_USB_SERIAL_WHITEHEAT=m
 310 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
 311 +CONFIG_USB_SERIAL_CP210X=m
 312 +CONFIG_USB_SERIAL_CYPRESS_M8=m
 313 +CONFIG_USB_SERIAL_EMPEG=m
 314 +CONFIG_USB_SERIAL_FTDI_SIO=m
 315 +CONFIG_USB_SERIAL_FUNSOFT=m
 316 +CONFIG_USB_SERIAL_VISOR=m
 317 +CONFIG_USB_SERIAL_IPAQ=m
 318 +CONFIG_USB_SERIAL_IR=m
 319 +CONFIG_USB_SERIAL_EDGEPORT=m
 320 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
 321 +CONFIG_USB_SERIAL_GARMIN=m
 322 +CONFIG_USB_SERIAL_IPW=m
 323 +CONFIG_USB_SERIAL_IUU=m
 324 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
 325 +CONFIG_USB_SERIAL_KEYSPAN=m
 326 +CONFIG_USB_SERIAL_KLSI=m
 327 +CONFIG_USB_SERIAL_KOBIL_SCT=m
 328 +CONFIG_USB_SERIAL_MCT_U232=m
 329 +CONFIG_USB_SERIAL_MOS7720=m
 330 +CONFIG_USB_SERIAL_MOS7840=m
 331 +CONFIG_USB_SERIAL_MOTOROLA=m
 332 +CONFIG_USB_SERIAL_NAVMAN=m
 333 +CONFIG_USB_SERIAL_PL2303=m
 334 +CONFIG_USB_SERIAL_OTI6858=m
 335 +CONFIG_USB_SERIAL_QCAUX=m
 336 +CONFIG_USB_SERIAL_QUALCOMM=m
 337 +CONFIG_USB_SERIAL_SPCP8X5=m
 338 +CONFIG_USB_SERIAL_HP4X=m
 339 +CONFIG_USB_SERIAL_SAFE=m
 340 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
 341 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
 342 +CONFIG_USB_SERIAL_SYMBOL=m
 343 +CONFIG_USB_SERIAL_TI=m
 344 +CONFIG_USB_SERIAL_CYBERJACK=m
 345 +CONFIG_USB_SERIAL_XIRCOM=m
 346 +CONFIG_USB_SERIAL_OPTION=m
 347 +CONFIG_USB_SERIAL_OMNINET=m
 348 +CONFIG_USB_SERIAL_OPTICON=m
 349 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
 350 +CONFIG_USB_SERIAL_ZIO=m
 351 +CONFIG_USB_SERIAL_SSU100=m
 352 +CONFIG_USB_SERIAL_DEBUG=m
 353 +CONFIG_USB_EMI62=m
 354 +CONFIG_USB_EMI26=m
 355 +CONFIG_USB_ADUTUX=m
 356 +CONFIG_USB_SEVSEG=m
 357 +CONFIG_USB_RIO500=m
 358 +CONFIG_USB_LEGOTOWER=m
 359 +CONFIG_USB_LCD=m
 360 +CONFIG_USB_LED=m
 361 +CONFIG_USB_CYPRESS_CY7C63=m
 362 +CONFIG_USB_CYTHERM=m
 363 +CONFIG_USB_IDMOUSE=m
 364 +CONFIG_USB_FTDI_ELAN=m
 365 +CONFIG_USB_APPLEDISPLAY=m
 366 +CONFIG_USB_LD=m
 367 +CONFIG_USB_TRANCEVIBRATOR=m
 368 +CONFIG_USB_IOWARRIOR=m
 369 +CONFIG_USB_TEST=m
 370 +CONFIG_USB_ISIGHTFW=m
 371 +CONFIG_USB_YUREX=m
 372 +CONFIG_MMC=y
 373 +CONFIG_MMC_SDHCI=y
 374 +CONFIG_MMC_SDHCI_PLTFM=y
 375 +CONFIG_MMC_SDHCI_BCM2708=y
 376 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
 377 +CONFIG_LEDS_GPIO=y
 378 +CONFIG_LEDS_TRIGGER_TIMER=m
 379 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
 380 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
 381 +CONFIG_UIO=m
 382 +CONFIG_UIO_PDRV=m
 383 +CONFIG_UIO_PDRV_GENIRQ=m
 384 +# CONFIG_IOMMU_SUPPORT is not set
 385 +CONFIG_EXT4_FS=y
 386 +CONFIG_EXT4_FS_POSIX_ACL=y
 387 +CONFIG_EXT4_FS_SECURITY=y
 388 +CONFIG_REISERFS_FS=m
 389 +CONFIG_REISERFS_FS_XATTR=y
 390 +CONFIG_REISERFS_FS_POSIX_ACL=y
 391 +CONFIG_REISERFS_FS_SECURITY=y
 392 +CONFIG_JFS_FS=m
 393 +CONFIG_JFS_POSIX_ACL=y
 394 +CONFIG_JFS_SECURITY=y
 395 +CONFIG_XFS_FS=m
 396 +CONFIG_XFS_QUOTA=y
 397 +CONFIG_XFS_POSIX_ACL=y
 398 +CONFIG_XFS_RT=y
 399 +CONFIG_GFS2_FS=m
 400 +CONFIG_OCFS2_FS=m
 401 +CONFIG_BTRFS_FS=m
 402 +CONFIG_BTRFS_FS_POSIX_ACL=y
 403 +CONFIG_NILFS2_FS=m
 404 +CONFIG_AUTOFS4_FS=y
 405 +CONFIG_FUSE_FS=m
 406 +CONFIG_CUSE=m
 407 +CONFIG_FSCACHE=y
 408 +CONFIG_CACHEFILES=y
 409 +CONFIG_ISO9660_FS=m
 410 +CONFIG_JOLIET=y
 411 +CONFIG_ZISOFS=y
 412 +CONFIG_UDF_FS=m
 413 +CONFIG_MSDOS_FS=y
 414 +CONFIG_VFAT_FS=y
 415 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 416 +CONFIG_NTFS_FS=m
 417 +CONFIG_TMPFS=y
 418 +CONFIG_TMPFS_POSIX_ACL=y
 419 +CONFIG_CONFIGFS_FS=y
 420 +CONFIG_SQUASHFS=m
 421 +CONFIG_SQUASHFS_XATTR=y
 422 +CONFIG_SQUASHFS_LZO=y
 423 +CONFIG_SQUASHFS_XZ=y
 424 +CONFIG_NFS_FS=y
 425 +CONFIG_NFS_V3=y
 426 +CONFIG_NFS_V3_ACL=y
 427 +CONFIG_NFS_V4=y
 428 +CONFIG_ROOT_NFS=y
 429 +CONFIG_NFS_FSCACHE=y
 430 +CONFIG_CIFS=m
 431 +CONFIG_CIFS_WEAK_PW_HASH=y
 432 +CONFIG_CIFS_XATTR=y
 433 +CONFIG_CIFS_POSIX=y
 434 +CONFIG_9P_FS=m
 435 +CONFIG_PARTITION_ADVANCED=y
 436 +CONFIG_MAC_PARTITION=y
 437 +CONFIG_EFI_PARTITION=y
 438 +CONFIG_NLS_DEFAULT="utf8"
 439 +CONFIG_NLS_CODEPAGE_437=y
 440 +CONFIG_NLS_CODEPAGE_737=m
 441 +CONFIG_NLS_CODEPAGE_775=m
 442 +CONFIG_NLS_CODEPAGE_850=m
 443 +CONFIG_NLS_CODEPAGE_852=m
 444 +CONFIG_NLS_CODEPAGE_855=m
 445 +CONFIG_NLS_CODEPAGE_857=m
 446 +CONFIG_NLS_CODEPAGE_860=m
 447 +CONFIG_NLS_CODEPAGE_861=m
 448 +CONFIG_NLS_CODEPAGE_862=m
 449 +CONFIG_NLS_CODEPAGE_863=m
 450 +CONFIG_NLS_CODEPAGE_864=m
 451 +CONFIG_NLS_CODEPAGE_865=m
 452 +CONFIG_NLS_CODEPAGE_866=m
 453 +CONFIG_NLS_CODEPAGE_869=m
 454 +CONFIG_NLS_CODEPAGE_936=m
 455 +CONFIG_NLS_CODEPAGE_950=m
 456 +CONFIG_NLS_CODEPAGE_932=m
 457 +CONFIG_NLS_CODEPAGE_949=m
 458 +CONFIG_NLS_CODEPAGE_874=m
 459 +CONFIG_NLS_ISO8859_8=m
 460 +CONFIG_NLS_CODEPAGE_1250=m
 461 +CONFIG_NLS_CODEPAGE_1251=m
 462 +CONFIG_NLS_ASCII=y
 463 +CONFIG_NLS_ISO8859_1=m
 464 +CONFIG_NLS_ISO8859_2=m
 465 +CONFIG_NLS_ISO8859_3=m
 466 +CONFIG_NLS_ISO8859_4=m
 467 +CONFIG_NLS_ISO8859_5=m
 468 +CONFIG_NLS_ISO8859_6=m
 469 +CONFIG_NLS_ISO8859_7=m
 470 +CONFIG_NLS_ISO8859_9=m
 471 +CONFIG_NLS_ISO8859_13=m
 472 +CONFIG_NLS_ISO8859_14=m
 473 +CONFIG_NLS_ISO8859_15=m
 474 +CONFIG_NLS_KOI8_R=m
 475 +CONFIG_NLS_KOI8_U=m
 476 +CONFIG_NLS_UTF8=m
 477 +# CONFIG_SCHED_DEBUG is not set
 478 +# CONFIG_DEBUG_BUGVERBOSE is not set
 479 +# CONFIG_FTRACE is not set
 480 +# CONFIG_ARM_UNWIND is not set
 481 +CONFIG_CRYPTO_AUTHENC=m
 482 +CONFIG_CRYPTO_SEQIV=m
 483 +CONFIG_CRYPTO_CBC=y
 484 +CONFIG_CRYPTO_HMAC=y
 485 +CONFIG_CRYPTO_XCBC=m
 486 +CONFIG_CRYPTO_MD5=y
 487 +CONFIG_CRYPTO_SHA1=y
 488 +CONFIG_CRYPTO_SHA256=m
 489 +CONFIG_CRYPTO_SHA512=m
 490 +CONFIG_CRYPTO_TGR192=m
 491 +CONFIG_CRYPTO_WP512=m
 492 +CONFIG_CRYPTO_CAST5=m
 493 +CONFIG_CRYPTO_DES=y
 494 +CONFIG_CRYPTO_DEFLATE=m
 495 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
 496 +# CONFIG_CRYPTO_HW is not set
 497 +CONFIG_CRC_ITU_T=y
 498 +CONFIG_LIBCRC32C=y
 499 +CONFIG_I2C=y
 500 +CONFIG_I2C_BOARDINFO=y
 501 +CONFIG_I2C_COMPAT=y
 502 +CONFIG_I2C_CHARDEV=m
 503 +CONFIG_I2C_HELPER_AUTO=y
 504 +CONFIG_I2C_BCM2708=m
 505 +CONFIG_SPI=y
 506 +CONFIG_SPI_MASTER=y
 507 +CONFIG_SPI_BCM2708=m
 508 +
 509 diff -urN linux-3.10/arch/arm/configs/bcmrpi_defconfig linux-rpi-3.10.y/arch/arm/configs/bcmrpi_defconfig
 510 --- linux-3.10/arch/arm/configs/bcmrpi_defconfig        1970-01-01 01:00:00.000000000 +0100
 511 +++ linux-rpi-3.10.y/arch/arm/configs/bcmrpi_defconfig  2013-07-06 15:25:50.000000000 +0100
 512 @@ -0,0 +1,743 @@
 513 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set
 514 +# CONFIG_LOCALVERSION_AUTO is not set
 515 +CONFIG_SYSVIPC=y
 516 +CONFIG_POSIX_MQUEUE=y
 517 +CONFIG_FHANDLE=y
 518 +CONFIG_AUDIT=y
 519 +CONFIG_NO_HZ=y
 520 +CONFIG_HIGH_RES_TIMERS=y
 521 +CONFIG_BSD_PROCESS_ACCT=y
 522 +CONFIG_BSD_PROCESS_ACCT_V3=y
 523 +CONFIG_IKCONFIG=y
 524 +CONFIG_IKCONFIG_PROC=y
 525 +CONFIG_CGROUP_FREEZER=y
 526 +CONFIG_CGROUP_DEVICE=y
 527 +CONFIG_CGROUP_CPUACCT=y
 528 +CONFIG_RESOURCE_COUNTERS=y
 529 +CONFIG_BLK_CGROUP=y
 530 +CONFIG_NAMESPACES=y
 531 +CONFIG_SCHED_AUTOGROUP=y
 532 +CONFIG_EMBEDDED=y
 533 +# CONFIG_COMPAT_BRK is not set
 534 +CONFIG_SLAB=y
 535 +CONFIG_PROFILING=y
 536 +CONFIG_OPROFILE=m
 537 +CONFIG_KPROBES=y
 538 +CONFIG_MODULES=y
 539 +CONFIG_MODULE_UNLOAD=y
 540 +CONFIG_MODVERSIONS=y
 541 +CONFIG_MODULE_SRCVERSION_ALL=y
 542 +# CONFIG_BLK_DEV_BSG is not set
 543 +CONFIG_BLK_DEV_THROTTLING=y
 544 +CONFIG_PARTITION_ADVANCED=y
 545 +CONFIG_MAC_PARTITION=y
 546 +CONFIG_CFQ_GROUP_IOSCHED=y
 547 +CONFIG_ARCH_BCM2708=y
 548 +CONFIG_AEABI=y
 549 +CONFIG_SECCOMP=y
 550 +CONFIG_CC_STACKPROTECTOR=y
 551 +CONFIG_ZBOOT_ROM_TEXT=0x0
 552 +CONFIG_ZBOOT_ROM_BSS=0x0
 553 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
 554 +CONFIG_KEXEC=y
 555 +CONFIG_CPU_FREQ=y
 556 +CONFIG_CPU_FREQ_STAT=m
 557 +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
 558 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 559 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
 560 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
 561 +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
 562 +CONFIG_CPU_IDLE=y
 563 +CONFIG_VFP=y
 564 +CONFIG_BINFMT_MISC=m
 565 +CONFIG_NET=y
 566 +CONFIG_PACKET=y
 567 +CONFIG_UNIX=y
 568 +CONFIG_XFRM_USER=y
 569 +CONFIG_NET_KEY=m
 570 +CONFIG_INET=y
 571 +CONFIG_IP_MULTICAST=y
 572 +CONFIG_IP_PNP=y
 573 +CONFIG_IP_PNP_DHCP=y
 574 +CONFIG_IP_PNP_RARP=y
 575 +CONFIG_SYN_COOKIES=y
 576 +CONFIG_INET_AH=m
 577 +CONFIG_INET_ESP=m
 578 +CONFIG_INET_IPCOMP=m
 579 +CONFIG_INET_XFRM_MODE_TRANSPORT=m
 580 +CONFIG_INET_XFRM_MODE_TUNNEL=m
 581 +CONFIG_INET_XFRM_MODE_BEET=m
 582 +CONFIG_INET_LRO=m
 583 +CONFIG_INET_DIAG=m
 584 +CONFIG_IPV6_PRIVACY=y
 585 +CONFIG_INET6_AH=m
 586 +CONFIG_INET6_ESP=m
 587 +CONFIG_INET6_IPCOMP=m
 588 +CONFIG_IPV6_MULTIPLE_TABLES=y
 589 +CONFIG_NETFILTER=y
 590 +CONFIG_NF_CONNTRACK=m
 591 +CONFIG_NF_CONNTRACK_ZONES=y
 592 +CONFIG_NF_CONNTRACK_EVENTS=y
 593 +CONFIG_NF_CONNTRACK_TIMESTAMP=y
 594 +CONFIG_NF_CT_PROTO_DCCP=m
 595 +CONFIG_NF_CT_PROTO_SCTP=m
 596 +CONFIG_NF_CT_PROTO_UDPLITE=m
 597 +CONFIG_NF_CONNTRACK_AMANDA=m
 598 +CONFIG_NF_CONNTRACK_FTP=m
 599 +CONFIG_NF_CONNTRACK_H323=m
 600 +CONFIG_NF_CONNTRACK_IRC=m
 601 +CONFIG_NF_CONNTRACK_NETBIOS_NS=m
 602 +CONFIG_NF_CONNTRACK_SNMP=m
 603 +CONFIG_NF_CONNTRACK_PPTP=m
 604 +CONFIG_NF_CONNTRACK_SANE=m
 605 +CONFIG_NF_CONNTRACK_SIP=m
 606 +CONFIG_NF_CONNTRACK_TFTP=m
 607 +CONFIG_NF_CT_NETLINK=m
 608 +CONFIG_NETFILTER_TPROXY=m
 609 +CONFIG_NETFILTER_XT_SET=m
 610 +CONFIG_NETFILTER_XT_TARGET_AUDIT=m
 611 +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 612 +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 613 +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 614 +CONFIG_NETFILTER_XT_TARGET_DSCP=m
 615 +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
 616 +CONFIG_NETFILTER_XT_TARGET_MARK=m
 617 +CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 618 +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
 619 +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
 620 +CONFIG_NETFILTER_XT_TARGET_TEE=m
 621 +CONFIG_NETFILTER_XT_TARGET_TPROXY=m
 622 +CONFIG_NETFILTER_XT_TARGET_TRACE=m
 623 +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 624 +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
 625 +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
 626 +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
 627 +CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 628 +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
 629 +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
 630 +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
 631 +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
 632 +CONFIG_NETFILTER_XT_MATCH_CPU=m
 633 +CONFIG_NETFILTER_XT_MATCH_DCCP=m
 634 +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
 635 +CONFIG_NETFILTER_XT_MATCH_DSCP=m
 636 +CONFIG_NETFILTER_XT_MATCH_ESP=m
 637 +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 638 +CONFIG_NETFILTER_XT_MATCH_HELPER=m
 639 +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
 640 +CONFIG_NETFILTER_XT_MATCH_LENGTH=m
 641 +CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 642 +CONFIG_NETFILTER_XT_MATCH_MAC=m
 643 +CONFIG_NETFILTER_XT_MATCH_MARK=m
 644 +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
 645 +CONFIG_NETFILTER_XT_MATCH_OSF=m
 646 +CONFIG_NETFILTER_XT_MATCH_OWNER=m
 647 +CONFIG_NETFILTER_XT_MATCH_POLICY=m
 648 +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
 649 +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
 650 +CONFIG_NETFILTER_XT_MATCH_QUOTA=m
 651 +CONFIG_NETFILTER_XT_MATCH_RATEEST=m
 652 +CONFIG_NETFILTER_XT_MATCH_REALM=m
 653 +CONFIG_NETFILTER_XT_MATCH_RECENT=m
 654 +CONFIG_NETFILTER_XT_MATCH_SCTP=m
 655 +CONFIG_NETFILTER_XT_MATCH_SOCKET=m
 656 +CONFIG_NETFILTER_XT_MATCH_STATE=m
 657 +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
 658 +CONFIG_NETFILTER_XT_MATCH_STRING=m
 659 +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 660 +CONFIG_NETFILTER_XT_MATCH_TIME=m
 661 +CONFIG_NETFILTER_XT_MATCH_U32=m
 662 +CONFIG_IP_SET=m
 663 +CONFIG_IP_SET_BITMAP_IP=m
 664 +CONFIG_IP_SET_BITMAP_IPMAC=m
 665 +CONFIG_IP_SET_BITMAP_PORT=m
 666 +CONFIG_IP_SET_HASH_IP=m
 667 +CONFIG_IP_SET_HASH_IPPORT=m
 668 +CONFIG_IP_SET_HASH_IPPORTIP=m
 669 +CONFIG_IP_SET_HASH_IPPORTNET=m
 670 +CONFIG_IP_SET_HASH_NET=m
 671 +CONFIG_IP_SET_HASH_NETPORT=m
 672 +CONFIG_IP_SET_HASH_NETIFACE=m
 673 +CONFIG_IP_SET_LIST_SET=m
 674 +CONFIG_NF_CONNTRACK_IPV4=m
 675 +CONFIG_IP_NF_IPTABLES=m
 676 +CONFIG_IP_NF_MATCH_AH=m
 677 +CONFIG_IP_NF_MATCH_ECN=m
 678 +CONFIG_IP_NF_MATCH_TTL=m
 679 +CONFIG_IP_NF_FILTER=m
 680 +CONFIG_IP_NF_TARGET_REJECT=m
 681 +CONFIG_IP_NF_TARGET_ULOG=m
 682 +CONFIG_IP_NF_MANGLE=m
 683 +CONFIG_IP_NF_TARGET_ECN=m
 684 +CONFIG_IP_NF_TARGET_TTL=m
 685 +CONFIG_IP_NF_RAW=m
 686 +CONFIG_IP_NF_ARPTABLES=m
 687 +CONFIG_IP_NF_ARPFILTER=m
 688 +CONFIG_IP_NF_ARP_MANGLE=m
 689 +CONFIG_NF_CONNTRACK_IPV6=m
 690 +CONFIG_IP6_NF_IPTABLES=m
 691 +CONFIG_IP6_NF_MATCH_AH=m
 692 +CONFIG_IP6_NF_MATCH_EUI64=m
 693 +CONFIG_IP6_NF_MATCH_FRAG=m
 694 +CONFIG_IP6_NF_MATCH_OPTS=m
 695 +CONFIG_IP6_NF_MATCH_HL=m
 696 +CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 697 +CONFIG_IP6_NF_MATCH_MH=m
 698 +CONFIG_IP6_NF_MATCH_RT=m
 699 +CONFIG_IP6_NF_TARGET_HL=m
 700 +CONFIG_IP6_NF_FILTER=m
 701 +CONFIG_IP6_NF_TARGET_REJECT=m
 702 +CONFIG_IP6_NF_MANGLE=m
 703 +CONFIG_IP6_NF_RAW=m
 704 +CONFIG_BRIDGE_NF_EBTABLES=m
 705 +CONFIG_BRIDGE_EBT_BROUTE=m
 706 +CONFIG_BRIDGE_EBT_T_FILTER=m
 707 +CONFIG_BRIDGE_EBT_T_NAT=m
 708 +CONFIG_BRIDGE_EBT_802_3=m
 709 +CONFIG_BRIDGE_EBT_AMONG=m
 710 +CONFIG_BRIDGE_EBT_ARP=m
 711 +CONFIG_BRIDGE_EBT_IP=m
 712 +CONFIG_BRIDGE_EBT_IP6=m
 713 +CONFIG_BRIDGE_EBT_LIMIT=m
 714 +CONFIG_BRIDGE_EBT_MARK=m
 715 +CONFIG_BRIDGE_EBT_PKTTYPE=m
 716 +CONFIG_BRIDGE_EBT_STP=m
 717 +CONFIG_BRIDGE_EBT_VLAN=m
 718 +CONFIG_BRIDGE_EBT_ARPREPLY=m
 719 +CONFIG_BRIDGE_EBT_DNAT=m
 720 +CONFIG_BRIDGE_EBT_MARK_T=m
 721 +CONFIG_BRIDGE_EBT_REDIRECT=m
 722 +CONFIG_BRIDGE_EBT_SNAT=m
 723 +CONFIG_BRIDGE_EBT_LOG=m
 724 +CONFIG_BRIDGE_EBT_ULOG=m
 725 +CONFIG_BRIDGE_EBT_NFLOG=m
 726 +CONFIG_L2TP=m
 727 +CONFIG_BRIDGE=m
 728 +CONFIG_VLAN_8021Q=m
 729 +CONFIG_VLAN_8021Q_GVRP=y
 730 +CONFIG_NET_SCHED=y
 731 +CONFIG_NET_SCH_CBQ=m
 732 +CONFIG_NET_SCH_HTB=m
 733 +CONFIG_NET_SCH_HFSC=m
 734 +CONFIG_NET_SCH_PRIO=m
 735 +CONFIG_NET_SCH_MULTIQ=m
 736 +CONFIG_NET_SCH_RED=m
 737 +CONFIG_NET_SCH_SFB=m
 738 +CONFIG_NET_SCH_SFQ=m
 739 +CONFIG_NET_SCH_TEQL=m
 740 +CONFIG_NET_SCH_TBF=m
 741 +CONFIG_NET_SCH_GRED=m
 742 +CONFIG_NET_SCH_DSMARK=m
 743 +CONFIG_NET_SCH_NETEM=m
 744 +CONFIG_NET_SCH_DRR=m
 745 +CONFIG_NET_SCH_MQPRIO=m
 746 +CONFIG_NET_SCH_CHOKE=m
 747 +CONFIG_NET_SCH_QFQ=m
 748 +CONFIG_NET_CLS_BASIC=m
 749 +CONFIG_NET_CLS_TCINDEX=m
 750 +CONFIG_NET_CLS_ROUTE4=m
 751 +CONFIG_NET_CLS_FW=m
 752 +CONFIG_NET_CLS_U32=m
 753 +CONFIG_CLS_U32_MARK=y
 754 +CONFIG_NET_CLS_RSVP=m
 755 +CONFIG_NET_CLS_RSVP6=m
 756 +CONFIG_NET_CLS_FLOW=m
 757 +CONFIG_NET_CLS_CGROUP=m
 758 +CONFIG_NET_EMATCH=y
 759 +CONFIG_NET_EMATCH_CMP=m
 760 +CONFIG_NET_EMATCH_NBYTE=m
 761 +CONFIG_NET_EMATCH_U32=m
 762 +CONFIG_NET_EMATCH_META=m
 763 +CONFIG_NET_EMATCH_TEXT=m
 764 +CONFIG_NET_CLS_ACT=y
 765 +CONFIG_NET_ACT_POLICE=m
 766 +CONFIG_NET_ACT_GACT=m
 767 +CONFIG_GACT_PROB=y
 768 +CONFIG_NET_ACT_MIRRED=m
 769 +CONFIG_NET_ACT_IPT=m
 770 +CONFIG_NET_ACT_NAT=m
 771 +CONFIG_NET_ACT_PEDIT=m
 772 +CONFIG_NET_ACT_SIMP=m
 773 +CONFIG_NET_ACT_SKBEDIT=m
 774 +CONFIG_NET_ACT_CSUM=m
 775 +CONFIG_NET_PKTGEN=m
 776 +CONFIG_IRDA=m
 777 +CONFIG_IRLAN=m
 778 +CONFIG_IRCOMM=m
 779 +CONFIG_IRDA_ULTRA=y
 780 +CONFIG_IRDA_CACHE_LAST_LSAP=y
 781 +CONFIG_IRDA_FAST_RR=y
 782 +CONFIG_IRTTY_SIR=m
 783 +CONFIG_KINGSUN_DONGLE=m
 784 +CONFIG_KSDAZZLE_DONGLE=m
 785 +CONFIG_KS959_DONGLE=m
 786 +CONFIG_USB_IRDA=m
 787 +CONFIG_SIGMATEL_FIR=m
 788 +CONFIG_MCS_FIR=m
 789 +CONFIG_BT=m
 790 +CONFIG_BT_RFCOMM=m
 791 +CONFIG_BT_RFCOMM_TTY=y
 792 +CONFIG_BT_BNEP=m
 793 +CONFIG_BT_BNEP_MC_FILTER=y
 794 +CONFIG_BT_BNEP_PROTO_FILTER=y
 795 +CONFIG_BT_HIDP=m
 796 +CONFIG_BT_HCIBTUSB=m
 797 +CONFIG_BT_HCIBCM203X=m
 798 +CONFIG_BT_HCIBPA10X=m
 799 +CONFIG_BT_HCIBFUSB=m
 800 +CONFIG_BT_HCIVHCI=m
 801 +CONFIG_BT_MRVL=m
 802 +CONFIG_BT_MRVL_SDIO=m
 803 +CONFIG_BT_ATH3K=m
 804 +CONFIG_CFG80211=m
 805 +CONFIG_MAC80211=m
 806 +CONFIG_MAC80211_RC_PID=y
 807 +CONFIG_MAC80211_MESH=y
 808 +CONFIG_WIMAX=m
 809 +CONFIG_NET_9P=m
 810 +CONFIG_NFC=m
 811 +CONFIG_NFC_PN533=m
 812 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 813 +CONFIG_DEVTMPFS=y
 814 +CONFIG_DEVTMPFS_MOUNT=y
 815 +CONFIG_BLK_DEV_LOOP=y
 816 +CONFIG_BLK_DEV_CRYPTOLOOP=m
 817 +CONFIG_BLK_DEV_DRBD=m
 818 +CONFIG_BLK_DEV_NBD=m
 819 +CONFIG_BLK_DEV_RAM=y
 820 +CONFIG_CDROM_PKTCDVD=m
 821 +CONFIG_SCSI=y
 822 +# CONFIG_SCSI_PROC_FS is not set
 823 +CONFIG_BLK_DEV_SD=m
 824 +CONFIG_BLK_DEV_SR=m
 825 +CONFIG_SCSI_MULTI_LUN=y
 826 +# CONFIG_SCSI_LOWLEVEL is not set
 827 +CONFIG_MD=y
 828 +CONFIG_NETDEVICES=y
 829 +CONFIG_NETCONSOLE=m
 830 +CONFIG_TUN=m
 831 +CONFIG_MDIO_BITBANG=m
 832 +CONFIG_PPP=m
 833 +CONFIG_PPP_BSDCOMP=m
 834 +CONFIG_PPP_DEFLATE=m
 835 +CONFIG_PPP_ASYNC=m
 836 +CONFIG_PPP_SYNC_TTY=m
 837 +CONFIG_SLIP=m
 838 +CONFIG_SLIP_COMPRESSED=y
 839 +CONFIG_USB_CATC=m
 840 +CONFIG_USB_KAWETH=m
 841 +CONFIG_USB_PEGASUS=m
 842 +CONFIG_USB_RTL8150=m
 843 +CONFIG_USB_USBNET=y
 844 +CONFIG_USB_NET_AX8817X=m
 845 +CONFIG_USB_NET_CDCETHER=m
 846 +CONFIG_USB_NET_CDC_EEM=m
 847 +CONFIG_USB_NET_DM9601=m
 848 +CONFIG_USB_NET_SMSC75XX=m
 849 +CONFIG_USB_NET_SMSC95XX=y
 850 +CONFIG_USB_NET_GL620A=m
 851 +CONFIG_USB_NET_NET1080=m
 852 +CONFIG_USB_NET_PLUSB=m
 853 +CONFIG_USB_NET_MCS7830=m
 854 +CONFIG_USB_NET_CDC_SUBSET=m
 855 +CONFIG_USB_ALI_M5632=y
 856 +CONFIG_USB_AN2720=y
 857 +CONFIG_USB_KC2190=y
 858 +# CONFIG_USB_NET_ZAURUS is not set
 859 +CONFIG_USB_NET_CX82310_ETH=m
 860 +CONFIG_USB_NET_KALMIA=m
 861 +CONFIG_USB_NET_INT51X1=m
 862 +CONFIG_USB_IPHETH=m
 863 +CONFIG_USB_SIERRA_NET=m
 864 +CONFIG_USB_VL600=m
 865 +CONFIG_LIBERTAS_THINFIRM=m
 866 +CONFIG_LIBERTAS_THINFIRM_USB=m
 867 +CONFIG_AT76C50X_USB=m
 868 +CONFIG_USB_ZD1201=m
 869 +CONFIG_USB_NET_RNDIS_WLAN=m
 870 +CONFIG_RTL8187=m
 871 +CONFIG_MAC80211_HWSIM=m
 872 +CONFIG_B43=m
 873 +CONFIG_B43LEGACY=m
 874 +CONFIG_HOSTAP=m
 875 +CONFIG_LIBERTAS=m
 876 +CONFIG_LIBERTAS_USB=m
 877 +CONFIG_LIBERTAS_SDIO=m
 878 +CONFIG_P54_COMMON=m
 879 +CONFIG_P54_USB=m
 880 +CONFIG_RT2X00=m
 881 +CONFIG_RT2500USB=m
 882 +CONFIG_RT73USB=m
 883 +CONFIG_RT2800USB=m
 884 +CONFIG_RT2800USB_RT53XX=y
 885 +CONFIG_RT2800USB_UNKNOWN=y
 886 +CONFIG_ZD1211RW=m
 887 +CONFIG_MWIFIEX=m
 888 +CONFIG_MWIFIEX_SDIO=m
 889 +CONFIG_WIMAX_I2400M_USB=m
 890 +CONFIG_INPUT_POLLDEV=m
 891 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 892 +CONFIG_INPUT_JOYDEV=m
 893 +CONFIG_INPUT_EVDEV=m
 894 +# CONFIG_INPUT_KEYBOARD is not set
 895 +# CONFIG_INPUT_MOUSE is not set
 896 +CONFIG_INPUT_MISC=y
 897 +CONFIG_INPUT_AD714X=m
 898 +CONFIG_INPUT_ATI_REMOTE2=m
 899 +CONFIG_INPUT_KEYSPAN_REMOTE=m
 900 +CONFIG_INPUT_POWERMATE=m
 901 +CONFIG_INPUT_YEALINK=m
 902 +CONFIG_INPUT_CM109=m
 903 +CONFIG_INPUT_UINPUT=m
 904 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
 905 +CONFIG_INPUT_ADXL34X=m
 906 +CONFIG_INPUT_CMA3000=m
 907 +CONFIG_SERIO=m
 908 +CONFIG_SERIO_RAW=m
 909 +CONFIG_GAMEPORT=m
 910 +CONFIG_GAMEPORT_NS558=m
 911 +CONFIG_GAMEPORT_L4=m
 912 +CONFIG_VT_HW_CONSOLE_BINDING=y
 913 +# CONFIG_LEGACY_PTYS is not set
 914 +# CONFIG_DEVKMEM is not set
 915 +CONFIG_SERIAL_AMBA_PL011=y
 916 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 917 +# CONFIG_HW_RANDOM is not set
 918 +CONFIG_RAW_DRIVER=y
 919 +CONFIG_I2C=y
 920 +CONFIG_I2C_CHARDEV=m
 921 +CONFIG_I2C_BCM2708=m
 922 +CONFIG_SPI=y
 923 +CONFIG_SPI_BCM2708=m
 924 +CONFIG_SPI_SPIDEV=m
 925 +CONFIG_GPIO_SYSFS=y
 926 +# CONFIG_HWMON is not set
 927 +CONFIG_THERMAL=y
 928 +CONFIG_THERMAL_BCM2835=y
 929 +CONFIG_WATCHDOG=y
 930 +CONFIG_BCM2708_WDT=m
 931 +CONFIG_MEDIA_SUPPORT=m
 932 +CONFIG_FB=y
 933 +CONFIG_FB_BCM2708=y
 934 +CONFIG_FRAMEBUFFER_CONSOLE=y
 935 +CONFIG_LOGO=y
 936 +# CONFIG_LOGO_LINUX_MONO is not set
 937 +# CONFIG_LOGO_LINUX_VGA16 is not set
 938 +CONFIG_SOUND=y
 939 +CONFIG_SND=m
 940 +CONFIG_SND_SEQUENCER=m
 941 +CONFIG_SND_SEQ_DUMMY=m
 942 +CONFIG_SND_MIXER_OSS=m
 943 +CONFIG_SND_PCM_OSS=m
 944 +CONFIG_SND_SEQUENCER_OSS=y
 945 +CONFIG_SND_HRTIMER=m
 946 +CONFIG_SND_DUMMY=m
 947 +CONFIG_SND_ALOOP=m
 948 +CONFIG_SND_VIRMIDI=m
 949 +CONFIG_SND_MTPAV=m
 950 +CONFIG_SND_SERIAL_U16550=m
 951 +CONFIG_SND_MPU401=m
 952 +CONFIG_SND_BCM2835=m
 953 +CONFIG_SND_USB_AUDIO=m
 954 +CONFIG_SND_USB_UA101=m
 955 +CONFIG_SND_USB_CAIAQ=m
 956 +CONFIG_SND_USB_6FIRE=m
 957 +CONFIG_SOUND_PRIME=m
 958 +CONFIG_HID_A4TECH=m
 959 +CONFIG_HID_ACRUX=m
 960 +CONFIG_HID_APPLE=m
 961 +CONFIG_HID_BELKIN=m
 962 +CONFIG_HID_CHERRY=m
 963 +CONFIG_HID_CHICONY=m
 964 +CONFIG_HID_CYPRESS=m
 965 +CONFIG_HID_DRAGONRISE=m
 966 +CONFIG_HID_EMS_FF=m
 967 +CONFIG_HID_ELECOM=m
 968 +CONFIG_HID_EZKEY=m
 969 +CONFIG_HID_HOLTEK=m
 970 +CONFIG_HID_KEYTOUCH=m
 971 +CONFIG_HID_KYE=m
 972 +CONFIG_HID_UCLOGIC=m
 973 +CONFIG_HID_WALTOP=m
 974 +CONFIG_HID_GYRATION=m
 975 +CONFIG_HID_TWINHAN=m
 976 +CONFIG_HID_KENSINGTON=m
 977 +CONFIG_HID_LCPOWER=m
 978 +CONFIG_HID_LOGITECH=m
 979 +CONFIG_HID_MAGICMOUSE=m
 980 +CONFIG_HID_MICROSOFT=m
 981 +CONFIG_HID_MONTEREY=m
 982 +CONFIG_HID_MULTITOUCH=m
 983 +CONFIG_HID_NTRIG=m
 984 +CONFIG_HID_ORTEK=m
 985 +CONFIG_HID_PANTHERLORD=m
 986 +CONFIG_HID_PETALYNX=m
 987 +CONFIG_HID_PICOLCD=m
 988 +CONFIG_HID_ROCCAT=m
 989 +CONFIG_HID_SAMSUNG=m
 990 +CONFIG_HID_SONY=m
 991 +CONFIG_HID_SPEEDLINK=m
 992 +CONFIG_HID_SUNPLUS=m
 993 +CONFIG_HID_GREENASIA=m
 994 +CONFIG_HID_SMARTJOYPLUS=m
 995 +CONFIG_HID_TOPSEED=m
 996 +CONFIG_HID_THRUSTMASTER=m
 997 +CONFIG_HID_ZEROPLUS=m
 998 +CONFIG_HID_ZYDACRON=m
 999 +CONFIG_HID_PID=y
1000 +CONFIG_USB_HIDDEV=y
1001 +CONFIG_USB=y
1002 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1003 +CONFIG_USB_MON=m
1004 +CONFIG_USB_DWCOTG=y
1005 +CONFIG_USB_STORAGE=y
1006 +CONFIG_USB_STORAGE_REALTEK=m
1007 +CONFIG_USB_STORAGE_DATAFAB=m
1008 +CONFIG_USB_STORAGE_FREECOM=m
1009 +CONFIG_USB_STORAGE_ISD200=m
1010 +CONFIG_USB_STORAGE_USBAT=m
1011 +CONFIG_USB_STORAGE_SDDR09=m
1012 +CONFIG_USB_STORAGE_SDDR55=m
1013 +CONFIG_USB_STORAGE_JUMPSHOT=m
1014 +CONFIG_USB_STORAGE_ALAUDA=m
1015 +CONFIG_USB_STORAGE_ONETOUCH=m
1016 +CONFIG_USB_STORAGE_KARMA=m
1017 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
1018 +CONFIG_USB_STORAGE_ENE_UB6250=m
1019 +CONFIG_USB_MDC800=m
1020 +CONFIG_USB_MICROTEK=m
1021 +CONFIG_USB_SERIAL=m
1022 +CONFIG_USB_SERIAL_GENERIC=y
1023 +CONFIG_USB_SERIAL_AIRCABLE=m
1024 +CONFIG_USB_SERIAL_ARK3116=m
1025 +CONFIG_USB_SERIAL_BELKIN=m
1026 +CONFIG_USB_SERIAL_CH341=m
1027 +CONFIG_USB_SERIAL_WHITEHEAT=m
1028 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
1029 +CONFIG_USB_SERIAL_CP210X=m
1030 +CONFIG_USB_SERIAL_CYPRESS_M8=m
1031 +CONFIG_USB_SERIAL_EMPEG=m
1032 +CONFIG_USB_SERIAL_FTDI_SIO=m
1033 +CONFIG_USB_SERIAL_FUNSOFT=m
1034 +CONFIG_USB_SERIAL_VISOR=m
1035 +CONFIG_USB_SERIAL_IPAQ=m
1036 +CONFIG_USB_SERIAL_IR=m
1037 +CONFIG_USB_SERIAL_EDGEPORT=m
1038 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
1039 +CONFIG_USB_SERIAL_GARMIN=m
1040 +CONFIG_USB_SERIAL_IPW=m
1041 +CONFIG_USB_SERIAL_IUU=m
1042 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
1043 +CONFIG_USB_SERIAL_KEYSPAN=m
1044 +CONFIG_USB_SERIAL_KLSI=m
1045 +CONFIG_USB_SERIAL_KOBIL_SCT=m
1046 +CONFIG_USB_SERIAL_MCT_U232=m
1047 +CONFIG_USB_SERIAL_MOS7720=m
1048 +CONFIG_USB_SERIAL_MOS7840=m
1049 +CONFIG_USB_SERIAL_MOTOROLA=m
1050 +CONFIG_USB_SERIAL_NAVMAN=m
1051 +CONFIG_USB_SERIAL_PL2303=m
1052 +CONFIG_USB_SERIAL_OTI6858=m
1053 +CONFIG_USB_SERIAL_QCAUX=m
1054 +CONFIG_USB_SERIAL_QUALCOMM=m
1055 +CONFIG_USB_SERIAL_SPCP8X5=m
1056 +CONFIG_USB_SERIAL_HP4X=m
1057 +CONFIG_USB_SERIAL_SAFE=m
1058 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
1059 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
1060 +CONFIG_USB_SERIAL_SYMBOL=m
1061 +CONFIG_USB_SERIAL_TI=m
1062 +CONFIG_USB_SERIAL_CYBERJACK=m
1063 +CONFIG_USB_SERIAL_XIRCOM=m
1064 +CONFIG_USB_SERIAL_OPTION=m
1065 +CONFIG_USB_SERIAL_OMNINET=m
1066 +CONFIG_USB_SERIAL_OPTICON=m
1067 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
1068 +CONFIG_USB_SERIAL_ZIO=m
1069 +CONFIG_USB_SERIAL_SSU100=m
1070 +CONFIG_USB_SERIAL_DEBUG=m
1071 +CONFIG_USB_EMI62=m
1072 +CONFIG_USB_EMI26=m
1073 +CONFIG_USB_ADUTUX=m
1074 +CONFIG_USB_SEVSEG=m
1075 +CONFIG_USB_RIO500=m
1076 +CONFIG_USB_LEGOTOWER=m
1077 +CONFIG_USB_LCD=m
1078 +CONFIG_USB_LED=m
1079 +CONFIG_USB_CYPRESS_CY7C63=m
1080 +CONFIG_USB_CYTHERM=m
1081 +CONFIG_USB_IDMOUSE=m
1082 +CONFIG_USB_FTDI_ELAN=m
1083 +CONFIG_USB_APPLEDISPLAY=m
1084 +CONFIG_USB_LD=m
1085 +CONFIG_USB_TRANCEVIBRATOR=m
1086 +CONFIG_USB_IOWARRIOR=m
1087 +CONFIG_USB_TEST=m
1088 +CONFIG_USB_ISIGHTFW=m
1089 +CONFIG_USB_YUREX=m
1090 +CONFIG_MMC=y
1091 +CONFIG_MMC_SDHCI=y
1092 +CONFIG_MMC_SDHCI_PLTFM=y
1093 +CONFIG_MMC_SDHCI_BCM2708=y
1094 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1095 +CONFIG_RTC_CLASS=y
1096 +CONFIG_RTC_DRV_DS1307=m
1097 +CONFIG_RTC_DRV_DS1374=m
1098 +CONFIG_RTC_DRV_DS1672=m
1099 +CONFIG_RTC_DRV_DS3232=m
1100 +CONFIG_RTC_DRV_MAX6900=m
1101 +CONFIG_RTC_DRV_RS5C372=m
1102 +CONFIG_RTC_DRV_ISL1208=m
1103 +CONFIG_RTC_DRV_ISL12022=m
1104 +CONFIG_RTC_DRV_X1205=m
1105 +CONFIG_RTC_DRV_PCF8563=m
1106 +CONFIG_RTC_DRV_PCF8583=m
1107 +CONFIG_RTC_DRV_M41T80=m
1108 +CONFIG_RTC_DRV_BQ32K=m
1109 +CONFIG_RTC_DRV_S35390A=m
1110 +CONFIG_RTC_DRV_FM3130=m
1111 +CONFIG_RTC_DRV_RX8581=m
1112 +CONFIG_RTC_DRV_RX8025=m
1113 +CONFIG_RTC_DRV_EM3027=m
1114 +CONFIG_RTC_DRV_RV3029C2=m
1115 +CONFIG_RTC_DRV_M41T93=m
1116 +CONFIG_RTC_DRV_M41T94=m
1117 +CONFIG_RTC_DRV_DS1305=m
1118 +CONFIG_RTC_DRV_DS1390=m
1119 +CONFIG_RTC_DRV_MAX6902=m
1120 +CONFIG_RTC_DRV_R9701=m
1121 +CONFIG_RTC_DRV_RS5C348=m
1122 +CONFIG_RTC_DRV_DS3234=m
1123 +CONFIG_RTC_DRV_PCF2123=m
1124 +CONFIG_UIO=m
1125 +CONFIG_UIO_PDRV=m
1126 +CONFIG_UIO_PDRV_GENIRQ=m
1127 +# CONFIG_IOMMU_SUPPORT is not set
1128 +CONFIG_EXT4_FS=y
1129 +CONFIG_EXT4_FS_POSIX_ACL=y
1130 +CONFIG_EXT4_FS_SECURITY=y
1131 +CONFIG_REISERFS_FS=m
1132 +CONFIG_REISERFS_FS_XATTR=y
1133 +CONFIG_REISERFS_FS_POSIX_ACL=y
1134 +CONFIG_REISERFS_FS_SECURITY=y
1135 +CONFIG_JFS_FS=m
1136 +CONFIG_JFS_POSIX_ACL=y
1137 +CONFIG_JFS_SECURITY=y
1138 +CONFIG_JFS_STATISTICS=y
1139 +CONFIG_XFS_FS=m
1140 +CONFIG_XFS_QUOTA=y
1141 +CONFIG_XFS_POSIX_ACL=y
1142 +CONFIG_XFS_RT=y
1143 +CONFIG_GFS2_FS=m
1144 +CONFIG_OCFS2_FS=m
1145 +CONFIG_BTRFS_FS=m
1146 +CONFIG_BTRFS_FS_POSIX_ACL=y
1147 +CONFIG_NILFS2_FS=m
1148 +CONFIG_FANOTIFY=y
1149 +CONFIG_AUTOFS4_FS=y
1150 +CONFIG_FUSE_FS=m
1151 +CONFIG_CUSE=m
1152 +CONFIG_FSCACHE=y
1153 +CONFIG_FSCACHE_STATS=y
1154 +CONFIG_FSCACHE_HISTOGRAM=y
1155 +CONFIG_CACHEFILES=y
1156 +CONFIG_ISO9660_FS=m
1157 +CONFIG_JOLIET=y
1158 +CONFIG_ZISOFS=y
1159 +CONFIG_UDF_FS=m
1160 +CONFIG_MSDOS_FS=y
1161 +CONFIG_VFAT_FS=y
1162 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1163 +CONFIG_NTFS_FS=m
1164 +CONFIG_TMPFS=y
1165 +CONFIG_TMPFS_POSIX_ACL=y
1166 +CONFIG_CONFIGFS_FS=y
1167 +CONFIG_SQUASHFS=m
1168 +CONFIG_SQUASHFS_XATTR=y
1169 +CONFIG_SQUASHFS_LZO=y
1170 +CONFIG_SQUASHFS_XZ=y
1171 +CONFIG_NFS_FS=y
1172 +CONFIG_NFS_V3_ACL=y
1173 +CONFIG_NFS_V4=y
1174 +CONFIG_ROOT_NFS=y
1175 +CONFIG_NFS_FSCACHE=y
1176 +CONFIG_NFSD=m
1177 +CONFIG_NFSD_V3_ACL=y
1178 +CONFIG_NFSD_V4=y
1179 +CONFIG_CIFS=m
1180 +CONFIG_CIFS_WEAK_PW_HASH=y
1181 +CONFIG_CIFS_XATTR=y
1182 +CONFIG_CIFS_POSIX=y
1183 +CONFIG_9P_FS=m
1184 +CONFIG_9P_FS_POSIX_ACL=y
1185 +CONFIG_NLS_DEFAULT="utf8"
1186 +CONFIG_NLS_CODEPAGE_437=y
1187 +CONFIG_NLS_CODEPAGE_737=m
1188 +CONFIG_NLS_CODEPAGE_775=m
1189 +CONFIG_NLS_CODEPAGE_850=m
1190 +CONFIG_NLS_CODEPAGE_852=m
1191 +CONFIG_NLS_CODEPAGE_855=m
1192 +CONFIG_NLS_CODEPAGE_857=m
1193 +CONFIG_NLS_CODEPAGE_860=m
1194 +CONFIG_NLS_CODEPAGE_861=m
1195 +CONFIG_NLS_CODEPAGE_862=m
1196 +CONFIG_NLS_CODEPAGE_863=m
1197 +CONFIG_NLS_CODEPAGE_864=m
1198 +CONFIG_NLS_CODEPAGE_865=m
1199 +CONFIG_NLS_CODEPAGE_866=m
1200 +CONFIG_NLS_CODEPAGE_869=m
1201 +CONFIG_NLS_CODEPAGE_936=m
1202 +CONFIG_NLS_CODEPAGE_950=m
1203 +CONFIG_NLS_CODEPAGE_932=m
1204 +CONFIG_NLS_CODEPAGE_949=m
1205 +CONFIG_NLS_CODEPAGE_874=m
1206 +CONFIG_NLS_ISO8859_8=m
1207 +CONFIG_NLS_CODEPAGE_1250=m
1208 +CONFIG_NLS_CODEPAGE_1251=m
1209 +CONFIG_NLS_ASCII=y
1210 +CONFIG_NLS_ISO8859_1=m
1211 +CONFIG_NLS_ISO8859_2=m
1212 +CONFIG_NLS_ISO8859_3=m
1213 +CONFIG_NLS_ISO8859_4=m
1214 +CONFIG_NLS_ISO8859_5=m
1215 +CONFIG_NLS_ISO8859_6=m
1216 +CONFIG_NLS_ISO8859_7=m
1217 +CONFIG_NLS_ISO8859_9=m
1218 +CONFIG_NLS_ISO8859_13=m
1219 +CONFIG_NLS_ISO8859_14=m
1220 +CONFIG_NLS_ISO8859_15=m
1221 +CONFIG_NLS_KOI8_R=m
1222 +CONFIG_NLS_KOI8_U=m
1223 +CONFIG_NLS_UTF8=m
1224 +CONFIG_PRINTK_TIME=y
1225 +CONFIG_DETECT_HUNG_TASK=y
1226 +CONFIG_TIMER_STATS=y
1227 +CONFIG_DEBUG_STACK_USAGE=y
1228 +CONFIG_DEBUG_INFO=y
1229 +CONFIG_DEBUG_MEMORY_INIT=y
1230 +CONFIG_BOOT_PRINTK_DELAY=y
1231 +CONFIG_LATENCYTOP=y
1232 +CONFIG_IRQSOFF_TRACER=y
1233 +CONFIG_SCHED_TRACER=y
1234 +CONFIG_STACK_TRACER=y
1235 +CONFIG_BLK_DEV_IO_TRACE=y
1236 +CONFIG_FUNCTION_PROFILER=y
1237 +CONFIG_KGDB=y
1238 +CONFIG_KGDB_KDB=y
1239 +CONFIG_KDB_KEYBOARD=y
1240 +CONFIG_STRICT_DEVMEM=y
1241 +CONFIG_CRYPTO_SEQIV=m
1242 +CONFIG_CRYPTO_CBC=y
1243 +CONFIG_CRYPTO_HMAC=y
1244 +CONFIG_CRYPTO_XCBC=m
1245 +CONFIG_CRYPTO_MD5=y
1246 +CONFIG_CRYPTO_SHA1=y
1247 +CONFIG_CRYPTO_SHA512=m
1248 +CONFIG_CRYPTO_TGR192=m
1249 +CONFIG_CRYPTO_WP512=m
1250 +CONFIG_CRYPTO_CAST5=m
1251 +CONFIG_CRYPTO_DES=y
1252 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1253 +# CONFIG_CRYPTO_HW is not set
1254 +CONFIG_CRC_ITU_T=y
1255 +CONFIG_LIBCRC32C=y
1256 diff -urN linux-3.10/arch/arm/configs/bcmrpi_emergency_defconfig linux-rpi-3.10.y/arch/arm/configs/bcmrpi_emergency_defconfig
1257 --- linux-3.10/arch/arm/configs/bcmrpi_emergency_defconfig      1970-01-01 01:00:00.000000000 +0100
1258 +++ linux-rpi-3.10.y/arch/arm/configs/bcmrpi_emergency_defconfig        2013-07-06 15:25:50.000000000 +0100
1259 @@ -0,0 +1,532 @@
1260 +CONFIG_EXPERIMENTAL=y
1261 +# CONFIG_LOCALVERSION_AUTO is not set
1262 +CONFIG_SYSVIPC=y
1263 +CONFIG_POSIX_MQUEUE=y
1264 +CONFIG_BSD_PROCESS_ACCT=y
1265 +CONFIG_BSD_PROCESS_ACCT_V3=y
1266 +CONFIG_FHANDLE=y
1267 +CONFIG_AUDIT=y
1268 +CONFIG_IKCONFIG=y
1269 +CONFIG_IKCONFIG_PROC=y
1270 +CONFIG_BLK_DEV_INITRD=y
1271 +CONFIG_INITRAMFS_SOURCE="../target_fs"
1272 +CONFIG_CGROUP_FREEZER=y
1273 +CONFIG_CGROUP_DEVICE=y
1274 +CONFIG_CGROUP_CPUACCT=y
1275 +CONFIG_RESOURCE_COUNTERS=y
1276 +CONFIG_BLK_CGROUP=y
1277 +CONFIG_NAMESPACES=y
1278 +CONFIG_SCHED_AUTOGROUP=y
1279 +CONFIG_EMBEDDED=y
1280 +# CONFIG_COMPAT_BRK is not set
1281 +CONFIG_SLAB=y
1282 +CONFIG_PROFILING=y
1283 +CONFIG_OPROFILE=m
1284 +CONFIG_KPROBES=y
1285 +CONFIG_MODULES=y
1286 +CONFIG_MODULE_UNLOAD=y
1287 +CONFIG_MODVERSIONS=y
1288 +CONFIG_MODULE_SRCVERSION_ALL=y
1289 +# CONFIG_BLK_DEV_BSG is not set
1290 +CONFIG_BLK_DEV_THROTTLING=y
1291 +CONFIG_CFQ_GROUP_IOSCHED=y
1292 +CONFIG_ARCH_BCM2708=y
1293 +CONFIG_NO_HZ=y
1294 +CONFIG_HIGH_RES_TIMERS=y
1295 +CONFIG_AEABI=y
1296 +CONFIG_SECCOMP=y
1297 +CONFIG_CC_STACKPROTECTOR=y
1298 +CONFIG_ZBOOT_ROM_TEXT=0x0
1299 +CONFIG_ZBOOT_ROM_BSS=0x0
1300 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
1301 +CONFIG_KEXEC=y
1302 +CONFIG_CPU_IDLE=y
1303 +CONFIG_VFP=y
1304 +CONFIG_BINFMT_MISC=m
1305 +CONFIG_NET=y
1306 +CONFIG_PACKET=y
1307 +CONFIG_UNIX=y
1308 +CONFIG_XFRM_USER=y
1309 +CONFIG_NET_KEY=m
1310 +CONFIG_INET=y
1311 +CONFIG_IP_MULTICAST=y
1312 +CONFIG_IP_PNP=y
1313 +CONFIG_IP_PNP_DHCP=y
1314 +CONFIG_IP_PNP_RARP=y
1315 +CONFIG_SYN_COOKIES=y
1316 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
1317 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
1318 +# CONFIG_INET_XFRM_MODE_BEET is not set
1319 +# CONFIG_INET_LRO is not set
1320 +# CONFIG_INET_DIAG is not set
1321 +# CONFIG_IPV6 is not set
1322 +CONFIG_NET_PKTGEN=m
1323 +CONFIG_IRDA=m
1324 +CONFIG_IRLAN=m
1325 +CONFIG_IRCOMM=m
1326 +CONFIG_IRDA_ULTRA=y
1327 +CONFIG_IRDA_CACHE_LAST_LSAP=y
1328 +CONFIG_IRDA_FAST_RR=y
1329 +CONFIG_IRTTY_SIR=m
1330 +CONFIG_KINGSUN_DONGLE=m
1331 +CONFIG_KSDAZZLE_DONGLE=m
1332 +CONFIG_KS959_DONGLE=m
1333 +CONFIG_USB_IRDA=m
1334 +CONFIG_SIGMATEL_FIR=m
1335 +CONFIG_MCS_FIR=m
1336 +CONFIG_BT=m
1337 +CONFIG_BT_L2CAP=y
1338 +CONFIG_BT_SCO=y
1339 +CONFIG_BT_RFCOMM=m
1340 +CONFIG_BT_RFCOMM_TTY=y
1341 +CONFIG_BT_BNEP=m
1342 +CONFIG_BT_BNEP_MC_FILTER=y
1343 +CONFIG_BT_BNEP_PROTO_FILTER=y
1344 +CONFIG_BT_HIDP=m
1345 +CONFIG_BT_HCIBTUSB=m
1346 +CONFIG_BT_HCIBCM203X=m
1347 +CONFIG_BT_HCIBPA10X=m
1348 +CONFIG_BT_HCIBFUSB=m
1349 +CONFIG_BT_HCIVHCI=m
1350 +CONFIG_BT_MRVL=m
1351 +CONFIG_BT_MRVL_SDIO=m
1352 +CONFIG_BT_ATH3K=m
1353 +CONFIG_CFG80211=m
1354 +CONFIG_MAC80211=m
1355 +CONFIG_MAC80211_RC_PID=y
1356 +CONFIG_MAC80211_MESH=y
1357 +CONFIG_WIMAX=m
1358 +CONFIG_NET_9P=m
1359 +CONFIG_NFC=m
1360 +CONFIG_NFC_PN533=m
1361 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
1362 +CONFIG_BLK_DEV_LOOP=y
1363 +CONFIG_BLK_DEV_CRYPTOLOOP=m
1364 +CONFIG_BLK_DEV_NBD=m
1365 +CONFIG_BLK_DEV_RAM=y
1366 +CONFIG_CDROM_PKTCDVD=m
1367 +CONFIG_MISC_DEVICES=y
1368 +CONFIG_SCSI=y
1369 +# CONFIG_SCSI_PROC_FS is not set
1370 +CONFIG_BLK_DEV_SD=y
1371 +CONFIG_BLK_DEV_SR=m
1372 +CONFIG_SCSI_MULTI_LUN=y
1373 +# CONFIG_SCSI_LOWLEVEL is not set
1374 +CONFIG_MD=y
1375 +CONFIG_NETDEVICES=y
1376 +CONFIG_TUN=m
1377 +CONFIG_PHYLIB=m
1378 +CONFIG_MDIO_BITBANG=m
1379 +CONFIG_NET_ETHERNET=y
1380 +# CONFIG_NETDEV_1000 is not set
1381 +# CONFIG_NETDEV_10000 is not set
1382 +CONFIG_LIBERTAS_THINFIRM=m
1383 +CONFIG_LIBERTAS_THINFIRM_USB=m
1384 +CONFIG_AT76C50X_USB=m
1385 +CONFIG_USB_ZD1201=m
1386 +CONFIG_USB_NET_RNDIS_WLAN=m
1387 +CONFIG_RTL8187=m
1388 +CONFIG_MAC80211_HWSIM=m
1389 +CONFIG_ATH_COMMON=m
1390 +CONFIG_ATH9K=m
1391 +CONFIG_ATH9K_HTC=m
1392 +CONFIG_CARL9170=m
1393 +CONFIG_B43=m
1394 +CONFIG_B43LEGACY=m
1395 +CONFIG_HOSTAP=m
1396 +CONFIG_IWM=m
1397 +CONFIG_LIBERTAS=m
1398 +CONFIG_LIBERTAS_USB=m
1399 +CONFIG_LIBERTAS_SDIO=m
1400 +CONFIG_P54_COMMON=m
1401 +CONFIG_P54_USB=m
1402 +CONFIG_RT2X00=m
1403 +CONFIG_RT2500USB=m
1404 +CONFIG_RT73USB=m
1405 +CONFIG_RT2800USB=m
1406 +CONFIG_RT2800USB_RT53XX=y
1407 +CONFIG_RTL8192CU=m
1408 +CONFIG_WL1251=m
1409 +CONFIG_WL12XX_MENU=m
1410 +CONFIG_ZD1211RW=m
1411 +CONFIG_MWIFIEX=m
1412 +CONFIG_MWIFIEX_SDIO=m
1413 +CONFIG_WIMAX_I2400M_USB=m
1414 +CONFIG_USB_CATC=m
1415 +CONFIG_USB_KAWETH=m
1416 +CONFIG_USB_PEGASUS=m
1417 +CONFIG_USB_RTL8150=m
1418 +CONFIG_USB_USBNET=y
1419 +CONFIG_USB_NET_AX8817X=m
1420 +CONFIG_USB_NET_CDCETHER=m
1421 +CONFIG_USB_NET_CDC_EEM=m
1422 +CONFIG_USB_NET_DM9601=m
1423 +CONFIG_USB_NET_SMSC75XX=m
1424 +CONFIG_USB_NET_SMSC95XX=y
1425 +CONFIG_USB_NET_GL620A=m
1426 +CONFIG_USB_NET_NET1080=m
1427 +CONFIG_USB_NET_PLUSB=m
1428 +CONFIG_USB_NET_MCS7830=m
1429 +CONFIG_USB_NET_CDC_SUBSET=m
1430 +CONFIG_USB_ALI_M5632=y
1431 +CONFIG_USB_AN2720=y
1432 +CONFIG_USB_KC2190=y
1433 +# CONFIG_USB_NET_ZAURUS is not set
1434 +CONFIG_USB_NET_CX82310_ETH=m
1435 +CONFIG_USB_NET_KALMIA=m
1436 +CONFIG_USB_NET_INT51X1=m
1437 +CONFIG_USB_IPHETH=m
1438 +CONFIG_USB_SIERRA_NET=m
1439 +CONFIG_USB_VL600=m
1440 +CONFIG_PPP=m
1441 +CONFIG_PPP_ASYNC=m
1442 +CONFIG_PPP_SYNC_TTY=m
1443 +CONFIG_PPP_DEFLATE=m
1444 +CONFIG_PPP_BSDCOMP=m
1445 +CONFIG_SLIP=m
1446 +CONFIG_SLIP_COMPRESSED=y
1447 +CONFIG_NETCONSOLE=m
1448 +CONFIG_INPUT_POLLDEV=m
1449 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1450 +CONFIG_INPUT_JOYDEV=m
1451 +CONFIG_INPUT_EVDEV=m
1452 +# CONFIG_INPUT_KEYBOARD is not set
1453 +# CONFIG_INPUT_MOUSE is not set
1454 +CONFIG_INPUT_MISC=y
1455 +CONFIG_INPUT_AD714X=m
1456 +CONFIG_INPUT_ATI_REMOTE=m
1457 +CONFIG_INPUT_ATI_REMOTE2=m
1458 +CONFIG_INPUT_KEYSPAN_REMOTE=m
1459 +CONFIG_INPUT_POWERMATE=m
1460 +CONFIG_INPUT_YEALINK=m
1461 +CONFIG_INPUT_CM109=m
1462 +CONFIG_INPUT_UINPUT=m
1463 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
1464 +CONFIG_INPUT_ADXL34X=m
1465 +CONFIG_INPUT_CMA3000=m
1466 +CONFIG_SERIO=m
1467 +CONFIG_SERIO_RAW=m
1468 +CONFIG_GAMEPORT=m
1469 +CONFIG_GAMEPORT_NS558=m
1470 +CONFIG_GAMEPORT_L4=m
1471 +CONFIG_VT_HW_CONSOLE_BINDING=y
1472 +# CONFIG_LEGACY_PTYS is not set
1473 +# CONFIG_DEVKMEM is not set
1474 +CONFIG_SERIAL_AMBA_PL011=y
1475 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1476 +# CONFIG_HW_RANDOM is not set
1477 +CONFIG_RAW_DRIVER=y
1478 +CONFIG_GPIO_SYSFS=y
1479 +# CONFIG_HWMON is not set
1480 +CONFIG_WATCHDOG=y
1481 +CONFIG_BCM2708_WDT=m
1482 +# CONFIG_MFD_SUPPORT is not set
1483 +CONFIG_FB=y
1484 +CONFIG_FB_BCM2708=y
1485 +CONFIG_FRAMEBUFFER_CONSOLE=y
1486 +CONFIG_LOGO=y
1487 +# CONFIG_LOGO_LINUX_MONO is not set
1488 +# CONFIG_LOGO_LINUX_VGA16 is not set
1489 +CONFIG_SOUND=y
1490 +CONFIG_SND=m
1491 +CONFIG_SND_SEQUENCER=m
1492 +CONFIG_SND_SEQ_DUMMY=m
1493 +CONFIG_SND_MIXER_OSS=m
1494 +CONFIG_SND_PCM_OSS=m
1495 +CONFIG_SND_SEQUENCER_OSS=y
1496 +CONFIG_SND_HRTIMER=m
1497 +CONFIG_SND_DUMMY=m
1498 +CONFIG_SND_ALOOP=m
1499 +CONFIG_SND_VIRMIDI=m
1500 +CONFIG_SND_MTPAV=m
1501 +CONFIG_SND_SERIAL_U16550=m
1502 +CONFIG_SND_MPU401=m
1503 +CONFIG_SND_BCM2835=m
1504 +CONFIG_SND_USB_AUDIO=m
1505 +CONFIG_SND_USB_UA101=m
1506 +CONFIG_SND_USB_CAIAQ=m
1507 +CONFIG_SND_USB_6FIRE=m
1508 +CONFIG_SOUND_PRIME=m
1509 +CONFIG_HID_PID=y
1510 +CONFIG_USB_HIDDEV=y
1511 +CONFIG_HID_A4TECH=m
1512 +CONFIG_HID_ACRUX=m
1513 +CONFIG_HID_APPLE=m
1514 +CONFIG_HID_BELKIN=m
1515 +CONFIG_HID_CHERRY=m
1516 +CONFIG_HID_CHICONY=m
1517 +CONFIG_HID_CYPRESS=m
1518 +CONFIG_HID_DRAGONRISE=m
1519 +CONFIG_HID_EMS_FF=m
1520 +CONFIG_HID_ELECOM=m
1521 +CONFIG_HID_EZKEY=m
1522 +CONFIG_HID_HOLTEK=m
1523 +CONFIG_HID_KEYTOUCH=m
1524 +CONFIG_HID_KYE=m
1525 +CONFIG_HID_UCLOGIC=m
1526 +CONFIG_HID_WALTOP=m
1527 +CONFIG_HID_GYRATION=m
1528 +CONFIG_HID_TWINHAN=m
1529 +CONFIG_HID_KENSINGTON=m
1530 +CONFIG_HID_LCPOWER=m
1531 +CONFIG_HID_LOGITECH=m
1532 +CONFIG_HID_MAGICMOUSE=m
1533 +CONFIG_HID_MICROSOFT=m
1534 +CONFIG_HID_MONTEREY=m
1535 +CONFIG_HID_MULTITOUCH=m
1536 +CONFIG_HID_NTRIG=m
1537 +CONFIG_HID_ORTEK=m
1538 +CONFIG_HID_PANTHERLORD=m
1539 +CONFIG_HID_PETALYNX=m
1540 +CONFIG_HID_PICOLCD=m
1541 +CONFIG_HID_QUANTA=m
1542 +CONFIG_HID_ROCCAT=m
1543 +CONFIG_HID_SAMSUNG=m
1544 +CONFIG_HID_SONY=m
1545 +CONFIG_HID_SPEEDLINK=m
1546 +CONFIG_HID_SUNPLUS=m
1547 +CONFIG_HID_GREENASIA=m
1548 +CONFIG_HID_SMARTJOYPLUS=m
1549 +CONFIG_HID_TOPSEED=m
1550 +CONFIG_HID_THRUSTMASTER=m
1551 +CONFIG_HID_WACOM=m
1552 +CONFIG_HID_WIIMOTE=m
1553 +CONFIG_HID_ZEROPLUS=m
1554 +CONFIG_HID_ZYDACRON=m
1555 +CONFIG_USB=y
1556 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1557 +CONFIG_USB_MON=m
1558 +CONFIG_USB_DWCOTG=y
1559 +CONFIG_USB_STORAGE=y
1560 +CONFIG_USB_STORAGE_REALTEK=m
1561 +CONFIG_USB_STORAGE_DATAFAB=m
1562 +CONFIG_USB_STORAGE_FREECOM=m
1563 +CONFIG_USB_STORAGE_ISD200=m
1564 +CONFIG_USB_STORAGE_USBAT=m
1565 +CONFIG_USB_STORAGE_SDDR09=m
1566 +CONFIG_USB_STORAGE_SDDR55=m
1567 +CONFIG_USB_STORAGE_JUMPSHOT=m
1568 +CONFIG_USB_STORAGE_ALAUDA=m
1569 +CONFIG_USB_STORAGE_ONETOUCH=m
1570 +CONFIG_USB_STORAGE_KARMA=m
1571 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
1572 +CONFIG_USB_STORAGE_ENE_UB6250=m
1573 +CONFIG_USB_UAS=y
1574 +CONFIG_USB_LIBUSUAL=y
1575 +CONFIG_USB_MDC800=m
1576 +CONFIG_USB_MICROTEK=m
1577 +CONFIG_USB_SERIAL=m
1578 +CONFIG_USB_SERIAL_GENERIC=y
1579 +CONFIG_USB_SERIAL_AIRCABLE=m
1580 +CONFIG_USB_SERIAL_ARK3116=m
1581 +CONFIG_USB_SERIAL_BELKIN=m
1582 +CONFIG_USB_SERIAL_CH341=m
1583 +CONFIG_USB_SERIAL_WHITEHEAT=m
1584 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
1585 +CONFIG_USB_SERIAL_CP210X=m
1586 +CONFIG_USB_SERIAL_CYPRESS_M8=m
1587 +CONFIG_USB_SERIAL_EMPEG=m
1588 +CONFIG_USB_SERIAL_FTDI_SIO=m
1589 +CONFIG_USB_SERIAL_FUNSOFT=m
1590 +CONFIG_USB_SERIAL_VISOR=m
1591 +CONFIG_USB_SERIAL_IPAQ=m
1592 +CONFIG_USB_SERIAL_IR=m
1593 +CONFIG_USB_SERIAL_EDGEPORT=m
1594 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
1595 +CONFIG_USB_SERIAL_GARMIN=m
1596 +CONFIG_USB_SERIAL_IPW=m
1597 +CONFIG_USB_SERIAL_IUU=m
1598 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
1599 +CONFIG_USB_SERIAL_KEYSPAN=m
1600 +CONFIG_USB_SERIAL_KLSI=m
1601 +CONFIG_USB_SERIAL_KOBIL_SCT=m
1602 +CONFIG_USB_SERIAL_MCT_U232=m
1603 +CONFIG_USB_SERIAL_MOS7720=m
1604 +CONFIG_USB_SERIAL_MOS7840=m
1605 +CONFIG_USB_SERIAL_MOTOROLA=m
1606 +CONFIG_USB_SERIAL_NAVMAN=m
1607 +CONFIG_USB_SERIAL_PL2303=m
1608 +CONFIG_USB_SERIAL_OTI6858=m
1609 +CONFIG_USB_SERIAL_QCAUX=m
1610 +CONFIG_USB_SERIAL_QUALCOMM=m
1611 +CONFIG_USB_SERIAL_SPCP8X5=m
1612 +CONFIG_USB_SERIAL_HP4X=m
1613 +CONFIG_USB_SERIAL_SAFE=m
1614 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
1615 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
1616 +CONFIG_USB_SERIAL_SYMBOL=m
1617 +CONFIG_USB_SERIAL_TI=m
1618 +CONFIG_USB_SERIAL_CYBERJACK=m
1619 +CONFIG_USB_SERIAL_XIRCOM=m
1620 +CONFIG_USB_SERIAL_OPTION=m
1621 +CONFIG_USB_SERIAL_OMNINET=m
1622 +CONFIG_USB_SERIAL_OPTICON=m
1623 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
1624 +CONFIG_USB_SERIAL_ZIO=m
1625 +CONFIG_USB_SERIAL_SSU100=m
1626 +CONFIG_USB_SERIAL_DEBUG=m
1627 +CONFIG_USB_EMI62=m
1628 +CONFIG_USB_EMI26=m
1629 +CONFIG_USB_ADUTUX=m
1630 +CONFIG_USB_SEVSEG=m
1631 +CONFIG_USB_RIO500=m
1632 +CONFIG_USB_LEGOTOWER=m
1633 +CONFIG_USB_LCD=m
1634 +CONFIG_USB_LED=m
1635 +CONFIG_USB_CYPRESS_CY7C63=m
1636 +CONFIG_USB_CYTHERM=m
1637 +CONFIG_USB_IDMOUSE=m
1638 +CONFIG_USB_FTDI_ELAN=m
1639 +CONFIG_USB_APPLEDISPLAY=m
1640 +CONFIG_USB_LD=m
1641 +CONFIG_USB_TRANCEVIBRATOR=m
1642 +CONFIG_USB_IOWARRIOR=m
1643 +CONFIG_USB_TEST=m
1644 +CONFIG_USB_ISIGHTFW=m
1645 +CONFIG_USB_YUREX=m
1646 +CONFIG_MMC=y
1647 +CONFIG_MMC_SDHCI=y
1648 +CONFIG_MMC_SDHCI_PLTFM=y
1649 +CONFIG_MMC_SDHCI_BCM2708=y
1650 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1651 +CONFIG_LEDS_GPIO=y
1652 +CONFIG_LEDS_TRIGGER_TIMER=m
1653 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1654 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
1655 +CONFIG_UIO=m
1656 +CONFIG_UIO_PDRV=m
1657 +CONFIG_UIO_PDRV_GENIRQ=m
1658 +# CONFIG_IOMMU_SUPPORT is not set
1659 +CONFIG_EXT4_FS=y
1660 +CONFIG_EXT4_FS_POSIX_ACL=y
1661 +CONFIG_EXT4_FS_SECURITY=y
1662 +CONFIG_REISERFS_FS=m
1663 +CONFIG_REISERFS_FS_XATTR=y
1664 +CONFIG_REISERFS_FS_POSIX_ACL=y
1665 +CONFIG_REISERFS_FS_SECURITY=y
1666 +CONFIG_JFS_FS=m
1667 +CONFIG_JFS_POSIX_ACL=y
1668 +CONFIG_JFS_SECURITY=y
1669 +CONFIG_JFS_STATISTICS=y
1670 +CONFIG_XFS_FS=m
1671 +CONFIG_XFS_QUOTA=y
1672 +CONFIG_XFS_POSIX_ACL=y
1673 +CONFIG_XFS_RT=y
1674 +CONFIG_GFS2_FS=m
1675 +CONFIG_OCFS2_FS=m
1676 +CONFIG_BTRFS_FS=m
1677 +CONFIG_BTRFS_FS_POSIX_ACL=y
1678 +CONFIG_NILFS2_FS=m
1679 +CONFIG_FANOTIFY=y
1680 +CONFIG_AUTOFS4_FS=y
1681 +CONFIG_FUSE_FS=m
1682 +CONFIG_CUSE=m
1683 +CONFIG_FSCACHE=y
1684 +CONFIG_FSCACHE_STATS=y
1685 +CONFIG_FSCACHE_HISTOGRAM=y
1686 +CONFIG_CACHEFILES=y
1687 +CONFIG_ISO9660_FS=m
1688 +CONFIG_JOLIET=y
1689 +CONFIG_ZISOFS=y
1690 +CONFIG_UDF_FS=m
1691 +CONFIG_MSDOS_FS=y
1692 +CONFIG_VFAT_FS=y
1693 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1694 +CONFIG_NTFS_FS=m
1695 +CONFIG_TMPFS=y
1696 +CONFIG_TMPFS_POSIX_ACL=y
1697 +CONFIG_CONFIGFS_FS=y
1698 +CONFIG_SQUASHFS=m
1699 +CONFIG_SQUASHFS_XATTR=y
1700 +CONFIG_SQUASHFS_LZO=y
1701 +CONFIG_SQUASHFS_XZ=y
1702 +CONFIG_NFS_FS=y
1703 +CONFIG_NFS_V3=y
1704 +CONFIG_NFS_V3_ACL=y
1705 +CONFIG_NFS_V4=y
1706 +CONFIG_ROOT_NFS=y
1707 +CONFIG_NFS_FSCACHE=y
1708 +CONFIG_CIFS=m
1709 +CONFIG_CIFS_WEAK_PW_HASH=y
1710 +CONFIG_CIFS_XATTR=y
1711 +CONFIG_CIFS_POSIX=y
1712 +CONFIG_9P_FS=m
1713 +CONFIG_9P_FS_POSIX_ACL=y
1714 +CONFIG_PARTITION_ADVANCED=y
1715 +CONFIG_MAC_PARTITION=y
1716 +CONFIG_EFI_PARTITION=y
1717 +CONFIG_NLS_DEFAULT="utf8"
1718 +CONFIG_NLS_CODEPAGE_437=y
1719 +CONFIG_NLS_CODEPAGE_737=m
1720 +CONFIG_NLS_CODEPAGE_775=m
1721 +CONFIG_NLS_CODEPAGE_850=m
1722 +CONFIG_NLS_CODEPAGE_852=m
1723 +CONFIG_NLS_CODEPAGE_855=m
1724 +CONFIG_NLS_CODEPAGE_857=m
1725 +CONFIG_NLS_CODEPAGE_860=m
1726 +CONFIG_NLS_CODEPAGE_861=m
1727 +CONFIG_NLS_CODEPAGE_862=m
1728 +CONFIG_NLS_CODEPAGE_863=m
1729 +CONFIG_NLS_CODEPAGE_864=m
1730 +CONFIG_NLS_CODEPAGE_865=m
1731 +CONFIG_NLS_CODEPAGE_866=m
1732 +CONFIG_NLS_CODEPAGE_869=m
1733 +CONFIG_NLS_CODEPAGE_936=m
1734 +CONFIG_NLS_CODEPAGE_950=m
1735 +CONFIG_NLS_CODEPAGE_932=m
1736 +CONFIG_NLS_CODEPAGE_949=m
1737 +CONFIG_NLS_CODEPAGE_874=m
1738 +CONFIG_NLS_ISO8859_8=m
1739 +CONFIG_NLS_CODEPAGE_1250=m
1740 +CONFIG_NLS_CODEPAGE_1251=m
1741 +CONFIG_NLS_ASCII=y
1742 +CONFIG_NLS_ISO8859_1=m
1743 +CONFIG_NLS_ISO8859_2=m
1744 +CONFIG_NLS_ISO8859_3=m
1745 +CONFIG_NLS_ISO8859_4=m
1746 +CONFIG_NLS_ISO8859_5=m
1747 +CONFIG_NLS_ISO8859_6=m
1748 +CONFIG_NLS_ISO8859_7=m
1749 +CONFIG_NLS_ISO8859_9=m
1750 +CONFIG_NLS_ISO8859_13=m
1751 +CONFIG_NLS_ISO8859_14=m
1752 +CONFIG_NLS_ISO8859_15=m
1753 +CONFIG_NLS_KOI8_R=m
1754 +CONFIG_NLS_KOI8_U=m
1755 +CONFIG_NLS_UTF8=m
1756 +CONFIG_PRINTK_TIME=y
1757 +CONFIG_DETECT_HUNG_TASK=y
1758 +CONFIG_TIMER_STATS=y
1759 +CONFIG_DEBUG_STACK_USAGE=y
1760 +CONFIG_DEBUG_INFO=y
1761 +CONFIG_DEBUG_MEMORY_INIT=y
1762 +CONFIG_BOOT_PRINTK_DELAY=y
1763 +CONFIG_LATENCYTOP=y
1764 +CONFIG_SYSCTL_SYSCALL_CHECK=y
1765 +CONFIG_IRQSOFF_TRACER=y
1766 +CONFIG_SCHED_TRACER=y
1767 +CONFIG_STACK_TRACER=y
1768 +CONFIG_BLK_DEV_IO_TRACE=y
1769 +CONFIG_FUNCTION_PROFILER=y
1770 +CONFIG_KGDB=y
1771 +CONFIG_KGDB_KDB=y
1772 +CONFIG_KDB_KEYBOARD=y
1773 +CONFIG_STRICT_DEVMEM=y
1774 +CONFIG_CRYPTO_AUTHENC=m
1775 +CONFIG_CRYPTO_SEQIV=m
1776 +CONFIG_CRYPTO_CBC=y
1777 +CONFIG_CRYPTO_HMAC=y
1778 +CONFIG_CRYPTO_XCBC=m
1779 +CONFIG_CRYPTO_MD5=y
1780 +CONFIG_CRYPTO_SHA1=y
1781 +CONFIG_CRYPTO_SHA256=m
1782 +CONFIG_CRYPTO_SHA512=m
1783 +CONFIG_CRYPTO_TGR192=m
1784 +CONFIG_CRYPTO_WP512=m
1785 +CONFIG_CRYPTO_CAST5=m
1786 +CONFIG_CRYPTO_DES=y
1787 +CONFIG_CRYPTO_DEFLATE=m
1788 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1789 +# CONFIG_CRYPTO_HW is not set
1790 +CONFIG_CRC_ITU_T=y
1791 +CONFIG_LIBCRC32C=y
1792 diff -urN linux-3.10/arch/arm/configs/bcmrpi_quick_defconfig linux-rpi-3.10.y/arch/arm/configs/bcmrpi_quick_defconfig
1793 --- linux-3.10/arch/arm/configs/bcmrpi_quick_defconfig  1970-01-01 01:00:00.000000000 +0100
1794 +++ linux-rpi-3.10.y/arch/arm/configs/bcmrpi_quick_defconfig    2013-07-06 15:25:50.000000000 +0100
1795 @@ -0,0 +1,197 @@
1796 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set
1797 +CONFIG_LOCALVERSION="-quick"
1798 +# CONFIG_LOCALVERSION_AUTO is not set
1799 +# CONFIG_SWAP is not set
1800 +CONFIG_SYSVIPC=y
1801 +CONFIG_POSIX_MQUEUE=y
1802 +CONFIG_NO_HZ=y
1803 +CONFIG_HIGH_RES_TIMERS=y
1804 +CONFIG_IKCONFIG=y
1805 +CONFIG_IKCONFIG_PROC=y
1806 +CONFIG_KALLSYMS_ALL=y
1807 +CONFIG_EMBEDDED=y
1808 +CONFIG_PERF_EVENTS=y
1809 +# CONFIG_COMPAT_BRK is not set
1810 +CONFIG_SLAB=y
1811 +CONFIG_MODULES=y
1812 +CONFIG_MODULE_UNLOAD=y
1813 +CONFIG_MODVERSIONS=y
1814 +CONFIG_MODULE_SRCVERSION_ALL=y
1815 +# CONFIG_BLK_DEV_BSG is not set
1816 +CONFIG_ARCH_BCM2708=y
1817 +CONFIG_PREEMPT=y
1818 +CONFIG_AEABI=y
1819 +CONFIG_UACCESS_WITH_MEMCPY=y
1820 +CONFIG_ZBOOT_ROM_TEXT=0x0
1821 +CONFIG_ZBOOT_ROM_BSS=0x0
1822 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
1823 +CONFIG_CPU_FREQ=y
1824 +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
1825 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
1826 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
1827 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
1828 +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
1829 +CONFIG_CPU_IDLE=y
1830 +CONFIG_VFP=y
1831 +CONFIG_BINFMT_MISC=y
1832 +CONFIG_NET=y
1833 +CONFIG_PACKET=y
1834 +CONFIG_UNIX=y
1835 +CONFIG_INET=y
1836 +CONFIG_IP_MULTICAST=y
1837 +CONFIG_IP_PNP=y
1838 +CONFIG_IP_PNP_DHCP=y
1839 +CONFIG_IP_PNP_RARP=y
1840 +CONFIG_SYN_COOKIES=y
1841 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
1842 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
1843 +# CONFIG_INET_XFRM_MODE_BEET is not set
1844 +# CONFIG_INET_LRO is not set
1845 +# CONFIG_INET_DIAG is not set
1846 +# CONFIG_IPV6 is not set
1847 +# CONFIG_WIRELESS is not set
1848 +CONFIG_DEVTMPFS=y
1849 +CONFIG_DEVTMPFS_MOUNT=y
1850 +CONFIG_BLK_DEV_LOOP=y
1851 +CONFIG_BLK_DEV_RAM=y
1852 +CONFIG_SCSI=y
1853 +# CONFIG_SCSI_PROC_FS is not set
1854 +# CONFIG_SCSI_LOWLEVEL is not set
1855 +CONFIG_NETDEVICES=y
1856 +# CONFIG_NET_VENDOR_BROADCOM is not set
1857 +# CONFIG_NET_VENDOR_CIRRUS is not set
1858 +# CONFIG_NET_VENDOR_FARADAY is not set
1859 +# CONFIG_NET_VENDOR_INTEL is not set
1860 +# CONFIG_NET_VENDOR_MARVELL is not set
1861 +# CONFIG_NET_VENDOR_MICREL is not set
1862 +# CONFIG_NET_VENDOR_NATSEMI is not set
1863 +# CONFIG_NET_VENDOR_SEEQ is not set
1864 +# CONFIG_NET_VENDOR_STMICRO is not set
1865 +# CONFIG_NET_VENDOR_WIZNET is not set
1866 +CONFIG_USB_USBNET=y
1867 +# CONFIG_USB_NET_AX8817X is not set
1868 +# CONFIG_USB_NET_CDCETHER is not set
1869 +# CONFIG_USB_NET_CDC_NCM is not set
1870 +CONFIG_USB_NET_SMSC95XX=y
1871 +# CONFIG_USB_NET_NET1080 is not set
1872 +# CONFIG_USB_NET_CDC_SUBSET is not set
1873 +# CONFIG_USB_NET_ZAURUS is not set
1874 +# CONFIG_WLAN is not set
1875 +# CONFIG_INPUT_MOUSEDEV is not set
1876 +CONFIG_INPUT_EVDEV=y
1877 +# CONFIG_INPUT_KEYBOARD is not set
1878 +# CONFIG_INPUT_MOUSE is not set
1879 +# CONFIG_SERIO is not set
1880 +CONFIG_VT_HW_CONSOLE_BINDING=y
1881 +# CONFIG_LEGACY_PTYS is not set
1882 +# CONFIG_DEVKMEM is not set
1883 +CONFIG_SERIAL_AMBA_PL011=y
1884 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1885 +CONFIG_TTY_PRINTK=y
1886 +CONFIG_HW_RANDOM=y
1887 +CONFIG_HW_RANDOM_BCM2708=y
1888 +CONFIG_RAW_DRIVER=y
1889 +CONFIG_THERMAL=y
1890 +CONFIG_THERMAL_BCM2835=y
1891 +CONFIG_WATCHDOG=y
1892 +CONFIG_BCM2708_WDT=y
1893 +CONFIG_REGULATOR=y
1894 +CONFIG_REGULATOR_DEBUG=y
1895 +CONFIG_REGULATOR_FIXED_VOLTAGE=y
1896 +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
1897 +CONFIG_REGULATOR_USERSPACE_CONSUMER=y
1898 +CONFIG_FB=y
1899 +CONFIG_FB_BCM2708=y
1900 +CONFIG_FRAMEBUFFER_CONSOLE=y
1901 +CONFIG_LOGO=y
1902 +# CONFIG_LOGO_LINUX_MONO is not set
1903 +# CONFIG_LOGO_LINUX_VGA16 is not set
1904 +CONFIG_SOUND=y
1905 +CONFIG_SND=y
1906 +CONFIG_SND_BCM2835=y
1907 +# CONFIG_SND_USB is not set
1908 +CONFIG_USB=y
1909 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1910 +CONFIG_USB_DWCOTG=y
1911 +CONFIG_MMC=y
1912 +CONFIG_MMC_SDHCI=y
1913 +CONFIG_MMC_SDHCI_PLTFM=y
1914 +CONFIG_MMC_SDHCI_BCM2708=y
1915 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1916 +CONFIG_NEW_LEDS=y
1917 +CONFIG_LEDS_CLASS=y
1918 +CONFIG_LEDS_TRIGGERS=y
1919 +# CONFIG_IOMMU_SUPPORT is not set
1920 +CONFIG_EXT4_FS=y
1921 +CONFIG_EXT4_FS_POSIX_ACL=y
1922 +CONFIG_EXT4_FS_SECURITY=y
1923 +CONFIG_AUTOFS4_FS=y
1924 +CONFIG_FSCACHE=y
1925 +CONFIG_CACHEFILES=y
1926 +CONFIG_MSDOS_FS=y
1927 +CONFIG_VFAT_FS=y
1928 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1929 +CONFIG_TMPFS=y
1930 +CONFIG_TMPFS_POSIX_ACL=y
1931 +CONFIG_CONFIGFS_FS=y
1932 +# CONFIG_MISC_FILESYSTEMS is not set
1933 +CONFIG_NFS_FS=y
1934 +CONFIG_NFS_V3_ACL=y
1935 +CONFIG_NFS_V4=y
1936 +CONFIG_ROOT_NFS=y
1937 +CONFIG_NFS_FSCACHE=y
1938 +CONFIG_NLS_DEFAULT="utf8"
1939 +CONFIG_NLS_CODEPAGE_437=y
1940 +CONFIG_NLS_CODEPAGE_737=y
1941 +CONFIG_NLS_CODEPAGE_775=y
1942 +CONFIG_NLS_CODEPAGE_850=y
1943 +CONFIG_NLS_CODEPAGE_852=y
1944 +CONFIG_NLS_CODEPAGE_855=y
1945 +CONFIG_NLS_CODEPAGE_857=y
1946 +CONFIG_NLS_CODEPAGE_860=y
1947 +CONFIG_NLS_CODEPAGE_861=y
1948 +CONFIG_NLS_CODEPAGE_862=y
1949 +CONFIG_NLS_CODEPAGE_863=y
1950 +CONFIG_NLS_CODEPAGE_864=y
1951 +CONFIG_NLS_CODEPAGE_865=y
1952 +CONFIG_NLS_CODEPAGE_866=y
1953 +CONFIG_NLS_CODEPAGE_869=y
1954 +CONFIG_NLS_CODEPAGE_936=y
1955 +CONFIG_NLS_CODEPAGE_950=y
1956 +CONFIG_NLS_CODEPAGE_932=y
1957 +CONFIG_NLS_CODEPAGE_949=y
1958 +CONFIG_NLS_CODEPAGE_874=y
1959 +CONFIG_NLS_ISO8859_8=y
1960 +CONFIG_NLS_CODEPAGE_1250=y
1961 +CONFIG_NLS_CODEPAGE_1251=y
1962 +CONFIG_NLS_ASCII=y
1963 +CONFIG_NLS_ISO8859_1=y
1964 +CONFIG_NLS_ISO8859_2=y
1965 +CONFIG_NLS_ISO8859_3=y
1966 +CONFIG_NLS_ISO8859_4=y
1967 +CONFIG_NLS_ISO8859_5=y
1968 +CONFIG_NLS_ISO8859_6=y
1969 +CONFIG_NLS_ISO8859_7=y
1970 +CONFIG_NLS_ISO8859_9=y
1971 +CONFIG_NLS_ISO8859_13=y
1972 +CONFIG_NLS_ISO8859_14=y
1973 +CONFIG_NLS_ISO8859_15=y
1974 +CONFIG_NLS_UTF8=y
1975 +CONFIG_PRINTK_TIME=y
1976 +CONFIG_DEBUG_FS=y
1977 +CONFIG_DETECT_HUNG_TASK=y
1978 +# CONFIG_DEBUG_PREEMPT is not set
1979 +# CONFIG_DEBUG_BUGVERBOSE is not set
1980 +# CONFIG_FTRACE is not set
1981 +CONFIG_KGDB=y
1982 +CONFIG_KGDB_KDB=y
1983 +# CONFIG_ARM_UNWIND is not set
1984 +CONFIG_CRYPTO_CBC=y
1985 +CONFIG_CRYPTO_HMAC=y
1986 +CONFIG_CRYPTO_MD5=y
1987 +CONFIG_CRYPTO_SHA1=y
1988 +CONFIG_CRYPTO_DES=y
1989 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1990 +# CONFIG_CRYPTO_HW is not set
1991 +CONFIG_CRC_ITU_T=y
1992 +CONFIG_LIBCRC32C=y
1993 diff -urN linux-3.10/arch/arm/include/asm/fiq.h linux-rpi-3.10.y/arch/arm/include/asm/fiq.h
1994 --- linux-3.10/arch/arm/include/asm/fiq.h       2013-06-30 23:13:29.000000000 +0100
1995 +++ linux-rpi-3.10.y/arch/arm/include/asm/fiq.h 2013-07-06 15:25:50.000000000 +0100
1996 @@ -42,6 +42,7 @@
1997  /* helpers defined in fiqasm.S: */
1998  extern void __set_fiq_regs(unsigned long const *regs);
1999  extern void __get_fiq_regs(unsigned long *regs);
2000 +extern void __FIQ_Branch(unsigned long *regs);
2001
2002  static inline void set_fiq_regs(struct pt_regs const *regs)
2003  {
2004 diff -urN linux-3.10/arch/arm/Kconfig linux-rpi-3.10.y/arch/arm/Kconfig
2005 --- linux-3.10/arch/arm/Kconfig 2013-06-30 23:13:29.000000000 +0100
2006 +++ linux-rpi-3.10.y/arch/arm/Kconfig   2013-07-06 15:25:50.000000000 +0100
2007 @@ -361,6 +361,23 @@
2008           This enables support for systems based on Atmel
2009           AT91RM9200 and AT91SAM9* processors.
2010
2011 +config ARCH_BCM2708
2012 +       bool "Broadcom BCM2708 family"
2013 +       select CPU_V6
2014 +       select ARM_AMBA
2015 +       select HAVE_CLK
2016 +       select HAVE_SCHED_CLOCK
2017 +       select NEED_MACH_MEMORY_H
2018 +       select CLKDEV_LOOKUP
2019 +       select ARCH_HAS_CPUFREQ
2020 +       select GENERIC_CLOCKEVENTS
2021 +       select ARM_ERRATA_411920
2022 +       select MACH_BCM2708
2023 +       select VC4
2024 +       select FIQ
2025 +       help
2026 +         This enables support for Broadcom BCM2708 boards.
2027 +
2028  config ARCH_CLPS711X
2029         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
2030         select ARCH_REQUIRE_GPIOLIB
2031 @@ -1025,6 +1042,7 @@
2032  source "arch/arm/mach-vt8500/Kconfig"
2033
2034  source "arch/arm/mach-w90x900/Kconfig"
2035 +source "arch/arm/mach-bcm2708/Kconfig"
2036
2037  source "arch/arm/mach-zynq/Kconfig"
2038
2039 diff -urN linux-3.10/arch/arm/Kconfig.debug linux-rpi-3.10.y/arch/arm/Kconfig.debug
2040 --- linux-3.10/arch/arm/Kconfig.debug   2013-06-30 23:13:29.000000000 +0100
2041 +++ linux-rpi-3.10.y/arch/arm/Kconfig.debug     2013-07-06 15:25:50.000000000 +0100
2042 @@ -519,6 +519,14 @@
2043                   For more details about semihosting, please see
2044                   chapter 8 of DUI0203I_rvct_developer_guide.pdf from ARM Ltd.
2045
2046 +       config DEBUG_BCM2708_UART0
2047 +               bool "Broadcom BCM2708 UART0 (PL011)"
2048 +               depends on MACH_BCM2708
2049 +               help
2050 +                 Say Y here if you want the debug print routines to direct
2051 +                 their output to UART 0. The port must have been initialised
2052 +                 by the boot-loader before use.
2053 +
2054  endchoice
2055
2056  config DEBUG_EXYNOS_UART
2057 diff -urN linux-3.10/arch/arm/kernel/armksyms.c linux-rpi-3.10.y/arch/arm/kernel/armksyms.c
2058 --- linux-3.10/arch/arm/kernel/armksyms.c       2013-06-30 23:13:29.000000000 +0100
2059 +++ linux-rpi-3.10.y/arch/arm/kernel/armksyms.c 2013-07-06 15:25:50.000000000 +0100
2060 @@ -156,3 +156,7 @@
2061  #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
2062  EXPORT_SYMBOL(__pv_phys_offset);
2063  #endif
2064 +
2065 +extern void v6wbi_flush_kern_tlb_range(void);
2066 +EXPORT_SYMBOL(v6wbi_flush_kern_tlb_range);
2067 +
2068 diff -urN linux-3.10/arch/arm/kernel/fiqasm.S linux-rpi-3.10.y/arch/arm/kernel/fiqasm.S
2069 --- linux-3.10/arch/arm/kernel/fiqasm.S 2013-06-30 23:13:29.000000000 +0100
2070 +++ linux-rpi-3.10.y/arch/arm/kernel/fiqasm.S   2013-07-06 15:25:50.000000000 +0100
2071 @@ -25,6 +25,9 @@
2072  ENTRY(__set_fiq_regs)
2073         mov     r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
2074         mrs     r1, cpsr
2075 +@@@@@@@@@@@@@@@ hack: enable the fiq here to keep usb driver happy
2076 +       and     r1, #~PSR_F_BIT
2077 +@@@@@@@@@@@@@@@ endhack: (need to find better place for this to happen)
2078         msr     cpsr_c, r2      @ select FIQ mode
2079         mov     r0, r0          @ avoid hazard prior to ARMv4
2080         ldmia   r0!, {r8 - r12}
2081 @@ -47,3 +50,7 @@
2082         mov     r0, r0          @ avoid hazard prior to ARMv4
2083         mov     pc, lr
2084  ENDPROC(__get_fiq_regs)
2085 +
2086 +ENTRY(__FIQ_Branch)
2087 +       mov pc, r8
2088 +ENDPROC(__FIQ_Branch)
2089 diff -urN linux-3.10/arch/arm/kernel/fiq.c linux-rpi-3.10.y/arch/arm/kernel/fiq.c
2090 --- linux-3.10/arch/arm/kernel/fiq.c    2013-06-30 23:13:29.000000000 +0100
2091 +++ linux-rpi-3.10.y/arch/arm/kernel/fiq.c      2013-07-06 15:25:50.000000000 +0100
2092 @@ -137,6 +137,7 @@
2093  EXPORT_SYMBOL(set_fiq_handler);
2094  EXPORT_SYMBOL(__set_fiq_regs); /* defined in fiqasm.S */
2095  EXPORT_SYMBOL(__get_fiq_regs); /* defined in fiqasm.S */
2096 +EXPORT_SYMBOL(__FIQ_Branch);   /* defined in fiqasm.S */
2097  EXPORT_SYMBOL(claim_fiq);
2098  EXPORT_SYMBOL(release_fiq);
2099  EXPORT_SYMBOL(enable_fiq);
2100 diff -urN linux-3.10/arch/arm/mach-bcm2708/armctrl.c linux-rpi-3.10.y/arch/arm/mach-bcm2708/armctrl.c
2101 --- linux-3.10/arch/arm/mach-bcm2708/armctrl.c  1970-01-01 01:00:00.000000000 +0100
2102 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/armctrl.c    2013-07-06 15:25:50.000000000 +0100
2103 @@ -0,0 +1,219 @@
2104 +/*
2105 + *  linux/arch/arm/mach-bcm2708/armctrl.c
2106 + *
2107 + *  Copyright (C) 2010 Broadcom
2108 + *
2109 + * This program is free software; you can redistribute it and/or modify
2110 + * it under the terms of the GNU General Public License as published by
2111 + * the Free Software Foundation; either version 2 of the License, or
2112 + * (at your option) any later version.
2113 + *
2114 + * This program is distributed in the hope that it will be useful,
2115 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2116 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2117 + * GNU General Public License for more details.
2118 + *
2119 + * You should have received a copy of the GNU General Public License
2120 + * along with this program; if not, write to the Free Software
2121 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2122 + */
2123 +#include <linux/init.h>
2124 +#include <linux/list.h>
2125 +#include <linux/io.h>
2126 +#include <linux/version.h>
2127 +#include <linux/syscore_ops.h>
2128 +#include <linux/interrupt.h>
2129 +
2130 +#include <asm/mach/irq.h>
2131 +#include <mach/hardware.h>
2132 +#include "armctrl.h"
2133 +
2134 +/* For support of kernels >= 3.0 assume only one VIC for now*/
2135 +static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
2136 +       INTERRUPT_VC_JPEG,
2137 +       INTERRUPT_VC_USB,
2138 +       INTERRUPT_VC_3D,
2139 +       INTERRUPT_VC_DMA2,
2140 +       INTERRUPT_VC_DMA3,
2141 +       INTERRUPT_VC_I2C,
2142 +       INTERRUPT_VC_SPI,
2143 +       INTERRUPT_VC_I2SPCM,
2144 +       INTERRUPT_VC_SDIO,
2145 +       INTERRUPT_VC_UART,
2146 +       INTERRUPT_VC_ARASANSDIO
2147 +};
2148 +
2149 +static void armctrl_mask_irq(struct irq_data *d)
2150 +{
2151 +       static const unsigned int disables[4] = {
2152 +               ARM_IRQ_DIBL1,
2153 +               ARM_IRQ_DIBL2,
2154 +               ARM_IRQ_DIBL3,
2155 +               0
2156 +       };
2157 +
2158 +       if (d->irq >= FIQ_START) {
2159 +               writel(0, __io_address(ARM_IRQ_FAST));
2160 +       } else {
2161 +               unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
2162 +               writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
2163 +       }
2164 +}
2165 +
2166 +static void armctrl_unmask_irq(struct irq_data *d)
2167 +{
2168 +       static const unsigned int enables[4] = {
2169 +               ARM_IRQ_ENBL1,
2170 +               ARM_IRQ_ENBL2,
2171 +               ARM_IRQ_ENBL3,
2172 +               0
2173 +       };
2174 +
2175 +       if (d->irq >= FIQ_START) {
2176 +               unsigned int data =
2177 +                   (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
2178 +               writel(0x80 | data, __io_address(ARM_IRQ_FAST));
2179 +       } else {
2180 +               unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
2181 +               writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
2182 +       }
2183 +}
2184 +
2185 +#if defined(CONFIG_PM)
2186 +
2187 +/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
2188 +
2189 +/* Static defines
2190 + * struct armctrl_device - VIC PM device (< 3.xx)
2191 + * @sysdev: The system device which is registered. (< 3.xx)
2192 + * @irq: The IRQ number for the base of the VIC.
2193 + * @base: The register base for the VIC.
2194 + * @resume_sources: A bitmask of interrupts for resume.
2195 + * @resume_irqs: The IRQs enabled for resume.
2196 + * @int_select: Save for VIC_INT_SELECT.
2197 + * @int_enable: Save for VIC_INT_ENABLE.
2198 + * @soft_int: Save for VIC_INT_SOFT.
2199 + * @protect: Save for VIC_PROTECT.
2200 + */
2201 +struct armctrl_info {
2202 +       void __iomem *base;
2203 +       int irq;
2204 +       u32 resume_sources;
2205 +       u32 resume_irqs;
2206 +       u32 int_select;
2207 +       u32 int_enable;
2208 +       u32 soft_int;
2209 +       u32 protect;
2210 +} armctrl;
2211 +
2212 +static int armctrl_suspend(void)
2213 +{
2214 +       return 0;
2215 +}
2216 +
2217 +static void armctrl_resume(void)
2218 +{
2219 +       return;
2220 +}
2221 +
2222 +/**
2223 + * armctrl_pm_register - Register a VIC for later power management control
2224 + * @base: The base address of the VIC.
2225 + * @irq: The base IRQ for the VIC.
2226 + * @resume_sources: bitmask of interrupts allowed for resume sources.
2227 + *
2228 + * For older kernels (< 3.xx) do -
2229 + * Register the VIC with the system device tree so that it can be notified
2230 + * of suspend and resume requests and ensure that the correct actions are
2231 + * taken to re-instate the settings on resume.
2232 + */
2233 +static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
2234 +                                      u32 resume_sources)
2235 +{
2236 +       armctrl.base = base;
2237 +       armctrl.resume_sources = resume_sources;
2238 +       armctrl.irq = irq;
2239 +}
2240 +
2241 +static int armctrl_set_wake(struct irq_data *d, unsigned int on)
2242 +{
2243 +       unsigned int off = d->irq & 31;
2244 +       u32 bit = 1 << off;
2245 +
2246 +       if (!(bit & armctrl.resume_sources))
2247 +               return -EINVAL;
2248 +
2249 +       if (on)
2250 +               armctrl.resume_irqs |= bit;
2251 +       else
2252 +               armctrl.resume_irqs &= ~bit;
2253 +
2254 +       return 0;
2255 +}
2256 +
2257 +#else
2258 +static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
2259 +                                      u32 arg1)
2260 +{
2261 +}
2262 +
2263 +#define armctrl_suspend NULL
2264 +#define armctrl_resume NULL
2265 +#define armctrl_set_wake NULL
2266 +#endif /* CONFIG_PM */
2267 +
2268 +static struct syscore_ops armctrl_syscore_ops = {
2269 +       .suspend = armctrl_suspend,
2270 +       .resume = armctrl_resume,
2271 +};
2272 +
2273 +/**
2274 + * armctrl_syscore_init - initicall to register VIC pm functions
2275 + *
2276 + * This is called via late_initcall() to register
2277 + * the resources for the VICs due to the early
2278 + * nature of the VIC's registration.
2279 +*/
2280 +static int __init armctrl_syscore_init(void)
2281 +{
2282 +       register_syscore_ops(&armctrl_syscore_ops);
2283 +       return 0;
2284 +}
2285 +
2286 +late_initcall(armctrl_syscore_init);
2287 +
2288 +static struct irq_chip armctrl_chip = {
2289 +       .name = "ARMCTRL",
2290 +       .irq_ack = armctrl_mask_irq,
2291 +       .irq_mask = armctrl_mask_irq,
2292 +       .irq_unmask = armctrl_unmask_irq,
2293 +       .irq_set_wake = armctrl_set_wake,
2294 +};
2295 +
2296 +/**
2297 + * armctrl_init - initialise a vectored interrupt controller
2298 + * @base: iomem base address
2299 + * @irq_start: starting interrupt number, must be muliple of 32
2300 + * @armctrl_sources: bitmask of interrupt sources to allow
2301 + * @resume_sources: bitmask of interrupt sources to allow for resume
2302 + */
2303 +int __init armctrl_init(void __iomem * base, unsigned int irq_start,
2304 +                       u32 armctrl_sources, u32 resume_sources)
2305 +{
2306 +       unsigned int irq;
2307 +
2308 +       for (irq = 0; irq < NR_IRQS; irq++) {
2309 +               unsigned int data = irq;
2310 +               if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
2311 +                       data = remap_irqs[irq - INTERRUPT_JPEG];
2312 +
2313 +               irq_set_chip(irq, &armctrl_chip);
2314 +               irq_set_chip_data(irq, (void *)data);
2315 +               irq_set_handler(irq, handle_level_irq);
2316 +               set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED);
2317 +       }
2318 +
2319 +       armctrl_pm_register(base, irq_start, resume_sources);
2320 +       init_FIQ(FIQ_START);
2321 +       return 0;
2322 +}
2323 diff -urN linux-3.10/arch/arm/mach-bcm2708/armctrl.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/armctrl.h
2324 --- linux-3.10/arch/arm/mach-bcm2708/armctrl.h  1970-01-01 01:00:00.000000000 +0100
2325 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/armctrl.h    2013-07-06 15:25:50.000000000 +0100
2326 @@ -0,0 +1,27 @@
2327 +/*
2328 + *  linux/arch/arm/mach-bcm2708/armctrl.h
2329 + *
2330 + *  Copyright (C) 2010 Broadcom
2331 + *
2332 + * This program is free software; you can redistribute it and/or modify
2333 + * it under the terms of the GNU General Public License as published by
2334 + * the Free Software Foundation; either version 2 of the License, or
2335 + * (at your option) any later version.
2336 + *
2337 + * This program is distributed in the hope that it will be useful,
2338 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2339 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2340 + * GNU General Public License for more details.
2341 + *
2342 + * You should have received a copy of the GNU General Public License
2343 + * along with this program; if not, write to the Free Software
2344 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2345 + */
2346 +
2347 +#ifndef __BCM2708_ARMCTRL_H
2348 +#define __BCM2708_ARMCTRL_H
2349 +
2350 +extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
2351 +                              u32 armctrl_sources, u32 resume_sources);
2352 +
2353 +#endif
2354 diff -urN linux-3.10/arch/arm/mach-bcm2708/bcm2708.c linux-rpi-3.10.y/arch/arm/mach-bcm2708/bcm2708.c
2355 --- linux-3.10/arch/arm/mach-bcm2708/bcm2708.c  1970-01-01 01:00:00.000000000 +0100
2356 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/bcm2708.c    2013-07-06 15:25:50.000000000 +0100
2357 @@ -0,0 +1,885 @@
2358 +/*
2359 + *  linux/arch/arm/mach-bcm2708/bcm2708.c
2360 + *
2361 + *  Copyright (C) 2010 Broadcom
2362 + *
2363 + * This program is free software; you can redistribute it and/or modify
2364 + * it under the terms of the GNU General Public License as published by
2365 + * the Free Software Foundation; either version 2 of the License, or
2366 + * (at your option) any later version.
2367 + *
2368 + * This program is distributed in the hope that it will be useful,
2369 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2370 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2371 + * GNU General Public License for more details.
2372 + *
2373 + * You should have received a copy of the GNU General Public License
2374 + * along with this program; if not, write to the Free Software
2375 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2376 + */
2377 +
2378 +#include <linux/init.h>
2379 +#include <linux/device.h>
2380 +#include <linux/dma-mapping.h>
2381 +#include <linux/serial_8250.h>
2382 +#include <linux/platform_device.h>
2383 +#include <linux/syscore_ops.h>
2384 +#include <linux/interrupt.h>
2385 +#include <linux/amba/bus.h>
2386 +#include <linux/amba/clcd.h>
2387 +#include <linux/clockchips.h>
2388 +#include <linux/cnt32_to_63.h>
2389 +#include <linux/io.h>
2390 +#include <linux/module.h>
2391 +#include <linux/spi/spi.h>
2392 +#include <linux/w1-gpio.h>
2393 +
2394 +#include <linux/version.h>
2395 +#include <linux/clkdev.h>
2396 +#include <asm/system.h>
2397 +#include <mach/hardware.h>
2398 +#include <asm/irq.h>
2399 +#include <linux/leds.h>
2400 +#include <asm/mach-types.h>
2401 +#include <asm/sched_clock.h>
2402 +
2403 +#include <asm/mach/arch.h>
2404 +#include <asm/mach/flash.h>
2405 +#include <asm/mach/irq.h>
2406 +#include <asm/mach/time.h>
2407 +#include <asm/mach/map.h>
2408 +
2409 +#include <mach/timex.h>
2410 +#include <mach/dma.h>
2411 +#include <mach/vcio.h>
2412 +#include <mach/system.h>
2413 +
2414 +#include <linux/delay.h>
2415 +
2416 +#include "bcm2708.h"
2417 +#include "armctrl.h"
2418 +#include "clock.h"
2419 +
2420 +#ifdef CONFIG_BCM_VC_CMA
2421 +#include <linux/broadcom/vc_cma.h>
2422 +#endif
2423 +
2424 +
2425 +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
2426 + * give us IO access only to 64Mbytes of physical memory (26 bits).  We could
2427 + * represent this window by setting our dmamasks to 26 bits but, in fact
2428 + * we're not going to use addresses outside this range (they're not in real
2429 + * memory) so we don't bother.
2430 + *
2431 + * In the future we might include code to use this IOMMU to remap other
2432 + * physical addresses onto VideoCore memory then the use of 32-bits would be
2433 + * more legitimate.
2434 + */
2435 +#define DMA_MASK_BITS_COMMON 32
2436 +
2437 +// use GPIO 4 for the one-wire GPIO pin, if enabled
2438 +#define W1_GPIO 4
2439 +
2440 +/* command line parameters */
2441 +static unsigned boardrev, serial;
2442 +static unsigned uart_clock;
2443 +
2444 +static void __init bcm2708_init_led(void);
2445 +
2446 +void __init bcm2708_init_irq(void)
2447 +{
2448 +       armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
2449 +}
2450 +
2451 +static struct map_desc bcm2708_io_desc[] __initdata = {
2452 +       {
2453 +        .virtual = IO_ADDRESS(ARMCTRL_BASE),
2454 +        .pfn = __phys_to_pfn(ARMCTRL_BASE),
2455 +        .length = SZ_4K,
2456 +        .type = MT_DEVICE},
2457 +       {
2458 +        .virtual = IO_ADDRESS(UART0_BASE),
2459 +        .pfn = __phys_to_pfn(UART0_BASE),
2460 +        .length = SZ_4K,
2461 +        .type = MT_DEVICE},
2462 +       {
2463 +        .virtual = IO_ADDRESS(UART1_BASE),
2464 +        .pfn = __phys_to_pfn(UART1_BASE),
2465 +        .length = SZ_4K,
2466 +        .type = MT_DEVICE},
2467 +       {
2468 +        .virtual = IO_ADDRESS(DMA_BASE),
2469 +        .pfn = __phys_to_pfn(DMA_BASE),
2470 +        .length = SZ_4K,
2471 +        .type = MT_DEVICE},
2472 +       {
2473 +        .virtual = IO_ADDRESS(MCORE_BASE),
2474 +        .pfn = __phys_to_pfn(MCORE_BASE),
2475 +        .length = SZ_4K,
2476 +        .type = MT_DEVICE},
2477 +       {
2478 +        .virtual = IO_ADDRESS(ST_BASE),
2479 +        .pfn = __phys_to_pfn(ST_BASE),
2480 +        .length = SZ_4K,
2481 +        .type = MT_DEVICE},
2482 +       {
2483 +        .virtual = IO_ADDRESS(USB_BASE),
2484 +        .pfn = __phys_to_pfn(USB_BASE),
2485 +        .length = SZ_128K,
2486 +        .type = MT_DEVICE},
2487 +       {
2488 +        .virtual = IO_ADDRESS(PM_BASE),
2489 +        .pfn = __phys_to_pfn(PM_BASE),
2490 +        .length = SZ_4K,
2491 +        .type = MT_DEVICE},
2492 +       {
2493 +        .virtual = IO_ADDRESS(GPIO_BASE),
2494 +        .pfn = __phys_to_pfn(GPIO_BASE),
2495 +        .length = SZ_4K,
2496 +        .type = MT_DEVICE}
2497 +};
2498 +
2499 +void __init bcm2708_map_io(void)
2500 +{
2501 +       iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
2502 +}
2503 +
2504 +/* The STC is a free running counter that increments at the rate of 1MHz */
2505 +#define STC_FREQ_HZ 1000000
2506 +
2507 +static inline uint32_t timer_read(void)
2508 +{
2509 +       /* STC: a free running counter that increments at the rate of 1MHz */
2510 +       return readl(__io_address(ST_BASE + 0x04));
2511 +}
2512 +
2513 +static unsigned long bcm2708_read_current_timer(void)
2514 +{
2515 +       return timer_read();
2516 +}
2517 +
2518 +static u32 notrace bcm2708_read_sched_clock(void)
2519 +{
2520 +       return timer_read();
2521 +}
2522 +
2523 +static cycle_t clksrc_read(struct clocksource *cs)
2524 +{
2525 +       return timer_read();
2526 +}
2527 +
2528 +static struct clocksource clocksource_stc = {
2529 +       .name = "stc",
2530 +       .rating = 300,
2531 +       .read = clksrc_read,
2532 +       .mask = CLOCKSOURCE_MASK(32),
2533 +       .flags = CLOCK_SOURCE_IS_CONTINUOUS,
2534 +};
2535 +
2536 +unsigned long frc_clock_ticks32(void)
2537 +{
2538 +       return timer_read();
2539 +}
2540 +
2541 +static void __init bcm2708_clocksource_init(void)
2542 +{
2543 +       if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
2544 +               printk(KERN_ERR "timer: failed to initialize clock "
2545 +                      "source %s\n", clocksource_stc.name);
2546 +       }
2547 +}
2548 +
2549 +
2550 +/*
2551 + * These are fixed clocks.
2552 + */
2553 +static struct clk ref24_clk = {
2554 +       .rate = UART0_CLOCK,    /* The UART is clocked at 3MHz via APB_CLK */
2555 +};
2556 +
2557 +static struct clk osc_clk = {
2558 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
2559 +       .rate = 27000000,
2560 +#else
2561 +       .rate = 500000000,      /* ARM clock is set from the VideoCore booter */
2562 +#endif
2563 +};
2564 +
2565 +/* warning - the USB needs a clock > 34MHz */
2566 +
2567 +static struct clk sdhost_clk = {
2568 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
2569 +       .rate = 4000000,        /* 4MHz */
2570 +#else
2571 +       .rate = 250000000,      /* 250MHz */
2572 +#endif
2573 +};
2574 +
2575 +static struct clk_lookup lookups[] = {
2576 +       {                       /* UART0 */
2577 +        .dev_id = "dev:f1",
2578 +        .clk = &ref24_clk,
2579 +        },
2580 +       {                       /* USB */
2581 +        .dev_id = "bcm2708_usb",
2582 +        .clk = &osc_clk,
2583 +        }, {   /* SPI */
2584 +                .dev_id = "bcm2708_spi.0",
2585 +                .clk = &sdhost_clk,
2586 +        }, {   /* BSC0 */
2587 +                .dev_id = "bcm2708_i2c.0",
2588 +                .clk = &sdhost_clk,
2589 +        }, {   /* BSC1 */
2590 +                .dev_id = "bcm2708_i2c.1",
2591 +                .clk = &sdhost_clk,
2592 +        }
2593 +};
2594 +
2595 +#define UART0_IRQ      { IRQ_UART, 0 /*NO_IRQ*/ }
2596 +#define UART0_DMA      { 15, 14 }
2597 +
2598 +AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
2599 +
2600 +static struct amba_device *amba_devs[] __initdata = {
2601 +       &uart0_device,
2602 +};
2603 +
2604 +static struct resource bcm2708_dmaman_resources[] = {
2605 +       {
2606 +        .start = DMA_BASE,
2607 +        .end = DMA_BASE + SZ_4K - 1,
2608 +        .flags = IORESOURCE_MEM,
2609 +        }
2610 +};
2611 +
2612 +static struct platform_device bcm2708_dmaman_device = {
2613 +       .name = BCM_DMAMAN_DRIVER_NAME,
2614 +       .id = 0,                /* first bcm2708_dma */
2615 +       .resource = bcm2708_dmaman_resources,
2616 +       .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources),
2617 +};
2618 +
2619 +#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
2620 +static struct w1_gpio_platform_data w1_gpio_pdata = {
2621 +       .pin = W1_GPIO,
2622 +       .is_open_drain = 0,
2623 +};
2624 +
2625 +static struct platform_device w1_device = {
2626 +       .name = "w1-gpio",
2627 +       .id = -1,
2628 +       .dev.platform_data = &w1_gpio_pdata,
2629 +};
2630 +#endif
2631 +
2632 +static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2633 +
2634 +static struct platform_device bcm2708_fb_device = {
2635 +       .name = "bcm2708_fb",
2636 +       .id = -1,               /* only one bcm2708_fb */
2637 +       .resource = NULL,
2638 +       .num_resources = 0,
2639 +       .dev = {
2640 +               .dma_mask = &fb_dmamask,
2641 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2642 +               },
2643 +};
2644 +
2645 +static struct plat_serial8250_port bcm2708_uart1_platform_data[] = {
2646 +       {
2647 +        .mapbase = UART1_BASE + 0x40,
2648 +        .irq = IRQ_AUX,
2649 +        .uartclk = 125000000,
2650 +        .regshift = 2,
2651 +        .iotype = UPIO_MEM,
2652 +        .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST,
2653 +        .type = PORT_8250,
2654 +        },
2655 +       {},
2656 +};
2657 +
2658 +static struct platform_device bcm2708_uart1_device = {
2659 +       .name = "serial8250",
2660 +       .id = PLAT8250_DEV_PLATFORM,
2661 +       .dev = {
2662 +               .platform_data = bcm2708_uart1_platform_data,
2663 +               },
2664 +};
2665 +
2666 +static struct resource bcm2708_usb_resources[] = {
2667 +       [0] = {
2668 +              .start = USB_BASE,
2669 +              .end = USB_BASE + SZ_128K - 1,
2670 +              .flags = IORESOURCE_MEM,
2671 +              },
2672 +       [1] = {
2673 +               .start = MPHI_BASE,
2674 +               .end = MPHI_BASE + SZ_4K - 1,
2675 +               .flags = IORESOURCE_MEM,
2676 +             },
2677 +       [2] = {
2678 +              .start = IRQ_HOSTPORT,
2679 +              .end = IRQ_HOSTPORT,
2680 +              .flags = IORESOURCE_IRQ,
2681 +              },
2682 +};
2683 +
2684 +bool fiq_fix_enable = true;
2685 +
2686 +static struct resource bcm2708_usb_resources_no_fiq_fix[] = {
2687 +       [0] = {
2688 +               .start = USB_BASE,
2689 +               .end = USB_BASE + SZ_128K - 1,
2690 +               .flags = IORESOURCE_MEM,
2691 +               },
2692 +       [1] = {
2693 +               .start = IRQ_USB,
2694 +               .end = IRQ_USB,
2695 +               .flags = IORESOURCE_IRQ,
2696 +               },
2697 +};
2698 +
2699 +static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2700 +
2701 +static struct platform_device bcm2708_usb_device = {
2702 +       .name = "bcm2708_usb",
2703 +       .id = -1,               /* only one bcm2708_usb */
2704 +       .resource = bcm2708_usb_resources,
2705 +       .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
2706 +       .dev = {
2707 +               .dma_mask = &usb_dmamask,
2708 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2709 +               },
2710 +};
2711 +
2712 +static struct resource bcm2708_vcio_resources[] = {
2713 +       [0] = {                 /* mailbox/semaphore/doorbell access */
2714 +              .start = MCORE_BASE,
2715 +              .end = MCORE_BASE + SZ_4K - 1,
2716 +              .flags = IORESOURCE_MEM,
2717 +              },
2718 +};
2719 +
2720 +static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2721 +
2722 +static struct platform_device bcm2708_vcio_device = {
2723 +       .name = BCM_VCIO_DRIVER_NAME,
2724 +       .id = -1,               /* only one VideoCore I/O area */
2725 +       .resource = bcm2708_vcio_resources,
2726 +       .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
2727 +       .dev = {
2728 +               .dma_mask = &vcio_dmamask,
2729 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2730 +               },
2731 +};
2732 +
2733 +#ifdef CONFIG_BCM2708_GPIO
2734 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
2735 +
2736 +static struct resource bcm2708_gpio_resources[] = {
2737 +       [0] = {                 /* general purpose I/O */
2738 +              .start = GPIO_BASE,
2739 +              .end = GPIO_BASE + SZ_4K - 1,
2740 +              .flags = IORESOURCE_MEM,
2741 +              },
2742 +};
2743 +
2744 +static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2745 +
2746 +static struct platform_device bcm2708_gpio_device = {
2747 +       .name = BCM_GPIO_DRIVER_NAME,
2748 +       .id = -1,               /* only one VideoCore I/O area */
2749 +       .resource = bcm2708_gpio_resources,
2750 +       .num_resources = ARRAY_SIZE(bcm2708_gpio_resources),
2751 +       .dev = {
2752 +               .dma_mask = &gpio_dmamask,
2753 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2754 +               },
2755 +};
2756 +#endif
2757 +
2758 +static struct resource bcm2708_systemtimer_resources[] = {
2759 +       [0] = {                 /* system timer access */
2760 +              .start = ST_BASE,
2761 +              .end = ST_BASE + SZ_4K - 1,
2762 +              .flags = IORESOURCE_MEM,
2763 +              },
2764 +       {
2765 +        .start = IRQ_TIMER3,
2766 +        .end = IRQ_TIMER3,
2767 +        .flags = IORESOURCE_IRQ,
2768 +        }
2769 +
2770 +};
2771 +
2772 +static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2773 +
2774 +static struct platform_device bcm2708_systemtimer_device = {
2775 +       .name = "bcm2708_systemtimer",
2776 +       .id = -1,               /* only one VideoCore I/O area */
2777 +       .resource = bcm2708_systemtimer_resources,
2778 +       .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources),
2779 +       .dev = {
2780 +               .dma_mask = &systemtimer_dmamask,
2781 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2782 +               },
2783 +};
2784 +
2785 +#ifdef CONFIG_MMC_SDHCI_BCM2708        /* Arasan emmc SD */
2786 +static struct resource bcm2708_emmc_resources[] = {
2787 +       [0] = {
2788 +              .start = EMMC_BASE,
2789 +              .end = EMMC_BASE + SZ_256 - 1,   /* we only need this area */
2790 +              /* the memory map actually makes SZ_4K available  */
2791 +              .flags = IORESOURCE_MEM,
2792 +              },
2793 +       [1] = {
2794 +              .start = IRQ_ARASANSDIO,
2795 +              .end = IRQ_ARASANSDIO,
2796 +              .flags = IORESOURCE_IRQ,
2797 +              },
2798 +};
2799 +
2800 +static u64 bcm2708_emmc_dmamask = 0xffffffffUL;
2801 +
2802 +struct platform_device bcm2708_emmc_device = {
2803 +       .name = "bcm2708_sdhci",
2804 +       .id = 0,
2805 +       .num_resources = ARRAY_SIZE(bcm2708_emmc_resources),
2806 +       .resource = bcm2708_emmc_resources,
2807 +       .dev = {
2808 +               .dma_mask = &bcm2708_emmc_dmamask,
2809 +               .coherent_dma_mask = 0xffffffffUL},
2810 +};
2811 +#endif /* CONFIG_MMC_SDHCI_BCM2708 */
2812 +
2813 +static struct resource bcm2708_powerman_resources[] = {
2814 +       [0] = {
2815 +              .start = PM_BASE,
2816 +              .end = PM_BASE + SZ_256 - 1,
2817 +              .flags = IORESOURCE_MEM,
2818 +              },
2819 +};
2820 +
2821 +static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2822 +
2823 +struct platform_device bcm2708_powerman_device = {
2824 +       .name = "bcm2708_powerman",
2825 +       .id = 0,
2826 +       .num_resources = ARRAY_SIZE(bcm2708_powerman_resources),
2827 +       .resource = bcm2708_powerman_resources,
2828 +       .dev = {
2829 +               .dma_mask = &powerman_dmamask,
2830 +               .coherent_dma_mask = 0xffffffffUL},
2831 +};
2832 +
2833 +
2834 +static struct platform_device bcm2708_alsa_devices[] = {
2835 +       [0] = {
2836 +              .name = "bcm2835_AUD0",
2837 +              .id = 0,         /* first audio device */
2838 +              .resource = 0,
2839 +              .num_resources = 0,
2840 +              },
2841 +       [1] = {
2842 +              .name = "bcm2835_AUD1",
2843 +              .id = 1,         /* second audio device */
2844 +              .resource = 0,
2845 +              .num_resources = 0,
2846 +              },
2847 +       [2] = {
2848 +              .name = "bcm2835_AUD2",
2849 +              .id = 2,         /* third audio device */
2850 +              .resource = 0,
2851 +              .num_resources = 0,
2852 +              },
2853 +       [3] = {
2854 +              .name = "bcm2835_AUD3",
2855 +              .id = 3,         /* forth audio device */
2856 +              .resource = 0,
2857 +              .num_resources = 0,
2858 +              },
2859 +       [4] = {
2860 +              .name = "bcm2835_AUD4",
2861 +              .id = 4,         /* fifth audio device */
2862 +              .resource = 0,
2863 +              .num_resources = 0,
2864 +              },
2865 +       [5] = {
2866 +              .name = "bcm2835_AUD5",
2867 +              .id = 5,         /* sixth audio device */
2868 +              .resource = 0,
2869 +              .num_resources = 0,
2870 +              },
2871 +       [6] = {
2872 +              .name = "bcm2835_AUD6",
2873 +              .id = 6,         /* seventh audio device */
2874 +              .resource = 0,
2875 +              .num_resources = 0,
2876 +              },
2877 +       [7] = {
2878 +              .name = "bcm2835_AUD7",
2879 +              .id = 7,         /* eighth audio device */
2880 +              .resource = 0,
2881 +              .num_resources = 0,
2882 +              },
2883 +};
2884 +
2885 +static struct resource bcm2708_spi_resources[] = {
2886 +       {
2887 +               .start = SPI0_BASE,
2888 +               .end = SPI0_BASE + SZ_256 - 1,
2889 +               .flags = IORESOURCE_MEM,
2890 +       }, {
2891 +               .start = IRQ_SPI,
2892 +               .end = IRQ_SPI,
2893 +               .flags = IORESOURCE_IRQ,
2894 +       }
2895 +};
2896 +
2897 +
2898 +static struct platform_device bcm2708_spi_device = {
2899 +       .name = "bcm2708_spi",
2900 +       .id = 0,
2901 +       .num_resources = ARRAY_SIZE(bcm2708_spi_resources),
2902 +       .resource = bcm2708_spi_resources,
2903 +};
2904 +
2905 +#ifdef CONFIG_BCM2708_SPIDEV
2906 +static struct spi_board_info bcm2708_spi_devices[] = {
2907 +#ifdef CONFIG_SPI_SPIDEV
2908 +       {
2909 +               .modalias = "spidev",
2910 +               .max_speed_hz = 500000,
2911 +               .bus_num = 0,
2912 +               .chip_select = 0,
2913 +               .mode = SPI_MODE_0,
2914 +       }, {
2915 +               .modalias = "spidev",
2916 +               .max_speed_hz = 500000,
2917 +               .bus_num = 0,
2918 +               .chip_select = 1,
2919 +               .mode = SPI_MODE_0,
2920 +       }
2921 +#endif
2922 +};
2923 +#endif
2924 +
2925 +static struct resource bcm2708_bsc0_resources[] = {
2926 +       {
2927 +               .start = BSC0_BASE,
2928 +               .end = BSC0_BASE + SZ_256 - 1,
2929 +               .flags = IORESOURCE_MEM,
2930 +       }, {
2931 +               .start = INTERRUPT_I2C,
2932 +               .end = INTERRUPT_I2C,
2933 +               .flags = IORESOURCE_IRQ,
2934 +       }
2935 +};
2936 +
2937 +static struct platform_device bcm2708_bsc0_device = {
2938 +       .name = "bcm2708_i2c",
2939 +       .id = 0,
2940 +       .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources),
2941 +       .resource = bcm2708_bsc0_resources,
2942 +};
2943 +
2944 +
2945 +static struct resource bcm2708_bsc1_resources[] = {
2946 +       {
2947 +               .start = BSC1_BASE,
2948 +               .end = BSC1_BASE + SZ_256 - 1,
2949 +               .flags = IORESOURCE_MEM,
2950 +       }, {
2951 +               .start = INTERRUPT_I2C,
2952 +               .end = INTERRUPT_I2C,
2953 +               .flags = IORESOURCE_IRQ,
2954 +       }
2955 +};
2956 +
2957 +static struct platform_device bcm2708_bsc1_device = {
2958 +       .name = "bcm2708_i2c",
2959 +       .id = 1,
2960 +       .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources),
2961 +       .resource = bcm2708_bsc1_resources,
2962 +};
2963 +
2964 +static struct platform_device bcm2835_hwmon_device = {
2965 +       .name = "bcm2835_hwmon",
2966 +};
2967 +
2968 +static struct platform_device bcm2835_thermal_device = {
2969 +       .name = "bcm2835_thermal",
2970 +};
2971 +
2972 +int __init bcm_register_device(struct platform_device *pdev)
2973 +{
2974 +       int ret;
2975 +
2976 +       ret = platform_device_register(pdev);
2977 +       if (ret)
2978 +               pr_debug("Unable to register platform device '%s': %d\n",
2979 +                        pdev->name, ret);
2980 +
2981 +       return ret;
2982 +}
2983 +
2984 +static void bcm2708_restart(char mode, const char *cmd)
2985 +{
2986 +       uint32_t pm_rstc, pm_wdog;
2987 +       uint32_t timeout = 10;
2988 +
2989 +       /* For quick reset notification add reboot=q to cmdline
2990 +        */
2991 +       if(mode == 'q')
2992 +       {
2993 +               uint32_t pm_rsts = readl(__io_address(PM_RSTS));
2994 +               pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
2995 +               writel(pm_rsts, __io_address(PM_RSTS));
2996 +       }
2997 +
2998 +       /* Setup watchdog for reset */
2999 +       pm_rstc = readl(__io_address(PM_RSTC));
3000 +
3001 +       pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
3002 +       pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
3003 +
3004 +       writel(pm_wdog, __io_address(PM_WDOG));
3005 +       writel(pm_rstc, __io_address(PM_RSTC));
3006 +}
3007 +
3008 +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
3009 +static void bcm2708_power_off(void)
3010 +{
3011 +       /* we set the watchdog hard reset bit here to distinguish this reset from the normal (full) reset. bootcode.bin will not reboot after a hard reset */
3012 +       uint32_t pm_rsts = readl(__io_address(PM_RSTS));
3013 +       pm_rsts = PM_PASSWORD | (pm_rsts & PM_RSTC_WRCFG_CLR) | PM_RSTS_HADWRH_SET;
3014 +       writel(pm_rsts, __io_address(PM_RSTS));
3015 +       /* continue with normal reset mechanism */
3016 +       bcm2708_restart(0, "");
3017 +}
3018 +
3019 +void __init bcm2708_init(void)
3020 +{
3021 +       int i;
3022 +
3023 +#if defined(CONFIG_BCM_VC_CMA)
3024 +       vc_cma_early_init();
3025 +#endif
3026 +       printk("bcm2708.uart_clock = %d\n", uart_clock);
3027 +       pm_power_off = bcm2708_power_off;
3028 +
3029 +       if (uart_clock)
3030 +               lookups[0].clk->rate = uart_clock;
3031 +
3032 +       for (i = 0; i < ARRAY_SIZE(lookups); i++)
3033 +               clkdev_add(&lookups[i]);
3034 +
3035 +       bcm_register_device(&bcm2708_dmaman_device);
3036 +       bcm_register_device(&bcm2708_vcio_device);
3037 +#ifdef CONFIG_BCM2708_GPIO
3038 +       bcm_register_device(&bcm2708_gpio_device);
3039 +#endif
3040 +#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
3041 +       platform_device_register(&w1_device);
3042 +#endif
3043 +       bcm_register_device(&bcm2708_systemtimer_device);
3044 +       bcm_register_device(&bcm2708_fb_device);
3045 +       if (!fiq_fix_enable)
3046 +       {
3047 +               bcm2708_usb_device.resource = bcm2708_usb_resources_no_fiq_fix;
3048 +               bcm2708_usb_device.num_resources = ARRAY_SIZE(bcm2708_usb_resources_no_fiq_fix);
3049 +       }
3050 +       bcm_register_device(&bcm2708_usb_device);
3051 +       bcm_register_device(&bcm2708_uart1_device);
3052 +       bcm_register_device(&bcm2708_powerman_device);
3053 +
3054 +#ifdef CONFIG_MMC_SDHCI_BCM2708
3055 +       bcm_register_device(&bcm2708_emmc_device);
3056 +#endif
3057 +       bcm2708_init_led();
3058 +       for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++)
3059 +               bcm_register_device(&bcm2708_alsa_devices[i]);
3060 +
3061 +       bcm_register_device(&bcm2708_spi_device);
3062 +       bcm_register_device(&bcm2708_bsc0_device);
3063 +       bcm_register_device(&bcm2708_bsc1_device);
3064 +
3065 +       bcm_register_device(&bcm2835_hwmon_device);
3066 +       bcm_register_device(&bcm2835_thermal_device);
3067 +
3068 +       for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
3069 +               struct amba_device *d = amba_devs[i];
3070 +               amba_device_register(d, &iomem_resource);
3071 +       }
3072 +       system_rev = boardrev;
3073 +       system_serial_low = serial;
3074 +
3075 +#ifdef CONFIG_BCM2708_SPIDEV
3076 +       spi_register_board_info(bcm2708_spi_devices,
3077 +                       ARRAY_SIZE(bcm2708_spi_devices));
3078 +#endif
3079 +}
3080 +
3081 +static void timer_set_mode(enum clock_event_mode mode,
3082 +                          struct clock_event_device *clk)
3083 +{
3084 +       switch (mode) {
3085 +       case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
3086 +       case CLOCK_EVT_MODE_SHUTDOWN:
3087 +               break;
3088 +       case CLOCK_EVT_MODE_PERIODIC:
3089 +
3090 +       case CLOCK_EVT_MODE_UNUSED:
3091 +       case CLOCK_EVT_MODE_RESUME:
3092 +
3093 +       default:
3094 +               printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
3095 +                      (int)mode);
3096 +               break;
3097 +       }
3098 +
3099 +}
3100 +
3101 +static int timer_set_next_event(unsigned long cycles,
3102 +                               struct clock_event_device *unused)
3103 +{
3104 +       unsigned long stc;
3105 +
3106 +       stc = readl(__io_address(ST_BASE + 0x04));
3107 +       writel(stc + cycles, __io_address(ST_BASE + 0x18));     /* stc3 */
3108 +       return 0;
3109 +}
3110 +
3111 +static struct clock_event_device timer0_clockevent = {
3112 +       .name = "timer0",
3113 +       .shift = 32,
3114 +       .features = CLOCK_EVT_FEAT_ONESHOT,
3115 +       .set_mode = timer_set_mode,
3116 +       .set_next_event = timer_set_next_event,
3117 +};
3118 +
3119 +/*
3120 + * IRQ handler for the timer
3121 + */
3122 +static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id)
3123 +{
3124 +       struct clock_event_device *evt = &timer0_clockevent;
3125 +
3126 +       writel(1 << 3, __io_address(ST_BASE + 0x00));   /* stcs clear timer int */
3127 +
3128 +       evt->event_handler(evt);
3129 +
3130 +       return IRQ_HANDLED;
3131 +}
3132 +
3133 +static struct irqaction bcm2708_timer_irq = {
3134 +       .name = "BCM2708 Timer Tick",
3135 +       .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
3136 +       .handler = bcm2708_timer_interrupt,
3137 +};
3138 +
3139 +/*
3140 + * Set up timer interrupt, and return the current time in seconds.
3141 + */
3142 +
3143 +static struct delay_timer bcm2708_delay_timer = {
3144 +       .read_current_timer = bcm2708_read_current_timer,
3145 +       .freq = STC_FREQ_HZ,
3146 +};
3147 +
3148 +static void __init bcm2708_timer_init(void)
3149 +{
3150 +       /* init high res timer */
3151 +       bcm2708_clocksource_init();
3152 +
3153 +       /*
3154 +        * Initialise to a known state (all timers off)
3155 +        */
3156 +       writel(0, __io_address(ARM_T_CONTROL));
3157 +       /*
3158 +        * Make irqs happen for the system timer
3159 +        */
3160 +       setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
3161 +
3162 +       setup_sched_clock(bcm2708_read_sched_clock, 32, STC_FREQ_HZ);
3163 +
3164 +       timer0_clockevent.mult =
3165 +           div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
3166 +       timer0_clockevent.max_delta_ns =
3167 +           clockevent_delta2ns(0xffffffff, &timer0_clockevent);
3168 +       timer0_clockevent.min_delta_ns =
3169 +           clockevent_delta2ns(0xf, &timer0_clockevent);
3170 +
3171 +       timer0_clockevent.cpumask = cpumask_of(0);
3172 +       clockevents_register_device(&timer0_clockevent);
3173 +
3174 +       register_current_timer_delay(&bcm2708_delay_timer);
3175 +}
3176 +
3177 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
3178 +#include <linux/leds.h>
3179 +
3180 +static struct gpio_led bcm2708_leds[] = {
3181 +       [0] = {
3182 +              .gpio = 16,
3183 +              .name = "led0",
3184 +              .default_trigger = "mmc0",
3185 +              .active_low = 1,
3186 +              },
3187 +};
3188 +
3189 +static struct gpio_led_platform_data bcm2708_led_pdata = {
3190 +       .num_leds = ARRAY_SIZE(bcm2708_leds),
3191 +       .leds = bcm2708_leds,
3192 +};
3193 +
3194 +static struct platform_device bcm2708_led_device = {
3195 +       .name = "leds-gpio",
3196 +       .id = -1,
3197 +       .dev = {
3198 +               .platform_data = &bcm2708_led_pdata,
3199 +               },
3200 +};
3201 +
3202 +static void __init bcm2708_init_led(void)
3203 +{
3204 +       platform_device_register(&bcm2708_led_device);
3205 +}
3206 +#else
3207 +static inline void bcm2708_init_led(void)
3208 +{
3209 +}
3210 +#endif
3211 +
3212 +void __init bcm2708_init_early(void)
3213 +{
3214 +       /*
3215 +        * Some devices allocate their coherent buffers from atomic
3216 +        * context. Increase size of atomic coherent pool to make sure such
3217 +        * the allocations won't fail.
3218 +        */
3219 +       init_dma_coherent_pool_size(SZ_4M);
3220 +}
3221 +
3222 +static void __init board_reserve(void)
3223 +{
3224 +#if defined(CONFIG_BCM_VC_CMA)
3225 +       vc_cma_reserve();
3226 +#endif
3227 +}
3228 +
3229 +MACHINE_START(BCM2708, "BCM2708")
3230 +    /* Maintainer: Broadcom Europe Ltd. */
3231 +       .map_io = bcm2708_map_io,
3232 +       .init_irq = bcm2708_init_irq,
3233 +       .init_time = bcm2708_timer_init,
3234 +       .init_machine = bcm2708_init,
3235 +       .init_early = bcm2708_init_early,
3236 +       .reserve = board_reserve,
3237 +       .restart        = bcm2708_restart,
3238 +MACHINE_END
3239 +
3240 +module_param(boardrev, uint, 0644);
3241 +module_param(serial, uint, 0644);
3242 +module_param(uart_clock, uint, 0644);
3243 diff -urN linux-3.10/arch/arm/mach-bcm2708/bcm2708_gpio.c linux-rpi-3.10.y/arch/arm/mach-bcm2708/bcm2708_gpio.c
3244 --- linux-3.10/arch/arm/mach-bcm2708/bcm2708_gpio.c     1970-01-01 01:00:00.000000000 +0100
3245 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/bcm2708_gpio.c       2013-07-06 15:25:50.000000000 +0100
3246 @@ -0,0 +1,339 @@
3247 +/*
3248 + *  linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
3249 + *
3250 + *  Copyright (C) 2010 Broadcom
3251 + *
3252 + * This program is free software; you can redistribute it and/or modify
3253 + * it under the terms of the GNU General Public License version 2 as
3254 + * published by the Free Software Foundation.
3255 + *
3256 + */
3257 +
3258 +#include <linux/spinlock.h>
3259 +#include <linux/module.h>
3260 +#include <linux/list.h>
3261 +#include <linux/io.h>
3262 +#include <linux/irq.h>
3263 +#include <linux/interrupt.h>
3264 +#include <linux/slab.h>
3265 +#include <mach/gpio.h>
3266 +#include <linux/gpio.h>
3267 +#include <linux/platform_device.h>
3268 +#include <mach/platform.h>
3269 +
3270 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
3271 +#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
3272 +#define BCM_GPIO_USE_IRQ 1
3273 +
3274 +#define GPIOFSEL(x)  (0x00+(x)*4)
3275 +#define GPIOSET(x)   (0x1c+(x)*4)
3276 +#define GPIOCLR(x)   (0x28+(x)*4)
3277 +#define GPIOLEV(x)   (0x34+(x)*4)
3278 +#define GPIOEDS(x)   (0x40+(x)*4)
3279 +#define GPIOREN(x)   (0x4c+(x)*4)
3280 +#define GPIOFEN(x)   (0x58+(x)*4)
3281 +#define GPIOHEN(x)   (0x64+(x)*4)
3282 +#define GPIOLEN(x)   (0x70+(x)*4)
3283 +#define GPIOAREN(x)  (0x7c+(x)*4)
3284 +#define GPIOAFEN(x)  (0x88+(x)*4)
3285 +#define GPIOUD(x)    (0x94+(x)*4)
3286 +#define GPIOUDCLK(x) (0x98+(x)*4)
3287 +
3288 +enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
3289 +       GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
3290 +       GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
3291 +       GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
3292 +};
3293 +
3294 +       /* Each of the two spinlocks protects a different set of hardware
3295 +        * regiters and data structurs. This decouples the code of the IRQ from
3296 +        * the GPIO code. This also makes the case of a GPIO routine call from
3297 +        * the IRQ code simpler.
3298 +        */
3299 +static DEFINE_SPINLOCK(lock);  /* GPIO registers */
3300 +
3301 +struct bcm2708_gpio {
3302 +       struct list_head list;
3303 +       void __iomem *base;
3304 +       struct gpio_chip gc;
3305 +       unsigned long rising;
3306 +       unsigned long falling;
3307 +};
3308 +
3309 +static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset,
3310 +                               int function)
3311 +{
3312 +       struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
3313 +       unsigned long flags;
3314 +       unsigned gpiodir;
3315 +       unsigned gpio_bank = offset / 10;
3316 +       unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
3317 +
3318 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
3319 +       if (offset >= ARCH_NR_GPIOS)
3320 +               return -EINVAL;
3321 +
3322 +       spin_lock_irqsave(&lock, flags);
3323 +
3324 +       gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
3325 +       gpiodir &= ~(7 << gpio_field_offset);
3326 +       gpiodir |= function << gpio_field_offset;
3327 +       writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
3328 +       spin_unlock_irqrestore(&lock, flags);
3329 +       gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
3330 +
3331 +       return 0;
3332 +}
3333 +
3334 +static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
3335 +{
3336 +       return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
3337 +}
3338 +
3339 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
3340 +static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
3341 +                               int value)
3342 +{
3343 +       int ret;
3344 +       ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
3345 +       if (ret >= 0)
3346 +               bcm2708_gpio_set(gc, offset, value);
3347 +       return ret;
3348 +}
3349 +
3350 +static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
3351 +{
3352 +       struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
3353 +       unsigned gpio_bank = offset / 32;
3354 +       unsigned gpio_field_offset = (offset - 32 * gpio_bank);
3355 +       unsigned lev;
3356 +
3357 +       if (offset >= ARCH_NR_GPIOS)
3358 +               return 0;
3359 +       lev = readl(gpio->base + GPIOLEV(gpio_bank));
3360 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
3361 +       return 0x1 & (lev >> gpio_field_offset);
3362 +}
3363 +
3364 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
3365 +{
3366 +       struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
3367 +       unsigned gpio_bank = offset / 32;
3368 +       unsigned gpio_field_offset = (offset - 32 * gpio_bank);
3369 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
3370 +       if (offset >= ARCH_NR_GPIOS)
3371 +               return;
3372 +       if (value)
3373 +               writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
3374 +       else
3375 +               writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
3376 +}
3377 +
3378 +/*************************************************************************************************************************
3379 + * bcm2708 GPIO IRQ
3380 + */
3381 +
3382 +#if BCM_GPIO_USE_IRQ
3383 +
3384 +static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
3385 +{
3386 +       return gpio_to_irq(gpio);
3387 +}
3388 +
3389 +static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type)
3390 +{
3391 +       unsigned irq = d->irq;
3392 +       struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
3393 +
3394 +       if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
3395 +               return -EINVAL;
3396 +
3397 +       if (type & IRQ_TYPE_EDGE_RISING) {
3398 +               gpio->rising |= (1 << irq_to_gpio(irq));
3399 +       } else {
3400 +               gpio->rising &= ~(1 << irq_to_gpio(irq));
3401 +       }
3402 +
3403 +       if (type & IRQ_TYPE_EDGE_FALLING) {
3404 +               gpio->falling |= (1 << irq_to_gpio(irq));
3405 +       } else {
3406 +               gpio->falling &= ~(1 << irq_to_gpio(irq));
3407 +       }
3408 +       return 0;
3409 +}
3410 +
3411 +static void bcm2708_gpio_irq_mask(struct irq_data *d)
3412 +{
3413 +       unsigned irq = d->irq;
3414 +       struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
3415 +       unsigned gn = irq_to_gpio(irq);
3416 +       unsigned gb = gn / 32;
3417 +       unsigned long rising = readl(gpio->base + GPIOREN(gb));
3418 +       unsigned long falling = readl(gpio->base + GPIOFEN(gb));
3419 +
3420 +       gn = gn % 32;
3421 +
3422 +       writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
3423 +       writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
3424 +}
3425 +
3426 +static void bcm2708_gpio_irq_unmask(struct irq_data *d)
3427 +{
3428 +       unsigned irq = d->irq;
3429 +       struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
3430 +       unsigned gn = irq_to_gpio(irq);
3431 +       unsigned gb = gn / 32;
3432 +       unsigned long rising = readl(gpio->base + GPIOREN(gb));
3433 +       unsigned long falling = readl(gpio->base + GPIOFEN(gb));
3434 +
3435 +       gn = gn % 32;
3436 +
3437 +       writel(1 << gn, gpio->base + GPIOEDS(gb));
3438 +
3439 +       if (gpio->rising & (1 << gn)) {
3440 +               writel(rising | (1 << gn), gpio->base + GPIOREN(gb));
3441 +       } else {
3442 +               writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
3443 +       }
3444 +
3445 +       if (gpio->falling & (1 << gn)) {
3446 +               writel(falling | (1 << gn), gpio->base + GPIOFEN(gb));
3447 +       } else {
3448 +               writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
3449 +       }
3450 +}
3451 +
3452 +static struct irq_chip bcm2708_irqchip = {
3453 +       .name = "GPIO",
3454 +       .irq_enable = bcm2708_gpio_irq_unmask,
3455 +       .irq_disable = bcm2708_gpio_irq_mask,
3456 +       .irq_unmask = bcm2708_gpio_irq_unmask,
3457 +       .irq_mask = bcm2708_gpio_irq_mask,
3458 +       .irq_set_type = bcm2708_gpio_irq_set_type,
3459 +};
3460 +
3461 +static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id)
3462 +{
3463 +       unsigned long edsr;
3464 +       unsigned bank;
3465 +       int i;
3466 +       unsigned gpio;
3467 +       for (bank = 0; bank <= 1; bank++) {
3468 +               edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank));
3469 +               for_each_set_bit(i, &edsr, 32) {
3470 +                       gpio = i + bank * 32;
3471 +                       generic_handle_irq(gpio_to_irq(gpio));
3472 +               }
3473 +               writel(0xffffffff, __io_address(GPIO_BASE) + GPIOEDS(bank));
3474 +       }
3475 +       return IRQ_HANDLED;
3476 +}
3477 +
3478 +static struct irqaction bcm2708_gpio_irq = {
3479 +       .name = "BCM2708 GPIO catchall handler",
3480 +       .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
3481 +       .handler = bcm2708_gpio_interrupt,
3482 +};
3483 +
3484 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
3485 +{
3486 +       unsigned irq;
3487 +
3488 +       ucb->gc.to_irq = bcm2708_gpio_to_irq;
3489 +
3490 +       for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) {
3491 +               irq_set_chip_data(irq, ucb);
3492 +               irq_set_chip(irq, &bcm2708_irqchip);
3493 +               set_irq_flags(irq, IRQF_VALID);
3494 +       }
3495 +       setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq);
3496 +}
3497 +
3498 +#else
3499 +
3500 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
3501 +{
3502 +}
3503 +
3504 +#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */
3505 +
3506 +static int bcm2708_gpio_probe(struct platform_device *dev)
3507 +{
3508 +       struct bcm2708_gpio *ucb;
3509 +       struct resource *res;
3510 +       int err = 0;
3511 +
3512 +       printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
3513 +
3514 +       ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
3515 +       if (NULL == ucb) {
3516 +               printk(KERN_ERR DRIVER_NAME ": failed to allocate "
3517 +                      "mailbox memory\n");
3518 +               err = -ENOMEM;
3519 +               goto err;
3520 +       }
3521 +
3522 +       res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3523 +
3524 +       platform_set_drvdata(dev, ucb);
3525 +       ucb->base = __io_address(GPIO_BASE);
3526 +
3527 +       ucb->gc.label = "bcm2708_gpio";
3528 +       ucb->gc.base = 0;
3529 +       ucb->gc.ngpio = ARCH_NR_GPIOS;
3530 +       ucb->gc.owner = THIS_MODULE;
3531 +
3532 +       ucb->gc.direction_input = bcm2708_gpio_dir_in;
3533 +       ucb->gc.direction_output = bcm2708_gpio_dir_out;
3534 +       ucb->gc.get = bcm2708_gpio_get;
3535 +       ucb->gc.set = bcm2708_gpio_set;
3536 +       ucb->gc.can_sleep = 0;
3537 +
3538 +       bcm2708_gpio_irq_init(ucb);
3539 +
3540 +       err = gpiochip_add(&ucb->gc);
3541 +       if (err)
3542 +               goto err;
3543 +
3544 +err:
3545 +       return err;
3546 +
3547 +}
3548 +
3549 +static int bcm2708_gpio_remove(struct platform_device *dev)
3550 +{
3551 +       int err = 0;
3552 +       struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
3553 +
3554 +       printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
3555 +
3556 +       err = gpiochip_remove(&ucb->gc);
3557 +
3558 +       platform_set_drvdata(dev, NULL);
3559 +       kfree(ucb);
3560 +
3561 +       return err;
3562 +}
3563 +
3564 +static struct platform_driver bcm2708_gpio_driver = {
3565 +       .probe = bcm2708_gpio_probe,
3566 +       .remove = bcm2708_gpio_remove,
3567 +       .driver = {
3568 +                  .name = "bcm2708_gpio"},
3569 +};
3570 +
3571 +static int __init bcm2708_gpio_init(void)
3572 +{
3573 +       return platform_driver_register(&bcm2708_gpio_driver);
3574 +}
3575 +
3576 +static void __exit bcm2708_gpio_exit(void)
3577 +{
3578 +       platform_driver_unregister(&bcm2708_gpio_driver);
3579 +}
3580 +
3581 +module_init(bcm2708_gpio_init);
3582 +module_exit(bcm2708_gpio_exit);
3583 +
3584 +MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
3585 +MODULE_LICENSE("GPL");
3586 diff -urN linux-3.10/arch/arm/mach-bcm2708/bcm2708.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/bcm2708.h
3587 --- linux-3.10/arch/arm/mach-bcm2708/bcm2708.h  1970-01-01 01:00:00.000000000 +0100
3588 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/bcm2708.h    2013-07-06 15:25:50.000000000 +0100
3589 @@ -0,0 +1,51 @@
3590 +/*
3591 + * linux/arch/arm/mach-bcm2708/bcm2708.h
3592 + *
3593 + * BCM2708 machine support header
3594 + *
3595 + *  Copyright (C) 2010 Broadcom
3596 + *
3597 + * This program is free software; you can redistribute it and/or modify
3598 + * it under the terms of the GNU General Public License as published by
3599 + * the Free Software Foundation; either version 2 of the License, or
3600 + * (at your option) any later version.
3601 + *
3602 + * This program is distributed in the hope that it will be useful,
3603 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3604 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3605 + * GNU General Public License for more details.
3606 + *
3607 + * You should have received a copy of the GNU General Public License
3608 + * along with this program; if not, write to the Free Software
3609 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
3610 + */
3611 +
3612 +#ifndef __BCM2708_BCM2708_H
3613 +#define __BCM2708_BCM2708_H
3614 +
3615 +#include <linux/amba/bus.h>
3616 +
3617 +extern void __init bcm2708_init(void);
3618 +extern void __init bcm2708_init_irq(void);
3619 +extern void __init bcm2708_map_io(void);
3620 +extern struct sys_timer bcm2708_timer;
3621 +extern unsigned int mmc_status(struct device *dev);
3622 +
3623 +#define AMBA_DEVICE(name, busid, base, plat)                   \
3624 +static struct amba_device name##_device = {                    \
3625 +       .dev            = {                                     \
3626 +               .coherent_dma_mask = ~0,                        \
3627 +               .init_name = busid,                             \
3628 +               .platform_data = plat,                          \
3629 +       },                                                      \
3630 +       .res            = {                                     \
3631 +               .start  = base##_BASE,          \
3632 +               .end    = (base##_BASE) + SZ_4K - 1,\
3633 +               .flags  = IORESOURCE_MEM,                       \
3634 +       },                                                      \
3635 +       .dma_mask       = ~0,                                   \
3636 +       .irq            = base##_IRQ,                           \
3637 +       /* .dma         = base##_DMA,*/                         \
3638 +}
3639 +
3640 +#endif
3641 diff -urN linux-3.10/arch/arm/mach-bcm2708/clock.c linux-rpi-3.10.y/arch/arm/mach-bcm2708/clock.c
3642 --- linux-3.10/arch/arm/mach-bcm2708/clock.c    1970-01-01 01:00:00.000000000 +0100
3643 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/clock.c      2013-07-06 15:25:50.000000000 +0100
3644 @@ -0,0 +1,61 @@
3645 +/*
3646 + *  linux/arch/arm/mach-bcm2708/clock.c
3647 + *
3648 + *  Copyright (C) 2010 Broadcom
3649 + *
3650 + * This program is free software; you can redistribute it and/or modify
3651 + * it under the terms of the GNU General Public License as published by
3652 + * the Free Software Foundation; either version 2 of the License, or
3653 + * (at your option) any later version.
3654 + *
3655 + * This program is distributed in the hope that it will be useful,
3656 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3657 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3658 + * GNU General Public License for more details.
3659 + *
3660 + * You should have received a copy of the GNU General Public License
3661 + * along with this program; if not, write to the Free Software
3662 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
3663 + */
3664 +#include <linux/module.h>
3665 +#include <linux/kernel.h>
3666 +#include <linux/device.h>
3667 +#include <linux/list.h>
3668 +#include <linux/errno.h>
3669 +#include <linux/err.h>
3670 +#include <linux/string.h>
3671 +#include <linux/clk.h>
3672 +#include <linux/mutex.h>
3673 +
3674 +#include <asm/clkdev.h>
3675 +
3676 +#include "clock.h"
3677 +
3678 +int clk_enable(struct clk *clk)
3679 +{
3680 +       return 0;
3681 +}
3682 +EXPORT_SYMBOL(clk_enable);
3683 +
3684 +void clk_disable(struct clk *clk)
3685 +{
3686 +}
3687 +EXPORT_SYMBOL(clk_disable);
3688 +
3689 +unsigned long clk_get_rate(struct clk *clk)
3690 +{
3691 +       return clk->rate;
3692 +}
3693 +EXPORT_SYMBOL(clk_get_rate);
3694 +
3695 +long clk_round_rate(struct clk *clk, unsigned long rate)
3696 +{
3697 +       return clk->rate;
3698 +}
3699 +EXPORT_SYMBOL(clk_round_rate);
3700 +
3701 +int clk_set_rate(struct clk *clk, unsigned long rate)
3702 +{
3703 +       return -EIO;
3704 +}
3705 +EXPORT_SYMBOL(clk_set_rate);
3706 diff -urN linux-3.10/arch/arm/mach-bcm2708/clock.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/clock.h
3707 --- linux-3.10/arch/arm/mach-bcm2708/clock.h    1970-01-01 01:00:00.000000000 +0100
3708 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/clock.h      2013-07-06 15:25:50.000000000 +0100
3709 @@ -0,0 +1,24 @@
3710 +/*
3711 + *  linux/arch/arm/mach-bcm2708/clock.h
3712 + *
3713 + *  Copyright (C) 2010 Broadcom
3714 + *
3715 + * This program is free software; you can redistribute it and/or modify
3716 + * it under the terms of the GNU General Public License as published by
3717 + * the Free Software Foundation; either version 2 of the License, or
3718 + * (at your option) any later version.
3719 + *
3720 + * This program is distributed in the hope that it will be useful,
3721 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3722 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3723 + * GNU General Public License for more details.
3724 + *
3725 + * You should have received a copy of the GNU General Public License
3726 + * along with this program; if not, write to the Free Software
3727 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
3728 + */
3729 +struct module;
3730 +
3731 +struct clk {
3732 +       unsigned long           rate;
3733 +};
3734 diff -urN linux-3.10/arch/arm/mach-bcm2708/dma.c linux-rpi-3.10.y/arch/arm/mach-bcm2708/dma.c
3735 --- linux-3.10/arch/arm/mach-bcm2708/dma.c      1970-01-01 01:00:00.000000000 +0100
3736 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/dma.c        2013-07-06 15:25:50.000000000 +0100
3737 @@ -0,0 +1,399 @@
3738 +/*
3739 + *  linux/arch/arm/mach-bcm2708/dma.c
3740 + *
3741 + *  Copyright (C) 2010 Broadcom
3742 + *
3743 + * This program is free software; you can redistribute it and/or modify
3744 + * it under the terms of the GNU General Public License version 2 as
3745 + * published by the Free Software Foundation.
3746 + */
3747 +
3748 +#include <linux/slab.h>
3749 +#include <linux/device.h>
3750 +#include <linux/platform_device.h>
3751 +#include <linux/module.h>
3752 +#include <linux/scatterlist.h>
3753 +
3754 +#include <mach/dma.h>
3755 +#include <mach/irqs.h>
3756 +
3757 +/*****************************************************************************\
3758 + *                                                                          *
3759 + * Configuration                                                            *
3760 + *                                                                          *
3761 +\*****************************************************************************/
3762 +
3763 +#define CACHE_LINE_MASK 31
3764 +#define DRIVER_NAME BCM_DMAMAN_DRIVER_NAME
3765 +#define DEFAULT_DMACHAN_BITMAP 0x10  /* channel 4 only */
3766 +
3767 +/* valid only for channels 0 - 14, 15 has its own base address */
3768 +#define BCM2708_DMA_CHAN(n)    ((n)<<8) /* base address */
3769 +#define BCM2708_DMA_CHANIO(dma_base, n) \
3770 +   ((void __iomem *)((char *)(dma_base)+BCM2708_DMA_CHAN(n)))
3771 +
3772 +
3773 +/*****************************************************************************\
3774 + *                                                                          *
3775 + * DMA Auxilliary Functions                                                 *
3776 + *                                                                          *
3777 +\*****************************************************************************/
3778 +
3779 +/* A DMA buffer on an arbitrary boundary may separate a cache line into a
3780 +   section inside the DMA buffer and another section outside it.
3781 +   Even if we flush DMA buffers from the cache there is always the chance that
3782 +   during a DMA someone will access the part of a cache line that is outside
3783 +   the DMA buffer - which will then bring in unwelcome data.
3784 +   Without being able to dictate our own buffer pools we must insist that
3785 +   DMA buffers consist of a whole number of cache lines.
3786 +*/
3787 +
3788 +extern int
3789 +bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
3790 +{
3791 +       int i;
3792 +
3793 +       for (i = 0; i < sg_len; i++) {
3794 +               if (sg_ptr[i].offset & CACHE_LINE_MASK ||
3795 +                   sg_ptr[i].length & CACHE_LINE_MASK)
3796 +                       return 0;
3797 +       }
3798 +
3799 +       return 1;
3800 +}
3801 +EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
3802 +
3803 +extern void
3804 +bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block)
3805 +{
3806 +       dsb();  /* ARM data synchronization (push) operation */
3807 +
3808 +       writel(control_block,        dma_chan_base + BCM2708_DMA_ADDR);
3809 +       writel(BCM2708_DMA_ACTIVE,   dma_chan_base + BCM2708_DMA_CS);
3810 +}
3811 +
3812 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
3813 +{
3814 +  dsb();
3815 +
3816 +  /* ugly busy wait only option for now */
3817 +  while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
3818 +    cpu_relax();
3819 +}
3820 +
3821 +EXPORT_SYMBOL_GPL(bcm_dma_start);
3822 +
3823 +/* Complete an ongoing DMA (assuming its results are to be ignored)
3824 +   Does nothing if there is no DMA in progress.
3825 +   This routine waits for the current AXI transfer to complete before
3826 +   terminating the current DMA.         If the current transfer is hung on a DREQ used
3827 +   by an uncooperative peripheral the AXI transfer may never complete. In this
3828 +   case the routine times out and return a non-zero error code.
3829 +   Use of this routine doesn't guarantee that the ongoing or aborted DMA
3830 +   does not produce an interrupt.
3831 +*/
3832 +extern int
3833 +bcm_dma_abort(void __iomem *dma_chan_base)
3834 +{
3835 +       unsigned long int cs;
3836 +       int rc = 0;
3837 +
3838 +       cs = readl(dma_chan_base + BCM2708_DMA_CS);
3839 +
3840 +       if (BCM2708_DMA_ACTIVE & cs) {
3841 +               long int timeout = 10000;
3842 +
3843 +               /* write 0 to the active bit - pause the DMA */
3844 +               writel(0, dma_chan_base + BCM2708_DMA_CS);
3845 +
3846 +               /* wait for any current AXI transfer to complete */
3847 +               while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
3848 +                       cs = readl(dma_chan_base + BCM2708_DMA_CS);
3849 +
3850 +               if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
3851 +                       /* we'll un-pause when we set of our next DMA */
3852 +                       rc = -ETIMEDOUT;
3853 +
3854 +               } else if (BCM2708_DMA_ACTIVE & cs) {
3855 +                       /* terminate the control block chain */
3856 +                       writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
3857 +
3858 +                       /* abort the whole DMA */
3859 +                       writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
3860 +                              dma_chan_base + BCM2708_DMA_CS);
3861 +               }
3862 +       }
3863 +
3864 +       return rc;
3865 +}
3866 +EXPORT_SYMBOL_GPL(bcm_dma_abort);
3867 +
3868 +
3869 +/***************************************************************************** \
3870 + *                                                                          *
3871 + * DMA Manager Device Methods                                               *
3872 + *                                                                          *
3873 +\*****************************************************************************/
3874 +
3875 +struct vc_dmaman {
3876 +       void __iomem *dma_base;
3877 +       u32 chan_available; /* bitmap of available channels */
3878 +       u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
3879 +};
3880 +
3881 +static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
3882 +                          u32 chans_available)
3883 +{
3884 +       dmaman->dma_base = dma_base;
3885 +       dmaman->chan_available = chans_available;
3886 +       dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c;  /* chans 2 & 3 */
3887 +       dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01;  /* chan 0 */
3888 +}
3889 +
3890 +static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
3891 +                               unsigned preferred_feature_set)
3892 +{
3893 +       u32 chans;
3894 +       int feature;
3895 +
3896 +       chans = dmaman->chan_available;
3897 +       for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
3898 +               /* select the subset of available channels with the desired
3899 +                  feature so long as some of the candidate channels have that
3900 +                  feature */
3901 +               if ((preferred_feature_set & (1 << feature)) &&
3902 +                   (chans & dmaman->has_feature[feature]))
3903 +                       chans &= dmaman->has_feature[feature];
3904 +
3905 +       if (chans) {
3906 +               int chan = 0;
3907 +               /* return the ordinal of the first channel in the bitmap */
3908 +               while (chans != 0 && (chans & 1) == 0) {
3909 +                       chans >>= 1;
3910 +                       chan++;
3911 +               }
3912 +               /* claim the channel */
3913 +               dmaman->chan_available &= ~(1 << chan);
3914 +               return chan;
3915 +       } else
3916 +               return -ENOMEM;
3917 +}
3918 +
3919 +static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
3920 +{
3921 +       if (chan < 0)
3922 +               return -EINVAL;
3923 +       else if ((1 << chan) & dmaman->chan_available)
3924 +               return -EIDRM;
3925 +       else {
3926 +               dmaman->chan_available |= (1 << chan);
3927 +               return 0;
3928 +       }
3929 +}
3930 +
3931 +/*****************************************************************************\
3932 + *                                                                          *
3933 + * DMA IRQs                                                                 *
3934 + *                                                                          *
3935 +\*****************************************************************************/
3936 +
3937 +static unsigned char bcm_dma_irqs[] = {
3938 +       IRQ_DMA0,
3939 +       IRQ_DMA1,
3940 +       IRQ_DMA2,
3941 +       IRQ_DMA3,
3942 +       IRQ_DMA4,
3943 +       IRQ_DMA5,
3944 +       IRQ_DMA6,
3945 +       IRQ_DMA7,
3946 +       IRQ_DMA8,
3947 +       IRQ_DMA9,
3948 +       IRQ_DMA10,
3949 +       IRQ_DMA11,
3950 +       IRQ_DMA12
3951 +};
3952 +
3953 +
3954 +/***************************************************************************** \
3955 + *                                                                          *
3956 + * DMA Manager Monitor                                                      *
3957 + *                                                                          *
3958 +\*****************************************************************************/
3959 +
3960 +static struct device *dmaman_dev;      /* we assume there's only one! */
3961 +
3962 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
3963 +                             void __iomem **out_dma_base, int *out_dma_irq)
3964 +{
3965 +       if (!dmaman_dev)
3966 +               return -ENODEV;
3967 +       else {
3968 +               struct vc_dmaman *dmaman  = dev_get_drvdata(dmaman_dev);
3969 +               int rc;
3970 +
3971 +               device_lock(dmaman_dev);
3972 +               rc = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
3973 +               if (rc >= 0) {
3974 +                       *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base,
3975 +                                                          rc);
3976 +                       *out_dma_irq = bcm_dma_irqs[rc];
3977 +               }
3978 +               device_unlock(dmaman_dev);
3979 +
3980 +               return rc;
3981 +       }
3982 +}
3983 +EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
3984 +
3985 +extern int bcm_dma_chan_free(int channel)
3986 +{
3987 +       if (dmaman_dev) {
3988 +               struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
3989 +               int rc;
3990 +
3991 +               device_lock(dmaman_dev);
3992 +               rc = vc_dmaman_chan_free(dmaman, channel);
3993 +               device_unlock(dmaman_dev);
3994 +
3995 +               return rc;
3996 +       } else
3997 +               return -ENODEV;
3998 +}
3999 +EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
4000 +
4001 +static int dev_dmaman_register(const char *dev_name, struct device *dev)
4002 +{
4003 +       int rc = dmaman_dev ? -EINVAL : 0;
4004 +       dmaman_dev = dev;
4005 +       return rc;
4006 +}
4007 +
4008 +static void dev_dmaman_deregister(const char *dev_name, struct device *dev)
4009 +{
4010 +       dmaman_dev = NULL;
4011 +}
4012 +
4013 +/*****************************************************************************\
4014 + *                                                                          *
4015 + * DMA Device                                                               *
4016 + *                                                                          *
4017 +\*****************************************************************************/
4018 +
4019 +static int dmachans = -1; /* module parameter */
4020 +
4021 +static int bcm_dmaman_probe(struct platform_device *pdev)
4022 +{
4023 +       int ret = 0;
4024 +       struct vc_dmaman *dmaman;
4025 +       struct resource *dma_res = NULL;
4026 +       void __iomem *dma_base = NULL;
4027 +       int have_dma_region = 0;
4028 +
4029 +       dmaman = kzalloc(sizeof(*dmaman), GFP_KERNEL);
4030 +       if (NULL == dmaman) {
4031 +               printk(KERN_ERR DRIVER_NAME ": failed to allocate "
4032 +                      "DMA management memory\n");
4033 +               ret = -ENOMEM;
4034 +       } else {
4035 +
4036 +               dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4037 +               if (dma_res == NULL) {
4038 +                       printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
4039 +                              "resource\n");
4040 +                       ret = -ENODEV;
4041 +               } else if (!request_mem_region(dma_res->start,
4042 +                                              resource_size(dma_res),
4043 +                                              DRIVER_NAME)) {
4044 +                       dev_err(&pdev->dev, "cannot obtain DMA region\n");
4045 +                       ret = -EBUSY;
4046 +               } else {
4047 +                       have_dma_region = 1;
4048 +                       dma_base = ioremap(dma_res->start,
4049 +                                          resource_size(dma_res));
4050 +                       if (!dma_base) {
4051 +                               dev_err(&pdev->dev, "cannot map DMA region\n");
4052 +                               ret = -ENOMEM;
4053 +                       } else {
4054 +                               /* use module parameter if one was provided */
4055 +                               if (dmachans > 0)
4056 +                                       vc_dmaman_init(dmaman, dma_base,
4057 +                                                      dmachans);
4058 +                               else
4059 +                                       vc_dmaman_init(dmaman, dma_base,
4060 +                                                      DEFAULT_DMACHAN_BITMAP);
4061 +
4062 +                               platform_set_drvdata(pdev, dmaman);
4063 +                               dev_dmaman_register(DRIVER_NAME, &pdev->dev);
4064 +
4065 +                               printk(KERN_INFO DRIVER_NAME ": DMA manager "
4066 +                                      "at %p\n", dma_base);
4067 +                       }
4068 +               }
4069 +       }
4070 +       if (ret != 0) {
4071 +               if (dma_base)
4072 +                       iounmap(dma_base);
4073 +               if (dma_res && have_dma_region)
4074 +                       release_mem_region(dma_res->start,
4075 +                                          resource_size(dma_res));
4076 +               if (dmaman)
4077 +                       kfree(dmaman);
4078 +       }
4079 +       return ret;
4080 +}
4081 +
4082 +static int bcm_dmaman_remove(struct platform_device *pdev)
4083 +{
4084 +       struct vc_dmaman *dmaman = platform_get_drvdata(pdev);
4085 +
4086 +       platform_set_drvdata(pdev, NULL);
4087 +       dev_dmaman_deregister(DRIVER_NAME, &pdev->dev);
4088 +       kfree(dmaman);
4089 +
4090 +       return 0;
4091 +}
4092 +
4093 +static struct platform_driver bcm_dmaman_driver = {
4094 +       .probe = bcm_dmaman_probe,
4095 +       .remove = bcm_dmaman_remove,
4096 +
4097 +       .driver = {
4098 +                  .name = DRIVER_NAME,
4099 +                  .owner = THIS_MODULE,
4100 +                  },
4101 +};
4102 +
4103 +/*****************************************************************************\
4104 + *                                                                          *
4105 + * Driver init/exit                                                         *
4106 + *                                                                          *
4107 +\*****************************************************************************/
4108 +
4109 +static int __init bcm_dmaman_drv_init(void)
4110 +{
4111 +       int ret;
4112 +
4113 +       ret = platform_driver_register(&bcm_dmaman_driver);
4114 +       if (ret != 0) {
4115 +               printk(KERN_ERR DRIVER_NAME ": failed to register "
4116 +                      "on platform\n");
4117 +       }
4118 +
4119 +       return ret;
4120 +}
4121 +
4122 +static void __exit bcm_dmaman_drv_exit(void)
4123 +{
4124 +       platform_driver_unregister(&bcm_dmaman_driver);
4125 +}
4126 +
4127 +module_init(bcm_dmaman_drv_init);
4128 +module_exit(bcm_dmaman_drv_exit);
4129 +
4130 +module_param(dmachans, int, 0644);
4131 +
4132 +MODULE_AUTHOR("Gray Girling <grayg@broadcom.com>");
4133 +MODULE_DESCRIPTION("DMA channel manager driver");
4134 +MODULE_LICENSE("GPL");
4135 +
4136 +MODULE_PARM_DESC(dmachans, "Bitmap of DMA channels available to the ARM");
4137 diff -urN linux-3.10/arch/arm/mach-bcm2708/dmaer.c linux-rpi-3.10.y/arch/arm/mach-bcm2708/dmaer.c
4138 --- linux-3.10/arch/arm/mach-bcm2708/dmaer.c    1970-01-01 01:00:00.000000000 +0100
4139 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/dmaer.c      2013-07-06 15:25:50.000000000 +0100
4140 @@ -0,0 +1,887 @@
4141 +#include <linux/init.h>
4142 +#include <linux/sched.h>
4143 +#include <linux/module.h>
4144 +#include <linux/types.h>
4145 +#include <linux/kdev_t.h>
4146 +#include <linux/fs.h>
4147 +#include <linux/cdev.h>
4148 +#include <linux/mm.h>
4149 +#include <linux/slab.h>
4150 +#include <linux/pagemap.h>
4151 +#include <linux/device.h>
4152 +#include <linux/jiffies.h>
4153 +#include <linux/timex.h>
4154 +#include <linux/dma-mapping.h>
4155 +
4156 +#include <asm/uaccess.h>
4157 +#include <asm/atomic.h>
4158 +#include <asm/cacheflush.h>
4159 +#include <asm/io.h>
4160 +
4161 +#include <mach/dma.h>
4162 +#include <mach/vc_support.h>
4163 +
4164 +#ifdef ECLIPSE_IGNORE
4165 +
4166 +#define __user
4167 +#define __init
4168 +#define __exit
4169 +#define __iomem
4170 +#define KERN_DEBUG
4171 +#define KERN_ERR
4172 +#define KERN_WARNING
4173 +#define KERN_INFO
4174 +#define _IOWR(a, b, c) b
4175 +#define _IOW(a, b, c) b
4176 +#define _IO(a, b) b
4177 +
4178 +#endif
4179 +
4180 +//#define inline
4181 +
4182 +#define PRINTK(args...) printk(args)
4183 +//#define PRINTK_VERBOSE(args...) printk(args)
4184 +//#define PRINTK(args...)
4185 +#define PRINTK_VERBOSE(args...)
4186 +
4187 +/***** TYPES ****/
4188 +#define PAGES_PER_LIST 500
4189 +struct PageList
4190 +{
4191 +       struct page *m_pPages[PAGES_PER_LIST];
4192 +       unsigned int m_used;
4193 +       struct PageList *m_pNext;
4194 +};
4195 +
4196 +struct VmaPageList
4197 +{
4198 +       //each vma has a linked list of pages associated with it
4199 +       struct PageList *m_pPageHead;
4200 +       struct PageList *m_pPageTail;
4201 +       unsigned int m_refCount;
4202 +};
4203 +
4204 +struct DmaControlBlock
4205 +{
4206 +       unsigned int m_transferInfo;
4207 +       void __user *m_pSourceAddr;
4208 +       void __user *m_pDestAddr;
4209 +       unsigned int m_xferLen;
4210 +       unsigned int m_tdStride;
4211 +       struct DmaControlBlock *m_pNext;
4212 +       unsigned int m_blank1, m_blank2;
4213 +};
4214 +
4215 +/***** DEFINES ******/
4216 +//magic number defining the module
4217 +#define DMA_MAGIC              0xdd
4218 +
4219 +//do user virtual to physical translation of the CB chain
4220 +#define DMA_PREPARE            _IOWR(DMA_MAGIC, 0, struct DmaControlBlock *)
4221 +
4222 +//kick the pre-prepared CB chain
4223 +#define DMA_KICK               _IOW(DMA_MAGIC, 1, struct DmaControlBlock *)
4224 +
4225 +//prepare it, kick it, wait for it
4226 +#define DMA_PREPARE_KICK_WAIT  _IOWR(DMA_MAGIC, 2, struct DmaControlBlock *)
4227 +
4228 +//prepare it, kick it, don't wait for it
4229 +#define DMA_PREPARE_KICK       _IOWR(DMA_MAGIC, 3, struct DmaControlBlock *)
4230 +
4231 +//not currently implemented
4232 +#define DMA_WAIT_ONE           _IO(DMA_MAGIC, 4, struct DmaControlBlock *)
4233 +
4234 +//wait on all kicked CB chains
4235 +#define DMA_WAIT_ALL           _IO(DMA_MAGIC, 5)
4236 +
4237 +//in order to discover the largest AXI burst that should be programmed into the transfer params
4238 +#define DMA_MAX_BURST          _IO(DMA_MAGIC, 6)
4239 +
4240 +//set the address range through which the user address is assumed to already by a physical address
4241 +#define DMA_SET_MIN_PHYS       _IOW(DMA_MAGIC, 7, unsigned long)
4242 +#define DMA_SET_MAX_PHYS       _IOW(DMA_MAGIC, 8, unsigned long)
4243 +#define DMA_SET_PHYS_OFFSET    _IOW(DMA_MAGIC, 9, unsigned long)
4244 +
4245 +//used to define the size for the CMA-based allocation *in pages*, can only be done once once the file is opened
4246 +#define DMA_CMA_SET_SIZE       _IOW(DMA_MAGIC, 10, unsigned long)
4247 +
4248 +//used to get the version of the module, to test for a capability
4249 +#define DMA_GET_VERSION                _IO(DMA_MAGIC, 99)
4250 +
4251 +#define VERSION_NUMBER 1
4252 +
4253 +#define VIRT_TO_BUS_CACHE_SIZE 8
4254 +
4255 +/***** FILE OPS *****/
4256 +static int Open(struct inode *pInode, struct file *pFile);
4257 +static int Release(struct inode *pInode, struct file *pFile);
4258 +static long Ioctl(struct file *pFile, unsigned int cmd, unsigned long arg);
4259 +static ssize_t Read(struct file *pFile, char __user *pUser, size_t count, loff_t *offp);
4260 +static int Mmap(struct file *pFile, struct vm_area_struct *pVma);
4261 +
4262 +/***** VMA OPS ****/
4263 +static void VmaOpen4k(struct vm_area_struct *pVma);
4264 +static void VmaClose4k(struct vm_area_struct *pVma);
4265 +static int VmaFault4k(struct vm_area_struct *pVma, struct vm_fault *pVmf);
4266 +
4267 +/**** DMA PROTOTYPES */
4268 +static struct DmaControlBlock __user *DmaPrepare(struct DmaControlBlock __user *pUserCB, int *pError);
4269 +static int DmaKick(struct DmaControlBlock __user *pUserCB);
4270 +static void DmaWaitAll(void);
4271 +
4272 +/**** GENERIC ****/
4273 +static int __init dmaer_init(void);
4274 +static void __exit dmaer_exit(void);
4275 +
4276 +/*** OPS ***/
4277 +static struct vm_operations_struct g_vmOps4k = {
4278 +       .open = VmaOpen4k,
4279 +       .close = VmaClose4k,
4280 +       .fault = VmaFault4k,
4281 +};
4282 +
4283 +static struct file_operations g_fOps = {
4284 +       .owner = THIS_MODULE,
4285 +       .llseek = 0,
4286 +       .read = Read,
4287 +       .write = 0,
4288 +       .unlocked_ioctl = Ioctl,
4289 +       .open = Open,
4290 +       .release = Release,
4291 +       .mmap = Mmap,
4292 +};
4293 +
4294 +/***** GLOBALS ******/
4295 +static dev_t g_majorMinor;
4296 +
4297 +//tracking usage of the two files
4298 +static atomic_t g_oneLock4k = ATOMIC_INIT(1);
4299 +
4300 +//device operations
4301 +static struct cdev g_cDev;
4302 +static int g_trackedPages = 0;
4303 +
4304 +//dma control
4305 +static unsigned int *g_pDmaChanBase;
4306 +static int g_dmaIrq;
4307 +static int g_dmaChan;
4308 +
4309 +//cma allocation
4310 +static int g_cmaHandle;
4311 +
4312 +//user virtual to bus address translation acceleration
4313 +static unsigned long g_virtAddr[VIRT_TO_BUS_CACHE_SIZE];
4314 +static unsigned long g_busAddr[VIRT_TO_BUS_CACHE_SIZE];
4315 +static unsigned long g_cbVirtAddr;
4316 +static unsigned long g_cbBusAddr;
4317 +static int g_cacheInsertAt;
4318 +static int g_cacheHit, g_cacheMiss;
4319 +
4320 +//off by default
4321 +static void __user *g_pMinPhys;
4322 +static void __user *g_pMaxPhys;
4323 +static unsigned long g_physOffset;
4324 +
4325 +/****** CACHE OPERATIONS ********/
4326 +static inline void FlushAddrCache(void)
4327 +{
4328 +       int count = 0;
4329 +       for (count = 0; count < VIRT_TO_BUS_CACHE_SIZE; count++)
4330 +               g_virtAddr[count] = 0xffffffff;                 //never going to match as we always chop the bottom bits anyway
4331 +
4332 +       g_cbVirtAddr = 0xffffffff;
4333 +
4334 +       g_cacheInsertAt = 0;
4335 +}
4336 +
4337 +//translate from a user virtual address to a bus address by mapping the page
4338 +//NB this won't lock a page in memory, so to avoid potential paging issues using kernel logical addresses
4339 +static inline void __iomem *UserVirtualToBus(void __user *pUser)
4340 +{
4341 +       int mapped;
4342 +       struct page *pPage;
4343 +       void *phys;
4344 +
4345 +       //map it (requiring that the pointer points to something that does not hang off the page boundary)
4346 +       mapped = get_user_pages(current, current->mm,
4347 +               (unsigned long)pUser, 1,
4348 +               1, 0,
4349 +               &pPage,
4350 +               0);
4351 +
4352 +       if (mapped <= 0)                //error
4353 +               return 0;
4354 +
4355 +       PRINTK_VERBOSE(KERN_DEBUG "user virtual %p arm phys %p bus %p\n",
4356 +                       pUser, page_address(pPage), (void __iomem *)__virt_to_bus(page_address(pPage)));
4357 +
4358 +       //get the arm physical address
4359 +       phys = page_address(pPage) + offset_in_page(pUser);
4360 +       page_cache_release(pPage);
4361 +
4362 +       //and now the bus address
4363 +       return (void __iomem *)__virt_to_bus(phys);
4364 +}
4365 +
4366 +static inline void __iomem *UserVirtualToBusViaCbCache(void __user *pUser)
4367 +{
4368 +       unsigned long virtual_page = (unsigned long)pUser & ~4095;
4369 +       unsigned long page_offset = (unsigned long)pUser & 4095;
4370 +       unsigned long bus_addr;
4371 +
4372 +       if (g_cbVirtAddr == virtual_page)
4373 +       {
4374 +               bus_addr = g_cbBusAddr + page_offset;
4375 +               g_cacheHit++;
4376 +               return (void __iomem *)bus_addr;
4377 +       }
4378 +       else
4379 +       {
4380 +               bus_addr = (unsigned long)UserVirtualToBus(pUser);
4381 +
4382 +               if (!bus_addr)
4383 +                       return 0;
4384 +
4385 +               g_cbVirtAddr = virtual_page;
4386 +               g_cbBusAddr = bus_addr & ~4095;
4387 +               g_cacheMiss++;
4388 +
4389 +               return (void __iomem *)bus_addr;
4390 +       }
4391 +}
4392 +
4393 +//do the same as above, by query our virt->bus cache
4394 +static inline void __iomem *UserVirtualToBusViaCache(void __user *pUser)
4395 +{
4396 +       int count;
4397 +       //get the page and its offset
4398 +       unsigned long virtual_page = (unsigned long)pUser & ~4095;
4399 +       unsigned long page_offset = (unsigned long)pUser & 4095;
4400 +       unsigned long bus_addr;
4401 +
4402 +       if (pUser >= g_pMinPhys && pUser < g_pMaxPhys)
4403 +       {
4404 +               PRINTK_VERBOSE(KERN_DEBUG "user->phys passthrough on %p\n", pUser);
4405 +               return (void __iomem *)((unsigned long)pUser + g_physOffset);
4406 +       }
4407 +
4408 +       //check the cache for our entry
4409 +       for (count = 0; count < VIRT_TO_BUS_CACHE_SIZE; count++)
4410 +               if (g_virtAddr[count] == virtual_page)
4411 +               {
4412 +                       bus_addr = g_busAddr[count] + page_offset;
4413 +                       g_cacheHit++;
4414 +                       return (void __iomem *)bus_addr;
4415 +               }
4416 +
4417 +       //not found, look up manually and then insert its page address
4418 +       bus_addr = (unsigned long)UserVirtualToBus(pUser);
4419 +
4420 +       if (!bus_addr)
4421 +               return 0;
4422 +
4423 +       g_virtAddr[g_cacheInsertAt] = virtual_page;
4424 +       g_busAddr[g_cacheInsertAt] = bus_addr & ~4095;
4425 +
4426 +       //round robin
4427 +       g_cacheInsertAt++;
4428 +       if (g_cacheInsertAt == VIRT_TO_BUS_CACHE_SIZE)
4429 +               g_cacheInsertAt = 0;
4430 +
4431 +       g_cacheMiss++;
4432 +
4433 +       return (void __iomem *)bus_addr;
4434 +}
4435 +
4436 +/***** FILE OPERATIONS ****/
4437 +static int Open(struct inode *pInode, struct file *pFile)
4438 +{
4439 +       PRINTK(KERN_DEBUG "file opening: %d/%d\n", imajor(pInode), iminor(pInode));
4440 +
4441 +       //check which device we are
4442 +       if (iminor(pInode) == 0)                //4k
4443 +       {
4444 +               //only one at a time
4445 +               if (!atomic_dec_and_test(&g_oneLock4k))
4446 +               {
4447 +                       atomic_inc(&g_oneLock4k);
4448 +                       return -EBUSY;
4449 +               }
4450 +       }
4451 +       else
4452 +               return -EINVAL;
4453 +
4454 +       //todo there will be trouble if two different processes open the files
4455 +
4456 +       //reset after any file is opened
4457 +       g_pMinPhys = (void __user *)-1;
4458 +       g_pMaxPhys = (void __user *)0;
4459 +       g_physOffset = 0;
4460 +       g_cmaHandle = 0;
4461 +
4462 +       return 0;
4463 +}
4464 +
4465 +static int Release(struct inode *pInode, struct file *pFile)
4466 +{
4467 +       PRINTK(KERN_DEBUG "file closing, %d pages tracked\n", g_trackedPages);
4468 +       if (g_trackedPages)
4469 +               PRINTK(KERN_ERR "we\'re leaking memory!\n");
4470 +
4471 +       //wait for any dmas to finish
4472 +       DmaWaitAll();
4473 +
4474 +       //free this memory on the application closing the file or it crashing (implicitly closing the file)
4475 +       if (g_cmaHandle)
4476 +       {
4477 +               PRINTK(KERN_DEBUG "unlocking vc memory\n");
4478 +               if (UnlockVcMemory(g_cmaHandle))
4479 +                       PRINTK(KERN_ERR "uh-oh, unable to unlock vc memory!\n");
4480 +               PRINTK(KERN_DEBUG "releasing vc memory\n");
4481 +               if (ReleaseVcMemory(g_cmaHandle))
4482 +                       PRINTK(KERN_ERR "uh-oh, unable to release vc memory!\n");
4483 +       }
4484 +
4485 +       if (iminor(pInode) == 0)
4486 +               atomic_inc(&g_oneLock4k);
4487 +       else
4488 +               return -EINVAL;
4489 +
4490 +       return 0;
4491 +}
4492 +
4493 +static struct DmaControlBlock __user *DmaPrepare(struct DmaControlBlock __user *pUserCB, int *pError)
4494 +{
4495 +       struct DmaControlBlock kernCB;
4496 +       struct DmaControlBlock __user *pUNext;
4497 +       void __iomem *pSourceBus, __iomem *pDestBus;
4498 +
4499 +       //get the control block into kernel memory so we can work on it
4500 +       if (copy_from_user(&kernCB, pUserCB, sizeof(struct DmaControlBlock)) != 0)
4501 +       {
4502 +               PRINTK(KERN_ERR "copy_from_user failed for user cb %p\n", pUserCB);
4503 +               *pError = 1;
4504 +               return 0;
4505 +       }
4506 +
4507 +       if (kernCB.m_pSourceAddr == 0 || kernCB.m_pDestAddr == 0)
4508 +       {
4509 +               PRINTK(KERN_ERR "faulty source (%p) dest (%p) addresses for user cb %p\n",
4510 +                       kernCB.m_pSourceAddr, kernCB.m_pDestAddr, pUserCB);
4511 +               *pError = 1;
4512 +               return 0;
4513 +       }
4514 +
4515 +       pSourceBus = UserVirtualToBusViaCache(kernCB.m_pSourceAddr);
4516 +       pDestBus = UserVirtualToBusViaCache(kernCB.m_pDestAddr);
4517 +
4518 +       if (!pSourceBus || !pDestBus)
4519 +       {
4520 +               PRINTK(KERN_ERR "virtual to bus translation failure for source/dest %p/%p->%p/%p\n",
4521 +                               kernCB.m_pSourceAddr, kernCB.m_pDestAddr,
4522 +                               pSourceBus, pDestBus);
4523 +               *pError = 1;
4524 +               return 0;
4525 +       }
4526 +
4527 +       //update the user structure with the new bus addresses
4528 +       kernCB.m_pSourceAddr = pSourceBus;
4529 +       kernCB.m_pDestAddr = pDestBus;
4530 +
4531 +       PRINTK_VERBOSE(KERN_DEBUG "final source %p dest %p\n", kernCB.m_pSourceAddr, kernCB.m_pDestAddr);
4532 +
4533 +       //sort out the bus address for the next block
4534 +       pUNext = kernCB.m_pNext;
4535 +
4536 +       if (kernCB.m_pNext)
4537 +       {
4538 +               void __iomem *pNextBus;
4539 +               pNextBus = UserVirtualToBusViaCbCache(kernCB.m_pNext);
4540 +
4541 +               if (!pNextBus)
4542 +               {
4543 +                       PRINTK(KERN_ERR "virtual to bus translation failure for m_pNext\n");
4544 +                       *pError = 1;
4545 +                       return 0;
4546 +               }
4547 +
4548 +               //update the pointer with the bus address
4549 +               kernCB.m_pNext = pNextBus;
4550 +       }
4551 +
4552 +       //write it back to user space
4553 +       if (copy_to_user(pUserCB, &kernCB, sizeof(struct DmaControlBlock)) != 0)
4554 +       {
4555 +               PRINTK(KERN_ERR "copy_to_user failed for cb %p\n", pUserCB);
4556 +               *pError = 1;
4557 +               return 0;
4558 +       }
4559 +
4560 +       __cpuc_flush_dcache_area(pUserCB, 32);
4561 +
4562 +       *pError = 0;
4563 +       return pUNext;
4564 +}
4565 +
4566 +static int DmaKick(struct DmaControlBlock __user *pUserCB)
4567 +{
4568 +       void __iomem *pBusCB;
4569 +
4570 +       pBusCB = UserVirtualToBusViaCbCache(pUserCB);
4571 +       if (!pBusCB)
4572 +       {
4573 +               PRINTK(KERN_ERR "virtual to bus translation failure for cb\n");
4574 +               return 1;
4575 +       }
4576 +
4577 +       //flush_cache_all();
4578 +
4579 +       bcm_dma_start(g_pDmaChanBase, (dma_addr_t)pBusCB);
4580 +
4581 +       return 0;
4582 +}
4583 +
4584 +static void DmaWaitAll(void)
4585 +{
4586 +       int counter = 0;
4587 +       volatile int inner_count;
4588 +       volatile unsigned int cs;
4589 +       unsigned long time_before, time_after;
4590 +
4591 +       time_before = jiffies;
4592 +       //bcm_dma_wait_idle(g_pDmaChanBase);
4593 +       dsb();
4594 +
4595 +       cs = readl(g_pDmaChanBase);
4596 +
4597 +       while ((cs & 1) == 1)
4598 +       {
4599 +               cs = readl(g_pDmaChanBase);
4600 +               counter++;
4601 +
4602 +               for (inner_count = 0; inner_count < 32; inner_count++);
4603 +
4604 +               asm volatile ("MCR p15,0,r0,c7,c0,4 \n");
4605 +               //cpu_do_idle();
4606 +               if (counter >= 1000000)
4607 +               {
4608 +                       PRINTK(KERN_WARNING "DMA failed to finish in a timely fashion\n");
4609 +                       break;
4610 +               }
4611 +       }
4612 +       time_after = jiffies;
4613 +       PRINTK_VERBOSE(KERN_DEBUG "done, counter %d, cs %08x", counter, cs);
4614 +       PRINTK_VERBOSE(KERN_DEBUG "took %ld jiffies, %d HZ\n", time_after - time_before, HZ);
4615 +}
4616 +
4617 +static long Ioctl(struct file *pFile, unsigned int cmd, unsigned long arg)
4618 +{
4619 +       int error = 0;
4620 +       PRINTK_VERBOSE(KERN_DEBUG "ioctl cmd %x arg %lx\n", cmd, arg);
4621 +
4622 +       switch (cmd)
4623 +       {
4624 +       case DMA_PREPARE:
4625 +       case DMA_PREPARE_KICK:
4626 +       case DMA_PREPARE_KICK_WAIT:
4627 +               {
4628 +                       struct DmaControlBlock __user *pUCB = (struct DmaControlBlock *)arg;
4629 +                       int steps = 0;
4630 +                       unsigned long start_time = jiffies;
4631 +                       (void)start_time;
4632 +
4633 +                       //flush our address cache
4634 +                       FlushAddrCache();
4635 +
4636 +                       PRINTK_VERBOSE(KERN_DEBUG "dma prepare\n");
4637 +
4638 +                       //do virtual to bus translation for each entry
4639 +                       do
4640 +                       {
4641 +                               pUCB = DmaPrepare(pUCB, &error);
4642 +                       } while (error == 0 && ++steps && pUCB);
4643 +                       PRINTK_VERBOSE(KERN_DEBUG "prepare done in %d steps, %ld\n", steps, jiffies - start_time);
4644 +
4645 +                       //carry straight on if we want to kick too
4646 +                       if (cmd == DMA_PREPARE || error)
4647 +                       {
4648 +                               PRINTK_VERBOSE(KERN_DEBUG "falling out\n");
4649 +                               return error ? -EINVAL : 0;
4650 +                       }
4651 +               }
4652 +       case DMA_KICK:
4653 +               PRINTK_VERBOSE(KERN_DEBUG "dma begin\n");
4654 +
4655 +               if (cmd == DMA_KICK)
4656 +                       FlushAddrCache();
4657 +
4658 +               DmaKick((struct DmaControlBlock __user *)arg);
4659 +
4660 +               if (cmd != DMA_PREPARE_KICK_WAIT)
4661 +                       break;
4662 +/*     case DMA_WAIT_ONE:
4663 +               //PRINTK(KERN_DEBUG "dma wait one\n");
4664 +               break;*/
4665 +       case DMA_WAIT_ALL:
4666 +               //PRINTK(KERN_DEBUG "dma wait all\n");
4667 +               DmaWaitAll();
4668 +               break;
4669 +       case DMA_MAX_BURST:
4670 +               if (g_dmaChan == 0)
4671 +                       return 10;
4672 +               else
4673 +                       return 5;
4674 +       case DMA_SET_MIN_PHYS:
4675 +               g_pMinPhys = (void __user *)arg;
4676 +               PRINTK(KERN_DEBUG "min/max user/phys bypass set to %p %p\n", g_pMinPhys, g_pMaxPhys);
4677 +               break;
4678 +       case DMA_SET_MAX_PHYS:
4679 +               g_pMaxPhys = (void __user *)arg;
4680 +               PRINTK(KERN_DEBUG "min/max user/phys bypass set to %p %p\n", g_pMinPhys, g_pMaxPhys);
4681 +               break;
4682 +       case DMA_SET_PHYS_OFFSET:
4683 +               g_physOffset = arg;
4684 +               PRINTK(KERN_DEBUG "user/phys bypass offset set to %ld\n", g_physOffset);
4685 +               break;
4686 +       case DMA_CMA_SET_SIZE:
4687 +       {
4688 +               unsigned int pBusAddr;
4689 +
4690 +               if (g_cmaHandle)
4691 +               {
4692 +                       PRINTK(KERN_ERR "memory has already been allocated (handle %d)\n", g_cmaHandle);
4693 +                       return -EINVAL;
4694 +               }
4695 +
4696 +               PRINTK(KERN_INFO "allocating %ld bytes of VC memory\n", arg * 4096);
4697 +
4698 +               //get the memory
4699 +               if (AllocateVcMemory(&g_cmaHandle, arg * 4096, 4096, MEM_FLAG_L1_NONALLOCATING | MEM_FLAG_NO_INIT | MEM_FLAG_HINT_PERMALOCK))
4700 +               {
4701 +                       PRINTK(KERN_ERR "failed to allocate %ld bytes of VC memory\n", arg * 4096);
4702 +                       g_cmaHandle = 0;
4703 +                       return -EINVAL;
4704 +               }
4705 +
4706 +               //get an address for it
4707 +               PRINTK(KERN_INFO "trying to map VC memory\n");
4708 +
4709 +               if (LockVcMemory(&pBusAddr, g_cmaHandle))
4710 +               {
4711 +                       PRINTK(KERN_ERR "failed to map CMA handle %d, releasing memory\n", g_cmaHandle);
4712 +                       ReleaseVcMemory(g_cmaHandle);
4713 +                       g_cmaHandle = 0;
4714 +               }
4715 +
4716 +               PRINTK(KERN_INFO "bus address for CMA memory is %x\n", pBusAddr);
4717 +               return pBusAddr;
4718 +       }
4719 +       case DMA_GET_VERSION:
4720 +               PRINTK(KERN_DEBUG "returning version number, %d\n", VERSION_NUMBER);
4721 +               return VERSION_NUMBER;
4722 +       default:
4723 +               PRINTK(KERN_DEBUG "unknown ioctl: %d\n", cmd);
4724 +               return -EINVAL;
4725 +       }
4726 +
4727 +       return 0;
4728 +}
4729 +
4730 +static ssize_t Read(struct file *pFile, char __user *pUser, size_t count, loff_t *offp)
4731 +{
4732 +       return -EIO;
4733 +}
4734 +
4735 +static int Mmap(struct file *pFile, struct vm_area_struct *pVma)
4736 +{
4737 +       struct PageList *pPages;
4738 +       struct VmaPageList *pVmaList;
4739 +
4740 +       PRINTK_VERBOSE(KERN_DEBUG "MMAP vma %p, length %ld (%s %d)\n",
4741 +               pVma, pVma->vm_end - pVma->vm_start,
4742 +               current->comm, current->pid);
4743 +       PRINTK_VERBOSE(KERN_DEBUG "MMAP %p %d (tracked %d)\n", pVma, current->pid, g_trackedPages);
4744 +
4745 +       //make a new page list
4746 +       pPages = (struct PageList *)kmalloc(sizeof(struct PageList), GFP_KERNEL);
4747 +       if (!pPages)
4748 +       {
4749 +               PRINTK(KERN_ERR "couldn\'t allocate a new page list (%s %d)\n",
4750 +                       current->comm, current->pid);
4751 +               return -ENOMEM;
4752 +       }
4753 +
4754 +       //clear the page list
4755 +       pPages->m_used = 0;
4756 +       pPages->m_pNext = 0;
4757 +
4758 +       //insert our vma and new page list somewhere
4759 +       if (!pVma->vm_private_data)
4760 +       {
4761 +               struct VmaPageList *pList;
4762 +
4763 +               PRINTK_VERBOSE(KERN_DEBUG "new vma list, making new one (%s %d)\n",
4764 +                       current->comm, current->pid);
4765 +
4766 +               //make a new vma list
4767 +               pList = (struct VmaPageList *)kmalloc(sizeof(struct VmaPageList), GFP_KERNEL);
4768 +               if (!pList)
4769 +               {
4770 +                       PRINTK(KERN_ERR "couldn\'t allocate vma page list (%s %d)\n",
4771 +                               current->comm, current->pid);
4772 +                       kfree(pPages);
4773 +                       return -ENOMEM;
4774 +               }
4775 +
4776 +               //clear this list
4777 +               pVma->vm_private_data = (void *)pList;
4778 +               pList->m_refCount = 0;
4779 +       }
4780 +
4781 +       pVmaList = (struct VmaPageList *)pVma->vm_private_data;
4782 +
4783 +       //add it to the vma list
4784 +       pVmaList->m_pPageHead = pPages;
4785 +       pVmaList->m_pPageTail = pPages;
4786 +
4787 +       pVma->vm_ops = &g_vmOps4k;
4788 +       pVma->vm_flags |= VM_IO;
4789 +
4790 +       VmaOpen4k(pVma);
4791 +
4792 +       return 0;
4793 +}
4794 +
4795 +/****** VMA OPERATIONS ******/
4796 +
4797 +static void VmaOpen4k(struct vm_area_struct *pVma)
4798 +{
4799 +       struct VmaPageList *pVmaList;
4800 +
4801 +       PRINTK_VERBOSE(KERN_DEBUG "vma open %p private %p (%s %d), %d live pages\n", pVma, pVma->vm_private_data, current->comm, current->pid, g_trackedPages);
4802 +       PRINTK_VERBOSE(KERN_DEBUG "OPEN %p %d %ld pages (tracked pages %d)\n",
4803 +               pVma, current->pid, (pVma->vm_end - pVma->vm_start) >> 12,
4804 +               g_trackedPages);
4805 +
4806 +       pVmaList = (struct VmaPageList *)pVma->vm_private_data;
4807 +
4808 +       if (pVmaList)
4809 +       {
4810 +               pVmaList->m_refCount++;
4811 +               PRINTK_VERBOSE(KERN_DEBUG "ref count is now %d\n", pVmaList->m_refCount);
4812 +       }
4813 +       else
4814 +       {
4815 +               PRINTK_VERBOSE(KERN_DEBUG "err, open but no vma page list\n");
4816 +       }
4817 +}
4818 +
4819 +static void VmaClose4k(struct vm_area_struct *pVma)
4820 +{
4821 +       struct VmaPageList *pVmaList;
4822 +       int freed = 0;
4823 +
4824 +       PRINTK_VERBOSE(KERN_DEBUG "vma close %p private %p (%s %d)\n", pVma, pVma->vm_private_data, current->comm, current->pid);
4825 +
4826 +       //wait for any dmas to finish
4827 +       DmaWaitAll();
4828 +
4829 +       //find our vma in the list
4830 +       pVmaList = (struct VmaPageList *)pVma->vm_private_data;
4831 +
4832 +       //may be a fork
4833 +       if (pVmaList)
4834 +       {
4835 +               struct PageList *pPages;
4836 +
4837 +               pVmaList->m_refCount--;
4838 +
4839 +               if (pVmaList->m_refCount == 0)
4840 +               {
4841 +                       PRINTK_VERBOSE(KERN_DEBUG "found vma, freeing pages (%s %d)\n",
4842 +                               current->comm, current->pid);
4843 +
4844 +                       pPages = pVmaList->m_pPageHead;
4845 +
4846 +                       if (!pPages)
4847 +                       {
4848 +                               PRINTK(KERN_ERR "no page list (%s %d)!\n",
4849 +                                       current->comm, current->pid);
4850 +                               return;
4851 +                       }
4852 +
4853 +                       while (pPages)
4854 +                       {
4855 +                               struct PageList *next;
4856 +                               int count;
4857 +
4858 +                               PRINTK_VERBOSE(KERN_DEBUG "page list (%s %d)\n",
4859 +                                       current->comm, current->pid);
4860 +
4861 +                               next = pPages->m_pNext;
4862 +                               for (count = 0; count < pPages->m_used; count++)
4863 +                               {
4864 +                                       PRINTK_VERBOSE(KERN_DEBUG "freeing page %p (%s %d)\n",
4865 +                                               pPages->m_pPages[count],
4866 +                                               current->comm, current->pid);
4867 +                                       __free_pages(pPages->m_pPages[count], 0);
4868 +                                       g_trackedPages--;
4869 +                                       freed++;
4870 +                               }
4871 +
4872 +                               PRINTK_VERBOSE(KERN_DEBUG "freeing page list (%s %d)\n",
4873 +                                       current->comm, current->pid);
4874 +                               kfree(pPages);
4875 +                               pPages = next;
4876 +                       }
4877 +
4878 +                       //remove our vma from the list
4879 +                       kfree(pVmaList);
4880 +                       pVma->vm_private_data = 0;
4881 +               }
4882 +               else
4883 +               {
4884 +                       PRINTK_VERBOSE(KERN_DEBUG "ref count is %d, not closing\n", pVmaList->m_refCount);
4885 +               }
4886 +       }
4887 +       else
4888 +       {
4889 +               PRINTK_VERBOSE(KERN_ERR "uh-oh, vma %p not found (%s %d)!\n", pVma, current->comm, current->pid);
4890 +               PRINTK_VERBOSE(KERN_ERR "CLOSE ERR\n");
4891 +       }
4892 +
4893 +       PRINTK_VERBOSE(KERN_DEBUG "CLOSE %p %d %d pages (tracked pages %d)",
4894 +               pVma, current->pid, freed, g_trackedPages);
4895 +
4896 +       PRINTK_VERBOSE(KERN_DEBUG "%d pages open\n", g_trackedPages);
4897 +}
4898 +
4899 +static int VmaFault4k(struct vm_area_struct *pVma, struct vm_fault *pVmf)
4900 +{
4901 +       PRINTK_VERBOSE(KERN_DEBUG "vma fault for vma %p private %p at offset %ld (%s %d)\n", pVma, pVma->vm_private_data, pVmf->pgoff,
4902 +               current->comm, current->pid);
4903 +       PRINTK_VERBOSE(KERN_DEBUG "FAULT\n");
4904 +       pVmf->page = alloc_page(GFP_KERNEL);
4905 +
4906 +       if (pVmf->page)
4907 +       {
4908 +               PRINTK_VERBOSE(KERN_DEBUG "alloc page virtual %p\n", page_address(pVmf->page));
4909 +       }
4910 +
4911 +       if (!pVmf->page)
4912 +       {
4913 +               PRINTK(KERN_ERR "vma fault oom (%s %d)\n", current->comm, current->pid);
4914 +               return VM_FAULT_OOM;
4915 +       }
4916 +       else
4917 +       {
4918 +               struct VmaPageList *pVmaList;
4919 +
4920 +               get_page(pVmf->page);
4921 +               g_trackedPages++;
4922 +
4923 +               //find our vma in the list
4924 +               pVmaList = (struct VmaPageList *)pVma->vm_private_data;
4925 +
4926 +               if (pVmaList)
4927 +               {
4928 +                       PRINTK_VERBOSE(KERN_DEBUG "vma found (%s %d)\n", current->comm, current->pid);
4929 +
4930 +                       if (pVmaList->m_pPageTail->m_used == PAGES_PER_LIST)
4931 +                       {
4932 +                               PRINTK_VERBOSE(KERN_DEBUG "making new page list (%s %d)\n", current->comm, current->pid);
4933 +                               //making a new page list
4934 +                               pVmaList->m_pPageTail->m_pNext = (struct PageList *)kmalloc(sizeof(struct PageList), GFP_KERNEL);
4935 +                               if (!pVmaList->m_pPageTail->m_pNext)
4936 +                                       return -ENOMEM;
4937 +
4938 +                               //update the tail pointer
4939 +                               pVmaList->m_pPageTail = pVmaList->m_pPageTail->m_pNext;
4940 +                               pVmaList->m_pPageTail->m_used = 0;
4941 +                               pVmaList->m_pPageTail->m_pNext = 0;
4942 +                       }
4943 +
4944 +                       PRINTK_VERBOSE(KERN_DEBUG "adding page to list (%s %d)\n", current->comm, current->pid);
4945 +
4946 +                       pVmaList->m_pPageTail->m_pPages[pVmaList->m_pPageTail->m_used] = pVmf->page;
4947 +                       pVmaList->m_pPageTail->m_used++;
4948 +               }
4949 +               else
4950 +                       PRINTK(KERN_ERR "returned page for vma we don\'t know %p (%s %d)\n", pVma, current->comm, current->pid);
4951 +
4952 +               return 0;
4953 +       }
4954 +}
4955 +
4956 +/****** GENERIC FUNCTIONS ******/
4957 +static int __init dmaer_init(void)
4958 +{
4959 +       int result = alloc_chrdev_region(&g_majorMinor, 0, 1, "dmaer");
4960 +       if (result < 0)
4961 +       {
4962 +               PRINTK(KERN_ERR "unable to get major device number\n");
4963 +               return result;
4964 +       }
4965 +       else
4966 +               PRINTK(KERN_DEBUG "major device number %d\n", MAJOR(g_majorMinor));
4967 +
4968 +       PRINTK(KERN_DEBUG "vma list size %d, page list size %d, page size %ld\n",
4969 +               sizeof(struct VmaPageList), sizeof(struct PageList), PAGE_SIZE);
4970 +
4971 +       //get a dma channel to work with
4972 +       result = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST, (void **)&g_pDmaChanBase, &g_dmaIrq);
4973 +
4974 +       //uncomment to force to channel 0
4975 +       //result = 0;
4976 +       //g_pDmaChanBase = 0xce808000;
4977 +
4978 +       if (result < 0)
4979 +       {
4980 +               PRINTK(KERN_ERR "failed to allocate dma channel\n");
4981 +               cdev_del(&g_cDev);
4982 +               unregister_chrdev_region(g_majorMinor, 1);
4983 +       }
4984 +
4985 +       //reset the channel
4986 +       PRINTK(KERN_DEBUG "allocated dma channel %d (%p), initial state %08x\n", result, g_pDmaChanBase, *g_pDmaChanBase);
4987 +       *g_pDmaChanBase = 1 << 31;
4988 +       PRINTK(KERN_DEBUG "post-reset %08x\n", *g_pDmaChanBase);
4989 +
4990 +       g_dmaChan = result;
4991 +
4992 +       //clear the cache stats
4993 +       g_cacheHit = 0;
4994 +       g_cacheMiss = 0;
4995 +
4996 +       //register our device - after this we are go go go
4997 +       cdev_init(&g_cDev, &g_fOps);
4998 +       g_cDev.owner = THIS_MODULE;
4999 +       g_cDev.ops = &g_fOps;
5000 +
5001 +       result = cdev_add(&g_cDev, g_majorMinor, 1);
5002 +       if (result < 0)
5003 +       {
5004 +               PRINTK(KERN_ERR "failed to add character device\n");
5005 +               unregister_chrdev_region(g_majorMinor, 1);
5006 +               bcm_dma_chan_free(g_dmaChan);
5007 +               return result;
5008 +       }
5009 +
5010 +       return 0;
5011 +}
5012 +
5013 +static void __exit dmaer_exit(void)
5014 +{
5015 +       PRINTK(KERN_INFO "closing dmaer device, cache stats: %d hits %d misses\n", g_cacheHit, g_cacheMiss);
5016 +       //unregister the device
5017 +       cdev_del(&g_cDev);
5018 +       unregister_chrdev_region(g_majorMinor, 1);
5019 +       //free the dma channel
5020 +       bcm_dma_chan_free(g_dmaChan);
5021 +}
5022 +
5023 +MODULE_LICENSE("Dual BSD/GPL");
5024 +MODULE_AUTHOR("Simon Hall");
5025 +module_init(dmaer_init);
5026 +module_exit(dmaer_exit);
5027 +
5028 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/arm_control.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/arm_control.h
5029 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/arm_control.h 1970-01-01 01:00:00.000000000 +0100
5030 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/arm_control.h   2013-07-06 15:25:50.000000000 +0100
5031 @@ -0,0 +1,419 @@
5032 +/*
5033 + *  linux/arch/arm/mach-bcm2708/arm_control.h
5034 + *
5035 + *  Copyright (C) 2010 Broadcom
5036 + *
5037 + * This program is free software; you can redistribute it and/or modify
5038 + * it under the terms of the GNU General Public License as published by
5039 + * the Free Software Foundation; either version 2 of the License, or
5040 + * (at your option) any later version.
5041 + *
5042 + * This program is distributed in the hope that it will be useful,
5043 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5044 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5045 + * GNU General Public License for more details.
5046 + *
5047 + * You should have received a copy of the GNU General Public License
5048 + * along with this program; if not, write to the Free Software
5049 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5050 + */
5051 +
5052 +#ifndef __BCM2708_ARM_CONTROL_H
5053 +#define __BCM2708_ARM_CONTROL_H
5054 +
5055 +/*
5056 + * Definitions and addresses for the ARM CONTROL logic
5057 + * This file is manually generated.
5058 + */
5059 +
5060 +#define ARM_BASE  0x7E00B000
5061 +
5062 +/* Basic configuration */
5063 +#define ARM_CONTROL0  HW_REGISTER_RW(ARM_BASE+0x000)
5064 +#define ARM_C0_SIZ128M   0x00000000
5065 +#define ARM_C0_SIZ256M   0x00000001
5066 +#define ARM_C0_SIZ512M   0x00000002
5067 +#define ARM_C0_SIZ1G     0x00000003
5068 +#define ARM_C0_BRESP0    0x00000000
5069 +#define ARM_C0_BRESP1    0x00000004
5070 +#define ARM_C0_BRESP2    0x00000008
5071 +#define ARM_C0_BOOTHI    0x00000010
5072 +#define ARM_C0_UNUSED05  0x00000020 /* free */
5073 +#define ARM_C0_FULLPERI  0x00000040
5074 +#define ARM_C0_UNUSED78  0x00000180 /* free */
5075 +#define ARM_C0_JTAGMASK  0x00000E00
5076 +#define ARM_C0_JTAGOFF   0x00000000
5077 +#define ARM_C0_JTAGBASH  0x00000800 /* Debug on GPIO off */
5078 +#define ARM_C0_JTAGGPIO  0x00000C00 /* Debug on GPIO on */
5079 +#define ARM_C0_APROTMSK  0x0000F000
5080 +#define ARM_C0_DBG0SYNC  0x00010000 /* VPU0 halt sync */
5081 +#define ARM_C0_DBG1SYNC  0x00020000 /* VPU1 halt sync */
5082 +#define ARM_C0_SWDBGREQ  0x00040000 /* HW debug request */
5083 +#define ARM_C0_PASSHALT  0x00080000 /* ARM halt passed to debugger */
5084 +#define ARM_C0_PRIO_PER  0x00F00000 /* per priority mask */
5085 +#define ARM_C0_PRIO_L2   0x0F000000
5086 +#define ARM_C0_PRIO_UC   0xF0000000
5087 +
5088 +#define ARM_C0_APROTPASS  0x0000A000 /* Translate 1:1 */
5089 +#define ARM_C0_APROTUSER  0x00000000 /* Only user mode */
5090 +#define ARM_C0_APROTSYST  0x0000F000 /* Only system mode */
5091 +
5092 +
5093 +#define ARM_CONTROL1  HW_REGISTER_RW(ARM_BASE+0x440)
5094 +#define ARM_C1_TIMER     0x00000001 /* re-route timer IRQ  to VC */
5095 +#define ARM_C1_MAIL      0x00000002 /* re-route Mail IRQ   to VC */
5096 +#define ARM_C1_BELL0     0x00000004 /* re-route Doorbell 0 to VC */
5097 +#define ARM_C1_BELL1     0x00000008 /* re-route Doorbell 1 to VC */
5098 +#define ARM_C1_PERSON    0x00000100 /* peripherals on */
5099 +#define ARM_C1_REQSTOP   0x00000200 /* ASYNC bridge request stop */
5100 +
5101 +#define ARM_STATUS    HW_REGISTER_RW(ARM_BASE+0x444)
5102 +#define ARM_S_ACKSTOP    0x80000000 /* Bridge stopped */
5103 +#define ARM_S_READPEND   0x000003FF /* pending reads counter */
5104 +#define ARM_S_WRITPEND   0x000FFC00 /* pending writes counter */
5105 +
5106 +#define ARM_ERRHALT   HW_REGISTER_RW(ARM_BASE+0x448)
5107 +#define ARM_EH_PERIBURST  0x00000001 /* Burst write seen on peri bus */
5108 +#define ARM_EH_ILLADDRS1  0x00000002 /* Address bits 25-27 error */
5109 +#define ARM_EH_ILLADDRS2  0x00000004 /* Address bits 31-28 error */
5110 +#define ARM_EH_VPU0HALT   0x00000008 /* VPU0 halted & in debug mode */
5111 +#define ARM_EH_VPU1HALT   0x00000010 /* VPU1 halted & in debug mode */
5112 +#define ARM_EH_ARMHALT    0x00000020 /* ARM in halted debug mode */
5113 +
5114 +#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
5115 +#define ARM_ID        HW_REGISTER_RW(ARM_BASE+0x44C)
5116 +#define ARM_IDVAL        0x364D5241
5117 +
5118 +/* Translation memory */
5119 +#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
5120 +/* 32 locations: 0x100.. 0x17F */
5121 +/* 32 spare means we CAN go to 64 pages.... */
5122 +
5123 +
5124 +/* Interrupts */
5125 +#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200)        /* Top IRQ bits */
5126 +#define ARM_I0_TIMER    0x00000001 /* timer IRQ */
5127 +#define ARM_I0_MAIL     0x00000002 /* Mail IRQ */
5128 +#define ARM_I0_BELL0    0x00000004 /* Doorbell 0 */
5129 +#define ARM_I0_BELL1    0x00000008 /* Doorbell 1 */
5130 +#define ARM_I0_BANK1    0x00000100 /* Bank1 IRQ */
5131 +#define ARM_I0_BANK2    0x00000200 /* Bank2 IRQ */
5132 +
5133 +#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
5134 +/* todo: all I1_interrupt sources */
5135 +#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
5136 +/* todo: all I2_interrupt sources */
5137 +
5138 +#define ARM_IRQ_FAST  HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
5139 +#define ARM_IF_INDEX    0x0000007F     /* FIQ select */
5140 +#define ARM_IF_ENABLE   0x00000080     /* FIQ enable */
5141 +#define ARM_IF_VCMASK   0x0000003F     /* FIQ = (index from VC source) */
5142 +#define ARM_IF_TIMER    0x00000040     /* FIQ = ARM timer */
5143 +#define ARM_IF_MAIL     0x00000041     /* FIQ = ARM Mail */
5144 +#define ARM_IF_BELL0    0x00000042     /* FIQ = ARM Doorbell 0 */
5145 +#define ARM_IF_BELL1    0x00000043     /* FIQ = ARM Doorbell 1 */
5146 +#define ARM_IF_VP0HALT  0x00000044     /* FIQ = VPU0 Halt seen */
5147 +#define ARM_IF_VP1HALT  0x00000045     /* FIQ = VPU1 Halt seen */
5148 +#define ARM_IF_ILLEGAL  0x00000046     /* FIQ = Illegal access seen */
5149 +
5150 +#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
5151 +#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
5152 +#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
5153 +#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
5154 +#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
5155 +#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
5156 +#define ARM_IE_TIMER    0x00000001     /* Timer IRQ */
5157 +#define ARM_IE_MAIL     0x00000002     /* Mail IRQ */
5158 +#define ARM_IE_BELL0    0x00000004     /* Doorbell 0 */
5159 +#define ARM_IE_BELL1    0x00000008     /* Doorbell 1 */
5160 +#define ARM_IE_VP0HALT  0x00000010     /* VPU0 Halt */
5161 +#define ARM_IE_VP1HALT  0x00000020     /* VPU1 Halt */
5162 +#define ARM_IE_ILLEGAL  0x00000040     /* Illegal access seen */
5163 +
5164 +/* Timer */
5165 +/* For reg. fields see sp804 spec. */
5166 +#define ARM_T_LOAD    HW_REGISTER_RW(ARM_BASE+0x400)
5167 +#define ARM_T_VALUE   HW_REGISTER_RW(ARM_BASE+0x404)
5168 +#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
5169 +#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
5170 +#define ARM_T_RAWIRQ  HW_REGISTER_RW(ARM_BASE+0x410)
5171 +#define ARM_T_MSKIRQ  HW_REGISTER_RW(ARM_BASE+0x414)
5172 +#define ARM_T_RELOAD  HW_REGISTER_RW(ARM_BASE+0x418)
5173 +#define ARM_T_PREDIV  HW_REGISTER_RW(ARM_BASE+0x41c)
5174 +#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
5175 +
5176 +#define TIMER_CTRL_ONESHOT  (1 << 0)
5177 +#define TIMER_CTRL_32BIT    (1 << 1)
5178 +#define TIMER_CTRL_DIV1     (0 << 2)
5179 +#define TIMER_CTRL_DIV16    (1 << 2)
5180 +#define TIMER_CTRL_DIV256   (2 << 2)
5181 +#define TIMER_CTRL_IE       (1 << 5)
5182 +#define TIMER_CTRL_PERIODIC (1 << 6)
5183 +#define TIMER_CTRL_ENABLE   (1 << 7)
5184 +#define TIMER_CTRL_DBGHALT  (1 << 8)
5185 +#define TIMER_CTRL_ENAFREE  (1 << 9)
5186 +#define TIMER_CTRL_FREEDIV_SHIFT 16)
5187 +#define TIMER_CTRL_FREEDIV_MASK  0xff
5188 +
5189 +/* Semaphores, Doorbells, Mailboxes */
5190 +#define ARM_SBM_OWN0  (ARM_BASE+0x800)
5191 +#define ARM_SBM_OWN1  (ARM_BASE+0x900)
5192 +#define ARM_SBM_OWN2  (ARM_BASE+0xA00)
5193 +#define ARM_SBM_OWN3  (ARM_BASE+0xB00)
5194 +
5195 +/* MAILBOXES
5196 + * Register flags are common across all
5197 + * owner registers. See end of this section
5198 + *
5199 + * Semaphores, Doorbells, Mailboxes Owner 0
5200 + *
5201 + */
5202 +
5203 +#define ARM_0_SEMS       HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
5204 +#define ARM_0_SEM0       HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
5205 +#define ARM_0_SEM1       HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
5206 +#define ARM_0_SEM2       HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
5207 +#define ARM_0_SEM3       HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
5208 +#define ARM_0_SEM4       HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
5209 +#define ARM_0_SEM5       HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
5210 +#define ARM_0_SEM6       HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
5211 +#define ARM_0_SEM7       HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
5212 +#define ARM_0_BELL0      HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
5213 +#define ARM_0_BELL1      HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
5214 +#define ARM_0_BELL2      HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
5215 +#define ARM_0_BELL3      HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
5216 +/* MAILBOX 0 access in Owner 0 area */
5217 +/* Some addresses should ONLY be used by owner 0 */
5218 +#define ARM_0_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN0+0x80)  /* .. 0x8C (4 locations) */
5219 +#define ARM_0_MAIL0_RD   HW_REGISTER_RW(ARM_SBM_OWN0+0x80)  /* .. 0x8C (4 locations) Normal read */
5220 +#define ARM_0_MAIL0_POL  HW_REGISTER_RW(ARM_SBM_OWN0+0x90)  /* none-pop read */
5221 +#define ARM_0_MAIL0_SND  HW_REGISTER_RW(ARM_SBM_OWN0+0x94)  /* Sender read (only LS 2 bits) */
5222 +#define ARM_0_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN0+0x98)  /* Status read */
5223 +#define ARM_0_MAIL0_CNF  HW_REGISTER_RW(ARM_SBM_OWN0+0x9C)  /* Config read/write */
5224 +/* MAILBOX 1 access in Owner 0 area */
5225 +/* Owner 0 should only WRITE to this mailbox */
5226 +#define ARM_0_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN0+0xA0)   /* .. 0xAC (4 locations) */
5227 +/*#define ARM_0_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
5228 +/*#define ARM_0_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
5229 +/*#define ARM_0_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
5230 +#define ARM_0_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN0+0xB8)   /* Status read */
5231 +/*#define ARM_0_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
5232 +/* General SEM, BELL, MAIL config/status */
5233 +#define ARM_0_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN0+0xE0)  /* semaphore clear/debug register */
5234 +#define ARM_0_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN0+0xE4)  /* Doorbells clear/debug register */
5235 +#define ARM_0_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN0+0xF8)  /* ALL interrupts */
5236 +#define ARM_0_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN0+0xFC)  /* IRQS pending for owner 0 */
5237 +
5238 +/* Semaphores, Doorbells, Mailboxes Owner 1 */
5239 +#define ARM_1_SEMS       HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
5240 +#define ARM_1_SEM0       HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
5241 +#define ARM_1_SEM1       HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
5242 +#define ARM_1_SEM2       HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
5243 +#define ARM_1_SEM3       HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
5244 +#define ARM_1_SEM4       HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
5245 +#define ARM_1_SEM5       HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
5246 +#define ARM_1_SEM6       HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
5247 +#define ARM_1_SEM7       HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
5248 +#define ARM_1_BELL0      HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
5249 +#define ARM_1_BELL1      HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
5250 +#define ARM_1_BELL2      HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
5251 +#define ARM_1_BELL3      HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
5252 +/* MAILBOX 0 access in Owner 0 area */
5253 +/* Owner 1 should only WRITE to this mailbox */
5254 +#define ARM_1_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN1+0x80)  /* .. 0x8C (4 locations) */
5255 +/*#define ARM_1_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
5256 +/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
5257 +/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
5258 +#define ARM_1_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN1+0x98)  /* Status read */
5259 +/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
5260 +/* MAILBOX 1 access in Owner 0 area */
5261 +#define ARM_1_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN1+0xA0)  /* .. 0xAC (4 locations) */
5262 +#define ARM_1_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN1+0xA0)  /* .. 0xAC (4 locations) Normal read */
5263 +#define ARM_1_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN1+0xB0)  /* none-pop read */
5264 +#define ARM_1_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN1+0xB4)  /* Sender read (only LS 2 bits) */
5265 +#define ARM_1_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN1+0xB8)  /* Status read */
5266 +#define ARM_1_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
5267 +/* General SEM, BELL, MAIL config/status */
5268 +#define ARM_1_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN1+0xE0)  /* semaphore clear/debug register */
5269 +#define ARM_1_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN1+0xE4)  /* Doorbells clear/debug register */
5270 +#define ARM_1_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN1+0xFC)  /* IRQS pending for owner 1 */
5271 +#define ARM_1_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN1+0xF8)  /* ALL interrupts */
5272 +
5273 +/* Semaphores, Doorbells, Mailboxes Owner 2 */
5274 +#define ARM_2_SEMS       HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
5275 +#define ARM_2_SEM0       HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
5276 +#define ARM_2_SEM1       HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
5277 +#define ARM_2_SEM2       HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
5278 +#define ARM_2_SEM3       HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
5279 +#define ARM_2_SEM4       HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
5280 +#define ARM_2_SEM5       HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
5281 +#define ARM_2_SEM6       HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
5282 +#define ARM_2_SEM7       HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
5283 +#define ARM_2_BELL0      HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
5284 +#define ARM_2_BELL1      HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
5285 +#define ARM_2_BELL2      HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
5286 +#define ARM_2_BELL3      HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
5287 +/* MAILBOX 0 access in Owner 2 area */
5288 +/* Owner 2 should only WRITE to this mailbox */
5289 +#define ARM_2_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN2+0x80)   /* .. 0x8C (4 locations) */
5290 +/*#define ARM_2_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN2+0x80)  */ /* DO NOT USE THIS !!!!! */
5291 +/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90)  */ /* DO NOT USE THIS !!!!! */
5292 +/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94)  */ /* DO NOT USE THIS !!!!! */
5293 +#define ARM_2_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN2+0x98)   /* Status read */
5294 +/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C)  */ /* DO NOT USE THIS !!!!! */
5295 +/* MAILBOX 1 access in Owner 2 area */
5296 +/* Owner 2 should only WRITE to this mailbox */
5297 +#define ARM_2_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN2+0xA0)   /* .. 0xAC (4 locations) */
5298 +/*#define ARM_2_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
5299 +/*#define ARM_2_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
5300 +/*#define ARM_2_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
5301 +#define ARM_2_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN2+0xB8)   /* Status read */
5302 +/*#define ARM_2_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
5303 +/* General SEM, BELL, MAIL config/status */
5304 +#define ARM_2_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN2+0xE0)  /* semaphore clear/debug register */
5305 +#define ARM_2_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN2+0xE4)  /* Doorbells clear/debug register */
5306 +#define ARM_2_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN2+0xFC)  /* IRQS pending for owner 2 */
5307 +#define ARM_2_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN2+0xF8)  /* ALL interrupts */
5308 +
5309 +/* Semaphores, Doorbells, Mailboxes Owner 3 */
5310 +#define ARM_3_SEMS       HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
5311 +#define ARM_3_SEM0       HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
5312 +#define ARM_3_SEM1       HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
5313 +#define ARM_3_SEM2       HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
5314 +#define ARM_3_SEM3       HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
5315 +#define ARM_3_SEM4       HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
5316 +#define ARM_3_SEM5       HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
5317 +#define ARM_3_SEM6       HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
5318 +#define ARM_3_SEM7       HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
5319 +#define ARM_3_BELL0      HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
5320 +#define ARM_3_BELL1      HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
5321 +#define ARM_3_BELL2      HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
5322 +#define ARM_3_BELL3      HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
5323 +/* MAILBOX 0 access in Owner 3 area */
5324 +/* Owner 3 should only WRITE to this mailbox */
5325 +#define ARM_3_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN3+0x80)   /* .. 0x8C (4 locations) */
5326 +/*#define ARM_3_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN3+0x80)  */ /* DO NOT USE THIS !!!!! */
5327 +/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90)  */ /* DO NOT USE THIS !!!!! */
5328 +/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94)  */ /* DO NOT USE THIS !!!!! */
5329 +#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98)    /* Status read */
5330 +/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C)  */ /* DO NOT USE THIS !!!!! */
5331 +/* MAILBOX 1 access in Owner 3 area */
5332 +/* Owner 3 should only WRITE to this mailbox */
5333 +#define ARM_3_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN3+0xA0)   /* .. 0xAC (4 locations) */
5334 +/*#define ARM_3_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
5335 +/*#define ARM_3_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
5336 +/*#define ARM_3_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
5337 +#define ARM_3_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN3+0xB8)   /* Status read */
5338 +/*#define ARM_3_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
5339 +/* General SEM, BELL, MAIL config/status */
5340 +#define ARM_3_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN3+0xE0)  /* semaphore clear/debug register */
5341 +#define ARM_3_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN3+0xE4)  /* Doorbells clear/debug register */
5342 +#define ARM_3_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN3+0xFC)  /* IRQS pending for owner 3 */
5343 +#define ARM_3_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN3+0xF8)  /* ALL interrupts */
5344 +
5345 +
5346 +
5347 +/*  Mailbox flags. Valid for all owners */
5348 +
5349 +/* Mailbox status register (...0x98) */
5350 +#define ARM_MS_FULL       0x80000000
5351 +#define ARM_MS_EMPTY      0x40000000
5352 +#define ARM_MS_LEVEL      0x400000FF /* Max. value depdnds on mailbox depth parameter */
5353 +
5354 +/* MAILBOX config/status register (...0x9C) */
5355 +/* ANY write to this register clears the error bits! */
5356 +#define ARM_MC_IHAVEDATAIRQEN    0x00000001 /* mailbox irq enable:  has data */
5357 +#define ARM_MC_IHAVESPACEIRQEN   0x00000002 /* mailbox irq enable:  has space */
5358 +#define ARM_MC_OPPISEMPTYIRQEN   0x00000004 /* mailbox irq enable: Opp. is empty */
5359 +#define ARM_MC_MAIL_CLEAR        0x00000008 /* mailbox clear write 1, then  0 */
5360 +#define ARM_MC_IHAVEDATAIRQPEND  0x00000010 /* mailbox irq pending:  has space */
5361 +#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
5362 +#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
5363 +/* Bit 7 is unused */
5364 +#define ARM_MC_ERRNOOWN   0x00000100 /* error : none owner read from mailbox */
5365 +#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
5366 +#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
5367 +
5368 +/* Semaphore clear/debug register (...0xE0) */
5369 +#define ARM_SD_OWN0      0x00000003  /* Owner of sem 0 */
5370 +#define ARM_SD_OWN1      0x0000000C  /* Owner of sem 1 */
5371 +#define ARM_SD_OWN2      0x00000030  /* Owner of sem 2 */
5372 +#define ARM_SD_OWN3      0x000000C0  /* Owner of sem 3 */
5373 +#define ARM_SD_OWN4      0x00000300  /* Owner of sem 4 */
5374 +#define ARM_SD_OWN5      0x00000C00  /* Owner of sem 5 */
5375 +#define ARM_SD_OWN6      0x00003000  /* Owner of sem 6 */
5376 +#define ARM_SD_OWN7      0x0000C000  /* Owner of sem 7 */
5377 +#define ARM_SD_SEM0      0x00010000  /* Status of sem 0 */
5378 +#define ARM_SD_SEM1      0x00020000  /* Status of sem 1 */
5379 +#define ARM_SD_SEM2      0x00040000  /* Status of sem 2 */
5380 +#define ARM_SD_SEM3      0x00080000  /* Status of sem 3 */
5381 +#define ARM_SD_SEM4      0x00100000  /* Status of sem 4 */
5382 +#define ARM_SD_SEM5      0x00200000  /* Status of sem 5 */
5383 +#define ARM_SD_SEM6      0x00400000  /* Status of sem 6 */
5384 +#define ARM_SD_SEM7      0x00800000  /* Status of sem 7 */
5385 +
5386 +/* Doorbells clear/debug register (...0xE4) */
5387 +#define ARM_BD_OWN0      0x00000003  /* Owner of doorbell 0 */
5388 +#define ARM_BD_OWN1      0x0000000C  /* Owner of doorbell 1 */
5389 +#define ARM_BD_OWN2      0x00000030  /* Owner of doorbell 2 */
5390 +#define ARM_BD_OWN3      0x000000C0  /* Owner of doorbell 3 */
5391 +#define ARM_BD_BELL0     0x00000100  /* Status of doorbell 0 */
5392 +#define ARM_BD_BELL1     0x00000200  /* Status of doorbell 1 */
5393 +#define ARM_BD_BELL2     0x00000400  /* Status of doorbell 2 */
5394 +#define ARM_BD_BELL3     0x00000800  /* Status of doorbell 3 */
5395 +
5396 +/* MY IRQS register (...0xF8) */
5397 +#define ARM_MYIRQ_BELL   0x00000001  /* This owner has a doorbell IRQ */
5398 +#define ARM_MYIRQ_MAIL   0x00000002  /* This owner has a mailbox  IRQ */
5399 +
5400 +/* ALL IRQS register (...0xF8) */
5401 +#define ARM_AIS_BELL0 0x00000001  /* Doorbell 0 IRQ pending */
5402 +#define ARM_AIS_BELL1 0x00000002  /* Doorbell 1 IRQ pending */
5403 +#define ARM_AIS_BELL2 0x00000004  /* Doorbell 2 IRQ pending */
5404 +#define ARM_AIS_BELL3 0x00000008  /* Doorbell 3 IRQ pending */
5405 +#define ARM_AIS0_HAVEDATA 0x00000010  /* MAIL 0 has data IRQ pending */
5406 +#define ARM_AIS0_HAVESPAC 0x00000020  /* MAIL 0 has space IRQ pending */
5407 +#define ARM_AIS0_OPPEMPTY 0x00000040  /* MAIL 0 opposite is empty IRQ */
5408 +#define ARM_AIS1_HAVEDATA 0x00000080  /* MAIL 1 has data IRQ pending */
5409 +#define ARM_AIS1_HAVESPAC 0x00000100  /* MAIL 1 has space IRQ pending */
5410 +#define ARM_AIS1_OPPEMPTY 0x00000200  /* MAIL 1 opposite is empty IRQ */
5411 +/* Note   that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
5412 +/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
5413 +/* */
5414 +/* ARM JTAG BASH */
5415 +/* */
5416 +#define AJB_BASE 0x7e2000c0
5417 +
5418 +#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
5419 +#define   AJB_BITS0    0x000000
5420 +#define   AJB_BITS4    0x000004
5421 +#define   AJB_BITS8    0x000008
5422 +#define   AJB_BITS12   0x00000C
5423 +#define   AJB_BITS16   0x000010
5424 +#define   AJB_BITS20   0x000014
5425 +#define   AJB_BITS24   0x000018
5426 +#define   AJB_BITS28   0x00001C
5427 +#define   AJB_BITS32   0x000020
5428 +#define   AJB_BITS34   0x000022
5429 +#define   AJB_OUT_MS   0x000040
5430 +#define   AJB_OUT_LS   0x000000
5431 +#define   AJB_INV_CLK  0x000080
5432 +#define   AJB_D0_RISE  0x000100
5433 +#define   AJB_D0_FALL  0x000000
5434 +#define   AJB_D1_RISE  0x000200
5435 +#define   AJB_D1_FALL  0x000000
5436 +#define   AJB_IN_RISE  0x000400
5437 +#define   AJB_IN_FALL  0x000000
5438 +#define   AJB_ENABLE   0x000800
5439 +#define   AJB_HOLD0    0x000000
5440 +#define   AJB_HOLD1    0x001000
5441 +#define   AJB_HOLD2    0x002000
5442 +#define   AJB_HOLD3    0x003000
5443 +#define   AJB_RESETN   0x004000
5444 +#define   AJB_CLKSHFT  16
5445 +#define   AJB_BUSY     0x80000000
5446 +#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
5447 +#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
5448 +#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
5449 +
5450 +#endif
5451 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/arm_power.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/arm_power.h
5452 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/arm_power.h   1970-01-01 01:00:00.000000000 +0100
5453 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/arm_power.h     2013-07-06 15:25:50.000000000 +0100
5454 @@ -0,0 +1,60 @@
5455 +/*
5456 + *  linux/arch/arm/mach-bcm2708/include/mach/arm_power.h
5457 + *
5458 + *  Copyright (C) 2010 Broadcom
5459 + *
5460 + * This program is free software; you can redistribute it and/or modify
5461 + * it under the terms of the GNU General Public License as published by
5462 + * the Free Software Foundation; either version 2 of the License, or
5463 + * (at your option) any later version.
5464 + *
5465 + * This program is distributed in the hope that it will be useful,
5466 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5467 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5468 + * GNU General Public License for more details.
5469 + *
5470 + * You should have received a copy of the GNU General Public License
5471 + * along with this program; if not, write to the Free Software
5472 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5473 + */
5474 +
5475 +#ifndef _ARM_POWER_H
5476 +#define _ARM_POWER_H
5477 +
5478 +/* Use meaningful names on each side */
5479 +#ifdef __VIDEOCORE__
5480 +#define PREFIX(x) ARM_##x
5481 +#else
5482 +#define PREFIX(x) BCM_##x
5483 +#endif
5484 +
5485 +enum {
5486 +       PREFIX(POWER_SDCARD_BIT),
5487 +       PREFIX(POWER_UART_BIT),
5488 +       PREFIX(POWER_MINIUART_BIT),
5489 +       PREFIX(POWER_USB_BIT),
5490 +       PREFIX(POWER_I2C0_BIT),
5491 +       PREFIX(POWER_I2C1_BIT),
5492 +       PREFIX(POWER_I2C2_BIT),
5493 +       PREFIX(POWER_SPI_BIT),
5494 +       PREFIX(POWER_CCP2TX_BIT),
5495 +
5496 +       PREFIX(POWER_MAX)
5497 +};
5498 +
5499 +enum {
5500 +       PREFIX(POWER_SDCARD) = (1 << PREFIX(POWER_SDCARD_BIT)),
5501 +       PREFIX(POWER_UART) = (1 << PREFIX(POWER_UART_BIT)),
5502 +       PREFIX(POWER_MINIUART) = (1 << PREFIX(POWER_MINIUART_BIT)),
5503 +       PREFIX(POWER_USB) = (1 << PREFIX(POWER_USB_BIT)),
5504 +       PREFIX(POWER_I2C0) = (1 << PREFIX(POWER_I2C0_BIT)),
5505 +       PREFIX(POWER_I2C1_MASK) = (1 << PREFIX(POWER_I2C1_BIT)),
5506 +       PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)),
5507 +       PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)),
5508 +       PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)),
5509 +
5510 +       PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1,
5511 +       PREFIX(POWER_NONE) = 0
5512 +};
5513 +
5514 +#endif
5515 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/clkdev.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/clkdev.h
5516 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/clkdev.h      1970-01-01 01:00:00.000000000 +0100
5517 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/clkdev.h        2013-07-06 15:25:50.000000000 +0100
5518 @@ -0,0 +1,7 @@
5519 +#ifndef __ASM_MACH_CLKDEV_H
5520 +#define __ASM_MACH_CLKDEV_H
5521 +
5522 +#define __clk_get(clk) ({ 1; })
5523 +#define __clk_put(clk) do { } while (0)
5524 +
5525 +#endif
5526 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/debug-macro.S linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/debug-macro.S
5527 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/debug-macro.S 1970-01-01 01:00:00.000000000 +0100
5528 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/debug-macro.S   2013-07-06 15:25:50.000000000 +0100
5529 @@ -0,0 +1,22 @@
5530 +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
5531 + *
5532 + * Debugging macro include header
5533 + *
5534 + *  Copyright (C) 2010 Broadcom
5535 + *  Copyright (C) 1994-1999 Russell King
5536 + *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
5537 + *
5538 + * This program is free software; you can redistribute it and/or modify
5539 + * it under the terms of the GNU General Public License version 2 as
5540 + * published by the Free Software Foundation.
5541 + *
5542 +*/
5543 +
5544 +#include <mach/platform.h>
5545 +
5546 +               .macro  addruart, rp, rv, tmp
5547 +               ldr     \rp, =UART0_BASE
5548 +               ldr     \rv, =IO_ADDRESS(UART0_BASE)
5549 +               .endm
5550 +
5551 +#include <asm/hardware/debug-pl01x.S>
5552 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/dma.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/dma.h
5553 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/dma.h 1970-01-01 01:00:00.000000000 +0100
5554 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/dma.h   2013-07-06 15:25:50.000000000 +0100
5555 @@ -0,0 +1,86 @@
5556 +/*
5557 + *  linux/arch/arm/mach-bcm2708/include/mach/dma.h
5558 + *
5559 + *  Copyright (C) 2010 Broadcom
5560 + *
5561 + * This program is free software; you can redistribute it and/or modify
5562 + * it under the terms of the GNU General Public License version 2 as
5563 + * published by the Free Software Foundation.
5564 + */
5565 +
5566 +
5567 +#ifndef _MACH_BCM2708_DMA_H
5568 +#define _MACH_BCM2708_DMA_H
5569 +
5570 +#define BCM_DMAMAN_DRIVER_NAME "bcm2708_dma"
5571 +
5572 +/* DMA CS Control and Status bits */
5573 +#define BCM2708_DMA_ACTIVE     (1 << 0)
5574 +#define BCM2708_DMA_INT                (1 << 2)
5575 +#define BCM2708_DMA_ISPAUSED   (1 << 4)  /* Pause requested or not active */
5576 +#define BCM2708_DMA_ISHELD     (1 << 5)  /* Is held by DREQ flow control */
5577 +#define BCM2708_DMA_ERR                (1 << 8)
5578 +#define BCM2708_DMA_ABORT      (1 << 30) /* stop current CB, go to next, WO */
5579 +#define BCM2708_DMA_RESET      (1 << 31) /* WO, self clearing */
5580 +
5581 +/* DMA control block "info" field bits */
5582 +#define BCM2708_DMA_INT_EN     (1 << 0)
5583 +#define BCM2708_DMA_TDMODE     (1 << 1)
5584 +#define BCM2708_DMA_WAIT_RESP  (1 << 3)
5585 +#define BCM2708_DMA_D_INC      (1 << 4)
5586 +#define BCM2708_DMA_D_WIDTH    (1 << 5)
5587 +#define BCM2708_DMA_D_DREQ     (1 << 6)
5588 +#define BCM2708_DMA_S_INC      (1 << 8)
5589 +#define BCM2708_DMA_S_WIDTH    (1 << 9)
5590 +#define BCM2708_DMA_S_DREQ     (1 << 10)
5591 +
5592 +#define        BCM2708_DMA_BURST(x)    (((x)&0xf) << 12)
5593 +#define        BCM2708_DMA_PER_MAP(x)  ((x) << 16)
5594 +#define        BCM2708_DMA_WAITS(x)    (((x)&0x1f) << 21)
5595 +
5596 +#define BCM2708_DMA_DREQ_EMMC  11
5597 +#define BCM2708_DMA_DREQ_SDHOST        13
5598 +
5599 +#define BCM2708_DMA_CS         0x00 /* Control and Status */
5600 +#define BCM2708_DMA_ADDR       0x04
5601 +/* the current control block appears in the following registers - read only */
5602 +#define BCM2708_DMA_INFO       0x08
5603 +#define BCM2708_DMA_NEXTCB     0x1C
5604 +#define BCM2708_DMA_DEBUG      0x20
5605 +
5606 +#define BCM2708_DMA4_CS                (BCM2708_DMA_CHAN(4)+BCM2708_DMA_CS)
5607 +#define BCM2708_DMA4_ADDR      (BCM2708_DMA_CHAN(4)+BCM2708_DMA_ADDR)
5608 +
5609 +#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
5610 +
5611 +struct bcm2708_dma_cb {
5612 +       unsigned long info;
5613 +       unsigned long src;
5614 +       unsigned long dst;
5615 +       unsigned long length;
5616 +       unsigned long stride;
5617 +       unsigned long next;
5618 +       unsigned long pad[2];
5619 +};
5620 +
5621 +extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
5622 +extern void bcm_dma_start(void __iomem *dma_chan_base,
5623 +                         dma_addr_t control_block);
5624 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base);
5625 +extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base);
5626 +
5627 +/* When listing features we can ask for when allocating DMA channels give
5628 +   those with higher priority smaller ordinal numbers */
5629 +#define BCM_DMA_FEATURE_FAST_ORD 0
5630 +#define BCM_DMA_FEATURE_BULK_ORD 1
5631 +#define BCM_DMA_FEATURE_FAST    (1<<BCM_DMA_FEATURE_FAST_ORD)
5632 +#define BCM_DMA_FEATURE_BULK    (1<<BCM_DMA_FEATURE_BULK_ORD)
5633 +#define BCM_DMA_FEATURE_COUNT   2
5634 +
5635 +/* return channel no or -ve error */
5636 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
5637 +                             void __iomem **out_dma_base, int *out_dma_irq);
5638 +extern int bcm_dma_chan_free(int channel);
5639 +
5640 +
5641 +#endif /* _MACH_BCM2708_DMA_H */
5642 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/entry-macro.S linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/entry-macro.S
5643 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/entry-macro.S 1970-01-01 01:00:00.000000000 +0100
5644 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/entry-macro.S   2013-07-06 15:25:50.000000000 +0100
5645 @@ -0,0 +1,69 @@
5646 +/*
5647 + * arch/arm/mach-bcm2708/include/mach/entry-macro.S
5648 + *
5649 + * Low-level IRQ helper macros for BCM2708 platforms
5650 + *
5651 + *  Copyright (C) 2010 Broadcom
5652 + *
5653 + * This program is free software; you can redistribute it and/or modify
5654 + * it under the terms of the GNU General Public License as published by
5655 + * the Free Software Foundation; either version 2 of the License, or
5656 + * (at your option) any later version.
5657 + *
5658 + * This program is distributed in the hope that it will be useful,
5659 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5660 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5661 + * GNU General Public License for more details.
5662 + *
5663 + * You should have received a copy of the GNU General Public License
5664 + * along with this program; if not, write to the Free Software
5665 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5666 + */
5667 +#include <mach/hardware.h>
5668 +
5669 +               .macro  disable_fiq
5670 +               .endm
5671 +
5672 +               .macro  get_irqnr_preamble, base, tmp
5673 +               ldr     \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
5674 +               .endm
5675 +
5676 +               .macro  arch_ret_to_user, tmp1, tmp2
5677 +               .endm
5678 +
5679 +               .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
5680 +               /* get masked status */
5681 +               ldr     \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
5682 +               mov     \irqnr, #(ARM_IRQ0_BASE + 31)
5683 +               and     \tmp, \irqstat, #0x300           @ save bits 8 and 9
5684 +               /* clear bits 8 and 9, and test */
5685 +               bics    \irqstat, \irqstat, #0x300
5686 +               bne     1010f
5687 +
5688 +               tst     \tmp, #0x100
5689 +               ldrne   \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
5690 +               movne \irqnr, #(ARM_IRQ1_BASE + 31)
5691 +               @ Mask out the interrupts also present in PEND0 - see SW-5809
5692 +               bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
5693 +               bicne \irqstat, #((1<<18) | (1<<19))
5694 +               bne     1010f
5695 +
5696 +               tst     \tmp, #0x200
5697 +               ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
5698 +               movne \irqnr, #(ARM_IRQ2_BASE + 31)
5699 +               @ Mask out the interrupts also present in PEND0 - see SW-5809
5700 +               bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
5701 +               bicne \irqstat, #((1<<30))
5702 +               beq 1020f
5703 +
5704 +1010:
5705 +               @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
5706 +               @ N.B. CLZ is an ARM5 instruction.
5707 +               sub     \tmp, \irqstat, #1
5708 +               eor     \irqstat, \irqstat, \tmp
5709 +               clz     \tmp, \irqstat
5710 +               sub     \irqnr, \tmp
5711 +
5712 +1020:  @ EQ will be set if no irqs pending
5713 +
5714 +               .endm
5715 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/frc.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/frc.h
5716 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/frc.h 1970-01-01 01:00:00.000000000 +0100
5717 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/frc.h   2013-07-06 15:25:50.000000000 +0100
5718 @@ -0,0 +1,38 @@
5719 +/*
5720 + *  arch/arm/mach-bcm2708/include/mach/timex.h
5721 + *
5722 + *  BCM2708 free running counter (timer)
5723 + *
5724 + *  Copyright (C) 2010 Broadcom
5725 + *
5726 + * This program is free software; you can redistribute it and/or modify
5727 + * it under the terms of the GNU General Public License as published by
5728 + * the Free Software Foundation; either version 2 of the License, or
5729 + * (at your option) any later version.
5730 + *
5731 + * This program is distributed in the hope that it will be useful,
5732 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5733 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5734 + * GNU General Public License for more details.
5735 + *
5736 + * You should have received a copy of the GNU General Public License
5737 + * along with this program; if not, write to the Free Software
5738 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5739 + */
5740 +
5741 +#ifndef _MACH_FRC_H
5742 +#define _MACH_FRC_H
5743 +
5744 +#define FRC_TICK_RATE          (1000000)
5745 +
5746 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
5747 +    (slightly faster than frc_clock_ticks63()
5748 + */
5749 +extern unsigned long frc_clock_ticks32(void);
5750 +
5751 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
5752 + *  Note - top bit should be ignored (see cnt32_to_63)
5753 + */
5754 +extern unsigned long long frc_clock_ticks63(void);
5755 +
5756 +#endif
5757 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/gpio.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/gpio.h
5758 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/gpio.h        1970-01-01 01:00:00.000000000 +0100
5759 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/gpio.h  2013-07-06 15:25:50.000000000 +0100
5760 @@ -0,0 +1,18 @@
5761 +/*
5762 + * arch/arm/mach-bcm2708/include/mach/gpio.h
5763 + *
5764 + * This file is licensed under the terms of the GNU General Public
5765 + * License version 2.  This program is licensed "as is" without any
5766 + * warranty of any kind, whether express or implied.
5767 + */
5768 +
5769 +#ifndef __ASM_ARCH_GPIO_H
5770 +#define __ASM_ARCH_GPIO_H
5771 +
5772 +#define ARCH_NR_GPIOS 54 // number of gpio lines
5773 +
5774 +#define gpio_to_irq(x) ((x) + GPIO_IRQ_START)
5775 +#define irq_to_gpio(x) ((x) - GPIO_IRQ_START)
5776 +
5777 +#endif
5778 +
5779 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/hardware.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/hardware.h
5780 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/hardware.h    1970-01-01 01:00:00.000000000 +0100
5781 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/hardware.h      2013-07-06 15:25:50.000000000 +0100
5782 @@ -0,0 +1,28 @@
5783 +/*
5784 + *  arch/arm/mach-bcm2708/include/mach/hardware.h
5785 + *
5786 + *  This file contains the hardware definitions of the BCM2708 devices.
5787 + *
5788 + *  Copyright (C) 2010 Broadcom
5789 + *
5790 + * This program is free software; you can redistribute it and/or modify
5791 + * it under the terms of the GNU General Public License as published by
5792 + * the Free Software Foundation; either version 2 of the License, or
5793 + * (at your option) any later version.
5794 + *
5795 + * This program is distributed in the hope that it will be useful,
5796 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5797 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5798 + * GNU General Public License for more details.
5799 + *
5800 + * You should have received a copy of the GNU General Public License
5801 + * along with this program; if not, write to the Free Software
5802 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5803 + */
5804 +#ifndef __ASM_ARCH_HARDWARE_H
5805 +#define __ASM_ARCH_HARDWARE_H
5806 +
5807 +#include <asm/sizes.h>
5808 +#include <mach/platform.h>
5809 +
5810 +#endif
5811 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/io.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/io.h
5812 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/io.h  1970-01-01 01:00:00.000000000 +0100
5813 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/io.h    2013-07-06 15:25:50.000000000 +0100
5814 @@ -0,0 +1,27 @@
5815 +/*
5816 + *  arch/arm/mach-bcm2708/include/mach/io.h
5817 + *
5818 + *  Copyright (C) 2003 ARM Limited
5819 + *
5820 + * This program is free software; you can redistribute it and/or modify
5821 + * it under the terms of the GNU General Public License as published by
5822 + * the Free Software Foundation; either version 2 of the License, or
5823 + * (at your option) any later version.
5824 + *
5825 + * This program is distributed in the hope that it will be useful,
5826 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5827 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5828 + * GNU General Public License for more details.
5829 + *
5830 + * You should have received a copy of the GNU General Public License
5831 + * along with this program; if not, write to the Free Software
5832 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5833 + */
5834 +#ifndef __ASM_ARM_ARCH_IO_H
5835 +#define __ASM_ARM_ARCH_IO_H
5836 +
5837 +#define IO_SPACE_LIMIT 0xffffffff
5838 +
5839 +#define __io(a)                __typesafe_io(a)
5840 +
5841 +#endif
5842 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/irqs.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/irqs.h
5843 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/irqs.h        1970-01-01 01:00:00.000000000 +0100
5844 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/irqs.h  2013-07-06 15:25:50.000000000 +0100
5845 @@ -0,0 +1,199 @@
5846 +/*
5847 + *  arch/arm/mach-bcm2708/include/mach/irqs.h
5848 + *
5849 + *  Copyright (C) 2010 Broadcom
5850 + *  Copyright (C) 2003 ARM Limited
5851 + *  Copyright (C) 2000 Deep Blue Solutions Ltd.
5852 + *
5853 + * This program is free software; you can redistribute it and/or modify
5854 + * it under the terms of the GNU General Public License as published by
5855 + * the Free Software Foundation; either version 2 of the License, or
5856 + * (at your option) any later version.
5857 + *
5858 + * This program is distributed in the hope that it will be useful,
5859 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5860 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5861 + * GNU General Public License for more details.
5862 + *
5863 + * You should have received a copy of the GNU General Public License
5864 + * along with this program; if not, write to the Free Software
5865 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5866 + */
5867 +
5868 +#ifndef _BCM2708_IRQS_H_
5869 +#define _BCM2708_IRQS_H_
5870 +
5871 +#include <mach/platform.h>
5872 +
5873 +/*
5874 + *  IRQ interrupts definitions are the same as the INT definitions
5875 + *  held within platform.h
5876 + */
5877 +#define IRQ_ARMCTRL_START     0
5878 +#define IRQ_TIMER0            (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
5879 +#define IRQ_TIMER1            (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
5880 +#define IRQ_TIMER2            (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
5881 +#define IRQ_TIMER3            (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
5882 +#define IRQ_CODEC0            (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
5883 +#define IRQ_CODEC1            (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
5884 +#define IRQ_CODEC2            (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
5885 +#define IRQ_JPEG              (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
5886 +#define IRQ_ISP               (IRQ_ARMCTRL_START + INTERRUPT_ISP)
5887 +#define IRQ_USB               (IRQ_ARMCTRL_START + INTERRUPT_USB)
5888 +#define IRQ_3D                (IRQ_ARMCTRL_START + INTERRUPT_3D)
5889 +#define IRQ_TRANSPOSER        (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
5890 +#define IRQ_MULTICORESYNC0    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
5891 +#define IRQ_MULTICORESYNC1    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
5892 +#define IRQ_MULTICORESYNC2    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
5893 +#define IRQ_MULTICORESYNC3    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
5894 +#define IRQ_DMA0              (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
5895 +#define IRQ_DMA1              (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
5896 +#define IRQ_DMA2              (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
5897 +#define IRQ_DMA3              (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
5898 +#define IRQ_DMA4              (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
5899 +#define IRQ_DMA5              (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
5900 +#define IRQ_DMA6              (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
5901 +#define IRQ_DMA7              (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
5902 +#define IRQ_DMA8              (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
5903 +#define IRQ_DMA9              (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
5904 +#define IRQ_DMA10             (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
5905 +#define IRQ_DMA11             (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
5906 +#define IRQ_DMA12             (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
5907 +#define IRQ_AUX               (IRQ_ARMCTRL_START + INTERRUPT_AUX)
5908 +#define IRQ_ARM               (IRQ_ARMCTRL_START + INTERRUPT_ARM)
5909 +#define IRQ_VPUDMA            (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
5910 +#define IRQ_HOSTPORT          (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
5911 +#define IRQ_VIDEOSCALER       (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
5912 +#define IRQ_CCP2TX            (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
5913 +#define IRQ_SDC               (IRQ_ARMCTRL_START + INTERRUPT_SDC)
5914 +#define IRQ_DSI0              (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
5915 +#define IRQ_AVE               (IRQ_ARMCTRL_START + INTERRUPT_AVE)
5916 +#define IRQ_CAM0              (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
5917 +#define IRQ_CAM1              (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
5918 +#define IRQ_HDMI0             (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
5919 +#define IRQ_HDMI1             (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
5920 +#define IRQ_PIXELVALVE1       (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
5921 +#define IRQ_I2CSPISLV         (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
5922 +#define IRQ_DSI1              (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
5923 +#define IRQ_PWA0              (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
5924 +#define IRQ_PWA1              (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
5925 +#define IRQ_CPR               (IRQ_ARMCTRL_START + INTERRUPT_CPR)
5926 +#define IRQ_SMI               (IRQ_ARMCTRL_START + INTERRUPT_SMI)
5927 +#define IRQ_GPIO0             (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
5928 +#define IRQ_GPIO1             (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
5929 +#define IRQ_GPIO2             (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
5930 +#define IRQ_GPIO3             (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
5931 +#define IRQ_I2C               (IRQ_ARMCTRL_START + INTERRUPT_I2C)
5932 +#define IRQ_SPI               (IRQ_ARMCTRL_START + INTERRUPT_SPI)
5933 +#define IRQ_I2SPCM            (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
5934 +#define IRQ_SDIO              (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
5935 +#define IRQ_UART              (IRQ_ARMCTRL_START + INTERRUPT_UART)
5936 +#define IRQ_SLIMBUS           (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
5937 +#define IRQ_VEC               (IRQ_ARMCTRL_START + INTERRUPT_VEC)
5938 +#define IRQ_CPG               (IRQ_ARMCTRL_START + INTERRUPT_CPG)
5939 +#define IRQ_RNG               (IRQ_ARMCTRL_START + INTERRUPT_RNG)
5940 +#define IRQ_ARASANSDIO        (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
5941 +#define IRQ_AVSPMON           (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
5942 +
5943 +#define IRQ_ARM_TIMER         (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
5944 +#define IRQ_ARM_MAILBOX       (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
5945 +#define IRQ_ARM_DOORBELL_0    (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
5946 +#define IRQ_ARM_DOORBELL_1    (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
5947 +#define IRQ_VPU0_HALTED       (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
5948 +#define IRQ_VPU1_HALTED       (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
5949 +#define IRQ_ILLEGAL_TYPE0     (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
5950 +#define IRQ_ILLEGAL_TYPE1     (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
5951 +#define IRQ_PENDING1          (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
5952 +#define IRQ_PENDING2          (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
5953 +
5954 +#define FIQ_START             HARD_IRQS
5955 +
5956 +/*
5957 + *  FIQ interrupts definitions are the same as the INT definitions.
5958 + */
5959 +#define FIQ_TIMER0            (FIQ_START+INTERRUPT_TIMER0)
5960 +#define FIQ_TIMER1            (FIQ_START+INTERRUPT_TIMER1)
5961 +#define FIQ_TIMER2            (FIQ_START+INTERRUPT_TIMER2)
5962 +#define FIQ_TIMER3            (FIQ_START+INTERRUPT_TIMER3)
5963 +#define FIQ_CODEC0            (FIQ_START+INTERRUPT_CODEC0)
5964 +#define FIQ_CODEC1            (FIQ_START+INTERRUPT_CODEC1)
5965 +#define FIQ_CODEC2            (FIQ_START+INTERRUPT_CODEC2)
5966 +#define FIQ_JPEG              (FIQ_START+INTERRUPT_JPEG)
5967 +#define FIQ_ISP               (FIQ_START+INTERRUPT_ISP)
5968 +#define FIQ_USB               (FIQ_START+INTERRUPT_USB)
5969 +#define FIQ_3D                (FIQ_START+INTERRUPT_3D)
5970 +#define FIQ_TRANSPOSER        (FIQ_START+INTERRUPT_TRANSPOSER)
5971 +#define FIQ_MULTICORESYNC0    (FIQ_START+INTERRUPT_MULTICORESYNC0)
5972 +#define FIQ_MULTICORESYNC1    (FIQ_START+INTERRUPT_MULTICORESYNC1)
5973 +#define FIQ_MULTICORESYNC2    (FIQ_START+INTERRUPT_MULTICORESYNC2)
5974 +#define FIQ_MULTICORESYNC3    (FIQ_START+INTERRUPT_MULTICORESYNC3)
5975 +#define FIQ_DMA0              (FIQ_START+INTERRUPT_DMA0)
5976 +#define FIQ_DMA1              (FIQ_START+INTERRUPT_DMA1)
5977 +#define FIQ_DMA2              (FIQ_START+INTERRUPT_DMA2)
5978 +#define FIQ_DMA3              (FIQ_START+INTERRUPT_DMA3)
5979 +#define FIQ_DMA4              (FIQ_START+INTERRUPT_DMA4)
5980 +#define FIQ_DMA5              (FIQ_START+INTERRUPT_DMA5)
5981 +#define FIQ_DMA6              (FIQ_START+INTERRUPT_DMA6)
5982 +#define FIQ_DMA7              (FIQ_START+INTERRUPT_DMA7)
5983 +#define FIQ_DMA8              (FIQ_START+INTERRUPT_DMA8)
5984 +#define FIQ_DMA9              (FIQ_START+INTERRUPT_DMA9)
5985 +#define FIQ_DMA10             (FIQ_START+INTERRUPT_DMA10)
5986 +#define FIQ_DMA11             (FIQ_START+INTERRUPT_DMA11)
5987 +#define FIQ_DMA12             (FIQ_START+INTERRUPT_DMA12)
5988 +#define FIQ_AUX               (FIQ_START+INTERRUPT_AUX)
5989 +#define FIQ_ARM               (FIQ_START+INTERRUPT_ARM)
5990 +#define FIQ_VPUDMA            (FIQ_START+INTERRUPT_VPUDMA)
5991 +#define FIQ_HOSTPORT          (FIQ_START+INTERRUPT_HOSTPORT)
5992 +#define FIQ_VIDEOSCALER       (FIQ_START+INTERRUPT_VIDEOSCALER)
5993 +#define FIQ_CCP2TX            (FIQ_START+INTERRUPT_CCP2TX)
5994 +#define FIQ_SDC               (FIQ_START+INTERRUPT_SDC)
5995 +#define FIQ_DSI0              (FIQ_START+INTERRUPT_DSI0)
5996 +#define FIQ_AVE               (FIQ_START+INTERRUPT_AVE)
5997 +#define FIQ_CAM0              (FIQ_START+INTERRUPT_CAM0)
5998 +#define FIQ_CAM1              (FIQ_START+INTERRUPT_CAM1)
5999 +#define FIQ_HDMI0             (FIQ_START+INTERRUPT_HDMI0)
6000 +#define FIQ_HDMI1             (FIQ_START+INTERRUPT_HDMI1)
6001 +#define FIQ_PIXELVALVE1       (FIQ_START+INTERRUPT_PIXELVALVE1)
6002 +#define FIQ_I2CSPISLV         (FIQ_START+INTERRUPT_I2CSPISLV)
6003 +#define FIQ_DSI1              (FIQ_START+INTERRUPT_DSI1)
6004 +#define FIQ_PWA0              (FIQ_START+INTERRUPT_PWA0)
6005 +#define FIQ_PWA1              (FIQ_START+INTERRUPT_PWA1)
6006 +#define FIQ_CPR               (FIQ_START+INTERRUPT_CPR)
6007 +#define FIQ_SMI               (FIQ_START+INTERRUPT_SMI)
6008 +#define FIQ_GPIO0             (FIQ_START+INTERRUPT_GPIO0)
6009 +#define FIQ_GPIO1             (FIQ_START+INTERRUPT_GPIO1)
6010 +#define FIQ_GPIO2             (FIQ_START+INTERRUPT_GPIO2)
6011 +#define FIQ_GPIO3             (FIQ_START+INTERRUPT_GPIO3)
6012 +#define FIQ_I2C               (FIQ_START+INTERRUPT_I2C)
6013 +#define FIQ_SPI               (FIQ_START+INTERRUPT_SPI)
6014 +#define FIQ_I2SPCM            (FIQ_START+INTERRUPT_I2SPCM)
6015 +#define FIQ_SDIO              (FIQ_START+INTERRUPT_SDIO)
6016 +#define FIQ_UART              (FIQ_START+INTERRUPT_UART)
6017 +#define FIQ_SLIMBUS           (FIQ_START+INTERRUPT_SLIMBUS)
6018 +#define FIQ_VEC               (FIQ_START+INTERRUPT_VEC)
6019 +#define FIQ_CPG               (FIQ_START+INTERRUPT_CPG)
6020 +#define FIQ_RNG               (FIQ_START+INTERRUPT_RNG)
6021 +#define FIQ_ARASANSDIO        (FIQ_START+INTERRUPT_ARASANSDIO)
6022 +#define FIQ_AVSPMON           (FIQ_START+INTERRUPT_AVSPMON)
6023 +
6024 +#define FIQ_ARM_TIMER         (FIQ_START+INTERRUPT_ARM_TIMER)
6025 +#define FIQ_ARM_MAILBOX       (FIQ_START+INTERRUPT_ARM_MAILBOX)
6026 +#define FIQ_ARM_DOORBELL_0    (FIQ_START+INTERRUPT_ARM_DOORBELL_0)
6027 +#define FIQ_ARM_DOORBELL_1    (FIQ_START+INTERRUPT_ARM_DOORBELL_1)
6028 +#define FIQ_VPU0_HALTED       (FIQ_START+INTERRUPT_VPU0_HALTED)
6029 +#define FIQ_VPU1_HALTED       (FIQ_START+INTERRUPT_VPU1_HALTED)
6030 +#define FIQ_ILLEGAL_TYPE0     (FIQ_START+INTERRUPT_ILLEGAL_TYPE0)
6031 +#define FIQ_ILLEGAL_TYPE1     (FIQ_START+INTERRUPT_ILLEGAL_TYPE1)
6032 +#define FIQ_PENDING1          (FIQ_START+INTERRUPT_PENDING1)
6033 +#define FIQ_PENDING2          (FIQ_START+INTERRUPT_PENDING2)
6034 +
6035 +#define GPIO_IRQ_START       (HARD_IRQS + FIQ_IRQS)
6036 +
6037 +#define HARD_IRQS            (64 + 21)
6038 +#define FIQ_IRQS              (64 + 21)
6039 +#define GPIO_IRQS            (32*5)
6040 +
6041 +#define NR_IRQS                      HARD_IRQS+FIQ_IRQS+GPIO_IRQS
6042 +
6043 +
6044 +#endif /* _BCM2708_IRQS_H_ */
6045 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/memory.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/memory.h
6046 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/memory.h      1970-01-01 01:00:00.000000000 +0100
6047 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/memory.h        2013-07-06 15:25:50.000000000 +0100
6048 @@ -0,0 +1,57 @@
6049 +/*
6050 + *  arch/arm/mach-bcm2708/include/mach/memory.h
6051 + *
6052 + *  Copyright (C) 2010 Broadcom
6053 + *
6054 + * This program is free software; you can redistribute it and/or modify
6055 + * it under the terms of the GNU General Public License as published by
6056 + * the Free Software Foundation; either version 2 of the License, or
6057 + * (at your option) any later version.
6058 + *
6059 + * This program is distributed in the hope that it will be useful,
6060 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6061 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6062 + * GNU General Public License for more details.
6063 + *
6064 + * You should have received a copy of the GNU General Public License
6065 + * along with this program; if not, write to the Free Software
6066 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6067 + */
6068 +#ifndef __ASM_ARCH_MEMORY_H
6069 +#define __ASM_ARCH_MEMORY_H
6070 +
6071 +/* Memory overview:
6072 +
6073 +   [ARMcore] <--virtual addr-->
6074 +   [ARMmmu] <--physical addr-->
6075 +   [GERTmap] <--bus add-->
6076 +   [VCperiph]
6077 +
6078 +*/
6079 +
6080 +/*
6081 + * Physical DRAM offset.
6082 + */
6083 +#define PLAT_PHYS_OFFSET       UL(0x00000000)
6084 +#define VC_ARMMEM_OFFSET       UL(0x00000000)   /* offset in VC of ARM memory */
6085 +
6086 +#ifdef CONFIG_BCM2708_NOL2CACHE
6087 + #define _REAL_BUS_OFFSET UL(0xC0000000)   /* don't use L1 or L2 caches */
6088 +#else
6089 + #define _REAL_BUS_OFFSET UL(0x40000000)   /* use L2 cache */
6090 +#endif
6091 +
6092 +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
6093 + * will provide the offset into this area as well as setting the bits that
6094 + * stop the L1 and L2 cache from being used
6095 + *
6096 + * WARNING: this only works because the ARM is given memory at a fixed location
6097 + *          (ARMMEM_OFFSET)
6098 + */
6099 +#define BUS_OFFSET          (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
6100 +#define __virt_to_bus(x)    ((x) + (BUS_OFFSET - PAGE_OFFSET))
6101 +#define __bus_to_virt(x)    ((x) - (BUS_OFFSET - PAGE_OFFSET))
6102 +#define __pfn_to_bus(x)     (__pfn_to_phys(x) + (BUS_OFFSET - PLAT_PHYS_OFFSET))
6103 +#define __bus_to_pfn(x)     __phys_to_pfn((x) - (BUS_OFFSET - PLAT_PHYS_OFFSET))
6104 +
6105 +#endif
6106 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/platform.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/platform.h
6107 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/platform.h    1970-01-01 01:00:00.000000000 +0100
6108 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/platform.h      2013-07-06 15:25:50.000000000 +0100
6109 @@ -0,0 +1,226 @@
6110 +/*
6111 + * arch/arm/mach-bcm2708/include/mach/platform.h
6112 + *
6113 + * Copyright (C) 2010 Broadcom
6114 + *
6115 + * This program is free software; you can redistribute it and/or modify
6116 + * it under the terms of the GNU General Public License as published by
6117 + * the Free Software Foundation; either version 2 of the License, or
6118 + * (at your option) any later version.
6119 + *
6120 + * This program is distributed in the hope that it will be useful,
6121 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6122 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6123 + * GNU General Public License for more details.
6124 + *
6125 + * You should have received a copy of the GNU General Public License
6126 + * along with this program; if not, write to the Free Software
6127 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6128 + */
6129 +
6130 +#ifndef _BCM2708_PLATFORM_H
6131 +#define _BCM2708_PLATFORM_H
6132 +
6133 +
6134 +/* macros to get at IO space when running virtually */
6135 +#define IO_ADDRESS(x)  (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
6136 +
6137 +#define __io_address(n)     IOMEM(IO_ADDRESS(n))
6138 +
6139 +
6140 +/*
6141 + *  SDRAM
6142 + */
6143 +#define BCM2708_SDRAM_BASE           0x00000000
6144 +
6145 +/*
6146 + *  Logic expansion modules
6147 + *
6148 + */
6149 +
6150 +
6151 +/* ------------------------------------------------------------------------
6152 + *  BCM2708 ARMCTRL Registers
6153 + * ------------------------------------------------------------------------
6154 + */
6155 +
6156 +#define HW_REGISTER_RW(addr) (addr)
6157 +#define HW_REGISTER_RO(addr) (addr)
6158 +
6159 +#include "arm_control.h"
6160 +#undef ARM_BASE
6161 +
6162 +/*
6163 + * Definitions and addresses for the ARM CONTROL logic
6164 + * This file is manually generated.
6165 + */
6166 +
6167 +#define BCM2708_PERI_BASE        0x20000000
6168 +#define IC0_BASE                 (BCM2708_PERI_BASE + 0x2000)
6169 +#define ST_BASE                  (BCM2708_PERI_BASE + 0x3000)   /* System Timer */
6170 +#define MPHI_BASE               (BCM2708_PERI_BASE + 0x6000)   /* Message -based Parallel Host Interface */
6171 +#define DMA_BASE                (BCM2708_PERI_BASE + 0x7000)   /* DMA controller */
6172 +#define ARM_BASE                 (BCM2708_PERI_BASE + 0xB000)   /* BCM2708 ARM control block */
6173 +#define PM_BASE                         (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
6174 +#define RNG_BASE                 (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
6175 +#define GPIO_BASE                (BCM2708_PERI_BASE + 0x200000) /* GPIO */
6176 +#define UART0_BASE               (BCM2708_PERI_BASE + 0x201000)        /* Uart 0 */
6177 +#define MMCI0_BASE               (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
6178 +#define SPI0_BASE               (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
6179 +#define BSC0_BASE               (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
6180 +#define UART1_BASE               (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
6181 +#define EMMC_BASE                (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
6182 +#define SMI_BASE                (BCM2708_PERI_BASE + 0x600000) /* SMI */
6183 +#define BSC1_BASE               (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
6184 +#define USB_BASE                 (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
6185 +#define MCORE_BASE               (BCM2708_PERI_BASE + 0x0000)   /* Fake frame buffer device (actually the multicore sync block*/
6186 +
6187 +#define ARMCTRL_BASE             (ARM_BASE + 0x000)
6188 +#define ARMCTRL_IC_BASE          (ARM_BASE + 0x200)           /* ARM interrupt controller */
6189 +#define ARMCTRL_TIMER0_1_BASE    (ARM_BASE + 0x400)           /* Timer 0 and 1 */
6190 +#define ARMCTRL_0_SBM_BASE       (ARM_BASE + 0x800)           /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
6191 +
6192 +
6193 +/*
6194 + * Interrupt assignments
6195 + */
6196 +
6197 +#define ARM_IRQ1_BASE                  0
6198 +#define INTERRUPT_TIMER0               (ARM_IRQ1_BASE + 0)
6199 +#define INTERRUPT_TIMER1               (ARM_IRQ1_BASE + 1)
6200 +#define INTERRUPT_TIMER2               (ARM_IRQ1_BASE + 2)
6201 +#define INTERRUPT_TIMER3               (ARM_IRQ1_BASE + 3)
6202 +#define INTERRUPT_CODEC0               (ARM_IRQ1_BASE + 4)
6203 +#define INTERRUPT_CODEC1               (ARM_IRQ1_BASE + 5)
6204 +#define INTERRUPT_CODEC2               (ARM_IRQ1_BASE + 6)
6205 +#define INTERRUPT_VC_JPEG              (ARM_IRQ1_BASE + 7)
6206 +#define INTERRUPT_ISP                  (ARM_IRQ1_BASE + 8)
6207 +#define INTERRUPT_VC_USB               (ARM_IRQ1_BASE + 9)
6208 +#define INTERRUPT_VC_3D                (ARM_IRQ1_BASE + 10)
6209 +#define INTERRUPT_TRANSPOSER           (ARM_IRQ1_BASE + 11)
6210 +#define INTERRUPT_MULTICORESYNC0       (ARM_IRQ1_BASE + 12)
6211 +#define INTERRUPT_MULTICORESYNC1       (ARM_IRQ1_BASE + 13)
6212 +#define INTERRUPT_MULTICORESYNC2       (ARM_IRQ1_BASE + 14)
6213 +#define INTERRUPT_MULTICORESYNC3       (ARM_IRQ1_BASE + 15)
6214 +#define INTERRUPT_DMA0                 (ARM_IRQ1_BASE + 16)
6215 +#define INTERRUPT_DMA1                 (ARM_IRQ1_BASE + 17)
6216 +#define INTERRUPT_VC_DMA2              (ARM_IRQ1_BASE + 18)
6217 +#define INTERRUPT_VC_DMA3              (ARM_IRQ1_BASE + 19)
6218 +#define INTERRUPT_DMA4                 (ARM_IRQ1_BASE + 20)
6219 +#define INTERRUPT_DMA5                 (ARM_IRQ1_BASE + 21)
6220 +#define INTERRUPT_DMA6                 (ARM_IRQ1_BASE + 22)
6221 +#define INTERRUPT_DMA7                 (ARM_IRQ1_BASE + 23)
6222 +#define INTERRUPT_DMA8                 (ARM_IRQ1_BASE + 24)
6223 +#define INTERRUPT_DMA9                 (ARM_IRQ1_BASE + 25)
6224 +#define INTERRUPT_DMA10                (ARM_IRQ1_BASE + 26)
6225 +#define INTERRUPT_DMA11                (ARM_IRQ1_BASE + 27)
6226 +#define INTERRUPT_DMA12                (ARM_IRQ1_BASE + 28)
6227 +#define INTERRUPT_AUX                (ARM_IRQ1_BASE + 29)
6228 +#define INTERRUPT_ARM                  (ARM_IRQ1_BASE + 30)
6229 +#define INTERRUPT_VPUDMA               (ARM_IRQ1_BASE + 31)
6230 +
6231 +#define ARM_IRQ2_BASE                  32
6232 +#define INTERRUPT_HOSTPORT             (ARM_IRQ2_BASE + 0)
6233 +#define INTERRUPT_VIDEOSCALER          (ARM_IRQ2_BASE + 1)
6234 +#define INTERRUPT_CCP2TX               (ARM_IRQ2_BASE + 2)
6235 +#define INTERRUPT_SDC                  (ARM_IRQ2_BASE + 3)
6236 +#define INTERRUPT_DSI0                 (ARM_IRQ2_BASE + 4)
6237 +#define INTERRUPT_AVE                  (ARM_IRQ2_BASE + 5)
6238 +#define INTERRUPT_CAM0                 (ARM_IRQ2_BASE + 6)
6239 +#define INTERRUPT_CAM1                 (ARM_IRQ2_BASE + 7)
6240 +#define INTERRUPT_HDMI0                (ARM_IRQ2_BASE + 8)
6241 +#define INTERRUPT_HDMI1                (ARM_IRQ2_BASE + 9)
6242 +#define INTERRUPT_PIXELVALVE1          (ARM_IRQ2_BASE + 10)
6243 +#define INTERRUPT_I2CSPISLV            (ARM_IRQ2_BASE + 11)
6244 +#define INTERRUPT_DSI1                 (ARM_IRQ2_BASE + 12)
6245 +#define INTERRUPT_PWA0                 (ARM_IRQ2_BASE + 13)
6246 +#define INTERRUPT_PWA1                 (ARM_IRQ2_BASE + 14)
6247 +#define INTERRUPT_CPR                  (ARM_IRQ2_BASE + 15)
6248 +#define INTERRUPT_SMI                  (ARM_IRQ2_BASE + 16)
6249 +#define INTERRUPT_GPIO0                (ARM_IRQ2_BASE + 17)
6250 +#define INTERRUPT_GPIO1                (ARM_IRQ2_BASE + 18)
6251 +#define INTERRUPT_GPIO2                (ARM_IRQ2_BASE + 19)
6252 +#define INTERRUPT_GPIO3                (ARM_IRQ2_BASE + 20)
6253 +#define INTERRUPT_VC_I2C               (ARM_IRQ2_BASE + 21)
6254 +#define INTERRUPT_VC_SPI               (ARM_IRQ2_BASE + 22)
6255 +#define INTERRUPT_VC_I2SPCM            (ARM_IRQ2_BASE + 23)
6256 +#define INTERRUPT_VC_SDIO              (ARM_IRQ2_BASE + 24)
6257 +#define INTERRUPT_VC_UART              (ARM_IRQ2_BASE + 25)
6258 +#define INTERRUPT_SLIMBUS              (ARM_IRQ2_BASE + 26)
6259 +#define INTERRUPT_VEC                  (ARM_IRQ2_BASE + 27)
6260 +#define INTERRUPT_CPG                  (ARM_IRQ2_BASE + 28)
6261 +#define INTERRUPT_RNG                  (ARM_IRQ2_BASE + 29)
6262 +#define INTERRUPT_VC_ARASANSDIO        (ARM_IRQ2_BASE + 30)
6263 +#define INTERRUPT_AVSPMON              (ARM_IRQ2_BASE + 31)
6264 +
6265 +#define ARM_IRQ0_BASE                  64
6266 +#define INTERRUPT_ARM_TIMER            (ARM_IRQ0_BASE + 0)
6267 +#define INTERRUPT_ARM_MAILBOX          (ARM_IRQ0_BASE + 1)
6268 +#define INTERRUPT_ARM_DOORBELL_0       (ARM_IRQ0_BASE + 2)
6269 +#define INTERRUPT_ARM_DOORBELL_1       (ARM_IRQ0_BASE + 3)
6270 +#define INTERRUPT_VPU0_HALTED          (ARM_IRQ0_BASE + 4)
6271 +#define INTERRUPT_VPU1_HALTED          (ARM_IRQ0_BASE + 5)
6272 +#define INTERRUPT_ILLEGAL_TYPE0        (ARM_IRQ0_BASE + 6)
6273 +#define INTERRUPT_ILLEGAL_TYPE1        (ARM_IRQ0_BASE + 7)
6274 +#define INTERRUPT_PENDING1             (ARM_IRQ0_BASE + 8)
6275 +#define INTERRUPT_PENDING2             (ARM_IRQ0_BASE + 9)
6276 +#define INTERRUPT_JPEG                 (ARM_IRQ0_BASE + 10)
6277 +#define INTERRUPT_USB                  (ARM_IRQ0_BASE + 11)
6278 +#define INTERRUPT_3D                   (ARM_IRQ0_BASE + 12)
6279 +#define INTERRUPT_DMA2                 (ARM_IRQ0_BASE + 13)
6280 +#define INTERRUPT_DMA3                 (ARM_IRQ0_BASE + 14)
6281 +#define INTERRUPT_I2C                  (ARM_IRQ0_BASE + 15)
6282 +#define INTERRUPT_SPI                  (ARM_IRQ0_BASE + 16)
6283 +#define INTERRUPT_I2SPCM               (ARM_IRQ0_BASE + 17)
6284 +#define INTERRUPT_SDIO                 (ARM_IRQ0_BASE + 18)
6285 +#define INTERRUPT_UART                 (ARM_IRQ0_BASE + 19)
6286 +#define INTERRUPT_ARASANSDIO           (ARM_IRQ0_BASE + 20)
6287 +
6288 +#define MAXIRQNUM                      (32 + 32 + 20)
6289 +#define MAXFIQNUM                      (32 + 32 + 20)
6290 +
6291 +#define MAX_TIMER                       2
6292 +#define MAX_PERIOD                      699050
6293 +#define TICKS_PER_uSEC                  1
6294 +
6295 +/*
6296 + *  These are useconds NOT ticks.
6297 + *
6298 + */
6299 +#define mSEC_1                          1000
6300 +#define mSEC_5                          (mSEC_1 * 5)
6301 +#define mSEC_10                         (mSEC_1 * 10)
6302 +#define mSEC_25                         (mSEC_1 * 25)
6303 +#define SEC_1                           (mSEC_1 * 1000)
6304 +
6305 +/*
6306 + * Watchdog
6307 + */
6308 +#define PM_RSTC                               (PM_BASE+0x1c)
6309 +#define PM_RSTS                               (PM_BASE+0x20)
6310 +#define PM_WDOG                               (PM_BASE+0x24)
6311 +
6312 +#define PM_WDOG_RESET                                         0000000000
6313 +#define PM_PASSWORD                   0x5a000000
6314 +#define PM_WDOG_TIME_SET              0x000fffff
6315 +#define PM_RSTC_WRCFG_CLR              0xffffffcf
6316 +#define PM_RSTC_WRCFG_SET              0x00000030
6317 +#define PM_RSTC_WRCFG_FULL_RESET       0x00000020
6318 +#define PM_RSTC_RESET                  0x00000102
6319 +
6320 +#define PM_RSTS_HADPOR_SET                                 0x00001000
6321 +#define PM_RSTS_HADSRH_SET                                 0x00000400
6322 +#define PM_RSTS_HADSRF_SET                                 0x00000200
6323 +#define PM_RSTS_HADSRQ_SET                                 0x00000100
6324 +#define PM_RSTS_HADWRH_SET                                 0x00000040
6325 +#define PM_RSTS_HADWRF_SET                                 0x00000020
6326 +#define PM_RSTS_HADWRQ_SET                                 0x00000010
6327 +#define PM_RSTS_HADDRH_SET                                 0x00000004
6328 +#define PM_RSTS_HADDRF_SET                                 0x00000002
6329 +#define PM_RSTS_HADDRQ_SET                                 0x00000001
6330 +
6331 +#define UART0_CLOCK      3000000
6332 +
6333 +#endif
6334 +
6335 +/* END */
6336 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/power.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/power.h
6337 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/power.h       1970-01-01 01:00:00.000000000 +0100
6338 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/power.h 2013-07-06 15:25:50.000000000 +0100
6339 @@ -0,0 +1,26 @@
6340 +/*
6341 + *  linux/arch/arm/mach-bcm2708/power.h
6342 + *
6343 + *  Copyright (C) 2010 Broadcom
6344 + *
6345 + * This program is free software; you can redistribute it and/or modify
6346 + * it under the terms of the GNU General Public License version 2 as
6347 + * published by the Free Software Foundation.
6348 + *
6349 + * This device provides a shared mechanism for controlling the power to
6350 + * VideoCore subsystems.
6351 + */
6352 +
6353 +#ifndef _MACH_BCM2708_POWER_H
6354 +#define _MACH_BCM2708_POWER_H
6355 +
6356 +#include <linux/types.h>
6357 +#include <mach/arm_power.h>
6358 +
6359 +typedef unsigned int BCM_POWER_HANDLE_T;
6360 +
6361 +extern int bcm_power_open(BCM_POWER_HANDLE_T *handle);
6362 +extern int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request);
6363 +extern int bcm_power_close(BCM_POWER_HANDLE_T handle);
6364 +
6365 +#endif
6366 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/system.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/system.h
6367 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/system.h      1970-01-01 01:00:00.000000000 +0100
6368 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/system.h        2013-07-06 15:25:50.000000000 +0100
6369 @@ -0,0 +1,38 @@
6370 +/*
6371 + *  arch/arm/mach-bcm2708/include/mach/system.h
6372 + *
6373 + *  Copyright (C) 2010 Broadcom
6374 + *  Copyright (C) 2003 ARM Limited
6375 + *  Copyright (C) 2000 Deep Blue Solutions Ltd
6376 + *
6377 + * This program is free software; you can redistribute it and/or modify
6378 + * it under the terms of the GNU General Public License as published by
6379 + * the Free Software Foundation; either version 2 of the License, or
6380 + * (at your option) any later version.
6381 + *
6382 + * This program is distributed in the hope that it will be useful,
6383 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6384 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6385 + * GNU General Public License for more details.
6386 + *
6387 + * You should have received a copy of the GNU General Public License
6388 + * along with this program; if not, write to the Free Software
6389 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6390 + */
6391 +#ifndef __ASM_ARCH_SYSTEM_H
6392 +#define __ASM_ARCH_SYSTEM_H
6393 +
6394 +#include <linux/io.h>
6395 +#include <mach/hardware.h>
6396 +#include <mach/platform.h>
6397 +
6398 +static inline void arch_idle(void)
6399 +{
6400 +       /*
6401 +        * This should do all the clock switching
6402 +        * and wait for interrupt tricks
6403 +        */
6404 +       cpu_do_idle();
6405 +}
6406 +
6407 +#endif
6408 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/timex.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/timex.h
6409 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/timex.h       1970-01-01 01:00:00.000000000 +0100
6410 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/timex.h 2013-07-06 15:25:50.000000000 +0100
6411 @@ -0,0 +1,23 @@
6412 +/*
6413 + *  arch/arm/mach-bcm2708/include/mach/timex.h
6414 + *
6415 + *  BCM2708 sysem clock frequency
6416 + *
6417 + *  Copyright (C) 2010 Broadcom
6418 + *
6419 + * This program is free software; you can redistribute it and/or modify
6420 + * it under the terms of the GNU General Public License as published by
6421 + * the Free Software Foundation; either version 2 of the License, or
6422 + * (at your option) any later version.
6423 + *
6424 + * This program is distributed in the hope that it will be useful,
6425 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6426 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6427 + * GNU General Public License for more details.
6428 + *
6429 + * You should have received a copy of the GNU General Public License
6430 + * along with this program; if not, write to the Free Software
6431 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6432 + */
6433 +
6434 +#define CLOCK_TICK_RATE                (1000000)
6435 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/uncompress.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/uncompress.h
6436 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/uncompress.h  1970-01-01 01:00:00.000000000 +0100
6437 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/uncompress.h    2013-07-06 15:25:50.000000000 +0100
6438 @@ -0,0 +1,85 @@
6439 +/*
6440 + *  arch/arm/mach-bcn2708/include/mach/uncompress.h
6441 + *
6442 + *  Copyright (C) 2010 Broadcom
6443 + *  Copyright (C) 2003 ARM Limited
6444 + *
6445 + * This program is free software; you can redistribute it and/or modify
6446 + * it under the terms of the GNU General Public License as published by
6447 + * the Free Software Foundation; either version 2 of the License, or
6448 + * (at your option) any later version.
6449 + *
6450 + * This program is distributed in the hope that it will be useful,
6451 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6452 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6453 + * GNU General Public License for more details.
6454 + *
6455 + * You should have received a copy of the GNU General Public License
6456 + * along with this program; if not, write to the Free Software
6457 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6458 + */
6459 +
6460 +#include <linux/io.h>
6461 +#include <linux/amba/serial.h>
6462 +#include <mach/hardware.h>
6463 +
6464 +#define UART_BAUD 115200
6465 +
6466 +#define BCM2708_UART_DR   __io(UART0_BASE + UART01x_DR)
6467 +#define BCM2708_UART_FR   __io(UART0_BASE + UART01x_FR)
6468 +#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
6469 +#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
6470 +#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
6471 +#define BCM2708_UART_CR   __io(UART0_BASE + UART011_CR)
6472 +
6473 +/*
6474 + * This does not append a newline
6475 + */
6476 +static inline void putc(int c)
6477 +{
6478 +       while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
6479 +               barrier();
6480 +
6481 +       __raw_writel(c, BCM2708_UART_DR);
6482 +}
6483 +
6484 +static inline void flush(void)
6485 +{
6486 +       int fr;
6487 +
6488 +       do {
6489 +               fr = __raw_readl(BCM2708_UART_FR);
6490 +               barrier();
6491 +       } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
6492 +}
6493 +
6494 +static inline void arch_decomp_setup(void)
6495 +{
6496 +       int temp, div, rem, frac;
6497 +
6498 +       temp = 16 * UART_BAUD;
6499 +       div = UART0_CLOCK / temp;
6500 +       rem = UART0_CLOCK % temp;
6501 +       temp = (8 * rem) / UART_BAUD;
6502 +       frac = (temp >> 1) + (temp & 1);
6503 +
6504 +       /* Make sure the UART is disabled before we start */
6505 +       __raw_writel(0, BCM2708_UART_CR);
6506 +
6507 +       /* Set the baud rate */
6508 +       __raw_writel(div, BCM2708_UART_IBRD);
6509 +       __raw_writel(frac, BCM2708_UART_FBRD);
6510 +
6511 +       /* Set the UART to 8n1, FIFO enabled */
6512 +       __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
6513 +
6514 +       /* Enable the UART */
6515 +       __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
6516 +                       BCM2708_UART_CR);
6517 +}
6518 +
6519 +/*
6520 + * nothing to do
6521 + */
6522 +#define arch_decomp_wdog()
6523 +
6524 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/vcio.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/vcio.h
6525 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/vcio.h        1970-01-01 01:00:00.000000000 +0100
6526 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/vcio.h  2013-07-06 15:25:50.000000000 +0100
6527 @@ -0,0 +1,141 @@
6528 +/*
6529 + *  arch/arm/mach-bcm2708/include/mach/vcio.h
6530 + *
6531 + *  Copyright (C) 2010 Broadcom
6532 + *
6533 + * This program is free software; you can redistribute it and/or modify
6534 + * it under the terms of the GNU General Public License as published by
6535 + * the Free Software Foundation; either version 2 of the License, or
6536 + * (at your option) any later version.
6537 + *
6538 + * This program is distributed in the hope that it will be useful,
6539 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6540 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6541 + * GNU General Public License for more details.
6542 + *
6543 + * You should have received a copy of the GNU General Public License
6544 + * along with this program; if not, write to the Free Software
6545 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6546 + */
6547 +#ifndef _MACH_BCM2708_VCIO_H
6548 +#define _MACH_BCM2708_VCIO_H
6549 +
6550 +/* Routines to handle I/O via the VideoCore "ARM control" registers
6551 + * (semaphores, doorbells, mailboxes)
6552 + */
6553 +
6554 +#define BCM_VCIO_DRIVER_NAME "bcm2708_vcio"
6555 +
6556 +/* Constants shared with the ARM identifying separate mailbox channels */
6557 +#define MBOX_CHAN_POWER    0 /* for use by the power management interface */
6558 +#define MBOX_CHAN_FB       1 /* for use by the frame buffer */
6559 +#define MBOX_CHAN_VCHIQ    3 /* for use by the VCHIQ interface */
6560 +#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */
6561 +#define MBOX_CHAN_COUNT    9
6562 +
6563 +/* Mailbox property tags */
6564 +enum {
6565 +       VCMSG_PROPERTY_END               = 0x00000000,
6566 +       VCMSG_GET_FIRMWARE_REVISION      = 0x00000001,
6567 +       VCMSG_GET_BOARD_MODEL            = 0x00010001,
6568 +       VCMSG_GET_BOARD_REVISION         = 0x00020002,
6569 +       VCMSG_GET_BOARD_MAC_ADDRESS      = 0x00020003,
6570 +       VCMSG_GET_BOARD_SERIAL           = 0x00020004,
6571 +       VCMSG_GET_ARM_MEMORY             = 0x00020005,
6572 +       VCMSG_GET_VC_MEMORY              = 0x00020006,
6573 +       VCMSG_GET_CLOCKS                 = 0x00020007,
6574 +       VCMSG_GET_COMMAND_LINE           = 0x00050001,
6575 +       VCMSG_GET_DMA_CHANNELS           = 0x00060001,
6576 +       VCMSG_GET_POWER_STATE            = 0x00020001,
6577 +       VCMSG_GET_TIMING                 = 0x00020002,
6578 +       VCMSG_SET_POWER_STATE            = 0x00028001,
6579 +       VCMSG_GET_CLOCK_STATE            = 0x00030001,
6580 +       VCMSG_SET_CLOCK_STATE            = 0x00038001,
6581 +       VCMSG_GET_CLOCK_RATE             = 0x00030002,
6582 +       VCMSG_SET_CLOCK_RATE             = 0x00038002,
6583 +       VCMSG_GET_VOLTAGE                = 0x00030003,
6584 +       VCMSG_SET_VOLTAGE                = 0x00038003,
6585 +       VCMSG_GET_MAX_CLOCK              = 0x00030004,
6586 +       VCMSG_GET_MAX_VOLTAGE            = 0x00030005,
6587 +       VCMSG_GET_TEMPERATURE            = 0x00030006,
6588 +       VCMSG_GET_MIN_CLOCK              = 0x00030007,
6589 +       VCMSG_GET_MIN_VOLTAGE            = 0x00030008,
6590 +       VCMSG_GET_TURBO                  = 0x00030009,
6591 +       VCMSG_SET_TURBO                  = 0x00038009,
6592 +       VCMSG_SET_ALLOCATE_BUFFER        = 0x00040001,
6593 +       VCMSG_SET_RELEASE_BUFFER         = 0x00048001,
6594 +       VCMSG_SET_BLANK_SCREEN           = 0x00040002,
6595 +       VCMSG_TST_BLANK_SCREEN           = 0x00044002,
6596 +       VCMSG_GET_PHYSICAL_WIDTH_HEIGHT  = 0x00040003,
6597 +       VCMSG_TST_PHYSICAL_WIDTH_HEIGHT  = 0x00044003,
6598 +       VCMSG_SET_PHYSICAL_WIDTH_HEIGHT  = 0x00048003,
6599 +       VCMSG_GET_VIRTUAL_WIDTH_HEIGHT   = 0x00040004,
6600 +       VCMSG_TST_VIRTUAL_WIDTH_HEIGHT   = 0x00044004,
6601 +       VCMSG_SET_VIRTUAL_WIDTH_HEIGHT   = 0x00048004,
6602 +       VCMSG_GET_DEPTH                  = 0x00040005,
6603 +       VCMSG_TST_DEPTH                  = 0x00044005,
6604 +       VCMSG_SET_DEPTH                  = 0x00048005,
6605 +       VCMSG_GET_PIXEL_ORDER            = 0x00040006,
6606 +       VCMSG_TST_PIXEL_ORDER            = 0x00044006,
6607 +       VCMSG_SET_PIXEL_ORDER            = 0x00048006,
6608 +       VCMSG_GET_ALPHA_MODE             = 0x00040007,
6609 +       VCMSG_TST_ALPHA_MODE             = 0x00044007,
6610 +       VCMSG_SET_ALPHA_MODE             = 0x00048007,
6611 +       VCMSG_GET_PITCH                  = 0x00040008,
6612 +       VCMSG_TST_PITCH                  = 0x00044008,
6613 +       VCMSG_SET_PITCH                  = 0x00048008,
6614 +       VCMSG_GET_VIRTUAL_OFFSET         = 0x00040009,
6615 +       VCMSG_TST_VIRTUAL_OFFSET         = 0x00044009,
6616 +       VCMSG_SET_VIRTUAL_OFFSET         = 0x00048009,
6617 +       VCMSG_GET_OVERSCAN               = 0x0004000a,
6618 +       VCMSG_TST_OVERSCAN               = 0x0004400a,
6619 +       VCMSG_SET_OVERSCAN               = 0x0004800a,
6620 +       VCMSG_GET_PALETTE                = 0x0004000b,
6621 +       VCMSG_TST_PALETTE                = 0x0004400b,
6622 +       VCMSG_SET_PALETTE                = 0x0004800b,
6623 +       VCMSG_GET_LAYER                  = 0x0004000c,
6624 +       VCMSG_TST_LAYER                  = 0x0004400c,
6625 +       VCMSG_SET_LAYER                  = 0x0004800c,
6626 +       VCMSG_GET_TRANSFORM              = 0x0004000d,
6627 +       VCMSG_TST_TRANSFORM              = 0x0004400d,
6628 +       VCMSG_SET_TRANSFORM              = 0x0004800d,
6629 +};
6630 +
6631 +extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28);
6632 +extern int /*rc*/ bcm_mailbox_write(unsigned chan, uint32_t data28);
6633 +extern int /*rc*/ bcm_mailbox_property(void *data, int size);
6634 +
6635 +#include <linux/ioctl.h>
6636 +
6637 +/*
6638 + * The major device number. We can't rely on dynamic
6639 + * registration any more, because ioctls need to know
6640 + * it.
6641 + */
6642 +#define MAJOR_NUM 100
6643 +
6644 +/*
6645 + * Set the message of the device driver
6646 + */
6647 +#define IOCTL_MBOX_PROPERTY _IOWR(MAJOR_NUM, 0, char *)
6648 +/*
6649 + * _IOWR means that we're creating an ioctl command
6650 + * number for passing information from a user process
6651 + * to the kernel module and from the kernel module to user process
6652 + *
6653 + * The first arguments, MAJOR_NUM, is the major device
6654 + * number we're using.
6655 + *
6656 + * The second argument is the number of the command
6657 + * (there could be several with different meanings).
6658 + *
6659 + * The third argument is the type we want to get from
6660 + * the process to the kernel.
6661 + */
6662 +
6663 +/*
6664 + * The name of the device file
6665 + */
6666 +#define DEVICE_FILE_NAME "char_dev"
6667 +
6668 +#endif
6669 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/vc_mem.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/vc_mem.h
6670 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/vc_mem.h      1970-01-01 01:00:00.000000000 +0100
6671 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/vc_mem.h        2013-07-06 15:25:50.000000000 +0100
6672 @@ -0,0 +1,36 @@
6673 +/*****************************************************************************
6674 +* Copyright 2010 - 2011 Broadcom Corporation.  All rights reserved.
6675 +*
6676 +* Unless you and Broadcom execute a separate written software license
6677 +* agreement governing use of this software, this software is licensed to you
6678 +* under the terms of the GNU General Public License version 2, available at
6679 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
6680 +*
6681 +* Notwithstanding the above, under no circumstances may you combine this
6682 +* software in any way with any other Broadcom software provided under a
6683 +* license other than the GPL, without Broadcom's express prior written
6684 +* consent.
6685 +*****************************************************************************/
6686 +
6687 +#if !defined( VC_MEM_H )
6688 +#define VC_MEM_H
6689 +
6690 +#include <linux/ioctl.h>
6691 +
6692 +#define VC_MEM_IOC_MAGIC  'v'
6693 +
6694 +#define VC_MEM_IOC_MEM_PHYS_ADDR    _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
6695 +#define VC_MEM_IOC_MEM_SIZE         _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
6696 +#define VC_MEM_IOC_MEM_BASE         _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
6697 +#define VC_MEM_IOC_MEM_LOAD         _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
6698 +
6699 +#if defined( __KERNEL__ )
6700 +#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
6701 +
6702 +extern unsigned long mm_vc_mem_phys_addr;
6703 +extern unsigned int  mm_vc_mem_size;
6704 +extern int vc_mem_get_current_size( void );
6705 +#endif
6706 +
6707 +#endif  /* VC_MEM_H */
6708 +
6709 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/vc_support.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/vc_support.h
6710 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/vc_support.h  1970-01-01 01:00:00.000000000 +0100
6711 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/vc_support.h    2013-07-06 15:25:50.000000000 +0100
6712 @@ -0,0 +1,69 @@
6713 +#ifndef _VC_SUPPORT_H_
6714 +#define _VC_SUPPORT_H_
6715 +
6716 +/*
6717 + * vc_support.h
6718 + *
6719 + *  Created on: 25 Nov 2012
6720 + *      Author: Simon
6721 + */
6722 +
6723 +enum {
6724 +/*
6725 +      If a MEM_HANDLE_T is discardable, the memory manager may resize it to size
6726 +      0 at any time when it is not locked or retained.
6727 +   */
6728 +   MEM_FLAG_DISCARDABLE = 1 << 0,
6729 +
6730 +   /*
6731 +      If a MEM_HANDLE_T is allocating (or normal), its block of memory will be
6732 +      accessed in an allocating fashion through the cache.
6733 +   */
6734 +   MEM_FLAG_NORMAL = 0 << 2,
6735 +   MEM_FLAG_ALLOCATING = MEM_FLAG_NORMAL,
6736 +
6737 +   /*
6738 +      If a MEM_HANDLE_T is direct, its block of memory will be accessed
6739 +      directly, bypassing the cache.
6740 +   */
6741 +   MEM_FLAG_DIRECT = 1 << 2,
6742 +
6743 +   /*
6744 +      If a MEM_HANDLE_T is coherent, its block of memory will be accessed in a
6745 +      non-allocating fashion through the cache.
6746 +   */
6747 +   MEM_FLAG_COHERENT = 2 << 2,
6748 +
6749 +   /*
6750 +      If a MEM_HANDLE_T is L1-nonallocating, its block of memory will be accessed by
6751 +      the VPU in a fashion which is allocating in L2, but only coherent in L1.
6752 +   */
6753 +   MEM_FLAG_L1_NONALLOCATING = (MEM_FLAG_DIRECT | MEM_FLAG_COHERENT),
6754 +
6755 +   /*
6756 +      If a MEM_HANDLE_T is zero'd, its contents are set to 0 rather than
6757 +      MEM_HANDLE_INVALID on allocation and resize up.
6758 +   */
6759 +   MEM_FLAG_ZERO = 1 << 4,
6760 +
6761 +   /*
6762 +      If a MEM_HANDLE_T is uninitialised, it will not be reset to a defined value
6763 +      (either zero, or all 1's) on allocation.
6764 +    */
6765 +   MEM_FLAG_NO_INIT = 1 << 5,
6766 +
6767 +   /*
6768 +      Hints.
6769 +   */
6770 +   MEM_FLAG_HINT_PERMALOCK = 1 << 6, /* Likely to be locked for long periods of time. */
6771 +};
6772 +
6773 +unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags);
6774 +unsigned int ReleaseVcMemory(unsigned int handle);
6775 +unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle);
6776 +unsigned int UnlockVcMemory(unsigned int handle);
6777 +
6778 +unsigned int ExecuteVcCode(unsigned int code,
6779 +               unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5);
6780 +
6781 +#endif
6782 diff -urN linux-3.10/arch/arm/mach-bcm2708/include/mach/vmalloc.h linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/vmalloc.h
6783 --- linux-3.10/arch/arm/mach-bcm2708/include/mach/vmalloc.h     1970-01-01 01:00:00.000000000 +0100
6784 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/include/mach/vmalloc.h       2013-07-06 15:25:50.000000000 +0100
6785 @@ -0,0 +1,20 @@
6786 +/*
6787 + *  arch/arm/mach-bcm2708/include/mach/vmalloc.h
6788 + *
6789 + *  Copyright (C) 2010 Broadcom
6790 + *
6791 + * This program is free software; you can redistribute it and/or modify
6792 + * it under the terms of the GNU General Public License as published by
6793 + * the Free Software Foundation; either version 2 of the License, or
6794 + * (at your option) any later version.
6795 + *
6796 + * This program is distributed in the hope that it will be useful,
6797 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6798 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6799 + * GNU General Public License for more details.
6800 + *
6801 + * You should have received a copy of the GNU General Public License
6802 + * along with this program; if not, write to the Free Software
6803 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6804 + */
6805 +#define VMALLOC_END            (0xe8000000)
6806 diff -urN linux-3.10/arch/arm/mach-bcm2708/Kconfig linux-rpi-3.10.y/arch/arm/mach-bcm2708/Kconfig
6807 --- linux-3.10/arch/arm/mach-bcm2708/Kconfig    1970-01-01 01:00:00.000000000 +0100
6808 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/Kconfig      2013-07-06 15:25:50.000000000 +0100
6809 @@ -0,0 +1,48 @@
6810 +menu "Broadcom BCM2708 Implementations"
6811 +       depends on ARCH_BCM2708
6812 +
6813 +config MACH_BCM2708
6814 +       bool "Broadcom BCM2708 Development Platform"
6815 +       select NEED_MACH_MEMORY_H
6816 +       select NEED_MACH_IO_H
6817 +       select CPU_V6
6818 +       help
6819 +         Include support for the Broadcom(R) BCM2708 platform.
6820 +
6821 +config BCM2708_GPIO
6822 +       bool "BCM2708 gpio support"
6823 +       depends on MACH_BCM2708
6824 +       select ARCH_REQUIRE_GPIOLIB
6825 +        default y
6826 +       help
6827 +         Include support for the Broadcom(R) BCM2708 gpio.
6828 +
6829 +config BCM2708_VCMEM
6830 +       bool "Videocore Memory"
6831 +       depends on MACH_BCM2708
6832 +        default y
6833 +        help
6834 +          Helper for videocore memory access and total size allocation.
6835 +
6836 +config BCM2708_NOL2CACHE
6837 +       bool "Videocore L2 cache disable"
6838 +       depends on MACH_BCM2708
6839 +        default n
6840 +        help
6841 +          Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
6842 +
6843 +config BCM2708_DMAER
6844 +       tristate "BCM2708 DMA helper"
6845 +       depends on MACH_BCM2708
6846 +        default n
6847 +        help
6848 +          Enable DMA helper for accelerating X composition
6849 +
6850 +config BCM2708_SPIDEV
6851 +       bool "Bind spidev to SPI0 master"
6852 +       depends on MACH_BCM2708
6853 +       depends on SPI
6854 +        default y
6855 +               help
6856 +                       Binds spidev driver to the SPI0 master
6857 +endmenu
6858 diff -urN linux-3.10/arch/arm/mach-bcm2708/Makefile linux-rpi-3.10.y/arch/arm/mach-bcm2708/Makefile
6859 --- linux-3.10/arch/arm/mach-bcm2708/Makefile   1970-01-01 01:00:00.000000000 +0100
6860 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/Makefile     2013-07-06 15:25:50.000000000 +0100
6861 @@ -0,0 +1,11 @@
6862 +#
6863 +# Makefile for the linux kernel.
6864 +#
6865 +
6866 +obj-$(CONFIG_MACH_BCM2708)     += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o
6867 +obj-$(CONFIG_BCM2708_GPIO)     += bcm2708_gpio.o
6868 +obj-$(CONFIG_BCM2708_VCMEM)    += vc_mem.o
6869 +
6870 +obj-$(CONFIG_BCM2708_DMAER)    += dmaer_master.o
6871 +dmaer_master-objs              := dmaer.o vc_support.o
6872 +
6873 diff -urN linux-3.10/arch/arm/mach-bcm2708/Makefile.boot linux-rpi-3.10.y/arch/arm/mach-bcm2708/Makefile.boot
6874 --- linux-3.10/arch/arm/mach-bcm2708/Makefile.boot      1970-01-01 01:00:00.000000000 +0100
6875 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/Makefile.boot        2013-07-06 15:25:50.000000000 +0100
6876 @@ -0,0 +1,3 @@
6877 +   zreladdr-y  := 0x00008000
6878 +params_phys-y  := 0x00000100
6879 +initrd_phys-y  := 0x00800000
6880 diff -urN linux-3.10/arch/arm/mach-bcm2708/power.c linux-rpi-3.10.y/arch/arm/mach-bcm2708/power.c
6881 --- linux-3.10/arch/arm/mach-bcm2708/power.c    1970-01-01 01:00:00.000000000 +0100
6882 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/power.c      2013-07-06 15:25:50.000000000 +0100
6883 @@ -0,0 +1,194 @@
6884 +/*
6885 + *      linux/arch/arm/mach-bcm2708/power.c
6886 + *
6887 + *      Copyright (C) 2010 Broadcom
6888 + *
6889 + * This program is free software; you can redistribute it and/or modify
6890 + * it under the terms of the GNU General Public License version 2 as
6891 + * published by the Free Software Foundation.
6892 + *
6893 + * This device provides a shared mechanism for controlling the power to
6894 + * VideoCore subsystems.
6895 + */
6896 +
6897 +#include <linux/module.h>
6898 +#include <linux/semaphore.h>
6899 +#include <linux/bug.h>
6900 +#include <mach/power.h>
6901 +#include <mach/vcio.h>
6902 +#include <mach/arm_power.h>
6903 +
6904 +#define DRIVER_NAME "bcm2708_power"
6905 +
6906 +#define BCM_POWER_MAXCLIENTS 4
6907 +#define BCM_POWER_NOCLIENT (1<<31)
6908 +
6909 +/* Some drivers expect there devices to be permanently powered */
6910 +#define BCM_POWER_ALWAYS_ON (BCM_POWER_USB)
6911 +
6912 +#if 1
6913 +#define DPRINTK printk
6914 +#else
6915 +#define DPRINTK if (0) printk
6916 +#endif
6917 +
6918 +struct state_struct {
6919 +       uint32_t global_request;
6920 +       uint32_t client_request[BCM_POWER_MAXCLIENTS];
6921 +       struct semaphore client_mutex;
6922 +       struct semaphore mutex;
6923 +} g_state;
6924 +
6925 +int bcm_power_open(BCM_POWER_HANDLE_T *handle)
6926 +{
6927 +       BCM_POWER_HANDLE_T i;
6928 +       int ret = -EBUSY;
6929 +
6930 +       down(&g_state.client_mutex);
6931 +
6932 +       for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
6933 +               if (g_state.client_request[i] == BCM_POWER_NOCLIENT) {
6934 +                       g_state.client_request[i] = BCM_POWER_NONE;
6935 +                       *handle = i;
6936 +                       ret = 0;
6937 +                       break;
6938 +               }
6939 +       }
6940 +
6941 +       up(&g_state.client_mutex);
6942 +
6943 +       DPRINTK("bcm_power_open() -> %d\n", *handle);
6944 +
6945 +       return ret;
6946 +}
6947 +EXPORT_SYMBOL_GPL(bcm_power_open);
6948 +
6949 +int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request)
6950 +{
6951 +       int rc = 0;
6952 +
6953 +       DPRINTK("bcm_power_request(%d, %x)\n", handle, request);
6954 +
6955 +       if ((handle < BCM_POWER_MAXCLIENTS) &&
6956 +           (g_state.client_request[handle] != BCM_POWER_NOCLIENT)) {
6957 +               if (down_interruptible(&g_state.mutex) != 0) {
6958 +                       DPRINTK("bcm_power_request -> interrupted\n");
6959 +                       return -EINTR;
6960 +               }
6961 +
6962 +               if (request != g_state.client_request[handle]) {
6963 +                       uint32_t others_request = 0;
6964 +                       uint32_t global_request;
6965 +                       BCM_POWER_HANDLE_T i;
6966 +
6967 +                       for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
6968 +                               if (i != handle)
6969 +                                       others_request |=
6970 +                                           g_state.client_request[i];
6971 +                       }
6972 +                       others_request &= ~BCM_POWER_NOCLIENT;
6973 +
6974 +                       global_request = request | others_request;
6975 +                       if (global_request != g_state.global_request) {
6976 +                               uint32_t actual;
6977 +
6978 +                               /* Send a request to VideoCore */
6979 +                               bcm_mailbox_write(MBOX_CHAN_POWER,
6980 +                                                 global_request << 4);
6981 +
6982 +                               /* Wait for a response during power-up */
6983 +                               if (global_request & ~g_state.global_request) {
6984 +                                       rc = bcm_mailbox_read(MBOX_CHAN_POWER,
6985 +                                                             &actual);
6986 +                                       DPRINTK
6987 +                                           ("bcm_mailbox_read -> %08x, %d\n",
6988 +                                            actual, rc);
6989 +                                       actual >>= 4;
6990 +                               } else {
6991 +                                       rc = 0;
6992 +                                       actual = global_request;
6993 +                               }
6994 +
6995 +                               if (rc == 0) {
6996 +                                       if (actual != global_request) {
6997 +                                               printk(KERN_ERR
6998 +                                                    "%s: prev global %x, new global %x, actual %x, request %x, others_request %x\n",
6999 +                                                    __func__,
7000 +                                                    g_state.global_request,
7001 +                                                    global_request, actual, request, others_request);
7002 +                                               /* A failure */
7003 +                                               BUG_ON((others_request & actual)
7004 +                                                      != others_request);
7005 +                                               request &= actual;
7006 +                                               rc = -EIO;
7007 +                                       }
7008 +
7009 +                                       g_state.global_request = actual;
7010 +                                       g_state.client_request[handle] =
7011 +                                           request;
7012 +                               }
7013 +                       }
7014 +               }
7015 +               up(&g_state.mutex);
7016 +       } else {
7017 +               rc = -EINVAL;
7018 +       }
7019 +       DPRINTK("bcm_power_request -> %d\n", rc);
7020 +       return rc;
7021 +}
7022 +EXPORT_SYMBOL_GPL(bcm_power_request);
7023 +
7024 +int bcm_power_close(BCM_POWER_HANDLE_T handle)
7025 +{
7026 +       int rc;
7027 +
7028 +       DPRINTK("bcm_power_close(%d)\n", handle);
7029 +
7030 +       rc = bcm_power_request(handle, BCM_POWER_NONE);
7031 +       if (rc == 0)
7032 +               g_state.client_request[handle] = BCM_POWER_NOCLIENT;
7033 +
7034 +       return rc;
7035 +}
7036 +EXPORT_SYMBOL_GPL(bcm_power_close);
7037 +
7038 +static int __init bcm_power_init(void)
7039 +{
7040 +#if defined(BCM_POWER_ALWAYS_ON)
7041 +       BCM_POWER_HANDLE_T always_on_handle;
7042 +#endif
7043 +       int rc = 0;
7044 +       int i;
7045 +
7046 +       printk(KERN_INFO "bcm_power: Broadcom power driver\n");
7047 +       bcm_mailbox_write(MBOX_CHAN_POWER, 0);
7048 +
7049 +       for (i = 0; i < BCM_POWER_MAXCLIENTS; i++)
7050 +               g_state.client_request[i] = BCM_POWER_NOCLIENT;
7051 +
7052 +       sema_init(&g_state.client_mutex, 1);
7053 +       sema_init(&g_state.mutex, 1);
7054 +
7055 +       g_state.global_request = 0;
7056 +
7057 +#if defined(BCM_POWER_ALWAYS_ON)
7058 +       if (BCM_POWER_ALWAYS_ON) {
7059 +               bcm_power_open(&always_on_handle);
7060 +               bcm_power_request(always_on_handle, BCM_POWER_ALWAYS_ON);
7061 +       }
7062 +#endif
7063 +
7064 +       return rc;
7065 +}
7066 +
7067 +static void __exit bcm_power_exit(void)
7068 +{
7069 +       bcm_mailbox_write(MBOX_CHAN_POWER, 0);
7070 +}
7071 +
7072 +arch_initcall(bcm_power_init); /* Initialize early */
7073 +module_exit(bcm_power_exit);
7074 +
7075 +MODULE_AUTHOR("Phil Elwell");
7076 +MODULE_DESCRIPTION("Interface to BCM2708 power management");
7077 +MODULE_LICENSE("GPL");
7078 diff -urN linux-3.10/arch/arm/mach-bcm2708/vcio.c linux-rpi-3.10.y/arch/arm/mach-bcm2708/vcio.c
7079 --- linux-3.10/arch/arm/mach-bcm2708/vcio.c     1970-01-01 01:00:00.000000000 +0100
7080 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/vcio.c       2013-07-06 15:25:50.000000000 +0100
7081 @@ -0,0 +1,474 @@
7082 +/*
7083 + *  linux/arch/arm/mach-bcm2708/vcio.c
7084 + *
7085 + *  Copyright (C) 2010 Broadcom
7086 + *
7087 + * This program is free software; you can redistribute it and/or modify
7088 + * it under the terms of the GNU General Public License version 2 as
7089 + * published by the Free Software Foundation.
7090 + *
7091 + * This device provides a shared mechanism for writing to the mailboxes,
7092 + * semaphores, doorbells etc. that are shared between the ARM and the
7093 + * VideoCore processor
7094 + */
7095 +
7096 +#if defined(CONFIG_SERIAL_BCM_MBOX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
7097 +#define SUPPORT_SYSRQ
7098 +#endif
7099 +
7100 +#include <linux/module.h>
7101 +#include <linux/console.h>
7102 +#include <linux/serial_core.h>
7103 +#include <linux/serial.h>
7104 +#include <linux/errno.h>
7105 +#include <linux/device.h>
7106 +#include <linux/init.h>
7107 +#include <linux/mm.h>
7108 +#include <linux/dma-mapping.h>
7109 +#include <linux/platform_device.h>
7110 +#include <linux/sysrq.h>
7111 +#include <linux/delay.h>
7112 +#include <linux/slab.h>
7113 +#include <linux/interrupt.h>
7114 +#include <linux/irq.h>
7115 +
7116 +#include <linux/io.h>
7117 +
7118 +#include <mach/vcio.h>
7119 +#include <mach/platform.h>
7120 +
7121 +#include <asm/uaccess.h>
7122 +
7123 +
7124 +#define DRIVER_NAME BCM_VCIO_DRIVER_NAME
7125 +
7126 +/* ----------------------------------------------------------------------
7127 + *     Mailbox
7128 + * -------------------------------------------------------------------- */
7129 +
7130 +/* offsets from a mail box base address */
7131 +#define MAIL_WRT       0x00    /* write - and next 4 words */
7132 +#define MAIL_RD                0x00    /* read - and next 4 words */
7133 +#define MAIL_POL       0x10    /* read without popping the fifo */
7134 +#define MAIL_SND       0x14    /* sender ID (bottom two bits) */
7135 +#define MAIL_STA       0x18    /* status */
7136 +#define MAIL_CNF       0x1C    /* configuration */
7137 +
7138 +#define MBOX_MSG(chan, data28)         (((data28) & ~0xf) | ((chan) & 0xf))
7139 +#define MBOX_MSG_LSB(chan, data28) (((data28) << 4) | ((chan) & 0xf))
7140 +#define MBOX_CHAN(msg)                 ((msg) & 0xf)
7141 +#define MBOX_DATA28(msg)               ((msg) & ~0xf)
7142 +#define MBOX_DATA28_LSB(msg)           (((uint32_t)msg) >> 4)
7143 +
7144 +#define MBOX_MAGIC 0xd0d0c0de
7145 +
7146 +struct vc_mailbox {
7147 +       struct device *dev;     /* parent device */
7148 +       void __iomem *status;
7149 +       void __iomem *config;
7150 +       void __iomem *read;
7151 +       void __iomem *write;
7152 +       uint32_t msg[MBOX_CHAN_COUNT];
7153 +       struct semaphore sema[MBOX_CHAN_COUNT];
7154 +       uint32_t magic;
7155 +};
7156 +
7157 +static void mbox_init(struct vc_mailbox *mbox_out, struct device *dev,
7158 +                     uint32_t addr_mbox)
7159 +{
7160 +       int i;
7161 +
7162 +       mbox_out->dev = dev;
7163 +       mbox_out->status = __io_address(addr_mbox + MAIL_STA);
7164 +       mbox_out->config = __io_address(addr_mbox + MAIL_CNF);
7165 +       mbox_out->read = __io_address(addr_mbox + MAIL_RD);
7166 +       /* Write to the other mailbox */
7167 +       mbox_out->write =
7168 +           __io_address((addr_mbox ^ ARM_0_MAIL0_WRT ^ ARM_0_MAIL1_WRT) +
7169 +                        MAIL_WRT);
7170 +
7171 +       for (i = 0; i < MBOX_CHAN_COUNT; i++) {
7172 +               mbox_out->msg[i] = 0;
7173 +               sema_init(&mbox_out->sema[i], 0);
7174 +       }
7175 +
7176 +       /* Enable the interrupt on data reception */
7177 +       writel(ARM_MC_IHAVEDATAIRQEN, mbox_out->config);
7178 +
7179 +       mbox_out->magic = MBOX_MAGIC;
7180 +}
7181 +
7182 +static int mbox_write(struct vc_mailbox *mbox, unsigned chan, uint32_t data28)
7183 +{
7184 +       int rc;
7185 +
7186 +       if (mbox->magic != MBOX_MAGIC)
7187 +               rc = -EINVAL;
7188 +       else {
7189 +               /* wait for the mailbox FIFO to have some space in it */
7190 +               while (0 != (readl(mbox->status) & ARM_MS_FULL))
7191 +                       cpu_relax();
7192 +
7193 +               writel(MBOX_MSG(chan, data28), mbox->write);
7194 +               rc = 0;
7195 +       }
7196 +       return rc;
7197 +}
7198 +
7199 +static int mbox_read(struct vc_mailbox *mbox, unsigned chan, uint32_t *data28)
7200 +{
7201 +       int rc;
7202 +
7203 +       if (mbox->magic != MBOX_MAGIC)
7204 +               rc = -EINVAL;
7205 +       else {
7206 +               down(&mbox->sema[chan]);
7207 +               *data28 = MBOX_DATA28(mbox->msg[chan]);
7208 +               mbox->msg[chan] = 0;
7209 +               rc = 0;
7210 +       }
7211 +       return rc;
7212 +}
7213 +
7214 +static irqreturn_t mbox_irq(int irq, void *dev_id)
7215 +{
7216 +       /* wait for the mailbox FIFO to have some data in it */
7217 +       struct vc_mailbox *mbox = (struct vc_mailbox *) dev_id;
7218 +       int status = readl(mbox->status);
7219 +       int ret = IRQ_NONE;
7220 +
7221 +       while (!(status & ARM_MS_EMPTY)) {
7222 +               uint32_t msg = readl(mbox->read);
7223 +               int chan = MBOX_CHAN(msg);
7224 +               if (chan < MBOX_CHAN_COUNT) {
7225 +                       if (mbox->msg[chan]) {
7226 +                               /* Overflow */
7227 +                               printk(KERN_ERR DRIVER_NAME
7228 +                                      ": mbox chan %d overflow - drop %08x\n",
7229 +                                      chan, msg);
7230 +                       } else {
7231 +                               mbox->msg[chan] = (msg | 0xf);
7232 +                               up(&mbox->sema[chan]);
7233 +                       }
7234 +               } else {
7235 +                       printk(KERN_ERR DRIVER_NAME
7236 +                              ": invalid channel selector (msg %08x)\n", msg);
7237 +               }
7238 +               ret = IRQ_HANDLED;
7239 +               status = readl(mbox->status);
7240 +       }
7241 +       return ret;
7242 +}
7243 +
7244 +static struct irqaction mbox_irqaction = {
7245 +       .name = "ARM Mailbox IRQ",
7246 +       .flags = IRQF_DISABLED | IRQF_IRQPOLL,
7247 +       .handler = mbox_irq,
7248 +};
7249 +
7250 +/* ----------------------------------------------------------------------
7251 + *     Mailbox Methods
7252 + * -------------------------------------------------------------------- */
7253 +
7254 +static struct device *mbox_dev;        /* we assume there's only one! */
7255 +
7256 +static int dev_mbox_write(struct device *dev, unsigned chan, uint32_t data28)
7257 +{
7258 +       int rc;
7259 +
7260 +       struct vc_mailbox *mailbox = dev_get_drvdata(dev);
7261 +       device_lock(dev);
7262 +       rc = mbox_write(mailbox, chan, data28);
7263 +       device_unlock(dev);
7264 +
7265 +       return rc;
7266 +}
7267 +
7268 +static int dev_mbox_read(struct device *dev, unsigned chan, uint32_t *data28)
7269 +{
7270 +       int rc;
7271 +
7272 +       struct vc_mailbox *mailbox = dev_get_drvdata(dev);
7273 +       device_lock(dev);
7274 +       rc = mbox_read(mailbox, chan, data28);
7275 +       device_unlock(dev);
7276 +
7277 +       return rc;
7278 +}
7279 +
7280 +extern int bcm_mailbox_write(unsigned chan, uint32_t data28)
7281 +{
7282 +       if (mbox_dev)
7283 +               return dev_mbox_write(mbox_dev, chan, data28);
7284 +       else
7285 +               return -ENODEV;
7286 +}
7287 +EXPORT_SYMBOL_GPL(bcm_mailbox_write);
7288 +
7289 +extern int bcm_mailbox_read(unsigned chan, uint32_t *data28)
7290 +{
7291 +       if (mbox_dev)
7292 +               return dev_mbox_read(mbox_dev, chan, data28);
7293 +       else
7294 +               return -ENODEV;
7295 +}
7296 +EXPORT_SYMBOL_GPL(bcm_mailbox_read);
7297 +
7298 +static void dev_mbox_register(const char *dev_name, struct device *dev)
7299 +{
7300 +       mbox_dev = dev;
7301 +}
7302 +
7303 +static int mbox_copy_from_user(void *dst, const void *src, int size)
7304 +{
7305 +       if ( (uint32_t)src < TASK_SIZE)
7306 +       {
7307 +               return copy_from_user(dst, src, size);
7308 +       }
7309 +       else
7310 +       {
7311 +               memcpy( dst, src, size );
7312 +               return 0;
7313 +       }
7314 +}
7315 +
7316 +static int mbox_copy_to_user(void *dst, const void *src, int size)
7317 +{
7318 +       if ( (uint32_t)dst < TASK_SIZE)
7319 +       {
7320 +               return copy_to_user(dst, src, size);
7321 +       }
7322 +       else
7323 +       {
7324 +               memcpy( dst, src, size );
7325 +               return 0;
7326 +       }
7327 +}
7328 +
7329 +static DEFINE_MUTEX(mailbox_lock);
7330 +extern int bcm_mailbox_property(void *data, int size)
7331 +{
7332 +       uint32_t success;
7333 +       dma_addr_t mem_bus;                             /* the memory address accessed from videocore */
7334 +       void *mem_kern;                                 /* the memory address accessed from driver */
7335 +       int s = 0;
7336 +
7337 +        mutex_lock(&mailbox_lock);
7338 +       /* allocate some memory for the messages communicating with GPU */
7339 +       mem_kern = dma_alloc_coherent(NULL, PAGE_ALIGN(size), &mem_bus, GFP_ATOMIC);
7340 +       if (mem_kern) {
7341 +               /* create the message */
7342 +               mbox_copy_from_user(mem_kern, data, size);
7343 +
7344 +               /* send the message */
7345 +               wmb();
7346 +               s = bcm_mailbox_write(MBOX_CHAN_PROPERTY, (uint32_t)mem_bus);
7347 +               if (s == 0) {
7348 +                       s = bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success);
7349 +               }
7350 +               if (s == 0) {
7351 +                       /* copy the response */
7352 +                       rmb();
7353 +                       mbox_copy_to_user(data, mem_kern, size);
7354 +               }
7355 +               dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus);
7356 +       } else {
7357 +               s = -ENOMEM;
7358 +       }
7359 +       if (s != 0)
7360 +               printk(KERN_ERR DRIVER_NAME ": %s failed (%d)\n", __func__, s);
7361 +
7362 +        mutex_unlock(&mailbox_lock);
7363 +       return s;
7364 +}
7365 +EXPORT_SYMBOL_GPL(bcm_mailbox_property);
7366 +
7367 +/* ----------------------------------------------------------------------
7368 + *     Platform Device for Mailbox
7369 + * -------------------------------------------------------------------- */
7370 +
7371 +/*
7372 + * Is the device open right now? Used to prevent
7373 + * concurent access into the same device
7374 + */
7375 +static int Device_Open = 0;
7376 +
7377 +/*
7378 + * This is called whenever a process attempts to open the device file
7379 + */
7380 +static int device_open(struct inode *inode, struct file *file)
7381 +{
7382 +       /*
7383 +        * We don't want to talk to two processes at the same time
7384 +        */
7385 +       if (Device_Open)
7386 +               return -EBUSY;
7387 +
7388 +       Device_Open++;
7389 +       /*
7390 +        * Initialize the message
7391 +        */
7392 +       try_module_get(THIS_MODULE);
7393 +       return 0;
7394 +}
7395 +
7396 +static int device_release(struct inode *inode, struct file *file)
7397 +{
7398 +       /*
7399 +        * We're now ready for our next caller
7400 +        */
7401 +       Device_Open--;
7402 +
7403 +       module_put(THIS_MODULE);
7404 +       return 0;
7405 +}
7406 +
7407 +/*
7408 + * This function is called whenever a process tries to do an ioctl on our
7409 + * device file. We get two extra parameters (additional to the inode and file
7410 + * structures, which all device functions get): the number of the ioctl called
7411 + * and the parameter given to the ioctl function.
7412 + *
7413 + * If the ioctl is write or read/write (meaning output is returned to the
7414 + * calling process), the ioctl call returns the output of this function.
7415 + *
7416 + */
7417 +static long device_ioctl(struct file *file,    /* see include/linux/fs.h */
7418 +                unsigned int ioctl_num,        /* number and param for ioctl */
7419 +                unsigned long ioctl_param)
7420 +{
7421 +       unsigned size;
7422 +       /*
7423 +        * Switch according to the ioctl called
7424 +        */
7425 +       switch (ioctl_num) {
7426 +       case IOCTL_MBOX_PROPERTY:
7427 +               /*
7428 +                * Receive a pointer to a message (in user space) and set that
7429 +                * to be the device's message.  Get the parameter given to
7430 +                * ioctl by the process.
7431 +                */
7432 +               mbox_copy_from_user(&size, (void *)ioctl_param, sizeof size);
7433 +               return bcm_mailbox_property((void *)ioctl_param, size);
7434 +               break;
7435 +       default:
7436 +               printk(KERN_ERR DRIVER_NAME "unknown ioctl: %d\n", ioctl_num);
7437 +               return -EINVAL;
7438 +       }
7439 +
7440 +       return 0;
7441 +}
7442 +
7443 +/* Module Declarations */
7444 +
7445 +/*
7446 + * This structure will hold the functions to be called
7447 + * when a process does something to the device we
7448 + * created. Since a pointer to this structure is kept in
7449 + * the devices table, it can't be local to
7450 + * init_module. NULL is for unimplemented functios.
7451 + */
7452 +struct file_operations fops = {
7453 +       .unlocked_ioctl = device_ioctl,
7454 +       .open = device_open,
7455 +       .release = device_release,      /* a.k.a. close */
7456 +};
7457 +
7458 +static int bcm_vcio_probe(struct platform_device *pdev)
7459 +{
7460 +       int ret = 0;
7461 +       struct vc_mailbox *mailbox;
7462 +
7463 +       mailbox = kzalloc(sizeof(*mailbox), GFP_KERNEL);
7464 +       if (NULL == mailbox) {
7465 +               printk(KERN_ERR DRIVER_NAME ": failed to allocate "
7466 +                      "mailbox memory\n");
7467 +               ret = -ENOMEM;
7468 +       } else {
7469 +               struct resource *res;
7470 +
7471 +               res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7472 +               if (res == NULL) {
7473 +                       printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
7474 +                              "resource\n");
7475 +                       ret = -ENODEV;
7476 +                       kfree(mailbox);
7477 +               } else {
7478 +                       /* should be based on the registers from res really */
7479 +                       mbox_init(mailbox, &pdev->dev, ARM_0_MAIL0_RD);
7480 +
7481 +                       platform_set_drvdata(pdev, mailbox);
7482 +                       dev_mbox_register(DRIVER_NAME, &pdev->dev);
7483 +
7484 +                       mbox_irqaction.dev_id = mailbox;
7485 +                       setup_irq(IRQ_ARM_MAILBOX, &mbox_irqaction);
7486 +                       printk(KERN_INFO DRIVER_NAME ": mailbox at %p\n",
7487 +                              __io_address(ARM_0_MAIL0_RD));
7488 +               }
7489 +       }
7490 +
7491 +       if (ret == 0) {
7492 +               /*
7493 +                * Register the character device
7494 +                */
7495 +               ret = register_chrdev(MAJOR_NUM, DEVICE_FILE_NAME, &fops);
7496 +
7497 +               /*
7498 +                * Negative values signify an error
7499 +                */
7500 +               if (ret < 0) {
7501 +                       printk(KERN_ERR DRIVER_NAME
7502 +                              "Failed registering the character device %d\n", ret);
7503 +                       return ret;
7504 +               }
7505 +       }
7506 +       return ret;
7507 +}
7508 +
7509 +static int bcm_vcio_remove(struct platform_device *pdev)
7510 +{
7511 +       struct vc_mailbox *mailbox = platform_get_drvdata(pdev);
7512 +
7513 +       platform_set_drvdata(pdev, NULL);
7514 +       kfree(mailbox);
7515 +
7516 +       return 0;
7517 +}
7518 +
7519 +static struct platform_driver bcm_mbox_driver = {
7520 +       .probe = bcm_vcio_probe,
7521 +       .remove = bcm_vcio_remove,
7522 +
7523 +       .driver = {
7524 +                  .name = DRIVER_NAME,
7525 +                  .owner = THIS_MODULE,
7526 +                  },
7527 +};
7528 +
7529 +static int __init bcm_mbox_init(void)
7530 +{
7531 +       int ret;
7532 +
7533 +       printk(KERN_INFO "mailbox: Broadcom VideoCore Mailbox driver\n");
7534 +
7535 +       ret = platform_driver_register(&bcm_mbox_driver);
7536 +       if (ret != 0) {
7537 +               printk(KERN_ERR DRIVER_NAME ": failed to register "
7538 +                      "on platform\n");
7539 +       }
7540 +
7541 +       return ret;
7542 +}
7543 +
7544 +static void __exit bcm_mbox_exit(void)
7545 +{
7546 +       platform_driver_unregister(&bcm_mbox_driver);
7547 +}
7548 +
7549 +arch_initcall(bcm_mbox_init);  /* Initialize early */
7550 +module_exit(bcm_mbox_exit);
7551 +
7552 +MODULE_AUTHOR("Gray Girling");
7553 +MODULE_DESCRIPTION("ARM I/O to VideoCore processor");
7554 +MODULE_LICENSE("GPL");
7555 +MODULE_ALIAS("platform:bcm-mbox");
7556 diff -urN linux-3.10/arch/arm/mach-bcm2708/vc_mem.c linux-rpi-3.10.y/arch/arm/mach-bcm2708/vc_mem.c
7557 --- linux-3.10/arch/arm/mach-bcm2708/vc_mem.c   1970-01-01 01:00:00.000000000 +0100
7558 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/vc_mem.c     2013-07-06 15:25:50.000000000 +0100
7559 @@ -0,0 +1,462 @@
7560 +/*****************************************************************************
7561 +* Copyright 2010 - 2011 Broadcom Corporation.  All rights reserved.
7562 +*
7563 +* Unless you and Broadcom execute a separate written software license
7564 +* agreement governing use of this software, this software is licensed to you
7565 +* under the terms of the GNU General Public License version 2, available at
7566 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
7567 +*
7568 +* Notwithstanding the above, under no circumstances may you combine this
7569 +* software in any way with any other Broadcom software provided under a
7570 +* license other than the GPL, without Broadcom's express prior written
7571 +* consent.
7572 +*****************************************************************************/
7573 +
7574 +#include <linux/kernel.h>
7575 +#include <linux/module.h>
7576 +#include <linux/fs.h>
7577 +#include <linux/device.h>
7578 +#include <linux/cdev.h>
7579 +#include <linux/mm.h>
7580 +#include <linux/slab.h>
7581 +#include <linux/proc_fs.h>
7582 +#include <asm/uaccess.h>
7583 +#include <linux/dma-mapping.h>
7584 +
7585 +#ifdef CONFIG_ARCH_KONA
7586 +#include <chal/chal_ipc.h>
7587 +#elif CONFIG_ARCH_BCM2708
7588 +#else
7589 +#include <csp/chal_ipc.h>
7590 +#endif
7591 +
7592 +#include "mach/vc_mem.h"
7593 +#include <mach/vcio.h>
7594 +
7595 +#define DRIVER_NAME  "vc-mem"
7596 +
7597 +// Uncomment to enable debug logging
7598 +// #define ENABLE_DBG
7599 +
7600 +#if defined(ENABLE_DBG)
7601 +#define LOG_DBG( fmt, ... )  printk( KERN_INFO fmt "\n", ##__VA_ARGS__ )
7602 +#else
7603 +#define LOG_DBG( fmt, ... )
7604 +#endif
7605 +#define LOG_ERR( fmt, ... )  printk( KERN_ERR fmt "\n", ##__VA_ARGS__ )
7606 +
7607 +// Device (/dev) related variables
7608 +static dev_t vc_mem_devnum = 0;
7609 +static struct class *vc_mem_class = NULL;
7610 +static struct cdev vc_mem_cdev;
7611 +static int vc_mem_inited = 0;
7612 +
7613 +// Proc entry
7614 +static struct proc_dir_entry *vc_mem_proc_entry;
7615 +
7616 +/*
7617 + * Videocore memory addresses and size
7618 + *
7619 + * Drivers that wish to know the videocore memory addresses and sizes should
7620 + * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
7621 + * headers. This allows the other drivers to not be tied down to a a certain
7622 + * address/size at compile time.
7623 + *
7624 + * In the future, the goal is to have the videocore memory virtual address and
7625 + * size be calculated at boot time rather than at compile time. The decision of
7626 + * where the videocore memory resides and its size would be in the hands of the
7627 + * bootloader (and/or kernel). When that happens, the values of these variables
7628 + * would be calculated and assigned in the init function.
7629 + */
7630 +// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
7631 +unsigned long mm_vc_mem_phys_addr = 0x00000000;
7632 +unsigned int mm_vc_mem_size = 0;
7633 +unsigned int mm_vc_mem_base = 0;
7634 +
7635 +EXPORT_SYMBOL(mm_vc_mem_phys_addr);
7636 +EXPORT_SYMBOL(mm_vc_mem_size);
7637 +EXPORT_SYMBOL(mm_vc_mem_base);
7638 +
7639 +static uint phys_addr = 0;
7640 +static uint mem_size = 0;
7641 +static uint mem_base = 0;
7642 +
7643 +
7644 +/****************************************************************************
7645 +*
7646 +*   vc_mem_open
7647 +*
7648 +***************************************************************************/
7649 +
7650 +static int
7651 +vc_mem_open(struct inode *inode, struct file *file)
7652 +{
7653 +       (void) inode;
7654 +       (void) file;
7655 +
7656 +       LOG_DBG("%s: called file = 0x%p", __func__, file);
7657 +
7658 +       return 0;
7659 +}
7660 +
7661 +/****************************************************************************
7662 +*
7663 +*   vc_mem_release
7664 +*
7665 +***************************************************************************/
7666 +
7667 +static int
7668 +vc_mem_release(struct inode *inode, struct file *file)
7669 +{
7670 +       (void) inode;
7671 +       (void) file;
7672 +
7673 +       LOG_DBG("%s: called file = 0x%p", __func__, file);
7674 +
7675 +       return 0;
7676 +}
7677 +
7678 +/****************************************************************************
7679 +*
7680 +*   vc_mem_get_size
7681 +*
7682 +***************************************************************************/
7683 +
7684 +static void
7685 +vc_mem_get_size(void)
7686 +{
7687 +}
7688 +
7689 +/****************************************************************************
7690 +*
7691 +*   vc_mem_get_base
7692 +*
7693 +***************************************************************************/
7694 +
7695 +static void
7696 +vc_mem_get_base(void)
7697 +{
7698 +}
7699 +
7700 +/****************************************************************************
7701 +*
7702 +*   vc_mem_get_current_size
7703 +*
7704 +***************************************************************************/
7705 +
7706 +int
7707 +vc_mem_get_current_size(void)
7708 +{
7709 +       return mm_vc_mem_size;
7710 +}
7711 +
7712 +EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
7713 +
7714 +/****************************************************************************
7715 +*
7716 +*   vc_mem_ioctl
7717 +*
7718 +***************************************************************************/
7719 +
7720 +static long
7721 +vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
7722 +{
7723 +       int rc = 0;
7724 +
7725 +       (void) cmd;
7726 +       (void) arg;
7727 +
7728 +       LOG_DBG("%s: called file = 0x%p", __func__, file);
7729 +
7730 +       switch (cmd) {
7731 +       case VC_MEM_IOC_MEM_PHYS_ADDR:
7732 +               {
7733 +                       LOG_DBG("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p",
7734 +                               __func__, (void *) mm_vc_mem_phys_addr);
7735 +
7736 +                       if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
7737 +                                        sizeof (mm_vc_mem_phys_addr)) != 0) {
7738 +                               rc = -EFAULT;
7739 +                       }
7740 +                       break;
7741 +               }
7742 +       case VC_MEM_IOC_MEM_SIZE:
7743 +               {
7744 +                       // Get the videocore memory size first
7745 +                       vc_mem_get_size();
7746 +
7747 +                       LOG_DBG("%s: VC_MEM_IOC_MEM_SIZE=%u", __func__,
7748 +                               mm_vc_mem_size);
7749 +
7750 +                       if (copy_to_user((void *) arg, &mm_vc_mem_size,
7751 +                                        sizeof (mm_vc_mem_size)) != 0) {
7752 +                               rc = -EFAULT;
7753 +                       }
7754 +                       break;
7755 +               }
7756 +       case VC_MEM_IOC_MEM_BASE:
7757 +               {
7758 +                       // Get the videocore memory base
7759 +                       vc_mem_get_base();
7760 +
7761 +                       LOG_DBG("%s: VC_MEM_IOC_MEM_BASE=%u", __func__,
7762 +                               mm_vc_mem_base);
7763 +
7764 +                       if (copy_to_user((void *) arg, &mm_vc_mem_base,
7765 +                                        sizeof (mm_vc_mem_base)) != 0) {
7766 +                               rc = -EFAULT;
7767 +                       }
7768 +                       break;
7769 +               }
7770 +       case VC_MEM_IOC_MEM_LOAD:
7771 +               {
7772 +                       // Get the videocore memory base
7773 +                       vc_mem_get_base();
7774 +
7775 +                       LOG_DBG("%s: VC_MEM_IOC_MEM_LOAD=%u", __func__,
7776 +                               mm_vc_mem_base);
7777 +
7778 +                       if (copy_to_user((void *) arg, &mm_vc_mem_base,
7779 +                                        sizeof (mm_vc_mem_base)) != 0) {
7780 +                               rc = -EFAULT;
7781 +                       }
7782 +                       break;
7783 +               }
7784 +       default:
7785 +               {
7786 +                       return -ENOTTY;
7787 +               }
7788 +       }
7789 +       LOG_DBG("%s: file = 0x%p returning %d", __func__, file, rc);
7790 +
7791 +       return rc;
7792 +}
7793 +
7794 +/****************************************************************************
7795 +*
7796 +*   vc_mem_mmap
7797 +*
7798 +***************************************************************************/
7799 +
7800 +static int
7801 +vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
7802 +{
7803 +       int rc = 0;
7804 +       unsigned long length = vma->vm_end - vma->vm_start;
7805 +       unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
7806 +
7807 +       LOG_DBG("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx",
7808 +               __func__, (long) vma->vm_start, (long) vma->vm_end,
7809 +               (long) vma->vm_pgoff);
7810 +
7811 +       if (offset + length > mm_vc_mem_size) {
7812 +               LOG_ERR("%s: length %ld is too big", __func__, length);
7813 +               return -EINVAL;
7814 +       }
7815 +       // Do not cache the memory map
7816 +       vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
7817 +
7818 +       rc = remap_pfn_range(vma, vma->vm_start,
7819 +                            (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
7820 +                            vma->vm_pgoff, length, vma->vm_page_prot);
7821 +       if (rc != 0) {
7822 +               LOG_ERR("%s: remap_pfn_range failed (rc=%d)", __func__, rc);
7823 +       }
7824 +
7825 +       return rc;
7826 +}
7827 +
7828 +/****************************************************************************
7829 +*
7830 +*   File Operations for the driver.
7831 +*
7832 +***************************************************************************/
7833 +
7834 +static const struct file_operations vc_mem_fops = {
7835 +       .owner = THIS_MODULE,
7836 +       .open = vc_mem_open,
7837 +       .release = vc_mem_release,
7838 +       .unlocked_ioctl = vc_mem_ioctl,
7839 +       .mmap = vc_mem_mmap,
7840 +};
7841 +
7842 +/****************************************************************************
7843 +*
7844 +*   vc_mem_proc_read
7845 +*
7846 +***************************************************************************/
7847 +
7848 +static int
7849 +vc_mem_proc_read(char *buf, char **start, off_t offset, int count, int *eof,
7850 +                void *data)
7851 +{
7852 +       char *p = buf;
7853 +
7854 +       (void) start;
7855 +       (void) count;
7856 +       (void) data;
7857 +
7858 +       if (offset > 0) {
7859 +               *eof = 1;
7860 +               return 0;
7861 +       }
7862 +       // Get the videocore memory size first
7863 +       vc_mem_get_size();
7864 +
7865 +       p += sprintf(p, "Videocore memory:\n");
7866 +       if (mm_vc_mem_phys_addr != 0)
7867 +               p += sprintf(p, "   Physical address: 0x%p\n",
7868 +                            (void *) mm_vc_mem_phys_addr);
7869 +       else
7870 +               p += sprintf(p, "   Physical address: 0x00000000\n");
7871 +       p += sprintf(p, "   Length (bytes):   %u\n", mm_vc_mem_size);
7872 +
7873 +       *eof = 1;
7874 +       return p - buf;
7875 +}
7876 +
7877 +/****************************************************************************
7878 +*
7879 +*   vc_mem_proc_write
7880 +*
7881 +***************************************************************************/
7882 +
7883 +static int
7884 +vc_mem_proc_write(struct file *file, const char __user * buffer,
7885 +                 unsigned long count, void *data)
7886 +{
7887 +       int rc = -EFAULT;
7888 +       char input_str[10];
7889 +
7890 +       memset(input_str, 0, sizeof (input_str));
7891 +
7892 +       if (count > sizeof (input_str)) {
7893 +               LOG_ERR("%s: input string length too long", __func__);
7894 +               goto out;
7895 +       }
7896 +
7897 +       if (copy_from_user(input_str, buffer, count - 1)) {
7898 +               LOG_ERR("%s: failed to get input string", __func__);
7899 +               goto out;
7900 +       }
7901 +
7902 +       if (strncmp(input_str, "connect", strlen("connect")) == 0) {
7903 +               // Get the videocore memory size from the videocore
7904 +               vc_mem_get_size();
7905 +       }
7906 +
7907 +      out:
7908 +       return rc;
7909 +}
7910 +
7911 +/****************************************************************************
7912 +*
7913 +*   vc_mem_init
7914 +*
7915 +***************************************************************************/
7916 +
7917 +static int __init
7918 +vc_mem_init(void)
7919 +{
7920 +       int rc = -EFAULT;
7921 +       struct device *dev;
7922 +
7923 +       LOG_DBG("%s: called", __func__);
7924 +
7925 +       mm_vc_mem_phys_addr = phys_addr;
7926 +       mm_vc_mem_size = mem_size;
7927 +       mm_vc_mem_base = mem_base;
7928 +
7929 +       vc_mem_get_size();
7930 +
7931 +       printk("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
7932 +               mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
7933 +
7934 +       if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
7935 +               LOG_ERR("%s: alloc_chrdev_region failed (rc=%d)", __func__, rc);
7936 +               goto out_err;
7937 +       }
7938 +
7939 +       cdev_init(&vc_mem_cdev, &vc_mem_fops);
7940 +       if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
7941 +               LOG_ERR("%s: cdev_add failed (rc=%d)", __func__, rc);
7942 +               goto out_unregister;
7943 +       }
7944 +
7945 +       vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
7946 +       if (IS_ERR(vc_mem_class)) {
7947 +               rc = PTR_ERR(vc_mem_class);
7948 +               LOG_ERR("%s: class_create failed (rc=%d)", __func__, rc);
7949 +               goto out_cdev_del;
7950 +       }
7951 +
7952 +       dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
7953 +                           DRIVER_NAME);
7954 +       if (IS_ERR(dev)) {
7955 +               rc = PTR_ERR(dev);
7956 +               LOG_ERR("%s: device_create failed (rc=%d)", __func__, rc);
7957 +               goto out_class_destroy;
7958 +       }
7959 +
7960 +#if 0
7961 +       vc_mem_proc_entry = create_proc_entry(DRIVER_NAME, 0444, NULL);
7962 +       if (vc_mem_proc_entry == NULL) {
7963 +               rc = -EFAULT;
7964 +               LOG_ERR("%s: create_proc_entry failed", __func__);
7965 +               goto out_device_destroy;
7966 +       }
7967 +       vc_mem_proc_entry->read_proc = vc_mem_proc_read;
7968 +       vc_mem_proc_entry->write_proc = vc_mem_proc_write;
7969 +#endif
7970 +
7971 +       vc_mem_inited = 1;
7972 +       return 0;
7973 +
7974 +      out_device_destroy:
7975 +       device_destroy(vc_mem_class, vc_mem_devnum);
7976 +
7977 +      out_class_destroy:
7978 +       class_destroy(vc_mem_class);
7979 +       vc_mem_class = NULL;
7980 +
7981 +      out_cdev_del:
7982 +       cdev_del(&vc_mem_cdev);
7983 +
7984 +      out_unregister:
7985 +       unregister_chrdev_region(vc_mem_devnum, 1);
7986 +
7987 +      out_err:
7988 +       return -1;
7989 +}
7990 +
7991 +/****************************************************************************
7992 +*
7993 +*   vc_mem_exit
7994 +*
7995 +***************************************************************************/
7996 +
7997 +static void __exit
7998 +vc_mem_exit(void)
7999 +{
8000 +       LOG_DBG("%s: called", __func__);
8001 +
8002 +       if (vc_mem_inited) {
8003 +#if 0
8004 +               remove_proc_entry(vc_mem_proc_entry->name, NULL);
8005 +#endif
8006 +               device_destroy(vc_mem_class, vc_mem_devnum);
8007 +               class_destroy(vc_mem_class);
8008 +               cdev_del(&vc_mem_cdev);
8009 +               unregister_chrdev_region(vc_mem_devnum, 1);
8010 +       }
8011 +}
8012 +
8013 +module_init(vc_mem_init);
8014 +module_exit(vc_mem_exit);
8015 +MODULE_LICENSE("GPL");
8016 +MODULE_AUTHOR("Broadcom Corporation");
8017 +
8018 +module_param(phys_addr, uint, 0644);
8019 +module_param(mem_size, uint, 0644);
8020 +module_param(mem_base, uint, 0644);
8021 +
8022 diff -urN linux-3.10/arch/arm/mach-bcm2708/vc_support.c linux-rpi-3.10.y/arch/arm/mach-bcm2708/vc_support.c
8023 --- linux-3.10/arch/arm/mach-bcm2708/vc_support.c       1970-01-01 01:00:00.000000000 +0100
8024 +++ linux-rpi-3.10.y/arch/arm/mach-bcm2708/vc_support.c 2013-07-06 15:25:50.000000000 +0100
8025 @@ -0,0 +1,319 @@
8026 +/*
8027 + * vc_support.c
8028 + *
8029 + *  Created on: 25 Nov 2012
8030 + *      Author: Simon
8031 + */
8032 +
8033 +#include <linux/module.h>
8034 +#include <mach/vcio.h>
8035 +
8036 +#ifdef ECLIPSE_IGNORE
8037 +
8038 +#define __user
8039 +#define __init
8040 +#define __exit
8041 +#define __iomem
8042 +#define KERN_DEBUG
8043 +#define KERN_ERR
8044 +#define KERN_WARNING
8045 +#define KERN_INFO
8046 +#define _IOWR(a, b, c) b
8047 +#define _IOW(a, b, c) b
8048 +#define _IO(a, b) b
8049 +
8050 +#endif
8051 +
8052 +/****** VC MAILBOX FUNCTIONALITY ******/
8053 +unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags)
8054 +{
8055 +       struct vc_msg
8056 +       {
8057 +               unsigned int m_msgSize;
8058 +               unsigned int m_response;
8059 +
8060 +               struct vc_tag
8061 +               {
8062 +                       unsigned int m_tagId;
8063 +                       unsigned int m_sendBufferSize;
8064 +                       union {
8065 +                               unsigned int m_sendDataSize;
8066 +                               unsigned int m_recvDataSize;
8067 +                       };
8068 +
8069 +                       struct args
8070 +                       {
8071 +                               union {
8072 +                                       unsigned int m_size;
8073 +                                       unsigned int m_handle;
8074 +                               };
8075 +                               unsigned int m_alignment;
8076 +                               unsigned int m_flags;
8077 +                       } m_args;
8078 +               } m_tag;
8079 +
8080 +               unsigned int m_endTag;
8081 +       } msg;
8082 +       int s;
8083 +
8084 +       msg.m_msgSize = sizeof(msg);
8085 +       msg.m_response = 0;
8086 +       msg.m_endTag = 0;
8087 +
8088 +       //fill in the tag for the allocation command
8089 +       msg.m_tag.m_tagId = 0x3000c;
8090 +       msg.m_tag.m_sendBufferSize = 12;
8091 +       msg.m_tag.m_sendDataSize = 12;
8092 +
8093 +       //fill in our args
8094 +       msg.m_tag.m_args.m_size = size;
8095 +       msg.m_tag.m_args.m_alignment = alignment;
8096 +       msg.m_tag.m_args.m_flags = flags;
8097 +
8098 +       //run the command
8099 +       s = bcm_mailbox_property(&msg, sizeof(msg));
8100 +
8101 +       if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
8102 +       {
8103 +               *pHandle = msg.m_tag.m_args.m_handle;
8104 +               return 0;
8105 +       }
8106 +       else
8107 +       {
8108 +               printk(KERN_ERR "failed to allocate vc memory: s=%d response=%08x recv data size=%08x\n",
8109 +                               s, msg.m_response, msg.m_tag.m_recvDataSize);
8110 +               return 1;
8111 +       }
8112 +}
8113 +
8114 +unsigned int ReleaseVcMemory(unsigned int handle)
8115 +{
8116 +       struct vc_msg
8117 +       {
8118 +               unsigned int m_msgSize;
8119 +               unsigned int m_response;
8120 +
8121 +               struct vc_tag
8122 +               {
8123 +                       unsigned int m_tagId;
8124 +                       unsigned int m_sendBufferSize;
8125 +                       union {
8126 +                               unsigned int m_sendDataSize;
8127 +                               unsigned int m_recvDataSize;
8128 +                       };
8129 +
8130 +                       struct args
8131 +                       {
8132 +                               union {
8133 +                                       unsigned int m_handle;
8134 +                                       unsigned int m_error;
8135 +                               };
8136 +                       } m_args;
8137 +               } m_tag;
8138 +
8139 +               unsigned int m_endTag;
8140 +       } msg;
8141 +       int s;
8142 +
8143 +       msg.m_msgSize = sizeof(msg);
8144 +       msg.m_response = 0;
8145 +       msg.m_endTag = 0;
8146 +
8147 +       //fill in the tag for the release command
8148 +       msg.m_tag.m_tagId = 0x3000f;
8149 +       msg.m_tag.m_sendBufferSize = 4;
8150 +       msg.m_tag.m_sendDataSize = 4;
8151 +
8152 +       //pass across the handle
8153 +       msg.m_tag.m_args.m_handle = handle;
8154 +
8155 +       s = bcm_mailbox_property(&msg, sizeof(msg));
8156 +
8157 +       if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0)
8158 +               return 0;
8159 +       else
8160 +       {
8161 +               printk(KERN_ERR "failed to release vc memory: s=%d response=%08x recv data size=%08x error=%08x\n",
8162 +                               s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error);
8163 +               return 1;
8164 +       }
8165 +}
8166 +
8167 +unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle)
8168 +{
8169 +       struct vc_msg
8170 +       {
8171 +               unsigned int m_msgSize;
8172 +               unsigned int m_response;
8173 +
8174 +               struct vc_tag
8175 +               {
8176 +                       unsigned int m_tagId;
8177 +                       unsigned int m_sendBufferSize;
8178 +                       union {
8179 +                               unsigned int m_sendDataSize;
8180 +                               unsigned int m_recvDataSize;
8181 +                       };
8182 +
8183 +                       struct args
8184 +                       {
8185 +                               union {
8186 +                                       unsigned int m_handle;
8187 +                                       unsigned int m_busAddress;
8188 +                               };
8189 +                       } m_args;
8190 +               } m_tag;
8191 +
8192 +               unsigned int m_endTag;
8193 +       } msg;
8194 +       int s;
8195 +
8196 +       msg.m_msgSize = sizeof(msg);
8197 +       msg.m_response = 0;
8198 +       msg.m_endTag = 0;
8199 +
8200 +       //fill in the tag for the lock command
8201 +       msg.m_tag.m_tagId = 0x3000d;
8202 +       msg.m_tag.m_sendBufferSize = 4;
8203 +       msg.m_tag.m_sendDataSize = 4;
8204 +
8205 +       //pass across the handle
8206 +       msg.m_tag.m_args.m_handle = handle;
8207 +
8208 +       s = bcm_mailbox_property(&msg, sizeof(msg));
8209 +
8210 +       if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
8211 +       {
8212 +               //pick out the bus address
8213 +               *pBusAddress = msg.m_tag.m_args.m_busAddress;
8214 +               return 0;
8215 +       }
8216 +       else
8217 +       {
8218 +               printk(KERN_ERR "failed to lock vc memory: s=%d response=%08x recv data size=%08x\n",
8219 +                               s, msg.m_response, msg.m_tag.m_recvDataSize);
8220 +               return 1;
8221 +       }
8222 +}
8223 +
8224 +unsigned int UnlockVcMemory(unsigned int handle)
8225 +{
8226 +       struct vc_msg
8227 +       {
8228 +               unsigned int m_msgSize;
8229 +               unsigned int m_response;
8230 +
8231 +               struct vc_tag
8232 +               {
8233 +                       unsigned int m_tagId;
8234 +                       unsigned int m_sendBufferSize;
8235 +                       union {
8236 +                               unsigned int m_sendDataSize;
8237 +                               unsigned int m_recvDataSize;
8238 +                       };
8239 +
8240 +                       struct args
8241 +                       {
8242 +                               union {
8243 +                                       unsigned int m_handle;
8244 +                                       unsigned int m_error;
8245 +                               };
8246 +                       } m_args;
8247 +               } m_tag;
8248 +
8249 +               unsigned int m_endTag;
8250 +       } msg;
8251 +       int s;
8252 +
8253 +       msg.m_msgSize = sizeof(msg);
8254 +       msg.m_response = 0;
8255 +       msg.m_endTag = 0;
8256 +
8257 +       //fill in the tag for the unlock command
8258 +       msg.m_tag.m_tagId = 0x3000e;
8259 +       msg.m_tag.m_sendBufferSize = 4;
8260 +       msg.m_tag.m_sendDataSize = 4;
8261 +
8262 +       //pass across the handle
8263 +       msg.m_tag.m_args.m_handle = handle;
8264 +
8265 +       s = bcm_mailbox_property(&msg, sizeof(msg));
8266 +
8267 +       //check the error code too
8268 +       if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0)
8269 +               return 0;
8270 +       else
8271 +       {
8272 +               printk(KERN_ERR "failed to unlock vc memory: s=%d response=%08x recv data size=%08x error%08x\n",
8273 +                               s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error);
8274 +               return 1;
8275 +       }
8276 +}
8277 +
8278 +unsigned int ExecuteVcCode(unsigned int code,
8279 +               unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5)
8280 +{
8281 +       struct vc_msg
8282 +       {
8283 +               unsigned int m_msgSize;
8284 +               unsigned int m_response;
8285 +
8286 +               struct vc_tag
8287 +               {
8288 +                       unsigned int m_tagId;
8289 +                       unsigned int m_sendBufferSize;
8290 +                       union {
8291 +                               unsigned int m_sendDataSize;
8292 +                               unsigned int m_recvDataSize;
8293 +                       };
8294 +
8295 +                       struct args
8296 +                       {
8297 +                               union {
8298 +                                       unsigned int m_pCode;
8299 +                                       unsigned int m_return;
8300 +                               };
8301 +                               unsigned int m_r0;
8302 +                               unsigned int m_r1;
8303 +                               unsigned int m_r2;
8304 +                               unsigned int m_r3;
8305 +                               unsigned int m_r4;
8306 +                               unsigned int m_r5;
8307 +                       } m_args;
8308 +               } m_tag;
8309 +
8310 +               unsigned int m_endTag;
8311 +       } msg;
8312 +       int s;
8313 +
8314 +       msg.m_msgSize = sizeof(msg);
8315 +       msg.m_response = 0;
8316 +       msg.m_endTag = 0;
8317 +
8318 +       //fill in the tag for the unlock command
8319 +       msg.m_tag.m_tagId = 0x30010;
8320 +       msg.m_tag.m_sendBufferSize = 28;
8321 +       msg.m_tag.m_sendDataSize = 28;
8322 +
8323 +       //pass across the handle
8324 +       msg.m_tag.m_args.m_pCode = code;
8325 +       msg.m_tag.m_args.m_r0 = r0;
8326 +       msg.m_tag.m_args.m_r1 = r1;
8327 +       msg.m_tag.m_args.m_r2 = r2;
8328 +       msg.m_tag.m_args.m_r3 = r3;
8329 +       msg.m_tag.m_args.m_r4 = r4;
8330 +       msg.m_tag.m_args.m_r5 = r5;
8331 +
8332 +       s = bcm_mailbox_property(&msg, sizeof(msg));
8333 +
8334 +       //check the error code too
8335 +       if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
8336 +               return msg.m_tag.m_args.m_return;
8337 +       else
8338 +       {
8339 +               printk(KERN_ERR "failed to execute: s=%d response=%08x recv data size=%08x\n",
8340 +                               s, msg.m_response, msg.m_tag.m_recvDataSize);
8341 +               return 1;
8342 +       }
8343 +}
8344 +
8345 diff -urN linux-3.10/arch/arm/Makefile linux-rpi-3.10.y/arch/arm/Makefile
8346 --- linux-3.10/arch/arm/Makefile        2013-06-30 23:13:29.000000000 +0100
8347 +++ linux-rpi-3.10.y/arch/arm/Makefile  2013-07-06 15:25:50.000000000 +0100
8348 @@ -139,6 +139,7 @@
8349  # by CONFIG_* macro name.
8350  machine-$(CONFIG_ARCH_AT91)            += at91
8351  machine-$(CONFIG_ARCH_BCM)             += bcm
8352 +machine-$(CONFIG_ARCH_BCM2708)         += bcm2708
8353  machine-$(CONFIG_ARCH_BCM2835)         += bcm2835
8354  machine-$(CONFIG_ARCH_CLPS711X)                += clps711x
8355  machine-$(CONFIG_ARCH_CNS3XXX)         += cns3xxx
8356 diff -urN linux-3.10/arch/arm/mm/Kconfig linux-rpi-3.10.y/arch/arm/mm/Kconfig
8357 --- linux-3.10/arch/arm/mm/Kconfig      2013-06-30 23:13:29.000000000 +0100
8358 +++ linux-rpi-3.10.y/arch/arm/mm/Kconfig        2013-07-06 15:25:50.000000000 +0100
8359 @@ -358,7 +358,7 @@
8360
8361  # ARMv6
8362  config CPU_V6
8363 -       bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
8364 +       bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708
8365         select CPU_32v6
8366         select CPU_ABRT_EV6
8367         select CPU_CACHE_V6
8368 diff -urN linux-3.10/arch/arm/mm/proc-v6.S linux-rpi-3.10.y/arch/arm/mm/proc-v6.S
8369 --- linux-3.10/arch/arm/mm/proc-v6.S    2013-06-30 23:13:29.000000000 +0100
8370 +++ linux-rpi-3.10.y/arch/arm/mm/proc-v6.S      2013-07-06 15:25:50.000000000 +0100
8371 @@ -73,10 +73,19 @@
8372   *
8373   *     IRQs are already disabled.
8374   */
8375 +
8376 +/* See jira SW-5991 for details of this workaround */
8377  ENTRY(cpu_v6_do_idle)
8378 -       mov     r1, #0
8379 -       mcr     p15, 0, r1, c7, c10, 4          @ DWB - WFI may enter a low-power mode
8380 -       mcr     p15, 0, r1, c7, c0, 4           @ wait for interrupt
8381 +       .align 5
8382 +       mov     r1, #2
8383 +1:     subs    r1, #1
8384 +       nop
8385 +       mcreq   p15, 0, r1, c7, c10, 4          @ DWB - WFI may enter a low-power mode
8386 +       mcreq   p15, 0, r1, c7, c0, 4           @ wait for interrupt
8387 +       nop
8388 +       nop
8389 +       nop
8390 +       bne 1b
8391         mov     pc, lr
8392
8393  ENTRY(cpu_v6_dcache_clean_area)
8394 diff -urN linux-3.10/arch/arm/tools/mach-types linux-rpi-3.10.y/arch/arm/tools/mach-types
8395 --- linux-3.10/arch/arm/tools/mach-types        2013-06-30 23:13:29.000000000 +0100
8396 +++ linux-rpi-3.10.y/arch/arm/tools/mach-types  2013-07-06 15:25:50.000000000 +0100
8397 @@ -522,6 +522,7 @@
8398  prima2_evb             MACH_PRIMA2_EVB         PRIMA2_EVB              3103
8399  paz00                  MACH_PAZ00              PAZ00                   3128
8400  acmenetusfoxg20                MACH_ACMENETUSFOXG20    ACMENETUSFOXG20         3129
8401 +bcm2708                        MACH_BCM2708            BCM2708                 3138
8402  ag5evm                 MACH_AG5EVM             AG5EVM                  3189
8403  ics_if_voip            MACH_ICS_IF_VOIP        ICS_IF_VOIP             3206
8404  wlf_cragg_6410         MACH_WLF_CRAGG_6410     WLF_CRAGG_6410          3207