target/linux/brcm2708/patches-3.10/0001-Main-bcm2708-linux-port.patch

   1 From 47ecfc09ad3289994f80bd3dcaec876ac536d884 Mon Sep 17 00:00:00 2001
   2 From: popcornmix <popcornmix@gmail.com>
   3 Date: Sun, 12 May 2013 12:24:19 +0100
   4 Subject: [PATCH 001/174] Main bcm2708 linux port
   5
   6 Signed-off-by: popcornmix <popcornmix@gmail.com>
   7 ---
   8  arch/arm/Kconfig                                 |   16 +
   9  arch/arm/Kconfig.debug                           |    8 +
  10  arch/arm/Makefile                                |    1 +
  11  arch/arm/configs/bcmrpi_cutdown_defconfig        |  474 +++++++
  12  arch/arm/configs/bcmrpi_defconfig                |  510 ++++++++
  13  arch/arm/configs/bcmrpi_emergency_defconfig      |  532 ++++++++
  14  arch/arm/kernel/process.c                        |    2 +-
  15  arch/arm/mach-bcm2708/Kconfig                    |   34 +
  16  arch/arm/mach-bcm2708/Makefile                   |    8 +
  17  arch/arm/mach-bcm2708/Makefile.boot              |    3 +
  18  arch/arm/mach-bcm2708/armctrl.c                  |  208 ++++
  19  arch/arm/mach-bcm2708/armctrl.h                  |   27 +
  20  arch/arm/mach-bcm2708/bcm2708.c                  |  695 +++++++++++
  21  arch/arm/mach-bcm2708/bcm2708.h                  |   51 +
  22  arch/arm/mach-bcm2708/bcm2708_gpio.c             |  339 +++++
  23  arch/arm/mach-bcm2708/clock.c                    |   61 +
  24  arch/arm/mach-bcm2708/clock.h                    |   24 +
  25  arch/arm/mach-bcm2708/dma.c                      |  399 ++++++
  26  arch/arm/mach-bcm2708/include/mach/arm_control.h |  419 +++++++
  27  arch/arm/mach-bcm2708/include/mach/arm_power.h   |   60 +
  28  arch/arm/mach-bcm2708/include/mach/clkdev.h      |    7 +
  29  arch/arm/mach-bcm2708/include/mach/debug-macro.S |   22 +
  30  arch/arm/mach-bcm2708/include/mach/dma.h         |   86 ++
  31  arch/arm/mach-bcm2708/include/mach/entry-macro.S |   69 ++
  32  arch/arm/mach-bcm2708/include/mach/frc.h         |   38 +
  33  arch/arm/mach-bcm2708/include/mach/gpio.h        |   18 +
  34  arch/arm/mach-bcm2708/include/mach/hardware.h    |   28 +
  35  arch/arm/mach-bcm2708/include/mach/io.h          |   27 +
  36  arch/arm/mach-bcm2708/include/mach/irqs.h        |  196 +++
  37  arch/arm/mach-bcm2708/include/mach/memory.h      |   57 +
  38  arch/arm/mach-bcm2708/include/mach/platform.h    |  220 ++++
  39  arch/arm/mach-bcm2708/include/mach/power.h       |   26 +
  40  arch/arm/mach-bcm2708/include/mach/system.h      |   38 +
  41  arch/arm/mach-bcm2708/include/mach/timex.h       |   23 +
  42  arch/arm/mach-bcm2708/include/mach/uncompress.h  |   85 ++
  43  arch/arm/mach-bcm2708/include/mach/vc_mem.h      |   36 +
  44  arch/arm/mach-bcm2708/include/mach/vcio.h        |  141 +++
  45  arch/arm/mach-bcm2708/include/mach/vmalloc.h     |   20 +
  46  arch/arm/mach-bcm2708/power.c                    |  194 +++
  47  arch/arm/mach-bcm2708/vc_mem.c                   |  462 +++++++
  48  arch/arm/mach-bcm2708/vcio.c                     |  474 +++++++
  49  arch/arm/mm/Kconfig                              |    2 +-
  50  arch/arm/mm/proc-v6.S                            |   15 +-
  51  arch/arm/tools/mach-types                        |    1 +
  52  drivers/mmc/host/Kconfig                         |   21 +
  53  drivers/mmc/host/Makefile                        |    1 +
  54  drivers/mmc/host/sdhci-bcm2708.c                 | 1425 ++++++++++++++++++++++
  55  drivers/mmc/host/sdhci.c                         |  209 +++-
  56  drivers/mmc/host/sdhci.h                         |   37 +
  57  include/linux/mmc/sdhci.h                        |    2 +
  58  50 files changed, 7779 insertions(+), 72 deletions(-)
  59  create mode 100644 arch/arm/configs/bcmrpi_cutdown_defconfig
  60  create mode 100644 arch/arm/configs/bcmrpi_defconfig
  61  create mode 100644 arch/arm/configs/bcmrpi_emergency_defconfig
  62  create mode 100644 arch/arm/mach-bcm2708/Kconfig
  63  create mode 100644 arch/arm/mach-bcm2708/Makefile
  64  create mode 100644 arch/arm/mach-bcm2708/Makefile.boot
  65  create mode 100644 arch/arm/mach-bcm2708/armctrl.c
  66  create mode 100644 arch/arm/mach-bcm2708/armctrl.h
  67  create mode 100644 arch/arm/mach-bcm2708/bcm2708.c
  68  create mode 100644 arch/arm/mach-bcm2708/bcm2708.h
  69  create mode 100644 arch/arm/mach-bcm2708/bcm2708_gpio.c
  70  create mode 100644 arch/arm/mach-bcm2708/clock.c
  71  create mode 100644 arch/arm/mach-bcm2708/clock.h
  72  create mode 100644 arch/arm/mach-bcm2708/dma.c
  73  create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_control.h
  74  create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_power.h
  75  create mode 100644 arch/arm/mach-bcm2708/include/mach/clkdev.h
  76  create mode 100644 arch/arm/mach-bcm2708/include/mach/debug-macro.S
  77  create mode 100644 arch/arm/mach-bcm2708/include/mach/dma.h
  78  create mode 100644 arch/arm/mach-bcm2708/include/mach/entry-macro.S
  79  create mode 100644 arch/arm/mach-bcm2708/include/mach/frc.h
  80  create mode 100644 arch/arm/mach-bcm2708/include/mach/gpio.h
  81  create mode 100644 arch/arm/mach-bcm2708/include/mach/hardware.h
  82  create mode 100644 arch/arm/mach-bcm2708/include/mach/io.h
  83  create mode 100644 arch/arm/mach-bcm2708/include/mach/irqs.h
  84  create mode 100644 arch/arm/mach-bcm2708/include/mach/memory.h
  85  create mode 100644 arch/arm/mach-bcm2708/include/mach/platform.h
  86  create mode 100644 arch/arm/mach-bcm2708/include/mach/power.h
  87  create mode 100644 arch/arm/mach-bcm2708/include/mach/system.h
  88  create mode 100644 arch/arm/mach-bcm2708/include/mach/timex.h
  89  create mode 100644 arch/arm/mach-bcm2708/include/mach/uncompress.h
  90  create mode 100644 arch/arm/mach-bcm2708/include/mach/vc_mem.h
  91  create mode 100644 arch/arm/mach-bcm2708/include/mach/vcio.h
  92  create mode 100644 arch/arm/mach-bcm2708/include/mach/vmalloc.h
  93  create mode 100644 arch/arm/mach-bcm2708/power.c
  94  create mode 100644 arch/arm/mach-bcm2708/vc_mem.c
  95  create mode 100644 arch/arm/mach-bcm2708/vcio.c
  96  create mode 100644 drivers/mmc/host/sdhci-bcm2708.c
  97
  98 --- a/arch/arm/Kconfig
  99 +++ b/arch/arm/Kconfig
 100 @@ -361,6 +361,21 @@ config ARCH_AT91
 101           This enables support for systems based on Atmel
 102           AT91RM9200 and AT91SAM9* processors.
 103
 104 +config ARCH_BCM2708
 105 +       bool "Broadcom BCM2708 family"
 106 +       select CPU_V6
 107 +       select ARM_AMBA
 108 +       select HAVE_CLK
 109 +       select HAVE_SCHED_CLOCK
 110 +       select NEED_MACH_MEMORY_H
 111 +       select CLKDEV_LOOKUP
 112 +       select GENERIC_CLOCKEVENTS
 113 +       select ARM_ERRATA_411920
 114 +       select MACH_BCM2708
 115 +       select VC4
 116 +       help
 117 +         This enables support for Broadcom BCM2708 boards.
 118 +
 119  config ARCH_CLPS711X
 120         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 121         select ARCH_REQUIRE_GPIOLIB
 122 @@ -1025,6 +1040,7 @@ source "arch/arm/mach-virt/Kconfig"
 123  source "arch/arm/mach-vt8500/Kconfig"
 124
 125  source "arch/arm/mach-w90x900/Kconfig"
 126 +source "arch/arm/mach-bcm2708/Kconfig"
 127
 128  source "arch/arm/mach-zynq/Kconfig"
 129
 130 --- a/arch/arm/Kconfig.debug
 131 +++ b/arch/arm/Kconfig.debug
 132 @@ -519,6 +519,14 @@ choice
 133                   For more details about semihosting, please see
 134                   chapter 8 of DUI0203I_rvct_developer_guide.pdf from ARM Ltd.
 135
 136 +       config DEBUG_BCM2708_UART0
 137 +               bool "Broadcom BCM2708 UART0 (PL011)"
 138 +               depends on MACH_BCM2708
 139 +               help
 140 +                 Say Y here if you want the debug print routines to direct
 141 +                 their output to UART 0. The port must have been initialised
 142 +                 by the boot-loader before use.
 143 +
 144  endchoice
 145
 146  config DEBUG_EXYNOS_UART
 147 --- a/arch/arm/Makefile
 148 +++ b/arch/arm/Makefile
 149 @@ -144,6 +144,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x0020
 150  # by CONFIG_* macro name.
 151  machine-$(CONFIG_ARCH_AT91)            += at91
 152  machine-$(CONFIG_ARCH_BCM)             += bcm
 153 +machine-$(CONFIG_ARCH_BCM2708)         += bcm2708
 154  machine-$(CONFIG_ARCH_BCM2835)         += bcm2835
 155  machine-$(CONFIG_ARCH_CLPS711X)                += clps711x
 156  machine-$(CONFIG_ARCH_CNS3XXX)         += cns3xxx
 157 --- /dev/null
 158 +++ b/arch/arm/configs/bcmrpi_cutdown_defconfig
 159 @@ -0,0 +1,474 @@
 160 +CONFIG_EXPERIMENTAL=y
 161 +# CONFIG_LOCALVERSION_AUTO is not set
 162 +CONFIG_SYSVIPC=y
 163 +CONFIG_POSIX_MQUEUE=y
 164 +CONFIG_IKCONFIG=y
 165 +CONFIG_IKCONFIG_PROC=y
 166 +# CONFIG_UID16 is not set
 167 +# CONFIG_KALLSYMS is not set
 168 +CONFIG_EMBEDDED=y
 169 +# CONFIG_VM_EVENT_COUNTERS is not set
 170 +# CONFIG_COMPAT_BRK is not set
 171 +CONFIG_SLAB=y
 172 +CONFIG_MODULES=y
 173 +CONFIG_MODULE_UNLOAD=y
 174 +CONFIG_MODVERSIONS=y
 175 +CONFIG_MODULE_SRCVERSION_ALL=y
 176 +# CONFIG_BLK_DEV_BSG is not set
 177 +CONFIG_ARCH_BCM2708=y
 178 +CONFIG_NO_HZ=y
 179 +CONFIG_HIGH_RES_TIMERS=y
 180 +CONFIG_AEABI=y
 181 +CONFIG_ZBOOT_ROM_TEXT=0x0
 182 +CONFIG_ZBOOT_ROM_BSS=0x0
 183 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
 184 +CONFIG_CPU_IDLE=y
 185 +CONFIG_VFP=y
 186 +CONFIG_BINFMT_MISC=m
 187 +CONFIG_NET=y
 188 +CONFIG_PACKET=y
 189 +CONFIG_UNIX=y
 190 +CONFIG_XFRM_USER=y
 191 +CONFIG_NET_KEY=m
 192 +CONFIG_INET=y
 193 +CONFIG_IP_MULTICAST=y
 194 +CONFIG_IP_PNP=y
 195 +CONFIG_IP_PNP_DHCP=y
 196 +CONFIG_IP_PNP_RARP=y
 197 +CONFIG_SYN_COOKIES=y
 198 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 199 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
 200 +# CONFIG_INET_XFRM_MODE_BEET is not set
 201 +# CONFIG_INET_LRO is not set
 202 +# CONFIG_INET_DIAG is not set
 203 +# CONFIG_IPV6 is not set
 204 +CONFIG_NET_PKTGEN=m
 205 +CONFIG_IRDA=m
 206 +CONFIG_IRLAN=m
 207 +CONFIG_IRCOMM=m
 208 +CONFIG_IRDA_ULTRA=y
 209 +CONFIG_IRDA_CACHE_LAST_LSAP=y
 210 +CONFIG_IRDA_FAST_RR=y
 211 +CONFIG_IRTTY_SIR=m
 212 +CONFIG_KINGSUN_DONGLE=m
 213 +CONFIG_KSDAZZLE_DONGLE=m
 214 +CONFIG_KS959_DONGLE=m
 215 +CONFIG_USB_IRDA=m
 216 +CONFIG_SIGMATEL_FIR=m
 217 +CONFIG_MCS_FIR=m
 218 +CONFIG_BT=m
 219 +CONFIG_BT_L2CAP=y
 220 +CONFIG_BT_SCO=y
 221 +CONFIG_BT_RFCOMM=m
 222 +CONFIG_BT_RFCOMM_TTY=y
 223 +CONFIG_BT_BNEP=m
 224 +CONFIG_BT_BNEP_MC_FILTER=y
 225 +CONFIG_BT_BNEP_PROTO_FILTER=y
 226 +CONFIG_BT_HIDP=m
 227 +CONFIG_BT_HCIBTUSB=m
 228 +CONFIG_BT_HCIBCM203X=m
 229 +CONFIG_BT_HCIBPA10X=m
 230 +CONFIG_BT_HCIBFUSB=m
 231 +CONFIG_BT_HCIVHCI=m
 232 +CONFIG_BT_MRVL=m
 233 +CONFIG_BT_MRVL_SDIO=m
 234 +CONFIG_BT_ATH3K=m
 235 +CONFIG_CFG80211=m
 236 +CONFIG_MAC80211=m
 237 +CONFIG_MAC80211_RC_PID=y
 238 +CONFIG_MAC80211_MESH=y
 239 +CONFIG_WIMAX=m
 240 +CONFIG_NET_9P=m
 241 +CONFIG_NFC=m
 242 +CONFIG_NFC_PN533=m
 243 +CONFIG_DEVTMPFS=y
 244 +CONFIG_BLK_DEV_LOOP=y
 245 +CONFIG_BLK_DEV_CRYPTOLOOP=m
 246 +CONFIG_BLK_DEV_NBD=m
 247 +CONFIG_BLK_DEV_RAM=y
 248 +CONFIG_CDROM_PKTCDVD=m
 249 +CONFIG_MISC_DEVICES=y
 250 +CONFIG_SCSI=y
 251 +# CONFIG_SCSI_PROC_FS is not set
 252 +CONFIG_BLK_DEV_SD=m
 253 +CONFIG_BLK_DEV_SR=m
 254 +CONFIG_SCSI_MULTI_LUN=y
 255 +# CONFIG_SCSI_LOWLEVEL is not set
 256 +CONFIG_NETDEVICES=y
 257 +CONFIG_TUN=m
 258 +CONFIG_PHYLIB=m
 259 +CONFIG_MDIO_BITBANG=m
 260 +CONFIG_NET_ETHERNET=y
 261 +# CONFIG_NETDEV_1000 is not set
 262 +# CONFIG_NETDEV_10000 is not set
 263 +CONFIG_LIBERTAS_THINFIRM=m
 264 +CONFIG_LIBERTAS_THINFIRM_USB=m
 265 +CONFIG_AT76C50X_USB=m
 266 +CONFIG_USB_ZD1201=m
 267 +CONFIG_USB_NET_RNDIS_WLAN=m
 268 +CONFIG_RTL8187=m
 269 +CONFIG_MAC80211_HWSIM=m
 270 +CONFIG_ATH_COMMON=m
 271 +CONFIG_ATH9K=m
 272 +CONFIG_ATH9K_HTC=m
 273 +CONFIG_CARL9170=m
 274 +CONFIG_B43=m
 275 +CONFIG_B43LEGACY=m
 276 +CONFIG_HOSTAP=m
 277 +CONFIG_IWM=m
 278 +CONFIG_LIBERTAS=m
 279 +CONFIG_LIBERTAS_USB=m
 280 +CONFIG_LIBERTAS_SDIO=m
 281 +CONFIG_P54_COMMON=m
 282 +CONFIG_P54_USB=m
 283 +CONFIG_RT2X00=m
 284 +CONFIG_RT2500USB=m
 285 +CONFIG_RT73USB=m
 286 +CONFIG_RT2800USB=m
 287 +CONFIG_RT2800USB_RT53XX=y
 288 +CONFIG_RTL8192CU=m
 289 +CONFIG_WL1251=m
 290 +CONFIG_WL12XX_MENU=m
 291 +CONFIG_ZD1211RW=m
 292 +CONFIG_MWIFIEX=m
 293 +CONFIG_MWIFIEX_SDIO=m
 294 +CONFIG_WIMAX_I2400M_USB=m
 295 +CONFIG_USB_CATC=m
 296 +CONFIG_USB_KAWETH=m
 297 +CONFIG_USB_PEGASUS=m
 298 +CONFIG_USB_RTL8150=m
 299 +CONFIG_USB_USBNET=y
 300 +CONFIG_USB_NET_AX8817X=m
 301 +CONFIG_USB_NET_CDCETHER=m
 302 +CONFIG_USB_NET_CDC_EEM=m
 303 +CONFIG_USB_NET_DM9601=m
 304 +CONFIG_USB_NET_SMSC75XX=m
 305 +CONFIG_USB_NET_SMSC95XX=y
 306 +CONFIG_USB_NET_GL620A=m
 307 +CONFIG_USB_NET_NET1080=m
 308 +CONFIG_USB_NET_PLUSB=m
 309 +CONFIG_USB_NET_MCS7830=m
 310 +CONFIG_USB_NET_CDC_SUBSET=m
 311 +CONFIG_USB_ALI_M5632=y
 312 +CONFIG_USB_AN2720=y
 313 +CONFIG_USB_KC2190=y
 314 +# CONFIG_USB_NET_ZAURUS is not set
 315 +CONFIG_USB_NET_CX82310_ETH=m
 316 +CONFIG_USB_NET_KALMIA=m
 317 +CONFIG_USB_NET_INT51X1=m
 318 +CONFIG_USB_IPHETH=m
 319 +CONFIG_USB_SIERRA_NET=m
 320 +CONFIG_USB_VL600=m
 321 +CONFIG_PPP=m
 322 +CONFIG_PPP_ASYNC=m
 323 +CONFIG_PPP_SYNC_TTY=m
 324 +CONFIG_PPP_DEFLATE=m
 325 +CONFIG_PPP_BSDCOMP=m
 326 +CONFIG_SLIP=m
 327 +CONFIG_SLIP_COMPRESSED=y
 328 +CONFIG_NETCONSOLE=m
 329 +CONFIG_INPUT_POLLDEV=m
 330 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 331 +CONFIG_INPUT_JOYDEV=m
 332 +CONFIG_INPUT_EVDEV=m
 333 +# CONFIG_INPUT_KEYBOARD is not set
 334 +# CONFIG_INPUT_MOUSE is not set
 335 +CONFIG_INPUT_MISC=y
 336 +CONFIG_INPUT_AD714X=m
 337 +CONFIG_INPUT_ATI_REMOTE=m
 338 +CONFIG_INPUT_ATI_REMOTE2=m
 339 +CONFIG_INPUT_KEYSPAN_REMOTE=m
 340 +CONFIG_INPUT_POWERMATE=m
 341 +CONFIG_INPUT_YEALINK=m
 342 +CONFIG_INPUT_CM109=m
 343 +CONFIG_INPUT_UINPUT=m
 344 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
 345 +CONFIG_INPUT_ADXL34X=m
 346 +CONFIG_INPUT_CMA3000=m
 347 +CONFIG_SERIO=m
 348 +CONFIG_SERIO_RAW=m
 349 +CONFIG_GAMEPORT=m
 350 +CONFIG_GAMEPORT_NS558=m
 351 +CONFIG_GAMEPORT_L4=m
 352 +CONFIG_VT_HW_CONSOLE_BINDING=y
 353 +# CONFIG_LEGACY_PTYS is not set
 354 +# CONFIG_DEVKMEM is not set
 355 +CONFIG_SERIAL_AMBA_PL011=y
 356 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 357 +# CONFIG_HW_RANDOM is not set
 358 +CONFIG_RAW_DRIVER=y
 359 +CONFIG_GPIO_SYSFS=y
 360 +# CONFIG_HWMON is not set
 361 +CONFIG_WATCHDOG=y
 362 +CONFIG_BCM2708_WDT=m
 363 +# CONFIG_MFD_SUPPORT is not set
 364 +CONFIG_FB=y
 365 +CONFIG_FB_BCM2708=y
 366 +CONFIG_FRAMEBUFFER_CONSOLE=y
 367 +CONFIG_LOGO=y
 368 +# CONFIG_LOGO_LINUX_MONO is not set
 369 +# CONFIG_LOGO_LINUX_VGA16 is not set
 370 +CONFIG_HID_PID=y
 371 +CONFIG_USB_HIDDEV=y
 372 +CONFIG_HID_A4TECH=m
 373 +CONFIG_HID_ACRUX=m
 374 +CONFIG_HID_APPLE=m
 375 +CONFIG_HID_BELKIN=m
 376 +CONFIG_HID_CHERRY=m
 377 +CONFIG_HID_CHICONY=m
 378 +CONFIG_HID_CYPRESS=m
 379 +CONFIG_HID_DRAGONRISE=m
 380 +CONFIG_HID_EMS_FF=m
 381 +CONFIG_HID_ELECOM=m
 382 +CONFIG_HID_EZKEY=m
 383 +CONFIG_HID_HOLTEK=m
 384 +CONFIG_HID_KEYTOUCH=m
 385 +CONFIG_HID_KYE=m
 386 +CONFIG_HID_UCLOGIC=m
 387 +CONFIG_HID_WALTOP=m
 388 +CONFIG_HID_GYRATION=m
 389 +CONFIG_HID_TWINHAN=m
 390 +CONFIG_HID_KENSINGTON=m
 391 +CONFIG_HID_LCPOWER=m
 392 +CONFIG_HID_LOGITECH=m
 393 +CONFIG_HID_MAGICMOUSE=m
 394 +CONFIG_HID_MICROSOFT=m
 395 +CONFIG_HID_MONTEREY=m
 396 +CONFIG_HID_MULTITOUCH=m
 397 +CONFIG_HID_NTRIG=m
 398 +CONFIG_HID_ORTEK=m
 399 +CONFIG_HID_PANTHERLORD=m
 400 +CONFIG_HID_PETALYNX=m
 401 +CONFIG_HID_PICOLCD=m
 402 +CONFIG_HID_QUANTA=m
 403 +CONFIG_HID_ROCCAT=m
 404 +CONFIG_HID_SAMSUNG=m
 405 +CONFIG_HID_SONY=m
 406 +CONFIG_HID_SPEEDLINK=m
 407 +CONFIG_HID_SUNPLUS=m
 408 +CONFIG_HID_GREENASIA=m
 409 +CONFIG_HID_SMARTJOYPLUS=m
 410 +CONFIG_HID_TOPSEED=m
 411 +CONFIG_HID_THRUSTMASTER=m
 412 +CONFIG_HID_WACOM=m
 413 +CONFIG_HID_WIIMOTE=m
 414 +CONFIG_HID_ZEROPLUS=m
 415 +CONFIG_HID_ZYDACRON=m
 416 +CONFIG_USB=y
 417 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 418 +CONFIG_USB_MON=m
 419 +CONFIG_USB_DWCOTG=y
 420 +CONFIG_USB_STORAGE=y
 421 +CONFIG_USB_STORAGE_REALTEK=m
 422 +CONFIG_USB_STORAGE_DATAFAB=m
 423 +CONFIG_USB_STORAGE_FREECOM=m
 424 +CONFIG_USB_STORAGE_ISD200=m
 425 +CONFIG_USB_STORAGE_USBAT=m
 426 +CONFIG_USB_STORAGE_SDDR09=m
 427 +CONFIG_USB_STORAGE_SDDR55=m
 428 +CONFIG_USB_STORAGE_JUMPSHOT=m
 429 +CONFIG_USB_STORAGE_ALAUDA=m
 430 +CONFIG_USB_STORAGE_ONETOUCH=m
 431 +CONFIG_USB_STORAGE_KARMA=m
 432 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
 433 +CONFIG_USB_STORAGE_ENE_UB6250=m
 434 +CONFIG_USB_UAS=m
 435 +CONFIG_USB_LIBUSUAL=y
 436 +CONFIG_USB_MDC800=m
 437 +CONFIG_USB_MICROTEK=m
 438 +CONFIG_USB_SERIAL=m
 439 +CONFIG_USB_SERIAL_GENERIC=y
 440 +CONFIG_USB_SERIAL_AIRCABLE=m
 441 +CONFIG_USB_SERIAL_ARK3116=m
 442 +CONFIG_USB_SERIAL_BELKIN=m
 443 +CONFIG_USB_SERIAL_CH341=m
 444 +CONFIG_USB_SERIAL_WHITEHEAT=m
 445 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
 446 +CONFIG_USB_SERIAL_CP210X=m
 447 +CONFIG_USB_SERIAL_CYPRESS_M8=m
 448 +CONFIG_USB_SERIAL_EMPEG=m
 449 +CONFIG_USB_SERIAL_FTDI_SIO=m
 450 +CONFIG_USB_SERIAL_FUNSOFT=m
 451 +CONFIG_USB_SERIAL_VISOR=m
 452 +CONFIG_USB_SERIAL_IPAQ=m
 453 +CONFIG_USB_SERIAL_IR=m
 454 +CONFIG_USB_SERIAL_EDGEPORT=m
 455 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
 456 +CONFIG_USB_SERIAL_GARMIN=m
 457 +CONFIG_USB_SERIAL_IPW=m
 458 +CONFIG_USB_SERIAL_IUU=m
 459 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
 460 +CONFIG_USB_SERIAL_KEYSPAN=m
 461 +CONFIG_USB_SERIAL_KLSI=m
 462 +CONFIG_USB_SERIAL_KOBIL_SCT=m
 463 +CONFIG_USB_SERIAL_MCT_U232=m
 464 +CONFIG_USB_SERIAL_MOS7720=m
 465 +CONFIG_USB_SERIAL_MOS7840=m
 466 +CONFIG_USB_SERIAL_MOTOROLA=m
 467 +CONFIG_USB_SERIAL_NAVMAN=m
 468 +CONFIG_USB_SERIAL_PL2303=m
 469 +CONFIG_USB_SERIAL_OTI6858=m
 470 +CONFIG_USB_SERIAL_QCAUX=m
 471 +CONFIG_USB_SERIAL_QUALCOMM=m
 472 +CONFIG_USB_SERIAL_SPCP8X5=m
 473 +CONFIG_USB_SERIAL_HP4X=m
 474 +CONFIG_USB_SERIAL_SAFE=m
 475 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
 476 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
 477 +CONFIG_USB_SERIAL_SYMBOL=m
 478 +CONFIG_USB_SERIAL_TI=m
 479 +CONFIG_USB_SERIAL_CYBERJACK=m
 480 +CONFIG_USB_SERIAL_XIRCOM=m
 481 +CONFIG_USB_SERIAL_OPTION=m
 482 +CONFIG_USB_SERIAL_OMNINET=m
 483 +CONFIG_USB_SERIAL_OPTICON=m
 484 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
 485 +CONFIG_USB_SERIAL_ZIO=m
 486 +CONFIG_USB_SERIAL_SSU100=m
 487 +CONFIG_USB_SERIAL_DEBUG=m
 488 +CONFIG_USB_EMI62=m
 489 +CONFIG_USB_EMI26=m
 490 +CONFIG_USB_ADUTUX=m
 491 +CONFIG_USB_SEVSEG=m
 492 +CONFIG_USB_RIO500=m
 493 +CONFIG_USB_LEGOTOWER=m
 494 +CONFIG_USB_LCD=m
 495 +CONFIG_USB_LED=m
 496 +CONFIG_USB_CYPRESS_CY7C63=m
 497 +CONFIG_USB_CYTHERM=m
 498 +CONFIG_USB_IDMOUSE=m
 499 +CONFIG_USB_FTDI_ELAN=m
 500 +CONFIG_USB_APPLEDISPLAY=m
 501 +CONFIG_USB_LD=m
 502 +CONFIG_USB_TRANCEVIBRATOR=m
 503 +CONFIG_USB_IOWARRIOR=m
 504 +CONFIG_USB_TEST=m
 505 +CONFIG_USB_ISIGHTFW=m
 506 +CONFIG_USB_YUREX=m
 507 +CONFIG_MMC=y
 508 +CONFIG_MMC_SDHCI=y
 509 +CONFIG_MMC_SDHCI_PLTFM=y
 510 +CONFIG_MMC_SDHCI_BCM2708=y
 511 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
 512 +CONFIG_LEDS_GPIO=y
 513 +CONFIG_LEDS_TRIGGER_TIMER=m
 514 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
 515 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
 516 +CONFIG_UIO=m
 517 +CONFIG_UIO_PDRV=m
 518 +CONFIG_UIO_PDRV_GENIRQ=m
 519 +# CONFIG_IOMMU_SUPPORT is not set
 520 +CONFIG_EXT4_FS=y
 521 +CONFIG_EXT4_FS_POSIX_ACL=y
 522 +CONFIG_EXT4_FS_SECURITY=y
 523 +CONFIG_REISERFS_FS=m
 524 +CONFIG_REISERFS_FS_XATTR=y
 525 +CONFIG_REISERFS_FS_POSIX_ACL=y
 526 +CONFIG_REISERFS_FS_SECURITY=y
 527 +CONFIG_JFS_FS=m
 528 +CONFIG_JFS_POSIX_ACL=y
 529 +CONFIG_JFS_SECURITY=y
 530 +CONFIG_XFS_FS=m
 531 +CONFIG_XFS_QUOTA=y
 532 +CONFIG_XFS_POSIX_ACL=y
 533 +CONFIG_XFS_RT=y
 534 +CONFIG_GFS2_FS=m
 535 +CONFIG_OCFS2_FS=m
 536 +CONFIG_BTRFS_FS=m
 537 +CONFIG_BTRFS_FS_POSIX_ACL=y
 538 +CONFIG_NILFS2_FS=m
 539 +CONFIG_AUTOFS4_FS=y
 540 +CONFIG_FUSE_FS=m
 541 +CONFIG_CUSE=m
 542 +CONFIG_FSCACHE=y
 543 +CONFIG_CACHEFILES=y
 544 +CONFIG_ISO9660_FS=m
 545 +CONFIG_JOLIET=y
 546 +CONFIG_ZISOFS=y
 547 +CONFIG_UDF_FS=m
 548 +CONFIG_MSDOS_FS=y
 549 +CONFIG_VFAT_FS=y
 550 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 551 +CONFIG_NTFS_FS=m
 552 +CONFIG_TMPFS=y
 553 +CONFIG_TMPFS_POSIX_ACL=y
 554 +CONFIG_CONFIGFS_FS=y
 555 +CONFIG_SQUASHFS=m
 556 +CONFIG_SQUASHFS_XATTR=y
 557 +CONFIG_SQUASHFS_LZO=y
 558 +CONFIG_SQUASHFS_XZ=y
 559 +CONFIG_NFS_FS=y
 560 +CONFIG_NFS_V3=y
 561 +CONFIG_NFS_V3_ACL=y
 562 +CONFIG_NFS_V4=y
 563 +CONFIG_ROOT_NFS=y
 564 +CONFIG_NFS_FSCACHE=y
 565 +CONFIG_CIFS=m
 566 +CONFIG_CIFS_WEAK_PW_HASH=y
 567 +CONFIG_CIFS_XATTR=y
 568 +CONFIG_CIFS_POSIX=y
 569 +CONFIG_9P_FS=m
 570 +CONFIG_PARTITION_ADVANCED=y
 571 +CONFIG_MAC_PARTITION=y
 572 +CONFIG_EFI_PARTITION=y
 573 +CONFIG_NLS_DEFAULT="utf8"
 574 +CONFIG_NLS_CODEPAGE_437=y
 575 +CONFIG_NLS_CODEPAGE_737=m
 576 +CONFIG_NLS_CODEPAGE_775=m
 577 +CONFIG_NLS_CODEPAGE_850=m
 578 +CONFIG_NLS_CODEPAGE_852=m
 579 +CONFIG_NLS_CODEPAGE_855=m
 580 +CONFIG_NLS_CODEPAGE_857=m
 581 +CONFIG_NLS_CODEPAGE_860=m
 582 +CONFIG_NLS_CODEPAGE_861=m
 583 +CONFIG_NLS_CODEPAGE_862=m
 584 +CONFIG_NLS_CODEPAGE_863=m
 585 +CONFIG_NLS_CODEPAGE_864=m
 586 +CONFIG_NLS_CODEPAGE_865=m
 587 +CONFIG_NLS_CODEPAGE_866=m
 588 +CONFIG_NLS_CODEPAGE_869=m
 589 +CONFIG_NLS_CODEPAGE_936=m
 590 +CONFIG_NLS_CODEPAGE_950=m
 591 +CONFIG_NLS_CODEPAGE_932=m
 592 +CONFIG_NLS_CODEPAGE_949=m
 593 +CONFIG_NLS_CODEPAGE_874=m
 594 +CONFIG_NLS_ISO8859_8=m
 595 +CONFIG_NLS_CODEPAGE_1250=m
 596 +CONFIG_NLS_CODEPAGE_1251=m
 597 +CONFIG_NLS_ASCII=y
 598 +CONFIG_NLS_ISO8859_1=m
 599 +CONFIG_NLS_ISO8859_2=m
 600 +CONFIG_NLS_ISO8859_3=m
 601 +CONFIG_NLS_ISO8859_4=m
 602 +CONFIG_NLS_ISO8859_5=m
 603 +CONFIG_NLS_ISO8859_6=m
 604 +CONFIG_NLS_ISO8859_7=m
 605 +CONFIG_NLS_ISO8859_9=m
 606 +CONFIG_NLS_ISO8859_13=m
 607 +CONFIG_NLS_ISO8859_14=m
 608 +CONFIG_NLS_ISO8859_15=m
 609 +CONFIG_NLS_KOI8_R=m
 610 +CONFIG_NLS_KOI8_U=m
 611 +CONFIG_NLS_UTF8=m
 612 +# CONFIG_SCHED_DEBUG is not set
 613 +# CONFIG_DEBUG_BUGVERBOSE is not set
 614 +# CONFIG_FTRACE is not set
 615 +# CONFIG_ARM_UNWIND is not set
 616 +CONFIG_CRYPTO_AUTHENC=m
 617 +CONFIG_CRYPTO_SEQIV=m
 618 +CONFIG_CRYPTO_CBC=y
 619 +CONFIG_CRYPTO_HMAC=y
 620 +CONFIG_CRYPTO_XCBC=m
 621 +CONFIG_CRYPTO_MD5=y
 622 +CONFIG_CRYPTO_SHA1=y
 623 +CONFIG_CRYPTO_SHA256=m
 624 +CONFIG_CRYPTO_SHA512=m
 625 +CONFIG_CRYPTO_TGR192=m
 626 +CONFIG_CRYPTO_WP512=m
 627 +CONFIG_CRYPTO_CAST5=m
 628 +CONFIG_CRYPTO_DES=y
 629 +CONFIG_CRYPTO_DEFLATE=m
 630 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
 631 +# CONFIG_CRYPTO_HW is not set
 632 +CONFIG_CRC_ITU_T=y
 633 +CONFIG_LIBCRC32C=y
 634 --- /dev/null
 635 +++ b/arch/arm/configs/bcmrpi_defconfig
 636 @@ -0,0 +1,510 @@
 637 +CONFIG_EXPERIMENTAL=y
 638 +# CONFIG_LOCALVERSION_AUTO is not set
 639 +CONFIG_SYSVIPC=y
 640 +CONFIG_POSIX_MQUEUE=y
 641 +CONFIG_BSD_PROCESS_ACCT=y
 642 +CONFIG_BSD_PROCESS_ACCT_V3=y
 643 +CONFIG_FHANDLE=y
 644 +CONFIG_AUDIT=y
 645 +CONFIG_IKCONFIG=y
 646 +CONFIG_IKCONFIG_PROC=y
 647 +CONFIG_CGROUP_FREEZER=y
 648 +CONFIG_CGROUP_DEVICE=y
 649 +CONFIG_CGROUP_CPUACCT=y
 650 +CONFIG_RESOURCE_COUNTERS=y
 651 +CONFIG_BLK_CGROUP=y
 652 +CONFIG_NAMESPACES=y
 653 +CONFIG_SCHED_AUTOGROUP=y
 654 +CONFIG_EMBEDDED=y
 655 +# CONFIG_COMPAT_BRK is not set
 656 +CONFIG_SLAB=y
 657 +CONFIG_PROFILING=y
 658 +CONFIG_OPROFILE=m
 659 +CONFIG_KPROBES=y
 660 +CONFIG_MODULES=y
 661 +CONFIG_MODULE_UNLOAD=y
 662 +CONFIG_MODVERSIONS=y
 663 +CONFIG_MODULE_SRCVERSION_ALL=y
 664 +# CONFIG_BLK_DEV_BSG is not set
 665 +CONFIG_BLK_DEV_THROTTLING=y
 666 +CONFIG_CFQ_GROUP_IOSCHED=y
 667 +CONFIG_ARCH_BCM2708=y
 668 +CONFIG_NO_HZ=y
 669 +CONFIG_HIGH_RES_TIMERS=y
 670 +CONFIG_AEABI=y
 671 +CONFIG_SECCOMP=y
 672 +CONFIG_CC_STACKPROTECTOR=y
 673 +CONFIG_ZBOOT_ROM_TEXT=0x0
 674 +CONFIG_ZBOOT_ROM_BSS=0x0
 675 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
 676 +CONFIG_KEXEC=y
 677 +CONFIG_CPU_IDLE=y
 678 +CONFIG_VFP=y
 679 +CONFIG_BINFMT_MISC=m
 680 +CONFIG_NET=y
 681 +CONFIG_PACKET=y
 682 +CONFIG_UNIX=y
 683 +CONFIG_XFRM_USER=y
 684 +CONFIG_NET_KEY=m
 685 +CONFIG_INET=y
 686 +CONFIG_IP_MULTICAST=y
 687 +CONFIG_IP_PNP=y
 688 +CONFIG_IP_PNP_DHCP=y
 689 +CONFIG_IP_PNP_RARP=y
 690 +CONFIG_SYN_COOKIES=y
 691 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 692 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
 693 +# CONFIG_INET_XFRM_MODE_BEET is not set
 694 +# CONFIG_INET_LRO is not set
 695 +# CONFIG_INET_DIAG is not set
 696 +# CONFIG_IPV6 is not set
 697 +CONFIG_NET_PKTGEN=m
 698 +CONFIG_IRDA=m
 699 +CONFIG_IRLAN=m
 700 +CONFIG_IRCOMM=m
 701 +CONFIG_IRDA_ULTRA=y
 702 +CONFIG_IRDA_CACHE_LAST_LSAP=y
 703 +CONFIG_IRDA_FAST_RR=y
 704 +CONFIG_IRTTY_SIR=m
 705 +CONFIG_KINGSUN_DONGLE=m
 706 +CONFIG_KSDAZZLE_DONGLE=m
 707 +CONFIG_KS959_DONGLE=m
 708 +CONFIG_USB_IRDA=m
 709 +CONFIG_SIGMATEL_FIR=m
 710 +CONFIG_MCS_FIR=m
 711 +CONFIG_BT=m
 712 +CONFIG_BT_L2CAP=y
 713 +CONFIG_BT_SCO=y
 714 +CONFIG_BT_RFCOMM=m
 715 +CONFIG_BT_RFCOMM_TTY=y
 716 +CONFIG_BT_BNEP=m
 717 +CONFIG_BT_BNEP_MC_FILTER=y
 718 +CONFIG_BT_BNEP_PROTO_FILTER=y
 719 +CONFIG_BT_HIDP=m
 720 +CONFIG_BT_HCIBTUSB=m
 721 +CONFIG_BT_HCIBCM203X=m
 722 +CONFIG_BT_HCIBPA10X=m
 723 +CONFIG_BT_HCIBFUSB=m
 724 +CONFIG_BT_HCIVHCI=m
 725 +CONFIG_BT_MRVL=m
 726 +CONFIG_BT_MRVL_SDIO=m
 727 +CONFIG_BT_ATH3K=m
 728 +CONFIG_CFG80211=m
 729 +CONFIG_MAC80211=m
 730 +CONFIG_MAC80211_RC_PID=y
 731 +CONFIG_MAC80211_MESH=y
 732 +CONFIG_WIMAX=m
 733 +CONFIG_NET_9P=m
 734 +CONFIG_NFC=m
 735 +CONFIG_NFC_PN533=m
 736 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 737 +CONFIG_BLK_DEV_LOOP=y
 738 +CONFIG_BLK_DEV_CRYPTOLOOP=m
 739 +CONFIG_BLK_DEV_NBD=m
 740 +CONFIG_BLK_DEV_RAM=y
 741 +CONFIG_CDROM_PKTCDVD=m
 742 +CONFIG_MISC_DEVICES=y
 743 +CONFIG_SCSI=y
 744 +# CONFIG_SCSI_PROC_FS is not set
 745 +CONFIG_BLK_DEV_SD=m
 746 +CONFIG_BLK_DEV_SR=m
 747 +CONFIG_SCSI_MULTI_LUN=y
 748 +# CONFIG_SCSI_LOWLEVEL is not set
 749 +CONFIG_MD=y
 750 +CONFIG_NETDEVICES=y
 751 +CONFIG_TUN=m
 752 +CONFIG_PHYLIB=m
 753 +CONFIG_MDIO_BITBANG=m
 754 +CONFIG_NET_ETHERNET=y
 755 +# CONFIG_NETDEV_1000 is not set
 756 +# CONFIG_NETDEV_10000 is not set
 757 +CONFIG_LIBERTAS_THINFIRM=m
 758 +CONFIG_LIBERTAS_THINFIRM_USB=m
 759 +CONFIG_AT76C50X_USB=m
 760 +CONFIG_USB_ZD1201=m
 761 +CONFIG_USB_NET_RNDIS_WLAN=m
 762 +CONFIG_RTL8187=m
 763 +CONFIG_MAC80211_HWSIM=m
 764 +CONFIG_ATH_COMMON=m
 765 +CONFIG_ATH9K=m
 766 +CONFIG_ATH9K_HTC=m
 767 +CONFIG_CARL9170=m
 768 +CONFIG_B43=m
 769 +CONFIG_B43LEGACY=m
 770 +CONFIG_HOSTAP=m
 771 +CONFIG_IWM=m
 772 +CONFIG_LIBERTAS=m
 773 +CONFIG_LIBERTAS_USB=m
 774 +CONFIG_LIBERTAS_SDIO=m
 775 +CONFIG_P54_COMMON=m
 776 +CONFIG_P54_USB=m
 777 +CONFIG_RT2X00=m
 778 +CONFIG_RT2500USB=m
 779 +CONFIG_RT73USB=m
 780 +CONFIG_RT2800USB=m
 781 +CONFIG_RT2800USB_RT53XX=y
 782 +CONFIG_RTL8192CU=m
 783 +CONFIG_WL1251=m
 784 +CONFIG_WL12XX_MENU=m
 785 +CONFIG_ZD1211RW=m
 786 +CONFIG_MWIFIEX=m
 787 +CONFIG_MWIFIEX_SDIO=m
 788 +CONFIG_WIMAX_I2400M_USB=m
 789 +CONFIG_USB_CATC=m
 790 +CONFIG_USB_KAWETH=m
 791 +CONFIG_USB_PEGASUS=m
 792 +CONFIG_USB_RTL8150=m
 793 +CONFIG_USB_USBNET=y
 794 +CONFIG_USB_NET_AX8817X=m
 795 +CONFIG_USB_NET_CDCETHER=m
 796 +CONFIG_USB_NET_CDC_EEM=m
 797 +CONFIG_USB_NET_DM9601=m
 798 +CONFIG_USB_NET_SMSC75XX=m
 799 +CONFIG_USB_NET_SMSC95XX=y
 800 +CONFIG_USB_NET_GL620A=m
 801 +CONFIG_USB_NET_NET1080=m
 802 +CONFIG_USB_NET_PLUSB=m
 803 +CONFIG_USB_NET_MCS7830=m
 804 +CONFIG_USB_NET_CDC_SUBSET=m
 805 +CONFIG_USB_ALI_M5632=y
 806 +CONFIG_USB_AN2720=y
 807 +CONFIG_USB_KC2190=y
 808 +# CONFIG_USB_NET_ZAURUS is not set
 809 +CONFIG_USB_NET_CX82310_ETH=m
 810 +CONFIG_USB_NET_KALMIA=m
 811 +CONFIG_USB_NET_INT51X1=m
 812 +CONFIG_USB_IPHETH=m
 813 +CONFIG_USB_SIERRA_NET=m
 814 +CONFIG_USB_VL600=m
 815 +CONFIG_PPP=m
 816 +CONFIG_PPP_ASYNC=m
 817 +CONFIG_PPP_SYNC_TTY=m
 818 +CONFIG_PPP_DEFLATE=m
 819 +CONFIG_PPP_BSDCOMP=m
 820 +CONFIG_SLIP=m
 821 +CONFIG_SLIP_COMPRESSED=y
 822 +CONFIG_NETCONSOLE=m
 823 +CONFIG_INPUT_POLLDEV=m
 824 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 825 +CONFIG_INPUT_JOYDEV=m
 826 +CONFIG_INPUT_EVDEV=m
 827 +# CONFIG_INPUT_KEYBOARD is not set
 828 +# CONFIG_INPUT_MOUSE is not set
 829 +CONFIG_INPUT_MISC=y
 830 +CONFIG_INPUT_AD714X=m
 831 +CONFIG_INPUT_ATI_REMOTE=m
 832 +CONFIG_INPUT_ATI_REMOTE2=m
 833 +CONFIG_INPUT_KEYSPAN_REMOTE=m
 834 +CONFIG_INPUT_POWERMATE=m
 835 +CONFIG_INPUT_YEALINK=m
 836 +CONFIG_INPUT_CM109=m
 837 +CONFIG_INPUT_UINPUT=m
 838 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
 839 +CONFIG_INPUT_ADXL34X=m
 840 +CONFIG_INPUT_CMA3000=m
 841 +CONFIG_SERIO=m
 842 +CONFIG_SERIO_RAW=m
 843 +CONFIG_GAMEPORT=m
 844 +CONFIG_GAMEPORT_NS558=m
 845 +CONFIG_GAMEPORT_L4=m
 846 +CONFIG_VT_HW_CONSOLE_BINDING=y
 847 +# CONFIG_LEGACY_PTYS is not set
 848 +# CONFIG_DEVKMEM is not set
 849 +CONFIG_SERIAL_AMBA_PL011=y
 850 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 851 +# CONFIG_HW_RANDOM is not set
 852 +CONFIG_RAW_DRIVER=y
 853 +CONFIG_GPIO_SYSFS=y
 854 +# CONFIG_HWMON is not set
 855 +CONFIG_WATCHDOG=y
 856 +CONFIG_BCM2708_WDT=m
 857 +# CONFIG_MFD_SUPPORT is not set
 858 +CONFIG_FB=y
 859 +CONFIG_FB_BCM2708=y
 860 +CONFIG_FRAMEBUFFER_CONSOLE=y
 861 +CONFIG_LOGO=y
 862 +# CONFIG_LOGO_LINUX_MONO is not set
 863 +# CONFIG_LOGO_LINUX_VGA16 is not set
 864 +CONFIG_HID_PID=y
 865 +CONFIG_USB_HIDDEV=y
 866 +CONFIG_HID_A4TECH=m
 867 +CONFIG_HID_ACRUX=m
 868 +CONFIG_HID_APPLE=m
 869 +CONFIG_HID_BELKIN=m
 870 +CONFIG_HID_CHERRY=m
 871 +CONFIG_HID_CHICONY=m
 872 +CONFIG_HID_CYPRESS=m
 873 +CONFIG_HID_DRAGONRISE=m
 874 +CONFIG_HID_EMS_FF=m
 875 +CONFIG_HID_ELECOM=m
 876 +CONFIG_HID_EZKEY=m
 877 +CONFIG_HID_HOLTEK=m
 878 +CONFIG_HID_KEYTOUCH=m
 879 +CONFIG_HID_KYE=m
 880 +CONFIG_HID_UCLOGIC=m
 881 +CONFIG_HID_WALTOP=m
 882 +CONFIG_HID_GYRATION=m
 883 +CONFIG_HID_TWINHAN=m
 884 +CONFIG_HID_KENSINGTON=m
 885 +CONFIG_HID_LCPOWER=m
 886 +CONFIG_HID_LOGITECH=m
 887 +CONFIG_HID_MAGICMOUSE=m
 888 +CONFIG_HID_MICROSOFT=m
 889 +CONFIG_HID_MONTEREY=m
 890 +CONFIG_HID_MULTITOUCH=m
 891 +CONFIG_HID_NTRIG=m
 892 +CONFIG_HID_ORTEK=m
 893 +CONFIG_HID_PANTHERLORD=m
 894 +CONFIG_HID_PETALYNX=m
 895 +CONFIG_HID_PICOLCD=m
 896 +CONFIG_HID_QUANTA=m
 897 +CONFIG_HID_ROCCAT=m
 898 +CONFIG_HID_SAMSUNG=m
 899 +CONFIG_HID_SONY=m
 900 +CONFIG_HID_SPEEDLINK=m
 901 +CONFIG_HID_SUNPLUS=m
 902 +CONFIG_HID_GREENASIA=m
 903 +CONFIG_HID_SMARTJOYPLUS=m
 904 +CONFIG_HID_TOPSEED=m
 905 +CONFIG_HID_THRUSTMASTER=m
 906 +CONFIG_HID_WACOM=m
 907 +CONFIG_HID_WIIMOTE=m
 908 +CONFIG_HID_ZEROPLUS=m
 909 +CONFIG_HID_ZYDACRON=m
 910 +CONFIG_USB=y
 911 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 912 +CONFIG_USB_MON=m
 913 +CONFIG_USB_DWCOTG=y
 914 +CONFIG_USB_STORAGE=y
 915 +CONFIG_USB_STORAGE_REALTEK=m
 916 +CONFIG_USB_STORAGE_DATAFAB=m
 917 +CONFIG_USB_STORAGE_FREECOM=m
 918 +CONFIG_USB_STORAGE_ISD200=m
 919 +CONFIG_USB_STORAGE_USBAT=m
 920 +CONFIG_USB_STORAGE_SDDR09=m
 921 +CONFIG_USB_STORAGE_SDDR55=m
 922 +CONFIG_USB_STORAGE_JUMPSHOT=m
 923 +CONFIG_USB_STORAGE_ALAUDA=m
 924 +CONFIG_USB_STORAGE_ONETOUCH=m
 925 +CONFIG_USB_STORAGE_KARMA=m
 926 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
 927 +CONFIG_USB_STORAGE_ENE_UB6250=m
 928 +CONFIG_USB_UAS=m
 929 +CONFIG_USB_LIBUSUAL=y
 930 +CONFIG_USB_MDC800=m
 931 +CONFIG_USB_MICROTEK=m
 932 +CONFIG_USB_SERIAL=m
 933 +CONFIG_USB_SERIAL_GENERIC=y
 934 +CONFIG_USB_SERIAL_AIRCABLE=m
 935 +CONFIG_USB_SERIAL_ARK3116=m
 936 +CONFIG_USB_SERIAL_BELKIN=m
 937 +CONFIG_USB_SERIAL_CH341=m
 938 +CONFIG_USB_SERIAL_WHITEHEAT=m
 939 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
 940 +CONFIG_USB_SERIAL_CP210X=m
 941 +CONFIG_USB_SERIAL_CYPRESS_M8=m
 942 +CONFIG_USB_SERIAL_EMPEG=m
 943 +CONFIG_USB_SERIAL_FTDI_SIO=m
 944 +CONFIG_USB_SERIAL_FUNSOFT=m
 945 +CONFIG_USB_SERIAL_VISOR=m
 946 +CONFIG_USB_SERIAL_IPAQ=m
 947 +CONFIG_USB_SERIAL_IR=m
 948 +CONFIG_USB_SERIAL_EDGEPORT=m
 949 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
 950 +CONFIG_USB_SERIAL_GARMIN=m
 951 +CONFIG_USB_SERIAL_IPW=m
 952 +CONFIG_USB_SERIAL_IUU=m
 953 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
 954 +CONFIG_USB_SERIAL_KEYSPAN=m
 955 +CONFIG_USB_SERIAL_KLSI=m
 956 +CONFIG_USB_SERIAL_KOBIL_SCT=m
 957 +CONFIG_USB_SERIAL_MCT_U232=m
 958 +CONFIG_USB_SERIAL_MOS7720=m
 959 +CONFIG_USB_SERIAL_MOS7840=m
 960 +CONFIG_USB_SERIAL_MOTOROLA=m
 961 +CONFIG_USB_SERIAL_NAVMAN=m
 962 +CONFIG_USB_SERIAL_PL2303=m
 963 +CONFIG_USB_SERIAL_OTI6858=m
 964 +CONFIG_USB_SERIAL_QCAUX=m
 965 +CONFIG_USB_SERIAL_QUALCOMM=m
 966 +CONFIG_USB_SERIAL_SPCP8X5=m
 967 +CONFIG_USB_SERIAL_HP4X=m
 968 +CONFIG_USB_SERIAL_SAFE=m
 969 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
 970 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
 971 +CONFIG_USB_SERIAL_SYMBOL=m
 972 +CONFIG_USB_SERIAL_TI=m
 973 +CONFIG_USB_SERIAL_CYBERJACK=m
 974 +CONFIG_USB_SERIAL_XIRCOM=m
 975 +CONFIG_USB_SERIAL_OPTION=m
 976 +CONFIG_USB_SERIAL_OMNINET=m
 977 +CONFIG_USB_SERIAL_OPTICON=m
 978 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
 979 +CONFIG_USB_SERIAL_ZIO=m
 980 +CONFIG_USB_SERIAL_SSU100=m
 981 +CONFIG_USB_SERIAL_DEBUG=m
 982 +CONFIG_USB_EMI62=m
 983 +CONFIG_USB_EMI26=m
 984 +CONFIG_USB_ADUTUX=m
 985 +CONFIG_USB_SEVSEG=m
 986 +CONFIG_USB_RIO500=m
 987 +CONFIG_USB_LEGOTOWER=m
 988 +CONFIG_USB_LCD=m
 989 +CONFIG_USB_LED=m
 990 +CONFIG_USB_CYPRESS_CY7C63=m
 991 +CONFIG_USB_CYTHERM=m
 992 +CONFIG_USB_IDMOUSE=m
 993 +CONFIG_USB_FTDI_ELAN=m
 994 +CONFIG_USB_APPLEDISPLAY=m
 995 +CONFIG_USB_LD=m
 996 +CONFIG_USB_TRANCEVIBRATOR=m
 997 +CONFIG_USB_IOWARRIOR=m
 998 +CONFIG_USB_TEST=m
 999 +CONFIG_USB_ISIGHTFW=m
1000 +CONFIG_USB_YUREX=m
1001 +CONFIG_MMC=y
1002 +CONFIG_MMC_SDHCI=y
1003 +CONFIG_MMC_SDHCI_PLTFM=y
1004 +CONFIG_MMC_SDHCI_BCM2708=y
1005 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1006 +CONFIG_LEDS_GPIO=y
1007 +CONFIG_LEDS_TRIGGER_TIMER=m
1008 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1009 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
1010 +CONFIG_UIO=m
1011 +CONFIG_UIO_PDRV=m
1012 +CONFIG_UIO_PDRV_GENIRQ=m
1013 +# CONFIG_IOMMU_SUPPORT is not set
1014 +CONFIG_EXT4_FS=y
1015 +CONFIG_EXT4_FS_POSIX_ACL=y
1016 +CONFIG_EXT4_FS_SECURITY=y
1017 +CONFIG_REISERFS_FS=m
1018 +CONFIG_REISERFS_FS_XATTR=y
1019 +CONFIG_REISERFS_FS_POSIX_ACL=y
1020 +CONFIG_REISERFS_FS_SECURITY=y
1021 +CONFIG_JFS_FS=m
1022 +CONFIG_JFS_POSIX_ACL=y
1023 +CONFIG_JFS_SECURITY=y
1024 +CONFIG_JFS_STATISTICS=y
1025 +CONFIG_XFS_FS=m
1026 +CONFIG_XFS_QUOTA=y
1027 +CONFIG_XFS_POSIX_ACL=y
1028 +CONFIG_XFS_RT=y
1029 +CONFIG_GFS2_FS=m
1030 +CONFIG_OCFS2_FS=m
1031 +CONFIG_BTRFS_FS=m
1032 +CONFIG_BTRFS_FS_POSIX_ACL=y
1033 +CONFIG_NILFS2_FS=m
1034 +CONFIG_FANOTIFY=y
1035 +CONFIG_AUTOFS4_FS=y
1036 +CONFIG_FUSE_FS=m
1037 +CONFIG_CUSE=m
1038 +CONFIG_FSCACHE=y
1039 +CONFIG_FSCACHE_STATS=y
1040 +CONFIG_FSCACHE_HISTOGRAM=y
1041 +CONFIG_CACHEFILES=y
1042 +CONFIG_ISO9660_FS=m
1043 +CONFIG_JOLIET=y
1044 +CONFIG_ZISOFS=y
1045 +CONFIG_UDF_FS=m
1046 +CONFIG_MSDOS_FS=y
1047 +CONFIG_VFAT_FS=y
1048 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1049 +CONFIG_NTFS_FS=m
1050 +CONFIG_TMPFS=y
1051 +CONFIG_TMPFS_POSIX_ACL=y
1052 +CONFIG_CONFIGFS_FS=y
1053 +CONFIG_SQUASHFS=m
1054 +CONFIG_SQUASHFS_XATTR=y
1055 +CONFIG_SQUASHFS_LZO=y
1056 +CONFIG_SQUASHFS_XZ=y
1057 +CONFIG_NFS_FS=y
1058 +CONFIG_NFS_V3=y
1059 +CONFIG_NFS_V3_ACL=y
1060 +CONFIG_NFS_V4=y
1061 +CONFIG_ROOT_NFS=y
1062 +CONFIG_NFS_FSCACHE=y
1063 +CONFIG_CIFS=m
1064 +CONFIG_CIFS_WEAK_PW_HASH=y
1065 +CONFIG_CIFS_XATTR=y
1066 +CONFIG_CIFS_POSIX=y
1067 +CONFIG_9P_FS=m
1068 +CONFIG_9P_FS_POSIX_ACL=y
1069 +CONFIG_PARTITION_ADVANCED=y
1070 +CONFIG_MAC_PARTITION=y
1071 +CONFIG_EFI_PARTITION=y
1072 +CONFIG_NLS_DEFAULT="utf8"
1073 +CONFIG_NLS_CODEPAGE_437=y
1074 +CONFIG_NLS_CODEPAGE_737=m
1075 +CONFIG_NLS_CODEPAGE_775=m
1076 +CONFIG_NLS_CODEPAGE_850=m
1077 +CONFIG_NLS_CODEPAGE_852=m
1078 +CONFIG_NLS_CODEPAGE_855=m
1079 +CONFIG_NLS_CODEPAGE_857=m
1080 +CONFIG_NLS_CODEPAGE_860=m
1081 +CONFIG_NLS_CODEPAGE_861=m
1082 +CONFIG_NLS_CODEPAGE_862=m
1083 +CONFIG_NLS_CODEPAGE_863=m
1084 +CONFIG_NLS_CODEPAGE_864=m
1085 +CONFIG_NLS_CODEPAGE_865=m
1086 +CONFIG_NLS_CODEPAGE_866=m
1087 +CONFIG_NLS_CODEPAGE_869=m
1088 +CONFIG_NLS_CODEPAGE_936=m
1089 +CONFIG_NLS_CODEPAGE_950=m
1090 +CONFIG_NLS_CODEPAGE_932=m
1091 +CONFIG_NLS_CODEPAGE_949=m
1092 +CONFIG_NLS_CODEPAGE_874=m
1093 +CONFIG_NLS_ISO8859_8=m
1094 +CONFIG_NLS_CODEPAGE_1250=m
1095 +CONFIG_NLS_CODEPAGE_1251=m
1096 +CONFIG_NLS_ASCII=y
1097 +CONFIG_NLS_ISO8859_1=m
1098 +CONFIG_NLS_ISO8859_2=m
1099 +CONFIG_NLS_ISO8859_3=m
1100 +CONFIG_NLS_ISO8859_4=m
1101 +CONFIG_NLS_ISO8859_5=m
1102 +CONFIG_NLS_ISO8859_6=m
1103 +CONFIG_NLS_ISO8859_7=m
1104 +CONFIG_NLS_ISO8859_9=m
1105 +CONFIG_NLS_ISO8859_13=m
1106 +CONFIG_NLS_ISO8859_14=m
1107 +CONFIG_NLS_ISO8859_15=m
1108 +CONFIG_NLS_KOI8_R=m
1109 +CONFIG_NLS_KOI8_U=m
1110 +CONFIG_NLS_UTF8=m
1111 +CONFIG_PRINTK_TIME=y
1112 +CONFIG_DETECT_HUNG_TASK=y
1113 +CONFIG_TIMER_STATS=y
1114 +CONFIG_DEBUG_STACK_USAGE=y
1115 +CONFIG_DEBUG_INFO=y
1116 +CONFIG_DEBUG_MEMORY_INIT=y
1117 +CONFIG_BOOT_PRINTK_DELAY=y
1118 +CONFIG_LATENCYTOP=y
1119 +CONFIG_SYSCTL_SYSCALL_CHECK=y
1120 +CONFIG_IRQSOFF_TRACER=y
1121 +CONFIG_SCHED_TRACER=y
1122 +CONFIG_STACK_TRACER=y
1123 +CONFIG_BLK_DEV_IO_TRACE=y
1124 +CONFIG_FUNCTION_PROFILER=y
1125 +CONFIG_KGDB=y
1126 +CONFIG_KGDB_KDB=y
1127 +CONFIG_KDB_KEYBOARD=y
1128 +CONFIG_STRICT_DEVMEM=y
1129 +CONFIG_CRYPTO_AUTHENC=m
1130 +CONFIG_CRYPTO_SEQIV=m
1131 +CONFIG_CRYPTO_CBC=y
1132 +CONFIG_CRYPTO_HMAC=y
1133 +CONFIG_CRYPTO_XCBC=m
1134 +CONFIG_CRYPTO_MD5=y
1135 +CONFIG_CRYPTO_SHA1=y
1136 +CONFIG_CRYPTO_SHA256=m
1137 +CONFIG_CRYPTO_SHA512=m
1138 +CONFIG_CRYPTO_TGR192=m
1139 +CONFIG_CRYPTO_WP512=m
1140 +CONFIG_CRYPTO_CAST5=m
1141 +CONFIG_CRYPTO_DES=y
1142 +CONFIG_CRYPTO_DEFLATE=m
1143 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1144 +# CONFIG_CRYPTO_HW is not set
1145 +CONFIG_CRC_ITU_T=y
1146 +CONFIG_LIBCRC32C=y
1147 --- /dev/null
1148 +++ b/arch/arm/configs/bcmrpi_emergency_defconfig
1149 @@ -0,0 +1,532 @@
1150 +CONFIG_EXPERIMENTAL=y
1151 +# CONFIG_LOCALVERSION_AUTO is not set
1152 +CONFIG_SYSVIPC=y
1153 +CONFIG_POSIX_MQUEUE=y
1154 +CONFIG_BSD_PROCESS_ACCT=y
1155 +CONFIG_BSD_PROCESS_ACCT_V3=y
1156 +CONFIG_FHANDLE=y
1157 +CONFIG_AUDIT=y
1158 +CONFIG_IKCONFIG=y
1159 +CONFIG_IKCONFIG_PROC=y
1160 +CONFIG_BLK_DEV_INITRD=y
1161 +CONFIG_INITRAMFS_SOURCE="../target_fs"
1162 +CONFIG_CGROUP_FREEZER=y
1163 +CONFIG_CGROUP_DEVICE=y
1164 +CONFIG_CGROUP_CPUACCT=y
1165 +CONFIG_RESOURCE_COUNTERS=y
1166 +CONFIG_BLK_CGROUP=y
1167 +CONFIG_NAMESPACES=y
1168 +CONFIG_SCHED_AUTOGROUP=y
1169 +CONFIG_EMBEDDED=y
1170 +# CONFIG_COMPAT_BRK is not set
1171 +CONFIG_SLAB=y
1172 +CONFIG_PROFILING=y
1173 +CONFIG_OPROFILE=m
1174 +CONFIG_KPROBES=y
1175 +CONFIG_MODULES=y
1176 +CONFIG_MODULE_UNLOAD=y
1177 +CONFIG_MODVERSIONS=y
1178 +CONFIG_MODULE_SRCVERSION_ALL=y
1179 +# CONFIG_BLK_DEV_BSG is not set
1180 +CONFIG_BLK_DEV_THROTTLING=y
1181 +CONFIG_CFQ_GROUP_IOSCHED=y
1182 +CONFIG_ARCH_BCM2708=y
1183 +CONFIG_NO_HZ=y
1184 +CONFIG_HIGH_RES_TIMERS=y
1185 +CONFIG_AEABI=y
1186 +CONFIG_SECCOMP=y
1187 +CONFIG_CC_STACKPROTECTOR=y
1188 +CONFIG_ZBOOT_ROM_TEXT=0x0
1189 +CONFIG_ZBOOT_ROM_BSS=0x0
1190 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
1191 +CONFIG_KEXEC=y
1192 +CONFIG_CPU_IDLE=y
1193 +CONFIG_VFP=y
1194 +CONFIG_BINFMT_MISC=m
1195 +CONFIG_NET=y
1196 +CONFIG_PACKET=y
1197 +CONFIG_UNIX=y
1198 +CONFIG_XFRM_USER=y
1199 +CONFIG_NET_KEY=m
1200 +CONFIG_INET=y
1201 +CONFIG_IP_MULTICAST=y
1202 +CONFIG_IP_PNP=y
1203 +CONFIG_IP_PNP_DHCP=y
1204 +CONFIG_IP_PNP_RARP=y
1205 +CONFIG_SYN_COOKIES=y
1206 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
1207 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
1208 +# CONFIG_INET_XFRM_MODE_BEET is not set
1209 +# CONFIG_INET_LRO is not set
1210 +# CONFIG_INET_DIAG is not set
1211 +# CONFIG_IPV6 is not set
1212 +CONFIG_NET_PKTGEN=m
1213 +CONFIG_IRDA=m
1214 +CONFIG_IRLAN=m
1215 +CONFIG_IRCOMM=m
1216 +CONFIG_IRDA_ULTRA=y
1217 +CONFIG_IRDA_CACHE_LAST_LSAP=y
1218 +CONFIG_IRDA_FAST_RR=y
1219 +CONFIG_IRTTY_SIR=m
1220 +CONFIG_KINGSUN_DONGLE=m
1221 +CONFIG_KSDAZZLE_DONGLE=m
1222 +CONFIG_KS959_DONGLE=m
1223 +CONFIG_USB_IRDA=m
1224 +CONFIG_SIGMATEL_FIR=m
1225 +CONFIG_MCS_FIR=m
1226 +CONFIG_BT=m
1227 +CONFIG_BT_L2CAP=y
1228 +CONFIG_BT_SCO=y
1229 +CONFIG_BT_RFCOMM=m
1230 +CONFIG_BT_RFCOMM_TTY=y
1231 +CONFIG_BT_BNEP=m
1232 +CONFIG_BT_BNEP_MC_FILTER=y
1233 +CONFIG_BT_BNEP_PROTO_FILTER=y
1234 +CONFIG_BT_HIDP=m
1235 +CONFIG_BT_HCIBTUSB=m
1236 +CONFIG_BT_HCIBCM203X=m
1237 +CONFIG_BT_HCIBPA10X=m
1238 +CONFIG_BT_HCIBFUSB=m
1239 +CONFIG_BT_HCIVHCI=m
1240 +CONFIG_BT_MRVL=m
1241 +CONFIG_BT_MRVL_SDIO=m
1242 +CONFIG_BT_ATH3K=m
1243 +CONFIG_CFG80211=m
1244 +CONFIG_MAC80211=m
1245 +CONFIG_MAC80211_RC_PID=y
1246 +CONFIG_MAC80211_MESH=y
1247 +CONFIG_WIMAX=m
1248 +CONFIG_NET_9P=m
1249 +CONFIG_NFC=m
1250 +CONFIG_NFC_PN533=m
1251 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
1252 +CONFIG_BLK_DEV_LOOP=y
1253 +CONFIG_BLK_DEV_CRYPTOLOOP=m
1254 +CONFIG_BLK_DEV_NBD=m
1255 +CONFIG_BLK_DEV_RAM=y
1256 +CONFIG_CDROM_PKTCDVD=m
1257 +CONFIG_MISC_DEVICES=y
1258 +CONFIG_SCSI=y
1259 +# CONFIG_SCSI_PROC_FS is not set
1260 +CONFIG_BLK_DEV_SD=y
1261 +CONFIG_BLK_DEV_SR=m
1262 +CONFIG_SCSI_MULTI_LUN=y
1263 +# CONFIG_SCSI_LOWLEVEL is not set
1264 +CONFIG_MD=y
1265 +CONFIG_NETDEVICES=y
1266 +CONFIG_TUN=m
1267 +CONFIG_PHYLIB=m
1268 +CONFIG_MDIO_BITBANG=m
1269 +CONFIG_NET_ETHERNET=y
1270 +# CONFIG_NETDEV_1000 is not set
1271 +# CONFIG_NETDEV_10000 is not set
1272 +CONFIG_LIBERTAS_THINFIRM=m
1273 +CONFIG_LIBERTAS_THINFIRM_USB=m
1274 +CONFIG_AT76C50X_USB=m
1275 +CONFIG_USB_ZD1201=m
1276 +CONFIG_USB_NET_RNDIS_WLAN=m
1277 +CONFIG_RTL8187=m
1278 +CONFIG_MAC80211_HWSIM=m
1279 +CONFIG_ATH_COMMON=m
1280 +CONFIG_ATH9K=m
1281 +CONFIG_ATH9K_HTC=m
1282 +CONFIG_CARL9170=m
1283 +CONFIG_B43=m
1284 +CONFIG_B43LEGACY=m
1285 +CONFIG_HOSTAP=m
1286 +CONFIG_IWM=m
1287 +CONFIG_LIBERTAS=m
1288 +CONFIG_LIBERTAS_USB=m
1289 +CONFIG_LIBERTAS_SDIO=m
1290 +CONFIG_P54_COMMON=m
1291 +CONFIG_P54_USB=m
1292 +CONFIG_RT2X00=m
1293 +CONFIG_RT2500USB=m
1294 +CONFIG_RT73USB=m
1295 +CONFIG_RT2800USB=m
1296 +CONFIG_RT2800USB_RT53XX=y
1297 +CONFIG_RTL8192CU=m
1298 +CONFIG_WL1251=m
1299 +CONFIG_WL12XX_MENU=m
1300 +CONFIG_ZD1211RW=m
1301 +CONFIG_MWIFIEX=m
1302 +CONFIG_MWIFIEX_SDIO=m
1303 +CONFIG_WIMAX_I2400M_USB=m
1304 +CONFIG_USB_CATC=m
1305 +CONFIG_USB_KAWETH=m
1306 +CONFIG_USB_PEGASUS=m
1307 +CONFIG_USB_RTL8150=m
1308 +CONFIG_USB_USBNET=y
1309 +CONFIG_USB_NET_AX8817X=m
1310 +CONFIG_USB_NET_CDCETHER=m
1311 +CONFIG_USB_NET_CDC_EEM=m
1312 +CONFIG_USB_NET_DM9601=m
1313 +CONFIG_USB_NET_SMSC75XX=m
1314 +CONFIG_USB_NET_SMSC95XX=y
1315 +CONFIG_USB_NET_GL620A=m
1316 +CONFIG_USB_NET_NET1080=m
1317 +CONFIG_USB_NET_PLUSB=m
1318 +CONFIG_USB_NET_MCS7830=m
1319 +CONFIG_USB_NET_CDC_SUBSET=m
1320 +CONFIG_USB_ALI_M5632=y
1321 +CONFIG_USB_AN2720=y
1322 +CONFIG_USB_KC2190=y
1323 +# CONFIG_USB_NET_ZAURUS is not set
1324 +CONFIG_USB_NET_CX82310_ETH=m
1325 +CONFIG_USB_NET_KALMIA=m
1326 +CONFIG_USB_NET_INT51X1=m
1327 +CONFIG_USB_IPHETH=m
1328 +CONFIG_USB_SIERRA_NET=m
1329 +CONFIG_USB_VL600=m
1330 +CONFIG_PPP=m
1331 +CONFIG_PPP_ASYNC=m
1332 +CONFIG_PPP_SYNC_TTY=m
1333 +CONFIG_PPP_DEFLATE=m
1334 +CONFIG_PPP_BSDCOMP=m
1335 +CONFIG_SLIP=m
1336 +CONFIG_SLIP_COMPRESSED=y
1337 +CONFIG_NETCONSOLE=m
1338 +CONFIG_INPUT_POLLDEV=m
1339 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1340 +CONFIG_INPUT_JOYDEV=m
1341 +CONFIG_INPUT_EVDEV=m
1342 +# CONFIG_INPUT_KEYBOARD is not set
1343 +# CONFIG_INPUT_MOUSE is not set
1344 +CONFIG_INPUT_MISC=y
1345 +CONFIG_INPUT_AD714X=m
1346 +CONFIG_INPUT_ATI_REMOTE=m
1347 +CONFIG_INPUT_ATI_REMOTE2=m
1348 +CONFIG_INPUT_KEYSPAN_REMOTE=m
1349 +CONFIG_INPUT_POWERMATE=m
1350 +CONFIG_INPUT_YEALINK=m
1351 +CONFIG_INPUT_CM109=m
1352 +CONFIG_INPUT_UINPUT=m
1353 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
1354 +CONFIG_INPUT_ADXL34X=m
1355 +CONFIG_INPUT_CMA3000=m
1356 +CONFIG_SERIO=m
1357 +CONFIG_SERIO_RAW=m
1358 +CONFIG_GAMEPORT=m
1359 +CONFIG_GAMEPORT_NS558=m
1360 +CONFIG_GAMEPORT_L4=m
1361 +CONFIG_VT_HW_CONSOLE_BINDING=y
1362 +# CONFIG_LEGACY_PTYS is not set
1363 +# CONFIG_DEVKMEM is not set
1364 +CONFIG_SERIAL_AMBA_PL011=y
1365 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1366 +# CONFIG_HW_RANDOM is not set
1367 +CONFIG_RAW_DRIVER=y
1368 +CONFIG_GPIO_SYSFS=y
1369 +# CONFIG_HWMON is not set
1370 +CONFIG_WATCHDOG=y
1371 +CONFIG_BCM2708_WDT=m
1372 +# CONFIG_MFD_SUPPORT is not set
1373 +CONFIG_FB=y
1374 +CONFIG_FB_BCM2708=y
1375 +CONFIG_FRAMEBUFFER_CONSOLE=y
1376 +CONFIG_LOGO=y
1377 +# CONFIG_LOGO_LINUX_MONO is not set
1378 +# CONFIG_LOGO_LINUX_VGA16 is not set
1379 +CONFIG_SOUND=y
1380 +CONFIG_SND=m
1381 +CONFIG_SND_SEQUENCER=m
1382 +CONFIG_SND_SEQ_DUMMY=m
1383 +CONFIG_SND_MIXER_OSS=m
1384 +CONFIG_SND_PCM_OSS=m
1385 +CONFIG_SND_SEQUENCER_OSS=y
1386 +CONFIG_SND_HRTIMER=m
1387 +CONFIG_SND_DUMMY=m
1388 +CONFIG_SND_ALOOP=m
1389 +CONFIG_SND_VIRMIDI=m
1390 +CONFIG_SND_MTPAV=m
1391 +CONFIG_SND_SERIAL_U16550=m
1392 +CONFIG_SND_MPU401=m
1393 +CONFIG_SND_BCM2835=m
1394 +CONFIG_SND_USB_AUDIO=m
1395 +CONFIG_SND_USB_UA101=m
1396 +CONFIG_SND_USB_CAIAQ=m
1397 +CONFIG_SND_USB_6FIRE=m
1398 +CONFIG_SOUND_PRIME=m
1399 +CONFIG_HID_PID=y
1400 +CONFIG_USB_HIDDEV=y
1401 +CONFIG_HID_A4TECH=m
1402 +CONFIG_HID_ACRUX=m
1403 +CONFIG_HID_APPLE=m
1404 +CONFIG_HID_BELKIN=m
1405 +CONFIG_HID_CHERRY=m
1406 +CONFIG_HID_CHICONY=m
1407 +CONFIG_HID_CYPRESS=m
1408 +CONFIG_HID_DRAGONRISE=m
1409 +CONFIG_HID_EMS_FF=m
1410 +CONFIG_HID_ELECOM=m
1411 +CONFIG_HID_EZKEY=m
1412 +CONFIG_HID_HOLTEK=m
1413 +CONFIG_HID_KEYTOUCH=m
1414 +CONFIG_HID_KYE=m
1415 +CONFIG_HID_UCLOGIC=m
1416 +CONFIG_HID_WALTOP=m
1417 +CONFIG_HID_GYRATION=m
1418 +CONFIG_HID_TWINHAN=m
1419 +CONFIG_HID_KENSINGTON=m
1420 +CONFIG_HID_LCPOWER=m
1421 +CONFIG_HID_LOGITECH=m
1422 +CONFIG_HID_MAGICMOUSE=m
1423 +CONFIG_HID_MICROSOFT=m
1424 +CONFIG_HID_MONTEREY=m
1425 +CONFIG_HID_MULTITOUCH=m
1426 +CONFIG_HID_NTRIG=m
1427 +CONFIG_HID_ORTEK=m
1428 +CONFIG_HID_PANTHERLORD=m
1429 +CONFIG_HID_PETALYNX=m
1430 +CONFIG_HID_PICOLCD=m
1431 +CONFIG_HID_QUANTA=m
1432 +CONFIG_HID_ROCCAT=m
1433 +CONFIG_HID_SAMSUNG=m
1434 +CONFIG_HID_SONY=m
1435 +CONFIG_HID_SPEEDLINK=m
1436 +CONFIG_HID_SUNPLUS=m
1437 +CONFIG_HID_GREENASIA=m
1438 +CONFIG_HID_SMARTJOYPLUS=m
1439 +CONFIG_HID_TOPSEED=m
1440 +CONFIG_HID_THRUSTMASTER=m
1441 +CONFIG_HID_WACOM=m
1442 +CONFIG_HID_WIIMOTE=m
1443 +CONFIG_HID_ZEROPLUS=m
1444 +CONFIG_HID_ZYDACRON=m
1445 +CONFIG_USB=y
1446 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1447 +CONFIG_USB_MON=m
1448 +CONFIG_USB_DWCOTG=y
1449 +CONFIG_USB_STORAGE=y
1450 +CONFIG_USB_STORAGE_REALTEK=m
1451 +CONFIG_USB_STORAGE_DATAFAB=m
1452 +CONFIG_USB_STORAGE_FREECOM=m
1453 +CONFIG_USB_STORAGE_ISD200=m
1454 +CONFIG_USB_STORAGE_USBAT=m
1455 +CONFIG_USB_STORAGE_SDDR09=m
1456 +CONFIG_USB_STORAGE_SDDR55=m
1457 +CONFIG_USB_STORAGE_JUMPSHOT=m
1458 +CONFIG_USB_STORAGE_ALAUDA=m
1459 +CONFIG_USB_STORAGE_ONETOUCH=m
1460 +CONFIG_USB_STORAGE_KARMA=m
1461 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
1462 +CONFIG_USB_STORAGE_ENE_UB6250=m
1463 +CONFIG_USB_UAS=y
1464 +CONFIG_USB_LIBUSUAL=y
1465 +CONFIG_USB_MDC800=m
1466 +CONFIG_USB_MICROTEK=m
1467 +CONFIG_USB_SERIAL=m
1468 +CONFIG_USB_SERIAL_GENERIC=y
1469 +CONFIG_USB_SERIAL_AIRCABLE=m
1470 +CONFIG_USB_SERIAL_ARK3116=m
1471 +CONFIG_USB_SERIAL_BELKIN=m
1472 +CONFIG_USB_SERIAL_CH341=m
1473 +CONFIG_USB_SERIAL_WHITEHEAT=m
1474 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
1475 +CONFIG_USB_SERIAL_CP210X=m
1476 +CONFIG_USB_SERIAL_CYPRESS_M8=m
1477 +CONFIG_USB_SERIAL_EMPEG=m
1478 +CONFIG_USB_SERIAL_FTDI_SIO=m
1479 +CONFIG_USB_SERIAL_FUNSOFT=m
1480 +CONFIG_USB_SERIAL_VISOR=m
1481 +CONFIG_USB_SERIAL_IPAQ=m
1482 +CONFIG_USB_SERIAL_IR=m
1483 +CONFIG_USB_SERIAL_EDGEPORT=m
1484 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
1485 +CONFIG_USB_SERIAL_GARMIN=m
1486 +CONFIG_USB_SERIAL_IPW=m
1487 +CONFIG_USB_SERIAL_IUU=m
1488 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
1489 +CONFIG_USB_SERIAL_KEYSPAN=m
1490 +CONFIG_USB_SERIAL_KLSI=m
1491 +CONFIG_USB_SERIAL_KOBIL_SCT=m
1492 +CONFIG_USB_SERIAL_MCT_U232=m
1493 +CONFIG_USB_SERIAL_MOS7720=m
1494 +CONFIG_USB_SERIAL_MOS7840=m
1495 +CONFIG_USB_SERIAL_MOTOROLA=m
1496 +CONFIG_USB_SERIAL_NAVMAN=m
1497 +CONFIG_USB_SERIAL_PL2303=m
1498 +CONFIG_USB_SERIAL_OTI6858=m
1499 +CONFIG_USB_SERIAL_QCAUX=m
1500 +CONFIG_USB_SERIAL_QUALCOMM=m
1501 +CONFIG_USB_SERIAL_SPCP8X5=m
1502 +CONFIG_USB_SERIAL_HP4X=m
1503 +CONFIG_USB_SERIAL_SAFE=m
1504 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
1505 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
1506 +CONFIG_USB_SERIAL_SYMBOL=m
1507 +CONFIG_USB_SERIAL_TI=m
1508 +CONFIG_USB_SERIAL_CYBERJACK=m
1509 +CONFIG_USB_SERIAL_XIRCOM=m
1510 +CONFIG_USB_SERIAL_OPTION=m
1511 +CONFIG_USB_SERIAL_OMNINET=m
1512 +CONFIG_USB_SERIAL_OPTICON=m
1513 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
1514 +CONFIG_USB_SERIAL_ZIO=m
1515 +CONFIG_USB_SERIAL_SSU100=m
1516 +CONFIG_USB_SERIAL_DEBUG=m
1517 +CONFIG_USB_EMI62=m
1518 +CONFIG_USB_EMI26=m
1519 +CONFIG_USB_ADUTUX=m
1520 +CONFIG_USB_SEVSEG=m
1521 +CONFIG_USB_RIO500=m
1522 +CONFIG_USB_LEGOTOWER=m
1523 +CONFIG_USB_LCD=m
1524 +CONFIG_USB_LED=m
1525 +CONFIG_USB_CYPRESS_CY7C63=m
1526 +CONFIG_USB_CYTHERM=m
1527 +CONFIG_USB_IDMOUSE=m
1528 +CONFIG_USB_FTDI_ELAN=m
1529 +CONFIG_USB_APPLEDISPLAY=m
1530 +CONFIG_USB_LD=m
1531 +CONFIG_USB_TRANCEVIBRATOR=m
1532 +CONFIG_USB_IOWARRIOR=m
1533 +CONFIG_USB_TEST=m
1534 +CONFIG_USB_ISIGHTFW=m
1535 +CONFIG_USB_YUREX=m
1536 +CONFIG_MMC=y
1537 +CONFIG_MMC_SDHCI=y
1538 +CONFIG_MMC_SDHCI_PLTFM=y
1539 +CONFIG_MMC_SDHCI_BCM2708=y
1540 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1541 +CONFIG_LEDS_GPIO=y
1542 +CONFIG_LEDS_TRIGGER_TIMER=m
1543 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1544 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
1545 +CONFIG_UIO=m
1546 +CONFIG_UIO_PDRV=m
1547 +CONFIG_UIO_PDRV_GENIRQ=m
1548 +# CONFIG_IOMMU_SUPPORT is not set
1549 +CONFIG_EXT4_FS=y
1550 +CONFIG_EXT4_FS_POSIX_ACL=y
1551 +CONFIG_EXT4_FS_SECURITY=y
1552 +CONFIG_REISERFS_FS=m
1553 +CONFIG_REISERFS_FS_XATTR=y
1554 +CONFIG_REISERFS_FS_POSIX_ACL=y
1555 +CONFIG_REISERFS_FS_SECURITY=y
1556 +CONFIG_JFS_FS=m
1557 +CONFIG_JFS_POSIX_ACL=y
1558 +CONFIG_JFS_SECURITY=y
1559 +CONFIG_JFS_STATISTICS=y
1560 +CONFIG_XFS_FS=m
1561 +CONFIG_XFS_QUOTA=y
1562 +CONFIG_XFS_POSIX_ACL=y
1563 +CONFIG_XFS_RT=y
1564 +CONFIG_GFS2_FS=m
1565 +CONFIG_OCFS2_FS=m
1566 +CONFIG_BTRFS_FS=m
1567 +CONFIG_BTRFS_FS_POSIX_ACL=y
1568 +CONFIG_NILFS2_FS=m
1569 +CONFIG_FANOTIFY=y
1570 +CONFIG_AUTOFS4_FS=y
1571 +CONFIG_FUSE_FS=m
1572 +CONFIG_CUSE=m
1573 +CONFIG_FSCACHE=y
1574 +CONFIG_FSCACHE_STATS=y
1575 +CONFIG_FSCACHE_HISTOGRAM=y
1576 +CONFIG_CACHEFILES=y
1577 +CONFIG_ISO9660_FS=m
1578 +CONFIG_JOLIET=y
1579 +CONFIG_ZISOFS=y
1580 +CONFIG_UDF_FS=m
1581 +CONFIG_MSDOS_FS=y
1582 +CONFIG_VFAT_FS=y
1583 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1584 +CONFIG_NTFS_FS=m
1585 +CONFIG_TMPFS=y
1586 +CONFIG_TMPFS_POSIX_ACL=y
1587 +CONFIG_CONFIGFS_FS=y
1588 +CONFIG_SQUASHFS=m
1589 +CONFIG_SQUASHFS_XATTR=y
1590 +CONFIG_SQUASHFS_LZO=y
1591 +CONFIG_SQUASHFS_XZ=y
1592 +CONFIG_NFS_FS=y
1593 +CONFIG_NFS_V3=y
1594 +CONFIG_NFS_V3_ACL=y
1595 +CONFIG_NFS_V4=y
1596 +CONFIG_ROOT_NFS=y
1597 +CONFIG_NFS_FSCACHE=y
1598 +CONFIG_CIFS=m
1599 +CONFIG_CIFS_WEAK_PW_HASH=y
1600 +CONFIG_CIFS_XATTR=y
1601 +CONFIG_CIFS_POSIX=y
1602 +CONFIG_9P_FS=m
1603 +CONFIG_9P_FS_POSIX_ACL=y
1604 +CONFIG_PARTITION_ADVANCED=y
1605 +CONFIG_MAC_PARTITION=y
1606 +CONFIG_EFI_PARTITION=y
1607 +CONFIG_NLS_DEFAULT="utf8"
1608 +CONFIG_NLS_CODEPAGE_437=y
1609 +CONFIG_NLS_CODEPAGE_737=m
1610 +CONFIG_NLS_CODEPAGE_775=m
1611 +CONFIG_NLS_CODEPAGE_850=m
1612 +CONFIG_NLS_CODEPAGE_852=m
1613 +CONFIG_NLS_CODEPAGE_855=m
1614 +CONFIG_NLS_CODEPAGE_857=m
1615 +CONFIG_NLS_CODEPAGE_860=m
1616 +CONFIG_NLS_CODEPAGE_861=m
1617 +CONFIG_NLS_CODEPAGE_862=m
1618 +CONFIG_NLS_CODEPAGE_863=m
1619 +CONFIG_NLS_CODEPAGE_864=m
1620 +CONFIG_NLS_CODEPAGE_865=m
1621 +CONFIG_NLS_CODEPAGE_866=m
1622 +CONFIG_NLS_CODEPAGE_869=m
1623 +CONFIG_NLS_CODEPAGE_936=m
1624 +CONFIG_NLS_CODEPAGE_950=m
1625 +CONFIG_NLS_CODEPAGE_932=m
1626 +CONFIG_NLS_CODEPAGE_949=m
1627 +CONFIG_NLS_CODEPAGE_874=m
1628 +CONFIG_NLS_ISO8859_8=m
1629 +CONFIG_NLS_CODEPAGE_1250=m
1630 +CONFIG_NLS_CODEPAGE_1251=m
1631 +CONFIG_NLS_ASCII=y
1632 +CONFIG_NLS_ISO8859_1=m
1633 +CONFIG_NLS_ISO8859_2=m
1634 +CONFIG_NLS_ISO8859_3=m
1635 +CONFIG_NLS_ISO8859_4=m
1636 +CONFIG_NLS_ISO8859_5=m
1637 +CONFIG_NLS_ISO8859_6=m
1638 +CONFIG_NLS_ISO8859_7=m
1639 +CONFIG_NLS_ISO8859_9=m
1640 +CONFIG_NLS_ISO8859_13=m
1641 +CONFIG_NLS_ISO8859_14=m
1642 +CONFIG_NLS_ISO8859_15=m
1643 +CONFIG_NLS_KOI8_R=m
1644 +CONFIG_NLS_KOI8_U=m
1645 +CONFIG_NLS_UTF8=m
1646 +CONFIG_PRINTK_TIME=y
1647 +CONFIG_DETECT_HUNG_TASK=y
1648 +CONFIG_TIMER_STATS=y
1649 +CONFIG_DEBUG_STACK_USAGE=y
1650 +CONFIG_DEBUG_INFO=y
1651 +CONFIG_DEBUG_MEMORY_INIT=y
1652 +CONFIG_BOOT_PRINTK_DELAY=y
1653 +CONFIG_LATENCYTOP=y
1654 +CONFIG_SYSCTL_SYSCALL_CHECK=y
1655 +CONFIG_IRQSOFF_TRACER=y
1656 +CONFIG_SCHED_TRACER=y
1657 +CONFIG_STACK_TRACER=y
1658 +CONFIG_BLK_DEV_IO_TRACE=y
1659 +CONFIG_FUNCTION_PROFILER=y
1660 +CONFIG_KGDB=y
1661 +CONFIG_KGDB_KDB=y
1662 +CONFIG_KDB_KEYBOARD=y
1663 +CONFIG_STRICT_DEVMEM=y
1664 +CONFIG_CRYPTO_AUTHENC=m
1665 +CONFIG_CRYPTO_SEQIV=m
1666 +CONFIG_CRYPTO_CBC=y
1667 +CONFIG_CRYPTO_HMAC=y
1668 +CONFIG_CRYPTO_XCBC=m
1669 +CONFIG_CRYPTO_MD5=y
1670 +CONFIG_CRYPTO_SHA1=y
1671 +CONFIG_CRYPTO_SHA256=m
1672 +CONFIG_CRYPTO_SHA512=m
1673 +CONFIG_CRYPTO_TGR192=m
1674 +CONFIG_CRYPTO_WP512=m
1675 +CONFIG_CRYPTO_CAST5=m
1676 +CONFIG_CRYPTO_DES=y
1677 +CONFIG_CRYPTO_DEFLATE=m
1678 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1679 +# CONFIG_CRYPTO_HW is not set
1680 +CONFIG_CRC_ITU_T=y
1681 +CONFIG_LIBCRC32C=y
1682 --- a/arch/arm/kernel/process.c
1683 +++ b/arch/arm/kernel/process.c
1684 @@ -174,7 +174,7 @@ void arch_cpu_idle(void)
1685                 default_idle();
1686  }
1687
1688 -static char reboot_mode = 'h';
1689 +char reboot_mode = 'h';
1690
1691  int __init reboot_setup(char *str)
1692  {
1693 --- /dev/null
1694 +++ b/arch/arm/mach-bcm2708/Kconfig
1695 @@ -0,0 +1,34 @@
1696 +menu "Broadcom BCM2708 Implementations"
1697 +       depends on ARCH_BCM2708
1698 +
1699 +config MACH_BCM2708
1700 +       bool "Broadcom BCM2708 Development Platform"
1701 +       select NEED_MACH_MEMORY_H
1702 +       select NEED_MACH_IO_H
1703 +       select CPU_V6
1704 +       help
1705 +         Include support for the Broadcom(R) BCM2708 platform.
1706 +
1707 +config BCM2708_GPIO
1708 +       bool "BCM2708 gpio support"
1709 +       depends on MACH_BCM2708
1710 +       select ARCH_REQUIRE_GPIOLIB
1711 +        default y
1712 +       help
1713 +         Include support for the Broadcom(R) BCM2708 gpio.
1714 +
1715 +config BCM2708_VCMEM
1716 +       bool "Videocore Memory"
1717 +       depends on MACH_BCM2708
1718 +        default y
1719 +        help
1720 +          Helper for videocore memory access and total size allocation.
1721 +
1722 +config BCM2708_NOL2CACHE
1723 +       bool "Videocore L2 cache disable"
1724 +       depends on MACH_BCM2708
1725 +        default n
1726 +        help
1727 +          Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
1728 +
1729 +endmenu
1730 --- /dev/null
1731 +++ b/arch/arm/mach-bcm2708/Makefile
1732 @@ -0,0 +1,8 @@
1733 +#
1734 +# Makefile for the linux kernel.
1735 +#
1736 +
1737 +obj-$(CONFIG_MACH_BCM2708)     += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o
1738 +obj-$(CONFIG_BCM2708_GPIO)     += bcm2708_gpio.o
1739 +obj-$(CONFIG_BCM2708_VCMEM)    += vc_mem.o
1740 +
1741 --- /dev/null
1742 +++ b/arch/arm/mach-bcm2708/Makefile.boot
1743 @@ -0,0 +1,3 @@
1744 +   zreladdr-y  := 0x00008000
1745 +params_phys-y  := 0x00000100
1746 +initrd_phys-y  := 0x00800000
1747 --- /dev/null
1748 +++ b/arch/arm/mach-bcm2708/armctrl.c
1749 @@ -0,0 +1,208 @@
1750 +/*
1751 + *  linux/arch/arm/mach-bcm2708/armctrl.c
1752 + *
1753 + *  Copyright (C) 2010 Broadcom
1754 + *
1755 + * This program is free software; you can redistribute it and/or modify
1756 + * it under the terms of the GNU General Public License as published by
1757 + * the Free Software Foundation; either version 2 of the License, or
1758 + * (at your option) any later version.
1759 + *
1760 + * This program is distributed in the hope that it will be useful,
1761 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1762 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1763 + * GNU General Public License for more details.
1764 + *
1765 + * You should have received a copy of the GNU General Public License
1766 + * along with this program; if not, write to the Free Software
1767 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
1768 + */
1769 +#include <linux/init.h>
1770 +#include <linux/list.h>
1771 +#include <linux/io.h>
1772 +#include <linux/version.h>
1773 +#include <linux/syscore_ops.h>
1774 +#include <linux/interrupt.h>
1775 +
1776 +#include <asm/mach/irq.h>
1777 +#include <mach/hardware.h>
1778 +#include "armctrl.h"
1779 +
1780 +/* For support of kernels >= 3.0 assume only one VIC for now*/
1781 +static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
1782 +       INTERRUPT_VC_JPEG,
1783 +       INTERRUPT_VC_USB,
1784 +       INTERRUPT_VC_3D,
1785 +       INTERRUPT_VC_DMA2,
1786 +       INTERRUPT_VC_DMA3,
1787 +       INTERRUPT_VC_I2C,
1788 +       INTERRUPT_VC_SPI,
1789 +       INTERRUPT_VC_I2SPCM,
1790 +       INTERRUPT_VC_SDIO,
1791 +       INTERRUPT_VC_UART,
1792 +       INTERRUPT_VC_ARASANSDIO
1793 +};
1794 +
1795 +static void armctrl_mask_irq(struct irq_data *d)
1796 +{
1797 +       static const unsigned int disables[4] = {
1798 +               ARM_IRQ_DIBL1,
1799 +               ARM_IRQ_DIBL2,
1800 +               ARM_IRQ_DIBL3,
1801 +               0
1802 +       };
1803 +
1804 +       unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
1805 +       writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
1806 +}
1807 +
1808 +static void armctrl_unmask_irq(struct irq_data *d)
1809 +{
1810 +       static const unsigned int enables[4] = {
1811 +               ARM_IRQ_ENBL1,
1812 +               ARM_IRQ_ENBL2,
1813 +               ARM_IRQ_ENBL3,
1814 +               0
1815 +       };
1816 +
1817 +       unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
1818 +       writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
1819 +}
1820 +
1821 +#if defined(CONFIG_PM)
1822 +
1823 +/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
1824 +
1825 +/* Static defines
1826 + * struct armctrl_device - VIC PM device (< 3.xx)
1827 + * @sysdev: The system device which is registered. (< 3.xx)
1828 + * @irq: The IRQ number for the base of the VIC.
1829 + * @base: The register base for the VIC.
1830 + * @resume_sources: A bitmask of interrupts for resume.
1831 + * @resume_irqs: The IRQs enabled for resume.
1832 + * @int_select: Save for VIC_INT_SELECT.
1833 + * @int_enable: Save for VIC_INT_ENABLE.
1834 + * @soft_int: Save for VIC_INT_SOFT.
1835 + * @protect: Save for VIC_PROTECT.
1836 + */
1837 +struct armctrl_info {
1838 +       void __iomem *base;
1839 +       int irq;
1840 +       u32 resume_sources;
1841 +       u32 resume_irqs;
1842 +       u32 int_select;
1843 +       u32 int_enable;
1844 +       u32 soft_int;
1845 +       u32 protect;
1846 +} armctrl;
1847 +
1848 +static int armctrl_suspend(void)
1849 +{
1850 +       return 0;
1851 +}
1852 +
1853 +static void armctrl_resume(void)
1854 +{
1855 +       return;
1856 +}
1857 +
1858 +/**
1859 + * armctrl_pm_register - Register a VIC for later power management control
1860 + * @base: The base address of the VIC.
1861 + * @irq: The base IRQ for the VIC.
1862 + * @resume_sources: bitmask of interrupts allowed for resume sources.
1863 + *
1864 + * For older kernels (< 3.xx) do -
1865 + * Register the VIC with the system device tree so that it can be notified
1866 + * of suspend and resume requests and ensure that the correct actions are
1867 + * taken to re-instate the settings on resume.
1868 + */
1869 +static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
1870 +                                      u32 resume_sources)
1871 +{
1872 +       armctrl.base = base;
1873 +       armctrl.resume_sources = resume_sources;
1874 +       armctrl.irq = irq;
1875 +}
1876 +
1877 +static int armctrl_set_wake(struct irq_data *d, unsigned int on)
1878 +{
1879 +       unsigned int off = d->irq & 31;
1880 +       u32 bit = 1 << off;
1881 +
1882 +       if (!(bit & armctrl.resume_sources))
1883 +               return -EINVAL;
1884 +
1885 +       if (on)
1886 +               armctrl.resume_irqs |= bit;
1887 +       else
1888 +               armctrl.resume_irqs &= ~bit;
1889 +
1890 +       return 0;
1891 +}
1892 +
1893 +#else
1894 +static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
1895 +                                      u32 arg1)
1896 +{
1897 +}
1898 +
1899 +#define armctrl_suspend NULL
1900 +#define armctrl_resume NULL
1901 +#define armctrl_set_wake NULL
1902 +#endif /* CONFIG_PM */
1903 +
1904 +static struct syscore_ops armctrl_syscore_ops = {
1905 +       .suspend = armctrl_suspend,
1906 +       .resume = armctrl_resume,
1907 +};
1908 +
1909 +/**
1910 + * armctrl_syscore_init - initicall to register VIC pm functions
1911 + *
1912 + * This is called via late_initcall() to register
1913 + * the resources for the VICs due to the early
1914 + * nature of the VIC's registration.
1915 +*/
1916 +static int __init armctrl_syscore_init(void)
1917 +{
1918 +       register_syscore_ops(&armctrl_syscore_ops);
1919 +       return 0;
1920 +}
1921 +
1922 +late_initcall(armctrl_syscore_init);
1923 +
1924 +static struct irq_chip armctrl_chip = {
1925 +       .name = "ARMCTRL",
1926 +       .irq_ack = armctrl_mask_irq,
1927 +       .irq_mask = armctrl_mask_irq,
1928 +       .irq_unmask = armctrl_unmask_irq,
1929 +       .irq_set_wake = armctrl_set_wake,
1930 +};
1931 +
1932 +/**
1933 + * armctrl_init - initialise a vectored interrupt controller
1934 + * @base: iomem base address
1935 + * @irq_start: starting interrupt number, must be muliple of 32
1936 + * @armctrl_sources: bitmask of interrupt sources to allow
1937 + * @resume_sources: bitmask of interrupt sources to allow for resume
1938 + */
1939 +int __init armctrl_init(void __iomem * base, unsigned int irq_start,
1940 +                       u32 armctrl_sources, u32 resume_sources)
1941 +{
1942 +       unsigned int irq;
1943 +
1944 +       for (irq = 0; irq < NR_IRQS; irq++) {
1945 +               unsigned int data = irq;
1946 +               if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
1947 +                       data = remap_irqs[irq - INTERRUPT_JPEG];
1948 +
1949 +               irq_set_chip(irq, &armctrl_chip);
1950 +               irq_set_chip_data(irq, (void *)data);
1951 +               irq_set_handler(irq, handle_level_irq);
1952 +               set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED);
1953 +       }
1954 +
1955 +       armctrl_pm_register(base, irq_start, resume_sources);
1956 +       return 0;
1957 +}
1958 --- /dev/null
1959 +++ b/arch/arm/mach-bcm2708/armctrl.h
1960 @@ -0,0 +1,27 @@
1961 +/*
1962 + *  linux/arch/arm/mach-bcm2708/armctrl.h
1963 + *
1964 + *  Copyright (C) 2010 Broadcom
1965 + *
1966 + * This program is free software; you can redistribute it and/or modify
1967 + * it under the terms of the GNU General Public License as published by
1968 + * the Free Software Foundation; either version 2 of the License, or
1969 + * (at your option) any later version.
1970 + *
1971 + * This program is distributed in the hope that it will be useful,
1972 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1973 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1974 + * GNU General Public License for more details.
1975 + *
1976 + * You should have received a copy of the GNU General Public License
1977 + * along with this program; if not, write to the Free Software
1978 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
1979 + */
1980 +
1981 +#ifndef __BCM2708_ARMCTRL_H
1982 +#define __BCM2708_ARMCTRL_H
1983 +
1984 +extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
1985 +                              u32 armctrl_sources, u32 resume_sources);
1986 +
1987 +#endif
1988 --- /dev/null
1989 +++ b/arch/arm/mach-bcm2708/bcm2708.c
1990 @@ -0,0 +1,695 @@
1991 +/*
1992 + *  linux/arch/arm/mach-bcm2708/bcm2708.c
1993 + *
1994 + *  Copyright (C) 2010 Broadcom
1995 + *
1996 + * This program is free software; you can redistribute it and/or modify
1997 + * it under the terms of the GNU General Public License as published by
1998 + * the Free Software Foundation; either version 2 of the License, or
1999 + * (at your option) any later version.
2000 + *
2001 + * This program is distributed in the hope that it will be useful,
2002 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2003 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2004 + * GNU General Public License for more details.
2005 + *
2006 + * You should have received a copy of the GNU General Public License
2007 + * along with this program; if not, write to the Free Software
2008 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2009 + */
2010 +
2011 +#include <linux/init.h>
2012 +#include <linux/device.h>
2013 +#include <linux/dma-mapping.h>
2014 +#include <linux/serial_8250.h>
2015 +#include <linux/platform_device.h>
2016 +#include <linux/syscore_ops.h>
2017 +#include <linux/interrupt.h>
2018 +#include <linux/amba/bus.h>
2019 +#include <linux/amba/clcd.h>
2020 +#include <linux/clockchips.h>
2021 +#include <linux/cnt32_to_63.h>
2022 +#include <linux/io.h>
2023 +#include <linux/module.h>
2024 +
2025 +#include <linux/version.h>
2026 +#include <linux/clkdev.h>
2027 +#include <asm/system.h>
2028 +#include <mach/hardware.h>
2029 +#include <asm/irq.h>
2030 +#include <linux/leds.h>
2031 +#include <asm/mach-types.h>
2032 +#include <asm/sched_clock.h>
2033 +
2034 +#include <asm/mach/arch.h>
2035 +#include <asm/mach/flash.h>
2036 +#include <asm/mach/irq.h>
2037 +#include <asm/mach/time.h>
2038 +#include <asm/mach/map.h>
2039 +
2040 +#include <mach/timex.h>
2041 +#include <mach/dma.h>
2042 +#include <mach/vcio.h>
2043 +#include <mach/system.h>
2044 +
2045 +#include <linux/delay.h>
2046 +
2047 +#include "bcm2708.h"
2048 +#include "armctrl.h"
2049 +#include "clock.h"
2050 +
2051 +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
2052 + * give us IO access only to 64Mbytes of physical memory (26 bits).  We could
2053 + * represent this window by setting our dmamasks to 26 bits but, in fact
2054 + * we're not going to use addresses outside this range (they're not in real
2055 + * memory) so we don't bother.
2056 + *
2057 + * In the future we might include code to use this IOMMU to remap other
2058 + * physical addresses onto VideoCore memory then the use of 32-bits would be
2059 + * more legitimate.
2060 + */
2061 +#define DMA_MASK_BITS_COMMON 32
2062 +
2063 +/* command line parameters */
2064 +static unsigned boardrev, serial;
2065 +static unsigned uart_clock;
2066 +static unsigned reboot_part = 0;
2067 +
2068 +static void __init bcm2708_init_led(void);
2069 +
2070 +void __init bcm2708_init_irq(void)
2071 +{
2072 +       armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
2073 +}
2074 +
2075 +static struct map_desc bcm2708_io_desc[] __initdata = {
2076 +       {
2077 +        .virtual = IO_ADDRESS(ARMCTRL_BASE),
2078 +        .pfn = __phys_to_pfn(ARMCTRL_BASE),
2079 +        .length = SZ_4K,
2080 +        .type = MT_DEVICE},
2081 +       {
2082 +        .virtual = IO_ADDRESS(UART0_BASE),
2083 +        .pfn = __phys_to_pfn(UART0_BASE),
2084 +        .length = SZ_4K,
2085 +        .type = MT_DEVICE},
2086 +       {
2087 +        .virtual = IO_ADDRESS(UART1_BASE),
2088 +        .pfn = __phys_to_pfn(UART1_BASE),
2089 +        .length = SZ_4K,
2090 +        .type = MT_DEVICE},
2091 +       {
2092 +        .virtual = IO_ADDRESS(DMA_BASE),
2093 +        .pfn = __phys_to_pfn(DMA_BASE),
2094 +        .length = SZ_4K,
2095 +        .type = MT_DEVICE},
2096 +       {
2097 +        .virtual = IO_ADDRESS(MCORE_BASE),
2098 +        .pfn = __phys_to_pfn(MCORE_BASE),
2099 +        .length = SZ_4K,
2100 +        .type = MT_DEVICE},
2101 +       {
2102 +        .virtual = IO_ADDRESS(ST_BASE),
2103 +        .pfn = __phys_to_pfn(ST_BASE),
2104 +        .length = SZ_4K,
2105 +        .type = MT_DEVICE},
2106 +       {
2107 +        .virtual = IO_ADDRESS(USB_BASE),
2108 +        .pfn = __phys_to_pfn(USB_BASE),
2109 +        .length = SZ_128K,
2110 +        .type = MT_DEVICE},
2111 +       {
2112 +        .virtual = IO_ADDRESS(PM_BASE),
2113 +        .pfn = __phys_to_pfn(PM_BASE),
2114 +        .length = SZ_4K,
2115 +        .type = MT_DEVICE},
2116 +       {
2117 +        .virtual = IO_ADDRESS(GPIO_BASE),
2118 +        .pfn = __phys_to_pfn(GPIO_BASE),
2119 +        .length = SZ_4K,
2120 +        .type = MT_DEVICE}
2121 +};
2122 +
2123 +void __init bcm2708_map_io(void)
2124 +{
2125 +       iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
2126 +}
2127 +
2128 +/* The STC is a free running counter that increments at the rate of 1MHz */
2129 +#define STC_FREQ_HZ 1000000
2130 +
2131 +static inline uint32_t timer_read(void)
2132 +{
2133 +       /* STC: a free running counter that increments at the rate of 1MHz */
2134 +       return readl(__io_address(ST_BASE + 0x04));
2135 +}
2136 +
2137 +static unsigned long bcm2708_read_current_timer(void)
2138 +{
2139 +       return timer_read();
2140 +}
2141 +
2142 +static u32 notrace bcm2708_read_sched_clock(void)
2143 +{
2144 +       return timer_read();
2145 +}
2146 +
2147 +static cycle_t clksrc_read(struct clocksource *cs)
2148 +{
2149 +       return timer_read();
2150 +}
2151 +
2152 +static struct clocksource clocksource_stc = {
2153 +       .name = "stc",
2154 +       .rating = 300,
2155 +       .read = clksrc_read,
2156 +       .mask = CLOCKSOURCE_MASK(32),
2157 +       .flags = CLOCK_SOURCE_IS_CONTINUOUS,
2158 +};
2159 +
2160 +unsigned long frc_clock_ticks32(void)
2161 +{
2162 +       return timer_read();
2163 +}
2164 +
2165 +static void __init bcm2708_clocksource_init(void)
2166 +{
2167 +       if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
2168 +               printk(KERN_ERR "timer: failed to initialize clock "
2169 +                      "source %s\n", clocksource_stc.name);
2170 +       }
2171 +}
2172 +
2173 +
2174 +/*
2175 + * These are fixed clocks.
2176 + */
2177 +static struct clk ref24_clk = {
2178 +       .rate = UART0_CLOCK,    /* The UART is clocked at 3MHz via APB_CLK */
2179 +};
2180 +
2181 +static struct clk osc_clk = {
2182 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
2183 +       .rate = 27000000,
2184 +#else
2185 +       .rate = 500000000,      /* ARM clock is set from the VideoCore booter */
2186 +#endif
2187 +};
2188 +
2189 +/* warning - the USB needs a clock > 34MHz */
2190 +
2191 +#ifdef CONFIG_MMC_BCM2708
2192 +static struct clk sdhost_clk = {
2193 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
2194 +       .rate = 4000000,        /* 4MHz */
2195 +#else
2196 +       .rate = 250000000,      /* 250MHz */
2197 +#endif
2198 +};
2199 +#endif
2200 +
2201 +static struct clk_lookup lookups[] = {
2202 +       {                       /* UART0 */
2203 +        .dev_id = "dev:f1",
2204 +        .clk = &ref24_clk,
2205 +        },
2206 +       {                       /* USB */
2207 +        .dev_id = "bcm2708_usb",
2208 +        .clk = &osc_clk,
2209 +        }
2210 +};
2211 +
2212 +#define UART0_IRQ      { IRQ_UART, 0 /*NO_IRQ*/ }
2213 +#define UART0_DMA      { 15, 14 }
2214 +
2215 +AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
2216 +
2217 +static struct amba_device *amba_devs[] __initdata = {
2218 +       &uart0_device,
2219 +};
2220 +
2221 +static struct resource bcm2708_dmaman_resources[] = {
2222 +       {
2223 +        .start = DMA_BASE,
2224 +        .end = DMA_BASE + SZ_4K - 1,
2225 +        .flags = IORESOURCE_MEM,
2226 +        }
2227 +};
2228 +
2229 +static struct platform_device bcm2708_dmaman_device = {
2230 +       .name = BCM_DMAMAN_DRIVER_NAME,
2231 +       .id = 0,                /* first bcm2708_dma */
2232 +       .resource = bcm2708_dmaman_resources,
2233 +       .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources),
2234 +};
2235 +
2236 +static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2237 +
2238 +static struct platform_device bcm2708_fb_device = {
2239 +       .name = "bcm2708_fb",
2240 +       .id = -1,               /* only one bcm2708_fb */
2241 +       .resource = NULL,
2242 +       .num_resources = 0,
2243 +       .dev = {
2244 +               .dma_mask = &fb_dmamask,
2245 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2246 +               },
2247 +};
2248 +
2249 +static struct plat_serial8250_port bcm2708_uart1_platform_data[] = {
2250 +       {
2251 +        .mapbase = UART1_BASE + 0x40,
2252 +        .irq = IRQ_AUX,
2253 +        .uartclk = 125000000,
2254 +        .regshift = 2,
2255 +        .iotype = UPIO_MEM,
2256 +        .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST,
2257 +        .type = PORT_8250,
2258 +        },
2259 +       {},
2260 +};
2261 +
2262 +static struct platform_device bcm2708_uart1_device = {
2263 +       .name = "serial8250",
2264 +       .id = PLAT8250_DEV_PLATFORM,
2265 +       .dev = {
2266 +               .platform_data = bcm2708_uart1_platform_data,
2267 +               },
2268 +};
2269 +
2270 +static struct resource bcm2708_usb_resources[] = {
2271 +       [0] = {
2272 +              .start = USB_BASE,
2273 +              .end = USB_BASE + SZ_128K - 1,
2274 +              .flags = IORESOURCE_MEM,
2275 +              },
2276 +       [1] = {
2277 +              .start = IRQ_USB,
2278 +              .end = IRQ_USB,
2279 +              .flags = IORESOURCE_IRQ,
2280 +              },
2281 +};
2282 +
2283 +static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2284 +
2285 +static struct platform_device bcm2708_usb_device = {
2286 +       .name = "bcm2708_usb",
2287 +       .id = -1,               /* only one bcm2708_usb */
2288 +       .resource = bcm2708_usb_resources,
2289 +       .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
2290 +       .dev = {
2291 +               .dma_mask = &usb_dmamask,
2292 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2293 +               },
2294 +};
2295 +
2296 +static struct resource bcm2708_vcio_resources[] = {
2297 +       [0] = {                 /* mailbox/semaphore/doorbell access */
2298 +              .start = MCORE_BASE,
2299 +              .end = MCORE_BASE + SZ_4K - 1,
2300 +              .flags = IORESOURCE_MEM,
2301 +              },
2302 +};
2303 +
2304 +static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2305 +
2306 +static struct platform_device bcm2708_vcio_device = {
2307 +       .name = BCM_VCIO_DRIVER_NAME,
2308 +       .id = -1,               /* only one VideoCore I/O area */
2309 +       .resource = bcm2708_vcio_resources,
2310 +       .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
2311 +       .dev = {
2312 +               .dma_mask = &vcio_dmamask,
2313 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2314 +               },
2315 +};
2316 +
2317 +#ifdef CONFIG_BCM2708_GPIO
2318 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
2319 +
2320 +static struct resource bcm2708_gpio_resources[] = {
2321 +       [0] = {                 /* general purpose I/O */
2322 +              .start = GPIO_BASE,
2323 +              .end = GPIO_BASE + SZ_4K - 1,
2324 +              .flags = IORESOURCE_MEM,
2325 +              },
2326 +};
2327 +
2328 +static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2329 +
2330 +static struct platform_device bcm2708_gpio_device = {
2331 +       .name = BCM_GPIO_DRIVER_NAME,
2332 +       .id = -1,               /* only one VideoCore I/O area */
2333 +       .resource = bcm2708_gpio_resources,
2334 +       .num_resources = ARRAY_SIZE(bcm2708_gpio_resources),
2335 +       .dev = {
2336 +               .dma_mask = &gpio_dmamask,
2337 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2338 +               },
2339 +};
2340 +#endif
2341 +
2342 +static struct resource bcm2708_systemtimer_resources[] = {
2343 +       [0] = {                 /* system timer access */
2344 +              .start = ST_BASE,
2345 +              .end = ST_BASE + SZ_4K - 1,
2346 +              .flags = IORESOURCE_MEM,
2347 +              },
2348 +       {
2349 +        .start = IRQ_TIMER3,
2350 +        .end = IRQ_TIMER3,
2351 +        .flags = IORESOURCE_IRQ,
2352 +        }
2353 +
2354 +};
2355 +
2356 +static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2357 +
2358 +static struct platform_device bcm2708_systemtimer_device = {
2359 +       .name = "bcm2708_systemtimer",
2360 +       .id = -1,               /* only one VideoCore I/O area */
2361 +       .resource = bcm2708_systemtimer_resources,
2362 +       .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources),
2363 +       .dev = {
2364 +               .dma_mask = &systemtimer_dmamask,
2365 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2366 +               },
2367 +};
2368 +
2369 +#ifdef CONFIG_MMC_SDHCI_BCM2708        /* Arasan emmc SD */
2370 +static struct resource bcm2708_emmc_resources[] = {
2371 +       [0] = {
2372 +              .start = EMMC_BASE,
2373 +              .end = EMMC_BASE + SZ_256 - 1,   /* we only need this area */
2374 +              /* the memory map actually makes SZ_4K available  */
2375 +              .flags = IORESOURCE_MEM,
2376 +              },
2377 +       [1] = {
2378 +              .start = IRQ_ARASANSDIO,
2379 +              .end = IRQ_ARASANSDIO,
2380 +              .flags = IORESOURCE_IRQ,
2381 +              },
2382 +};
2383 +
2384 +static u64 bcm2708_emmc_dmamask = 0xffffffffUL;
2385 +
2386 +struct platform_device bcm2708_emmc_device = {
2387 +       .name = "bcm2708_sdhci",
2388 +       .id = 0,
2389 +       .num_resources = ARRAY_SIZE(bcm2708_emmc_resources),
2390 +       .resource = bcm2708_emmc_resources,
2391 +       .dev = {
2392 +               .dma_mask = &bcm2708_emmc_dmamask,
2393 +               .coherent_dma_mask = 0xffffffffUL},
2394 +};
2395 +#endif /* CONFIG_MMC_SDHCI_BCM2708 */
2396 +
2397 +static struct resource bcm2708_powerman_resources[] = {
2398 +       [0] = {
2399 +              .start = PM_BASE,
2400 +              .end = PM_BASE + SZ_256 - 1,
2401 +              .flags = IORESOURCE_MEM,
2402 +              },
2403 +};
2404 +
2405 +static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2406 +
2407 +struct platform_device bcm2708_powerman_device = {
2408 +       .name = "bcm2708_powerman",
2409 +       .id = 0,
2410 +       .num_resources = ARRAY_SIZE(bcm2708_powerman_resources),
2411 +       .resource = bcm2708_powerman_resources,
2412 +       .dev = {
2413 +               .dma_mask = &powerman_dmamask,
2414 +               .coherent_dma_mask = 0xffffffffUL},
2415 +};
2416 +
2417 +int __init bcm_register_device(struct platform_device *pdev)
2418 +{
2419 +       int ret;
2420 +
2421 +       ret = platform_device_register(pdev);
2422 +       if (ret)
2423 +               pr_debug("Unable to register platform device '%s': %d\n",
2424 +                        pdev->name, ret);
2425 +
2426 +       return ret;
2427 +}
2428 +
2429 +int calc_rsts(int partition)
2430 +{
2431 +       return PM_PASSWORD |
2432 +               ((partition & (1 << 0))  << 0) |
2433 +               ((partition & (1 << 1))  << 1) |
2434 +               ((partition & (1 << 2))  << 2) |
2435 +               ((partition & (1 << 3))  << 3) |
2436 +               ((partition & (1 << 4))  << 4) |
2437 +               ((partition & (1 << 5))  << 5);
2438 +}
2439 +
2440 +static void bcm2708_restart(char mode, const char *cmd)
2441 +{
2442 +       uint32_t pm_rstc, pm_wdog;
2443 +       uint32_t timeout = 10;
2444 +       uint32_t pm_rsts = 0;
2445 +
2446 +       if(mode == 'q')
2447 +       {
2448 +               // NOOBS < 1.3 booting with reboot=q
2449 +               pm_rsts = readl(__io_address(PM_RSTS));
2450 +               pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
2451 +       }
2452 +       else if(mode == 'p')
2453 +       {
2454 +               // NOOBS < 1.3 halting
2455 +               pm_rsts = readl(__io_address(PM_RSTS));
2456 +               pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
2457 +       }
2458 +       else
2459 +       {
2460 +               pm_rsts = calc_rsts(reboot_part);
2461 +       }
2462 +
2463 +       writel(pm_rsts, __io_address(PM_RSTS));
2464 +
2465 +       /* Setup watchdog for reset */
2466 +       pm_rstc = readl(__io_address(PM_RSTC));
2467 +
2468 +       pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
2469 +       pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
2470 +
2471 +       writel(pm_wdog, __io_address(PM_WDOG));
2472 +       writel(pm_rstc, __io_address(PM_RSTC));
2473 +}
2474 +
2475 +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
2476 +static void bcm2708_power_off(void)
2477 +{
2478 +       extern char reboot_mode;
2479 +
2480 +       if(reboot_mode == 'q')
2481 +       {
2482 +               // NOOBS < v1.3
2483 +               bcm2708_restart('p', "");
2484 +       }
2485 +       else
2486 +       {
2487 +               /* partition 63 is special code for HALT the bootloader knows not to boot*/
2488 +               reboot_part = 63;
2489 +               /* continue with normal reset mechanism */
2490 +               bcm2708_restart(0, "");
2491 +       }
2492 +}
2493 +
2494 +void __init bcm2708_init(void)
2495 +{
2496 +       int i;
2497 +
2498 +       printk("bcm2708.uart_clock = %d\n", uart_clock);
2499 +       pm_power_off = bcm2708_power_off;
2500 +
2501 +       if (uart_clock)
2502 +               lookups[0].clk->rate = uart_clock;
2503 +
2504 +       for (i = 0; i < ARRAY_SIZE(lookups); i++)
2505 +               clkdev_add(&lookups[i]);
2506 +
2507 +       bcm_register_device(&bcm2708_dmaman_device);
2508 +       bcm_register_device(&bcm2708_vcio_device);
2509 +#ifdef CONFIG_BCM2708_GPIO
2510 +       bcm_register_device(&bcm2708_gpio_device);
2511 +#endif
2512 +       bcm_register_device(&bcm2708_systemtimer_device);
2513 +       bcm_register_device(&bcm2708_fb_device);
2514 +       bcm_register_device(&bcm2708_usb_device);
2515 +       bcm_register_device(&bcm2708_uart1_device);
2516 +       bcm_register_device(&bcm2708_powerman_device);
2517 +
2518 +#ifdef CONFIG_MMC_SDHCI_BCM2708
2519 +       bcm_register_device(&bcm2708_emmc_device);
2520 +#endif
2521 +       bcm2708_init_led();
2522 +
2523 +       for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
2524 +               struct amba_device *d = amba_devs[i];
2525 +               amba_device_register(d, &iomem_resource);
2526 +       }
2527 +       system_rev = boardrev;
2528 +       system_serial_low = serial;
2529 +}
2530 +
2531 +static void timer_set_mode(enum clock_event_mode mode,
2532 +                          struct clock_event_device *clk)
2533 +{
2534 +       switch (mode) {
2535 +       case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
2536 +       case CLOCK_EVT_MODE_SHUTDOWN:
2537 +               break;
2538 +       case CLOCK_EVT_MODE_PERIODIC:
2539 +
2540 +       case CLOCK_EVT_MODE_UNUSED:
2541 +       case CLOCK_EVT_MODE_RESUME:
2542 +
2543 +       default:
2544 +               printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
2545 +                      (int)mode);
2546 +               break;
2547 +       }
2548 +
2549 +}
2550 +
2551 +static int timer_set_next_event(unsigned long cycles,
2552 +                               struct clock_event_device *unused)
2553 +{
2554 +       unsigned long stc;
2555 +
2556 +       stc = readl(__io_address(ST_BASE + 0x04));
2557 +       writel(stc + cycles, __io_address(ST_BASE + 0x18));     /* stc3 */
2558 +       return 0;
2559 +}
2560 +
2561 +static struct clock_event_device timer0_clockevent = {
2562 +       .name = "timer0",
2563 +       .shift = 32,
2564 +       .features = CLOCK_EVT_FEAT_ONESHOT,
2565 +       .set_mode = timer_set_mode,
2566 +       .set_next_event = timer_set_next_event,
2567 +};
2568 +
2569 +/*
2570 + * IRQ handler for the timer
2571 + */
2572 +static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id)
2573 +{
2574 +       struct clock_event_device *evt = &timer0_clockevent;
2575 +
2576 +       writel(1 << 3, __io_address(ST_BASE + 0x00));   /* stcs clear timer int */
2577 +
2578 +       evt->event_handler(evt);
2579 +
2580 +       return IRQ_HANDLED;
2581 +}
2582 +
2583 +static struct irqaction bcm2708_timer_irq = {
2584 +       .name = "BCM2708 Timer Tick",
2585 +       .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
2586 +       .handler = bcm2708_timer_interrupt,
2587 +};
2588 +
2589 +/*
2590 + * Set up timer interrupt, and return the current time in seconds.
2591 + */
2592 +
2593 +static struct delay_timer bcm2708_delay_timer = {
2594 +       .read_current_timer = bcm2708_read_current_timer,
2595 +       .freq = STC_FREQ_HZ,
2596 +};
2597 +
2598 +static void __init bcm2708_timer_init(void)
2599 +{
2600 +       /* init high res timer */
2601 +       bcm2708_clocksource_init();
2602 +
2603 +       /*
2604 +        * Initialise to a known state (all timers off)
2605 +        */
2606 +       writel(0, __io_address(ARM_T_CONTROL));
2607 +       /*
2608 +        * Make irqs happen for the system timer
2609 +        */
2610 +       setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
2611 +
2612 +       setup_sched_clock(bcm2708_read_sched_clock, 32, STC_FREQ_HZ);
2613 +
2614 +       timer0_clockevent.mult =
2615 +           div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
2616 +       timer0_clockevent.max_delta_ns =
2617 +           clockevent_delta2ns(0xffffffff, &timer0_clockevent);
2618 +       timer0_clockevent.min_delta_ns =
2619 +           clockevent_delta2ns(0xf, &timer0_clockevent);
2620 +
2621 +       timer0_clockevent.cpumask = cpumask_of(0);
2622 +       clockevents_register_device(&timer0_clockevent);
2623 +
2624 +       register_current_timer_delay(&bcm2708_delay_timer);
2625 +}
2626 +
2627 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
2628 +#include <linux/leds.h>
2629 +
2630 +static struct gpio_led bcm2708_leds[] = {
2631 +       [0] = {
2632 +              .gpio = 16,
2633 +              .name = "led0",
2634 +              .default_trigger = "mmc0",
2635 +              .active_low = 1,
2636 +              },
2637 +};
2638 +
2639 +static struct gpio_led_platform_data bcm2708_led_pdata = {
2640 +       .num_leds = ARRAY_SIZE(bcm2708_leds),
2641 +       .leds = bcm2708_leds,
2642 +};
2643 +
2644 +static struct platform_device bcm2708_led_device = {
2645 +       .name = "leds-gpio",
2646 +       .id = -1,
2647 +       .dev = {
2648 +               .platform_data = &bcm2708_led_pdata,
2649 +               },
2650 +};
2651 +
2652 +static void __init bcm2708_init_led(void)
2653 +{
2654 +       platform_device_register(&bcm2708_led_device);
2655 +}
2656 +#else
2657 +static inline void bcm2708_init_led(void)
2658 +{
2659 +}
2660 +#endif
2661 +
2662 +void __init bcm2708_init_early(void)
2663 +{
2664 +       /*
2665 +        * Some devices allocate their coherent buffers from atomic
2666 +        * context. Increase size of atomic coherent pool to make sure such
2667 +        * the allocations won't fail.
2668 +        */
2669 +       init_dma_coherent_pool_size(SZ_4M);
2670 +}
2671 +
2672 +MACHINE_START(BCM2708, "BCM2708")
2673 +    /* Maintainer: Broadcom Europe Ltd. */
2674 +       .map_io = bcm2708_map_io,
2675 +       .init_irq = bcm2708_init_irq,
2676 +       .init_time = bcm2708_timer_init,
2677 +       .init_machine = bcm2708_init,
2678 +       .init_early = bcm2708_init_early,
2679 +       .restart = bcm2708_restart,
2680 +MACHINE_END
2681 +
2682 +module_param(boardrev, uint, 0644);
2683 +module_param(serial, uint, 0644);
2684 +module_param(uart_clock, uint, 0644);
2685 +module_param(reboot_part, uint, 0644);
2686 --- /dev/null
2687 +++ b/arch/arm/mach-bcm2708/bcm2708.h
2688 @@ -0,0 +1,51 @@
2689 +/*
2690 + * linux/arch/arm/mach-bcm2708/bcm2708.h
2691 + *
2692 + * BCM2708 machine support header
2693 + *
2694 + *  Copyright (C) 2010 Broadcom
2695 + *
2696 + * This program is free software; you can redistribute it and/or modify
2697 + * it under the terms of the GNU General Public License as published by
2698 + * the Free Software Foundation; either version 2 of the License, or
2699 + * (at your option) any later version.
2700 + *
2701 + * This program is distributed in the hope that it will be useful,
2702 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2703 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2704 + * GNU General Public License for more details.
2705 + *
2706 + * You should have received a copy of the GNU General Public License
2707 + * along with this program; if not, write to the Free Software
2708 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2709 + */
2710 +
2711 +#ifndef __BCM2708_BCM2708_H
2712 +#define __BCM2708_BCM2708_H
2713 +
2714 +#include <linux/amba/bus.h>
2715 +
2716 +extern void __init bcm2708_init(void);
2717 +extern void __init bcm2708_init_irq(void);
2718 +extern void __init bcm2708_map_io(void);
2719 +extern struct sys_timer bcm2708_timer;
2720 +extern unsigned int mmc_status(struct device *dev);
2721 +
2722 +#define AMBA_DEVICE(name, busid, base, plat)                   \
2723 +static struct amba_device name##_device = {                    \
2724 +       .dev            = {                                     \
2725 +               .coherent_dma_mask = ~0,                        \
2726 +               .init_name = busid,                             \
2727 +               .platform_data = plat,                          \
2728 +       },                                                      \
2729 +       .res            = {                                     \
2730 +               .start  = base##_BASE,          \
2731 +               .end    = (base##_BASE) + SZ_4K - 1,\
2732 +               .flags  = IORESOURCE_MEM,                       \
2733 +       },                                                      \
2734 +       .dma_mask       = ~0,                                   \
2735 +       .irq            = base##_IRQ,                           \
2736 +       /* .dma         = base##_DMA,*/                         \
2737 +}
2738 +
2739 +#endif
2740 --- /dev/null
2741 +++ b/arch/arm/mach-bcm2708/bcm2708_gpio.c
2742 @@ -0,0 +1,339 @@
2743 +/*
2744 + *  linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
2745 + *
2746 + *  Copyright (C) 2010 Broadcom
2747 + *
2748 + * This program is free software; you can redistribute it and/or modify
2749 + * it under the terms of the GNU General Public License version 2 as
2750 + * published by the Free Software Foundation.
2751 + *
2752 + */
2753 +
2754 +#include <linux/spinlock.h>
2755 +#include <linux/module.h>
2756 +#include <linux/list.h>
2757 +#include <linux/io.h>
2758 +#include <linux/irq.h>
2759 +#include <linux/interrupt.h>
2760 +#include <linux/slab.h>
2761 +#include <mach/gpio.h>
2762 +#include <linux/gpio.h>
2763 +#include <linux/platform_device.h>
2764 +#include <mach/platform.h>
2765 +
2766 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
2767 +#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
2768 +#define BCM_GPIO_USE_IRQ 1
2769 +
2770 +#define GPIOFSEL(x)  (0x00+(x)*4)
2771 +#define GPIOSET(x)   (0x1c+(x)*4)
2772 +#define GPIOCLR(x)   (0x28+(x)*4)
2773 +#define GPIOLEV(x)   (0x34+(x)*4)
2774 +#define GPIOEDS(x)   (0x40+(x)*4)
2775 +#define GPIOREN(x)   (0x4c+(x)*4)
2776 +#define GPIOFEN(x)   (0x58+(x)*4)
2777 +#define GPIOHEN(x)   (0x64+(x)*4)
2778 +#define GPIOLEN(x)   (0x70+(x)*4)
2779 +#define GPIOAREN(x)  (0x7c+(x)*4)
2780 +#define GPIOAFEN(x)  (0x88+(x)*4)
2781 +#define GPIOUD(x)    (0x94+(x)*4)
2782 +#define GPIOUDCLK(x) (0x98+(x)*4)
2783 +
2784 +enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
2785 +       GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
2786 +       GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
2787 +       GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
2788 +};
2789 +
2790 +       /* Each of the two spinlocks protects a different set of hardware
2791 +        * regiters and data structurs. This decouples the code of the IRQ from
2792 +        * the GPIO code. This also makes the case of a GPIO routine call from
2793 +        * the IRQ code simpler.
2794 +        */
2795 +static DEFINE_SPINLOCK(lock);  /* GPIO registers */
2796 +
2797 +struct bcm2708_gpio {
2798 +       struct list_head list;
2799 +       void __iomem *base;
2800 +       struct gpio_chip gc;
2801 +       unsigned long rising;
2802 +       unsigned long falling;
2803 +};
2804 +
2805 +static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset,
2806 +                               int function)
2807 +{
2808 +       struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2809 +       unsigned long flags;
2810 +       unsigned gpiodir;
2811 +       unsigned gpio_bank = offset / 10;
2812 +       unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
2813 +
2814 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
2815 +       if (offset >= ARCH_NR_GPIOS)
2816 +               return -EINVAL;
2817 +
2818 +       spin_lock_irqsave(&lock, flags);
2819 +
2820 +       gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
2821 +       gpiodir &= ~(7 << gpio_field_offset);
2822 +       gpiodir |= function << gpio_field_offset;
2823 +       writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
2824 +       spin_unlock_irqrestore(&lock, flags);
2825 +       gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
2826 +
2827 +       return 0;
2828 +}
2829 +
2830 +static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
2831 +{
2832 +       return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
2833 +}
2834 +
2835 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2836 +static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
2837 +                               int value)
2838 +{
2839 +       int ret;
2840 +       ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
2841 +       if (ret >= 0)
2842 +               bcm2708_gpio_set(gc, offset, value);
2843 +       return ret;
2844 +}
2845 +
2846 +static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
2847 +{
2848 +       struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2849 +       unsigned gpio_bank = offset / 32;
2850 +       unsigned gpio_field_offset = (offset - 32 * gpio_bank);
2851 +       unsigned lev;
2852 +
2853 +       if (offset >= ARCH_NR_GPIOS)
2854 +               return 0;
2855 +       lev = readl(gpio->base + GPIOLEV(gpio_bank));
2856 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
2857 +       return 0x1 & (lev >> gpio_field_offset);
2858 +}
2859 +
2860 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2861 +{
2862 +       struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2863 +       unsigned gpio_bank = offset / 32;
2864 +       unsigned gpio_field_offset = (offset - 32 * gpio_bank);
2865 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
2866 +       if (offset >= ARCH_NR_GPIOS)
2867 +               return;
2868 +       if (value)
2869 +               writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
2870 +       else
2871 +               writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
2872 +}
2873 +
2874 +/*************************************************************************************************************************
2875 + * bcm2708 GPIO IRQ
2876 + */
2877 +
2878 +#if BCM_GPIO_USE_IRQ
2879 +
2880 +static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
2881 +{
2882 +       return gpio_to_irq(gpio);
2883 +}
2884 +
2885 +static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type)
2886 +{
2887 +       unsigned irq = d->irq;
2888 +       struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2889 +
2890 +       if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
2891 +               return -EINVAL;
2892 +
2893 +       if (type & IRQ_TYPE_EDGE_RISING) {
2894 +               gpio->rising |= (1 << irq_to_gpio(irq));
2895 +       } else {
2896 +               gpio->rising &= ~(1 << irq_to_gpio(irq));
2897 +       }
2898 +
2899 +       if (type & IRQ_TYPE_EDGE_FALLING) {
2900 +               gpio->falling |= (1 << irq_to_gpio(irq));
2901 +       } else {
2902 +               gpio->falling &= ~(1 << irq_to_gpio(irq));
2903 +       }
2904 +       return 0;
2905 +}
2906 +
2907 +static void bcm2708_gpio_irq_mask(struct irq_data *d)
2908 +{
2909 +       unsigned irq = d->irq;
2910 +       struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2911 +       unsigned gn = irq_to_gpio(irq);
2912 +       unsigned gb = gn / 32;
2913 +       unsigned long rising = readl(gpio->base + GPIOREN(gb));
2914 +       unsigned long falling = readl(gpio->base + GPIOFEN(gb));
2915 +
2916 +       gn = gn % 32;
2917 +
2918 +       writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
2919 +       writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
2920 +}
2921 +
2922 +static void bcm2708_gpio_irq_unmask(struct irq_data *d)
2923 +{
2924 +       unsigned irq = d->irq;
2925 +       struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2926 +       unsigned gn = irq_to_gpio(irq);
2927 +       unsigned gb = gn / 32;
2928 +       unsigned long rising = readl(gpio->base + GPIOREN(gb));
2929 +       unsigned long falling = readl(gpio->base + GPIOFEN(gb));
2930 +
2931 +       gn = gn % 32;
2932 +
2933 +       writel(1 << gn, gpio->base + GPIOEDS(gb));
2934 +
2935 +       if (gpio->rising & (1 << gn)) {
2936 +               writel(rising | (1 << gn), gpio->base + GPIOREN(gb));
2937 +       } else {
2938 +               writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
2939 +       }
2940 +
2941 +       if (gpio->falling & (1 << gn)) {
2942 +               writel(falling | (1 << gn), gpio->base + GPIOFEN(gb));
2943 +       } else {
2944 +               writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
2945 +       }
2946 +}
2947 +
2948 +static struct irq_chip bcm2708_irqchip = {
2949 +       .name = "GPIO",
2950 +       .irq_enable = bcm2708_gpio_irq_unmask,
2951 +       .irq_disable = bcm2708_gpio_irq_mask,
2952 +       .irq_unmask = bcm2708_gpio_irq_unmask,
2953 +       .irq_mask = bcm2708_gpio_irq_mask,
2954 +       .irq_set_type = bcm2708_gpio_irq_set_type,
2955 +};
2956 +
2957 +static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id)
2958 +{
2959 +       unsigned long edsr;
2960 +       unsigned bank;
2961 +       int i;
2962 +       unsigned gpio;
2963 +       for (bank = 0; bank <= 1; bank++) {
2964 +               edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank));
2965 +               for_each_set_bit(i, &edsr, 32) {
2966 +                       gpio = i + bank * 32;
2967 +                       generic_handle_irq(gpio_to_irq(gpio));
2968 +               }
2969 +               writel(0xffffffff, __io_address(GPIO_BASE) + GPIOEDS(bank));
2970 +       }
2971 +       return IRQ_HANDLED;
2972 +}
2973 +
2974 +static struct irqaction bcm2708_gpio_irq = {
2975 +       .name = "BCM2708 GPIO catchall handler",
2976 +       .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
2977 +       .handler = bcm2708_gpio_interrupt,
2978 +};
2979 +
2980 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
2981 +{
2982 +       unsigned irq;
2983 +
2984 +       ucb->gc.to_irq = bcm2708_gpio_to_irq;
2985 +
2986 +       for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) {
2987 +               irq_set_chip_data(irq, ucb);
2988 +               irq_set_chip(irq, &bcm2708_irqchip);
2989 +               set_irq_flags(irq, IRQF_VALID);
2990 +       }
2991 +       setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq);
2992 +}
2993 +
2994 +#else
2995 +
2996 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
2997 +{
2998 +}
2999 +
3000 +#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */
3001 +
3002 +static int bcm2708_gpio_probe(struct platform_device *dev)
3003 +{
3004 +       struct bcm2708_gpio *ucb;
3005 +       struct resource *res;
3006 +       int err = 0;
3007 +
3008 +       printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
3009 +
3010 +       ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
3011 +       if (NULL == ucb) {
3012 +               printk(KERN_ERR DRIVER_NAME ": failed to allocate "
3013 +                      "mailbox memory\n");
3014 +               err = -ENOMEM;
3015 +               goto err;
3016 +       }
3017 +
3018 +       res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3019 +
3020 +       platform_set_drvdata(dev, ucb);
3021 +       ucb->base = __io_address(GPIO_BASE);
3022 +
3023 +       ucb->gc.label = "bcm2708_gpio";
3024 +       ucb->gc.base = 0;
3025 +       ucb->gc.ngpio = ARCH_NR_GPIOS;
3026 +       ucb->gc.owner = THIS_MODULE;
3027 +
3028 +       ucb->gc.direction_input = bcm2708_gpio_dir_in;
3029 +       ucb->gc.direction_output = bcm2708_gpio_dir_out;
3030 +       ucb->gc.get = bcm2708_gpio_get;
3031 +       ucb->gc.set = bcm2708_gpio_set;
3032 +       ucb->gc.can_sleep = 0;
3033 +
3034 +       bcm2708_gpio_irq_init(ucb);
3035 +
3036 +       err = gpiochip_add(&ucb->gc);
3037 +       if (err)
3038 +               goto err;
3039 +
3040 +err:
3041 +       return err;
3042 +
3043 +}
3044 +
3045 +static int bcm2708_gpio_remove(struct platform_device *dev)
3046 +{
3047 +       int err = 0;
3048 +       struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
3049 +
3050 +       printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
3051 +
3052 +       err = gpiochip_remove(&ucb->gc);
3053 +
3054 +       platform_set_drvdata(dev, NULL);
3055 +       kfree(ucb);
3056 +
3057 +       return err;
3058 +}
3059 +
3060 +static struct platform_driver bcm2708_gpio_driver = {
3061 +       .probe = bcm2708_gpio_probe,
3062 +       .remove = bcm2708_gpio_remove,
3063 +       .driver = {
3064 +                  .name = "bcm2708_gpio"},
3065 +};
3066 +
3067 +static int __init bcm2708_gpio_init(void)
3068 +{
3069 +       return platform_driver_register(&bcm2708_gpio_driver);
3070 +}
3071 +
3072 +static void __exit bcm2708_gpio_exit(void)
3073 +{
3074 +       platform_driver_unregister(&bcm2708_gpio_driver);
3075 +}
3076 +
3077 +module_init(bcm2708_gpio_init);
3078 +module_exit(bcm2708_gpio_exit);
3079 +
3080 +MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
3081 +MODULE_LICENSE("GPL");
3082 --- /dev/null
3083 +++ b/arch/arm/mach-bcm2708/clock.c
3084 @@ -0,0 +1,61 @@
3085 +/*
3086 + *  linux/arch/arm/mach-bcm2708/clock.c
3087 + *
3088 + *  Copyright (C) 2010 Broadcom
3089 + *
3090 + * This program is free software; you can redistribute it and/or modify
3091 + * it under the terms of the GNU General Public License as published by
3092 + * the Free Software Foundation; either version 2 of the License, or
3093 + * (at your option) any later version.
3094 + *
3095 + * This program is distributed in the hope that it will be useful,
3096 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3097 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3098 + * GNU General Public License for more details.
3099 + *
3100 + * You should have received a copy of the GNU General Public License
3101 + * along with this program; if not, write to the Free Software
3102 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
3103 + */
3104 +#include <linux/module.h>
3105 +#include <linux/kernel.h>
3106 +#include <linux/device.h>
3107 +#include <linux/list.h>
3108 +#include <linux/errno.h>
3109 +#include <linux/err.h>
3110 +#include <linux/string.h>
3111 +#include <linux/clk.h>
3112 +#include <linux/mutex.h>
3113 +
3114 +#include <asm/clkdev.h>
3115 +
3116 +#include "clock.h"
3117 +
3118 +int clk_enable(struct clk *clk)
3119 +{
3120 +       return 0;
3121 +}
3122 +EXPORT_SYMBOL(clk_enable);
3123 +
3124 +void clk_disable(struct clk *clk)
3125 +{
3126 +}
3127 +EXPORT_SYMBOL(clk_disable);
3128 +
3129 +unsigned long clk_get_rate(struct clk *clk)
3130 +{
3131 +       return clk->rate;
3132 +}
3133 +EXPORT_SYMBOL(clk_get_rate);
3134 +
3135 +long clk_round_rate(struct clk *clk, unsigned long rate)
3136 +{
3137 +       return clk->rate;
3138 +}
3139 +EXPORT_SYMBOL(clk_round_rate);
3140 +
3141 +int clk_set_rate(struct clk *clk, unsigned long rate)
3142 +{
3143 +       return -EIO;
3144 +}
3145 +EXPORT_SYMBOL(clk_set_rate);
3146 --- /dev/null
3147 +++ b/arch/arm/mach-bcm2708/clock.h
3148 @@ -0,0 +1,24 @@
3149 +/*
3150 + *  linux/arch/arm/mach-bcm2708/clock.h
3151 + *
3152 + *  Copyright (C) 2010 Broadcom
3153 + *
3154 + * This program is free software; you can redistribute it and/or modify
3155 + * it under the terms of the GNU General Public License as published by
3156 + * the Free Software Foundation; either version 2 of the License, or
3157 + * (at your option) any later version.
3158 + *
3159 + * This program is distributed in the hope that it will be useful,
3160 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3161 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3162 + * GNU General Public License for more details.
3163 + *
3164 + * You should have received a copy of the GNU General Public License
3165 + * along with this program; if not, write to the Free Software
3166 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
3167 + */
3168 +struct module;
3169 +
3170 +struct clk {
3171 +       unsigned long           rate;
3172 +};
3173 --- /dev/null
3174 +++ b/arch/arm/mach-bcm2708/dma.c
3175 @@ -0,0 +1,399 @@
3176 +/*
3177 + *  linux/arch/arm/mach-bcm2708/dma.c
3178 + *
3179 + *  Copyright (C) 2010 Broadcom
3180 + *
3181 + * This program is free software; you can redistribute it and/or modify
3182 + * it under the terms of the GNU General Public License version 2 as
3183 + * published by the Free Software Foundation.
3184 + */
3185 +
3186 +#include <linux/slab.h>
3187 +#include <linux/device.h>
3188 +#include <linux/platform_device.h>
3189 +#include <linux/module.h>
3190 +#include <linux/scatterlist.h>
3191 +
3192 +#include <mach/dma.h>
3193 +#include <mach/irqs.h>
3194 +
3195 +/*****************************************************************************\
3196 + *                                                                          *
3197 + * Configuration                                                            *
3198 + *                                                                          *
3199 +\*****************************************************************************/
3200 +
3201 +#define CACHE_LINE_MASK 31
3202 +#define DRIVER_NAME BCM_DMAMAN_DRIVER_NAME
3203 +#define DEFAULT_DMACHAN_BITMAP 0x10  /* channel 4 only */
3204 +
3205 +/* valid only for channels 0 - 14, 15 has its own base address */
3206 +#define BCM2708_DMA_CHAN(n)    ((n)<<8) /* base address */
3207 +#define BCM2708_DMA_CHANIO(dma_base, n) \
3208 +   ((void __iomem *)((char *)(dma_base)+BCM2708_DMA_CHAN(n)))
3209 +
3210 +
3211 +/*****************************************************************************\
3212 + *                                                                          *
3213 + * DMA Auxilliary Functions                                                 *
3214 + *                                                                          *
3215 +\*****************************************************************************/
3216 +
3217 +/* A DMA buffer on an arbitrary boundary may separate a cache line into a
3218 +   section inside the DMA buffer and another section outside it.
3219 +   Even if we flush DMA buffers from the cache there is always the chance that
3220 +   during a DMA someone will access the part of a cache line that is outside
3221 +   the DMA buffer - which will then bring in unwelcome data.
3222 +   Without being able to dictate our own buffer pools we must insist that
3223 +   DMA buffers consist of a whole number of cache lines.
3224 +*/
3225 +
3226 +extern int
3227 +bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
3228 +{
3229 +       int i;
3230 +
3231 +       for (i = 0; i < sg_len; i++) {
3232 +               if (sg_ptr[i].offset & CACHE_LINE_MASK ||
3233 +                   sg_ptr[i].length & CACHE_LINE_MASK)
3234 +                       return 0;
3235 +       }
3236 +
3237 +       return 1;
3238 +}
3239 +EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
3240 +
3241 +extern void
3242 +bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block)
3243 +{
3244 +       dsb();  /* ARM data synchronization (push) operation */
3245 +
3246 +       writel(control_block,        dma_chan_base + BCM2708_DMA_ADDR);
3247 +       writel(BCM2708_DMA_ACTIVE,   dma_chan_base + BCM2708_DMA_CS);
3248 +}
3249 +
3250 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
3251 +{
3252 +  dsb();
3253 +
3254 +  /* ugly busy wait only option for now */
3255 +  while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
3256 +    cpu_relax();
3257 +}
3258 +
3259 +EXPORT_SYMBOL_GPL(bcm_dma_start);
3260 +
3261 +/* Complete an ongoing DMA (assuming its results are to be ignored)
3262 +   Does nothing if there is no DMA in progress.
3263 +   This routine waits for the current AXI transfer to complete before
3264 +   terminating the current DMA.         If the current transfer is hung on a DREQ used
3265 +   by an uncooperative peripheral the AXI transfer may never complete. In this
3266 +   case the routine times out and return a non-zero error code.
3267 +   Use of this routine doesn't guarantee that the ongoing or aborted DMA
3268 +   does not produce an interrupt.
3269 +*/
3270 +extern int
3271 +bcm_dma_abort(void __iomem *dma_chan_base)
3272 +{
3273 +       unsigned long int cs;
3274 +       int rc = 0;
3275 +
3276 +       cs = readl(dma_chan_base + BCM2708_DMA_CS);
3277 +
3278 +       if (BCM2708_DMA_ACTIVE & cs) {
3279 +               long int timeout = 10000;
3280 +
3281 +               /* write 0 to the active bit - pause the DMA */
3282 +               writel(0, dma_chan_base + BCM2708_DMA_CS);
3283 +
3284 +               /* wait for any current AXI transfer to complete */
3285 +               while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
3286 +                       cs = readl(dma_chan_base + BCM2708_DMA_CS);
3287 +
3288 +               if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
3289 +                       /* we'll un-pause when we set of our next DMA */
3290 +                       rc = -ETIMEDOUT;
3291 +
3292 +               } else if (BCM2708_DMA_ACTIVE & cs) {
3293 +                       /* terminate the control block chain */
3294 +                       writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
3295 +
3296 +                       /* abort the whole DMA */
3297 +                       writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
3298 +                              dma_chan_base + BCM2708_DMA_CS);
3299 +               }
3300 +       }
3301 +
3302 +       return rc;
3303 +}
3304 +EXPORT_SYMBOL_GPL(bcm_dma_abort);
3305 +
3306 +
3307 +/***************************************************************************** \
3308 + *                                                                          *
3309 + * DMA Manager Device Methods                                               *
3310 + *                                                                          *
3311 +\*****************************************************************************/
3312 +
3313 +struct vc_dmaman {
3314 +       void __iomem *dma_base;
3315 +       u32 chan_available; /* bitmap of available channels */
3316 +       u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
3317 +};
3318 +
3319 +static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
3320 +                          u32 chans_available)
3321 +{
3322 +       dmaman->dma_base = dma_base;
3323 +       dmaman->chan_available = chans_available;
3324 +       dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c;  /* chans 2 & 3 */
3325 +       dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01;  /* chan 0 */
3326 +}
3327 +
3328 +static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
3329 +                               unsigned preferred_feature_set)
3330 +{
3331 +       u32 chans;
3332 +       int feature;
3333 +
3334 +       chans = dmaman->chan_available;
3335 +       for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
3336 +               /* select the subset of available channels with the desired
3337 +                  feature so long as some of the candidate channels have that
3338 +                  feature */
3339 +               if ((preferred_feature_set & (1 << feature)) &&
3340 +                   (chans & dmaman->has_feature[feature]))
3341 +                       chans &= dmaman->has_feature[feature];
3342 +
3343 +       if (chans) {
3344 +               int chan = 0;
3345 +               /* return the ordinal of the first channel in the bitmap */
3346 +               while (chans != 0 && (chans & 1) == 0) {
3347 +                       chans >>= 1;
3348 +                       chan++;
3349 +               }
3350 +               /* claim the channel */
3351 +               dmaman->chan_available &= ~(1 << chan);
3352 +               return chan;
3353 +       } else
3354 +               return -ENOMEM;
3355 +}
3356 +
3357 +static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
3358 +{
3359 +       if (chan < 0)
3360 +               return -EINVAL;
3361 +       else if ((1 << chan) & dmaman->chan_available)
3362 +               return -EIDRM;
3363 +       else {
3364 +               dmaman->chan_available |= (1 << chan);
3365 +               return 0;
3366 +       }
3367 +}
3368 +
3369 +/*****************************************************************************\
3370 + *                                                                          *
3371 + * DMA IRQs                                                                 *
3372 + *                                                                          *
3373 +\*****************************************************************************/
3374 +
3375 +static unsigned char bcm_dma_irqs[] = {
3376 +       IRQ_DMA0,
3377 +       IRQ_DMA1,
3378 +       IRQ_DMA2,
3379 +       IRQ_DMA3,
3380 +       IRQ_DMA4,
3381 +       IRQ_DMA5,
3382 +       IRQ_DMA6,
3383 +       IRQ_DMA7,
3384 +       IRQ_DMA8,
3385 +       IRQ_DMA9,
3386 +       IRQ_DMA10,
3387 +       IRQ_DMA11,
3388 +       IRQ_DMA12
3389 +};
3390 +
3391 +
3392 +/***************************************************************************** \
3393 + *                                                                          *
3394 + * DMA Manager Monitor                                                      *
3395 + *                                                                          *
3396 +\*****************************************************************************/
3397 +
3398 +static struct device *dmaman_dev;      /* we assume there's only one! */
3399 +
3400 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
3401 +                             void __iomem **out_dma_base, int *out_dma_irq)
3402 +{
3403 +       if (!dmaman_dev)
3404 +               return -ENODEV;
3405 +       else {
3406 +               struct vc_dmaman *dmaman  = dev_get_drvdata(dmaman_dev);
3407 +               int rc;
3408 +
3409 +               device_lock(dmaman_dev);
3410 +               rc = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
3411 +               if (rc >= 0) {
3412 +                       *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base,
3413 +                                                          rc);
3414 +                       *out_dma_irq = bcm_dma_irqs[rc];
3415 +               }
3416 +               device_unlock(dmaman_dev);
3417 +
3418 +               return rc;
3419 +       }
3420 +}
3421 +EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
3422 +
3423 +extern int bcm_dma_chan_free(int channel)
3424 +{
3425 +       if (dmaman_dev) {
3426 +               struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
3427 +               int rc;
3428 +
3429 +               device_lock(dmaman_dev);
3430 +               rc = vc_dmaman_chan_free(dmaman, channel);
3431 +               device_unlock(dmaman_dev);
3432 +
3433 +               return rc;
3434 +       } else
3435 +               return -ENODEV;
3436 +}
3437 +EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
3438 +
3439 +static int dev_dmaman_register(const char *dev_name, struct device *dev)
3440 +{
3441 +       int rc = dmaman_dev ? -EINVAL : 0;
3442 +       dmaman_dev = dev;
3443 +       return rc;
3444 +}
3445 +
3446 +static void dev_dmaman_deregister(const char *dev_name, struct device *dev)
3447 +{
3448 +       dmaman_dev = NULL;
3449 +}
3450 +
3451 +/*****************************************************************************\
3452 + *                                                                          *
3453 + * DMA Device                                                               *
3454 + *                                                                          *
3455 +\*****************************************************************************/
3456 +
3457 +static int dmachans = -1; /* module parameter */
3458 +
3459 +static int bcm_dmaman_probe(struct platform_device *pdev)
3460 +{
3461 +       int ret = 0;
3462 +       struct vc_dmaman *dmaman;
3463 +       struct resource *dma_res = NULL;
3464 +       void __iomem *dma_base = NULL;
3465 +       int have_dma_region = 0;
3466 +
3467 +       dmaman = kzalloc(sizeof(*dmaman), GFP_KERNEL);
3468 +       if (NULL == dmaman) {
3469 +               printk(KERN_ERR DRIVER_NAME ": failed to allocate "
3470 +                      "DMA management memory\n");
3471 +               ret = -ENOMEM;
3472 +       } else {
3473 +
3474 +               dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3475 +               if (dma_res == NULL) {
3476 +                       printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
3477 +                              "resource\n");
3478 +                       ret = -ENODEV;
3479 +               } else if (!request_mem_region(dma_res->start,
3480 +                                              resource_size(dma_res),
3481 +                                              DRIVER_NAME)) {
3482 +                       dev_err(&pdev->dev, "cannot obtain DMA region\n");
3483 +                       ret = -EBUSY;
3484 +               } else {
3485 +                       have_dma_region = 1;
3486 +                       dma_base = ioremap(dma_res->start,
3487 +                                          resource_size(dma_res));
3488 +                       if (!dma_base) {
3489 +                               dev_err(&pdev->dev, "cannot map DMA region\n");
3490 +                               ret = -ENOMEM;
3491 +                       } else {
3492 +                               /* use module parameter if one was provided */
3493 +                               if (dmachans > 0)
3494 +                                       vc_dmaman_init(dmaman, dma_base,
3495 +                                                      dmachans);
3496 +                               else
3497 +                                       vc_dmaman_init(dmaman, dma_base,
3498 +                                                      DEFAULT_DMACHAN_BITMAP);
3499 +
3500 +                               platform_set_drvdata(pdev, dmaman);
3501 +                               dev_dmaman_register(DRIVER_NAME, &pdev->dev);
3502 +
3503 +                               printk(KERN_INFO DRIVER_NAME ": DMA manager "
3504 +                                      "at %p\n", dma_base);
3505 +                       }
3506 +               }
3507 +       }
3508 +       if (ret != 0) {
3509 +               if (dma_base)
3510 +                       iounmap(dma_base);
3511 +               if (dma_res && have_dma_region)
3512 +                       release_mem_region(dma_res->start,
3513 +                                          resource_size(dma_res));
3514 +               if (dmaman)
3515 +                       kfree(dmaman);
3516 +       }
3517 +       return ret;
3518 +}
3519 +
3520 +static int bcm_dmaman_remove(struct platform_device *pdev)
3521 +{
3522 +       struct vc_dmaman *dmaman = platform_get_drvdata(pdev);
3523 +
3524 +       platform_set_drvdata(pdev, NULL);
3525 +       dev_dmaman_deregister(DRIVER_NAME, &pdev->dev);
3526 +       kfree(dmaman);
3527 +
3528 +       return 0;
3529 +}
3530 +
3531 +static struct platform_driver bcm_dmaman_driver = {
3532 +       .probe = bcm_dmaman_probe,
3533 +       .remove = bcm_dmaman_remove,
3534 +
3535 +       .driver = {
3536 +                  .name = DRIVER_NAME,
3537 +                  .owner = THIS_MODULE,
3538 +                  },
3539 +};
3540 +
3541 +/*****************************************************************************\
3542 + *                                                                          *
3543 + * Driver init/exit                                                         *
3544 + *                                                                          *
3545 +\*****************************************************************************/
3546 +
3547 +static int __init bcm_dmaman_drv_init(void)
3548 +{
3549 +       int ret;
3550 +
3551 +       ret = platform_driver_register(&bcm_dmaman_driver);
3552 +       if (ret != 0) {
3553 +               printk(KERN_ERR DRIVER_NAME ": failed to register "
3554 +                      "on platform\n");
3555 +       }
3556 +
3557 +       return ret;
3558 +}
3559 +
3560 +static void __exit bcm_dmaman_drv_exit(void)
3561 +{
3562 +       platform_driver_unregister(&bcm_dmaman_driver);
3563 +}
3564 +
3565 +module_init(bcm_dmaman_drv_init);
3566 +module_exit(bcm_dmaman_drv_exit);
3567 +
3568 +module_param(dmachans, int, 0644);
3569 +
3570 +MODULE_AUTHOR("Gray Girling <grayg@broadcom.com>");
3571 +MODULE_DESCRIPTION("DMA channel manager driver");
3572 +MODULE_LICENSE("GPL");
3573 +
3574 +MODULE_PARM_DESC(dmachans, "Bitmap of DMA channels available to the ARM");
3575 --- /dev/null
3576 +++ b/arch/arm/mach-bcm2708/include/mach/arm_control.h
3577 @@ -0,0 +1,419 @@
3578 +/*
3579 + *  linux/arch/arm/mach-bcm2708/arm_control.h
3580 + *
3581 + *  Copyright (C) 2010 Broadcom
3582 + *
3583 + * This program is free software; you can redistribute it and/or modify
3584 + * it under the terms of the GNU General Public License as published by
3585 + * the Free Software Foundation; either version 2 of the License, or
3586 + * (at your option) any later version.
3587 + *
3588 + * This program is distributed in the hope that it will be useful,
3589 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3590 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3591 + * GNU General Public License for more details.
3592 + *
3593 + * You should have received a copy of the GNU General Public License
3594 + * along with this program; if not, write to the Free Software
3595 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
3596 + */
3597 +
3598 +#ifndef __BCM2708_ARM_CONTROL_H
3599 +#define __BCM2708_ARM_CONTROL_H
3600 +
3601 +/*
3602 + * Definitions and addresses for the ARM CONTROL logic
3603 + * This file is manually generated.
3604 + */
3605 +
3606 +#define ARM_BASE  0x7E00B000
3607 +
3608 +/* Basic configuration */
3609 +#define ARM_CONTROL0  HW_REGISTER_RW(ARM_BASE+0x000)
3610 +#define ARM_C0_SIZ128M   0x00000000
3611 +#define ARM_C0_SIZ256M   0x00000001
3612 +#define ARM_C0_SIZ512M   0x00000002
3613 +#define ARM_C0_SIZ1G     0x00000003
3614 +#define ARM_C0_BRESP0    0x00000000
3615 +#define ARM_C0_BRESP1    0x00000004
3616 +#define ARM_C0_BRESP2    0x00000008
3617 +#define ARM_C0_BOOTHI    0x00000010
3618 +#define ARM_C0_UNUSED05  0x00000020 /* free */
3619 +#define ARM_C0_FULLPERI  0x00000040
3620 +#define ARM_C0_UNUSED78  0x00000180 /* free */
3621 +#define ARM_C0_JTAGMASK  0x00000E00
3622 +#define ARM_C0_JTAGOFF   0x00000000
3623 +#define ARM_C0_JTAGBASH  0x00000800 /* Debug on GPIO off */
3624 +#define ARM_C0_JTAGGPIO  0x00000C00 /* Debug on GPIO on */
3625 +#define ARM_C0_APROTMSK  0x0000F000
3626 +#define ARM_C0_DBG0SYNC  0x00010000 /* VPU0 halt sync */
3627 +#define ARM_C0_DBG1SYNC  0x00020000 /* VPU1 halt sync */
3628 +#define ARM_C0_SWDBGREQ  0x00040000 /* HW debug request */
3629 +#define ARM_C0_PASSHALT  0x00080000 /* ARM halt passed to debugger */
3630 +#define ARM_C0_PRIO_PER  0x00F00000 /* per priority mask */
3631 +#define ARM_C0_PRIO_L2   0x0F000000
3632 +#define ARM_C0_PRIO_UC   0xF0000000
3633 +
3634 +#define ARM_C0_APROTPASS  0x0000A000 /* Translate 1:1 */
3635 +#define ARM_C0_APROTUSER  0x00000000 /* Only user mode */
3636 +#define ARM_C0_APROTSYST  0x0000F000 /* Only system mode */
3637 +
3638 +
3639 +#define ARM_CONTROL1  HW_REGISTER_RW(ARM_BASE+0x440)
3640 +#define ARM_C1_TIMER     0x00000001 /* re-route timer IRQ  to VC */
3641 +#define ARM_C1_MAIL      0x00000002 /* re-route Mail IRQ   to VC */
3642 +#define ARM_C1_BELL0     0x00000004 /* re-route Doorbell 0 to VC */
3643 +#define ARM_C1_BELL1     0x00000008 /* re-route Doorbell 1 to VC */
3644 +#define ARM_C1_PERSON    0x00000100 /* peripherals on */
3645 +#define ARM_C1_REQSTOP   0x00000200 /* ASYNC bridge request stop */
3646 +
3647 +#define ARM_STATUS    HW_REGISTER_RW(ARM_BASE+0x444)
3648 +#define ARM_S_ACKSTOP    0x80000000 /* Bridge stopped */
3649 +#define ARM_S_READPEND   0x000003FF /* pending reads counter */
3650 +#define ARM_S_WRITPEND   0x000FFC00 /* pending writes counter */
3651 +
3652 +#define ARM_ERRHALT   HW_REGISTER_RW(ARM_BASE+0x448)
3653 +#define ARM_EH_PERIBURST  0x00000001 /* Burst write seen on peri bus */
3654 +#define ARM_EH_ILLADDRS1  0x00000002 /* Address bits 25-27 error */
3655 +#define ARM_EH_ILLADDRS2  0x00000004 /* Address bits 31-28 error */
3656 +#define ARM_EH_VPU0HALT   0x00000008 /* VPU0 halted & in debug mode */
3657 +#define ARM_EH_VPU1HALT   0x00000010 /* VPU1 halted & in debug mode */
3658 +#define ARM_EH_ARMHALT    0x00000020 /* ARM in halted debug mode */
3659 +
3660 +#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
3661 +#define ARM_ID        HW_REGISTER_RW(ARM_BASE+0x44C)
3662 +#define ARM_IDVAL        0x364D5241
3663 +
3664 +/* Translation memory */
3665 +#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
3666 +/* 32 locations: 0x100.. 0x17F */
3667 +/* 32 spare means we CAN go to 64 pages.... */
3668 +
3669 +
3670 +/* Interrupts */
3671 +#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200)        /* Top IRQ bits */
3672 +#define ARM_I0_TIMER    0x00000001 /* timer IRQ */
3673 +#define ARM_I0_MAIL     0x00000002 /* Mail IRQ */
3674 +#define ARM_I0_BELL0    0x00000004 /* Doorbell 0 */
3675 +#define ARM_I0_BELL1    0x00000008 /* Doorbell 1 */
3676 +#define ARM_I0_BANK1    0x00000100 /* Bank1 IRQ */
3677 +#define ARM_I0_BANK2    0x00000200 /* Bank2 IRQ */
3678 +
3679 +#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
3680 +/* todo: all I1_interrupt sources */
3681 +#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
3682 +/* todo: all I2_interrupt sources */
3683 +
3684 +#define ARM_IRQ_FAST  HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
3685 +#define ARM_IF_INDEX    0x0000007F     /* FIQ select */
3686 +#define ARM_IF_ENABLE   0x00000080     /* FIQ enable */
3687 +#define ARM_IF_VCMASK   0x0000003F     /* FIQ = (index from VC source) */
3688 +#define ARM_IF_TIMER    0x00000040     /* FIQ = ARM timer */
3689 +#define ARM_IF_MAIL     0x00000041     /* FIQ = ARM Mail */
3690 +#define ARM_IF_BELL0    0x00000042     /* FIQ = ARM Doorbell 0 */
3691 +#define ARM_IF_BELL1    0x00000043     /* FIQ = ARM Doorbell 1 */
3692 +#define ARM_IF_VP0HALT  0x00000044     /* FIQ = VPU0 Halt seen */
3693 +#define ARM_IF_VP1HALT  0x00000045     /* FIQ = VPU1 Halt seen */
3694 +#define ARM_IF_ILLEGAL  0x00000046     /* FIQ = Illegal access seen */
3695 +
3696 +#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
3697 +#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
3698 +#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
3699 +#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
3700 +#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
3701 +#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
3702 +#define ARM_IE_TIMER    0x00000001     /* Timer IRQ */
3703 +#define ARM_IE_MAIL     0x00000002     /* Mail IRQ */
3704 +#define ARM_IE_BELL0    0x00000004     /* Doorbell 0 */
3705 +#define ARM_IE_BELL1    0x00000008     /* Doorbell 1 */
3706 +#define ARM_IE_VP0HALT  0x00000010     /* VPU0 Halt */
3707 +#define ARM_IE_VP1HALT  0x00000020     /* VPU1 Halt */
3708 +#define ARM_IE_ILLEGAL  0x00000040     /* Illegal access seen */
3709 +
3710 +/* Timer */
3711 +/* For reg. fields see sp804 spec. */
3712 +#define ARM_T_LOAD    HW_REGISTER_RW(ARM_BASE+0x400)
3713 +#define ARM_T_VALUE   HW_REGISTER_RW(ARM_BASE+0x404)
3714 +#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
3715 +#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
3716 +#define ARM_T_RAWIRQ  HW_REGISTER_RW(ARM_BASE+0x410)
3717 +#define ARM_T_MSKIRQ  HW_REGISTER_RW(ARM_BASE+0x414)
3718 +#define ARM_T_RELOAD  HW_REGISTER_RW(ARM_BASE+0x418)
3719 +#define ARM_T_PREDIV  HW_REGISTER_RW(ARM_BASE+0x41c)
3720 +#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
3721 +
3722 +#define TIMER_CTRL_ONESHOT  (1 << 0)
3723 +#define TIMER_CTRL_32BIT    (1 << 1)
3724 +#define TIMER_CTRL_DIV1     (0 << 2)
3725 +#define TIMER_CTRL_DIV16    (1 << 2)
3726 +#define TIMER_CTRL_DIV256   (2 << 2)
3727 +#define TIMER_CTRL_IE       (1 << 5)
3728 +#define TIMER_CTRL_PERIODIC (1 << 6)
3729 +#define TIMER_CTRL_ENABLE   (1 << 7)
3730 +#define TIMER_CTRL_DBGHALT  (1 << 8)
3731 +#define TIMER_CTRL_ENAFREE  (1 << 9)
3732 +#define TIMER_CTRL_FREEDIV_SHIFT 16)
3733 +#define TIMER_CTRL_FREEDIV_MASK  0xff
3734 +
3735 +/* Semaphores, Doorbells, Mailboxes */
3736 +#define ARM_SBM_OWN0  (ARM_BASE+0x800)
3737 +#define ARM_SBM_OWN1  (ARM_BASE+0x900)
3738 +#define ARM_SBM_OWN2  (ARM_BASE+0xA00)
3739 +#define ARM_SBM_OWN3  (ARM_BASE+0xB00)
3740 +
3741 +/* MAILBOXES
3742 + * Register flags are common across all
3743 + * owner registers. See end of this section
3744 + *
3745 + * Semaphores, Doorbells, Mailboxes Owner 0
3746 + *
3747 + */
3748 +
3749 +#define ARM_0_SEMS       HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
3750 +#define ARM_0_SEM0       HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
3751 +#define ARM_0_SEM1       HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
3752 +#define ARM_0_SEM2       HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
3753 +#define ARM_0_SEM3       HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
3754 +#define ARM_0_SEM4       HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
3755 +#define ARM_0_SEM5       HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
3756 +#define ARM_0_SEM6       HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
3757 +#define ARM_0_SEM7       HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
3758 +#define ARM_0_BELL0      HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
3759 +#define ARM_0_BELL1      HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
3760 +#define ARM_0_BELL2      HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
3761 +#define ARM_0_BELL3      HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
3762 +/* MAILBOX 0 access in Owner 0 area */
3763 +/* Some addresses should ONLY be used by owner 0 */
3764 +#define ARM_0_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN0+0x80)  /* .. 0x8C (4 locations) */
3765 +#define ARM_0_MAIL0_RD   HW_REGISTER_RW(ARM_SBM_OWN0+0x80)  /* .. 0x8C (4 locations) Normal read */
3766 +#define ARM_0_MAIL0_POL  HW_REGISTER_RW(ARM_SBM_OWN0+0x90)  /* none-pop read */
3767 +#define ARM_0_MAIL0_SND  HW_REGISTER_RW(ARM_SBM_OWN0+0x94)  /* Sender read (only LS 2 bits) */
3768 +#define ARM_0_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN0+0x98)  /* Status read */
3769 +#define ARM_0_MAIL0_CNF  HW_REGISTER_RW(ARM_SBM_OWN0+0x9C)  /* Config read/write */
3770 +/* MAILBOX 1 access in Owner 0 area */
3771 +/* Owner 0 should only WRITE to this mailbox */
3772 +#define ARM_0_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN0+0xA0)   /* .. 0xAC (4 locations) */
3773 +/*#define ARM_0_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
3774 +/*#define ARM_0_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
3775 +/*#define ARM_0_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
3776 +#define ARM_0_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN0+0xB8)   /* Status read */
3777 +/*#define ARM_0_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
3778 +/* General SEM, BELL, MAIL config/status */
3779 +#define ARM_0_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN0+0xE0)  /* semaphore clear/debug register */
3780 +#define ARM_0_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN0+0xE4)  /* Doorbells clear/debug register */
3781 +#define ARM_0_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN0+0xF8)  /* ALL interrupts */
3782 +#define ARM_0_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN0+0xFC)  /* IRQS pending for owner 0 */
3783 +
3784 +/* Semaphores, Doorbells, Mailboxes Owner 1 */
3785 +#define ARM_1_SEMS       HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
3786 +#define ARM_1_SEM0       HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
3787 +#define ARM_1_SEM1       HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
3788 +#define ARM_1_SEM2       HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
3789 +#define ARM_1_SEM3       HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
3790 +#define ARM_1_SEM4       HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
3791 +#define ARM_1_SEM5       HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
3792 +#define ARM_1_SEM6       HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
3793 +#define ARM_1_SEM7       HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
3794 +#define ARM_1_BELL0      HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
3795 +#define ARM_1_BELL1      HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
3796 +#define ARM_1_BELL2      HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
3797 +#define ARM_1_BELL3      HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
3798 +/* MAILBOX 0 access in Owner 0 area */
3799 +/* Owner 1 should only WRITE to this mailbox */
3800 +#define ARM_1_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN1+0x80)  /* .. 0x8C (4 locations) */
3801 +/*#define ARM_1_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
3802 +/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
3803 +/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
3804 +#define ARM_1_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN1+0x98)  /* Status read */
3805 +/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
3806 +/* MAILBOX 1 access in Owner 0 area */
3807 +#define ARM_1_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN1+0xA0)  /* .. 0xAC (4 locations) */
3808 +#define ARM_1_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN1+0xA0)  /* .. 0xAC (4 locations) Normal read */
3809 +#define ARM_1_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN1+0xB0)  /* none-pop read */
3810 +#define ARM_1_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN1+0xB4)  /* Sender read (only LS 2 bits) */
3811 +#define ARM_1_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN1+0xB8)  /* Status read */
3812 +#define ARM_1_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
3813 +/* General SEM, BELL, MAIL config/status */
3814 +#define ARM_1_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN1+0xE0)  /* semaphore clear/debug register */
3815 +#define ARM_1_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN1+0xE4)  /* Doorbells clear/debug register */
3816 +#define ARM_1_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN1+0xFC)  /* IRQS pending for owner 1 */
3817 +#define ARM_1_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN1+0xF8)  /* ALL interrupts */
3818 +
3819 +/* Semaphores, Doorbells, Mailboxes Owner 2 */
3820 +#define ARM_2_SEMS       HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
3821 +#define ARM_2_SEM0       HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
3822 +#define ARM_2_SEM1       HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
3823 +#define ARM_2_SEM2       HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
3824 +#define ARM_2_SEM3       HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
3825 +#define ARM_2_SEM4       HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
3826 +#define ARM_2_SEM5       HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
3827 +#define ARM_2_SEM6       HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
3828 +#define ARM_2_SEM7       HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
3829 +#define ARM_2_BELL0      HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
3830 +#define ARM_2_BELL1      HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
3831 +#define ARM_2_BELL2      HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
3832 +#define ARM_2_BELL3      HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
3833 +/* MAILBOX 0 access in Owner 2 area */
3834 +/* Owner 2 should only WRITE to this mailbox */
3835 +#define ARM_2_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN2+0x80)   /* .. 0x8C (4 locations) */
3836 +/*#define ARM_2_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN2+0x80)  */ /* DO NOT USE THIS !!!!! */
3837 +/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90)  */ /* DO NOT USE THIS !!!!! */
3838 +/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94)  */ /* DO NOT USE THIS !!!!! */
3839 +#define ARM_2_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN2+0x98)   /* Status read */
3840 +/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C)  */ /* DO NOT USE THIS !!!!! */
3841 +/* MAILBOX 1 access in Owner 2 area */
3842 +/* Owner 2 should only WRITE to this mailbox */
3843 +#define ARM_2_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN2+0xA0)   /* .. 0xAC (4 locations) */
3844 +/*#define ARM_2_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
3845 +/*#define ARM_2_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
3846 +/*#define ARM_2_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
3847 +#define ARM_2_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN2+0xB8)   /* Status read */
3848 +/*#define ARM_2_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
3849 +/* General SEM, BELL, MAIL config/status */
3850 +#define ARM_2_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN2+0xE0)  /* semaphore clear/debug register */
3851 +#define ARM_2_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN2+0xE4)  /* Doorbells clear/debug register */
3852 +#define ARM_2_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN2+0xFC)  /* IRQS pending for owner 2 */
3853 +#define ARM_2_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN2+0xF8)  /* ALL interrupts */
3854 +
3855 +/* Semaphores, Doorbells, Mailboxes Owner 3 */
3856 +#define ARM_3_SEMS       HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
3857 +#define ARM_3_SEM0       HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
3858 +#define ARM_3_SEM1       HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
3859 +#define ARM_3_SEM2       HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
3860 +#define ARM_3_SEM3       HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
3861 +#define ARM_3_SEM4       HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
3862 +#define ARM_3_SEM5       HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
3863 +#define ARM_3_SEM6       HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
3864 +#define ARM_3_SEM7       HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
3865 +#define ARM_3_BELL0      HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
3866 +#define ARM_3_BELL1      HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
3867 +#define ARM_3_BELL2      HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
3868 +#define ARM_3_BELL3      HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
3869 +/* MAILBOX 0 access in Owner 3 area */
3870 +/* Owner 3 should only WRITE to this mailbox */
3871 +#define ARM_3_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN3+0x80)   /* .. 0x8C (4 locations) */
3872 +/*#define ARM_3_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN3+0x80)  */ /* DO NOT USE THIS !!!!! */
3873 +/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90)  */ /* DO NOT USE THIS !!!!! */
3874 +/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94)  */ /* DO NOT USE THIS !!!!! */
3875 +#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98)    /* Status read */
3876 +/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C)  */ /* DO NOT USE THIS !!!!! */
3877 +/* MAILBOX 1 access in Owner 3 area */
3878 +/* Owner 3 should only WRITE to this mailbox */
3879 +#define ARM_3_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN3+0xA0)   /* .. 0xAC (4 locations) */
3880 +/*#define ARM_3_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
3881 +/*#define ARM_3_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
3882 +/*#define ARM_3_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
3883 +#define ARM_3_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN3+0xB8)   /* Status read */
3884 +/*#define ARM_3_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
3885 +/* General SEM, BELL, MAIL config/status */
3886 +#define ARM_3_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN3+0xE0)  /* semaphore clear/debug register */
3887 +#define ARM_3_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN3+0xE4)  /* Doorbells clear/debug register */
3888 +#define ARM_3_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN3+0xFC)  /* IRQS pending for owner 3 */
3889 +#define ARM_3_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN3+0xF8)  /* ALL interrupts */
3890 +
3891 +
3892 +
3893 +/*  Mailbox flags. Valid for all owners */
3894 +
3895 +/* Mailbox status register (...0x98) */
3896 +#define ARM_MS_FULL       0x80000000
3897 +#define ARM_MS_EMPTY      0x40000000
3898 +#define ARM_MS_LEVEL      0x400000FF /* Max. value depdnds on mailbox depth parameter */
3899 +
3900 +/* MAILBOX config/status register (...0x9C) */
3901 +/* ANY write to this register clears the error bits! */
3902 +#define ARM_MC_IHAVEDATAIRQEN    0x00000001 /* mailbox irq enable:  has data */
3903 +#define ARM_MC_IHAVESPACEIRQEN   0x00000002 /* mailbox irq enable:  has space */
3904 +#define ARM_MC_OPPISEMPTYIRQEN   0x00000004 /* mailbox irq enable: Opp. is empty */
3905 +#define ARM_MC_MAIL_CLEAR        0x00000008 /* mailbox clear write 1, then  0 */
3906 +#define ARM_MC_IHAVEDATAIRQPEND  0x00000010 /* mailbox irq pending:  has space */
3907 +#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
3908 +#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
3909 +/* Bit 7 is unused */
3910 +#define ARM_MC_ERRNOOWN   0x00000100 /* error : none owner read from mailbox */
3911 +#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
3912 +#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
3913 +
3914 +/* Semaphore clear/debug register (...0xE0) */
3915 +#define ARM_SD_OWN0      0x00000003  /* Owner of sem 0 */
3916 +#define ARM_SD_OWN1      0x0000000C  /* Owner of sem 1 */
3917 +#define ARM_SD_OWN2      0x00000030  /* Owner of sem 2 */
3918 +#define ARM_SD_OWN3      0x000000C0  /* Owner of sem 3 */
3919 +#define ARM_SD_OWN4      0x00000300  /* Owner of sem 4 */
3920 +#define ARM_SD_OWN5      0x00000C00  /* Owner of sem 5 */
3921 +#define ARM_SD_OWN6      0x00003000  /* Owner of sem 6 */
3922 +#define ARM_SD_OWN7      0x0000C000  /* Owner of sem 7 */
3923 +#define ARM_SD_SEM0      0x00010000  /* Status of sem 0 */
3924 +#define ARM_SD_SEM1      0x00020000  /* Status of sem 1 */
3925 +#define ARM_SD_SEM2      0x00040000  /* Status of sem 2 */
3926 +#define ARM_SD_SEM3      0x00080000  /* Status of sem 3 */
3927 +#define ARM_SD_SEM4      0x00100000  /* Status of sem 4 */
3928 +#define ARM_SD_SEM5      0x00200000  /* Status of sem 5 */
3929 +#define ARM_SD_SEM6      0x00400000  /* Status of sem 6 */
3930 +#define ARM_SD_SEM7      0x00800000  /* Status of sem 7 */
3931 +
3932 +/* Doorbells clear/debug register (...0xE4) */
3933 +#define ARM_BD_OWN0      0x00000003  /* Owner of doorbell 0 */
3934 +#define ARM_BD_OWN1      0x0000000C  /* Owner of doorbell 1 */
3935 +#define ARM_BD_OWN2      0x00000030  /* Owner of doorbell 2 */
3936 +#define ARM_BD_OWN3      0x000000C0  /* Owner of doorbell 3 */
3937 +#define ARM_BD_BELL0     0x00000100  /* Status of doorbell 0 */
3938 +#define ARM_BD_BELL1     0x00000200  /* Status of doorbell 1 */
3939 +#define ARM_BD_BELL2     0x00000400  /* Status of doorbell 2 */
3940 +#define ARM_BD_BELL3     0x00000800  /* Status of doorbell 3 */
3941 +
3942 +/* MY IRQS register (...0xF8) */
3943 +#define ARM_MYIRQ_BELL   0x00000001  /* This owner has a doorbell IRQ */
3944 +#define ARM_MYIRQ_MAIL   0x00000002  /* This owner has a mailbox  IRQ */
3945 +
3946 +/* ALL IRQS register (...0xF8) */
3947 +#define ARM_AIS_BELL0 0x00000001  /* Doorbell 0 IRQ pending */
3948 +#define ARM_AIS_BELL1 0x00000002  /* Doorbell 1 IRQ pending */
3949 +#define ARM_AIS_BELL2 0x00000004  /* Doorbell 2 IRQ pending */
3950 +#define ARM_AIS_BELL3 0x00000008  /* Doorbell 3 IRQ pending */
3951 +#define ARM_AIS0_HAVEDATA 0x00000010  /* MAIL 0 has data IRQ pending */
3952 +#define ARM_AIS0_HAVESPAC 0x00000020  /* MAIL 0 has space IRQ pending */
3953 +#define ARM_AIS0_OPPEMPTY 0x00000040  /* MAIL 0 opposite is empty IRQ */
3954 +#define ARM_AIS1_HAVEDATA 0x00000080  /* MAIL 1 has data IRQ pending */
3955 +#define ARM_AIS1_HAVESPAC 0x00000100  /* MAIL 1 has space IRQ pending */
3956 +#define ARM_AIS1_OPPEMPTY 0x00000200  /* MAIL 1 opposite is empty IRQ */
3957 +/* Note   that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
3958 +/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
3959 +/* */
3960 +/* ARM JTAG BASH */
3961 +/* */
3962 +#define AJB_BASE 0x7e2000c0
3963 +
3964 +#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
3965 +#define   AJB_BITS0    0x000000
3966 +#define   AJB_BITS4    0x000004
3967 +#define   AJB_BITS8    0x000008
3968 +#define   AJB_BITS12   0x00000C
3969 +#define   AJB_BITS16   0x000010
3970 +#define   AJB_BITS20   0x000014
3971 +#define   AJB_BITS24   0x000018
3972 +#define   AJB_BITS28   0x00001C
3973 +#define   AJB_BITS32   0x000020
3974 +#define   AJB_BITS34   0x000022
3975 +#define   AJB_OUT_MS   0x000040
3976 +#define   AJB_OUT_LS   0x000000
3977 +#define   AJB_INV_CLK  0x000080
3978 +#define   AJB_D0_RISE  0x000100
3979 +#define   AJB_D0_FALL  0x000000
3980 +#define   AJB_D1_RISE  0x000200
3981 +#define   AJB_D1_FALL  0x000000
3982 +#define   AJB_IN_RISE  0x000400
3983 +#define   AJB_IN_FALL  0x000000
3984 +#define   AJB_ENABLE   0x000800
3985 +#define   AJB_HOLD0    0x000000
3986 +#define   AJB_HOLD1    0x001000
3987 +#define   AJB_HOLD2    0x002000
3988 +#define   AJB_HOLD3    0x003000
3989 +#define   AJB_RESETN   0x004000
3990 +#define   AJB_CLKSHFT  16
3991 +#define   AJB_BUSY     0x80000000
3992 +#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
3993 +#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
3994 +#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
3995 +
3996 +#endif
3997 --- /dev/null
3998 +++ b/arch/arm/mach-bcm2708/include/mach/arm_power.h
3999 @@ -0,0 +1,60 @@
4000 +/*
4001 + *  linux/arch/arm/mach-bcm2708/include/mach/arm_power.h
4002 + *
4003 + *  Copyright (C) 2010 Broadcom
4004 + *
4005 + * This program is free software; you can redistribute it and/or modify
4006 + * it under the terms of the GNU General Public License as published by
4007 + * the Free Software Foundation; either version 2 of the License, or
4008 + * (at your option) any later version.
4009 + *
4010 + * This program is distributed in the hope that it will be useful,
4011 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4012 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4013 + * GNU General Public License for more details.
4014 + *
4015 + * You should have received a copy of the GNU General Public License
4016 + * along with this program; if not, write to the Free Software
4017 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
4018 + */
4019 +
4020 +#ifndef _ARM_POWER_H
4021 +#define _ARM_POWER_H
4022 +
4023 +/* Use meaningful names on each side */
4024 +#ifdef __VIDEOCORE__
4025 +#define PREFIX(x) ARM_##x
4026 +#else
4027 +#define PREFIX(x) BCM_##x
4028 +#endif
4029 +
4030 +enum {
4031 +       PREFIX(POWER_SDCARD_BIT),
4032 +       PREFIX(POWER_UART_BIT),
4033 +       PREFIX(POWER_MINIUART_BIT),
4034 +       PREFIX(POWER_USB_BIT),
4035 +       PREFIX(POWER_I2C0_BIT),
4036 +       PREFIX(POWER_I2C1_BIT),
4037 +       PREFIX(POWER_I2C2_BIT),
4038 +       PREFIX(POWER_SPI_BIT),
4039 +       PREFIX(POWER_CCP2TX_BIT),
4040 +
4041 +       PREFIX(POWER_MAX)
4042 +};
4043 +
4044 +enum {
4045 +       PREFIX(POWER_SDCARD) = (1 << PREFIX(POWER_SDCARD_BIT)),
4046 +       PREFIX(POWER_UART) = (1 << PREFIX(POWER_UART_BIT)),
4047 +       PREFIX(POWER_MINIUART) = (1 << PREFIX(POWER_MINIUART_BIT)),
4048 +       PREFIX(POWER_USB) = (1 << PREFIX(POWER_USB_BIT)),
4049 +       PREFIX(POWER_I2C0) = (1 << PREFIX(POWER_I2C0_BIT)),
4050 +       PREFIX(POWER_I2C1_MASK) = (1 << PREFIX(POWER_I2C1_BIT)),
4051 +       PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)),
4052 +       PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)),
4053 +       PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)),
4054 +
4055 +       PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1,
4056 +       PREFIX(POWER_NONE) = 0
4057 +};
4058 +
4059 +#endif
4060 --- /dev/null
4061 +++ b/arch/arm/mach-bcm2708/include/mach/clkdev.h
4062 @@ -0,0 +1,7 @@
4063 +#ifndef __ASM_MACH_CLKDEV_H
4064 +#define __ASM_MACH_CLKDEV_H
4065 +
4066 +#define __clk_get(clk) ({ 1; })
4067 +#define __clk_put(clk) do { } while (0)
4068 +
4069 +#endif
4070 --- /dev/null
4071 +++ b/arch/arm/mach-bcm2708/include/mach/debug-macro.S
4072 @@ -0,0 +1,22 @@
4073 +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
4074 + *
4075 + * Debugging macro include header
4076 + *
4077 + *  Copyright (C) 2010 Broadcom
4078 + *  Copyright (C) 1994-1999 Russell King
4079 + *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
4080 + *
4081 + * This program is free software; you can redistribute it and/or modify
4082 + * it under the terms of the GNU General Public License version 2 as
4083 + * published by the Free Software Foundation.
4084 + *
4085 +*/
4086 +
4087 +#include <mach/platform.h>
4088 +
4089 +               .macro  addruart, rp, rv, tmp
4090 +               ldr     \rp, =UART0_BASE
4091 +               ldr     \rv, =IO_ADDRESS(UART0_BASE)
4092 +               .endm
4093 +
4094 +#include <asm/hardware/debug-pl01x.S>
4095 --- /dev/null
4096 +++ b/arch/arm/mach-bcm2708/include/mach/dma.h
4097 @@ -0,0 +1,86 @@
4098 +/*
4099 + *  linux/arch/arm/mach-bcm2708/include/mach/dma.h
4100 + *
4101 + *  Copyright (C) 2010 Broadcom
4102 + *
4103 + * This program is free software; you can redistribute it and/or modify
4104 + * it under the terms of the GNU General Public License version 2 as
4105 + * published by the Free Software Foundation.
4106 + */
4107 +
4108 +
4109 +#ifndef _MACH_BCM2708_DMA_H
4110 +#define _MACH_BCM2708_DMA_H
4111 +
4112 +#define BCM_DMAMAN_DRIVER_NAME "bcm2708_dma"
4113 +
4114 +/* DMA CS Control and Status bits */
4115 +#define BCM2708_DMA_ACTIVE     (1 << 0)
4116 +#define BCM2708_DMA_INT                (1 << 2)
4117 +#define BCM2708_DMA_ISPAUSED   (1 << 4)  /* Pause requested or not active */
4118 +#define BCM2708_DMA_ISHELD     (1 << 5)  /* Is held by DREQ flow control */
4119 +#define BCM2708_DMA_ERR                (1 << 8)
4120 +#define BCM2708_DMA_ABORT      (1 << 30) /* stop current CB, go to next, WO */
4121 +#define BCM2708_DMA_RESET      (1 << 31) /* WO, self clearing */
4122 +
4123 +/* DMA control block "info" field bits */
4124 +#define BCM2708_DMA_INT_EN     (1 << 0)
4125 +#define BCM2708_DMA_TDMODE     (1 << 1)
4126 +#define BCM2708_DMA_WAIT_RESP  (1 << 3)
4127 +#define BCM2708_DMA_D_INC      (1 << 4)
4128 +#define BCM2708_DMA_D_WIDTH    (1 << 5)
4129 +#define BCM2708_DMA_D_DREQ     (1 << 6)
4130 +#define BCM2708_DMA_S_INC      (1 << 8)
4131 +#define BCM2708_DMA_S_WIDTH    (1 << 9)
4132 +#define BCM2708_DMA_S_DREQ     (1 << 10)
4133 +
4134 +#define        BCM2708_DMA_BURST(x)    (((x)&0xf) << 12)
4135 +#define        BCM2708_DMA_PER_MAP(x)  ((x) << 16)
4136 +#define        BCM2708_DMA_WAITS(x)    (((x)&0x1f) << 21)
4137 +
4138 +#define BCM2708_DMA_DREQ_EMMC  11
4139 +#define BCM2708_DMA_DREQ_SDHOST        13
4140 +
4141 +#define BCM2708_DMA_CS         0x00 /* Control and Status */
4142 +#define BCM2708_DMA_ADDR       0x04
4143 +/* the current control block appears in the following registers - read only */
4144 +#define BCM2708_DMA_INFO       0x08
4145 +#define BCM2708_DMA_NEXTCB     0x1C
4146 +#define BCM2708_DMA_DEBUG      0x20
4147 +
4148 +#define BCM2708_DMA4_CS                (BCM2708_DMA_CHAN(4)+BCM2708_DMA_CS)
4149 +#define BCM2708_DMA4_ADDR      (BCM2708_DMA_CHAN(4)+BCM2708_DMA_ADDR)
4150 +
4151 +#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
4152 +
4153 +struct bcm2708_dma_cb {
4154 +       unsigned long info;
4155 +       unsigned long src;
4156 +       unsigned long dst;
4157 +       unsigned long length;
4158 +       unsigned long stride;
4159 +       unsigned long next;
4160 +       unsigned long pad[2];
4161 +};
4162 +
4163 +extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
4164 +extern void bcm_dma_start(void __iomem *dma_chan_base,
4165 +                         dma_addr_t control_block);
4166 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base);
4167 +extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base);
4168 +
4169 +/* When listing features we can ask for when allocating DMA channels give
4170 +   those with higher priority smaller ordinal numbers */
4171 +#define BCM_DMA_FEATURE_FAST_ORD 0
4172 +#define BCM_DMA_FEATURE_BULK_ORD 1
4173 +#define BCM_DMA_FEATURE_FAST    (1<<BCM_DMA_FEATURE_FAST_ORD)
4174 +#define BCM_DMA_FEATURE_BULK    (1<<BCM_DMA_FEATURE_BULK_ORD)
4175 +#define BCM_DMA_FEATURE_COUNT   2
4176 +
4177 +/* return channel no or -ve error */
4178 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
4179 +                             void __iomem **out_dma_base, int *out_dma_irq);
4180 +extern int bcm_dma_chan_free(int channel);
4181 +
4182 +
4183 +#endif /* _MACH_BCM2708_DMA_H */
4184 --- /dev/null
4185 +++ b/arch/arm/mach-bcm2708/include/mach/entry-macro.S
4186 @@ -0,0 +1,69 @@
4187 +/*
4188 + * arch/arm/mach-bcm2708/include/mach/entry-macro.S
4189 + *
4190 + * Low-level IRQ helper macros for BCM2708 platforms
4191 + *
4192 + *  Copyright (C) 2010 Broadcom
4193 + *
4194 + * This program is free software; you can redistribute it and/or modify
4195 + * it under the terms of the GNU General Public License as published by
4196 + * the Free Software Foundation; either version 2 of the License, or
4197 + * (at your option) any later version.
4198 + *
4199 + * This program is distributed in the hope that it will be useful,
4200 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4201 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4202 + * GNU General Public License for more details.
4203 + *
4204 + * You should have received a copy of the GNU General Public License
4205 + * along with this program; if not, write to the Free Software
4206 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
4207 + */
4208 +#include <mach/hardware.h>
4209 +
4210 +               .macro  disable_fiq
4211 +               .endm
4212 +
4213 +               .macro  get_irqnr_preamble, base, tmp
4214 +               ldr     \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
4215 +               .endm
4216 +
4217 +               .macro  arch_ret_to_user, tmp1, tmp2
4218 +               .endm
4219 +
4220 +               .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
4221 +               /* get masked status */
4222 +               ldr     \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
4223 +               mov     \irqnr, #(ARM_IRQ0_BASE + 31)
4224 +               and     \tmp, \irqstat, #0x300           @ save bits 8 and 9
4225 +               /* clear bits 8 and 9, and test */
4226 +               bics    \irqstat, \irqstat, #0x300
4227 +               bne     1010f
4228 +
4229 +               tst     \tmp, #0x100
4230 +               ldrne   \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
4231 +               movne \irqnr, #(ARM_IRQ1_BASE + 31)
4232 +               @ Mask out the interrupts also present in PEND0 - see SW-5809
4233 +               bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
4234 +               bicne \irqstat, #((1<<18) | (1<<19))
4235 +               bne     1010f
4236 +
4237 +               tst     \tmp, #0x200
4238 +               ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
4239 +               movne \irqnr, #(ARM_IRQ2_BASE + 31)
4240 +               @ Mask out the interrupts also present in PEND0 - see SW-5809
4241 +               bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
4242 +               bicne \irqstat, #((1<<30))
4243 +               beq 1020f
4244 +
4245 +1010:
4246 +               @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
4247 +               @ N.B. CLZ is an ARM5 instruction.
4248 +               sub     \tmp, \irqstat, #1
4249 +               eor     \irqstat, \irqstat, \tmp
4250 +               clz     \tmp, \irqstat
4251 +               sub     \irqnr, \tmp
4252 +
4253 +1020:  @ EQ will be set if no irqs pending
4254 +
4255 +               .endm
4256 --- /dev/null
4257 +++ b/arch/arm/mach-bcm2708/include/mach/frc.h
4258 @@ -0,0 +1,38 @@
4259 +/*
4260 + *  arch/arm/mach-bcm2708/include/mach/timex.h
4261 + *
4262 + *  BCM2708 free running counter (timer)
4263 + *
4264 + *  Copyright (C) 2010 Broadcom
4265 + *
4266 + * This program is free software; you can redistribute it and/or modify
4267 + * it under the terms of the GNU General Public License as published by
4268 + * the Free Software Foundation; either version 2 of the License, or
4269 + * (at your option) any later version.
4270 + *
4271 + * This program is distributed in the hope that it will be useful,
4272 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4273 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4274 + * GNU General Public License for more details.
4275 + *
4276 + * You should have received a copy of the GNU General Public License
4277 + * along with this program; if not, write to the Free Software
4278 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
4279 + */
4280 +
4281 +#ifndef _MACH_FRC_H
4282 +#define _MACH_FRC_H
4283 +
4284 +#define FRC_TICK_RATE          (1000000)
4285 +
4286 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
4287 +    (slightly faster than frc_clock_ticks63()
4288 + */
4289 +extern unsigned long frc_clock_ticks32(void);
4290 +
4291 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
4292 + *  Note - top bit should be ignored (see cnt32_to_63)
4293 + */
4294 +extern unsigned long long frc_clock_ticks63(void);
4295 +
4296 +#endif
4297 --- /dev/null
4298 +++ b/arch/arm/mach-bcm2708/include/mach/gpio.h
4299 @@ -0,0 +1,18 @@
4300 +/*
4301 + * arch/arm/mach-bcm2708/include/mach/gpio.h
4302 + *
4303 + * This file is licensed under the terms of the GNU General Public
4304 + * License version 2.  This program is licensed "as is" without any
4305 + * warranty of any kind, whether express or implied.
4306 + */
4307 +
4308 +#ifndef __ASM_ARCH_GPIO_H
4309 +#define __ASM_ARCH_GPIO_H
4310 +
4311 +#define ARCH_NR_GPIOS 54 // number of gpio lines
4312 +
4313 +#define gpio_to_irq(x) ((x) + GPIO_IRQ_START)
4314 +#define irq_to_gpio(x) ((x) - GPIO_IRQ_START)
4315 +
4316 +#endif
4317 +
4318 --- /dev/null
4319 +++ b/arch/arm/mach-bcm2708/include/mach/hardware.h
4320 @@ -0,0 +1,28 @@
4321 +/*
4322 + *  arch/arm/mach-bcm2708/include/mach/hardware.h
4323 + *
4324 + *  This file contains the hardware definitions of the BCM2708 devices.
4325 + *
4326 + *  Copyright (C) 2010 Broadcom
4327 + *
4328 + * This program is free software; you can redistribute it and/or modify
4329 + * it under the terms of the GNU General Public License as published by
4330 + * the Free Software Foundation; either version 2 of the License, or
4331 + * (at your option) any later version.
4332 + *
4333 + * This program is distributed in the hope that it will be useful,
4334 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4335 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4336 + * GNU General Public License for more details.
4337 + *
4338 + * You should have received a copy of the GNU General Public License
4339 + * along with this program; if not, write to the Free Software
4340 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
4341 + */
4342 +#ifndef __ASM_ARCH_HARDWARE_H
4343 +#define __ASM_ARCH_HARDWARE_H
4344 +
4345 +#include <asm/sizes.h>
4346 +#include <mach/platform.h>
4347 +
4348 +#endif
4349 --- /dev/null
4350 +++ b/arch/arm/mach-bcm2708/include/mach/io.h
4351 @@ -0,0 +1,27 @@
4352 +/*
4353 + *  arch/arm/mach-bcm2708/include/mach/io.h
4354 + *
4355 + *  Copyright (C) 2003 ARM Limited
4356 + *
4357 + * This program is free software; you can redistribute it and/or modify
4358 + * it under the terms of the GNU General Public License as published by
4359 + * the Free Software Foundation; either version 2 of the License, or
4360 + * (at your option) any later version.
4361 + *
4362 + * This program is distributed in the hope that it will be useful,
4363 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4364 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4365 + * GNU General Public License for more details.
4366 + *
4367 + * You should have received a copy of the GNU General Public License
4368 + * along with this program; if not, write to the Free Software
4369 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
4370 + */
4371 +#ifndef __ASM_ARM_ARCH_IO_H
4372 +#define __ASM_ARM_ARCH_IO_H
4373 +
4374 +#define IO_SPACE_LIMIT 0xffffffff
4375 +
4376 +#define __io(a)                __typesafe_io(a)
4377 +
4378 +#endif
4379 --- /dev/null
4380 +++ b/arch/arm/mach-bcm2708/include/mach/irqs.h
4381 @@ -0,0 +1,196 @@
4382 +/*
4383 + *  arch/arm/mach-bcm2708/include/mach/irqs.h
4384 + *
4385 + *  Copyright (C) 2010 Broadcom
4386 + *  Copyright (C) 2003 ARM Limited
4387 + *  Copyright (C) 2000 Deep Blue Solutions Ltd.
4388 + *
4389 + * This program is free software; you can redistribute it and/or modify
4390 + * it under the terms of the GNU General Public License as published by
4391 + * the Free Software Foundation; either version 2 of the License, or
4392 + * (at your option) any later version.
4393 + *
4394 + * This program is distributed in the hope that it will be useful,
4395 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4396 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4397 + * GNU General Public License for more details.
4398 + *
4399 + * You should have received a copy of the GNU General Public License
4400 + * along with this program; if not, write to the Free Software
4401 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
4402 + */
4403 +
4404 +#ifndef _BCM2708_IRQS_H_
4405 +#define _BCM2708_IRQS_H_
4406 +
4407 +#include <mach/platform.h>
4408 +
4409 +/*
4410 + *  IRQ interrupts definitions are the same as the INT definitions
4411 + *  held within platform.h
4412 + */
4413 +#define IRQ_ARMCTRL_START     0
4414 +#define IRQ_TIMER0            (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
4415 +#define IRQ_TIMER1            (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
4416 +#define IRQ_TIMER2            (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
4417 +#define IRQ_TIMER3            (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
4418 +#define IRQ_CODEC0            (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
4419 +#define IRQ_CODEC1            (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
4420 +#define IRQ_CODEC2            (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
4421 +#define IRQ_JPEG              (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
4422 +#define IRQ_ISP               (IRQ_ARMCTRL_START + INTERRUPT_ISP)
4423 +#define IRQ_USB               (IRQ_ARMCTRL_START + INTERRUPT_USB)
4424 +#define IRQ_3D                (IRQ_ARMCTRL_START + INTERRUPT_3D)
4425 +#define IRQ_TRANSPOSER        (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
4426 +#define IRQ_MULTICORESYNC0    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
4427 +#define IRQ_MULTICORESYNC1    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
4428 +#define IRQ_MULTICORESYNC2    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
4429 +#define IRQ_MULTICORESYNC3    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
4430 +#define IRQ_DMA0              (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
4431 +#define IRQ_DMA1              (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
4432 +#define IRQ_DMA2              (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
4433 +#define IRQ_DMA3              (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
4434 +#define IRQ_DMA4              (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
4435 +#define IRQ_DMA5              (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
4436 +#define IRQ_DMA6              (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
4437 +#define IRQ_DMA7              (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
4438 +#define IRQ_DMA8              (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
4439 +#define IRQ_DMA9              (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
4440 +#define IRQ_DMA10             (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
4441 +#define IRQ_DMA11             (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
4442 +#define IRQ_DMA12             (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
4443 +#define IRQ_AUX               (IRQ_ARMCTRL_START + INTERRUPT_AUX)
4444 +#define IRQ_ARM               (IRQ_ARMCTRL_START + INTERRUPT_ARM)
4445 +#define IRQ_VPUDMA            (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
4446 +#define IRQ_HOSTPORT          (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
4447 +#define IRQ_VIDEOSCALER       (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
4448 +#define IRQ_CCP2TX            (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
4449 +#define IRQ_SDC               (IRQ_ARMCTRL_START + INTERRUPT_SDC)
4450 +#define IRQ_DSI0              (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
4451 +#define IRQ_AVE               (IRQ_ARMCTRL_START + INTERRUPT_AVE)
4452 +#define IRQ_CAM0              (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
4453 +#define IRQ_CAM1              (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
4454 +#define IRQ_HDMI0             (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
4455 +#define IRQ_HDMI1             (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
4456 +#define IRQ_PIXELVALVE1       (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
4457 +#define IRQ_I2CSPISLV         (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
4458 +#define IRQ_DSI1              (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
4459 +#define IRQ_PWA0              (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
4460 +#define IRQ_PWA1              (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
4461 +#define IRQ_CPR               (IRQ_ARMCTRL_START + INTERRUPT_CPR)
4462 +#define IRQ_SMI               (IRQ_ARMCTRL_START + INTERRUPT_SMI)
4463 +#define IRQ_GPIO0             (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
4464 +#define IRQ_GPIO1             (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
4465 +#define IRQ_GPIO2             (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
4466 +#define IRQ_GPIO3             (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
4467 +#define IRQ_I2C               (IRQ_ARMCTRL_START + INTERRUPT_I2C)
4468 +#define IRQ_SPI               (IRQ_ARMCTRL_START + INTERRUPT_SPI)
4469 +#define IRQ_I2SPCM            (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
4470 +#define IRQ_SDIO              (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
4471 +#define IRQ_UART              (IRQ_ARMCTRL_START + INTERRUPT_UART)
4472 +#define IRQ_SLIMBUS           (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
4473 +#define IRQ_VEC               (IRQ_ARMCTRL_START + INTERRUPT_VEC)
4474 +#define IRQ_CPG               (IRQ_ARMCTRL_START + INTERRUPT_CPG)
4475 +#define IRQ_RNG               (IRQ_ARMCTRL_START + INTERRUPT_RNG)
4476 +#define IRQ_ARASANSDIO        (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
4477 +#define IRQ_AVSPMON           (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
4478 +
4479 +#define IRQ_ARM_TIMER         (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
4480 +#define IRQ_ARM_MAILBOX       (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
4481 +#define IRQ_ARM_DOORBELL_0    (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
4482 +#define IRQ_ARM_DOORBELL_1    (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
4483 +#define IRQ_VPU0_HALTED       (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
4484 +#define IRQ_VPU1_HALTED       (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
4485 +#define IRQ_ILLEGAL_TYPE0     (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
4486 +#define IRQ_ILLEGAL_TYPE1     (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
4487 +#define IRQ_PENDING1          (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
4488 +#define IRQ_PENDING2          (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
4489 +
4490 +/*
4491 + *  FIQ interrupts definitions are the same as the INT definitions.
4492 + */
4493 +#define FIQ_TIMER0            INT_TIMER0
4494 +#define FIQ_TIMER1            INT_TIMER1
4495 +#define FIQ_TIMER2            INT_TIMER2
4496 +#define FIQ_TIMER3            INT_TIMER3
4497 +#define FIQ_CODEC0            INT_CODEC0
4498 +#define FIQ_CODEC1            INT_CODEC1
4499 +#define FIQ_CODEC2            INT_CODEC2
4500 +#define FIQ_JPEG              INT_JPEG
4501 +#define FIQ_ISP               INT_ISP
4502 +#define FIQ_USB               INT_USB
4503 +#define FIQ_3D                INT_3D
4504 +#define FIQ_TRANSPOSER        INT_TRANSPOSER
4505 +#define FIQ_MULTICORESYNC0    INT_MULTICORESYNC0
4506 +#define FIQ_MULTICORESYNC1    INT_MULTICORESYNC1
4507 +#define FIQ_MULTICORESYNC2    INT_MULTICORESYNC2
4508 +#define FIQ_MULTICORESYNC3    INT_MULTICORESYNC3
4509 +#define FIQ_DMA0              INT_DMA0
4510 +#define FIQ_DMA1              INT_DMA1
4511 +#define FIQ_DMA2              INT_DMA2
4512 +#define FIQ_DMA3              INT_DMA3
4513 +#define FIQ_DMA4              INT_DMA4
4514 +#define FIQ_DMA5              INT_DMA5
4515 +#define FIQ_DMA6              INT_DMA6
4516 +#define FIQ_DMA7              INT_DMA7
4517 +#define FIQ_DMA8              INT_DMA8
4518 +#define FIQ_DMA9              INT_DMA9
4519 +#define FIQ_DMA10             INT_DMA10
4520 +#define FIQ_DMA11             INT_DMA11
4521 +#define FIQ_DMA12             INT_DMA12
4522 +#define FIQ_AUX               INT_AUX
4523 +#define FIQ_ARM               INT_ARM
4524 +#define FIQ_VPUDMA            INT_VPUDMA
4525 +#define FIQ_HOSTPORT          INT_HOSTPORT
4526 +#define FIQ_VIDEOSCALER       INT_VIDEOSCALER
4527 +#define FIQ_CCP2TX            INT_CCP2TX
4528 +#define FIQ_SDC               INT_SDC
4529 +#define FIQ_DSI0              INT_DSI0
4530 +#define FIQ_AVE               INT_AVE
4531 +#define FIQ_CAM0              INT_CAM0
4532 +#define FIQ_CAM1              INT_CAM1
4533 +#define FIQ_HDMI0             INT_HDMI0
4534 +#define FIQ_HDMI1             INT_HDMI1
4535 +#define FIQ_PIXELVALVE1       INT_PIXELVALVE1
4536 +#define FIQ_I2CSPISLV         INT_I2CSPISLV
4537 +#define FIQ_DSI1              INT_DSI1
4538 +#define FIQ_PWA0              INT_PWA0
4539 +#define FIQ_PWA1              INT_PWA1
4540 +#define FIQ_CPR               INT_CPR
4541 +#define FIQ_SMI               INT_SMI
4542 +#define FIQ_GPIO0             INT_GPIO0
4543 +#define FIQ_GPIO1             INT_GPIO1
4544 +#define FIQ_GPIO2             INT_GPIO2
4545 +#define FIQ_GPIO3             INT_GPIO3
4546 +#define FIQ_I2C               INT_I2C
4547 +#define FIQ_SPI               INT_SPI
4548 +#define FIQ_I2SPCM            INT_I2SPCM
4549 +#define FIQ_SDIO              INT_SDIO
4550 +#define FIQ_UART              INT_UART
4551 +#define FIQ_SLIMBUS           INT_SLIMBUS
4552 +#define FIQ_VEC               INT_VEC
4553 +#define FIQ_CPG               INT_CPG
4554 +#define FIQ_RNG               INT_RNG
4555 +#define FIQ_ARASANSDIO        INT_ARASANSDIO
4556 +#define FIQ_AVSPMON           INT_AVSPMON
4557 +
4558 +#define FIQ_ARM_TIMER         INT_ARM_TIMER
4559 +#define FIQ_ARM_MAILBOX       INT_ARM_MAILBOX
4560 +#define FIQ_ARM_DOORBELL_0    INT_ARM_DOORBELL_0
4561 +#define FIQ_ARM_DOORBELL_1    INT_ARM_DOORBELL_1
4562 +#define FIQ_VPU0_HALTED       INT_VPU0_HALTED
4563 +#define FIQ_VPU1_HALTED       INT_VPU1_HALTED
4564 +#define FIQ_ILLEGAL_TYPE0     INT_ILLEGAL_TYPE0
4565 +#define FIQ_ILLEGAL_TYPE1     INT_ILLEGAL_TYPE1
4566 +#define FIQ_PENDING1          INT_PENDING1
4567 +#define FIQ_PENDING2          INT_PENDING2
4568 +
4569 +#define HARD_IRQS            (64 + 21)
4570 +#define GPIO_IRQ_START       HARD_IRQS
4571 +
4572 +#define GPIO_IRQS            32*5
4573 +
4574 +#define NR_IRQS                      HARD_IRQS+GPIO_IRQS
4575 +
4576 +
4577 +#endif /* _BCM2708_IRQS_H_ */
4578 --- /dev/null
4579 +++ b/arch/arm/mach-bcm2708/include/mach/memory.h
4580 @@ -0,0 +1,57 @@
4581 +/*
4582 + *  arch/arm/mach-bcm2708/include/mach/memory.h
4583 + *
4584 + *  Copyright (C) 2010 Broadcom
4585 + *
4586 + * This program is free software; you can redistribute it and/or modify
4587 + * it under the terms of the GNU General Public License as published by
4588 + * the Free Software Foundation; either version 2 of the License, or
4589 + * (at your option) any later version.
4590 + *
4591 + * This program is distributed in the hope that it will be useful,
4592 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4593 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4594 + * GNU General Public License for more details.
4595 + *
4596 + * You should have received a copy of the GNU General Public License
4597 + * along with this program; if not, write to the Free Software
4598 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
4599 + */
4600 +#ifndef __ASM_ARCH_MEMORY_H
4601 +#define __ASM_ARCH_MEMORY_H
4602 +
4603 +/* Memory overview:
4604 +
4605 +   [ARMcore] <--virtual addr-->
4606 +   [ARMmmu] <--physical addr-->
4607 +   [GERTmap] <--bus add-->
4608 +   [VCperiph]
4609 +
4610 +*/
4611 +
4612 +/*
4613 + * Physical DRAM offset.
4614 + */
4615 +#define PLAT_PHYS_OFFSET       UL(0x00000000)
4616 +#define VC_ARMMEM_OFFSET       UL(0x00000000)   /* offset in VC of ARM memory */
4617 +
4618 +#ifdef CONFIG_BCM2708_NOL2CACHE
4619 + #define _REAL_BUS_OFFSET UL(0xC0000000)   /* don't use L1 or L2 caches */
4620 +#else
4621 + #define _REAL_BUS_OFFSET UL(0x40000000)   /* use L2 cache */
4622 +#endif
4623 +
4624 +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
4625 + * will provide the offset into this area as well as setting the bits that
4626 + * stop the L1 and L2 cache from being used
4627 + *
4628 + * WARNING: this only works because the ARM is given memory at a fixed location
4629 + *          (ARMMEM_OFFSET)
4630 + */
4631 +#define BUS_OFFSET          (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
4632 +#define __virt_to_bus(x)    ((x) + (BUS_OFFSET - PAGE_OFFSET))
4633 +#define __bus_to_virt(x)    ((x) - (BUS_OFFSET - PAGE_OFFSET))
4634 +#define __pfn_to_bus(x)     (__pfn_to_phys(x) + (BUS_OFFSET - PLAT_PHYS_OFFSET))
4635 +#define __bus_to_pfn(x)     __phys_to_pfn((x) - (BUS_OFFSET - PLAT_PHYS_OFFSET))
4636 +
4637 +#endif
4638 --- /dev/null
4639 +++ b/arch/arm/mach-bcm2708/include/mach/platform.h
4640 @@ -0,0 +1,220 @@
4641 +/*
4642 + * arch/arm/mach-bcm2708/include/mach/platform.h
4643 + *
4644 + * Copyright (C) 2010 Broadcom
4645 + *
4646 + * This program is free software; you can redistribute it and/or modify
4647 + * it under the terms of the GNU General Public License as published by
4648 + * the Free Software Foundation; either version 2 of the License, or
4649 + * (at your option) any later version.
4650 + *
4651 + * This program is distributed in the hope that it will be useful,
4652 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4653 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4654 + * GNU General Public License for more details.
4655 + *
4656 + * You should have received a copy of the GNU General Public License
4657 + * along with this program; if not, write to the Free Software
4658 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
4659 + */
4660 +
4661 +#ifndef _BCM2708_PLATFORM_H
4662 +#define _BCM2708_PLATFORM_H
4663 +
4664 +
4665 +/* macros to get at IO space when running virtually */
4666 +#define IO_ADDRESS(x)  (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
4667 +
4668 +#define __io_address(n)     IOMEM(IO_ADDRESS(n))
4669 +
4670 +
4671 +/*
4672 + *  SDRAM
4673 + */
4674 +#define BCM2708_SDRAM_BASE           0x00000000
4675 +
4676 +/*
4677 + *  Logic expansion modules
4678 + *
4679 + */
4680 +
4681 +
4682 +/* ------------------------------------------------------------------------
4683 + *  BCM2708 ARMCTRL Registers
4684 + * ------------------------------------------------------------------------
4685 + */
4686 +
4687 +#define HW_REGISTER_RW(addr) (addr)
4688 +#define HW_REGISTER_RO(addr) (addr)
4689 +
4690 +#include "arm_control.h"
4691 +#undef ARM_BASE
4692 +
4693 +/*
4694 + * Definitions and addresses for the ARM CONTROL logic
4695 + * This file is manually generated.
4696 + */
4697 +
4698 +#define BCM2708_PERI_BASE        0x20000000
4699 +#define ST_BASE                  (BCM2708_PERI_BASE + 0x3000)   /* System Timer */
4700 +#define DMA_BASE                (BCM2708_PERI_BASE + 0x7000)   /* DMA controller */
4701 +#define ARM_BASE                 (BCM2708_PERI_BASE + 0xB000)   /* BCM2708 ARM control block */
4702 +#define PM_BASE                         (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
4703 +#define GPIO_BASE                (BCM2708_PERI_BASE + 0x200000) /* GPIO */
4704 +#define UART0_BASE               (BCM2708_PERI_BASE + 0x201000)        /* Uart 0 */
4705 +#define MMCI0_BASE               (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
4706 +#define UART1_BASE               (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
4707 +#define EMMC_BASE                (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
4708 +#define SMI_BASE                (BCM2708_PERI_BASE + 0x600000) /* SMI */
4709 +#define USB_BASE                 (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
4710 +#define MCORE_BASE               (BCM2708_PERI_BASE + 0x0000)   /* Fake frame buffer device (actually the multicore sync block*/
4711 +
4712 +#define ARMCTRL_BASE             (ARM_BASE + 0x000)
4713 +#define ARMCTRL_IC_BASE          (ARM_BASE + 0x200)           /* ARM interrupt controller */
4714 +#define ARMCTRL_TIMER0_1_BASE    (ARM_BASE + 0x400)           /* Timer 0 and 1 */
4715 +#define ARMCTRL_0_SBM_BASE       (ARM_BASE + 0x800)           /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
4716 +
4717 +
4718 +/*
4719 + * Interrupt assignments
4720 + */
4721 +
4722 +#define ARM_IRQ1_BASE                  0
4723 +#define INTERRUPT_TIMER0               (ARM_IRQ1_BASE + 0)
4724 +#define INTERRUPT_TIMER1               (ARM_IRQ1_BASE + 1)
4725 +#define INTERRUPT_TIMER2               (ARM_IRQ1_BASE + 2)
4726 +#define INTERRUPT_TIMER3               (ARM_IRQ1_BASE + 3)
4727 +#define INTERRUPT_CODEC0               (ARM_IRQ1_BASE + 4)
4728 +#define INTERRUPT_CODEC1               (ARM_IRQ1_BASE + 5)
4729 +#define INTERRUPT_CODEC2               (ARM_IRQ1_BASE + 6)
4730 +#define INTERRUPT_VC_JPEG              (ARM_IRQ1_BASE + 7)
4731 +#define INTERRUPT_ISP                  (ARM_IRQ1_BASE + 8)
4732 +#define INTERRUPT_VC_USB               (ARM_IRQ1_BASE + 9)
4733 +#define INTERRUPT_VC_3D                (ARM_IRQ1_BASE + 10)
4734 +#define INTERRUPT_TRANSPOSER           (ARM_IRQ1_BASE + 11)
4735 +#define INTERRUPT_MULTICORESYNC0       (ARM_IRQ1_BASE + 12)
4736 +#define INTERRUPT_MULTICORESYNC1       (ARM_IRQ1_BASE + 13)
4737 +#define INTERRUPT_MULTICORESYNC2       (ARM_IRQ1_BASE + 14)
4738 +#define INTERRUPT_MULTICORESYNC3       (ARM_IRQ1_BASE + 15)
4739 +#define INTERRUPT_DMA0                 (ARM_IRQ1_BASE + 16)
4740 +#define INTERRUPT_DMA1                 (ARM_IRQ1_BASE + 17)
4741 +#define INTERRUPT_VC_DMA2              (ARM_IRQ1_BASE + 18)
4742 +#define INTERRUPT_VC_DMA3              (ARM_IRQ1_BASE + 19)
4743 +#define INTERRUPT_DMA4                 (ARM_IRQ1_BASE + 20)
4744 +#define INTERRUPT_DMA5                 (ARM_IRQ1_BASE + 21)
4745 +#define INTERRUPT_DMA6                 (ARM_IRQ1_BASE + 22)
4746 +#define INTERRUPT_DMA7                 (ARM_IRQ1_BASE + 23)
4747 +#define INTERRUPT_DMA8                 (ARM_IRQ1_BASE + 24)
4748 +#define INTERRUPT_DMA9                 (ARM_IRQ1_BASE + 25)
4749 +#define INTERRUPT_DMA10                (ARM_IRQ1_BASE + 26)
4750 +#define INTERRUPT_DMA11                (ARM_IRQ1_BASE + 27)
4751 +#define INTERRUPT_DMA12                (ARM_IRQ1_BASE + 28)
4752 +#define INTERRUPT_AUX                (ARM_IRQ1_BASE + 29)
4753 +#define INTERRUPT_ARM                  (ARM_IRQ1_BASE + 30)
4754 +#define INTERRUPT_VPUDMA               (ARM_IRQ1_BASE + 31)
4755 +
4756 +#define ARM_IRQ2_BASE                  32
4757 +#define INTERRUPT_HOSTPORT             (ARM_IRQ2_BASE + 0)
4758 +#define INTERRUPT_VIDEOSCALER          (ARM_IRQ2_BASE + 1)
4759 +#define INTERRUPT_CCP2TX               (ARM_IRQ2_BASE + 2)
4760 +#define INTERRUPT_SDC                  (ARM_IRQ2_BASE + 3)
4761 +#define INTERRUPT_DSI0                 (ARM_IRQ2_BASE + 4)
4762 +#define INTERRUPT_AVE                  (ARM_IRQ2_BASE + 5)
4763 +#define INTERRUPT_CAM0                 (ARM_IRQ2_BASE + 6)
4764 +#define INTERRUPT_CAM1                 (ARM_IRQ2_BASE + 7)
4765 +#define INTERRUPT_HDMI0                (ARM_IRQ2_BASE + 8)
4766 +#define INTERRUPT_HDMI1                (ARM_IRQ2_BASE + 9)
4767 +#define INTERRUPT_PIXELVALVE1          (ARM_IRQ2_BASE + 10)
4768 +#define INTERRUPT_I2CSPISLV            (ARM_IRQ2_BASE + 11)
4769 +#define INTERRUPT_DSI1                 (ARM_IRQ2_BASE + 12)
4770 +#define INTERRUPT_PWA0                 (ARM_IRQ2_BASE + 13)
4771 +#define INTERRUPT_PWA1                 (ARM_IRQ2_BASE + 14)
4772 +#define INTERRUPT_CPR                  (ARM_IRQ2_BASE + 15)
4773 +#define INTERRUPT_SMI                  (ARM_IRQ2_BASE + 16)
4774 +#define INTERRUPT_GPIO0                (ARM_IRQ2_BASE + 17)
4775 +#define INTERRUPT_GPIO1                (ARM_IRQ2_BASE + 18)
4776 +#define INTERRUPT_GPIO2                (ARM_IRQ2_BASE + 19)
4777 +#define INTERRUPT_GPIO3                (ARM_IRQ2_BASE + 20)
4778 +#define INTERRUPT_VC_I2C               (ARM_IRQ2_BASE + 21)
4779 +#define INTERRUPT_VC_SPI               (ARM_IRQ2_BASE + 22)
4780 +#define INTERRUPT_VC_I2SPCM            (ARM_IRQ2_BASE + 23)
4781 +#define INTERRUPT_VC_SDIO              (ARM_IRQ2_BASE + 24)
4782 +#define INTERRUPT_VC_UART              (ARM_IRQ2_BASE + 25)
4783 +#define INTERRUPT_SLIMBUS              (ARM_IRQ2_BASE + 26)
4784 +#define INTERRUPT_VEC                  (ARM_IRQ2_BASE + 27)
4785 +#define INTERRUPT_CPG                  (ARM_IRQ2_BASE + 28)
4786 +#define INTERRUPT_RNG                  (ARM_IRQ2_BASE + 29)
4787 +#define INTERRUPT_VC_ARASANSDIO        (ARM_IRQ2_BASE + 30)
4788 +#define INTERRUPT_AVSPMON              (ARM_IRQ2_BASE + 31)
4789 +
4790 +#define ARM_IRQ0_BASE                  64
4791 +#define INTERRUPT_ARM_TIMER            (ARM_IRQ0_BASE + 0)
4792 +#define INTERRUPT_ARM_MAILBOX          (ARM_IRQ0_BASE + 1)
4793 +#define INTERRUPT_ARM_DOORBELL_0       (ARM_IRQ0_BASE + 2)
4794 +#define INTERRUPT_ARM_DOORBELL_1       (ARM_IRQ0_BASE + 3)
4795 +#define INTERRUPT_VPU0_HALTED          (ARM_IRQ0_BASE + 4)
4796 +#define INTERRUPT_VPU1_HALTED          (ARM_IRQ0_BASE + 5)
4797 +#define INTERRUPT_ILLEGAL_TYPE0        (ARM_IRQ0_BASE + 6)
4798 +#define INTERRUPT_ILLEGAL_TYPE1        (ARM_IRQ0_BASE + 7)
4799 +#define INTERRUPT_PENDING1             (ARM_IRQ0_BASE + 8)
4800 +#define INTERRUPT_PENDING2             (ARM_IRQ0_BASE + 9)
4801 +#define INTERRUPT_JPEG                 (ARM_IRQ0_BASE + 10)
4802 +#define INTERRUPT_USB                  (ARM_IRQ0_BASE + 11)
4803 +#define INTERRUPT_3D                   (ARM_IRQ0_BASE + 12)
4804 +#define INTERRUPT_DMA2                 (ARM_IRQ0_BASE + 13)
4805 +#define INTERRUPT_DMA3                 (ARM_IRQ0_BASE + 14)
4806 +#define INTERRUPT_I2C                  (ARM_IRQ0_BASE + 15)
4807 +#define INTERRUPT_SPI                  (ARM_IRQ0_BASE + 16)
4808 +#define INTERRUPT_I2SPCM               (ARM_IRQ0_BASE + 17)
4809 +#define INTERRUPT_SDIO                 (ARM_IRQ0_BASE + 18)
4810 +#define INTERRUPT_UART                 (ARM_IRQ0_BASE + 19)
4811 +#define INTERRUPT_ARASANSDIO           (ARM_IRQ0_BASE + 20)
4812 +
4813 +#define MAXIRQNUM                      (32 + 32 + 20)
4814 +#define MAXFIQNUM                      (32 + 32 + 20)
4815 +
4816 +#define MAX_TIMER                       2
4817 +#define MAX_PERIOD                      699050
4818 +#define TICKS_PER_uSEC                  1
4819 +
4820 +/*
4821 + *  These are useconds NOT ticks.
4822 + *
4823 + */
4824 +#define mSEC_1                          1000
4825 +#define mSEC_5                          (mSEC_1 * 5)
4826 +#define mSEC_10                         (mSEC_1 * 10)
4827 +#define mSEC_25                         (mSEC_1 * 25)
4828 +#define SEC_1                           (mSEC_1 * 1000)
4829 +
4830 +/*
4831 + * Watchdog
4832 + */
4833 +#define PM_RSTC                               (PM_BASE+0x1c)
4834 +#define PM_RSTS                               (PM_BASE+0x20)
4835 +#define PM_WDOG                               (PM_BASE+0x24)
4836 +
4837 +#define PM_WDOG_RESET                                         0000000000
4838 +#define PM_PASSWORD                   0x5a000000
4839 +#define PM_WDOG_TIME_SET              0x000fffff
4840 +#define PM_RSTC_WRCFG_CLR              0xffffffcf
4841 +#define PM_RSTC_WRCFG_SET              0x00000030
4842 +#define PM_RSTC_WRCFG_FULL_RESET       0x00000020
4843 +#define PM_RSTC_RESET                  0x00000102
4844 +
4845 +#define PM_RSTS_HADPOR_SET                                 0x00001000
4846 +#define PM_RSTS_HADSRH_SET                                 0x00000400
4847 +#define PM_RSTS_HADSRF_SET                                 0x00000200
4848 +#define PM_RSTS_HADSRQ_SET                                 0x00000100
4849 +#define PM_RSTS_HADWRH_SET                                 0x00000040
4850 +#define PM_RSTS_HADWRF_SET                                 0x00000020
4851 +#define PM_RSTS_HADWRQ_SET                                 0x00000010
4852 +#define PM_RSTS_HADDRH_SET                                 0x00000004
4853 +#define PM_RSTS_HADDRF_SET                                 0x00000002
4854 +#define PM_RSTS_HADDRQ_SET                                 0x00000001
4855 +
4856 +#define UART0_CLOCK      3000000
4857 +
4858 +#endif
4859 +
4860 +/* END */
4861 --- /dev/null
4862 +++ b/arch/arm/mach-bcm2708/include/mach/power.h
4863 @@ -0,0 +1,26 @@
4864 +/*
4865 + *  linux/arch/arm/mach-bcm2708/power.h
4866 + *
4867 + *  Copyright (C) 2010 Broadcom
4868 + *
4869 + * This program is free software; you can redistribute it and/or modify
4870 + * it under the terms of the GNU General Public License version 2 as
4871 + * published by the Free Software Foundation.
4872 + *
4873 + * This device provides a shared mechanism for controlling the power to
4874 + * VideoCore subsystems.
4875 + */
4876 +
4877 +#ifndef _MACH_BCM2708_POWER_H
4878 +#define _MACH_BCM2708_POWER_H
4879 +
4880 +#include <linux/types.h>
4881 +#include <mach/arm_power.h>
4882 +
4883 +typedef unsigned int BCM_POWER_HANDLE_T;
4884 +
4885 +extern int bcm_power_open(BCM_POWER_HANDLE_T *handle);
4886 +extern int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request);
4887 +extern int bcm_power_close(BCM_POWER_HANDLE_T handle);
4888 +
4889 +#endif
4890 --- /dev/null
4891 +++ b/arch/arm/mach-bcm2708/include/mach/system.h
4892 @@ -0,0 +1,38 @@
4893 +/*
4894 + *  arch/arm/mach-bcm2708/include/mach/system.h
4895 + *
4896 + *  Copyright (C) 2010 Broadcom
4897 + *  Copyright (C) 2003 ARM Limited
4898 + *  Copyright (C) 2000 Deep Blue Solutions Ltd
4899 + *
4900 + * This program is free software; you can redistribute it and/or modify
4901 + * it under the terms of the GNU General Public License as published by
4902 + * the Free Software Foundation; either version 2 of the License, or
4903 + * (at your option) any later version.
4904 + *
4905 + * This program is distributed in the hope that it will be useful,
4906 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4907 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4908 + * GNU General Public License for more details.
4909 + *
4910 + * You should have received a copy of the GNU General Public License
4911 + * along with this program; if not, write to the Free Software
4912 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
4913 + */
4914 +#ifndef __ASM_ARCH_SYSTEM_H
4915 +#define __ASM_ARCH_SYSTEM_H
4916 +
4917 +#include <linux/io.h>
4918 +#include <mach/hardware.h>
4919 +#include <mach/platform.h>
4920 +
4921 +static inline void arch_idle(void)
4922 +{
4923 +       /*
4924 +        * This should do all the clock switching
4925 +        * and wait for interrupt tricks
4926 +        */
4927 +       cpu_do_idle();
4928 +}
4929 +
4930 +#endif
4931 --- /dev/null
4932 +++ b/arch/arm/mach-bcm2708/include/mach/timex.h
4933 @@ -0,0 +1,23 @@
4934 +/*
4935 + *  arch/arm/mach-bcm2708/include/mach/timex.h
4936 + *
4937 + *  BCM2708 sysem clock frequency
4938 + *
4939 + *  Copyright (C) 2010 Broadcom
4940 + *
4941 + * This program is free software; you can redistribute it and/or modify
4942 + * it under the terms of the GNU General Public License as published by
4943 + * the Free Software Foundation; either version 2 of the License, or
4944 + * (at your option) any later version.
4945 + *
4946 + * This program is distributed in the hope that it will be useful,
4947 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4948 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4949 + * GNU General Public License for more details.
4950 + *
4951 + * You should have received a copy of the GNU General Public License
4952 + * along with this program; if not, write to the Free Software
4953 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
4954 + */
4955 +
4956 +#define CLOCK_TICK_RATE                (1000000)
4957 --- /dev/null
4958 +++ b/arch/arm/mach-bcm2708/include/mach/uncompress.h
4959 @@ -0,0 +1,85 @@
4960 +/*
4961 + *  arch/arm/mach-bcn2708/include/mach/uncompress.h
4962 + *
4963 + *  Copyright (C) 2010 Broadcom
4964 + *  Copyright (C) 2003 ARM Limited
4965 + *
4966 + * This program is free software; you can redistribute it and/or modify
4967 + * it under the terms of the GNU General Public License as published by
4968 + * the Free Software Foundation; either version 2 of the License, or
4969 + * (at your option) any later version.
4970 + *
4971 + * This program is distributed in the hope that it will be useful,
4972 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4973 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4974 + * GNU General Public License for more details.
4975 + *
4976 + * You should have received a copy of the GNU General Public License
4977 + * along with this program; if not, write to the Free Software
4978 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
4979 + */
4980 +
4981 +#include <linux/io.h>
4982 +#include <linux/amba/serial.h>
4983 +#include <mach/hardware.h>
4984 +
4985 +#define UART_BAUD 115200
4986 +
4987 +#define BCM2708_UART_DR   __io(UART0_BASE + UART01x_DR)
4988 +#define BCM2708_UART_FR   __io(UART0_BASE + UART01x_FR)
4989 +#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
4990 +#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
4991 +#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
4992 +#define BCM2708_UART_CR   __io(UART0_BASE + UART011_CR)
4993 +
4994 +/*
4995 + * This does not append a newline
4996 + */
4997 +static inline void putc(int c)
4998 +{
4999 +       while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
5000 +               barrier();
5001 +
5002 +       __raw_writel(c, BCM2708_UART_DR);
5003 +}
5004 +
5005 +static inline void flush(void)
5006 +{
5007 +       int fr;
5008 +
5009 +       do {
5010 +               fr = __raw_readl(BCM2708_UART_FR);
5011 +               barrier();
5012 +       } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
5013 +}
5014 +
5015 +static inline void arch_decomp_setup(void)
5016 +{
5017 +       int temp, div, rem, frac;
5018 +
5019 +       temp = 16 * UART_BAUD;
5020 +       div = UART0_CLOCK / temp;
5021 +       rem = UART0_CLOCK % temp;
5022 +       temp = (8 * rem) / UART_BAUD;
5023 +       frac = (temp >> 1) + (temp & 1);
5024 +
5025 +       /* Make sure the UART is disabled before we start */
5026 +       __raw_writel(0, BCM2708_UART_CR);
5027 +
5028 +       /* Set the baud rate */
5029 +       __raw_writel(div, BCM2708_UART_IBRD);
5030 +       __raw_writel(frac, BCM2708_UART_FBRD);
5031 +
5032 +       /* Set the UART to 8n1, FIFO enabled */
5033 +       __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
5034 +
5035 +       /* Enable the UART */
5036 +       __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
5037 +                       BCM2708_UART_CR);
5038 +}
5039 +
5040 +/*
5041 + * nothing to do
5042 + */
5043 +#define arch_decomp_wdog()
5044 +
5045 --- /dev/null
5046 +++ b/arch/arm/mach-bcm2708/include/mach/vc_mem.h
5047 @@ -0,0 +1,36 @@
5048 +/*****************************************************************************
5049 +* Copyright 2010 - 2011 Broadcom Corporation.  All rights reserved.
5050 +*
5051 +* Unless you and Broadcom execute a separate written software license
5052 +* agreement governing use of this software, this software is licensed to you
5053 +* under the terms of the GNU General Public License version 2, available at
5054 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
5055 +*
5056 +* Notwithstanding the above, under no circumstances may you combine this
5057 +* software in any way with any other Broadcom software provided under a
5058 +* license other than the GPL, without Broadcom's express prior written
5059 +* consent.
5060 +*****************************************************************************/
5061 +
5062 +#if !defined( VC_MEM_H )
5063 +#define VC_MEM_H
5064 +
5065 +#include <linux/ioctl.h>
5066 +
5067 +#define VC_MEM_IOC_MAGIC  'v'
5068 +
5069 +#define VC_MEM_IOC_MEM_PHYS_ADDR    _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
5070 +#define VC_MEM_IOC_MEM_SIZE         _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
5071 +#define VC_MEM_IOC_MEM_BASE         _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
5072 +#define VC_MEM_IOC_MEM_LOAD         _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
5073 +
5074 +#if defined( __KERNEL__ )
5075 +#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
5076 +
5077 +extern unsigned long mm_vc_mem_phys_addr;
5078 +extern unsigned int  mm_vc_mem_size;
5079 +extern int vc_mem_get_current_size( void );
5080 +#endif
5081 +
5082 +#endif  /* VC_MEM_H */
5083 +
5084 --- /dev/null
5085 +++ b/arch/arm/mach-bcm2708/include/mach/vcio.h
5086 @@ -0,0 +1,141 @@
5087 +/*
5088 + *  arch/arm/mach-bcm2708/include/mach/vcio.h
5089 + *
5090 + *  Copyright (C) 2010 Broadcom
5091 + *
5092 + * This program is free software; you can redistribute it and/or modify
5093 + * it under the terms of the GNU General Public License as published by
5094 + * the Free Software Foundation; either version 2 of the License, or
5095 + * (at your option) any later version.
5096 + *
5097 + * This program is distributed in the hope that it will be useful,
5098 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5099 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5100 + * GNU General Public License for more details.
5101 + *
5102 + * You should have received a copy of the GNU General Public License
5103 + * along with this program; if not, write to the Free Software
5104 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5105 + */
5106 +#ifndef _MACH_BCM2708_VCIO_H
5107 +#define _MACH_BCM2708_VCIO_H
5108 +
5109 +/* Routines to handle I/O via the VideoCore "ARM control" registers
5110 + * (semaphores, doorbells, mailboxes)
5111 + */
5112 +
5113 +#define BCM_VCIO_DRIVER_NAME "bcm2708_vcio"
5114 +
5115 +/* Constants shared with the ARM identifying separate mailbox channels */
5116 +#define MBOX_CHAN_POWER    0 /* for use by the power management interface */
5117 +#define MBOX_CHAN_FB       1 /* for use by the frame buffer */
5118 +#define MBOX_CHAN_VCHIQ    3 /* for use by the VCHIQ interface */
5119 +#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */
5120 +#define MBOX_CHAN_COUNT    9
5121 +
5122 +/* Mailbox property tags */
5123 +enum {
5124 +       VCMSG_PROPERTY_END               = 0x00000000,
5125 +       VCMSG_GET_FIRMWARE_REVISION      = 0x00000001,
5126 +       VCMSG_GET_BOARD_MODEL            = 0x00010001,
5127 +       VCMSG_GET_BOARD_REVISION         = 0x00020002,
5128 +       VCMSG_GET_BOARD_MAC_ADDRESS      = 0x00020003,
5129 +       VCMSG_GET_BOARD_SERIAL           = 0x00020004,
5130 +       VCMSG_GET_ARM_MEMORY             = 0x00020005,
5131 +       VCMSG_GET_VC_MEMORY              = 0x00020006,
5132 +       VCMSG_GET_CLOCKS                 = 0x00020007,
5133 +       VCMSG_GET_COMMAND_LINE           = 0x00050001,
5134 +       VCMSG_GET_DMA_CHANNELS           = 0x00060001,
5135 +       VCMSG_GET_POWER_STATE            = 0x00020001,
5136 +       VCMSG_GET_TIMING                 = 0x00020002,
5137 +       VCMSG_SET_POWER_STATE            = 0x00028001,
5138 +       VCMSG_GET_CLOCK_STATE            = 0x00030001,
5139 +       VCMSG_SET_CLOCK_STATE            = 0x00038001,
5140 +       VCMSG_GET_CLOCK_RATE             = 0x00030002,
5141 +       VCMSG_SET_CLOCK_RATE             = 0x00038002,
5142 +       VCMSG_GET_VOLTAGE                = 0x00030003,
5143 +       VCMSG_SET_VOLTAGE                = 0x00038003,
5144 +       VCMSG_GET_MAX_CLOCK              = 0x00030004,
5145 +       VCMSG_GET_MAX_VOLTAGE            = 0x00030005,
5146 +       VCMSG_GET_TEMPERATURE            = 0x00030006,
5147 +       VCMSG_GET_MIN_CLOCK              = 0x00030007,
5148 +       VCMSG_GET_MIN_VOLTAGE            = 0x00030008,
5149 +       VCMSG_GET_TURBO                  = 0x00030009,
5150 +       VCMSG_SET_TURBO                  = 0x00038009,
5151 +       VCMSG_SET_ALLOCATE_BUFFER        = 0x00040001,
5152 +       VCMSG_SET_RELEASE_BUFFER         = 0x00048001,
5153 +       VCMSG_SET_BLANK_SCREEN           = 0x00040002,
5154 +       VCMSG_TST_BLANK_SCREEN           = 0x00044002,
5155 +       VCMSG_GET_PHYSICAL_WIDTH_HEIGHT  = 0x00040003,
5156 +       VCMSG_TST_PHYSICAL_WIDTH_HEIGHT  = 0x00044003,
5157 +       VCMSG_SET_PHYSICAL_WIDTH_HEIGHT  = 0x00048003,
5158 +       VCMSG_GET_VIRTUAL_WIDTH_HEIGHT   = 0x00040004,
5159 +       VCMSG_TST_VIRTUAL_WIDTH_HEIGHT   = 0x00044004,
5160 +       VCMSG_SET_VIRTUAL_WIDTH_HEIGHT   = 0x00048004,
5161 +       VCMSG_GET_DEPTH                  = 0x00040005,
5162 +       VCMSG_TST_DEPTH                  = 0x00044005,
5163 +       VCMSG_SET_DEPTH                  = 0x00048005,
5164 +       VCMSG_GET_PIXEL_ORDER            = 0x00040006,
5165 +       VCMSG_TST_PIXEL_ORDER            = 0x00044006,
5166 +       VCMSG_SET_PIXEL_ORDER            = 0x00048006,
5167 +       VCMSG_GET_ALPHA_MODE             = 0x00040007,
5168 +       VCMSG_TST_ALPHA_MODE             = 0x00044007,
5169 +       VCMSG_SET_ALPHA_MODE             = 0x00048007,
5170 +       VCMSG_GET_PITCH                  = 0x00040008,
5171 +       VCMSG_TST_PITCH                  = 0x00044008,
5172 +       VCMSG_SET_PITCH                  = 0x00048008,
5173 +       VCMSG_GET_VIRTUAL_OFFSET         = 0x00040009,
5174 +       VCMSG_TST_VIRTUAL_OFFSET         = 0x00044009,
5175 +       VCMSG_SET_VIRTUAL_OFFSET         = 0x00048009,
5176 +       VCMSG_GET_OVERSCAN               = 0x0004000a,
5177 +       VCMSG_TST_OVERSCAN               = 0x0004400a,
5178 +       VCMSG_SET_OVERSCAN               = 0x0004800a,
5179 +       VCMSG_GET_PALETTE                = 0x0004000b,
5180 +       VCMSG_TST_PALETTE                = 0x0004400b,
5181 +       VCMSG_SET_PALETTE                = 0x0004800b,
5182 +       VCMSG_GET_LAYER                  = 0x0004000c,
5183 +       VCMSG_TST_LAYER                  = 0x0004400c,
5184 +       VCMSG_SET_LAYER                  = 0x0004800c,
5185 +       VCMSG_GET_TRANSFORM              = 0x0004000d,
5186 +       VCMSG_TST_TRANSFORM              = 0x0004400d,
5187 +       VCMSG_SET_TRANSFORM              = 0x0004800d,
5188 +};
5189 +
5190 +extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28);
5191 +extern int /*rc*/ bcm_mailbox_write(unsigned chan, uint32_t data28);
5192 +extern int /*rc*/ bcm_mailbox_property(void *data, int size);
5193 +
5194 +#include <linux/ioctl.h>
5195 +
5196 +/*
5197 + * The major device number. We can't rely on dynamic
5198 + * registration any more, because ioctls need to know
5199 + * it.
5200 + */
5201 +#define MAJOR_NUM 100
5202 +
5203 +/*
5204 + * Set the message of the device driver
5205 + */
5206 +#define IOCTL_MBOX_PROPERTY _IOWR(MAJOR_NUM, 0, char *)
5207 +/*
5208 + * _IOWR means that we're creating an ioctl command
5209 + * number for passing information from a user process
5210 + * to the kernel module and from the kernel module to user process
5211 + *
5212 + * The first arguments, MAJOR_NUM, is the major device
5213 + * number we're using.
5214 + *
5215 + * The second argument is the number of the command
5216 + * (there could be several with different meanings).
5217 + *
5218 + * The third argument is the type we want to get from
5219 + * the process to the kernel.
5220 + */
5221 +
5222 +/*
5223 + * The name of the device file
5224 + */
5225 +#define DEVICE_FILE_NAME "char_dev"
5226 +
5227 +#endif
5228 --- /dev/null
5229 +++ b/arch/arm/mach-bcm2708/include/mach/vmalloc.h
5230 @@ -0,0 +1,20 @@
5231 +/*
5232 + *  arch/arm/mach-bcm2708/include/mach/vmalloc.h
5233 + *
5234 + *  Copyright (C) 2010 Broadcom
5235 + *
5236 + * This program is free software; you can redistribute it and/or modify
5237 + * it under the terms of the GNU General Public License as published by
5238 + * the Free Software Foundation; either version 2 of the License, or
5239 + * (at your option) any later version.
5240 + *
5241 + * This program is distributed in the hope that it will be useful,
5242 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5243 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5244 + * GNU General Public License for more details.
5245 + *
5246 + * You should have received a copy of the GNU General Public License
5247 + * along with this program; if not, write to the Free Software
5248 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5249 + */
5250 +#define VMALLOC_END            (0xe8000000)
5251 --- /dev/null
5252 +++ b/arch/arm/mach-bcm2708/power.c
5253 @@ -0,0 +1,194 @@
5254 +/*
5255 + *      linux/arch/arm/mach-bcm2708/power.c
5256 + *
5257 + *      Copyright (C) 2010 Broadcom
5258 + *
5259 + * This program is free software; you can redistribute it and/or modify
5260 + * it under the terms of the GNU General Public License version 2 as
5261 + * published by the Free Software Foundation.
5262 + *
5263 + * This device provides a shared mechanism for controlling the power to
5264 + * VideoCore subsystems.
5265 + */
5266 +
5267 +#include <linux/module.h>
5268 +#include <linux/semaphore.h>
5269 +#include <linux/bug.h>
5270 +#include <mach/power.h>
5271 +#include <mach/vcio.h>
5272 +#include <mach/arm_power.h>
5273 +
5274 +#define DRIVER_NAME "bcm2708_power"
5275 +
5276 +#define BCM_POWER_MAXCLIENTS 4
5277 +#define BCM_POWER_NOCLIENT (1<<31)
5278 +
5279 +/* Some drivers expect there devices to be permanently powered */
5280 +#define BCM_POWER_ALWAYS_ON (BCM_POWER_USB)
5281 +
5282 +#if 1
5283 +#define DPRINTK printk
5284 +#else
5285 +#define DPRINTK if (0) printk
5286 +#endif
5287 +
5288 +struct state_struct {
5289 +       uint32_t global_request;
5290 +       uint32_t client_request[BCM_POWER_MAXCLIENTS];
5291 +       struct semaphore client_mutex;
5292 +       struct semaphore mutex;
5293 +} g_state;
5294 +
5295 +int bcm_power_open(BCM_POWER_HANDLE_T *handle)
5296 +{
5297 +       BCM_POWER_HANDLE_T i;
5298 +       int ret = -EBUSY;
5299 +
5300 +       down(&g_state.client_mutex);
5301 +
5302 +       for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
5303 +               if (g_state.client_request[i] == BCM_POWER_NOCLIENT) {
5304 +                       g_state.client_request[i] = BCM_POWER_NONE;
5305 +                       *handle = i;
5306 +                       ret = 0;
5307 +                       break;
5308 +               }
5309 +       }
5310 +
5311 +       up(&g_state.client_mutex);
5312 +
5313 +       DPRINTK("bcm_power_open() -> %d\n", *handle);
5314 +
5315 +       return ret;
5316 +}
5317 +EXPORT_SYMBOL_GPL(bcm_power_open);
5318 +
5319 +int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request)
5320 +{
5321 +       int rc = 0;
5322 +
5323 +       DPRINTK("bcm_power_request(%d, %x)\n", handle, request);
5324 +
5325 +       if ((handle < BCM_POWER_MAXCLIENTS) &&
5326 +           (g_state.client_request[handle] != BCM_POWER_NOCLIENT)) {
5327 +               if (down_interruptible(&g_state.mutex) != 0) {
5328 +                       DPRINTK("bcm_power_request -> interrupted\n");
5329 +                       return -EINTR;
5330 +               }
5331 +
5332 +               if (request != g_state.client_request[handle]) {
5333 +                       uint32_t others_request = 0;
5334 +                       uint32_t global_request;
5335 +                       BCM_POWER_HANDLE_T i;
5336 +
5337 +                       for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
5338 +                               if (i != handle)
5339 +                                       others_request |=
5340 +                                           g_state.client_request[i];
5341 +                       }
5342 +                       others_request &= ~BCM_POWER_NOCLIENT;
5343 +
5344 +                       global_request = request | others_request;
5345 +                       if (global_request != g_state.global_request) {
5346 +                               uint32_t actual;
5347 +
5348 +                               /* Send a request to VideoCore */
5349 +                               bcm_mailbox_write(MBOX_CHAN_POWER,
5350 +                                                 global_request << 4);
5351 +
5352 +                               /* Wait for a response during power-up */
5353 +                               if (global_request & ~g_state.global_request) {
5354 +                                       rc = bcm_mailbox_read(MBOX_CHAN_POWER,
5355 +                                                             &actual);
5356 +                                       DPRINTK
5357 +                                           ("bcm_mailbox_read -> %08x, %d\n",
5358 +                                            actual, rc);
5359 +                                       actual >>= 4;
5360 +                               } else {
5361 +                                       rc = 0;
5362 +                                       actual = global_request;
5363 +                               }
5364 +
5365 +                               if (rc == 0) {
5366 +                                       if (actual != global_request) {
5367 +                                               printk(KERN_ERR
5368 +                                                    "%s: prev global %x, new global %x, actual %x, request %x, others_request %x\n",
5369 +                                                    __func__,
5370 +                                                    g_state.global_request,
5371 +                                                    global_request, actual, request, others_request);
5372 +                                               /* A failure */
5373 +                                               BUG_ON((others_request & actual)
5374 +                                                      != others_request);
5375 +                                               request &= actual;
5376 +                                               rc = -EIO;
5377 +                                       }
5378 +
5379 +                                       g_state.global_request = actual;
5380 +                                       g_state.client_request[handle] =
5381 +                                           request;
5382 +                               }
5383 +                       }
5384 +               }
5385 +               up(&g_state.mutex);
5386 +       } else {
5387 +               rc = -EINVAL;
5388 +       }
5389 +       DPRINTK("bcm_power_request -> %d\n", rc);
5390 +       return rc;
5391 +}
5392 +EXPORT_SYMBOL_GPL(bcm_power_request);
5393 +
5394 +int bcm_power_close(BCM_POWER_HANDLE_T handle)
5395 +{
5396 +       int rc;
5397 +
5398 +       DPRINTK("bcm_power_close(%d)\n", handle);
5399 +
5400 +       rc = bcm_power_request(handle, BCM_POWER_NONE);
5401 +       if (rc == 0)
5402 +               g_state.client_request[handle] = BCM_POWER_NOCLIENT;
5403 +
5404 +       return rc;
5405 +}
5406 +EXPORT_SYMBOL_GPL(bcm_power_close);
5407 +
5408 +static int __init bcm_power_init(void)
5409 +{
5410 +#if defined(BCM_POWER_ALWAYS_ON)
5411 +       BCM_POWER_HANDLE_T always_on_handle;
5412 +#endif
5413 +       int rc = 0;
5414 +       int i;
5415 +
5416 +       printk(KERN_INFO "bcm_power: Broadcom power driver\n");
5417 +       bcm_mailbox_write(MBOX_CHAN_POWER, 0);
5418 +
5419 +       for (i = 0; i < BCM_POWER_MAXCLIENTS; i++)
5420 +               g_state.client_request[i] = BCM_POWER_NOCLIENT;
5421 +
5422 +       sema_init(&g_state.client_mutex, 1);
5423 +       sema_init(&g_state.mutex, 1);
5424 +
5425 +       g_state.global_request = 0;
5426 +
5427 +#if defined(BCM_POWER_ALWAYS_ON)
5428 +       if (BCM_POWER_ALWAYS_ON) {
5429 +               bcm_power_open(&always_on_handle);
5430 +               bcm_power_request(always_on_handle, BCM_POWER_ALWAYS_ON);
5431 +       }
5432 +#endif
5433 +
5434 +       return rc;
5435 +}
5436 +
5437 +static void __exit bcm_power_exit(void)
5438 +{
5439 +       bcm_mailbox_write(MBOX_CHAN_POWER, 0);
5440 +}
5441 +
5442 +arch_initcall(bcm_power_init); /* Initialize early */
5443 +module_exit(bcm_power_exit);
5444 +
5445 +MODULE_AUTHOR("Phil Elwell");
5446 +MODULE_DESCRIPTION("Interface to BCM2708 power management");
5447 +MODULE_LICENSE("GPL");
5448 --- /dev/null
5449 +++ b/arch/arm/mach-bcm2708/vc_mem.c
5450 @@ -0,0 +1,462 @@
5451 +/*****************************************************************************
5452 +* Copyright 2010 - 2011 Broadcom Corporation.  All rights reserved.
5453 +*
5454 +* Unless you and Broadcom execute a separate written software license
5455 +* agreement governing use of this software, this software is licensed to you
5456 +* under the terms of the GNU General Public License version 2, available at
5457 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
5458 +*
5459 +* Notwithstanding the above, under no circumstances may you combine this
5460 +* software in any way with any other Broadcom software provided under a
5461 +* license other than the GPL, without Broadcom's express prior written
5462 +* consent.
5463 +*****************************************************************************/
5464 +
5465 +#include <linux/kernel.h>
5466 +#include <linux/module.h>
5467 +#include <linux/fs.h>
5468 +#include <linux/device.h>
5469 +#include <linux/cdev.h>
5470 +#include <linux/mm.h>
5471 +#include <linux/slab.h>
5472 +#include <linux/proc_fs.h>
5473 +#include <asm/uaccess.h>
5474 +#include <linux/dma-mapping.h>
5475 +
5476 +#ifdef CONFIG_ARCH_KONA
5477 +#include <chal/chal_ipc.h>
5478 +#elif CONFIG_ARCH_BCM2708
5479 +#else
5480 +#include <csp/chal_ipc.h>
5481 +#endif
5482 +
5483 +#include "mach/vc_mem.h"
5484 +#include <mach/vcio.h>
5485 +
5486 +#define DRIVER_NAME  "vc-mem"
5487 +
5488 +// Uncomment to enable debug logging
5489 +// #define ENABLE_DBG
5490 +
5491 +#if defined(ENABLE_DBG)
5492 +#define LOG_DBG( fmt, ... )  printk( KERN_INFO fmt "\n", ##__VA_ARGS__ )
5493 +#else
5494 +#define LOG_DBG( fmt, ... )
5495 +#endif
5496 +#define LOG_ERR( fmt, ... )  printk( KERN_ERR fmt "\n", ##__VA_ARGS__ )
5497 +
5498 +// Device (/dev) related variables
5499 +static dev_t vc_mem_devnum = 0;
5500 +static struct class *vc_mem_class = NULL;
5501 +static struct cdev vc_mem_cdev;
5502 +static int vc_mem_inited = 0;
5503 +
5504 +// Proc entry
5505 +static struct proc_dir_entry *vc_mem_proc_entry;
5506 +
5507 +/*
5508 + * Videocore memory addresses and size
5509 + *
5510 + * Drivers that wish to know the videocore memory addresses and sizes should
5511 + * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
5512 + * headers. This allows the other drivers to not be tied down to a a certain
5513 + * address/size at compile time.
5514 + *
5515 + * In the future, the goal is to have the videocore memory virtual address and
5516 + * size be calculated at boot time rather than at compile time. The decision of
5517 + * where the videocore memory resides and its size would be in the hands of the
5518 + * bootloader (and/or kernel). When that happens, the values of these variables
5519 + * would be calculated and assigned in the init function.
5520 + */
5521 +// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
5522 +unsigned long mm_vc_mem_phys_addr = 0x00000000;
5523 +unsigned int mm_vc_mem_size = 0;
5524 +unsigned int mm_vc_mem_base = 0;
5525 +
5526 +EXPORT_SYMBOL(mm_vc_mem_phys_addr);
5527 +EXPORT_SYMBOL(mm_vc_mem_size);
5528 +EXPORT_SYMBOL(mm_vc_mem_base);
5529 +
5530 +static uint phys_addr = 0;
5531 +static uint mem_size = 0;
5532 +static uint mem_base = 0;
5533 +
5534 +
5535 +/****************************************************************************
5536 +*
5537 +*   vc_mem_open
5538 +*
5539 +***************************************************************************/
5540 +
5541 +static int
5542 +vc_mem_open(struct inode *inode, struct file *file)
5543 +{
5544 +       (void) inode;
5545 +       (void) file;
5546 +
5547 +       LOG_DBG("%s: called file = 0x%p", __func__, file);
5548 +
5549 +       return 0;
5550 +}
5551 +
5552 +/****************************************************************************
5553 +*
5554 +*   vc_mem_release
5555 +*
5556 +***************************************************************************/
5557 +
5558 +static int
5559 +vc_mem_release(struct inode *inode, struct file *file)
5560 +{
5561 +       (void) inode;
5562 +       (void) file;
5563 +
5564 +       LOG_DBG("%s: called file = 0x%p", __func__, file);
5565 +
5566 +       return 0;
5567 +}
5568 +
5569 +/****************************************************************************
5570 +*
5571 +*   vc_mem_get_size
5572 +*
5573 +***************************************************************************/
5574 +
5575 +static void
5576 +vc_mem_get_size(void)
5577 +{
5578 +}
5579 +
5580 +/****************************************************************************
5581 +*
5582 +*   vc_mem_get_base
5583 +*
5584 +***************************************************************************/
5585 +
5586 +static void
5587 +vc_mem_get_base(void)
5588 +{
5589 +}
5590 +
5591 +/****************************************************************************
5592 +*
5593 +*   vc_mem_get_current_size
5594 +*
5595 +***************************************************************************/
5596 +
5597 +int
5598 +vc_mem_get_current_size(void)
5599 +{
5600 +       return mm_vc_mem_size;
5601 +}
5602 +
5603 +EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
5604 +
5605 +/****************************************************************************
5606 +*
5607 +*   vc_mem_ioctl
5608 +*
5609 +***************************************************************************/
5610 +
5611 +static long
5612 +vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
5613 +{
5614 +       int rc = 0;
5615 +
5616 +       (void) cmd;
5617 +       (void) arg;
5618 +
5619 +       LOG_DBG("%s: called file = 0x%p", __func__, file);
5620 +
5621 +       switch (cmd) {
5622 +       case VC_MEM_IOC_MEM_PHYS_ADDR:
5623 +               {
5624 +                       LOG_DBG("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p",
5625 +                               __func__, (void *) mm_vc_mem_phys_addr);
5626 +
5627 +                       if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
5628 +                                        sizeof (mm_vc_mem_phys_addr)) != 0) {
5629 +                               rc = -EFAULT;
5630 +                       }
5631 +                       break;
5632 +               }
5633 +       case VC_MEM_IOC_MEM_SIZE:
5634 +               {
5635 +                       // Get the videocore memory size first
5636 +                       vc_mem_get_size();
5637 +
5638 +                       LOG_DBG("%s: VC_MEM_IOC_MEM_SIZE=%u", __func__,
5639 +                               mm_vc_mem_size);
5640 +
5641 +                       if (copy_to_user((void *) arg, &mm_vc_mem_size,
5642 +                                        sizeof (mm_vc_mem_size)) != 0) {
5643 +                               rc = -EFAULT;
5644 +                       }
5645 +                       break;
5646 +               }
5647 +       case VC_MEM_IOC_MEM_BASE:
5648 +               {
5649 +                       // Get the videocore memory base
5650 +                       vc_mem_get_base();
5651 +
5652 +                       LOG_DBG("%s: VC_MEM_IOC_MEM_BASE=%u", __func__,
5653 +                               mm_vc_mem_base);
5654 +
5655 +                       if (copy_to_user((void *) arg, &mm_vc_mem_base,
5656 +                                        sizeof (mm_vc_mem_base)) != 0) {
5657 +                               rc = -EFAULT;
5658 +                       }
5659 +                       break;
5660 +               }
5661 +       case VC_MEM_IOC_MEM_LOAD:
5662 +               {
5663 +                       // Get the videocore memory base
5664 +                       vc_mem_get_base();
5665 +
5666 +                       LOG_DBG("%s: VC_MEM_IOC_MEM_LOAD=%u", __func__,
5667 +                               mm_vc_mem_base);
5668 +
5669 +                       if (copy_to_user((void *) arg, &mm_vc_mem_base,
5670 +                                        sizeof (mm_vc_mem_base)) != 0) {
5671 +                               rc = -EFAULT;
5672 +                       }
5673 +                       break;
5674 +               }
5675 +       default:
5676 +               {
5677 +                       return -ENOTTY;
5678 +               }
5679 +       }
5680 +       LOG_DBG("%s: file = 0x%p returning %d", __func__, file, rc);
5681 +
5682 +       return rc;
5683 +}
5684 +
5685 +/****************************************************************************
5686 +*
5687 +*   vc_mem_mmap
5688 +*
5689 +***************************************************************************/
5690 +
5691 +static int
5692 +vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
5693 +{
5694 +       int rc = 0;
5695 +       unsigned long length = vma->vm_end - vma->vm_start;
5696 +       unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
5697 +
5698 +       LOG_DBG("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx",
5699 +               __func__, (long) vma->vm_start, (long) vma->vm_end,
5700 +               (long) vma->vm_pgoff);
5701 +
5702 +       if (offset + length > mm_vc_mem_size) {
5703 +               LOG_ERR("%s: length %ld is too big", __func__, length);
5704 +               return -EINVAL;
5705 +       }
5706 +       // Do not cache the memory map
5707 +       vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
5708 +
5709 +       rc = remap_pfn_range(vma, vma->vm_start,
5710 +                            (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
5711 +                            vma->vm_pgoff, length, vma->vm_page_prot);
5712 +       if (rc != 0) {
5713 +               LOG_ERR("%s: remap_pfn_range failed (rc=%d)", __func__, rc);
5714 +       }
5715 +
5716 +       return rc;
5717 +}
5718 +
5719 +/****************************************************************************
5720 +*
5721 +*   File Operations for the driver.
5722 +*
5723 +***************************************************************************/
5724 +
5725 +static const struct file_operations vc_mem_fops = {
5726 +       .owner = THIS_MODULE,
5727 +       .open = vc_mem_open,
5728 +       .release = vc_mem_release,
5729 +       .unlocked_ioctl = vc_mem_ioctl,
5730 +       .mmap = vc_mem_mmap,
5731 +};
5732 +
5733 +/****************************************************************************
5734 +*
5735 +*   vc_mem_proc_read
5736 +*
5737 +***************************************************************************/
5738 +
5739 +static int
5740 +vc_mem_proc_read(char *buf, char **start, off_t offset, int count, int *eof,
5741 +                void *data)
5742 +{
5743 +       char *p = buf;
5744 +
5745 +       (void) start;
5746 +       (void) count;
5747 +       (void) data;
5748 +
5749 +       if (offset > 0) {
5750 +               *eof = 1;
5751 +               return 0;
5752 +       }
5753 +       // Get the videocore memory size first
5754 +       vc_mem_get_size();
5755 +
5756 +       p += sprintf(p, "Videocore memory:\n");
5757 +       if (mm_vc_mem_phys_addr != 0)
5758 +               p += sprintf(p, "   Physical address: 0x%p\n",
5759 +                            (void *) mm_vc_mem_phys_addr);
5760 +       else
5761 +               p += sprintf(p, "   Physical address: 0x00000000\n");
5762 +       p += sprintf(p, "   Length (bytes):   %u\n", mm_vc_mem_size);
5763 +
5764 +       *eof = 1;
5765 +       return p - buf;
5766 +}
5767 +
5768 +/****************************************************************************
5769 +*
5770 +*   vc_mem_proc_write
5771 +*
5772 +***************************************************************************/
5773 +
5774 +static int
5775 +vc_mem_proc_write(struct file *file, const char __user * buffer,
5776 +                 unsigned long count, void *data)
5777 +{
5778 +       int rc = -EFAULT;
5779 +       char input_str[10];
5780 +
5781 +       memset(input_str, 0, sizeof (input_str));
5782 +
5783 +       if (count > sizeof (input_str)) {
5784 +               LOG_ERR("%s: input string length too long", __func__);
5785 +               goto out;
5786 +       }
5787 +
5788 +       if (copy_from_user(input_str, buffer, count - 1)) {
5789 +               LOG_ERR("%s: failed to get input string", __func__);
5790 +               goto out;
5791 +       }
5792 +
5793 +       if (strncmp(input_str, "connect", strlen("connect")) == 0) {
5794 +               // Get the videocore memory size from the videocore
5795 +               vc_mem_get_size();
5796 +       }
5797 +
5798 +      out:
5799 +       return rc;
5800 +}
5801 +
5802 +/****************************************************************************
5803 +*
5804 +*   vc_mem_init
5805 +*
5806 +***************************************************************************/
5807 +
5808 +static int __init
5809 +vc_mem_init(void)
5810 +{
5811 +       int rc = -EFAULT;
5812 +       struct device *dev;
5813 +
5814 +       LOG_DBG("%s: called", __func__);
5815 +
5816 +       mm_vc_mem_phys_addr = phys_addr;
5817 +       mm_vc_mem_size = mem_size;
5818 +       mm_vc_mem_base = mem_base;
5819 +
5820 +       vc_mem_get_size();
5821 +
5822 +       printk("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
5823 +               mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
5824 +
5825 +       if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
5826 +               LOG_ERR("%s: alloc_chrdev_region failed (rc=%d)", __func__, rc);
5827 +               goto out_err;
5828 +       }
5829 +
5830 +       cdev_init(&vc_mem_cdev, &vc_mem_fops);
5831 +       if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
5832 +               LOG_ERR("%s: cdev_add failed (rc=%d)", __func__, rc);
5833 +               goto out_unregister;
5834 +       }
5835 +
5836 +       vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
5837 +       if (IS_ERR(vc_mem_class)) {
5838 +               rc = PTR_ERR(vc_mem_class);
5839 +               LOG_ERR("%s: class_create failed (rc=%d)", __func__, rc);
5840 +               goto out_cdev_del;
5841 +       }
5842 +
5843 +       dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
5844 +                           DRIVER_NAME);
5845 +       if (IS_ERR(dev)) {
5846 +               rc = PTR_ERR(dev);
5847 +               LOG_ERR("%s: device_create failed (rc=%d)", __func__, rc);
5848 +               goto out_class_destroy;
5849 +       }
5850 +
5851 +#if 0
5852 +       vc_mem_proc_entry = create_proc_entry(DRIVER_NAME, 0444, NULL);
5853 +       if (vc_mem_proc_entry == NULL) {
5854 +               rc = -EFAULT;
5855 +               LOG_ERR("%s: create_proc_entry failed", __func__);
5856 +               goto out_device_destroy;
5857 +       }
5858 +       vc_mem_proc_entry->read_proc = vc_mem_proc_read;
5859 +       vc_mem_proc_entry->write_proc = vc_mem_proc_write;
5860 +#endif
5861 +
5862 +       vc_mem_inited = 1;
5863 +       return 0;
5864 +
5865 +      out_device_destroy:
5866 +       device_destroy(vc_mem_class, vc_mem_devnum);
5867 +
5868 +      out_class_destroy:
5869 +       class_destroy(vc_mem_class);
5870 +       vc_mem_class = NULL;
5871 +
5872 +      out_cdev_del:
5873 +       cdev_del(&vc_mem_cdev);
5874 +
5875 +      out_unregister:
5876 +       unregister_chrdev_region(vc_mem_devnum, 1);
5877 +
5878 +      out_err:
5879 +       return -1;
5880 +}
5881 +
5882 +/****************************************************************************
5883 +*
5884 +*   vc_mem_exit
5885 +*
5886 +***************************************************************************/
5887 +
5888 +static void __exit
5889 +vc_mem_exit(void)
5890 +{
5891 +       LOG_DBG("%s: called", __func__);
5892 +
5893 +       if (vc_mem_inited) {
5894 +#if 0
5895 +               remove_proc_entry(vc_mem_proc_entry->name, NULL);
5896 +#endif
5897 +               device_destroy(vc_mem_class, vc_mem_devnum);
5898 +               class_destroy(vc_mem_class);
5899 +               cdev_del(&vc_mem_cdev);
5900 +               unregister_chrdev_region(vc_mem_devnum, 1);
5901 +       }
5902 +}
5903 +
5904 +module_init(vc_mem_init);
5905 +module_exit(vc_mem_exit);
5906 +MODULE_LICENSE("GPL");
5907 +MODULE_AUTHOR("Broadcom Corporation");
5908 +
5909 +module_param(phys_addr, uint, 0644);
5910 +module_param(mem_size, uint, 0644);
5911 +module_param(mem_base, uint, 0644);
5912 +
5913 --- /dev/null
5914 +++ b/arch/arm/mach-bcm2708/vcio.c
5915 @@ -0,0 +1,474 @@
5916 +/*
5917 + *  linux/arch/arm/mach-bcm2708/vcio.c
5918 + *
5919 + *  Copyright (C) 2010 Broadcom
5920 + *
5921 + * This program is free software; you can redistribute it and/or modify
5922 + * it under the terms of the GNU General Public License version 2 as
5923 + * published by the Free Software Foundation.
5924 + *
5925 + * This device provides a shared mechanism for writing to the mailboxes,
5926 + * semaphores, doorbells etc. that are shared between the ARM and the
5927 + * VideoCore processor
5928 + */
5929 +
5930 +#if defined(CONFIG_SERIAL_BCM_MBOX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
5931 +#define SUPPORT_SYSRQ
5932 +#endif
5933 +
5934 +#include <linux/module.h>
5935 +#include <linux/console.h>
5936 +#include <linux/serial_core.h>
5937 +#include <linux/serial.h>
5938 +#include <linux/errno.h>
5939 +#include <linux/device.h>
5940 +#include <linux/init.h>
5941 +#include <linux/mm.h>
5942 +#include <linux/dma-mapping.h>
5943 +#include <linux/platform_device.h>
5944 +#include <linux/sysrq.h>
5945 +#include <linux/delay.h>
5946 +#include <linux/slab.h>
5947 +#include <linux/interrupt.h>
5948 +#include <linux/irq.h>
5949 +
5950 +#include <linux/io.h>
5951 +
5952 +#include <mach/vcio.h>
5953 +#include <mach/platform.h>
5954 +
5955 +#include <asm/uaccess.h>
5956 +
5957 +
5958 +#define DRIVER_NAME BCM_VCIO_DRIVER_NAME
5959 +
5960 +/* ----------------------------------------------------------------------
5961 + *     Mailbox
5962 + * -------------------------------------------------------------------- */
5963 +
5964 +/* offsets from a mail box base address */
5965 +#define MAIL_WRT       0x00    /* write - and next 4 words */
5966 +#define MAIL_RD                0x00    /* read - and next 4 words */
5967 +#define MAIL_POL       0x10    /* read without popping the fifo */
5968 +#define MAIL_SND       0x14    /* sender ID (bottom two bits) */
5969 +#define MAIL_STA       0x18    /* status */
5970 +#define MAIL_CNF       0x1C    /* configuration */
5971 +
5972 +#define MBOX_MSG(chan, data28)         (((data28) & ~0xf) | ((chan) & 0xf))
5973 +#define MBOX_MSG_LSB(chan, data28) (((data28) << 4) | ((chan) & 0xf))
5974 +#define MBOX_CHAN(msg)                 ((msg) & 0xf)
5975 +#define MBOX_DATA28(msg)               ((msg) & ~0xf)
5976 +#define MBOX_DATA28_LSB(msg)           (((uint32_t)msg) >> 4)
5977 +
5978 +#define MBOX_MAGIC 0xd0d0c0de
5979 +
5980 +struct vc_mailbox {
5981 +       struct device *dev;     /* parent device */
5982 +       void __iomem *status;
5983 +       void __iomem *config;
5984 +       void __iomem *read;
5985 +       void __iomem *write;
5986 +       uint32_t msg[MBOX_CHAN_COUNT];
5987 +       struct semaphore sema[MBOX_CHAN_COUNT];
5988 +       uint32_t magic;
5989 +};
5990 +
5991 +static void mbox_init(struct vc_mailbox *mbox_out, struct device *dev,
5992 +                     uint32_t addr_mbox)
5993 +{
5994 +       int i;
5995 +
5996 +       mbox_out->dev = dev;
5997 +       mbox_out->status = __io_address(addr_mbox + MAIL_STA);
5998 +       mbox_out->config = __io_address(addr_mbox + MAIL_CNF);
5999 +       mbox_out->read = __io_address(addr_mbox + MAIL_RD);
6000 +       /* Write to the other mailbox */
6001 +       mbox_out->write =
6002 +           __io_address((addr_mbox ^ ARM_0_MAIL0_WRT ^ ARM_0_MAIL1_WRT) +
6003 +                        MAIL_WRT);
6004 +
6005 +       for (i = 0; i < MBOX_CHAN_COUNT; i++) {
6006 +               mbox_out->msg[i] = 0;
6007 +               sema_init(&mbox_out->sema[i], 0);
6008 +       }
6009 +
6010 +       /* Enable the interrupt on data reception */
6011 +       writel(ARM_MC_IHAVEDATAIRQEN, mbox_out->config);
6012 +
6013 +       mbox_out->magic = MBOX_MAGIC;
6014 +}
6015 +
6016 +static int mbox_write(struct vc_mailbox *mbox, unsigned chan, uint32_t data28)
6017 +{
6018 +       int rc;
6019 +
6020 +       if (mbox->magic != MBOX_MAGIC)
6021 +               rc = -EINVAL;
6022 +       else {
6023 +               /* wait for the mailbox FIFO to have some space in it */
6024 +               while (0 != (readl(mbox->status) & ARM_MS_FULL))
6025 +                       cpu_relax();
6026 +
6027 +               writel(MBOX_MSG(chan, data28), mbox->write);
6028 +               rc = 0;
6029 +       }
6030 +       return rc;
6031 +}
6032 +
6033 +static int mbox_read(struct vc_mailbox *mbox, unsigned chan, uint32_t *data28)
6034 +{
6035 +       int rc;
6036 +
6037 +       if (mbox->magic != MBOX_MAGIC)
6038 +               rc = -EINVAL;
6039 +       else {
6040 +               down(&mbox->sema[chan]);
6041 +               *data28 = MBOX_DATA28(mbox->msg[chan]);
6042 +               mbox->msg[chan] = 0;
6043 +               rc = 0;
6044 +       }
6045 +       return rc;
6046 +}
6047 +
6048 +static irqreturn_t mbox_irq(int irq, void *dev_id)
6049 +{
6050 +       /* wait for the mailbox FIFO to have some data in it */
6051 +       struct vc_mailbox *mbox = (struct vc_mailbox *) dev_id;
6052 +       int status = readl(mbox->status);
6053 +       int ret = IRQ_NONE;
6054 +
6055 +       while (!(status & ARM_MS_EMPTY)) {
6056 +               uint32_t msg = readl(mbox->read);
6057 +               int chan = MBOX_CHAN(msg);
6058 +               if (chan < MBOX_CHAN_COUNT) {
6059 +                       if (mbox->msg[chan]) {
6060 +                               /* Overflow */
6061 +                               printk(KERN_ERR DRIVER_NAME
6062 +                                      ": mbox chan %d overflow - drop %08x\n",
6063 +                                      chan, msg);
6064 +                       } else {
6065 +                               mbox->msg[chan] = (msg | 0xf);
6066 +                               up(&mbox->sema[chan]);
6067 +                       }
6068 +               } else {
6069 +                       printk(KERN_ERR DRIVER_NAME
6070 +                              ": invalid channel selector (msg %08x)\n", msg);
6071 +               }
6072 +               ret = IRQ_HANDLED;
6073 +               status = readl(mbox->status);
6074 +       }
6075 +       return ret;
6076 +}
6077 +
6078 +static struct irqaction mbox_irqaction = {
6079 +       .name = "ARM Mailbox IRQ",
6080 +       .flags = IRQF_DISABLED | IRQF_IRQPOLL,
6081 +       .handler = mbox_irq,
6082 +};
6083 +
6084 +/* ----------------------------------------------------------------------
6085 + *     Mailbox Methods
6086 + * -------------------------------------------------------------------- */
6087 +
6088 +static struct device *mbox_dev;        /* we assume there's only one! */
6089 +
6090 +static int dev_mbox_write(struct device *dev, unsigned chan, uint32_t data28)
6091 +{
6092 +       int rc;
6093 +
6094 +       struct vc_mailbox *mailbox = dev_get_drvdata(dev);
6095 +       device_lock(dev);
6096 +       rc = mbox_write(mailbox, chan, data28);
6097 +       device_unlock(dev);
6098 +
6099 +       return rc;
6100 +}
6101 +
6102 +static int dev_mbox_read(struct device *dev, unsigned chan, uint32_t *data28)
6103 +{
6104 +       int rc;
6105 +
6106 +       struct vc_mailbox *mailbox = dev_get_drvdata(dev);
6107 +       device_lock(dev);
6108 +       rc = mbox_read(mailbox, chan, data28);
6109 +       device_unlock(dev);
6110 +
6111 +       return rc;
6112 +}
6113 +
6114 +extern int bcm_mailbox_write(unsigned chan, uint32_t data28)
6115 +{
6116 +       if (mbox_dev)
6117 +               return dev_mbox_write(mbox_dev, chan, data28);
6118 +       else
6119 +               return -ENODEV;
6120 +}
6121 +EXPORT_SYMBOL_GPL(bcm_mailbox_write);
6122 +
6123 +extern int bcm_mailbox_read(unsigned chan, uint32_t *data28)
6124 +{
6125 +       if (mbox_dev)
6126 +               return dev_mbox_read(mbox_dev, chan, data28);
6127 +       else
6128 +               return -ENODEV;
6129 +}
6130 +EXPORT_SYMBOL_GPL(bcm_mailbox_read);
6131 +
6132 +static void dev_mbox_register(const char *dev_name, struct device *dev)
6133 +{
6134 +       mbox_dev = dev;
6135 +}
6136 +
6137 +static int mbox_copy_from_user(void *dst, const void *src, int size)
6138 +{
6139 +       if ( (uint32_t)src < TASK_SIZE)
6140 +       {
6141 +               return copy_from_user(dst, src, size);
6142 +       }
6143 +       else
6144 +       {
6145 +               memcpy( dst, src, size );
6146 +               return 0;
6147 +       }
6148 +}
6149 +
6150 +static int mbox_copy_to_user(void *dst, const void *src, int size)
6151 +{
6152 +       if ( (uint32_t)dst < TASK_SIZE)
6153 +       {
6154 +               return copy_to_user(dst, src, size);
6155 +       }
6156 +       else
6157 +       {
6158 +               memcpy( dst, src, size );
6159 +               return 0;
6160 +       }
6161 +}
6162 +
6163 +static DEFINE_MUTEX(mailbox_lock);
6164 +extern int bcm_mailbox_property(void *data, int size)
6165 +{
6166 +       uint32_t success;
6167 +       dma_addr_t mem_bus;                             /* the memory address accessed from videocore */
6168 +       void *mem_kern;                                 /* the memory address accessed from driver */
6169 +       int s = 0;
6170 +
6171 +        mutex_lock(&mailbox_lock);
6172 +       /* allocate some memory for the messages communicating with GPU */
6173 +       mem_kern = dma_alloc_coherent(NULL, PAGE_ALIGN(size), &mem_bus, GFP_ATOMIC);
6174 +       if (mem_kern) {
6175 +               /* create the message */
6176 +               mbox_copy_from_user(mem_kern, data, size);
6177 +
6178 +               /* send the message */
6179 +               wmb();
6180 +               s = bcm_mailbox_write(MBOX_CHAN_PROPERTY, (uint32_t)mem_bus);
6181 +               if (s == 0) {
6182 +                       s = bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success);
6183 +               }
6184 +               if (s == 0) {
6185 +                       /* copy the response */
6186 +                       rmb();
6187 +                       mbox_copy_to_user(data, mem_kern, size);
6188 +               }
6189 +               dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus);
6190 +       } else {
6191 +               s = -ENOMEM;
6192 +       }
6193 +       if (s != 0)
6194 +               printk(KERN_ERR DRIVER_NAME ": %s failed (%d)\n", __func__, s);
6195 +
6196 +        mutex_unlock(&mailbox_lock);
6197 +       return s;
6198 +}
6199 +EXPORT_SYMBOL_GPL(bcm_mailbox_property);
6200 +
6201 +/* ----------------------------------------------------------------------
6202 + *     Platform Device for Mailbox
6203 + * -------------------------------------------------------------------- */
6204 +
6205 +/*
6206 + * Is the device open right now? Used to prevent
6207 + * concurent access into the same device
6208 + */
6209 +static int Device_Open = 0;
6210 +
6211 +/*
6212 + * This is called whenever a process attempts to open the device file
6213 + */
6214 +static int device_open(struct inode *inode, struct file *file)
6215 +{
6216 +       /*
6217 +        * We don't want to talk to two processes at the same time
6218 +        */
6219 +       if (Device_Open)
6220 +               return -EBUSY;
6221 +
6222 +       Device_Open++;
6223 +       /*
6224 +        * Initialize the message
6225 +        */
6226 +       try_module_get(THIS_MODULE);
6227 +       return 0;
6228 +}
6229 +
6230 +static int device_release(struct inode *inode, struct file *file)
6231 +{
6232 +       /*
6233 +        * We're now ready for our next caller
6234 +        */
6235 +       Device_Open--;
6236 +
6237 +       module_put(THIS_MODULE);
6238 +       return 0;
6239 +}
6240 +
6241 +/*
6242 + * This function is called whenever a process tries to do an ioctl on our
6243 + * device file. We get two extra parameters (additional to the inode and file
6244 + * structures, which all device functions get): the number of the ioctl called
6245 + * and the parameter given to the ioctl function.
6246 + *
6247 + * If the ioctl is write or read/write (meaning output is returned to the
6248 + * calling process), the ioctl call returns the output of this function.
6249 + *
6250 + */
6251 +static long device_ioctl(struct file *file,    /* see include/linux/fs.h */
6252 +                unsigned int ioctl_num,        /* number and param for ioctl */
6253 +                unsigned long ioctl_param)
6254 +{
6255 +       unsigned size;
6256 +       /*
6257 +        * Switch according to the ioctl called
6258 +        */
6259 +       switch (ioctl_num) {
6260 +       case IOCTL_MBOX_PROPERTY:
6261 +               /*
6262 +                * Receive a pointer to a message (in user space) and set that
6263 +                * to be the device's message.  Get the parameter given to
6264 +                * ioctl by the process.
6265 +                */
6266 +               mbox_copy_from_user(&size, (void *)ioctl_param, sizeof size);
6267 +               return bcm_mailbox_property((void *)ioctl_param, size);
6268 +               break;
6269 +       default:
6270 +               printk(KERN_ERR DRIVER_NAME "unknown ioctl: %d\n", ioctl_num);
6271 +               return -EINVAL;
6272 +       }
6273 +
6274 +       return 0;
6275 +}
6276 +
6277 +/* Module Declarations */
6278 +
6279 +/*
6280 + * This structure will hold the functions to be called
6281 + * when a process does something to the device we
6282 + * created. Since a pointer to this structure is kept in
6283 + * the devices table, it can't be local to
6284 + * init_module. NULL is for unimplemented functios.
6285 + */
6286 +struct file_operations fops = {
6287 +       .unlocked_ioctl = device_ioctl,
6288 +       .open = device_open,
6289 +       .release = device_release,      /* a.k.a. close */
6290 +};
6291 +
6292 +static int bcm_vcio_probe(struct platform_device *pdev)
6293 +{
6294 +       int ret = 0;
6295 +       struct vc_mailbox *mailbox;
6296 +
6297 +       mailbox = kzalloc(sizeof(*mailbox), GFP_KERNEL);
6298 +       if (NULL == mailbox) {
6299 +               printk(KERN_ERR DRIVER_NAME ": failed to allocate "
6300 +                      "mailbox memory\n");
6301 +               ret = -ENOMEM;
6302 +       } else {
6303 +               struct resource *res;
6304 +
6305 +               res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6306 +               if (res == NULL) {
6307 +                       printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
6308 +                              "resource\n");
6309 +                       ret = -ENODEV;
6310 +                       kfree(mailbox);
6311 +               } else {
6312 +                       /* should be based on the registers from res really */
6313 +                       mbox_init(mailbox, &pdev->dev, ARM_0_MAIL0_RD);
6314 +
6315 +                       platform_set_drvdata(pdev, mailbox);
6316 +                       dev_mbox_register(DRIVER_NAME, &pdev->dev);
6317 +
6318 +                       mbox_irqaction.dev_id = mailbox;
6319 +                       setup_irq(IRQ_ARM_MAILBOX, &mbox_irqaction);
6320 +                       printk(KERN_INFO DRIVER_NAME ": mailbox at %p\n",
6321 +                              __io_address(ARM_0_MAIL0_RD));
6322 +               }
6323 +       }
6324 +
6325 +       if (ret == 0) {
6326 +               /*
6327 +                * Register the character device
6328 +                */
6329 +               ret = register_chrdev(MAJOR_NUM, DEVICE_FILE_NAME, &fops);
6330 +
6331 +               /*
6332 +                * Negative values signify an error
6333 +                */
6334 +               if (ret < 0) {
6335 +                       printk(KERN_ERR DRIVER_NAME
6336 +                              "Failed registering the character device %d\n", ret);
6337 +                       return ret;
6338 +               }
6339 +       }
6340 +       return ret;
6341 +}
6342 +
6343 +static int bcm_vcio_remove(struct platform_device *pdev)
6344 +{
6345 +       struct vc_mailbox *mailbox = platform_get_drvdata(pdev);
6346 +
6347 +       platform_set_drvdata(pdev, NULL);
6348 +       kfree(mailbox);
6349 +
6350 +       return 0;
6351 +}
6352 +
6353 +static struct platform_driver bcm_mbox_driver = {
6354 +       .probe = bcm_vcio_probe,
6355 +       .remove = bcm_vcio_remove,
6356 +
6357 +       .driver = {
6358 +                  .name = DRIVER_NAME,
6359 +                  .owner = THIS_MODULE,
6360 +                  },
6361 +};
6362 +
6363 +static int __init bcm_mbox_init(void)
6364 +{
6365 +       int ret;
6366 +
6367 +       printk(KERN_INFO "mailbox: Broadcom VideoCore Mailbox driver\n");
6368 +
6369 +       ret = platform_driver_register(&bcm_mbox_driver);
6370 +       if (ret != 0) {
6371 +               printk(KERN_ERR DRIVER_NAME ": failed to register "
6372 +                      "on platform\n");
6373 +       }
6374 +
6375 +       return ret;
6376 +}
6377 +
6378 +static void __exit bcm_mbox_exit(void)
6379 +{
6380 +       platform_driver_unregister(&bcm_mbox_driver);
6381 +}
6382 +
6383 +arch_initcall(bcm_mbox_init);  /* Initialize early */
6384 +module_exit(bcm_mbox_exit);
6385 +
6386 +MODULE_AUTHOR("Gray Girling");
6387 +MODULE_DESCRIPTION("ARM I/O to VideoCore processor");
6388 +MODULE_LICENSE("GPL");
6389 +MODULE_ALIAS("platform:bcm-mbox");
6390 --- a/arch/arm/mm/Kconfig
6391 +++ b/arch/arm/mm/Kconfig
6392 @@ -358,7 +358,7 @@ config CPU_PJ4B
6393
6394  # ARMv6
6395  config CPU_V6
6396 -       bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
6397 +       bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708
6398         select CPU_32v6
6399         select CPU_ABRT_EV6
6400         select CPU_CACHE_V6
6401 --- a/arch/arm/mm/proc-v6.S
6402 +++ b/arch/arm/mm/proc-v6.S
6403 @@ -73,10 +73,19 @@ ENDPROC(cpu_v6_reset)
6404   *
6405   *     IRQs are already disabled.
6406   */
6407 +
6408 +/* See jira SW-5991 for details of this workaround */
6409  ENTRY(cpu_v6_do_idle)
6410 -       mov     r1, #0
6411 -       mcr     p15, 0, r1, c7, c10, 4          @ DWB - WFI may enter a low-power mode
6412 -       mcr     p15, 0, r1, c7, c0, 4           @ wait for interrupt
6413 +       .align 5
6414 +       mov     r1, #2
6415 +1:     subs    r1, #1
6416 +       nop
6417 +       mcreq   p15, 0, r1, c7, c10, 4          @ DWB - WFI may enter a low-power mode
6418 +       mcreq   p15, 0, r1, c7, c0, 4           @ wait for interrupt
6419 +       nop
6420 +       nop
6421 +       nop
6422 +       bne 1b
6423         mov     pc, lr
6424
6425  ENTRY(cpu_v6_dcache_clean_area)
6426 --- a/arch/arm/tools/mach-types
6427 +++ b/arch/arm/tools/mach-types
6428 @@ -522,6 +522,7 @@ torbreck            MACH_TORBRECK           TORBRECK                3090
6429  prima2_evb             MACH_PRIMA2_EVB         PRIMA2_EVB              3103
6430  paz00                  MACH_PAZ00              PAZ00                   3128
6431  acmenetusfoxg20                MACH_ACMENETUSFOXG20    ACMENETUSFOXG20         3129
6432 +bcm2708                        MACH_BCM2708            BCM2708                 3138
6433  ag5evm                 MACH_AG5EVM             AG5EVM                  3189
6434  ics_if_voip            MACH_ICS_IF_VOIP        ICS_IF_VOIP             3206
6435  wlf_cragg_6410         MACH_WLF_CRAGG_6410     WLF_CRAGG_6410          3207
6436 --- a/drivers/mmc/host/Kconfig
6437 +++ b/drivers/mmc/host/Kconfig
6438 @@ -249,6 +249,27 @@ config MMC_SDHCI_S3C_DMA
6439
6440           YMMV.
6441
6442 +config MMC_SDHCI_BCM2708
6443 +       tristate "SDHCI support on BCM2708"
6444 +       depends on MMC_SDHCI && MACH_BCM2708
6445 +       select MMC_SDHCI_IO_ACCESSORS
6446 +       help
6447 +         This selects the Secure Digital Host Controller Interface (SDHCI)
6448 +         often referrered to as the eMMC block.
6449 +
6450 +         If you have a controller with this interface, say Y or M here.
6451 +
6452 +         If unsure, say N.
6453 +
6454 +config MMC_SDHCI_BCM2708_DMA
6455 +       bool "DMA support on BCM2708 Arasan controller"
6456 +       depends on MMC_SDHCI_BCM2708
6457 +       help
6458 +       Enable DMA support on the Arasan SDHCI controller in Broadcom 2708
6459 +         based chips.
6460 +
6461 +         If unsure, say N.
6462 +
6463  config MMC_SDHCI_BCM2835
6464         tristate "SDHCI platform support for the BCM2835 SD/MMC Controller"
6465         depends on ARCH_BCM2835
6466 --- a/drivers/mmc/host/Makefile
6467 +++ b/drivers/mmc/host/Makefile
6468 @@ -15,6 +15,7 @@ obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-p
6469  obj-$(CONFIG_MMC_SDHCI_S3C)    += sdhci-s3c.o
6470  obj-$(CONFIG_MMC_SDHCI_SIRF)           += sdhci-sirf.o
6471  obj-$(CONFIG_MMC_SDHCI_SPEAR)  += sdhci-spear.o
6472 +obj-$(CONFIG_MMC_SDHCI_BCM2708)        += sdhci-bcm2708.o
6473  obj-$(CONFIG_MMC_WBSD)         += wbsd.o
6474  obj-$(CONFIG_MMC_AU1X)         += au1xmmc.o
6475  obj-$(CONFIG_MMC_OMAP)         += omap.o
6476 --- /dev/null
6477 +++ b/drivers/mmc/host/sdhci-bcm2708.c
6478 @@ -0,0 +1,1425 @@
6479 +/*
6480 + * sdhci-bcm2708.c Support for SDHCI device on BCM2708
6481 + * Copyright (c) 2010 Broadcom
6482 + *
6483 + * This program is free software; you can redistribute it and/or modify
6484 + * it under the terms of the GNU General Public License version 2 as
6485 + * published by the Free Software Foundation.
6486 + *
6487 + * This program is distributed in the hope that it will be useful,
6488 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6489 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
6490 + * GNU General Public License for more details.
6491 + *
6492 + * You should have received a copy of the GNU General Public License
6493 + * along with this program; if not, write to the Free Software
6494 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
6495 + */
6496 +
6497 +/* Supports:
6498 + * SDHCI platform device - Arasan SD controller in BCM2708
6499 + *
6500 + * Inspired by sdhci-pci.c, by Pierre Ossman
6501 + */
6502 +
6503 +#include <linux/delay.h>
6504 +#include <linux/highmem.h>
6505 +#include <linux/platform_device.h>
6506 +#include <linux/module.h>
6507 +#include <linux/mmc/mmc.h>
6508 +#include <linux/mmc/host.h>
6509 +#include <linux/mmc/sd.h>
6510 +
6511 +#include <linux/io.h>
6512 +#include <linux/dma-mapping.h>
6513 +#include <mach/dma.h>
6514 +
6515 +#include "sdhci.h"
6516 +
6517 +/*****************************************************************************\
6518 + *                                                                          *
6519 + * Configuration                                                            *
6520 + *                                                                          *
6521 +\*****************************************************************************/
6522 +
6523 +#define DRIVER_NAME "bcm2708_sdhci"
6524 +
6525 +/* for the time being insist on DMA mode - PIO seems not to work */
6526 +#ifndef CONFIG_MMC_SDHCI_BCM2708_DMA
6527 +#warning Non-DMA (PIO) version of this driver currently unavailable
6528 +#endif
6529 +#undef CONFIG_MMC_SDHCI_BCM2708_DMA
6530 +#define CONFIG_MMC_SDHCI_BCM2708_DMA y
6531 +
6532 +#define USE_SYNC_AFTER_DMA
6533 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
6534 +/* #define CHECK_DMA_USE */
6535 +#endif
6536 +//#define LOG_REGISTERS
6537 +
6538 +#define USE_SCHED_TIME
6539 +#define USE_SPACED_WRITES_2CLK 1  /* space consecutive register writes */
6540 +#define USE_SOFTWARE_TIMEOUTS 1   /* not hardware timeouts */
6541 +#define SOFTWARE_ERASE_TIMEOUT_SEC 30
6542 +
6543 +#define SDHCI_BCM_DMA_CHAN 4   /* this default is normally overriden */
6544 +#define SDHCI_BCM_DMA_WAITS 0  /* delays slowing DMA transfers: 0-31 */
6545 +/* We are worried that SD card DMA use may be blocking the AXI bus for others */
6546 +
6547 +/*! TODO: obtain these from the physical address */
6548 +#define DMA_SDHCI_BASE  0x7e300000  /* EMMC register block on Videocore */
6549 +#define DMA_SDHCI_BUFFER (DMA_SDHCI_BASE + SDHCI_BUFFER)
6550 +
6551 +#define BCM2708_SDHCI_SLEEP_TIMEOUT 1000   /* msecs */
6552 +
6553 +/* Mhz clock that the EMMC core is running at. Should match the platform clockman settings */
6554 +#define BCM2708_EMMC_CLOCK_FREQ 80000000
6555 +
6556 +/*****************************************************************************\
6557 + *                                                                          *
6558 + * Debug                                                                    *
6559 + *                                                                          *
6560 +\*****************************************************************************/
6561 +
6562 +
6563 +
6564 +#define DBG(f, x...) \
6565 +       pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
6566 +//     printk(KERN_INFO DRIVER_NAME " [%s()]: " f, __func__,## x)//GRAYG
6567 +
6568 +
6569 +/*****************************************************************************\
6570 + *                                                                          *
6571 + * High Precision Time                                                      *
6572 + *                                                                          *
6573 +\*****************************************************************************/
6574 +
6575 +#ifdef USE_SCHED_TIME
6576 +
6577 +#include <mach/frc.h>
6578 +
6579 +typedef unsigned long hptime_t;
6580 +
6581 +#define FMT_HPT "lu"
6582 +
6583 +static inline hptime_t hptime(void)
6584 +{
6585 +       return frc_clock_ticks32();
6586 +}
6587 +
6588 +#define HPTIME_CLK_NS 1000ul
6589 +
6590 +#else
6591 +
6592 +typedef unsigned long hptime_t;
6593 +
6594 +#define FMT_HPT "lu"
6595 +
6596 +static inline hptime_t hptime(void)
6597 +{
6598 +       return jiffies;
6599 +}
6600 +
6601 +#define HPTIME_CLK_NS (1000000000ul/HZ)
6602 +
6603 +#endif
6604 +
6605 +static inline unsigned long int since_ns(hptime_t t)
6606 +{
6607 +       return (unsigned long)((hptime() - t) * HPTIME_CLK_NS);
6608 +}
6609 +
6610 +#if 0
6611 +static void hptime_test(void)
6612 +{
6613 +       hptime_t now;
6614 +       hptime_t later;
6615 +
6616 +       now = hptime();
6617 +       msleep(10);
6618 +       later = hptime();
6619 +
6620 +       printk(KERN_INFO DRIVER_NAME": 10ms = %"FMT_HPT" clks "
6621 +              "(from %"FMT_HPT" to %"FMT_HPT") = %luns\n",
6622 +              later-now, now, later,
6623 +              (unsigned long)(HPTIME_CLK_NS * (later - now)));
6624 +
6625 +       now = hptime();
6626 +       msleep(1000);
6627 +       later = hptime();
6628 +
6629 +       printk(KERN_INFO DRIVER_NAME": 1s = %"FMT_HPT" clks "
6630 +              "(from %"FMT_HPT" to %"FMT_HPT") = %luns\n",
6631 +              later-now, now, later,
6632 +              (unsigned long)(HPTIME_CLK_NS * (later - now)));
6633 +}
6634 +#endif
6635 +
6636 +/*****************************************************************************\
6637 + *                                                                          *
6638 + * SDHCI core callbacks                                                             *
6639 + *                                                                          *
6640 +\*****************************************************************************/
6641 +
6642 +
6643 +#ifdef CHECK_DMA_USE
6644 +/*#define CHECK_DMA_REG_USE*/
6645 +#endif
6646 +
6647 +#ifdef CHECK_DMA_REG_USE
6648 +/* we don't expect anything to be using these registers during a
6649 +   DMA (except the IRQ status) - so check */
6650 +static void check_dma_reg_use(struct sdhci_host *host, int reg);
6651 +#else
6652 +#define check_dma_reg_use(host, reg)
6653 +#endif
6654 +
6655 +
6656 +static inline u32 sdhci_bcm2708_raw_readl(struct sdhci_host *host, int reg)
6657 +{
6658 +       return readl(host->ioaddr + reg);
6659 +}
6660 +
6661 +u32 sdhci_bcm2708_readl(struct sdhci_host *host, int reg)
6662 +{
6663 +       u32 l = sdhci_bcm2708_raw_readl(host, reg);
6664 +
6665 +#ifdef LOG_REGISTERS
6666 +       printk(KERN_ERR "%s: readl from 0x%02x, value 0x%08x\n",
6667 +              mmc_hostname(host->mmc), reg, l);
6668 +#endif
6669 +       check_dma_reg_use(host, reg);
6670 +
6671 +       return l;
6672 +}
6673 +
6674 +u16 sdhci_bcm2708_readw(struct sdhci_host *host, int reg)
6675 +{
6676 +       u32 l = sdhci_bcm2708_raw_readl(host, reg & ~3);
6677 +       u32 w = l >> (reg << 3 & 0x18) & 0xffff;
6678 +
6679 +#ifdef LOG_REGISTERS
6680 +       printk(KERN_ERR "%s: readw from 0x%02x, value 0x%04x\n",
6681 +              mmc_hostname(host->mmc), reg, w);
6682 +#endif
6683 +       check_dma_reg_use(host, reg);
6684 +
6685 +       return (u16)w;
6686 +}
6687 +
6688 +u8 sdhci_bcm2708_readb(struct sdhci_host *host, int reg)
6689 +{
6690 +       u32 l = sdhci_bcm2708_raw_readl(host, reg & ~3);
6691 +       u32 b = l >> (reg << 3 & 0x18) & 0xff;
6692 +
6693 +#ifdef LOG_REGISTERS
6694 +       printk(KERN_ERR "%s: readb from 0x%02x, value 0x%02x\n",
6695 +              mmc_hostname(host->mmc), reg, b);
6696 +#endif
6697 +       check_dma_reg_use(host, reg);
6698 +
6699 +       return (u8)b;
6700 +}
6701 +
6702 +
6703 +static void sdhci_bcm2708_raw_writel(struct sdhci_host *host, u32 val, int reg)
6704 +{
6705 +       u32 ier;
6706 +
6707 +#if USE_SPACED_WRITES_2CLK
6708 +       static bool timeout_disabled = false;
6709 +       unsigned int ns_2clk = 0;
6710 +
6711 +       /* The Arasan has a bugette whereby it may lose the content of
6712 +        * successive writes to registers that are within two SD-card clock
6713 +        * cycles of each other (a clock domain crossing problem).
6714 +        * It seems, however, that the data register does not have this problem.
6715 +        * (Which is just as well - otherwise we'd have to nobble the DMA engine
6716 +        * too)
6717 +        */
6718 +       if (reg != SDHCI_BUFFER && host->clock != 0) {
6719 +               /* host->clock is the clock freq in Hz */
6720 +               static hptime_t last_write_hpt;
6721 +               hptime_t now = hptime();
6722 +               ns_2clk = 2000000000/host->clock;
6723 +
6724 +               if (now == last_write_hpt || now == last_write_hpt+1) {
6725 +                        /* we can't guarantee any significant time has
6726 +                         * passed - we'll have to wait anyway ! */
6727 +                       udelay((ns_2clk+1000-1)/1000);
6728 +               } else
6729 +               {
6730 +                       /* we must have waited at least this many ns: */
6731 +                       unsigned int ns_wait = HPTIME_CLK_NS *
6732 +                                              (last_write_hpt - now - 1);
6733 +                       if (ns_wait < ns_2clk)
6734 +                               udelay((ns_2clk-ns_wait+500)/1000);
6735 +               }
6736 +               last_write_hpt = now;
6737 +       }
6738 +#if USE_SOFTWARE_TIMEOUTS
6739 +       /* The Arasan is clocked for timeouts using the SD clock which is too
6740 +        * fast for ERASE commands and causes issues. So we disable timeouts
6741 +        * for ERASE */
6742 +       if (host->cmd != NULL && host->cmd->opcode == MMC_ERASE &&
6743 +            reg == (SDHCI_COMMAND & ~3)) {
6744 +               mod_timer(&host->timer,
6745 +                          jiffies + SOFTWARE_ERASE_TIMEOUT_SEC * HZ);
6746 +               ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
6747 +               ier &= ~SDHCI_INT_DATA_TIMEOUT;
6748 +               writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
6749 +               timeout_disabled = true;
6750 +               udelay((ns_2clk+1000-1)/1000);
6751 +       } else if (timeout_disabled) {
6752 +               ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
6753 +               ier |= SDHCI_INT_DATA_TIMEOUT;
6754 +               writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
6755 +               timeout_disabled = false;
6756 +               udelay((ns_2clk+1000-1)/1000);
6757 +       }
6758 +#endif
6759 +       writel(val, host->ioaddr + reg);
6760 +#else
6761 +       void __iomem * regaddr = host->ioaddr + reg;
6762 +
6763 +       writel(val, regaddr);
6764 +
6765 +       if (reg != SDHCI_BUFFER && reg != SDHCI_INT_STATUS && host->clock != 0)
6766 +       {
6767 +               int timeout = 100000;
6768 +               while (val != readl(regaddr) && --timeout > 0)
6769 +                  continue;
6770 +
6771 +               if (timeout <= 0)
6772 +                       printk(KERN_ERR "%s: writing 0x%X to reg 0x%X "
6773 +                              "always gives 0x%X\n",
6774 +                              mmc_hostname(host->mmc),
6775 +                              val, reg, readl(regaddr));
6776 +               BUG_ON(timeout <= 0);
6777 +       }
6778 +#endif
6779 +}
6780 +
6781 +
6782 +void sdhci_bcm2708_writel(struct sdhci_host *host, u32 val, int reg)
6783 +{
6784 +#ifdef LOG_REGISTERS
6785 +       printk(KERN_ERR "%s: writel to 0x%02x, value 0x%08x\n",
6786 +              mmc_hostname(host->mmc), reg, val);
6787 +#endif
6788 +       check_dma_reg_use(host, reg);
6789 +
6790 +       sdhci_bcm2708_raw_writel(host, val, reg);
6791 +}
6792 +
6793 +void sdhci_bcm2708_writew(struct sdhci_host *host, u16 val, int reg)
6794 +{
6795 +       static u32 shadow = 0;
6796 +
6797 +       u32 p = reg == SDHCI_COMMAND ? shadow :
6798 +                      sdhci_bcm2708_raw_readl(host, reg & ~3);
6799 +       u32 s = reg << 3 & 0x18;
6800 +       u32 l = val << s;
6801 +       u32 m = 0xffff << s;
6802 +
6803 +#ifdef LOG_REGISTERS
6804 +       printk(KERN_ERR "%s: writew to 0x%02x, value 0x%04x\n",
6805 +              mmc_hostname(host->mmc), reg, val);
6806 +#endif
6807 +
6808 +       if (reg == SDHCI_TRANSFER_MODE)
6809 +               shadow = (p & ~m) | l;
6810 +       else {
6811 +               check_dma_reg_use(host, reg);
6812 +               sdhci_bcm2708_raw_writel(host, (p & ~m) | l, reg & ~3);
6813 +       }
6814 +}
6815 +
6816 +void sdhci_bcm2708_writeb(struct sdhci_host *host, u8 val, int reg)
6817 +{
6818 +       u32 p = sdhci_bcm2708_raw_readl(host, reg & ~3);
6819 +       u32 s = reg << 3 & 0x18;
6820 +       u32 l = val << s;
6821 +       u32 m = 0xff << s;
6822 +
6823 +#ifdef LOG_REGISTERS
6824 +       printk(KERN_ERR "%s: writeb to 0x%02x, value 0x%02x\n",
6825 +              mmc_hostname(host->mmc), reg, val);
6826 +#endif
6827 +
6828 +       check_dma_reg_use(host, reg);
6829 +       sdhci_bcm2708_raw_writel(host, (p & ~m) | l, reg & ~3);
6830 +}
6831 +
6832 +static unsigned int sdhci_bcm2708_get_max_clock(struct sdhci_host *host)
6833 +{
6834 +       return 20000000;        // this value is in Hz (20MHz)
6835 +}
6836 +
6837 +static unsigned int sdhci_bcm2708_get_timeout_clock(struct sdhci_host *host)
6838 +{
6839 +       if(host->clock)
6840 +               return (host->clock / 1000);            // this value is in kHz (100MHz)
6841 +       else
6842 +               return (sdhci_bcm2708_get_max_clock(host) / 1000);
6843 +}
6844 +
6845 +static void sdhci_bcm2708_set_clock(struct sdhci_host *host, unsigned int clock)
6846 +{
6847 +       int div = 0;
6848 +       u16 clk = 0;
6849 +       unsigned long timeout;
6850 +
6851 +        if (clock == host->clock)
6852 +                return;
6853 +
6854 +        sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
6855 +
6856 +        if (clock == 0)
6857 +                goto out;
6858 +
6859 +       if (BCM2708_EMMC_CLOCK_FREQ <= clock)
6860 +               div = 1;
6861 +       else {
6862 +               for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
6863 +                       if ((BCM2708_EMMC_CLOCK_FREQ / div) <= clock)
6864 +                               break;
6865 +               }
6866 +       }
6867 +
6868 +        DBG( "desired SD clock: %d, actual: %d\n",
6869 +                clock, BCM2708_EMMC_CLOCK_FREQ / div);
6870 +
6871 +       clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
6872 +       clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
6873 +               << SDHCI_DIVIDER_HI_SHIFT;
6874 +       clk |= SDHCI_CLOCK_INT_EN;
6875 +
6876 +       sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
6877 +
6878 +        timeout = 20;
6879 +        while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
6880 +                        & SDHCI_CLOCK_INT_STABLE)) {
6881 +                if (timeout == 0) {
6882 +                       printk(KERN_ERR "%s: Internal clock never "
6883 +                               "stabilised.\n", mmc_hostname(host->mmc));
6884 +                        return;
6885 +                }
6886 +                timeout--;
6887 +                mdelay(1);
6888 +        }
6889 +
6890 +        clk |= SDHCI_CLOCK_CARD_EN;
6891 +        sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
6892 +out:
6893 +        host->clock = clock;
6894 + }
6895 +
6896 +/*****************************************************************************\
6897 + *                                                                          *
6898 + * DMA Operation                                                            *
6899 + *                                                                          *
6900 +\*****************************************************************************/
6901 +
6902 +struct sdhci_bcm2708_priv {
6903 +       int                     dma_chan;
6904 +       int                     dma_irq;
6905 +       void __iomem           *dma_chan_base;
6906 +       struct bcm2708_dma_cb  *cb_base;   /* DMA control blocks */
6907 +       dma_addr_t              cb_handle;
6908 +       /* tracking scatter gather progress */
6909 +       unsigned                sg_ix;     /* scatter gather list index */
6910 +       unsigned                sg_done;   /* bytes in current sg_ix done */
6911 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
6912 +       unsigned char           dma_wanted;  /* DMA transfer requested */
6913 +       unsigned char           dma_waits;   /* wait states in DMAs */
6914 +#ifdef CHECK_DMA_USE
6915 +       unsigned char           dmas_pending; /* no of unfinished DMAs */
6916 +       hptime_t                when_started;
6917 +       hptime_t                when_reset;
6918 +       hptime_t                when_stopped;
6919 +#endif
6920 +#endif
6921 +       /* signalling the end of a transfer */
6922 +       void                  (*complete)(struct sdhci_host *);
6923 +};
6924 +
6925 +#define SDHCI_HOST_PRIV(host) \
6926 +       (struct sdhci_bcm2708_priv *)((struct sdhci_host *)(host)+1)
6927 +
6928 +
6929 +
6930 +#ifdef CHECK_DMA_REG_USE
6931 +static void check_dma_reg_use(struct sdhci_host *host, int reg)
6932 +{
6933 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
6934 +       if (host_priv->dma_wanted && reg != SDHCI_INT_STATUS) {
6935 +               printk(KERN_INFO"%s: accessing register 0x%x during DMA\n",
6936 +                      mmc_hostname(host->mmc), reg);
6937 +       }
6938 +}
6939 +#endif
6940 +
6941 +
6942 +
6943 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
6944 +
6945 +static void sdhci_clear_set_irqgen(struct sdhci_host *host, u32 clear, u32 set)
6946 +{
6947 +       u32 ier;
6948 +
6949 +       ier = sdhci_bcm2708_raw_readl(host, SDHCI_SIGNAL_ENABLE);
6950 +       ier &= ~clear;
6951 +       ier |= set;
6952 +       /* change which requests generate IRQs - makes no difference to
6953 +          the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */
6954 +       sdhci_bcm2708_raw_writel(host, ier, SDHCI_SIGNAL_ENABLE);
6955 +}
6956 +
6957 +static void sdhci_signal_irqs(struct sdhci_host *host, u32 irqs)
6958 +{
6959 +       sdhci_clear_set_irqgen(host, 0, irqs);
6960 +}
6961 +
6962 +static void sdhci_unsignal_irqs(struct sdhci_host *host, u32 irqs)
6963 +{
6964 +       sdhci_clear_set_irqgen(host, irqs, 0);
6965 +}
6966 +
6967 +
6968 +
6969 +static void schci_bcm2708_cb_read(struct sdhci_bcm2708_priv *host,
6970 +                                 int ix,
6971 +                                 dma_addr_t dma_addr, unsigned len,
6972 +                                 int /*bool*/ is_last)
6973 +{
6974 +       struct bcm2708_dma_cb *cb = &host->cb_base[ix];
6975 +        unsigned char dmawaits = host->dma_waits;
6976 +
6977 +       cb->info   = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) |
6978 +                    BCM2708_DMA_WAITS(dmawaits) |
6979 +                    BCM2708_DMA_S_DREQ  |
6980 +                    BCM2708_DMA_D_WIDTH |
6981 +                    BCM2708_DMA_D_INC;
6982 +       cb->src    = DMA_SDHCI_BUFFER;  /* DATA register DMA address */
6983 +       cb->dst    = dma_addr;
6984 +       cb->length = len;
6985 +       cb->stride = 0;
6986 +
6987 +       if (is_last) {
6988 +               cb->info |= BCM2708_DMA_INT_EN |
6989 +                    BCM2708_DMA_WAIT_RESP;
6990 +               cb->next = 0;
6991 +       } else
6992 +               cb->next = host->cb_handle +
6993 +                          (ix+1)*sizeof(struct bcm2708_dma_cb);
6994 +
6995 +       cb->pad[0] = 0;
6996 +       cb->pad[1] = 0;
6997 +}
6998 +
6999 +static void schci_bcm2708_cb_write(struct sdhci_bcm2708_priv *host,
7000 +                                  int ix,
7001 +                                  dma_addr_t dma_addr, unsigned len,
7002 +                                  int /*bool*/ is_last)
7003 +{
7004 +       struct bcm2708_dma_cb *cb = &host->cb_base[ix];
7005 +        unsigned char dmawaits = host->dma_waits;
7006 +
7007 +       /* We can make arbitrarily large writes as long as we specify DREQ to
7008 +          pace the delivery of bytes to the Arasan hardware */
7009 +       cb->info   = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) |
7010 +                    BCM2708_DMA_WAITS(dmawaits) |
7011 +                    BCM2708_DMA_D_DREQ  |
7012 +                    BCM2708_DMA_S_WIDTH |
7013 +                    BCM2708_DMA_S_INC;
7014 +       cb->src    = dma_addr;
7015 +       cb->dst    = DMA_SDHCI_BUFFER;  /* DATA register DMA address */
7016 +       cb->length = len;
7017 +       cb->stride = 0;
7018 +
7019 +       if (is_last) {
7020 +               cb->info |= BCM2708_DMA_INT_EN |
7021 +                    BCM2708_DMA_WAIT_RESP;
7022 +               cb->next = 0;
7023 +       } else
7024 +               cb->next = host->cb_handle +
7025 +                          (ix+1)*sizeof(struct bcm2708_dma_cb);
7026 +
7027 +       cb->pad[0] = 0;
7028 +       cb->pad[1] = 0;
7029 +}
7030 +
7031 +
7032 +static void schci_bcm2708_dma_go(struct sdhci_host *host)
7033 +{
7034 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7035 +       void __iomem *dma_chan_base = host_priv->dma_chan_base;
7036 +
7037 +       BUG_ON(host_priv->dma_wanted);
7038 +#ifdef CHECK_DMA_USE
7039 +       if (host_priv->dma_wanted)
7040 +               printk(KERN_ERR "%s: DMA already in progress - "
7041 +                      "now %"FMT_HPT", last started %lu "
7042 +                      "reset %lu stopped %lu\n",
7043 +                      mmc_hostname(host->mmc),
7044 +                      hptime(), since_ns(host_priv->when_started),
7045 +                      since_ns(host_priv->when_reset),
7046 +                      since_ns(host_priv->when_stopped));
7047 +       else if (host_priv->dmas_pending > 0)
7048 +               printk(KERN_INFO "%s: note - new DMA when %d reset DMAs "
7049 +                      "already in progress - "
7050 +                      "now %"FMT_HPT", started %lu reset %lu stopped %lu\n",
7051 +                      mmc_hostname(host->mmc),
7052 +                      host_priv->dmas_pending,
7053 +                      hptime(), since_ns(host_priv->when_started),
7054 +                      since_ns(host_priv->when_reset),
7055 +                      since_ns(host_priv->when_stopped));
7056 +       host_priv->dmas_pending += 1;
7057 +       host_priv->when_started = hptime();
7058 +#endif
7059 +       host_priv->dma_wanted = 1;
7060 +       DBG("PDMA go - base %p handle %08X\n", dma_chan_base,
7061 +           host_priv->cb_handle);
7062 +       bcm_dma_start(dma_chan_base, host_priv->cb_handle);
7063 +}
7064 +
7065 +
7066 +static void
7067 +sdhci_platdma_read(struct sdhci_host *host, dma_addr_t dma_addr, size_t len)
7068 +{
7069 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7070 +
7071 +       DBG("PDMA to read %d bytes\n", len);
7072 +       host_priv->sg_done += len;
7073 +       schci_bcm2708_cb_read(host_priv, 0, dma_addr, len, 1/*TRUE*/);
7074 +       schci_bcm2708_dma_go(host);
7075 +}
7076 +
7077 +
7078 +static void
7079 +sdhci_platdma_write(struct sdhci_host *host, dma_addr_t dma_addr, size_t len)
7080 +{
7081 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7082 +
7083 +       DBG("PDMA to write %d bytes\n", len);
7084 +       //BUG_ON(0 != (len & 0x1ff));
7085 +
7086 +       host_priv->sg_done += len;
7087 +       schci_bcm2708_cb_write(host_priv, 0, dma_addr, len, 1/*TRUE*/);
7088 +       schci_bcm2708_dma_go(host);
7089 +}
7090 +
7091 +/*! space is avaiable to receive into or data is available to write
7092 +  Platform DMA exported function
7093 +*/
7094 +void
7095 +sdhci_bcm2708_platdma_avail(struct sdhci_host *host, unsigned int *ref_intmask,
7096 +                           void(*completion_callback)(struct sdhci_host *host))
7097 +{
7098 +       struct mmc_data *data = host->data;
7099 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7100 +       int sg_ix;
7101 +       size_t bytes;
7102 +       dma_addr_t addr;
7103 +
7104 +       BUG_ON(NULL == data);
7105 +       BUG_ON(0 == data->blksz);
7106 +
7107 +       host_priv->complete = completion_callback;
7108 +
7109 +       sg_ix = host_priv->sg_ix;
7110 +       BUG_ON(sg_ix >= data->sg_len);
7111 +
7112 +       /* we can DMA blocks larger than blksz - it may hang the DMA
7113 +          channel but we are its only user */
7114 +       bytes = sg_dma_len(&data->sg[sg_ix]) - host_priv->sg_done;
7115 +       addr = sg_dma_address(&data->sg[sg_ix]) + host_priv->sg_done;
7116 +
7117 +       if (bytes > 0) {
7118 +               /* We're going to poll for read/write available state until
7119 +                  we finish this DMA
7120 +               */
7121 +
7122 +               if (data->flags & MMC_DATA_READ) {
7123 +                       if (*ref_intmask & SDHCI_INT_DATA_AVAIL)  {
7124 +                               sdhci_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
7125 +                                                   SDHCI_INT_SPACE_AVAIL);
7126 +                               sdhci_platdma_read(host, addr, bytes);
7127 +                       }
7128 +               } else {
7129 +                       if (*ref_intmask & SDHCI_INT_SPACE_AVAIL) {
7130 +                               sdhci_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
7131 +                                                   SDHCI_INT_SPACE_AVAIL);
7132 +                               sdhci_platdma_write(host, addr, bytes);
7133 +                       }
7134 +               }
7135 +       }
7136 +       /* else:
7137 +          we have run out of bytes that need transferring (e.g. we may be in
7138 +          the middle of the last DMA transfer), or
7139 +          it is also possible that we've been called when another IRQ is
7140 +          signalled, even though we've turned off signalling of our own IRQ */
7141 +
7142 +       *ref_intmask &= ~SDHCI_INT_DATA_END;
7143 +       /* don't let the main sdhci driver act on this .. we'll deal with it
7144 +          when we respond to the DMA - if one is currently in progress */
7145 +}
7146 +
7147 +/* is it possible to DMA the given mmc_data structure?
7148 +   Platform DMA exported function
7149 +*/
7150 +int /*bool*/
7151 +sdhci_bcm2708_platdma_dmaable(struct sdhci_host *host, struct mmc_data *data)
7152 +{
7153 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7154 +       int ok = bcm_sg_suitable_for_dma(data->sg, data->sg_len);
7155 +
7156 +       if (!ok)
7157 +               DBG("Reverting to PIO - bad cache alignment\n");
7158 +
7159 +       else {
7160 +               host_priv->sg_ix = 0;    /* first SG index */
7161 +               host_priv->sg_done = 0;  /* no bytes done */
7162 +       }
7163 +
7164 +       return ok;
7165 +}
7166 +
7167 +#include <mach/arm_control.h> //GRAYG
7168 +/*! the current SD transacton has been abandonned
7169 +  We need to tidy up if we were in the middle of a DMA
7170 +  Platform DMA exported function
7171 +*/
7172 +void
7173 +sdhci_bcm2708_platdma_reset(struct sdhci_host *host, struct mmc_data *data)
7174 +{
7175 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7176 +       unsigned long flags;
7177 +
7178 +       BUG_ON(NULL == host);
7179 +
7180 +       spin_lock_irqsave(&host->lock, flags);
7181 +
7182 +       if (host_priv->dma_wanted) {
7183 +               if (NULL == data) {
7184 +                       printk(KERN_ERR "%s: ongoing DMA reset - no data!\n",
7185 +                              mmc_hostname(host->mmc));
7186 +                       BUG_ON(NULL == data);
7187 +               } else {
7188 +                       struct scatterlist *sg;
7189 +                       int sg_len;
7190 +                       int sg_todo;
7191 +                       int rc;
7192 +                       unsigned long cs;
7193 +
7194 +                       sg = data->sg;
7195 +                       sg_len = data->sg_len;
7196 +                       sg_todo = sg_dma_len(&sg[host_priv->sg_ix]);
7197 +
7198 +                       cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS);
7199 +
7200 +                       if (!(BCM2708_DMA_ACTIVE & cs))
7201 +                               printk(KERN_INFO "%s: missed completion of "
7202 +                                      "cmd %d DMA (%d/%d [%d]/[%d]) - "
7203 +                                      "ignoring it\n",
7204 +                                      mmc_hostname(host->mmc),
7205 +                                      host->last_cmdop,
7206 +                                      host_priv->sg_done, sg_todo,
7207 +                                      host_priv->sg_ix+1, sg_len);
7208 +                       else
7209 +                               printk(KERN_INFO "%s: resetting ongoing cmd %d"
7210 +                                      "DMA before %d/%d [%d]/[%d] complete\n",
7211 +                                      mmc_hostname(host->mmc),
7212 +                                      host->last_cmdop,
7213 +                                      host_priv->sg_done, sg_todo,
7214 +                                      host_priv->sg_ix+1, sg_len);
7215 +#ifdef CHECK_DMA_USE
7216 +                       printk(KERN_INFO "%s: now %"FMT_HPT" started %lu "
7217 +                              "last reset %lu last stopped %lu\n",
7218 +                              mmc_hostname(host->mmc),
7219 +                              hptime(), since_ns(host_priv->when_started),
7220 +                              since_ns(host_priv->when_reset),
7221 +                              since_ns(host_priv->when_stopped));
7222 +                       {       unsigned long info, debug;
7223 +                               void __iomem *base;
7224 +                               unsigned long pend0, pend1, pend2;
7225 +
7226 +                               base = host_priv->dma_chan_base;
7227 +                               cs = readl(base + BCM2708_DMA_CS);
7228 +                               info = readl(base + BCM2708_DMA_INFO);
7229 +                               debug = readl(base + BCM2708_DMA_DEBUG);
7230 +                               printk(KERN_INFO "%s: DMA%d CS=%08lX TI=%08lX "
7231 +                                      "DEBUG=%08lX\n",
7232 +                                      mmc_hostname(host->mmc),
7233 +                                       host_priv->dma_chan,
7234 +                                      cs, info, debug);
7235 +                               pend0 = readl(__io_address(ARM_IRQ_PEND0));
7236 +                               pend1 = readl(__io_address(ARM_IRQ_PEND1));
7237 +                               pend2 = readl(__io_address(ARM_IRQ_PEND2));
7238 +
7239 +                               printk(KERN_INFO "%s: PEND0=%08lX "
7240 +                                      "PEND1=%08lX PEND2=%08lX\n",
7241 +                                      mmc_hostname(host->mmc),
7242 +                                      pend0, pend1, pend2);
7243 +
7244 +                               //gintsts = readl(__io_address(GINTSTS));
7245 +                               //gintmsk = readl(__io_address(GINTMSK));
7246 +                               //printk(KERN_INFO "%s: USB GINTSTS=%08lX"
7247 +                               //       "GINTMSK=%08lX\n",
7248 +                               //       mmc_hostname(host->mmc), gintsts, gintmsk);
7249 +                       }
7250 +#endif
7251 +                       rc = bcm_dma_abort(host_priv->dma_chan_base);
7252 +                       BUG_ON(rc != 0);
7253 +               }
7254 +               host_priv->dma_wanted = 0;
7255 +#ifdef CHECK_DMA_USE
7256 +               host_priv->when_reset = hptime();
7257 +#endif
7258 +       }
7259 +
7260 +       spin_unlock_irqrestore(&host->lock, flags);
7261 +}
7262 +
7263 +
7264 +static void sdhci_bcm2708_dma_complete_irq(struct sdhci_host *host,
7265 +                                          u32 dma_cs)
7266 +{
7267 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7268 +       struct mmc_data *data;
7269 +       struct scatterlist *sg;
7270 +       int sg_len;
7271 +       int sg_ix;
7272 +       int sg_todo;
7273 +       unsigned long flags;
7274 +
7275 +       BUG_ON(NULL == host);
7276 +
7277 +       spin_lock_irqsave(&host->lock, flags);
7278 +       data = host->data;
7279 +
7280 +#ifdef CHECK_DMA_USE
7281 +       if (host_priv->dmas_pending <= 0)
7282 +               DBG("on completion no DMA in progress - "
7283 +                   "now %"FMT_HPT" started %lu reset %lu stopped %lu\n",
7284 +                   hptime(), since_ns(host_priv->when_started),
7285 +                   since_ns(host_priv->when_reset),
7286 +                   since_ns(host_priv->when_stopped));
7287 +       else if (host_priv->dmas_pending > 1)
7288 +               DBG("still %d DMA in progress after completion - "
7289 +                   "now %"FMT_HPT" started %lu reset %lu stopped %lu\n",
7290 +                   host_priv->dmas_pending - 1,
7291 +                   hptime(), since_ns(host_priv->when_started),
7292 +                   since_ns(host_priv->when_reset),
7293 +                   since_ns(host_priv->when_stopped));
7294 +       BUG_ON(host_priv->dmas_pending <= 0);
7295 +       host_priv->dmas_pending -= 1;
7296 +       host_priv->when_stopped = hptime();
7297 +#endif
7298 +       host_priv->dma_wanted = 0;
7299 +
7300 +       if (NULL == data) {
7301 +               DBG("PDMA unused completion - status 0x%X\n", dma_cs);
7302 +               spin_unlock_irqrestore(&host->lock, flags);
7303 +               return;
7304 +       }
7305 +       sg = data->sg;
7306 +       sg_len = data->sg_len;
7307 +       sg_todo = sg_dma_len(&sg[host_priv->sg_ix]);
7308 +
7309 +       DBG("PDMA complete %d/%d [%d]/[%d]..\n",
7310 +           host_priv->sg_done, sg_todo,
7311 +           host_priv->sg_ix+1, sg_len);
7312 +
7313 +       BUG_ON(host_priv->sg_done > sg_todo);
7314 +
7315 +       if (host_priv->sg_done >= sg_todo) {
7316 +               host_priv->sg_ix++;
7317 +               host_priv->sg_done = 0;
7318 +       }
7319 +
7320 +       sg_ix = host_priv->sg_ix;
7321 +       if (sg_ix < sg_len) {
7322 +               u32 irq_mask;
7323 +               /* Set off next DMA if we've got the capacity */
7324 +
7325 +               if (data->flags & MMC_DATA_READ)
7326 +                       irq_mask = SDHCI_INT_DATA_AVAIL;
7327 +               else
7328 +                       irq_mask = SDHCI_INT_SPACE_AVAIL;
7329 +
7330 +               /* We have to use the interrupt status register on the BCM2708
7331 +                  rather than the SDHCI_PRESENT_STATE register because latency
7332 +                  in the glue logic means that the information retrieved from
7333 +                  the latter is not always up-to-date w.r.t the DMA engine -
7334 +                  it may not indicate that a read or a write is ready yet */
7335 +               if (sdhci_bcm2708_raw_readl(host, SDHCI_INT_STATUS) &
7336 +                   irq_mask) {
7337 +                       size_t bytes = sg_dma_len(&sg[sg_ix]) -
7338 +                                      host_priv->sg_done;
7339 +                       dma_addr_t addr = sg_dma_address(&data->sg[sg_ix]) +
7340 +                                         host_priv->sg_done;
7341 +
7342 +                       /* acknowledge interrupt */
7343 +                       sdhci_bcm2708_raw_writel(host, irq_mask,
7344 +                                                SDHCI_INT_STATUS);
7345 +
7346 +                       BUG_ON(0 == bytes);
7347 +
7348 +                       if (data->flags & MMC_DATA_READ)
7349 +                               sdhci_platdma_read(host, addr, bytes);
7350 +                       else
7351 +                               sdhci_platdma_write(host, addr, bytes);
7352 +               } else {
7353 +                       DBG("PDMA - wait avail\n");
7354 +                       /* may generate an IRQ if already present */
7355 +                       sdhci_signal_irqs(host, SDHCI_INT_DATA_AVAIL |
7356 +                                               SDHCI_INT_SPACE_AVAIL);
7357 +               }
7358 +       } else {
7359 +#ifdef USE_SYNC_AFTER_DMA
7360 +               /* On the Arasan controller the stop command (which will be
7361 +                  scheduled after this completes) does not seem to work
7362 +                  properly if we allow it to be issued when we are
7363 +                  transferring data to/from the SD card.
7364 +                  We get CRC and DEND errors unless we wait for
7365 +                  the SD controller to finish reading/writing to the card. */
7366 +               u32 state_mask;
7367 +               int timeout=1000000;
7368 +               hptime_t now = hptime();
7369 +
7370 +               DBG("PDMA over - sync card\n");
7371 +               if (data->flags & MMC_DATA_READ)
7372 +                       state_mask = SDHCI_DOING_READ;
7373 +               else
7374 +                       state_mask = SDHCI_DOING_WRITE;
7375 +
7376 +               while (0 != (sdhci_bcm2708_raw_readl(host,
7377 +                                                    SDHCI_PRESENT_STATE) &
7378 +                            state_mask) && --timeout > 0)
7379 +                       continue;
7380 +
7381 +               if (1000000-timeout > 4000) /*ave. is about 3250*/
7382 +                       DBG("%s: note - long %s sync %luns - "
7383 +                              "%d its.\n",
7384 +                              mmc_hostname(host->mmc),
7385 +                              data->flags & MMC_DATA_READ? "read": "write",
7386 +                              since_ns(now), 1000000-timeout);
7387 +               if (timeout <= 0)
7388 +                       printk(KERN_ERR"%s: final %s to SD card still "
7389 +                              "running\n",
7390 +                              mmc_hostname(host->mmc),
7391 +                              data->flags & MMC_DATA_READ? "read": "write");
7392 +#endif
7393 +               if (host_priv->complete) {
7394 +                       (*host_priv->complete)(host);
7395 +                       DBG("PDMA %s complete\n",
7396 +                           data->flags & MMC_DATA_READ?"read":"write");
7397 +                       sdhci_signal_irqs(host, SDHCI_INT_DATA_AVAIL |
7398 +                                               SDHCI_INT_SPACE_AVAIL);
7399 +               }
7400 +       }
7401 +       spin_unlock_irqrestore(&host->lock, flags);
7402 +}
7403 +
7404 +static irqreturn_t sdhci_bcm2708_dma_irq(int irq, void *dev_id)
7405 +{
7406 +       irqreturn_t result = IRQ_NONE;
7407 +       struct sdhci_host *host = dev_id;
7408 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7409 +       u32 dma_cs; /* control and status register */
7410 +       unsigned long flags;
7411 +
7412 +       BUG_ON(NULL == dev_id);
7413 +       BUG_ON(NULL == host_priv->dma_chan_base);
7414 +
7415 +       spin_lock_irqsave(&host->lock, flags);
7416 +
7417 +       dma_cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS);
7418 +
7419 +       if (dma_cs & BCM2708_DMA_ERR) {
7420 +               unsigned long debug;
7421 +               debug = readl(host_priv->dma_chan_base +
7422 +                             BCM2708_DMA_DEBUG);
7423 +               printk(KERN_ERR "%s: DMA error - CS %lX DEBUG %lX\n",
7424 +                      mmc_hostname(host->mmc), (unsigned long)dma_cs,
7425 +                      (unsigned long)debug);
7426 +               /* reset error */
7427 +               writel(debug, host_priv->dma_chan_base +
7428 +                      BCM2708_DMA_DEBUG);
7429 +       }
7430 +       if (dma_cs & BCM2708_DMA_INT) {
7431 +               /* acknowledge interrupt */
7432 +               writel(BCM2708_DMA_INT,
7433 +                      host_priv->dma_chan_base + BCM2708_DMA_CS);
7434 +
7435 +               dsb(); /* ARM data synchronization (push) operation */
7436 +
7437 +               if (!host_priv->dma_wanted) {
7438 +                       /* ignore this interrupt - it was reset */
7439 +                       printk(KERN_INFO "%s: DMA IRQ %X ignored - "
7440 +                              "results were reset\n",
7441 +                              mmc_hostname(host->mmc), dma_cs);
7442 +#ifdef CHECK_DMA_USE
7443 +                       printk(KERN_INFO "%s: now %"FMT_HPT
7444 +                              " started %lu reset %lu stopped %lu\n",
7445 +                              mmc_hostname(host->mmc), hptime(),
7446 +                              since_ns(host_priv->when_started),
7447 +                              since_ns(host_priv->when_reset),
7448 +                              since_ns(host_priv->when_stopped));
7449 +                       host_priv->dmas_pending--;
7450 +#endif
7451 +               } else
7452 +                       sdhci_bcm2708_dma_complete_irq(host, dma_cs);
7453 +
7454 +               result = IRQ_HANDLED;
7455 +       }
7456 +
7457 +       spin_unlock_irqrestore(&host->lock, flags);
7458 +
7459 +       return result;
7460 +}
7461 +#endif /* CONFIG_MMC_SDHCI_BCM2708_DMA */
7462 +
7463 +
7464 +/***************************************************************************** \
7465 + *                                                                          *
7466 + * Device Attributes                                                        *
7467 + *                                                                          *
7468 +\*****************************************************************************/
7469 +
7470 +
7471 +/**
7472 + * Show the DMA-using status
7473 + */
7474 +static ssize_t attr_dma_show(struct device *_dev,
7475 +                            struct device_attribute *attr, char *buf)
7476 +{
7477 +       struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7478 +
7479 +       if (host) {
7480 +               int use_dma = (host->flags & SDHCI_USE_PLATDMA? 1:0);
7481 +               return sprintf(buf, "%d\n", use_dma);
7482 +       } else
7483 +               return -EINVAL;
7484 +}
7485 +
7486 +/**
7487 + * Set the DMA-using status
7488 + */
7489 +static ssize_t attr_dma_store(struct device *_dev,
7490 +                             struct device_attribute *attr,
7491 +                             const char *buf, size_t count)
7492 +{
7493 +       struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7494 +
7495 +       if (host) {
7496 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7497 +               int on = simple_strtol(buf, NULL, 0);
7498 +               if (on) {
7499 +                       host->flags |= SDHCI_USE_PLATDMA;
7500 +                       printk(KERN_INFO "%s: DMA enabled\n",
7501 +                              mmc_hostname(host->mmc));
7502 +               } else {
7503 +                       host->flags &= ~(SDHCI_USE_PLATDMA | SDHCI_REQ_USE_DMA);
7504 +                       printk(KERN_INFO "%s: DMA disabled\n",
7505 +                              mmc_hostname(host->mmc));
7506 +               }
7507 +#endif
7508 +               return count;
7509 +       } else
7510 +               return -EINVAL;
7511 +}
7512 +
7513 +static DEVICE_ATTR(use_dma, S_IRUGO | S_IWUGO, attr_dma_show, attr_dma_store);
7514 +
7515 +
7516 +/**
7517 + * Show the DMA wait states used
7518 + */
7519 +static ssize_t attr_dmawait_show(struct device *_dev,
7520 +                                struct device_attribute *attr, char *buf)
7521 +{
7522 +       struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7523 +
7524 +       if (host) {
7525 +               struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7526 +               int dmawait = host_priv->dma_waits;
7527 +               return sprintf(buf, "%d\n", dmawait);
7528 +       } else
7529 +               return -EINVAL;
7530 +}
7531 +
7532 +/**
7533 + * Set the DMA wait state used
7534 + */
7535 +static ssize_t attr_dmawait_store(struct device *_dev,
7536 +                                 struct device_attribute *attr,
7537 +                                 const char *buf, size_t count)
7538 +{
7539 +       struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7540 +
7541 +       if (host) {
7542 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7543 +               struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7544 +               int dma_waits = simple_strtol(buf, NULL, 0);
7545 +               if (dma_waits >= 0 && dma_waits < 32)
7546 +                        host_priv->dma_waits = dma_waits;
7547 +               else
7548 +                       printk(KERN_ERR "%s: illegal dma_waits value - %d",
7549 +                              mmc_hostname(host->mmc), dma_waits);
7550 +#endif
7551 +               return count;
7552 +       } else
7553 +               return -EINVAL;
7554 +}
7555 +
7556 +static DEVICE_ATTR(dma_wait, S_IRUGO | S_IWUGO,
7557 +                   attr_dmawait_show, attr_dmawait_store);
7558 +
7559 +
7560 +/**
7561 + * Show the DMA-using status
7562 + */
7563 +static ssize_t attr_status_show(struct device *_dev,
7564 +                               struct device_attribute *attr, char *buf)
7565 +{
7566 +       struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7567 +
7568 +       if (host) {
7569 +               struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7570 +               return sprintf(buf,
7571 +                              "present: yes\n"
7572 +                              "power: %s\n"
7573 +                              "clock: %u Hz\n"
7574 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7575 +                              "dma: %s (%d waits)\n",
7576 +#else
7577 +                              "dma: unconfigured\n",
7578 +#endif
7579 +                              "always on",
7580 +                              host->clock
7581 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7582 +                              , (host->flags & SDHCI_USE_PLATDMA)? "on": "off"
7583 +                               , host_priv->dma_waits
7584 +#endif
7585 +                              );
7586 +       } else
7587 +               return -EINVAL;
7588 +}
7589 +
7590 +static DEVICE_ATTR(status, S_IRUGO, attr_status_show, NULL);
7591 +
7592 +/***************************************************************************** \
7593 + *                                                                          *
7594 + * Power Management                                                         *
7595 + *                                                                          *
7596 +\*****************************************************************************/
7597 +
7598 +
7599 +#ifdef CONFIG_PM
7600 +static int sdhci_bcm2708_suspend(struct platform_device *dev, pm_message_t state)
7601 +{
7602 +       struct sdhci_host *host = (struct sdhci_host *)
7603 +                                 platform_get_drvdata(dev);
7604 +       int ret = 0;
7605 +
7606 +       if (host->mmc) {
7607 +               ret = mmc_suspend_host(host->mmc);
7608 +       }
7609 +
7610 +       return ret;
7611 +}
7612 +
7613 +static int sdhci_bcm2708_resume(struct platform_device *dev)
7614 +{
7615 +       struct sdhci_host *host = (struct sdhci_host *)
7616 +                                 platform_get_drvdata(dev);
7617 +       int ret = 0;
7618 +
7619 +       if (host->mmc) {
7620 +               ret = mmc_resume_host(host->mmc);
7621 +       }
7622 +
7623 +       return ret;
7624 +}
7625 +#endif
7626 +
7627 +
7628 +/*****************************************************************************\
7629 + *                                                                           *
7630 + * Device quirk functions. Implemented as local ops because the flags        *
7631 + * field is out of space with newer kernels. This implementation can be      *
7632 + * back ported to older kernels as well.                                     *
7633 +\****************************************************************************/
7634 +static unsigned int sdhci_bcm2708_quirk_extra_ints(struct sdhci_host *host)
7635 +{
7636 +        return 1;
7637 +}
7638 +
7639 +static unsigned int sdhci_bcm2708_quirk_spurious_crc(struct sdhci_host *host)
7640 +{
7641 +        return 1;
7642 +}
7643 +
7644 +static unsigned int sdhci_bcm2708_quirk_voltage_broken(struct sdhci_host *host)
7645 +{
7646 +        return 1;
7647 +}
7648 +
7649 +static unsigned int sdhci_bcm2708_uhs_broken(struct sdhci_host *host)
7650 +{
7651 +        return 1;
7652 +}
7653 +
7654 +/***************************************************************************** \
7655 + *                                                                          *
7656 + * Device ops                                                               *
7657 + *                                                                          *
7658 +\*****************************************************************************/
7659 +
7660 +static struct sdhci_ops sdhci_bcm2708_ops = {
7661 +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
7662 +       .read_l = sdhci_bcm2708_readl,
7663 +       .read_w = sdhci_bcm2708_readw,
7664 +       .read_b = sdhci_bcm2708_readb,
7665 +       .write_l = sdhci_bcm2708_writel,
7666 +       .write_w = sdhci_bcm2708_writew,
7667 +       .write_b = sdhci_bcm2708_writeb,
7668 +#else
7669 +#error The BCM2708 SDHCI driver needs CONFIG_MMC_SDHCI_IO_ACCESSORS to be set
7670 +#endif
7671 +       //.enable_dma = NULL,
7672 +       .set_clock = sdhci_bcm2708_set_clock,
7673 +       .get_max_clock = sdhci_bcm2708_get_max_clock,
7674 +       //.get_min_clock = NULL,
7675 +       .get_timeout_clock = sdhci_bcm2708_get_timeout_clock,
7676 +
7677 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7678 +       // Platform DMA operations
7679 +       .pdma_able  = sdhci_bcm2708_platdma_dmaable,
7680 +       .pdma_avail = sdhci_bcm2708_platdma_avail,
7681 +       .pdma_reset = sdhci_bcm2708_platdma_reset,
7682 +#endif
7683 +       .extra_ints = sdhci_bcm2708_quirk_extra_ints,
7684 +       .spurious_crc_acmd51 = sdhci_bcm2708_quirk_spurious_crc,
7685 +       .voltage_broken = sdhci_bcm2708_quirk_voltage_broken,
7686 +       .uhs_broken = sdhci_bcm2708_uhs_broken,
7687 +};
7688 +
7689 +/*****************************************************************************\
7690 + *                                                                          *
7691 + * Device probing/removal                                                   *
7692 + *                                                                          *
7693 +\*****************************************************************************/
7694 +
7695 +static int sdhci_bcm2708_probe(struct platform_device *pdev)
7696 +{
7697 +       struct sdhci_host *host;
7698 +       struct resource *iomem;
7699 +       struct sdhci_bcm2708_priv *host_priv;
7700 +       int ret;
7701 +
7702 +       BUG_ON(pdev == NULL);
7703 +
7704 +       iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7705 +       if (!iomem) {
7706 +               ret = -ENOMEM;
7707 +               goto err;
7708 +       }
7709 +
7710 +       if (resource_size(iomem) != 0x100)
7711 +               dev_err(&pdev->dev, "Invalid iomem size. You may "
7712 +                       "experience problems.\n");
7713 +
7714 +       if (pdev->dev.parent)
7715 +               host = sdhci_alloc_host(pdev->dev.parent,
7716 +                                       sizeof(struct sdhci_bcm2708_priv));
7717 +       else
7718 +               host = sdhci_alloc_host(&pdev->dev,
7719 +                                       sizeof(struct sdhci_bcm2708_priv));
7720 +
7721 +       if (IS_ERR(host)) {
7722 +               ret = PTR_ERR(host);
7723 +               goto err;
7724 +       }
7725 +
7726 +       host->hw_name = "BCM2708_Arasan";
7727 +       host->ops = &sdhci_bcm2708_ops;
7728 +       host->irq = platform_get_irq(pdev, 0);
7729 +
7730 +       host->quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
7731 +                      SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
7732 +                      SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
7733 +                      SDHCI_QUIRK_NONSTANDARD_CLOCK;
7734 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7735 +       host->flags = SDHCI_USE_PLATDMA;
7736 +#endif
7737 +
7738 +       if (!request_mem_region(iomem->start, resource_size(iomem),
7739 +                               mmc_hostname(host->mmc))) {
7740 +               dev_err(&pdev->dev, "cannot request region\n");
7741 +               ret = -EBUSY;
7742 +               goto err_request;
7743 +       }
7744 +
7745 +       host->ioaddr = ioremap(iomem->start, resource_size(iomem));
7746 +       if (!host->ioaddr) {
7747 +               dev_err(&pdev->dev, "failed to remap registers\n");
7748 +               ret = -ENOMEM;
7749 +               goto err_remap;
7750 +       }
7751 +
7752 +       host_priv = SDHCI_HOST_PRIV(host);
7753 +
7754 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7755 +       host_priv->dma_wanted = 0;
7756 +#ifdef CHECK_DMA_USE
7757 +       host_priv->dmas_pending = 0;
7758 +       host_priv->when_started = 0;
7759 +       host_priv->when_reset = 0;
7760 +       host_priv->when_stopped = 0;
7761 +#endif
7762 +       host_priv->sg_ix = 0;
7763 +       host_priv->sg_done = 0;
7764 +       host_priv->complete = NULL;
7765 +       host_priv->dma_waits = SDHCI_BCM_DMA_WAITS;
7766 +
7767 +       host_priv->cb_base = dma_alloc_writecombine(&pdev->dev, SZ_4K,
7768 +                                                   &host_priv->cb_handle,
7769 +                                                   GFP_KERNEL);
7770 +       if (!host_priv->cb_base) {
7771 +               dev_err(&pdev->dev, "cannot allocate DMA CBs\n");
7772 +               ret = -ENOMEM;
7773 +               goto err_alloc_cb;
7774 +       }
7775 +
7776 +       ret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST,
7777 +                                &host_priv->dma_chan_base,
7778 +                                &host_priv->dma_irq);
7779 +       if (ret < 0) {
7780 +               dev_err(&pdev->dev, "couldn't allocate a DMA channel\n");
7781 +               goto err_add_dma;
7782 +       }
7783 +       host_priv->dma_chan = ret;
7784 +
7785 +       ret = request_irq(host_priv->dma_irq, sdhci_bcm2708_dma_irq,
7786 +                         IRQF_SHARED, DRIVER_NAME " (dma)", host);
7787 +       if (ret) {
7788 +               dev_err(&pdev->dev, "cannot set DMA IRQ\n");
7789 +               goto err_add_dma_irq;
7790 +       }
7791 +       DBG("DMA CBs %p handle %08X DMA%d %p DMA IRQ %d\n",
7792 +           host_priv->cb_base, (unsigned)host_priv->cb_handle,
7793 +           host_priv->dma_chan, host_priv->dma_chan_base,
7794 +           host_priv->dma_irq);
7795 +
7796 +       host->mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
7797 +#endif
7798 +
7799 +       ret = sdhci_add_host(host);
7800 +       if (ret)
7801 +               goto err_add_host;
7802 +
7803 +       platform_set_drvdata(pdev, host);
7804 +       ret = device_create_file(&pdev->dev, &dev_attr_use_dma);
7805 +       ret = device_create_file(&pdev->dev, &dev_attr_dma_wait);
7806 +       ret = device_create_file(&pdev->dev, &dev_attr_status);
7807 +
7808 +       printk(KERN_INFO "%s: BCM2708 SDHC host at 0x%08llx DMA %d IRQ %d\n",
7809 +              mmc_hostname(host->mmc), (unsigned long long)iomem->start,
7810 +              host_priv->dma_chan, host_priv->dma_irq);
7811 +
7812 +       return 0;
7813 +
7814 +err_add_host:
7815 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7816 +       free_irq(host_priv->dma_irq, host);
7817 +err_add_dma_irq:
7818 +       bcm_dma_chan_free(host_priv->dma_chan);
7819 +err_add_dma:
7820 +       dma_free_writecombine(&pdev->dev, SZ_4K, host_priv->cb_base,
7821 +                             host_priv->cb_handle);
7822 +err_alloc_cb:
7823 +#endif
7824 +       iounmap(host->ioaddr);
7825 +err_remap:
7826 +       release_mem_region(iomem->start, resource_size(iomem));
7827 +err_request:
7828 +       sdhci_free_host(host);
7829 +err:
7830 +       dev_err(&pdev->dev, "probe failed, err %d\n", ret);
7831 +       return ret;
7832 +}
7833 +
7834 +static int sdhci_bcm2708_remove(struct platform_device *pdev)
7835 +{
7836 +       struct sdhci_host *host = platform_get_drvdata(pdev);
7837 +       struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7838 +       struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7839 +       int dead;
7840 +       u32 scratch;
7841 +
7842 +       dead = 0;
7843 +       scratch = sdhci_bcm2708_readl(host, SDHCI_INT_STATUS);
7844 +       if (scratch == (u32)-1)
7845 +               dead = 1;
7846 +
7847 +       device_remove_file(&pdev->dev, &dev_attr_status);
7848 +       device_remove_file(&pdev->dev, &dev_attr_dma_wait);
7849 +       device_remove_file(&pdev->dev, &dev_attr_use_dma);
7850 +
7851 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7852 +       free_irq(host_priv->dma_irq, host);
7853 +       dma_free_writecombine(&pdev->dev, SZ_4K, host_priv->cb_base,
7854 +                             host_priv->cb_handle);
7855 +#endif
7856 +       sdhci_remove_host(host, dead);
7857 +       iounmap(host->ioaddr);
7858 +       release_mem_region(iomem->start, resource_size(iomem));
7859 +       sdhci_free_host(host);
7860 +       platform_set_drvdata(pdev, NULL);
7861 +
7862 +       return 0;
7863 +}
7864 +
7865 +static struct platform_driver sdhci_bcm2708_driver = {
7866 +       .driver = {
7867 +               .name   = DRIVER_NAME,
7868 +               .owner  = THIS_MODULE,
7869 +       },
7870 +       .probe          = sdhci_bcm2708_probe,
7871 +       .remove         = sdhci_bcm2708_remove,
7872 +
7873 +#ifdef CONFIG_PM
7874 +       .suspend = sdhci_bcm2708_suspend,
7875 +       .resume = sdhci_bcm2708_resume,
7876 +#endif
7877 +
7878 +};
7879 +
7880 +/*****************************************************************************\
7881 + *                                                                          *
7882 + * Driver init/exit                                                         *
7883 + *                                                                          *
7884 +\*****************************************************************************/
7885 +
7886 +static int __init sdhci_drv_init(void)
7887 +{
7888 +       return platform_driver_register(&sdhci_bcm2708_driver);
7889 +}
7890 +
7891 +static void __exit sdhci_drv_exit(void)
7892 +{
7893 +       platform_driver_unregister(&sdhci_bcm2708_driver);
7894 +}
7895 +
7896 +module_init(sdhci_drv_init);
7897 +module_exit(sdhci_drv_exit);
7898 +
7899 +MODULE_DESCRIPTION("Secure Digital Host Controller Interface platform driver");
7900 +MODULE_AUTHOR("Broadcom <info@broadcom.com>");
7901 +MODULE_LICENSE("GPL v2");
7902 +MODULE_ALIAS("platform:"DRIVER_NAME);
7903 +
7904 --- a/drivers/mmc/host/sdhci.c
7905 +++ b/drivers/mmc/host/sdhci.c
7906 @@ -28,6 +28,7 @@
7907  #include <linux/mmc/mmc.h>
7908  #include <linux/mmc/host.h>
7909  #include <linux/mmc/card.h>
7910 +#include <linux/mmc/sd.h>
7911  #include <linux/mmc/slot-gpio.h>
7912
7913  #include "sdhci.h"
7914 @@ -315,7 +316,7 @@ static void sdhci_read_block_pio(struct
7915         u32 uninitialized_var(scratch);
7916         u8 *buf;
7917
7918 -       DBG("PIO reading\n");
7919 +       DBG("PIO reading %db\n", host->data->blksz);
7920
7921         blksize = host->data->blksz;
7922         chunk = 0;
7923 @@ -360,7 +361,7 @@ static void sdhci_write_block_pio(struct
7924         u32 scratch;
7925         u8 *buf;
7926
7927 -       DBG("PIO writing\n");
7928 +       DBG("PIO writing %db\n", host->data->blksz);
7929
7930         blksize = host->data->blksz;
7931         chunk = 0;
7932 @@ -399,19 +400,28 @@ static void sdhci_write_block_pio(struct
7933         local_irq_restore(flags);
7934  }
7935
7936 -static void sdhci_transfer_pio(struct sdhci_host *host)
7937 +static void sdhci_transfer_pio(struct sdhci_host *host, u32 intstate)
7938  {
7939         u32 mask;
7940 +       u32 state = 0;
7941 +       u32 intmask;
7942 +       int available;
7943
7944         BUG_ON(!host->data);
7945
7946         if (host->blocks == 0)
7947                 return;
7948
7949 -       if (host->data->flags & MMC_DATA_READ)
7950 +       if (host->data->flags & MMC_DATA_READ) {
7951                 mask = SDHCI_DATA_AVAILABLE;
7952 -       else
7953 +               intmask = SDHCI_INT_DATA_AVAIL;
7954 +       } else {
7955                 mask = SDHCI_SPACE_AVAILABLE;
7956 +               intmask = SDHCI_INT_SPACE_AVAIL;
7957 +       }
7958 +
7959 +       /* initially we can see whether we can procede using intstate */
7960 +       available = (intstate & intmask);
7961
7962         /*
7963          * Some controllers (JMicron JMB38x) mess up the buffer bits
7964 @@ -422,7 +432,7 @@ static void sdhci_transfer_pio(struct sd
7965                 (host->data->blocks == 1))
7966                 mask = ~0;
7967
7968 -       while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7969 +       while (available) {
7970                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
7971                         udelay(100);
7972
7973 @@ -434,9 +444,11 @@ static void sdhci_transfer_pio(struct sd
7974                 host->blocks--;
7975                 if (host->blocks == 0)
7976                         break;
7977 +               state = sdhci_readl(host, SDHCI_PRESENT_STATE);
7978 +               available = state & mask;
7979         }
7980
7981 -       DBG("PIO transfer complete.\n");
7982 +       DBG("PIO transfer complete - %d blocks left.\n", host->blocks);
7983  }
7984
7985  static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
7986 @@ -709,7 +721,9 @@ static void sdhci_set_transfer_irqs(stru
7987         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
7988         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
7989
7990 -       if (host->flags & SDHCI_REQ_USE_DMA)
7991 +       /* platform DMA will begin on receipt of PIO irqs */
7992 +       if ((host->flags & SDHCI_REQ_USE_DMA) &&
7993 +           !(host->flags & SDHCI_USE_PLATDMA))
7994                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
7995         else
7996                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
7997 @@ -741,44 +755,25 @@ static void sdhci_prepare_data(struct sd
7998         host->data_early = 0;
7999         host->data->bytes_xfered = 0;
8000
8001 -       if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
8002 +       if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA | SDHCI_USE_PLATDMA))
8003                 host->flags |= SDHCI_REQ_USE_DMA;
8004
8005         /*
8006          * FIXME: This doesn't account for merging when mapping the
8007          * scatterlist.
8008          */
8009 -       if (host->flags & SDHCI_REQ_USE_DMA) {
8010 -               int broken, i;
8011 -               struct scatterlist *sg;
8012 -
8013 -               broken = 0;
8014 -               if (host->flags & SDHCI_USE_ADMA) {
8015 -                       if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
8016 -                               broken = 1;
8017 -               } else {
8018 -                       if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
8019 -                               broken = 1;
8020 -               }
8021 -
8022 -               if (unlikely(broken)) {
8023 -                       for_each_sg(data->sg, sg, data->sg_len, i) {
8024 -                               if (sg->length & 0x3) {
8025 -                                       DBG("Reverting to PIO because of "
8026 -                                               "transfer size (%d)\n",
8027 -                                               sg->length);
8028 -                                       host->flags &= ~SDHCI_REQ_USE_DMA;
8029 -                                       break;
8030 -                               }
8031 -                       }
8032 -               }
8033 -       }
8034
8035         /*
8036          * The assumption here being that alignment is the same after
8037          * translation to device address space.
8038          */
8039 -       if (host->flags & SDHCI_REQ_USE_DMA) {
8040 +       if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_PLATDMA)) ==
8041 +           (SDHCI_REQ_USE_DMA | SDHCI_USE_PLATDMA)) {
8042 +
8043 +               if (! sdhci_platdma_dmaable(host, data))
8044 +                       host->flags &= ~SDHCI_REQ_USE_DMA;
8045 +
8046 +       } else if (host->flags & SDHCI_REQ_USE_DMA) {
8047                 int broken, i;
8048                 struct scatterlist *sg;
8049
8050 @@ -837,7 +832,8 @@ static void sdhci_prepare_data(struct sd
8051                                  */
8052                                 WARN_ON(1);
8053                                 host->flags &= ~SDHCI_REQ_USE_DMA;
8054 -                       } else {
8055 +                       } else
8056 +                       if (!(host->flags & SDHCI_USE_PLATDMA)) {
8057                                 WARN_ON(sg_cnt != 1);
8058                                 sdhci_writel(host, sg_dma_address(data->sg),
8059                                         SDHCI_DMA_ADDRESS);
8060 @@ -853,11 +849,13 @@ static void sdhci_prepare_data(struct sd
8061         if (host->version >= SDHCI_SPEC_200) {
8062                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
8063                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
8064 +               if (! (host->flags & SDHCI_USE_PLATDMA)) {
8065                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
8066                         (host->flags & SDHCI_USE_ADMA))
8067                         ctrl |= SDHCI_CTRL_ADMA32;
8068                 else
8069                         ctrl |= SDHCI_CTRL_SDMA;
8070 +               }
8071                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
8072         }
8073
8074 @@ -909,7 +907,8 @@ static void sdhci_set_transfer_mode(stru
8075
8076         if (data->flags & MMC_DATA_READ)
8077                 mode |= SDHCI_TRNS_READ;
8078 -       if (host->flags & SDHCI_REQ_USE_DMA)
8079 +       if ((host->flags & SDHCI_REQ_USE_DMA) &&
8080 +           !(host->flags & SDHCI_USE_PLATDMA))
8081                 mode |= SDHCI_TRNS_DMA;
8082
8083         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
8084 @@ -925,13 +924,16 @@ static void sdhci_finish_data(struct sdh
8085         host->data = NULL;
8086
8087         if (host->flags & SDHCI_REQ_USE_DMA) {
8088 -               if (host->flags & SDHCI_USE_ADMA)
8089 -                       sdhci_adma_table_post(host, data);
8090 -               else {
8091 +               /* we may have to abandon an ongoing platform DMA */
8092 +               if (host->flags & SDHCI_USE_PLATDMA)
8093 +                       sdhci_platdma_reset(host, data);
8094 +
8095 +               if (host->flags & (SDHCI_USE_PLATDMA | SDHCI_USE_SDMA)) {
8096                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
8097                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
8098                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
8099 -               }
8100 +               } else if (host->flags & SDHCI_USE_ADMA)
8101 +                        sdhci_adma_table_post(host, data);
8102         }
8103
8104         /*
8105 @@ -984,6 +986,12 @@ static void sdhci_send_command(struct sd
8106         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
8107                 mask |= SDHCI_DATA_INHIBIT;
8108
8109 +       if(host->ops->missing_status && (cmd->opcode == MMC_SEND_STATUS)) {
8110 +               timeout = 5000; // Really obscenely large delay to send the status, due to bug in controller
8111 +                               // which might cause the STATUS command to get stuck when a data operation is in flow
8112 +               mask |= SDHCI_DATA_INHIBIT;
8113 +       }
8114 +
8115         /* We shouldn't wait for data inihibit for stop commands, even
8116            though they might use busy signaling */
8117         if (host->mrq->data && (cmd == host->mrq->data->stop))
8118 @@ -1001,10 +1009,16 @@ static void sdhci_send_command(struct sd
8119                 timeout--;
8120                 mdelay(1);
8121         }
8122 +       DBG("send cmd %d - wait 0x%X irq 0x%x\n", cmd->opcode, mask,
8123 +           sdhci_readl(host, SDHCI_INT_STATUS));
8124
8125         mod_timer(&host->timer, jiffies + 10 * HZ);
8126
8127         host->cmd = cmd;
8128 +       if (host->last_cmdop == MMC_APP_CMD)
8129 +               host->last_cmdop = -cmd->opcode;
8130 +       else
8131 +               host->last_cmdop = cmd->opcode;
8132
8133         sdhci_prepare_data(host, cmd);
8134
8135 @@ -1470,7 +1484,7 @@ static void sdhci_do_set_ios(struct sdhc
8136         else
8137                 ctrl &= ~SDHCI_CTRL_HISPD;
8138
8139 -       if (host->version >= SDHCI_SPEC_300) {
8140 +       if (host->version >= SDHCI_SPEC_300 && !(host->ops->uhs_broken)) {
8141                 u16 clk, ctrl_2;
8142
8143                 /* In case of UHS-I modes, set High Speed Enable */
8144 @@ -2164,7 +2178,7 @@ static void sdhci_timeout_timer(unsigned
8145
8146         if (host->mrq) {
8147                 pr_err("%s: Timeout waiting for hardware "
8148 -                       "interrupt.\n", mmc_hostname(host->mmc));
8149 +                       "interrupt - cmd%d.\n", mmc_hostname(host->mmc), host->last_cmdop);
8150                 sdhci_dumpregs(host);
8151
8152                 if (host->data) {
8153 @@ -2209,10 +2223,13 @@ static void sdhci_cmd_irq(struct sdhci_h
8154         BUG_ON(intmask == 0);
8155
8156         if (!host->cmd) {
8157 +               if (!(host->ops->extra_ints)) {
8158                 pr_err("%s: Got command interrupt 0x%08x even "
8159                         "though no command operation was in progress.\n",
8160                         mmc_hostname(host->mmc), (unsigned)intmask);
8161                 sdhci_dumpregs(host);
8162 +               } else
8163 +                       DBG("cmd irq 0x%08x cmd complete\n", (unsigned)intmask);
8164                 return;
8165         }
8166
8167 @@ -2282,6 +2299,19 @@ static void sdhci_show_adma_error(struct
8168  static void sdhci_show_adma_error(struct sdhci_host *host) { }
8169  #endif
8170
8171 +static void sdhci_data_end(struct sdhci_host *host)
8172 +{
8173 +       if (host->cmd) {
8174 +               /*
8175 +                * Data managed to finish before the
8176 +                * command completed. Make sure we do
8177 +                * things in the proper order.
8178 +                */
8179 +               host->data_early = 1;
8180 +       } else
8181 +               sdhci_finish_data(host);
8182 +}
8183 +
8184  static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
8185  {
8186         u32 command;
8187 @@ -2311,23 +2341,39 @@ static void sdhci_data_irq(struct sdhci_
8188                         }
8189                 }
8190
8191 +               if (!(host->ops->extra_ints)) {
8192                 pr_err("%s: Got data interrupt 0x%08x even "
8193                         "though no data operation was in progress.\n",
8194                         mmc_hostname(host->mmc), (unsigned)intmask);
8195                 sdhci_dumpregs(host);
8196 +               } else
8197 +                       DBG("data irq 0x%08x but no data\n", (unsigned)intmask);
8198
8199                 return;
8200         }
8201
8202         if (intmask & SDHCI_INT_DATA_TIMEOUT)
8203                 host->data->error = -ETIMEDOUT;
8204 -       else if (intmask & SDHCI_INT_DATA_END_BIT)
8205 +       else if (intmask & SDHCI_INT_DATA_END_BIT) {
8206 +               DBG("end error in cmd %d\n", host->last_cmdop);
8207 +               if (host->ops->spurious_crc_acmd51 &&
8208 +                   host->last_cmdop == -SD_APP_SEND_SCR) {
8209 +                       DBG("ignoring spurious data_end_bit error\n");
8210 +                       intmask = SDHCI_INT_DATA_AVAIL|SDHCI_INT_DATA_END;
8211 +               } else
8212                 host->data->error = -EILSEQ;
8213 -       else if ((intmask & SDHCI_INT_DATA_CRC) &&
8214 +       } else if ((intmask & SDHCI_INT_DATA_CRC) &&
8215                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
8216 -                       != MMC_BUS_TEST_R)
8217 +                       != MMC_BUS_TEST_R) {
8218 +               DBG("crc error in cmd %d\n", host->last_cmdop);
8219 +               if (host->ops->spurious_crc_acmd51 &&
8220 +                               host->last_cmdop == -SD_APP_SEND_SCR) {
8221 +                       DBG("ignoring spurious data_crc_bit error\n");
8222 +                       intmask = SDHCI_INT_DATA_AVAIL|SDHCI_INT_DATA_END;
8223 +               } else {
8224                 host->data->error = -EILSEQ;
8225 -       else if (intmask & SDHCI_INT_ADMA_ERROR) {
8226 +               }
8227 +       } else if (intmask & SDHCI_INT_ADMA_ERROR) {
8228                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
8229                 sdhci_show_adma_error(host);
8230                 host->data->error = -EIO;
8231 @@ -2335,11 +2381,18 @@ static void sdhci_data_irq(struct sdhci_
8232                         host->ops->adma_workaround(host, intmask);
8233         }
8234
8235 -       if (host->data->error)
8236 +       if (host->data->error) {
8237 +               DBG("finish request early on error %d\n", host->data->error);
8238                 sdhci_finish_data(host);
8239 -       else {
8240 -               if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
8241 -                       sdhci_transfer_pio(host);
8242 +       } else {
8243 +               if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
8244 +                       if (host->flags & SDHCI_REQ_USE_DMA) {
8245 +                               /* possible only in PLATDMA mode */
8246 +                               sdhci_platdma_avail(host, &intmask,
8247 +                                               &sdhci_data_end);
8248 +                       } else
8249 +                               sdhci_transfer_pio(host, intmask);
8250 +               }
8251
8252                 /*
8253                  * We currently don't do anything fancy with DMA
8254 @@ -2368,18 +2421,8 @@ static void sdhci_data_irq(struct sdhci_
8255                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
8256                 }
8257
8258 -               if (intmask & SDHCI_INT_DATA_END) {
8259 -                       if (host->cmd) {
8260 -                               /*
8261 -                                * Data managed to finish before the
8262 -                                * command completed. Make sure we do
8263 -                                * things in the proper order.
8264 -                                */
8265 -                               host->data_early = 1;
8266 -                       } else {
8267 -                               sdhci_finish_data(host);
8268 -                       }
8269 -               }
8270 +               if (intmask & SDHCI_INT_DATA_END)
8271 +                       sdhci_data_end(host);
8272         }
8273  }
8274
8275 @@ -2435,6 +2478,22 @@ again:
8276                 tasklet_schedule(&host->card_tasklet);
8277         }
8278
8279 +       if (intmask & SDHCI_INT_ERROR_MASK & ~SDHCI_INT_ERROR)
8280 +               DBG("controller reports error 0x%x -"
8281 +                               "%s%s%s%s%s%s%s%s%s%s",
8282 +                               intmask,
8283 +                               intmask & SDHCI_INT_TIMEOUT? " timeout": "",
8284 +                               intmask & SDHCI_INT_CRC     ? " crc": "",
8285 +                               intmask & SDHCI_INT_END_BIT? " endbit": "",
8286 +                               intmask & SDHCI_INT_INDEX? " index": "",
8287 +                               intmask & SDHCI_INT_DATA_TIMEOUT? " data_timeout": "",
8288 +                               intmask & SDHCI_INT_DATA_CRC? " data_crc": "",
8289 +                               intmask & SDHCI_INT_DATA_END_BIT? " data_endbit": "",
8290 +                               intmask & SDHCI_INT_BUS_POWER? " buspower": "",
8291 +                               intmask & SDHCI_INT_ACMD12ERR? " acmd12": "",
8292 +                               intmask & SDHCI_INT_ADMA_ERROR? " adma": ""
8293 +                  );
8294 +
8295         if (intmask & SDHCI_INT_CMD_MASK) {
8296                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
8297                         SDHCI_INT_STATUS);
8298 @@ -2449,7 +2508,13 @@ again:
8299
8300         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
8301
8302 -       intmask &= ~SDHCI_INT_ERROR;
8303 +       if (intmask & SDHCI_INT_ERROR_MASK) {
8304 +               /* collect any uncovered errors */
8305 +               sdhci_writel(host, intmask & SDHCI_INT_ERROR_MASK,
8306 +                               SDHCI_INT_STATUS);
8307 +       }
8308 +
8309 +       intmask &= ~SDHCI_INT_ERROR_MASK;
8310
8311         if (intmask & SDHCI_INT_BUS_POWER) {
8312                 pr_err("%s: Card is consuming too much power!\n",
8313 @@ -2569,7 +2634,8 @@ int sdhci_resume_host(struct sdhci_host
8314  {
8315         int ret;
8316
8317 -       if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
8318 +       if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA |
8319 +                          SDHCI_USE_PLATDMA)) {
8320                 if (host->ops->enable_dma)
8321                         host->ops->enable_dma(host);
8322         }
8323 @@ -2785,14 +2851,16 @@ int sdhci_add_host(struct sdhci_host *ho
8324                 host->flags &= ~SDHCI_USE_ADMA;
8325         }
8326
8327 -       if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
8328 +       if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA |
8329 +                          SDHCI_USE_PLATDMA)) {
8330                 if (host->ops->enable_dma) {
8331                         if (host->ops->enable_dma(host)) {
8332                                 pr_warning("%s: No suitable DMA "
8333                                         "available. Falling back to PIO.\n",
8334                                         mmc_hostname(mmc));
8335                                 host->flags &=
8336 -                                       ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
8337 +                                       ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA |
8338 +                                         SDHCI_USE_PLATDMA);
8339                         }
8340                 }
8341         }
8342 @@ -3080,6 +3148,12 @@ int sdhci_add_host(struct sdhci_host *ho
8343                                    SDHCI_MAX_CURRENT_MULTIPLIER;
8344         }
8345
8346 +       if(host->ops->voltage_broken) {
8347 +               ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
8348 +               // Cannot support UHS modes if we are stuck at 3.3V;
8349 +               mmc->caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50);
8350 +       }
8351 +
8352         mmc->ocr_avail = ocr_avail;
8353         mmc->ocr_avail_sdio = ocr_avail;
8354         if (host->ocr_avail_sdio)
8355 @@ -3210,6 +3284,7 @@ int sdhci_add_host(struct sdhci_host *ho
8356
8357         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
8358                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
8359 +               (host->flags & SDHCI_USE_PLATDMA) ? "platform's DMA" :
8360                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
8361                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
8362
8363 --- a/drivers/mmc/host/sdhci.h
8364 +++ b/drivers/mmc/host/sdhci.h
8365 @@ -289,6 +289,20 @@ struct sdhci_ops {
8366         void    (*platform_reset_enter)(struct sdhci_host *host, u8 mask);
8367         void    (*platform_reset_exit)(struct sdhci_host *host, u8 mask);
8368         int     (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
8369 +
8370 +       int             (*pdma_able)(struct sdhci_host *host,
8371 +                                    struct mmc_data *data);
8372 +       void            (*pdma_avail)(struct sdhci_host *host,
8373 +                                     unsigned int *ref_intmask,
8374 +                                     void(*complete)(struct sdhci_host *));
8375 +       void            (*pdma_reset)(struct sdhci_host *host,
8376 +                                     struct mmc_data *data);
8377 +       unsigned int    (*extra_ints)(struct sdhci_host *host);
8378 +       unsigned int    (*spurious_crc_acmd51)(struct sdhci_host *host);
8379 +       unsigned int    (*voltage_broken)(struct sdhci_host *host);
8380 +       unsigned int    (*uhs_broken)(struct sdhci_host *host);
8381 +       unsigned int    (*missing_status)(struct sdhci_host *host);
8382 +
8383         void    (*hw_reset)(struct sdhci_host *host);
8384         void    (*platform_suspend)(struct sdhci_host *host);
8385         void    (*platform_resume)(struct sdhci_host *host);
8386 @@ -399,6 +413,29 @@ extern int sdhci_resume_host(struct sdhc
8387  extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
8388  #endif
8389
8390 +static inline int /*bool*/
8391 +sdhci_platdma_dmaable(struct sdhci_host *host, struct mmc_data *data)
8392 +{
8393 +       if (host->ops->pdma_able)
8394 +               return host->ops->pdma_able(host, data);
8395 +       else
8396 +               return 1;
8397 +}
8398 +static inline void
8399 +sdhci_platdma_avail(struct sdhci_host *host, unsigned int *ref_intmask,
8400 +               void(*completion_callback)(struct sdhci_host *))
8401 +{
8402 +       if (host->ops->pdma_avail)
8403 +               host->ops->pdma_avail(host, ref_intmask, completion_callback);
8404 +}
8405 +
8406 +static inline void
8407 +sdhci_platdma_reset(struct sdhci_host *host, struct mmc_data *data)
8408 +{
8409 +       if (host->ops->pdma_reset)
8410 +               host->ops->pdma_reset(host, data);
8411 +}
8412 +
8413  #ifdef CONFIG_PM_RUNTIME
8414  extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
8415  extern int sdhci_runtime_resume_host(struct sdhci_host *host);
8416 --- a/include/linux/mmc/sdhci.h
8417 +++ b/include/linux/mmc/sdhci.h
8418 @@ -128,6 +128,7 @@ struct sdhci_host {
8419  #define SDHCI_SDIO_IRQ_ENABLED (1<<9)  /* SDIO irq enabled */
8420  #define SDHCI_HS200_NEEDS_TUNING (1<<10)       /* HS200 needs tuning */
8421  #define SDHCI_USING_RETUNING_TIMER (1<<11)     /* Host is using a retuning timer for the card */
8422 +#define SDHCI_USE_PLATDMA       (1<<12) /* Host uses 3rd party DMA */
8423
8424         unsigned int version;   /* SDHCI spec. version */
8425
8426 @@ -142,6 +143,7 @@ struct sdhci_host {
8427
8428         struct mmc_request *mrq;        /* Current request */
8429         struct mmc_command *cmd;        /* Current command */
8430 +       int     last_cmdop;     /* Opcode of last cmd sent */
8431         struct mmc_data *data;  /* Current data request */
8432         unsigned int data_early:1;      /* Data finished before cmd */
8433