2 * Low-Level PCI and SB support for BCM47xx (Linux support code)
4 * Copyright 2006, Broadcom Corporation
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12 * $Id: pcibios.c,v 1.1.1.9 2006/02/27 03:42:55 honor Exp $
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
24 #include <asm/paccess.h>
36 /* Global SB handle */
37 extern sb_t *bcm947xx_sbh;
38 extern spinlock_t bcm947xx_sbh_lock;
41 #define sbh bcm947xx_sbh
42 #define sbh_lock bcm947xx_sbh_lock
45 sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
50 spin_lock_irqsave(&sbh_lock, flags);
51 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
52 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
53 spin_unlock_irqrestore(&sbh_lock, flags);
54 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
58 sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
63 spin_lock_irqsave(&sbh_lock, flags);
64 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
65 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
66 spin_unlock_irqrestore(&sbh_lock, flags);
67 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
71 sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
76 spin_lock_irqsave(&sbh_lock, flags);
77 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
78 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
79 spin_unlock_irqrestore(&sbh_lock, flags);
80 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
84 sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
89 spin_lock_irqsave(&sbh_lock, flags);
90 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
91 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
92 spin_unlock_irqrestore(&sbh_lock, flags);
93 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
97 sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
102 spin_lock_irqsave(&sbh_lock, flags);
103 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
104 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
105 spin_unlock_irqrestore(&sbh_lock, flags);
106 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
110 sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
115 spin_lock_irqsave(&sbh_lock, flags);
116 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
117 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
118 spin_unlock_irqrestore(&sbh_lock, flags);
119 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
122 static struct pci_ops pcibios_ops = {
123 sbpci_read_config_byte,
124 sbpci_read_config_word,
125 sbpci_read_config_dword,
126 sbpci_write_config_byte,
127 sbpci_write_config_word,
128 sbpci_write_config_dword
137 if (!(sbh = sb_kattach()))
138 panic("sb_kattach failed");
139 spin_lock_init(&sbh_lock);
141 spin_lock_irqsave(&sbh_lock, flags);
143 spin_unlock_irqrestore(&sbh_lock, flags);
145 set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
146 mdelay(300); /* workaround for atheros cards */
148 /* Scan the SB bus */
149 pci_scan_bus(0, &pcibios_ops, NULL);
154 pcibios_setup(char *str)
156 if (!strncmp(str, "ban=", 4)) {
157 sbpci_ban(simple_strtoul(str + 4, NULL, 0));
164 static u32 pci_iobase = 0x100;
165 static u32 pci_membase = SB_PCI_DMA;
166 static u32 pcmcia_membase = 0x40004000;
169 pcibios_fixup_bus(struct pci_bus *b)
171 struct list_head *ln;
173 struct resource *res;
178 printk("PCI: Fixing up bus %d\n", b->number);
181 if (b->number == 0) {
182 for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
184 /* Fix up interrupt lines */
185 pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
187 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
191 /* Fix up external PCI */
193 for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
195 /* Fix up resource bases */
196 for (pos = 0; pos < 6; pos++) {
197 res = &d->resource[pos];
198 base = (res->flags & IORESOURCE_IO) ? &pci_iobase : ((b->number == 2) ? &pcmcia_membase : &pci_membase);
200 size = res->end - res->start + 1;
201 if (*base & (size - 1))
202 *base = (*base + size) & ~(size - 1);
204 res->end = res->start + size - 1;
206 pci_write_config_dword(d,
207 PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
209 /* Fix up PCI bridge BAR0 only */
210 if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
213 /* Fix up interrupt lines */
214 if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
215 d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
216 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
222 pcibios_assign_all_busses(void)
228 pcibios_align_resource(void *data, struct resource *res,
229 unsigned long size, unsigned long align)
234 pcibios_enable_resources(struct pci_dev *dev)
240 /* External PCI only */
241 if (dev->bus->number == 0)
244 pci_read_config_word(dev, PCI_COMMAND, &cmd);
246 for (idx = 0; idx < 6; idx++) {
247 r = &dev->resource[idx];
248 if (r->flags & IORESOURCE_IO)
249 cmd |= PCI_COMMAND_IO;
250 if (r->flags & IORESOURCE_MEM)
251 cmd |= PCI_COMMAND_MEMORY;
253 if (dev->resource[PCI_ROM_RESOURCE].start)
254 cmd |= PCI_COMMAND_MEMORY;
255 if (cmd != old_cmd) {
256 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
257 pci_write_config_word(dev, PCI_COMMAND, cmd);
263 pcibios_enable_device(struct pci_dev *dev, int mask)
269 /* External PCI device enable */
270 if (dev->bus->number != 0)
271 return pcibios_enable_resources(dev);
273 /* These cores come out of reset enabled */
274 if (dev->device == SB_MIPS ||
275 dev->device == SB_MIPS33 ||
276 dev->device == SB_EXTIF ||
277 dev->device == SB_CC)
280 spin_lock_irqsave(&sbh_lock, flags);
281 coreidx = sb_coreidx(sbh);
282 regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
284 return PCIBIOS_DEVICE_NOT_FOUND;
287 * The USB core requires a special bit to be set during core
288 * reset to enable host (OHCI) mode. Resetting the SB core in
289 * pcibios_enable_device() is a hack for compatibility with
290 * vanilla usb-ohci so that it does not have to know about
291 * SB. A driver that wants to use the USB core in device mode
292 * should know about SB and should reset the bit back to 0
293 * after calling pcibios_enable_device().
295 if (sb_coreid(sbh) == SB_USB) {
296 sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
297 sb_core_reset(sbh, 1 << 29, 0);
300 * USB 2.0 special considerations:
302 * 1. Since the core supports both OHCI and EHCI functions, it must
303 * only be reset once.
305 * 2. In addition to the standard SB reset sequence, the Host Control
306 * Register must be programmed to bring the USB core and various
307 * phy components out of reset.
309 else if (sb_coreid(sbh) == SB_USB20H) {
310 if (!sb_iscoreup(sbh)) {
311 sb_core_reset(sbh, 0, 0);
312 writel(0x7FF, (ulong)regs + 0x200);
316 sb_core_reset(sbh, 0, 0);
318 sb_setcoreidx(sbh, coreidx);
319 spin_unlock_irqrestore(&sbh_lock, flags);
325 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
326 struct resource *res, int resource)
328 unsigned long where, size;
331 /* External PCI only */
332 if (dev->bus->number == 0)
335 where = PCI_BASE_ADDRESS_0 + (resource * 4);
336 size = res->end - res->start;
337 pci_read_config_dword(dev, where, ®);
339 if (dev->bus->number == 1)
340 reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
344 pci_write_config_dword(dev, where, reg);
348 quirk_sbpci_bridge(struct pci_dev *dev)
350 if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
353 printk("PCI: Fixing up bridge\n");
355 /* Enable PCI bridge bus mastering and memory space */
357 pcibios_enable_resources(dev);
359 /* Enable PCI bridge BAR1 prefetch and burst */
360 pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
363 struct pci_fixup pcibios_fixups[] = {
364 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
369 * If we set up a device for bus mastering, we need to check the latency
370 * timer as certain crappy BIOSes forget to set it properly.
372 unsigned int pcibios_max_latency = 255;
374 void pcibios_set_master(struct pci_dev *dev)
377 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
379 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
380 else if (lat > pcibios_max_latency)
381 lat = pcibios_max_latency;
384 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
385 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);