target/linux/bcm53xx/patches-3.14/003-mtd-spi-nor-from-3.19.patch

   1 --- a/drivers/mtd/spi-nor/spi-nor.c
   2 +++ b/drivers/mtd/spi-nor/spi-nor.c
   3 @@ -26,7 +26,38 @@
   4  /* Define max times to check status register before we give up. */
   5  #define        MAX_READY_WAIT_JIFFIES  (40 * HZ) /* M25P16 specs 40s max chip erase */
   6
   7 -#define JEDEC_MFR(_jedec_id)   ((_jedec_id) >> 16)
   8 +#define SPI_NOR_MAX_ID_LEN     6
   9 +
  10 +struct flash_info {
  11 +       /*
  12 +        * This array stores the ID bytes.
  13 +        * The first three bytes are the JEDIC ID.
  14 +        * JEDEC ID zero means "no ID" (mostly older chips).
  15 +        */
  16 +       u8              id[SPI_NOR_MAX_ID_LEN];
  17 +       u8              id_len;
  18 +
  19 +       /* The size listed here is what works with SPINOR_OP_SE, which isn't
  20 +        * necessarily called a "sector" by the vendor.
  21 +        */
  22 +       unsigned        sector_size;
  23 +       u16             n_sectors;
  24 +
  25 +       u16             page_size;
  26 +       u16             addr_width;
  27 +
  28 +       u16             flags;
  29 +#define        SECT_4K                 0x01    /* SPINOR_OP_BE_4K works uniformly */
  30 +#define        SPI_NOR_NO_ERASE        0x02    /* No erase command needed */
  31 +#define        SST_WRITE               0x04    /* use SST byte programming */
  32 +#define        SPI_NOR_NO_FR           0x08    /* Can't do fastread */
  33 +#define        SECT_4K_PMC             0x10    /* SPINOR_OP_BE_4K_PMC works uniformly */
  34 +#define        SPI_NOR_DUAL_READ       0x20    /* Flash supports Dual Read */
  35 +#define        SPI_NOR_QUAD_READ       0x40    /* Flash supports Quad Read */
  36 +#define        USE_FSR                 0x80    /* use flag status register */
  37 +};
  38 +
  39 +#define JEDEC_MFR(info)        ((info)->id[0])
  40
  41  static const struct spi_device_id *spi_nor_match_id(const char *name);
  42
  43 @@ -98,7 +129,7 @@ static inline int spi_nor_read_dummy_cyc
  44         case SPI_NOR_FAST:
  45         case SPI_NOR_DUAL:
  46         case SPI_NOR_QUAD:
  47 -               return 1;
  48 +               return 8;
  49         case SPI_NOR_NORMAL:
  50                 return 0;
  51         }
  52 @@ -138,13 +169,14 @@ static inline struct spi_nor *mtd_to_spi
  53  }
  54
  55  /* Enable/disable 4-byte addressing mode. */
  56 -static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable)
  57 +static inline int set_4byte(struct spi_nor *nor, struct flash_info *info,
  58 +                           int enable)
  59  {
  60         int status;
  61         bool need_wren = false;
  62         u8 cmd;
  63
  64 -       switch (JEDEC_MFR(jedec_id)) {
  65 +       switch (JEDEC_MFR(info)) {
  66         case CFI_MFR_ST: /* Micron, actually */
  67                 /* Some Micron need WREN command; all will accept it */
  68                 need_wren = true;
  69 @@ -165,81 +197,74 @@ static inline int set_4byte(struct spi_n
  70                 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
  71         }
  72  }
  73 -
  74 -static int spi_nor_wait_till_ready(struct spi_nor *nor)
  75 +static inline int spi_nor_sr_ready(struct spi_nor *nor)
  76  {
  77 -       unsigned long deadline;
  78 -       int sr;
  79 -
  80 -       deadline = jiffies + MAX_READY_WAIT_JIFFIES;
  81 -
  82 -       do {
  83 -               cond_resched();
  84 +       int sr = read_sr(nor);
  85 +       if (sr < 0)
  86 +               return sr;
  87 +       else
  88 +               return !(sr & SR_WIP);
  89 +}
  90
  91 -               sr = read_sr(nor);
  92 -               if (sr < 0)
  93 -                       break;
  94 -               else if (!(sr & SR_WIP))
  95 -                       return 0;
  96 -       } while (!time_after_eq(jiffies, deadline));
  97 +static inline int spi_nor_fsr_ready(struct spi_nor *nor)
  98 +{
  99 +       int fsr = read_fsr(nor);
 100 +       if (fsr < 0)
 101 +               return fsr;
 102 +       else
 103 +               return fsr & FSR_READY;
 104 +}
 105
 106 -       return -ETIMEDOUT;
 107 +static int spi_nor_ready(struct spi_nor *nor)
 108 +{
 109 +       int sr, fsr;
 110 +       sr = spi_nor_sr_ready(nor);
 111 +       if (sr < 0)
 112 +               return sr;
 113 +       fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
 114 +       if (fsr < 0)
 115 +               return fsr;
 116 +       return sr && fsr;
 117  }
 118
 119 -static int spi_nor_wait_till_fsr_ready(struct spi_nor *nor)
 120 +/*
 121 + * Service routine to read status register until ready, or timeout occurs.
 122 + * Returns non-zero if error.
 123 + */
 124 +static int spi_nor_wait_till_ready(struct spi_nor *nor)
 125  {
 126         unsigned long deadline;
 127 -       int sr;
 128 -       int fsr;
 129 +       int timeout = 0, ret;
 130
 131         deadline = jiffies + MAX_READY_WAIT_JIFFIES;
 132
 133 -       do {
 134 +       while (!timeout) {
 135 +               if (time_after_eq(jiffies, deadline))
 136 +                       timeout = 1;
 137 +
 138 +               ret = spi_nor_ready(nor);
 139 +               if (ret < 0)
 140 +                       return ret;
 141 +               if (ret)
 142 +                       return 0;
 143 +
 144                 cond_resched();
 145 +       }
 146
 147 -               sr = read_sr(nor);
 148 -               if (sr < 0) {
 149 -                       break;
 150 -               } else if (!(sr & SR_WIP)) {
 151 -                       fsr = read_fsr(nor);
 152 -                       if (fsr < 0)
 153 -                               break;
 154 -                       if (fsr & FSR_READY)
 155 -                               return 0;
 156 -               }
 157 -       } while (!time_after_eq(jiffies, deadline));
 158 +       dev_err(nor->dev, "flash operation timed out\n");
 159
 160         return -ETIMEDOUT;
 161  }
 162
 163  /*
 164 - * Service routine to read status register until ready, or timeout occurs.
 165 - * Returns non-zero if error.
 166 - */
 167 -static int wait_till_ready(struct spi_nor *nor)
 168 -{
 169 -       return nor->wait_till_ready(nor);
 170 -}
 171 -
 172 -/*
 173   * Erase the whole flash memory
 174   *
 175   * Returns 0 if successful, non-zero otherwise.
 176   */
 177  static int erase_chip(struct spi_nor *nor)
 178  {
 179 -       int ret;
 180 -
 181         dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
 182
 183 -       /* Wait until finished previous write command. */
 184 -       ret = wait_till_ready(nor);
 185 -       if (ret)
 186 -               return ret;
 187 -
 188 -       /* Send write enable, then erase commands. */
 189 -       write_enable(nor);
 190 -
 191         return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
 192  }
 193
 194 @@ -294,11 +319,17 @@ static int spi_nor_erase(struct mtd_info
 195
 196         /* whole-chip erase? */
 197         if (len == mtd->size) {
 198 +               write_enable(nor);
 199 +
 200                 if (erase_chip(nor)) {
 201                         ret = -EIO;
 202                         goto erase_err;
 203                 }
 204
 205 +               ret = spi_nor_wait_till_ready(nor);
 206 +               if (ret)
 207 +                       goto erase_err;
 208 +
 209         /* REVISIT in some cases we could speed up erasing large regions
 210          * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K.  We may have set up
 211          * to use "small sector erase", but that's not always optimal.
 212 @@ -307,6 +338,8 @@ static int spi_nor_erase(struct mtd_info
 213         /* "sector"-at-a-time erase */
 214         } else {
 215                 while (len) {
 216 +                       write_enable(nor);
 217 +
 218                         if (nor->erase(nor, addr)) {
 219                                 ret = -EIO;
 220                                 goto erase_err;
 221 @@ -314,9 +347,15 @@ static int spi_nor_erase(struct mtd_info
 222
 223                         addr += mtd->erasesize;
 224                         len -= mtd->erasesize;
 225 +
 226 +                       ret = spi_nor_wait_till_ready(nor);
 227 +                       if (ret)
 228 +                               goto erase_err;
 229                 }
 230         }
 231
 232 +       write_disable(nor);
 233 +
 234         spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
 235
 236         instr->state = MTD_ERASE_DONE;
 237 @@ -341,11 +380,6 @@ static int spi_nor_lock(struct mtd_info
 238         if (ret)
 239                 return ret;
 240
 241 -       /* Wait until finished previous command */
 242 -       ret = wait_till_ready(nor);
 243 -       if (ret)
 244 -               goto err;
 245 -
 246         status_old = read_sr(nor);
 247
 248         if (offset < mtd->size - (mtd->size / 2))
 249 @@ -388,11 +422,6 @@ static int spi_nor_unlock(struct mtd_inf
 250         if (ret)
 251                 return ret;
 252
 253 -       /* Wait until finished previous command */
 254 -       ret = wait_till_ready(nor);
 255 -       if (ret)
 256 -               goto err;
 257 -
 258         status_old = read_sr(nor);
 259
 260         if (offset+len > mtd->size - (mtd->size / 64))
 261 @@ -424,38 +453,34 @@ err:
 262         return ret;
 263  }
 264
 265 -struct flash_info {
 266 -       /* JEDEC id zero means "no ID" (most older chips); otherwise it has
 267 -        * a high byte of zero plus three data bytes: the manufacturer id,
 268 -        * then a two byte device id.
 269 -        */
 270 -       u32             jedec_id;
 271 -       u16             ext_id;
 272 -
 273 -       /* The size listed here is what works with SPINOR_OP_SE, which isn't
 274 -        * necessarily called a "sector" by the vendor.
 275 -        */
 276 -       unsigned        sector_size;
 277 -       u16             n_sectors;
 278 -
 279 -       u16             page_size;
 280 -       u16             addr_width;
 281 -
 282 -       u16             flags;
 283 -#define        SECT_4K                 0x01    /* SPINOR_OP_BE_4K works uniformly */
 284 -#define        SPI_NOR_NO_ERASE        0x02    /* No erase command needed */
 285 -#define        SST_WRITE               0x04    /* use SST byte programming */
 286 -#define        SPI_NOR_NO_FR           0x08    /* Can't do fastread */
 287 -#define        SECT_4K_PMC             0x10    /* SPINOR_OP_BE_4K_PMC works uniformly */
 288 -#define        SPI_NOR_DUAL_READ       0x20    /* Flash supports Dual Read */
 289 -#define        SPI_NOR_QUAD_READ       0x40    /* Flash supports Quad Read */
 290 -#define        USE_FSR                 0x80    /* use flag status register */
 291 -};
 292 -
 293 +/* Used when the "_ext_id" is two bytes at most */
 294  #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)     \
 295         ((kernel_ulong_t)&(struct flash_info) {                         \
 296 -               .jedec_id = (_jedec_id),                                \
 297 -               .ext_id = (_ext_id),                                    \
 298 +               .id = {                                                 \
 299 +                       ((_jedec_id) >> 16) & 0xff,                     \
 300 +                       ((_jedec_id) >> 8) & 0xff,                      \
 301 +                       (_jedec_id) & 0xff,                             \
 302 +                       ((_ext_id) >> 8) & 0xff,                        \
 303 +                       (_ext_id) & 0xff,                               \
 304 +                       },                                              \
 305 +               .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),       \
 306 +               .sector_size = (_sector_size),                          \
 307 +               .n_sectors = (_n_sectors),                              \
 308 +               .page_size = 256,                                       \
 309 +               .flags = (_flags),                                      \
 310 +       })
 311 +
 312 +#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)    \
 313 +       ((kernel_ulong_t)&(struct flash_info) {                         \
 314 +               .id = {                                                 \
 315 +                       ((_jedec_id) >> 16) & 0xff,                     \
 316 +                       ((_jedec_id) >> 8) & 0xff,                      \
 317 +                       (_jedec_id) & 0xff,                             \
 318 +                       ((_ext_id) >> 16) & 0xff,                       \
 319 +                       ((_ext_id) >> 8) & 0xff,                        \
 320 +                       (_ext_id) & 0xff,                               \
 321 +                       },                                              \
 322 +               .id_len = 6,                                            \
 323                 .sector_size = (_sector_size),                          \
 324                 .n_sectors = (_n_sectors),                              \
 325                 .page_size = 256,                                       \
 326 @@ -507,6 +532,9 @@ static const struct spi_device_id spi_no
 327         { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
 328         { "mr25h10",  CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
 329
 330 +       /* Fujitsu */
 331 +       { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
 332 +
 333         /* GigaDevice */
 334         { "gd25q32", INFO(0xc84016, 0, 64 * 1024,  64, SECT_4K) },
 335         { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
 336 @@ -532,6 +560,7 @@ static const struct spi_device_id spi_no
 337         { "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
 338
 339         /* Micron */
 340 +       { "n25q032",     INFO(0x20ba16, 0, 64 * 1024,   64, 0) },
 341         { "n25q064",     INFO(0x20ba17, 0, 64 * 1024,  128, 0) },
 342         { "n25q128a11",  INFO(0x20bb18, 0, 64 * 1024,  256, 0) },
 343         { "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256, 0) },
 344 @@ -556,6 +585,7 @@ static const struct spi_device_id spi_no
 345         { "s70fl01gs",  INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
 346         { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024,  64, 0) },
 347         { "s25sl12801", INFO(0x012018, 0x0301,  64 * 1024, 256, 0) },
 348 +       { "s25fl128s",  INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
 349         { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024,  64, 0) },
 350         { "s25fl129p1", INFO(0x012018, 0x4d01,  64 * 1024, 256, 0) },
 351         { "s25sl004a",  INFO(0x010212,      0,  64 * 1024,   8, 0) },
 352 @@ -577,6 +607,7 @@ static const struct spi_device_id spi_no
 353         { "sst25wf010",  INFO(0xbf2502, 0, 64 * 1024,  2, SECT_4K | SST_WRITE) },
 354         { "sst25wf020",  INFO(0xbf2503, 0, 64 * 1024,  4, SECT_4K | SST_WRITE) },
 355         { "sst25wf040",  INFO(0xbf2504, 0, 64 * 1024,  8, SECT_4K | SST_WRITE) },
 356 +       { "sst25wf080",  INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
 357
 358         /* ST Microelectronics -- newer production may have feature updates */
 359         { "m25p05",  INFO(0x202010,  0,  32 * 1024,   2, 0) },
 360 @@ -588,7 +619,6 @@ static const struct spi_device_id spi_no
 361         { "m25p32",  INFO(0x202016,  0,  64 * 1024,  64, 0) },
 362         { "m25p64",  INFO(0x202017,  0,  64 * 1024, 128, 0) },
 363         { "m25p128", INFO(0x202018,  0, 256 * 1024,  64, 0) },
 364 -       { "n25q032", INFO(0x20ba16,  0,  64 * 1024,  64, 0) },
 365
 366         { "m25p05-nonjedec",  INFO(0, 0,  32 * 1024,   2, 0) },
 367         { "m25p10-nonjedec",  INFO(0, 0,  32 * 1024,   4, 0) },
 368 @@ -643,32 +673,24 @@ static const struct spi_device_id spi_no
 369  static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor)
 370  {
 371         int                     tmp;
 372 -       u8                      id[5];
 373 -       u32                     jedec;
 374 -       u16                     ext_jedec;
 375 +       u8                      id[SPI_NOR_MAX_ID_LEN];
 376         struct flash_info       *info;
 377
 378 -       tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, 5);
 379 +       tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
 380         if (tmp < 0) {
 381                 dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
 382                 return ERR_PTR(tmp);
 383         }
 384 -       jedec = id[0];
 385 -       jedec = jedec << 8;
 386 -       jedec |= id[1];
 387 -       jedec = jedec << 8;
 388 -       jedec |= id[2];
 389 -
 390 -       ext_jedec = id[3] << 8 | id[4];
 391
 392         for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
 393                 info = (void *)spi_nor_ids[tmp].driver_data;
 394 -               if (info->jedec_id == jedec) {
 395 -                       if (info->ext_id == 0 || info->ext_id == ext_jedec)
 396 +               if (info->id_len) {
 397 +                       if (!memcmp(info->id, id, info->id_len))
 398                                 return &spi_nor_ids[tmp];
 399                 }
 400         }
 401 -       dev_err(nor->dev, "unrecognized JEDEC id %06x\n", jedec);
 402 +       dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %2x, %2x\n",
 403 +               id[0], id[1], id[2]);
 404         return ERR_PTR(-ENODEV);
 405  }
 406
 407 @@ -703,11 +725,6 @@ static int sst_write(struct mtd_info *mt
 408         if (ret)
 409                 return ret;
 410
 411 -       /* Wait until finished previous write command. */
 412 -       ret = wait_till_ready(nor);
 413 -       if (ret)
 414 -               goto time_out;
 415 -
 416         write_enable(nor);
 417
 418         nor->sst_write_second = false;
 419 @@ -719,7 +736,7 @@ static int sst_write(struct mtd_info *mt
 420
 421                 /* write one byte. */
 422                 nor->write(nor, to, 1, retlen, buf);
 423 -               ret = wait_till_ready(nor);
 424 +               ret = spi_nor_wait_till_ready(nor);
 425                 if (ret)
 426                         goto time_out;
 427         }
 428 @@ -731,7 +748,7 @@ static int sst_write(struct mtd_info *mt
 429
 430                 /* write two bytes. */
 431                 nor->write(nor, to, 2, retlen, buf + actual);
 432 -               ret = wait_till_ready(nor);
 433 +               ret = spi_nor_wait_till_ready(nor);
 434                 if (ret)
 435                         goto time_out;
 436                 to += 2;
 437 @@ -740,7 +757,7 @@ static int sst_write(struct mtd_info *mt
 438         nor->sst_write_second = false;
 439
 440         write_disable(nor);
 441 -       ret = wait_till_ready(nor);
 442 +       ret = spi_nor_wait_till_ready(nor);
 443         if (ret)
 444                 goto time_out;
 445
 446 @@ -751,7 +768,7 @@ static int sst_write(struct mtd_info *mt
 447                 nor->program_opcode = SPINOR_OP_BP;
 448                 nor->write(nor, to, 1, retlen, buf + actual);
 449
 450 -               ret = wait_till_ready(nor);
 451 +               ret = spi_nor_wait_till_ready(nor);
 452                 if (ret)
 453                         goto time_out;
 454                 write_disable(nor);
 455 @@ -779,11 +796,6 @@ static int spi_nor_write(struct mtd_info
 456         if (ret)
 457                 return ret;
 458
 459 -       /* Wait until finished previous write command. */
 460 -       ret = wait_till_ready(nor);
 461 -       if (ret)
 462 -               goto write_err;
 463 -
 464         write_enable(nor);
 465
 466         page_offset = to & (nor->page_size - 1);
 467 @@ -802,16 +814,20 @@ static int spi_nor_write(struct mtd_info
 468                         if (page_size > nor->page_size)
 469                                 page_size = nor->page_size;
 470
 471 -                       wait_till_ready(nor);
 472 +                       ret = spi_nor_wait_till_ready(nor);
 473 +                       if (ret)
 474 +                               goto write_err;
 475 +
 476                         write_enable(nor);
 477
 478                         nor->write(nor, to + i, page_size, retlen, buf + i);
 479                 }
 480         }
 481
 482 +       ret = spi_nor_wait_till_ready(nor);
 483  write_err:
 484         spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
 485 -       return 0;
 486 +       return ret;
 487  }
 488
 489  static int macronix_quad_enable(struct spi_nor *nor)
 490 @@ -824,7 +840,7 @@ static int macronix_quad_enable(struct s
 491         nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
 492         nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
 493
 494 -       if (wait_till_ready(nor))
 495 +       if (spi_nor_wait_till_ready(nor))
 496                 return 1;
 497
 498         ret = read_sr(nor);
 499 @@ -874,11 +890,11 @@ static int spansion_quad_enable(struct s
 500         return 0;
 501  }
 502
 503 -static int set_quad_mode(struct spi_nor *nor, u32 jedec_id)
 504 +static int set_quad_mode(struct spi_nor *nor, struct flash_info *info)
 505  {
 506         int status;
 507
 508 -       switch (JEDEC_MFR(jedec_id)) {
 509 +       switch (JEDEC_MFR(info)) {
 510         case CFI_MFR_MACRONIX:
 511                 status = macronix_quad_enable(nor);
 512                 if (status) {
 513 @@ -904,11 +920,6 @@ static int spi_nor_check(struct spi_nor
 514                 return -EINVAL;
 515         }
 516
 517 -       if (!nor->read_id)
 518 -               nor->read_id = spi_nor_read_id;
 519 -       if (!nor->wait_till_ready)
 520 -               nor->wait_till_ready = spi_nor_wait_till_ready;
 521 -
 522         return 0;
 523  }
 524
 525 @@ -926,16 +937,24 @@ int spi_nor_scan(struct spi_nor *nor, co
 526         if (ret)
 527                 return ret;
 528
 529 -       id = spi_nor_match_id(name);
 530 -       if (!id)
 531 +       /* Try to auto-detect if chip name wasn't specified */
 532 +       if (!name)
 533 +               id = spi_nor_read_id(nor);
 534 +       else
 535 +               id = spi_nor_match_id(name);
 536 +       if (IS_ERR_OR_NULL(id))
 537                 return -ENOENT;
 538
 539         info = (void *)id->driver_data;
 540
 541 -       if (info->jedec_id) {
 542 +       /*
 543 +        * If caller has specified name of flash model that can normally be
 544 +        * detected using JEDEC, let's verify it.
 545 +        */
 546 +       if (name && info->id_len) {
 547                 const struct spi_device_id *jid;
 548
 549 -               jid = nor->read_id(nor);
 550 +               jid = spi_nor_read_id(nor);
 551                 if (IS_ERR(jid)) {
 552                         return PTR_ERR(jid);
 553                 } else if (jid != id) {
 554 @@ -960,9 +979,9 @@ int spi_nor_scan(struct spi_nor *nor, co
 555          * up with the software protection bits set
 556          */
 557
 558 -       if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
 559 -           JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
 560 -           JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
 561 +       if (JEDEC_MFR(info) == CFI_MFR_ATMEL ||
 562 +           JEDEC_MFR(info) == CFI_MFR_INTEL ||
 563 +           JEDEC_MFR(info) == CFI_MFR_SST) {
 564                 write_enable(nor);
 565                 write_sr(nor, 0);
 566         }
 567 @@ -977,7 +996,7 @@ int spi_nor_scan(struct spi_nor *nor, co
 568         mtd->_read = spi_nor_read;
 569
 570         /* nor protection support for STmicro chips */
 571 -       if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
 572 +       if (JEDEC_MFR(info) == CFI_MFR_ST) {
 573                 mtd->_lock = spi_nor_lock;
 574                 mtd->_unlock = spi_nor_unlock;
 575         }
 576 @@ -988,9 +1007,8 @@ int spi_nor_scan(struct spi_nor *nor, co
 577         else
 578                 mtd->_write = spi_nor_write;
 579
 580 -       if ((info->flags & USE_FSR) &&
 581 -           nor->wait_till_ready == spi_nor_wait_till_ready)
 582 -               nor->wait_till_ready = spi_nor_wait_till_fsr_ready;
 583 +       if (info->flags & USE_FSR)
 584 +               nor->flags |= SNOR_F_USE_FSR;
 585
 586  #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
 587         /* prefer "small sector" erase if possible */
 588 @@ -1031,7 +1049,7 @@ int spi_nor_scan(struct spi_nor *nor, co
 589
 590         /* Quad/Dual-read mode takes precedence over fast/normal */
 591         if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
 592 -               ret = set_quad_mode(nor, info->jedec_id);
 593 +               ret = set_quad_mode(nor, info);
 594                 if (ret) {
 595                         dev_err(dev, "quad mode not supported\n");
 596                         return ret;
 597 @@ -1067,7 +1085,7 @@ int spi_nor_scan(struct spi_nor *nor, co
 598         else if (mtd->size > 0x1000000) {
 599                 /* enable 4-byte addressing if the device exceeds 16MiB */
 600                 nor->addr_width = 4;
 601 -               if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
 602 +               if (JEDEC_MFR(info) == CFI_MFR_AMD) {
 603                         /* Dedicated 4-byte command set */
 604                         switch (nor->flash_read) {
 605                         case SPI_NOR_QUAD:
 606 @@ -1088,7 +1106,7 @@ int spi_nor_scan(struct spi_nor *nor, co
 607                         nor->erase_opcode = SPINOR_OP_SE_4B;
 608                         mtd->erasesize = info->sector_size;
 609                 } else
 610 -                       set_4byte(nor, info->jedec_id, 1);
 611 +                       set_4byte(nor, info, 1);
 612         } else {
 613                 nor->addr_width = 3;
 614         }
 615 --- a/include/linux/mtd/spi-nor.h
 616 +++ b/include/linux/mtd/spi-nor.h
 617 @@ -116,6 +116,10 @@ enum spi_nor_ops {
 618         SPI_NOR_OPS_UNLOCK,
 619  };
 620
 621 +enum spi_nor_option_flags {
 622 +       SNOR_F_USE_FSR          = BIT(0),
 623 +};
 624 +
 625  /**
 626   * struct spi_nor - Structure for defining a the SPI NOR layer
 627   * @mtd:               point to a mtd_info structure
 628 @@ -129,6 +133,7 @@ enum spi_nor_ops {
 629   * @program_opcode:    the program opcode
 630   * @flash_read:                the mode of the read
 631   * @sst_write_second:  used by the SST write operation
 632 + * @flags:             flag options for the current SPI-NOR (SNOR_F_*)
 633   * @cfg:               used by the read_xfer/write_xfer
 634   * @cmd_buf:           used by the write_reg
 635   * @prepare:           [OPTIONAL] do some preparations for the
 636 @@ -139,9 +144,6 @@ enum spi_nor_ops {
 637   * @write_xfer:                [OPTIONAL] the writefundamental primitive
 638   * @read_reg:          [DRIVER-SPECIFIC] read out the register
 639   * @write_reg:         [DRIVER-SPECIFIC] write data to the register
 640 - * @read_id:           [REPLACEABLE] read out the ID data, and find
 641 - *                     the proper spi_device_id
 642 - * @wait_till_ready:   [REPLACEABLE] wait till the NOR becomes ready
 643   * @read:              [DRIVER-SPECIFIC] read data from the SPI NOR
 644   * @write:             [DRIVER-SPECIFIC] write data to the SPI NOR
 645   * @erase:             [DRIVER-SPECIFIC] erase a sector of the SPI NOR
 646 @@ -160,6 +162,7 @@ struct spi_nor {
 647         u8                      program_opcode;
 648         enum read_mode          flash_read;
 649         bool                    sst_write_second;
 650 +       u32                     flags;
 651         struct spi_nor_xfer_cfg cfg;
 652         u8                      cmd_buf[SPI_NOR_MAX_CMD_SIZE];
 653
 654 @@ -172,8 +175,6 @@ struct spi_nor {
 655         int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
 656         int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
 657                         int write_enable);
 658 -       const struct spi_device_id *(*read_id)(struct spi_nor *nor);
 659 -       int (*wait_till_ready)(struct spi_nor *nor);
 660
 661         int (*read)(struct spi_nor *nor, loff_t from,
 662                         size_t len, size_t *retlen, u_char *read_buf);