target/linux/atheros/patches-3.10/120-spiflash.patch

   1 --- a/drivers/mtd/devices/Kconfig
   2 +++ b/drivers/mtd/devices/Kconfig
   3 @@ -135,6 +135,10 @@ config MTD_BCM47XXSFLASH
   4           registered by bcma as platform devices. This enables driver for
   5           serial flash memories (only read-only mode is implemented).
   6
   7 +config MTD_AR2315
   8 +       tristate "Atheros AR2315+ SPI Flash support"
   9 +       depends on ATHEROS_AR2315
  10 +
  11  config MTD_SLRAM
  12         tristate "Uncached system RAM"
  13         help
  14 --- a/drivers/mtd/devices/Makefile
  15 +++ b/drivers/mtd/devices/Makefile
  16 @@ -15,6 +15,7 @@ obj-$(CONFIG_MTD_M25P80)      += m25p80.o
  17  obj-$(CONFIG_MTD_NAND_OMAP_BCH)        += elm.o
  18  obj-$(CONFIG_MTD_SPEAR_SMI)    += spear_smi.o
  19  obj-$(CONFIG_MTD_SST25L)       += sst25l.o
  20 +obj-$(CONFIG_MTD_AR2315)       += ar2315.o
  21  obj-$(CONFIG_MTD_BCM47XXSFLASH)        += bcm47xxsflash.o
  22
  23
  24 --- /dev/null
  25 +++ b/drivers/mtd/devices/ar2315.c
  26 @@ -0,0 +1,539 @@
  27 +
  28 +/*
  29 + * MTD driver for the SPI Flash Memory support on Atheros AR2315
  30 + *
  31 + * Copyright (c) 2005-2006 Atheros Communications Inc.
  32 + * Copyright (C) 2006-2007 FON Technology, SL.
  33 + * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
  34 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
  35 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
  36 + *
  37 + * This code is free software; you can redistribute it and/or modify
  38 + * it under the terms of the GNU General Public License version 2 as
  39 + * published by the Free Software Foundation.
  40 + *
  41 + */
  42 +
  43 +#include <linux/kernel.h>
  44 +#include <linux/module.h>
  45 +#include <linux/types.h>
  46 +#include <linux/version.h>
  47 +#include <linux/errno.h>
  48 +#include <linux/slab.h>
  49 +#include <linux/mtd/mtd.h>
  50 +#include <linux/mtd/partitions.h>
  51 +#include <linux/platform_device.h>
  52 +#include <linux/sched.h>
  53 +#include <linux/root_dev.h>
  54 +#include <linux/delay.h>
  55 +#include <linux/io.h>
  56 +
  57 +#include <ar231x.h>
  58 +#include "ar2315_spiflash.h"
  59 +
  60 +
  61 +#define SPIFLASH "spiflash: "
  62 +#define busy_wait(_priv, _condition, _wait) do { \
  63 +       while (_condition) { \
  64 +               spin_unlock_bh(&_priv->lock); \
  65 +               if (_wait > 1) \
  66 +                       msleep(_wait); \
  67 +               else if ((_wait == 1) && need_resched()) \
  68 +                       schedule(); \
  69 +               else \
  70 +                       udelay(1); \
  71 +               spin_lock_bh(&_priv->lock); \
  72 +       } \
  73 +} while (0)
  74 +
  75 +enum {
  76 +       FLASH_NONE,
  77 +       FLASH_1MB,
  78 +       FLASH_2MB,
  79 +       FLASH_4MB,
  80 +       FLASH_8MB,
  81 +       FLASH_16MB,
  82 +};
  83 +
  84 +/* Flash configuration table */
  85 +struct flashconfig {
  86 +       u32 byte_cnt;
  87 +       u32 sector_cnt;
  88 +       u32 sector_size;
  89 +};
  90 +
  91 +const struct flashconfig flashconfig_tbl[] = {
  92 +       [FLASH_NONE] = { 0, 0, 0},
  93 +       [FLASH_1MB]  = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT,
  94 +                        STM_1MB_SECTOR_SIZE},
  95 +       [FLASH_2MB]  = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT,
  96 +                        STM_2MB_SECTOR_SIZE},
  97 +       [FLASH_4MB]  = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT,
  98 +                        STM_4MB_SECTOR_SIZE},
  99 +       [FLASH_8MB]  = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT,
 100 +                        STM_8MB_SECTOR_SIZE},
 101 +       [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT,
 102 +                        STM_16MB_SECTOR_SIZE}
 103 +};
 104 +
 105 +/* Mapping of generic opcodes to STM serial flash opcodes */
 106 +enum {
 107 +       SPI_WRITE_ENABLE,
 108 +       SPI_WRITE_DISABLE,
 109 +       SPI_RD_STATUS,
 110 +       SPI_WR_STATUS,
 111 +       SPI_RD_DATA,
 112 +       SPI_FAST_RD_DATA,
 113 +       SPI_PAGE_PROGRAM,
 114 +       SPI_SECTOR_ERASE,
 115 +       SPI_BULK_ERASE,
 116 +       SPI_DEEP_PWRDOWN,
 117 +       SPI_RD_SIG,
 118 +};
 119 +
 120 +struct opcodes {
 121 +       __u16 code;
 122 +       __s8 tx_cnt;
 123 +       __s8 rx_cnt;
 124 +};
 125 +
 126 +const struct opcodes stm_opcodes[] = {
 127 +       [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
 128 +       [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
 129 +       [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
 130 +       [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
 131 +       [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
 132 +       [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
 133 +       [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
 134 +       [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
 135 +       [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
 136 +       [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
 137 +       [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
 138 +};
 139 +
 140 +/* Driver private data structure */
 141 +struct spiflash_priv {
 142 +       struct mtd_info mtd;
 143 +       void *readaddr; /* memory mapped data for read  */
 144 +       void *mmraddr;  /* memory mapped register space */
 145 +       wait_queue_head_t wq;
 146 +       spinlock_t lock;
 147 +       int state;
 148 +};
 149 +
 150 +#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
 151 +
 152 +enum {
 153 +       FL_READY,
 154 +       FL_READING,
 155 +       FL_ERASING,
 156 +       FL_WRITING
 157 +};
 158 +
 159 +/*****************************************************************************/
 160 +
 161 +static u32
 162 +spiflash_read_reg(struct spiflash_priv *priv, int reg)
 163 +{
 164 +       return ar231x_read_reg((u32) priv->mmraddr + reg);
 165 +}
 166 +
 167 +static void
 168 +spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
 169 +{
 170 +       ar231x_write_reg((u32) priv->mmraddr + reg, data);
 171 +}
 172 +
 173 +static u32
 174 +spiflash_wait_busy(struct spiflash_priv *priv)
 175 +{
 176 +       u32 reg;
 177 +
 178 +       busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
 179 +               SPI_CTL_BUSY, 0);
 180 +       return reg;
 181 +}
 182 +
 183 +static u32
 184 +spiflash_sendcmd(struct spiflash_priv *priv, int opcode, u32 addr)
 185 +{
 186 +       const struct opcodes *op;
 187 +       u32 reg, mask;
 188 +
 189 +       op = &stm_opcodes[opcode];
 190 +       reg = spiflash_wait_busy(priv);
 191 +       spiflash_write_reg(priv, SPI_FLASH_OPCODE,
 192 +               ((u32) op->code) | (addr << 8));
 193 +
 194 +       reg &= ~SPI_CTL_TX_RX_CNT_MASK;
 195 +       reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
 196 +
 197 +       spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
 198 +       spiflash_wait_busy(priv);
 199 +
 200 +       if (!op->rx_cnt)
 201 +               return 0;
 202 +
 203 +       reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
 204 +
 205 +       switch (op->rx_cnt) {
 206 +       case 1:
 207 +               mask = 0x000000ff;
 208 +               break;
 209 +       case 2:
 210 +               mask = 0x0000ffff;
 211 +               break;
 212 +       case 3:
 213 +               mask = 0x00ffffff;
 214 +               break;
 215 +       default:
 216 +               mask = 0xffffffff;
 217 +               break;
 218 +       }
 219 +       reg &= mask;
 220 +
 221 +       return reg;
 222 +}
 223 +
 224 +
 225 +/*
 226 + * Probe SPI flash device
 227 + * Function returns 0 for failure.
 228 + * and flashconfig_tbl array index for success.
 229 + */
 230 +static int
 231 +spiflash_probe_chip(struct spiflash_priv *priv)
 232 +{
 233 +       u32 sig;
 234 +       int flash_size;
 235 +
 236 +       /* Read the signature on the flash device */
 237 +       spin_lock_bh(&priv->lock);
 238 +       sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
 239 +       spin_unlock_bh(&priv->lock);
 240 +
 241 +       switch (sig) {
 242 +       case STM_8MBIT_SIGNATURE:
 243 +               flash_size = FLASH_1MB;
 244 +               break;
 245 +       case STM_16MBIT_SIGNATURE:
 246 +               flash_size = FLASH_2MB;
 247 +               break;
 248 +       case STM_32MBIT_SIGNATURE:
 249 +               flash_size = FLASH_4MB;
 250 +               break;
 251 +       case STM_64MBIT_SIGNATURE:
 252 +               flash_size = FLASH_8MB;
 253 +               break;
 254 +       case STM_128MBIT_SIGNATURE:
 255 +               flash_size = FLASH_16MB;
 256 +               break;
 257 +       default:
 258 +               pr_warn(SPIFLASH "Read of flash device signature failed!\n");
 259 +               return 0;
 260 +       }
 261 +
 262 +       return flash_size;
 263 +}
 264 +
 265 +
 266 +/* wait until the flash chip is ready and grab a lock */
 267 +static int spiflash_wait_ready(struct spiflash_priv *priv, int state)
 268 +{
 269 +       DECLARE_WAITQUEUE(wait, current);
 270 +
 271 +retry:
 272 +       spin_lock_bh(&priv->lock);
 273 +       if (priv->state != FL_READY) {
 274 +               set_current_state(TASK_UNINTERRUPTIBLE);
 275 +               add_wait_queue(&priv->wq, &wait);
 276 +               spin_unlock_bh(&priv->lock);
 277 +               schedule();
 278 +               remove_wait_queue(&priv->wq, &wait);
 279 +
 280 +               if (signal_pending(current))
 281 +                       return 0;
 282 +
 283 +               goto retry;
 284 +       }
 285 +       priv->state = state;
 286 +
 287 +       return 1;
 288 +}
 289 +
 290 +static inline void spiflash_done(struct spiflash_priv *priv)
 291 +{
 292 +       priv->state = FL_READY;
 293 +       spin_unlock_bh(&priv->lock);
 294 +       wake_up(&priv->wq);
 295 +}
 296 +
 297 +static void
 298 +spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
 299 +{
 300 +       busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
 301 +               SPI_STATUS_WIP, timeout);
 302 +       spiflash_done(priv);
 303 +}
 304 +
 305 +
 306 +
 307 +static int
 308 +spiflash_erase(struct mtd_info *mtd, struct erase_info *instr)
 309 +{
 310 +       struct spiflash_priv *priv = to_spiflash(mtd);
 311 +       const struct opcodes *op;
 312 +       u32 temp, reg;
 313 +
 314 +       if (instr->addr + instr->len > mtd->size)
 315 +               return -EINVAL;
 316 +
 317 +       if (!spiflash_wait_ready(priv, FL_ERASING))
 318 +               return -EINTR;
 319 +
 320 +       spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
 321 +       reg = spiflash_wait_busy(priv);
 322 +
 323 +       op = &stm_opcodes[SPI_SECTOR_ERASE];
 324 +       temp = ((u32)instr->addr << 8) | (u32)(op->code);
 325 +       spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
 326 +
 327 +       reg &= ~SPI_CTL_TX_RX_CNT_MASK;
 328 +       reg |= op->tx_cnt | SPI_CTL_START;
 329 +       spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
 330 +
 331 +       spiflash_wait_complete(priv, 20);
 332 +
 333 +       instr->state = MTD_ERASE_DONE;
 334 +       mtd_erase_callback(instr);
 335 +
 336 +       return 0;
 337 +}
 338 +
 339 +static int
 340 +spiflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
 341 +             u_char *buf)
 342 +{
 343 +       struct spiflash_priv *priv = to_spiflash(mtd);
 344 +       u8 *read_addr;
 345 +
 346 +       if (!len)
 347 +               return 0;
 348 +
 349 +       if (from + len > mtd->size)
 350 +               return -EINVAL;
 351 +
 352 +       *retlen = len;
 353 +
 354 +       if (!spiflash_wait_ready(priv, FL_READING))
 355 +               return -EINTR;
 356 +
 357 +       read_addr = (u8 *)(priv->readaddr + from);
 358 +       memcpy_fromio(buf, read_addr, len);
 359 +       spiflash_done(priv);
 360 +
 361 +       return 0;
 362 +}
 363 +
 364 +static int
 365 +spiflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
 366 +              const u8 *buf)
 367 +{
 368 +       struct spiflash_priv *priv = to_spiflash(mtd);
 369 +       u32 opcode, bytes_left;
 370 +
 371 +       *retlen = 0;
 372 +
 373 +       if (!len)
 374 +               return 0;
 375 +
 376 +       if (to + len > mtd->size)
 377 +               return -EINVAL;
 378 +
 379 +       bytes_left = len;
 380 +
 381 +       do {
 382 +               u32 read_len, reg, page_offset, spi_data = 0;
 383 +
 384 +               read_len = min(bytes_left, sizeof(u32));
 385 +
 386 +               /* 32-bit writes cannot span across a page boundary
 387 +                * (256 bytes). This types of writes require two page
 388 +                * program operations to handle it correctly. The STM part
 389 +                * will write the overflow data to the beginning of the
 390 +                * current page as opposed to the subsequent page.
 391 +                */
 392 +               page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
 393 +
 394 +               if (page_offset > STM_PAGE_SIZE)
 395 +                       read_len -= (page_offset - STM_PAGE_SIZE);
 396 +
 397 +               if (!spiflash_wait_ready(priv, FL_WRITING))
 398 +                       return -EINTR;
 399 +
 400 +               spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
 401 +               spi_data = 0;
 402 +               switch (read_len) {
 403 +               case 4:
 404 +                       spi_data |= buf[3] << 24;
 405 +                       /* fall through */
 406 +               case 3:
 407 +                       spi_data |= buf[2] << 16;
 408 +                       /* fall through */
 409 +               case 2:
 410 +                       spi_data |= buf[1] << 8;
 411 +                       /* fall through */
 412 +               case 1:
 413 +                       spi_data |= buf[0] & 0xff;
 414 +                       break;
 415 +               default:
 416 +                       break;
 417 +               }
 418 +
 419 +               spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
 420 +               opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
 421 +                       (to & 0x00ffffff) << 8;
 422 +               spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
 423 +
 424 +               reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
 425 +               reg &= ~SPI_CTL_TX_RX_CNT_MASK;
 426 +               reg |= (read_len + 4) | SPI_CTL_START;
 427 +               spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
 428 +
 429 +               spiflash_wait_complete(priv, 1);
 430 +
 431 +               bytes_left -= read_len;
 432 +               to += read_len;
 433 +               buf += read_len;
 434 +
 435 +               *retlen += read_len;
 436 +       } while (bytes_left != 0);
 437 +
 438 +       return 0;
 439 +}
 440 +
 441 +
 442 +#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
 443 +static const char * const part_probe_types[] = {
 444 +       "cmdlinepart", "RedBoot", "MyLoader", NULL
 445 +};
 446 +#endif
 447 +
 448 +
 449 +static int
 450 +spiflash_probe(struct platform_device *pdev)
 451 +{
 452 +       struct spiflash_priv *priv;
 453 +       struct mtd_info *mtd;
 454 +       struct resource *res;
 455 +       int index;
 456 +       int result = 0;
 457 +
 458 +       priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL);
 459 +       spin_lock_init(&priv->lock);
 460 +       init_waitqueue_head(&priv->wq);
 461 +       priv->state = FL_READY;
 462 +       mtd = &priv->mtd;
 463 +
 464 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 465 +       if (!res) {
 466 +               dev_err(&pdev->dev, "No MMR resource found\n");
 467 +               goto error;
 468 +       }
 469 +
 470 +       priv->mmraddr = ioremap_nocache(res->start, resource_size(res));
 471 +       if (!priv->mmraddr) {
 472 +               dev_warn(&pdev->dev, SPIFLASH "Failed to map flash device\n");
 473 +               goto error;
 474 +       }
 475 +
 476 +       index = spiflash_probe_chip(priv);
 477 +       if (!index) {
 478 +               dev_warn(&pdev->dev, SPIFLASH "Found no flash device\n");
 479 +               goto error;
 480 +       }
 481 +
 482 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 483 +       if (!res) {
 484 +               dev_err(&pdev->dev, "No flash readmem resource found\n");
 485 +               goto error;
 486 +       }
 487 +
 488 +       priv->readaddr = ioremap_nocache(res->start,
 489 +                                        flashconfig_tbl[index].byte_cnt);
 490 +       if (!priv->readaddr) {
 491 +               dev_warn(&pdev->dev, SPIFLASH "Failed to map flash device\n");
 492 +               goto error;
 493 +       }
 494 +
 495 +       platform_set_drvdata(pdev, priv);
 496 +       mtd->name = "spiflash";
 497 +       mtd->type = MTD_NORFLASH;
 498 +       mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
 499 +       mtd->size = flashconfig_tbl[index].byte_cnt;
 500 +       mtd->erasesize = flashconfig_tbl[index].sector_size;
 501 +       mtd->writesize = 1;
 502 +       mtd->numeraseregions = 0;
 503 +       mtd->eraseregions = NULL;
 504 +       mtd->_erase = spiflash_erase;
 505 +       mtd->_read = spiflash_read;
 506 +       mtd->_write = spiflash_write;
 507 +       mtd->owner = THIS_MODULE;
 508 +
 509 +       dev_info(&pdev->dev, "%lld Kbytes flash detected\n", mtd->size >> 10);
 510 +
 511 +#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
 512 +       /* parse redboot partitions */
 513 +
 514 +       result = mtd_device_parse_register(mtd, part_probe_types,
 515 +                       NULL, NULL, 0);
 516 +#endif
 517 +
 518 +       return result;
 519 +
 520 +error:
 521 +       if (priv->mmraddr)
 522 +               iounmap(priv->mmraddr);
 523 +       kfree(priv);
 524 +       return -ENXIO;
 525 +}
 526 +
 527 +static int
 528 +spiflash_remove(struct platform_device *pdev)
 529 +{
 530 +       struct spiflash_priv *priv = platform_get_drvdata(pdev);
 531 +       struct mtd_info *mtd = &priv->mtd;
 532 +
 533 +       mtd_device_unregister(mtd);
 534 +       iounmap(priv->mmraddr);
 535 +       iounmap(priv->readaddr);
 536 +       kfree(priv);
 537 +
 538 +       return 0;
 539 +}
 540 +
 541 +struct platform_driver spiflash_driver = {
 542 +       .driver.name = "spiflash",
 543 +       .probe = spiflash_probe,
 544 +       .remove = spiflash_remove,
 545 +};
 546 +
 547 +int __init
 548 +spiflash_init(void)
 549 +{
 550 +       return platform_driver_register(&spiflash_driver);
 551 +}
 552 +
 553 +void __exit
 554 +spiflash_exit(void)
 555 +{
 556 +       return platform_driver_unregister(&spiflash_driver);
 557 +}
 558 +
 559 +module_init(spiflash_init);
 560 +module_exit(spiflash_exit);
 561 +
 562 +MODULE_LICENSE("GPL");
 563 +MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc");
 564 +MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");
 565 +
 566 --- /dev/null
 567 +++ b/drivers/mtd/devices/ar2315_spiflash.h
 568 @@ -0,0 +1,116 @@
 569 +/*
 570 + * Atheros AR2315 SPI Flash Memory support header file.
 571 + *
 572 + * Copyright (c) 2005, Atheros Communications Inc.
 573 + * Copyright (C) 2006 FON Technology, SL.
 574 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
 575 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
 576 + *
 577 + * This code is free software; you can redistribute it and/or modify
 578 + * it under the terms of the GNU General Public License version 2 as
 579 + * published by the Free Software Foundation.
 580 + *
 581 + */
 582 +#ifndef __AR2315_SPIFLASH_H
 583 +#define __AR2315_SPIFLASH_H
 584 +
 585 +#define STM_PAGE_SIZE           256
 586 +
 587 +#define SFI_WRITE_BUFFER_SIZE   4
 588 +#define SFI_FLASH_ADDR_MASK     0x00ffffff
 589 +
 590 +#define STM_8MBIT_SIGNATURE     0x13
 591 +#define STM_M25P80_BYTE_COUNT   1048576
 592 +#define STM_M25P80_SECTOR_COUNT 16
 593 +#define STM_M25P80_SECTOR_SIZE  0x10000
 594 +
 595 +#define STM_16MBIT_SIGNATURE    0x14
 596 +#define STM_M25P16_BYTE_COUNT   2097152
 597 +#define STM_M25P16_SECTOR_COUNT 32
 598 +#define STM_M25P16_SECTOR_SIZE  0x10000
 599 +
 600 +#define STM_32MBIT_SIGNATURE    0x15
 601 +#define STM_M25P32_BYTE_COUNT   4194304
 602 +#define STM_M25P32_SECTOR_COUNT 64
 603 +#define STM_M25P32_SECTOR_SIZE  0x10000
 604 +
 605 +#define STM_64MBIT_SIGNATURE    0x16
 606 +#define STM_M25P64_BYTE_COUNT   8388608
 607 +#define STM_M25P64_SECTOR_COUNT 128
 608 +#define STM_M25P64_SECTOR_SIZE  0x10000
 609 +
 610 +#define STM_128MBIT_SIGNATURE   0x17
 611 +#define STM_M25P128_BYTE_COUNT   16777216
 612 +#define STM_M25P128_SECTOR_COUNT 256
 613 +#define STM_M25P128_SECTOR_SIZE  0x10000
 614 +
 615 +#define STM_1MB_BYTE_COUNT   STM_M25P80_BYTE_COUNT
 616 +#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
 617 +#define STM_1MB_SECTOR_SIZE  STM_M25P80_SECTOR_SIZE
 618 +#define STM_2MB_BYTE_COUNT   STM_M25P16_BYTE_COUNT
 619 +#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
 620 +#define STM_2MB_SECTOR_SIZE  STM_M25P16_SECTOR_SIZE
 621 +#define STM_4MB_BYTE_COUNT   STM_M25P32_BYTE_COUNT
 622 +#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
 623 +#define STM_4MB_SECTOR_SIZE  STM_M25P32_SECTOR_SIZE
 624 +#define STM_8MB_BYTE_COUNT   STM_M25P64_BYTE_COUNT
 625 +#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
 626 +#define STM_8MB_SECTOR_SIZE  STM_M25P64_SECTOR_SIZE
 627 +#define STM_16MB_BYTE_COUNT   STM_M25P128_BYTE_COUNT
 628 +#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
 629 +#define STM_16MB_SECTOR_SIZE  STM_M25P128_SECTOR_SIZE
 630 +
 631 +/*
 632 + * ST Microelectronics Opcodes for Serial Flash
 633 + */
 634 +
 635 +#define STM_OP_WR_ENABLE       0x06     /* Write Enable */
 636 +#define STM_OP_WR_DISABLE      0x04     /* Write Disable */
 637 +#define STM_OP_RD_STATUS       0x05     /* Read Status */
 638 +#define STM_OP_WR_STATUS       0x01     /* Write Status */
 639 +#define STM_OP_RD_DATA         0x03     /* Read Data */
 640 +#define STM_OP_FAST_RD_DATA    0x0b     /* Fast Read Data */
 641 +#define STM_OP_PAGE_PGRM       0x02     /* Page Program */
 642 +#define STM_OP_SECTOR_ERASE    0xd8     /* Sector Erase */
 643 +#define STM_OP_BULK_ERASE      0xc7     /* Bulk Erase */
 644 +#define STM_OP_DEEP_PWRDOWN    0xb9     /* Deep Power-Down Mode */
 645 +#define STM_OP_RD_SIG          0xab     /* Read Electronic Signature */
 646 +
 647 +#define STM_STATUS_WIP       0x01       /* Write-In-Progress */
 648 +#define STM_STATUS_WEL       0x02       /* Write Enable Latch */
 649 +#define STM_STATUS_BP0       0x04       /* Block Protect 0 */
 650 +#define STM_STATUS_BP1       0x08       /* Block Protect 1 */
 651 +#define STM_STATUS_BP2       0x10       /* Block Protect 2 */
 652 +#define STM_STATUS_SRWD      0x80       /* Status Register Write Disable */
 653 +
 654 +/*
 655 + * SPI Flash Interface Registers
 656 + */
 657 +#define AR531XPLUS_SPI_READ     0x08000000
 658 +#define AR531XPLUS_SPI_MMR      0x11300000
 659 +#define AR531XPLUS_SPI_MMR_SIZE 12
 660 +
 661 +#define AR531XPLUS_SPI_CTL      0x00
 662 +#define AR531XPLUS_SPI_OPCODE   0x04
 663 +#define AR531XPLUS_SPI_DATA     0x08
 664 +
 665 +#define SPI_FLASH_READ          AR531XPLUS_SPI_READ
 666 +#define SPI_FLASH_MMR           AR531XPLUS_SPI_MMR
 667 +#define SPI_FLASH_MMR_SIZE      AR531XPLUS_SPI_MMR_SIZE
 668 +#define SPI_FLASH_CTL           AR531XPLUS_SPI_CTL
 669 +#define SPI_FLASH_OPCODE        AR531XPLUS_SPI_OPCODE
 670 +#define SPI_FLASH_DATA          AR531XPLUS_SPI_DATA
 671 +
 672 +#define SPI_CTL_START           0x00000100
 673 +#define SPI_CTL_BUSY            0x00010000
 674 +#define SPI_CTL_TXCNT_MASK      0x0000000f
 675 +#define SPI_CTL_RXCNT_MASK      0x000000f0
 676 +#define SPI_CTL_TX_RX_CNT_MASK  0x000000ff
 677 +#define SPI_CTL_SIZE_MASK       0x00060000
 678 +
 679 +#define SPI_CTL_CLK_SEL_MASK    0x03000000
 680 +#define SPI_OPCODE_MASK         0x000000ff
 681 +
 682 +#define SPI_STATUS_WIP         STM_STATUS_WIP
 683 +
 684 +#endif