target/linux/atheros/patches-2.6.28/120-spiflash.patch

   1 --- a/drivers/mtd/devices/Kconfig
   2 +++ b/drivers/mtd/devices/Kconfig
   3 @@ -104,6 +104,10 @@ config M25PXX_USE_FAST_READ
   4         help
   5           This option enables FAST_READ access supported by ST M25Pxx.
   6
   7 +config MTD_AR2315
   8 +       tristate "Atheros AR2315+ SPI Flash support"
   9 +       depends on ATHEROS_AR2315
  10 +
  11  config MTD_SLRAM
  12         tristate "Uncached system RAM"
  13         help
  14 --- a/drivers/mtd/devices/Makefile
  15 +++ b/drivers/mtd/devices/Makefile
  16 @@ -16,3 +16,4 @@ obj-$(CONFIG_MTD_LART)                += lart.o
  17  obj-$(CONFIG_MTD_BLOCK2MTD)    += block2mtd.o
  18  obj-$(CONFIG_MTD_DATAFLASH)    += mtd_dataflash.o
  19  obj-$(CONFIG_MTD_M25P80)       += m25p80.o
  20 +obj-$(CONFIG_MTD_AR2315)       += ar2315.o
  21 --- /dev/null
  22 +++ b/drivers/mtd/devices/ar2315.c
  23 @@ -0,0 +1,519 @@
  24 +
  25 +/*
  26 + * MTD driver for the SPI Flash Memory support on Atheros AR2315
  27 + *
  28 + * Copyright (c) 2005-2006 Atheros Communications Inc.
  29 + * Copyright (C) 2006-2007 FON Technology, SL.
  30 + * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
  31 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
  32 + *
  33 + * This code is free software; you can redistribute it and/or modify
  34 + * it under the terms of the GNU General Public License version 2 as
  35 + * published by the Free Software Foundation.
  36 + *
  37 + */
  38 +
  39 +#include <linux/kernel.h>
  40 +#include <linux/module.h>
  41 +#include <linux/types.h>
  42 +#include <linux/version.h>
  43 +#include <linux/errno.h>
  44 +#include <linux/slab.h>
  45 +#include <linux/mtd/mtd.h>
  46 +#include <linux/mtd/partitions.h>
  47 +#include <linux/platform_device.h>
  48 +#include <linux/sched.h>
  49 +#include <linux/squashfs_fs.h>
  50 +#include <linux/root_dev.h>
  51 +#include <linux/delay.h>
  52 +#include <asm/delay.h>
  53 +#include <asm/io.h>
  54 +
  55 +#include <ar2315_spiflash.h>
  56 +#include <ar231x_platform.h>
  57 +#include <ar231x.h>
  58 +
  59 +
  60 +#define SPIFLASH "spiflash: "
  61 +#define busy_wait(_priv, _condition, _wait) do { \
  62 +       while (_condition) { \
  63 +               spin_unlock_bh(&_priv->lock); \
  64 +               if (_wait > 1) \
  65 +                       msleep(_wait); \
  66 +               else if ((_wait == 1) && need_resched()) \
  67 +                       schedule(); \
  68 +               else \
  69 +                       udelay(1); \
  70 +               spin_lock_bh(&_priv->lock); \
  71 +       } \
  72 +} while (0)
  73 +
  74 +enum {
  75 +       FLASH_NONE,
  76 +       FLASH_1MB,
  77 +       FLASH_2MB,
  78 +       FLASH_4MB,
  79 +       FLASH_8MB,
  80 +       FLASH_16MB,
  81 +};
  82 +
  83 +/* Flash configuration table */
  84 +struct flashconfig {
  85 +       u32 byte_cnt;
  86 +       u32 sector_cnt;
  87 +       u32 sector_size;
  88 +};
  89 +
  90 +const struct flashconfig flashconfig_tbl[] = {
  91 +       [FLASH_NONE] = { 0, 0, 0},
  92 +       [FLASH_1MB]  = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE},
  93 +       [FLASH_2MB]  = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE},
  94 +       [FLASH_4MB]  = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE},
  95 +       [FLASH_8MB]  = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE},
  96 +       [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE}
  97 +};
  98 +
  99 +/* Mapping of generic opcodes to STM serial flash opcodes */
 100 +enum {
 101 +       SPI_WRITE_ENABLE,
 102 +       SPI_WRITE_DISABLE,
 103 +       SPI_RD_STATUS,
 104 +       SPI_WR_STATUS,
 105 +       SPI_RD_DATA,
 106 +       SPI_FAST_RD_DATA,
 107 +       SPI_PAGE_PROGRAM,
 108 +       SPI_SECTOR_ERASE,
 109 +       SPI_BULK_ERASE,
 110 +       SPI_DEEP_PWRDOWN,
 111 +       SPI_RD_SIG,
 112 +};
 113 +
 114 +struct opcodes {
 115 +    __u16 code;
 116 +    __s8 tx_cnt;
 117 +    __s8 rx_cnt;
 118 +};
 119 +const struct opcodes stm_opcodes[] = {
 120 +       [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
 121 +       [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
 122 +       [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
 123 +       [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
 124 +       [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
 125 +       [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
 126 +       [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
 127 +       [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
 128 +       [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
 129 +       [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
 130 +       [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
 131 +};
 132 +
 133 +/* Driver private data structure */
 134 +struct spiflash_priv {
 135 +       struct mtd_info mtd;
 136 +       void *readaddr; /* memory mapped data for read  */
 137 +       void *mmraddr;  /* memory mapped register space */
 138 +       wait_queue_head_t wq;
 139 +       spinlock_t lock;
 140 +       int state;
 141 +};
 142 +
 143 +#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
 144 +
 145 +enum {
 146 +       FL_READY,
 147 +       FL_READING,
 148 +       FL_ERASING,
 149 +       FL_WRITING
 150 +};
 151 +
 152 +/***************************************************************************************************/
 153 +
 154 +static u32
 155 +spiflash_read_reg(struct spiflash_priv *priv, int reg)
 156 +{
 157 +       return ar231x_read_reg((u32) priv->mmraddr + reg);
 158 +}
 159 +
 160 +static void
 161 +spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
 162 +{
 163 +       ar231x_write_reg((u32) priv->mmraddr + reg, data);
 164 +}
 165 +
 166 +static u32
 167 +spiflash_wait_busy(struct spiflash_priv *priv)
 168 +{
 169 +       u32 reg;
 170 +
 171 +       busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
 172 +               SPI_CTL_BUSY, 0);
 173 +       return reg;
 174 +}
 175 +
 176 +static u32
 177 +spiflash_sendcmd (struct spiflash_priv *priv, int opcode, u32 addr)
 178 +{
 179 +       const struct opcodes *op;
 180 +       u32 reg, mask;
 181 +
 182 +       op = &stm_opcodes[opcode];
 183 +       reg = spiflash_wait_busy(priv);
 184 +       spiflash_write_reg(priv, SPI_FLASH_OPCODE,
 185 +               ((u32) op->code) | (addr << 8));
 186 +
 187 +       reg &= ~SPI_CTL_TX_RX_CNT_MASK;
 188 +       reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
 189 +
 190 +       spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
 191 +       spiflash_wait_busy(priv);
 192 +
 193 +       if (!op->rx_cnt)
 194 +               return 0;
 195 +
 196 +       reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
 197 +
 198 +       switch (op->rx_cnt) {
 199 +       case 1:
 200 +               mask = 0x000000ff;
 201 +               break;
 202 +       case 2:
 203 +               mask = 0x0000ffff;
 204 +               break;
 205 +       case 3:
 206 +               mask = 0x00ffffff;
 207 +               break;
 208 +       default:
 209 +               mask = 0xffffffff;
 210 +               break;
 211 +       }
 212 +       reg &= mask;
 213 +
 214 +       return reg;
 215 +}
 216 +
 217 +
 218 +/*
 219 + * Probe SPI flash device
 220 + * Function returns 0 for failure.
 221 + * and flashconfig_tbl array index for success.
 222 + */
 223 +static int
 224 +spiflash_probe_chip (struct spiflash_priv *priv)
 225 +{
 226 +       u32 sig;
 227 +       int flash_size;
 228 +
 229 +       /* Read the signature on the flash device */
 230 +       spin_lock_bh(&priv->lock);
 231 +       sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
 232 +       spin_unlock_bh(&priv->lock);
 233 +
 234 +       switch (sig) {
 235 +       case STM_8MBIT_SIGNATURE:
 236 +               flash_size = FLASH_1MB;
 237 +               break;
 238 +       case STM_16MBIT_SIGNATURE:
 239 +               flash_size = FLASH_2MB;
 240 +               break;
 241 +       case STM_32MBIT_SIGNATURE:
 242 +               flash_size = FLASH_4MB;
 243 +               break;
 244 +       case STM_64MBIT_SIGNATURE:
 245 +               flash_size = FLASH_8MB;
 246 +               break;
 247 +       case STM_128MBIT_SIGNATURE:
 248 +               flash_size = FLASH_16MB;
 249 +               break;
 250 +       default:
 251 +               printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n");
 252 +               return 0;
 253 +       }
 254 +
 255 +       return flash_size;
 256 +}
 257 +
 258 +
 259 +/* wait until the flash chip is ready and grab a lock */
 260 +static int spiflash_wait_ready(struct spiflash_priv *priv, int state)
 261 +{
 262 +       DECLARE_WAITQUEUE(wait, current);
 263 +
 264 +retry:
 265 +       spin_lock_bh(&priv->lock);
 266 +       if (priv->state != FL_READY) {
 267 +               set_current_state(TASK_UNINTERRUPTIBLE);
 268 +               add_wait_queue(&priv->wq, &wait);
 269 +               spin_unlock_bh(&priv->lock);
 270 +               schedule();
 271 +               remove_wait_queue(&priv->wq, &wait);
 272 +
 273 +               if(signal_pending(current))
 274 +                       return 0;
 275 +
 276 +               goto retry;
 277 +       }
 278 +       priv->state = state;
 279 +
 280 +       return 1;
 281 +}
 282 +
 283 +static inline void spiflash_done(struct spiflash_priv *priv)
 284 +{
 285 +       priv->state = FL_READY;
 286 +       spin_unlock_bh(&priv->lock);
 287 +       wake_up(&priv->wq);
 288 +}
 289 +
 290 +static void
 291 +spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
 292 +{
 293 +       busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
 294 +               SPI_STATUS_WIP, timeout);
 295 +       spiflash_done(priv);
 296 +}
 297 +
 298 +
 299 +
 300 +static int
 301 +spiflash_erase (struct mtd_info *mtd, struct erase_info *instr)
 302 +{
 303 +       struct spiflash_priv *priv = to_spiflash(mtd);
 304 +       const struct opcodes *op;
 305 +       u32 temp, reg;
 306 +
 307 +       if (instr->addr + instr->len > mtd->size)
 308 +               return -EINVAL;
 309 +
 310 +       if (!spiflash_wait_ready(priv, FL_ERASING))
 311 +               return -EINTR;
 312 +
 313 +       spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
 314 +       reg = spiflash_wait_busy(priv);
 315 +
 316 +       op = &stm_opcodes[SPI_SECTOR_ERASE];
 317 +       temp = ((u32)instr->addr << 8) | (u32)(op->code);
 318 +       spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
 319 +
 320 +       reg &= ~SPI_CTL_TX_RX_CNT_MASK;
 321 +       reg |= op->tx_cnt | SPI_CTL_START;
 322 +       spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
 323 +
 324 +       spiflash_wait_complete(priv, 20);
 325 +
 326 +       instr->state = MTD_ERASE_DONE;
 327 +       if (instr->callback)
 328 +               instr->callback(instr);
 329 +
 330 +       return 0;
 331 +}
 332 +
 333 +static int
 334 +spiflash_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
 335 +{
 336 +       struct spiflash_priv *priv = to_spiflash(mtd);
 337 +       u8 *read_addr;
 338 +
 339 +       if (!len)
 340 +               return 0;
 341 +
 342 +       if (from + len > mtd->size)
 343 +               return -EINVAL;
 344 +
 345 +       *retlen = len;
 346 +
 347 +       if (!spiflash_wait_ready(priv, FL_READING))
 348 +               return -EINTR;
 349 +
 350 +       read_addr = (u8 *)(priv->readaddr + from);
 351 +       memcpy_fromio(buf, read_addr, len);
 352 +       spiflash_done(priv);
 353 +
 354 +       return 0;
 355 +}
 356 +
 357 +static int
 358 +spiflash_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u8 *buf)
 359 +{
 360 +       struct spiflash_priv *priv = to_spiflash(mtd);
 361 +       u32 opcode, bytes_left;
 362 +
 363 +       *retlen = 0;
 364 +
 365 +       if (!len)
 366 +               return 0;
 367 +
 368 +       if (to + len > mtd->size)
 369 +               return -EINVAL;
 370 +
 371 +       bytes_left = len;
 372 +
 373 +       do {
 374 +               u32 read_len, reg, page_offset, spi_data = 0;
 375 +
 376 +               read_len = min(bytes_left, sizeof(u32));
 377 +
 378 +               /* 32-bit writes cannot span across a page boundary
 379 +                * (256 bytes). This types of writes require two page
 380 +                * program operations to handle it correctly. The STM part
 381 +                * will write the overflow data to the beginning of the
 382 +                * current page as opposed to the subsequent page.
 383 +                */
 384 +               page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
 385 +
 386 +               if (page_offset > STM_PAGE_SIZE)
 387 +                       read_len -= (page_offset - STM_PAGE_SIZE);
 388 +
 389 +               if (!spiflash_wait_ready(priv, FL_WRITING))
 390 +                       return -EINTR;
 391 +
 392 +               spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
 393 +               spi_data = 0;
 394 +               switch (read_len) {
 395 +               case 4:
 396 +                       spi_data |= buf[3] << 24;
 397 +                       /* fall through */
 398 +               case 3:
 399 +                       spi_data |= buf[2] << 16;
 400 +                       /* fall through */
 401 +               case 2:
 402 +                       spi_data |= buf[1] << 8;
 403 +                       /* fall through */
 404 +               case 1:
 405 +                       spi_data |= buf[0] & 0xff;
 406 +                       break;
 407 +               default:
 408 +                       break;
 409 +               }
 410 +
 411 +               spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
 412 +               opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
 413 +                       (to & 0x00ffffff) << 8;
 414 +               spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
 415 +
 416 +               reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
 417 +               reg &= ~SPI_CTL_TX_RX_CNT_MASK;
 418 +               reg |= (read_len + 4) | SPI_CTL_START;
 419 +               spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
 420 +
 421 +               spiflash_wait_complete(priv, 1);
 422 +
 423 +               bytes_left -= read_len;
 424 +               to += read_len;
 425 +               buf += read_len;
 426 +
 427 +               *retlen += read_len;
 428 +       } while (bytes_left != 0);
 429 +
 430 +       return 0;
 431 +}
 432 +
 433 +
 434 +#ifdef CONFIG_MTD_PARTITIONS
 435 +static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL };
 436 +#endif
 437 +
 438 +
 439 +static int
 440 +spiflash_probe(struct platform_device *pdev)
 441 +{
 442 +       struct spiflash_priv *priv;
 443 +       struct mtd_partition *parts;
 444 +       struct mtd_info *mtd;
 445 +       int index, num_parts;
 446 +       int result = 0;
 447 +
 448 +       priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL);
 449 +       spin_lock_init(&priv->lock);
 450 +       init_waitqueue_head(&priv->wq);
 451 +       priv->state = FL_READY;
 452 +       mtd = &priv->mtd;
 453 +
 454 +       priv->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE);
 455 +       if (!priv->mmraddr) {
 456 +               printk(KERN_WARNING SPIFLASH "Failed to map flash device\n");
 457 +               goto error;
 458 +       }
 459 +
 460 +       index = spiflash_probe_chip(priv);
 461 +       if (!index) {
 462 +               printk (KERN_WARNING SPIFLASH "Found no serial flash device\n");
 463 +               goto error;
 464 +       }
 465 +
 466 +       priv->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt);
 467 +       if (!priv->readaddr) {
 468 +               printk (KERN_WARNING SPIFLASH "Failed to map flash device\n");
 469 +               goto error;
 470 +       }
 471 +
 472 +       platform_set_drvdata(pdev, priv);
 473 +       mtd->name = "spiflash";
 474 +       mtd->type = MTD_NORFLASH;
 475 +       mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
 476 +       mtd->size = flashconfig_tbl[index].byte_cnt;
 477 +       mtd->erasesize = flashconfig_tbl[index].sector_size;
 478 +       mtd->writesize = 1;
 479 +       mtd->numeraseregions = 0;
 480 +       mtd->eraseregions = NULL;
 481 +       mtd->erase = spiflash_erase;
 482 +       mtd->read = spiflash_read;
 483 +       mtd->write = spiflash_write;
 484 +       mtd->owner = THIS_MODULE;
 485 +
 486 +#ifdef CONFIG_MTD_PARTITIONS
 487 +       /* parse redboot partitions */
 488 +       num_parts = parse_mtd_partitions(mtd, part_probe_types, &parts, 0);
 489 +       if (!num_parts)
 490 +               goto error;
 491 +
 492 +       result = add_mtd_partitions(mtd, parts, num_parts);
 493 +#endif
 494 +
 495 +       return result;
 496 +
 497 +error:
 498 +       if (priv->mmraddr)
 499 +               iounmap(priv->mmraddr);
 500 +       kfree(priv);
 501 +       return -ENXIO;
 502 +}
 503 +
 504 +static int
 505 +spiflash_remove (struct platform_device *pdev)
 506 +{
 507 +       struct spiflash_priv *priv = platform_get_drvdata(pdev);
 508 +       struct mtd_info *mtd = &priv->mtd;
 509 +
 510 +       del_mtd_partitions(mtd);
 511 +       iounmap(priv->mmraddr);
 512 +       iounmap(priv->readaddr);
 513 +       kfree(priv);
 514 +
 515 +       return 0;
 516 +}
 517 +
 518 +struct platform_driver spiflash_driver = {
 519 +       .driver.name = "spiflash",
 520 +       .probe = spiflash_probe,
 521 +       .remove = spiflash_remove,
 522 +};
 523 +
 524 +int __init
 525 +spiflash_init (void)
 526 +{
 527 +       return platform_driver_register(&spiflash_driver);
 528 +}
 529 +
 530 +void __exit
 531 +spiflash_exit (void)
 532 +{
 533 +       return platform_driver_unregister(&spiflash_driver);
 534 +}
 535 +
 536 +module_init (spiflash_init);
 537 +module_exit (spiflash_exit);
 538 +
 539 +MODULE_LICENSE("GPL");
 540 +MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc");
 541 +MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");
 542 +
 543 --- /dev/null
 544 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h
 545 @@ -0,0 +1,116 @@
 546 +/*
 547 + * SPI Flash Memory support header file.
 548 + *
 549 + * Copyright (c) 2005, Atheros Communications Inc.
 550 + * Copyright (C) 2006 FON Technology, SL.
 551 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
 552 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
 553 + *
 554 + * This code is free software; you can redistribute it and/or modify
 555 + * it under the terms of the GNU General Public License version 2 as
 556 + * published by the Free Software Foundation.
 557 + *
 558 + */
 559 +#ifndef __AR2315_SPIFLASH_H
 560 +#define __AR2315_SPIFLASH_H
 561 +
 562 +#define STM_PAGE_SIZE           256
 563 +
 564 +#define SFI_WRITE_BUFFER_SIZE   4
 565 +#define SFI_FLASH_ADDR_MASK     0x00ffffff
 566 +
 567 +#define STM_8MBIT_SIGNATURE     0x13
 568 +#define STM_M25P80_BYTE_COUNT   1048576
 569 +#define STM_M25P80_SECTOR_COUNT 16
 570 +#define STM_M25P80_SECTOR_SIZE  0x10000
 571 +
 572 +#define STM_16MBIT_SIGNATURE    0x14
 573 +#define STM_M25P16_BYTE_COUNT   2097152
 574 +#define STM_M25P16_SECTOR_COUNT 32
 575 +#define STM_M25P16_SECTOR_SIZE  0x10000
 576 +
 577 +#define STM_32MBIT_SIGNATURE    0x15
 578 +#define STM_M25P32_BYTE_COUNT   4194304
 579 +#define STM_M25P32_SECTOR_COUNT 64
 580 +#define STM_M25P32_SECTOR_SIZE  0x10000
 581 +
 582 +#define STM_64MBIT_SIGNATURE    0x16
 583 +#define STM_M25P64_BYTE_COUNT   8388608
 584 +#define STM_M25P64_SECTOR_COUNT 128
 585 +#define STM_M25P64_SECTOR_SIZE  0x10000
 586 +
 587 +#define STM_128MBIT_SIGNATURE   0x17
 588 +#define STM_M25P128_BYTE_COUNT   16777216
 589 +#define STM_M25P128_SECTOR_COUNT 256
 590 +#define STM_M25P128_SECTOR_SIZE  0x10000
 591 +
 592 +#define STM_1MB_BYTE_COUNT   STM_M25P80_BYTE_COUNT
 593 +#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
 594 +#define STM_1MB_SECTOR_SIZE  STM_M25P80_SECTOR_SIZE
 595 +#define STM_2MB_BYTE_COUNT   STM_M25P16_BYTE_COUNT
 596 +#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
 597 +#define STM_2MB_SECTOR_SIZE  STM_M25P16_SECTOR_SIZE
 598 +#define STM_4MB_BYTE_COUNT   STM_M25P32_BYTE_COUNT
 599 +#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
 600 +#define STM_4MB_SECTOR_SIZE  STM_M25P32_SECTOR_SIZE
 601 +#define STM_8MB_BYTE_COUNT   STM_M25P64_BYTE_COUNT
 602 +#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
 603 +#define STM_8MB_SECTOR_SIZE  STM_M25P64_SECTOR_SIZE
 604 +#define STM_16MB_BYTE_COUNT   STM_M25P128_BYTE_COUNT
 605 +#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
 606 +#define STM_16MB_SECTOR_SIZE  STM_M25P128_SECTOR_SIZE
 607 +
 608 +/*
 609 + * ST Microelectronics Opcodes for Serial Flash
 610 + */
 611 +
 612 +#define STM_OP_WR_ENABLE       0x06     /* Write Enable */
 613 +#define STM_OP_WR_DISABLE      0x04     /* Write Disable */
 614 +#define STM_OP_RD_STATUS       0x05     /* Read Status */
 615 +#define STM_OP_WR_STATUS       0x01     /* Write Status */
 616 +#define STM_OP_RD_DATA         0x03     /* Read Data */
 617 +#define STM_OP_FAST_RD_DATA    0x0b     /* Fast Read Data */
 618 +#define STM_OP_PAGE_PGRM       0x02     /* Page Program */
 619 +#define STM_OP_SECTOR_ERASE    0xd8     /* Sector Erase */
 620 +#define STM_OP_BULK_ERASE      0xc7     /* Bulk Erase */
 621 +#define STM_OP_DEEP_PWRDOWN    0xb9     /* Deep Power-Down Mode */
 622 +#define STM_OP_RD_SIG          0xab     /* Read Electronic Signature */
 623 +
 624 +#define STM_STATUS_WIP       0x01       /* Write-In-Progress */
 625 +#define STM_STATUS_WEL       0x02       /* Write Enable Latch */
 626 +#define STM_STATUS_BP0       0x04       /* Block Protect 0 */
 627 +#define STM_STATUS_BP1       0x08       /* Block Protect 1 */
 628 +#define STM_STATUS_BP2       0x10       /* Block Protect 2 */
 629 +#define STM_STATUS_SRWD      0x80       /* Status Register Write Disable */
 630 +
 631 +/*
 632 + * SPI Flash Interface Registers
 633 + */
 634 +#define AR531XPLUS_SPI_READ     0x08000000
 635 +#define AR531XPLUS_SPI_MMR      0x11300000
 636 +#define AR531XPLUS_SPI_MMR_SIZE 12
 637 +
 638 +#define AR531XPLUS_SPI_CTL      0x00
 639 +#define AR531XPLUS_SPI_OPCODE   0x04
 640 +#define AR531XPLUS_SPI_DATA     0x08
 641 +
 642 +#define SPI_FLASH_READ          AR531XPLUS_SPI_READ
 643 +#define SPI_FLASH_MMR           AR531XPLUS_SPI_MMR
 644 +#define SPI_FLASH_MMR_SIZE      AR531XPLUS_SPI_MMR_SIZE
 645 +#define SPI_FLASH_CTL           AR531XPLUS_SPI_CTL
 646 +#define SPI_FLASH_OPCODE        AR531XPLUS_SPI_OPCODE
 647 +#define SPI_FLASH_DATA          AR531XPLUS_SPI_DATA
 648 +
 649 +#define SPI_CTL_START           0x00000100
 650 +#define SPI_CTL_BUSY            0x00010000
 651 +#define SPI_CTL_TXCNT_MASK      0x0000000f
 652 +#define SPI_CTL_RXCNT_MASK      0x000000f0
 653 +#define SPI_CTL_TX_RX_CNT_MASK  0x000000ff
 654 +#define SPI_CTL_SIZE_MASK       0x00060000
 655 +
 656 +#define SPI_CTL_CLK_SEL_MASK    0x03000000
 657 +#define SPI_OPCODE_MASK         0x000000ff
 658 +
 659 +#define SPI_STATUS_WIP         STM_STATUS_WIP
 660 +
 661 +#endif