target/linux/aruba-2.6/patches/000-aruba.patch

   1 diff -Nur linux-2.6.17/arch/mips/aruba/Makefile linux-2.6.17-owrt/arch/mips/aruba/Makefile
   2 --- linux-2.6.17/arch/mips/aruba/Makefile       1970-01-01 01:00:00.000000000 +0100
   3 +++ linux-2.6.17-owrt/arch/mips/aruba/Makefile  2006-06-18 12:44:28.000000000 +0200
   4 @@ -0,0 +1,49 @@
   5 +###############################################################################
   6 +#
   7 +#  BRIEF MODULE DESCRIPTION
   8 +#     Makefile for IDT EB434 BSP
   9 +#
  10 +#  Copyright 2004 IDT Inc. (rischelp@idt.com)
  11 +#
  12 +#  This program is free software; you can redistribute  it and/or modify it
  13 +#  under  the terms of  the GNU General  Public License as published by the
  14 +#  Free Software Foundation;  either version 2 of the  License, or (at your
  15 +#  option) any later version.
  16 +#
  17 +#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  18 +#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  19 +#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  20 +#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  21 +#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22 +#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  23 +#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  24 +#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  25 +#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26 +#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 +#
  28 +#   You should have received a copy of the  GNU General Public License along
  29 +#   with this program; if not, write  to the Free Software Foundation, Inc.,
  30 +#   675 Mass Ave, Cambridge, MA 02139, USA.
  31 +#
  32 +#
  33 +###############################################################################
  34 +#  May 2004 rkt, neb
  35 +#
  36 +#  Initial Release
  37 +#
  38 +#
  39 +#
  40 +###############################################################################
  41 +
  42 +
  43 +# .S.s:
  44 +#      $(CPP) $(CFLAGS) $< -o $*.s
  45 +# .S.o:
  46 +#      $(CC) $(CFLAGS) -c $< -o $*.o
  47 +
  48 +obj-y   := prom.o setup.o idtIRQ.o irq.o time.o flash_lock.o
  49 +obj-$(CONFIG_SERIAL_8250)              += serial.o
  50 +
  51 +subdir-y         += nvram
  52 +obj-y            += nvram/built-in.o
  53 +
  54 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/Makefile linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile
  55 --- linux-2.6.17/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
  56 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile    2006-06-18 12:44:28.000000000 +0200
  57 @@ -0,0 +1,46 @@
  58 +###############################################################################
  59 +#
  60 +#  BRIEF MODULE DESCRIPTION
  61 +#     Makefile for IDT EB434 nvram access routines
  62 +#
  63 +#  Copyright 2004 IDT Inc. (rischelp@idt.com)
  64 +#
  65 +#  This program is free software; you can redistribute  it and/or modify it
  66 +#  under  the terms of  the GNU General  Public License as published by the
  67 +#  Free Software Foundation;  either version 2 of the  License, or (at your
  68 +#  option) any later version.
  69 +#
  70 +#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  71 +#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  72 +#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  73 +#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  74 +#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  75 +#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  76 +#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  77 +#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  78 +#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  79 +#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  80 +#
  81 +#   You should have received a copy of the  GNU General Public License along
  82 +#   with this program; if not, write  to the Free Software Foundation, Inc.,
  83 +#   675 Mass Ave, Cambridge, MA 02139, USA.
  84 +#
  85 +#
  86 +###############################################################################
  87 +#  May 2004  rkt, neb
  88 +#
  89 +#  Initial Release
  90 +#
  91 +#
  92 +#
  93 +###############################################################################
  94 +
  95 +obj-y   := nvram434.o
  96 +obj-m   := $(O_TARGET)
  97 +
  98 +
  99 +
 100 +
 101 +
 102 +
 103 +
 104 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.c linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c
 105 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.c       1970-01-01 01:00:00.000000000 +0100
 106 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c  2006-06-18 12:44:28.000000000 +0200
 107 @@ -0,0 +1,392 @@
 108 +/**************************************************************************
 109 + *
 110 + *  BRIEF MODULE DESCRIPTION
 111 + *     nvram interface routines.
 112 + *
 113 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 114 + *
 115 + *  This program is free software; you can redistribute  it and/or modify it
 116 + *  under  the terms of  the GNU General  Public License as published by the
 117 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 118 + *  option) any later version.
 119 + *
 120 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 121 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 122 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 123 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 124 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 125 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 126 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 127 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 128 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 129 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 130 + *
 131 + *  You should have received a copy of the  GNU General Public License along
 132 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 133 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 134 + *
 135 + *
 136 + **************************************************************************
 137 + * May 2004 rkt, neb
 138 + *
 139 + * Initial Release
 140 + *
 141 + *
 142 + *
 143 + **************************************************************************
 144 + */
 145 +
 146 +#include <linux/ctype.h>
 147 +#include <linux/string.h>
 148 +
 149 +//#include <asm/ds1553rtc.h>
 150 +#include "nvram434.h"
 151 +#define  NVRAM_BASE 0xbfff8000
 152 +
 153 +extern void setenv (char *e, char *v, int rewrite);
 154 +extern void unsetenv (char *e);
 155 +extern void mapenv (int (*func)(char *, char *));
 156 +extern char *getenv (char *s);
 157 +extern void purgeenv(void);
 158 +
 159 +static void nvram_initenv(void);
 160 +
 161 +static unsigned char
 162 +nvram_getbyte(int offs)
 163 +{
 164 +  return(*((unsigned char*)(NVRAM_BASE + offs)));
 165 +}
 166 +
 167 +static void
 168 +nvram_setbyte(int offs, unsigned char val)
 169 +{
 170 +  unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
 171 +
 172 +  *nvramDataPointer = val;
 173 +}
 174 +
 175 +/*
 176 + * BigEndian!
 177 + */
 178 +static unsigned short
 179 +nvram_getshort(int offs)
 180 +{
 181 +  return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
 182 +}
 183 +
 184 +static void
 185 +nvram_setshort(int offs, unsigned short val)
 186 +{
 187 +  nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
 188 +  nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
 189 +}
 190 +#if 0
 191 +static unsigned int
 192 +nvram_getint(int offs)
 193 +{
 194 +  unsigned int val;
 195 +  val = nvram_getbyte(offs) << 24;
 196 +  val |= nvram_getbyte(offs + 1) << 16;
 197 +  val |= nvram_getbyte(offs + 2) << 8;
 198 +  val |= nvram_getbyte(offs + 3);
 199 +  return(val);
 200 +}
 201 +
 202 +static void
 203 +nvram_setint(int offs, unsigned int val)
 204 +{
 205 +  nvram_setbyte(offs, val >> 24);
 206 +  nvram_setbyte(offs + 1, val >> 16);
 207 +  nvram_setbyte(offs + 2, val >> 8);
 208 +  nvram_setbyte(offs + 3, val);
 209 +}
 210 +#endif
 211 +/*
 212 + * calculate NVRAM checksum
 213 + */
 214 +static unsigned short
 215 +nvram_calcsum(void)
 216 +{
 217 +  unsigned short sum = NV_MAGIC;
 218 +  int     i;
 219 +
 220 +  for (i = ENV_BASE; i < ENV_TOP; i += 2)
 221 +    sum += nvram_getshort(i);
 222 +  return(sum);
 223 +}
 224 +
 225 +/*
 226 + * update the nvram checksum
 227 + */
 228 +static void
 229 +nvram_updatesum (void)
 230 +{
 231 +  nvram_setshort(NVOFF_CSUM, nvram_calcsum());
 232 +}
 233 +
 234 +/*
 235 + * test validity of nvram by checksumming it
 236 + */
 237 +static int
 238 +nvram_isvalid(void)
 239 +{
 240 +  static int  is_valid;
 241 +
 242 +  if (is_valid)
 243 +    return(1);
 244 +
 245 +  if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
 246 +       printk("nvram_isvalid FAILED\n");
 247 +    //nvram_initenv();
 248 +  }
 249 +  is_valid = 1;
 250 +  return(1);
 251 +}
 252 +
 253 +/* return nvram address of environment string */
 254 +static int
 255 +nvram_matchenv(char *s)
 256 +{
 257 +  int envsize, envp, n, i, varsize;
 258 +  char *var;
 259 +
 260 +  envsize = nvram_getshort(NVOFF_ENVSIZE);
 261 +
 262 +  if (envsize > ENV_AVAIL)
 263 +    return(0);     /* sanity */
 264 +
 265 +  envp = ENV_BASE;
 266 +
 267 +  if ((n = strlen (s)) > 255)
 268 +    return(0);
 269 +
 270 +  while (envsize > 0) {
 271 +    varsize = nvram_getbyte(envp);
 272 +    if (varsize == 0 || (envp + varsize) > ENV_TOP)
 273 +      return(0);   /* sanity */
 274 +    for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
 275 +      char c1 = nvram_getbyte(i);
 276 +      char c2 = *var;
 277 +      if (islower(c1))
 278 +        c1 = toupper(c1);
 279 +      if (islower(c2))
 280 +        c2 = toupper(c2);
 281 +      if (c1 != c2)
 282 +        break;
 283 +    }
 284 +    if (i > envp + n) {       /* match so far */
 285 +      if (n == varsize - 1)   /* match on boolean */
 286 +        return(envp);
 287 +      if (nvram_getbyte(i) == '=')  /* exact match on variable */
 288 +        return(envp);
 289 +    }
 290 +    envsize -= varsize;
 291 +    envp += varsize;
 292 +  }
 293 +  return(0);
 294 +}
 295 +
 296 +static void nvram_initenv(void)
 297 +{
 298 +  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
 299 +  nvram_setshort(NVOFF_ENVSIZE, 0);
 300 +
 301 +  nvram_updatesum();
 302 +}
 303 +
 304 +static void
 305 +nvram_delenv(char *s)
 306 +{
 307 +  int nenvp, envp, envsize, nbytes;
 308 +
 309 +  envp = nvram_matchenv(s);
 310 +  if (envp == 0)
 311 +    return;
 312 +
 313 +  nenvp = envp + nvram_getbyte(envp);
 314 +  envsize = nvram_getshort(NVOFF_ENVSIZE);
 315 +  nbytes = envsize - (nenvp - ENV_BASE);
 316 +  nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
 317 +  while (nbytes--) {
 318 +    nvram_setbyte(envp, nvram_getbyte(nenvp));
 319 +    envp++;
 320 +    nenvp++;
 321 +  }
 322 +  nvram_updatesum();
 323 +}
 324 +
 325 +static int
 326 +nvram_setenv(char *s, char *v)
 327 +{
 328 +  int ns, nv, total;
 329 +  int envp;
 330 +
 331 +  if (!nvram_isvalid())
 332 +    return(-1);
 333 +
 334 +  nvram_delenv(s);
 335 +  ns = strlen(s);
 336 +  if (ns == 0)
 337 +    return (-1);
 338 +  if (v && *v) {
 339 +    nv = strlen(v);
 340 +    total = ns + nv + 2;
 341 +  }
 342 +  else {
 343 +    nv = 0;
 344 +    total = ns + 1;
 345 +  }
 346 +  if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
 347 +    return(-1);
 348 +
 349 +  envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
 350 +
 351 +  nvram_setbyte(envp, (unsigned char) total);
 352 +  envp++;
 353 +
 354 +  while (ns--) {
 355 +    nvram_setbyte(envp, *s);
 356 +    envp++;
 357 +    s++;
 358 +  }
 359 +
 360 +  if (nv) {
 361 +    nvram_setbyte(envp, '=');
 362 +    envp++;
 363 +    while (nv--) {
 364 +      nvram_setbyte(envp, *v);
 365 +      envp++;
 366 +      v++;
 367 +    }
 368 +  }
 369 +  nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
 370 +  nvram_updatesum();
 371 +  return 0;
 372 +}
 373 +
 374 +static char *
 375 +nvram_getenv(char *s)
 376 +{
 377 +  static char buf[256];   /* FIXME: this cannot be static */
 378 +  int envp, ns, nbytes, i;
 379 +
 380 +  if (!nvram_isvalid())
 381 +    return "INVALID NVRAM"; //((char *)0);
 382 +
 383 +  envp = nvram_matchenv(s);
 384 +  if (envp == 0)
 385 +    return "NOT FOUND"; //((char *)0);
 386 +  ns = strlen(s);
 387 +  if (nvram_getbyte(envp) == ns + 1)  /* boolean */
 388 +    buf[0] = '\0';
 389 +  else {
 390 +    nbytes = nvram_getbyte(envp) - (ns + 2);
 391 +    envp += ns + 2;
 392 +    for (i = 0; i < nbytes; i++)
 393 +      buf[i] = nvram_getbyte(envp++);
 394 +    buf[i] = '\0';
 395 +  }
 396 +  return(buf);
 397 +}
 398 +
 399 +static void
 400 +nvram_unsetenv(char *s)
 401 +{
 402 +  if (!nvram_isvalid())
 403 +    return;
 404 +
 405 +  nvram_delenv(s);
 406 +}
 407 +
 408 +/*
 409 + * apply func to each string in environment
 410 + */
 411 +static void
 412 +nvram_mapenv(int (*func)(char *, char *))
 413 +{
 414 +  int envsize, envp, n, i, seeneql;
 415 +  char name[256], value[256];
 416 +  char c, *s;
 417 +
 418 +  if (!nvram_isvalid())
 419 +    return;
 420 +
 421 +  envsize = nvram_getshort(NVOFF_ENVSIZE);
 422 +  envp = ENV_BASE;
 423 +
 424 +  while (envsize > 0) {
 425 +    value[0] = '\0';
 426 +    seeneql = 0;
 427 +    s = name;
 428 +    n = nvram_getbyte(envp);
 429 +    for (i = envp + 1; i < envp + n; i++) {
 430 +      c = nvram_getbyte(i);
 431 +      if ((c == '=') && !seeneql) {
 432 +        *s = '\0';
 433 +        s = value;
 434 +        seeneql = 1;
 435 +        continue;
 436 +      }
 437 +      *s++ = c;
 438 +    }
 439 +    *s = '\0';
 440 +    (*func)(name, value);
 441 +    envsize -= n;
 442 +    envp += n;
 443 +  }
 444 +}
 445 +#if 0
 446 +static unsigned int
 447 +digit(char c)
 448 +{
 449 +  if ('0' <= c && c <= '9')
 450 +    return (c - '0');
 451 +  if ('A' <= c && c <= 'Z')
 452 +    return (10 + c - 'A');
 453 +  if ('a' <= c && c <= 'z')
 454 +    return (10 + c - 'a');
 455 +  return (~0);
 456 +}
 457 +#endif
 458 +/*
 459 + * Wrappers to allow 'special' environment variables to get processed
 460 + */
 461 +void
 462 +setenv(char *e, char *v, int rewrite)
 463 +{
 464 +  if (nvram_getenv(e) && !rewrite)
 465 +    return;
 466 +
 467 +  nvram_setenv(e, v);
 468 +}
 469 +
 470 +char *
 471 +getenv(char *e)
 472 +{
 473 +  return(nvram_getenv(e));
 474 +}
 475 +
 476 +void
 477 +unsetenv(char *e)
 478 +{
 479 +  nvram_unsetenv(e);
 480 +}
 481 +
 482 +void
 483 +purgeenv()
 484 +{
 485 +  int i;
 486 +  unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
 487 +
 488 +  for (i = ENV_BASE; i < ENV_TOP; i++)
 489 +    *nvramDataPointer++ = 0;
 490 +  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
 491 +  nvram_setshort(NVOFF_ENVSIZE, 0);
 492 +  nvram_setshort(NVOFF_CSUM, NV_MAGIC);
 493 +}
 494 +
 495 +void
 496 +mapenv(int (*func)(char *, char *))
 497 +{
 498 +  nvram_mapenv(func);
 499 +}
 500 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.h linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h
 501 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.h       1970-01-01 01:00:00.000000000 +0100
 502 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h  2006-06-18 12:44:28.000000000 +0200
 503 @@ -0,0 +1,66 @@
 504 +/**************************************************************************
 505 + *
 506 + *  BRIEF MODULE DESCRIPTION
 507 + *     nvram definitions.
 508 + *
 509 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 510 + *
 511 + *  This program is free software; you can redistribute  it and/or modify it
 512 + *  under  the terms of  the GNU General  Public License as published by the
 513 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 514 + *  option) any later version.
 515 + *
 516 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 517 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 518 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 519 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 520 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 521 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 522 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 523 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 524 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 525 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 526 + *
 527 + *  You should have received a copy of the  GNU General Public License along
 528 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 529 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 530 + *
 531 + *
 532 + **************************************************************************
 533 + * May 2004 rkt, neb
 534 + *
 535 + * Initial Release
 536 + *
 537 + *
 538 + *
 539 + **************************************************************************
 540 + */
 541 +
 542 +
 543 +#ifndef _NVRAM_
 544 +#define _NVRAM_
 545 +#define NVOFFSET        0                 /* use all of NVRAM */
 546 +
 547 +/* Offsets to reserved locations */
 548 +              /* size description */
 549 +#define NVOFF_MAGIC     (NVOFFSET + 0)    /* 2 magic value */
 550 +#define NVOFF_CSUM      (NVOFFSET + 2)    /* 2 NVRAM environment checksum */
 551 +#define NVOFF_ENVSIZE   (NVOFFSET + 4)    /* 2 size of 'environment' */
 552 +#define NVOFF_TEST      (NVOFFSET + 5)    /* 1 cold start test byte */
 553 +#define NVOFF_ETHADDR   (NVOFFSET + 6)    /* 6 decoded ethernet address */
 554 +#define NVOFF_UNUSED    (NVOFFSET + 12)   /* 0 current end of table */
 555 +
 556 +#define NV_MAGIC        0xdeaf            /* nvram magic number */
 557 +#define NV_RESERVED     6                 /* number of reserved bytes */
 558 +
 559 +#undef  NVOFF_ETHADDR
 560 +#define NVOFF_ETHADDR   (NVOFFSET + NV_RESERVED - 6)
 561 +
 562 +/* number of bytes available for environment */
 563 +#define ENV_BASE        (NVOFFSET + NV_RESERVED)
 564 +#define ENV_TOP         0x2000
 565 +#define ENV_AVAIL       (ENV_TOP - ENV_BASE)
 566 +
 567 +#endif /* _NVRAM_ */
 568 +
 569 +
 570 diff -Nur linux-2.6.17/arch/mips/aruba/prom.c linux-2.6.17-owrt/arch/mips/aruba/prom.c
 571 --- linux-2.6.17/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
 572 +++ linux-2.6.17-owrt/arch/mips/aruba/prom.c    2006-06-18 12:44:28.000000000 +0200
 573 @@ -0,0 +1,111 @@
 574 +/**************************************************************************
 575 + *
 576 + *  BRIEF MODULE DESCRIPTION
 577 + *     prom interface routines
 578 + *
 579 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 580 + *
 581 + *  This program is free software; you can redistribute  it and/or modify it
 582 + *  under  the terms of  the GNU General  Public License as published by the
 583 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 584 + *  option) any later version.
 585 + *
 586 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 587 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 588 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 589 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 590 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 591 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 592 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 593 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 594 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 595 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 596 + *
 597 + *  You should have received a copy of the  GNU General Public License along
 598 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 599 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 600 + *
 601 + *
 602 + **************************************************************************
 603 + * May 2004 rkt, neb
 604 + *
 605 + * Initial Release
 606 + *
 607 + *
 608 + *
 609 + **************************************************************************
 610 + */
 611 +
 612 +#include <linux/config.h>
 613 +#include <linux/init.h>
 614 +#include <linux/mm.h>
 615 +#include <linux/module.h>
 616 +#include <linux/string.h>
 617 +#include <linux/console.h>
 618 +#include <asm/bootinfo.h>
 619 +#include <linux/bootmem.h>
 620 +#include <linux/ioport.h>
 621 +#include <linux/serial.h>
 622 +#include <linux/serialP.h>
 623 +#include <asm/serial.h>
 624 +#include <linux/ioport.h>
 625 +
 626 +unsigned int idt_cpu_freq;
 627 +EXPORT_SYMBOL(idt_cpu_freq);
 628 +
 629 +unsigned int arch_has_pci=0;
 630 +
 631 +/* Kernel Boot parameters */
 632 +static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
 633 +
 634 +extern unsigned long mips_machgroup;
 635 +extern unsigned long mips_machtype;
 636 +
 637 +extern void setup_serial_port(void);
 638 +extern char * getenv(char *e);
 639 +
 640 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
 641 +#define RAM_SIZE        32*1024*1024
 642 +
 643 +char *__init prom_getcmdline(void)
 644 +{
 645 +       return &(arcs_cmdline[0]);
 646 +}
 647 +
 648 +void __init prom_init(void)
 649 +{
 650 +       char *boardname;
 651 +       sprintf(arcs_cmdline, "%s", bootparm);
 652 +
 653 +       /* set our arch type */
 654 +       mips_machgroup = MACH_GROUP_ARUBA;
 655 +       mips_machtype = MACH_ARUBA_UNKNOWN;
 656 +
 657 +       boardname=getenv("boardname");
 658 +
 659 +       if (!strcmp(boardname,"Muscat")) {
 660 +               mips_machtype = MACH_ARUBA_AP70;
 661 +               idt_cpu_freq = 133000000;
 662 +               arch_has_pci=1;
 663 +       } else if (!strcmp(boardname,"Mataro")) {
 664 +               mips_machtype = MACH_ARUBA_AP65;
 665 +               idt_cpu_freq = 110000000;
 666 +       } else if (!strcmp(boardname,"Merlot")) {
 667 +               mips_machtype = MACH_ARUBA_AP60;
 668 +               idt_cpu_freq = 90000000;
 669 +       }
 670 +
 671 +       /* turn on the console */
 672 +       setup_serial_port();
 673 +
 674 +       /*
 675 +        * give all RAM to boot allocator,
 676 +        * except where the kernel was loaded
 677 +        */
 678 +       add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
 679 +}
 680 +
 681 +void prom_free_prom_memory(void)
 682 +{
 683 +       printk("stubbed prom_free_prom_memory()\n");
 684 +}
 685 diff -Nur linux-2.6.17/arch/mips/aruba/serial.c linux-2.6.17-owrt/arch/mips/aruba/serial.c
 686 --- linux-2.6.17/arch/mips/aruba/serial.c       1970-01-01 01:00:00.000000000 +0100
 687 +++ linux-2.6.17-owrt/arch/mips/aruba/serial.c  2006-06-18 12:44:28.000000000 +0200
 688 @@ -0,0 +1,94 @@
 689 +/**************************************************************************
 690 + *
 691 + *  BRIEF MODULE DESCRIPTION
 692 + *     Serial port initialisation.
 693 + *
 694 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 695 + *
 696 + *  This program is free software; you can redistribute  it and/or modify it
 697 + *  under  the terms of  the GNU General  Public License as published by the
 698 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 699 + *  option) any later version.
 700 + *
 701 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 702 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 703 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 704 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 705 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 706 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 707 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 708 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 709 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 710 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 711 + *
 712 + *  You should have received a copy of the  GNU General Public License along
 713 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 714 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 715 + *
 716 + *
 717 + **************************************************************************
 718 + * May 2004 rkt, neb
 719 + *
 720 + * Initial Release
 721 + *
 722 + *
 723 + *
 724 + **************************************************************************
 725 + */
 726 +
 727 +
 728 +#include <linux/config.h>
 729 +#include <linux/init.h>
 730 +#include <linux/sched.h>
 731 +#include <linux/pci.h>
 732 +#include <linux/interrupt.h>
 733 +#include <linux/tty.h>
 734 +#include <linux/serial.h>
 735 +#include <linux/serial_core.h>
 736 +
 737 +#include <asm/time.h>
 738 +#include <asm/cpu.h>
 739 +#include <asm/bootinfo.h>
 740 +#include <asm/irq.h>
 741 +#include <asm/serial.h>
 742 +
 743 +#include <asm/idt-boards/rc32434/rc32434.h>
 744 +
 745 +extern int __init early_serial_setup(struct uart_port *port);
 746 +
 747 +#define BASE_BAUD (1843200 / 16)
 748 +
 749 +extern unsigned int idt_cpu_freq;
 750 +
 751 +extern int __init setup_serial_port(void)
 752 +{
 753 +       static struct uart_port serial_req[2];
 754 +
 755 +       memset(serial_req, 0, sizeof(serial_req));
 756 +       serial_req[0].type       = PORT_16550A;
 757 +       serial_req[0].line       = 0;
 758 +       serial_req[0].flags      = STD_COM_FLAGS;
 759 +       serial_req[0].iotype     = SERIAL_IO_MEM;
 760 +       serial_req[0].regshift   = 2;
 761 +
 762 +       switch (mips_machtype) {
 763 +               case MACH_ARUBA_AP70:
 764 +                       serial_req[0].irq        = 104;
 765 +                       serial_req[0].mapbase    = KSEG1ADDR(0x18058003);
 766 +                       serial_req[0].membase    = (char *) KSEG1ADDR(0x18058003);
 767 +                       serial_req[0].uartclk    = idt_cpu_freq;
 768 +                       break;
 769 +               case MACH_ARUBA_AP65:
 770 +               case MACH_ARUBA_AP60:
 771 +               default:
 772 +                       serial_req[0].irq        = 12;
 773 +                       serial_req[0].mapbase    = KSEG1ADDR(0xbc000003);
 774 +                       serial_req[0].membase    = (char *) KSEG1ADDR(0xbc000003);
 775 +                       serial_req[0].uartclk    = idt_cpu_freq / 2;
 776 +                       break;
 777 +       }
 778 +
 779 +       early_serial_setup(&serial_req[0]);
 780 +
 781 +       return(0);
 782 +}
 783 diff -Nur linux-2.6.17/arch/mips/aruba/setup.c linux-2.6.17-owrt/arch/mips/aruba/setup.c
 784 --- linux-2.6.17/arch/mips/aruba/setup.c        1970-01-01 01:00:00.000000000 +0100
 785 +++ linux-2.6.17-owrt/arch/mips/aruba/setup.c   2006-06-18 12:44:28.000000000 +0200
 786 @@ -0,0 +1,134 @@
 787 +/**************************************************************************
 788 + *
 789 + *  BRIEF MODULE DESCRIPTION
 790 + *     setup routines for IDT EB434 boards
 791 + *
 792 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 793 + *
 794 + *  This program is free software; you can redistribute  it and/or modify it
 795 + *  under  the terms of  the GNU General  Public License as published by the
 796 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 797 + *  option) any later version.
 798 + *
 799 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 800 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 801 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 802 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 803 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 804 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 805 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 806 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 807 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 808 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 809 + *
 810 + *  You should have received a copy of the  GNU General Public License along
 811 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 812 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 813 + *
 814 + *
 815 + **************************************************************************
 816 + * May 2004 rkt, neb
 817 + *
 818 + * Initial Release
 819 + *
 820 + *
 821 + *
 822 + **************************************************************************
 823 + */
 824 +
 825 +#include <linux/init.h>
 826 +#include <linux/module.h>
 827 +#include <linux/mm.h>
 828 +#include <linux/sched.h>
 829 +#include <linux/irq.h>
 830 +#include <asm/bootinfo.h>
 831 +#include <asm/io.h>
 832 +#include <linux/ioport.h>
 833 +#include <asm/mipsregs.h>
 834 +#include <asm/pgtable.h>
 835 +#include <asm/reboot.h>
 836 +#include <asm/addrspace.h>     /* for KSEG1ADDR() */
 837 +#include <asm/idt-boards/rc32434/rc32434.h>
 838 +#include <linux/pm.h>
 839 +
 840 +extern char *__init prom_getcmdline(void);
 841 +
 842 +extern void (*board_time_init) (void);
 843 +extern void (*board_timer_setup) (struct irqaction * irq);
 844 +extern void aruba_time_init(void);
 845 +extern void aruba_timer_setup(struct irqaction *irq);
 846 +extern void aruba_reset(void);
 847 +
 848 +#define epldMask ((volatile unsigned char *)0xB900000d)
 849 +
 850 +static void aruba_machine_restart(char *command)
 851 +{
 852 +       switch (mips_machtype) {
 853 +               case MACH_ARUBA_AP70:
 854 +                       *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
 855 +                       break;
 856 +               case MACH_ARUBA_AP65:
 857 +               case MACH_ARUBA_AP60:
 858 +               default:
 859 +                       /* Reset*/
 860 +                       *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
 861 +                       udelay(100);
 862 +                       *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
 863 +                       udelay(100);
 864 +                       *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
 865 +                       break;
 866 +       }
 867 +}
 868 +
 869 +static void aruba_machine_halt(void)
 870 +{
 871 +       for (;;) continue;
 872 +}
 873 +
 874 +extern char * getenv(char *e);
 875 +extern void unlock_ap60_70_flash(void);
 876 +
 877 +void __init plat_setup(void)
 878 +{
 879 +       board_time_init = aruba_time_init;
 880 +
 881 +       board_timer_setup = aruba_timer_setup;
 882 +
 883 +       _machine_restart = aruba_machine_restart;
 884 +       _machine_halt = aruba_machine_halt;
 885 +       pm_power_off = aruba_machine_halt;
 886 +
 887 +       set_io_port_base(KSEG1);
 888 +
 889 +       /* Enable PCI interrupts in EPLD Mask register */
 890 +       *epldMask = 0x0;
 891 +       *(epldMask + 1) = 0x0;
 892 +
 893 +       write_c0_wired(0);
 894 +       unlock_ap60_70_flash();
 895 +
 896 +       printk("BOARD - %s\n",getenv("boardname"));
 897 +
 898 +       return 0;
 899 +}
 900 +
 901 +int page_is_ram(unsigned long pagenr)
 902 +{
 903 +       return 1;
 904 +}
 905 +
 906 +const char *get_system_type(void)
 907 +{
 908 +       switch (mips_machtype) {
 909 +               case MACH_ARUBA_AP70:
 910 +                       return "Aruba AP70";
 911 +               case MACH_ARUBA_AP65:
 912 +                       return "Aruba AP65";
 913 +               case MACH_ARUBA_AP60:
 914 +                       return "Aruba AP60/AP61";
 915 +               default:
 916 +                       return "Aruba UNKNOWN";
 917 +       }
 918 +}
 919 +
 920 +EXPORT_SYMBOL(get_system_type);
 921 diff -Nur linux-2.6.17/arch/mips/aruba/time.c linux-2.6.17-owrt/arch/mips/aruba/time.c
 922 --- linux-2.6.17/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
 923 +++ linux-2.6.17-owrt/arch/mips/aruba/time.c    2006-06-18 12:44:28.000000000 +0200
 924 @@ -0,0 +1,108 @@
 925 +/**************************************************************************
 926 + *
 927 + *  BRIEF MODULE DESCRIPTION
 928 + *     timer routines for IDT EB434 boards
 929 + *
 930 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 931 + *
 932 + *  This program is free software; you can redistribute  it and/or modify it
 933 + *  under  the terms of  the GNU General  Public License as published by the
 934 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 935 + *  option) any later version.
 936 + *
 937 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 938 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 939 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 940 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 941 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 942 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 943 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 944 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 945 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 946 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 947 + *
 948 + *  You should have received a copy of the  GNU General Public License along
 949 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 950 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 951 + *
 952 + *
 953 + **************************************************************************
 954 + * May 2004 rkt, neb
 955 + *
 956 + * Initial Release
 957 + *
 958 + *
 959 + *
 960 + **************************************************************************
 961 + */
 962 +
 963 +#include <linux/config.h>
 964 +#include <linux/init.h>
 965 +#include <linux/kernel_stat.h>
 966 +#include <linux/sched.h>
 967 +#include <linux/spinlock.h>
 968 +#include <linux/mc146818rtc.h>
 969 +#include <linux/irq.h>
 970 +#include <linux/timex.h>
 971 +
 972 +#include <linux/param.h>
 973 +#include <asm/mipsregs.h>
 974 +#include <asm/ptrace.h>
 975 +#include <asm/time.h>
 976 +#include <asm/hardirq.h>
 977 +
 978 +#include <asm/mipsregs.h>
 979 +#include <asm/ptrace.h>
 980 +#include <asm/debug.h>
 981 +#include <asm/time.h>
 982 +
 983 +#include <asm/idt-boards/rc32434/rc32434.h>
 984 +
 985 +static unsigned long r4k_offset;       /* Amount to incr compare reg each time */
 986 +static unsigned long r4k_cur;  /* What counter should be at next timer irq */
 987 +
 988 +extern unsigned int idt_cpu_freq;
 989 +
 990 +static unsigned long __init cal_r4koff(void)
 991 +{
 992 +       mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
 993 +       return (mips_hpt_frequency / HZ);
 994 +}
 995 +
 996 +void __init aruba_time_init(void)
 997 +{
 998 +       unsigned int est_freq, flags;
 999 +       local_irq_save(flags);
1000 +
1001 +       printk("calculating r4koff... ");
1002 +       r4k_offset = cal_r4koff();
1003 +       printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
1004 +
1005 +       est_freq = 2 * r4k_offset * HZ;
1006 +       est_freq += 5000;       /* round */
1007 +       est_freq -= est_freq % 10000;
1008 +       printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
1009 +              (est_freq % 1000000) * 100 / 1000000);
1010 +       local_irq_restore(flags);
1011 +
1012 +}
1013 +
1014 +void __init aruba_timer_setup(struct irqaction *irq)
1015 +{
1016 +       /* we are using the cpu counter for timer interrupts */
1017 +       setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1018 +
1019 +       /* to generate the first timer interrupt */
1020 +       r4k_cur = (read_c0_count() + r4k_offset);
1021 +       write_c0_compare(r4k_cur);
1022 +
1023 +}
1024 +
1025 +asmlinkage void aruba_timer_interrupt(int irq, struct pt_regs *regs)
1026 +{
1027 +       irq_enter();
1028 +       kstat_this_cpu.irqs[irq]++;
1029 +
1030 +       timer_interrupt(irq, NULL, regs);
1031 +       irq_exit();
1032 +}
1033 diff -Nur linux-2.6.17/arch/mips/Kconfig linux-2.6.17-owrt/arch/mips/Kconfig
1034 --- linux-2.6.17/arch/mips/Kconfig      2006-06-18 03:49:35.000000000 +0200
1035 +++ linux-2.6.17-owrt/arch/mips/Kconfig 2006-06-18 12:44:28.000000000 +0200
1036 @@ -227,6 +227,17 @@
1037           either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1038           a kernel for this platform.
1039
1040 +config MACH_ARUBA
1041 +       bool "Support for the ARUBA product line"
1042 +       select DMA_NONCOHERENT
1043 +       select CPU_HAS_PREFETCH
1044 +       select HW_HAS_PCI
1045 +       select SWAP_IO_SPACE
1046 +       select SYS_SUPPORTS_32BIT_KERNEL
1047 +       select SYS_HAS_CPU_MIPS32_R1
1048 +       select SYS_SUPPORTS_BIG_ENDIAN
1049 +
1050 +
1051  config MACH_JAZZ
1052         bool "Jazz family of machines"
1053         select ARC
1054 diff -Nur linux-2.6.17/arch/mips/Makefile linux-2.6.17-owrt/arch/mips/Makefile
1055 --- linux-2.6.17/arch/mips/Makefile     2006-06-18 03:49:35.000000000 +0200
1056 +++ linux-2.6.17-owrt/arch/mips/Makefile        2006-06-18 12:44:28.000000000 +0200
1057 @@ -145,6 +145,14 @@
1058  #
1059
1060  #
1061 +# Aruba
1062 +#
1063 +
1064 +core-$(CONFIG_MACH_ARUBA)      += arch/mips/aruba/
1065 +cflags-$(CONFIG_MACH_ARUBA)    += -Iinclude/asm-mips/aruba
1066 +load-$(CONFIG_MACH_ARUBA)      += 0x80100000
1067 +
1068 +#
1069  # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1070  #
1071  core-$(CONFIG_MACH_JAZZ)       += arch/mips/jazz/
1072 diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex.c
1073 --- linux-2.6.17/arch/mips/mm/tlbex.c   2006-06-18 03:49:35.000000000 +0200
1074 +++ linux-2.6.17-owrt/arch/mips/mm/tlbex.c      2006-06-18 12:48:27.000000000 +0200
1075 @@ -876,7 +876,6 @@
1076         case CPU_R10000:
1077         case CPU_R12000:
1078         case CPU_R14000:
1079 -       case CPU_4KC:
1080         case CPU_SB1:
1081         case CPU_SB1A:
1082         case CPU_4KSC:
1083 @@ -904,6 +903,7 @@
1084                 tlbw(p);
1085                 break;
1086
1087 +       case CPU_4KC:
1088         case CPU_4KEC:
1089         case CPU_24K:
1090         case CPU_34K:
1091 diff -Nur linux-2.6.17/drivers/net/Kconfig linux-2.6.17-owrt/drivers/net/Kconfig
1092 --- linux-2.6.17/drivers/net/Kconfig    2006-06-18 03:49:35.000000000 +0200
1093 +++ linux-2.6.17-owrt/drivers/net/Kconfig       2006-06-18 12:44:28.000000000 +0200
1094 @@ -187,6 +187,13 @@
1095
1096  source "drivers/net/arm/Kconfig"
1097
1098 +config IDT_RC32434_ETH
1099 +        tristate "IDT RC32434 Local Ethernet support"
1100 +        depends on NET_ETHERNET
1101 +        help
1102 +        IDT RC32434 has one local ethernet port. Say Y here to enable it.
1103 +        To compile this driver as a module, choose M here.
1104 +
1105  config MACE
1106         tristate "MACE (Power Mac ethernet) support"
1107         depends on NET_ETHERNET && PPC_PMAC && PPC32
1108 diff -Nur linux-2.6.17/drivers/net/Makefile linux-2.6.17-owrt/drivers/net/Makefile
1109 --- linux-2.6.17/drivers/net/Makefile   2006-06-18 03:49:35.000000000 +0200
1110 +++ linux-2.6.17-owrt/drivers/net/Makefile      2006-06-18 12:44:28.000000000 +0200
1111 @@ -38,6 +38,7 @@
1112
1113  obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
1114
1115 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1116  obj-$(CONFIG_DGRS) += dgrs.o
1117  obj-$(CONFIG_VORTEX) += 3c59x.o
1118  obj-$(CONFIG_TYPHOON) += typhoon.o
1119 diff -Nur linux-2.6.17/drivers/net/natsemi.c linux-2.6.17-owrt/drivers/net/natsemi.c
1120 --- linux-2.6.17/drivers/net/natsemi.c  2006-06-18 03:49:35.000000000 +0200
1121 +++ linux-2.6.17-owrt/drivers/net/natsemi.c     2006-06-18 12:44:28.000000000 +0200
1122 @@ -771,6 +771,49 @@
1123  static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
1124  static struct ethtool_ops ethtool_ops;
1125
1126 +#ifdef CONFIG_MACH_ARUBA
1127 +
1128 +#include <linux/ctype.h>
1129 +
1130 +#ifndef ERR
1131 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
1132 +#endif
1133 +
1134 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1135 +{
1136 +        int i, j;
1137 +        unsigned char result, value;
1138 +
1139 +        for (i=0; i<6; i++) {
1140 +                result = 0;
1141 +                if (i != 5 && *(macstr+2) != ':') {
1142 +                        ERR("invalid mac address format: %d %c\n",
1143 +                            i, *(macstr+2));
1144 +                        return -EINVAL;
1145 +                }
1146 +                for (j=0; j<2; j++) {
1147 +                        if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1148 +                                                  toupper(*macstr)-'A'+10) < 16) {
1149 +                                result = result*16 + value;
1150 +                                macstr++;
1151 +                        }
1152 +                        else {
1153 +                                ERR("invalid mac address "
1154 +                                    "character: %c\n", *macstr);
1155 +                                return -EINVAL;
1156 +                        }
1157 +                }
1158 +
1159 +                macstr++;
1160 +                dev->dev_addr[i] = result;
1161 +        }
1162 +
1163 +       dev->dev_addr[5]++;
1164 +        return 0;
1165 +}
1166 +
1167 +#endif
1168 +
1169  static inline void __iomem *ns_ioaddr(struct net_device *dev)
1170  {
1171         return (void __iomem *) dev->base_addr;
1172 @@ -871,6 +914,7 @@
1173                 goto err_ioremap;
1174         }
1175
1176 +#ifndef CONFIG_MACH_ARUBA
1177         /* Work around the dropped serial bit. */
1178         prev_eedata = eeprom_read(ioaddr, 6);
1179         for (i = 0; i < 3; i++) {
1180 @@ -879,6 +923,19 @@
1181                 dev->dev_addr[i*2+1] = eedata >> 7;
1182                 prev_eedata = eedata;
1183         }
1184 +#else
1185 +       {
1186 +               char mac[32];
1187 +               unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
1188 +               extern char *getenv(char *e);
1189 +               memset(mac, 0, 32);
1190 +               memcpy(mac, getenv("ethaddr"), 17);
1191 +               if (parse_mac_addr(dev, mac)){
1192 +                       printk("%s: MAC address not found\n", __func__);
1193 +                       memcpy(dev->dev_addr, def_mac, 6);
1194 +               }
1195 +       }
1196 +#endif
1197
1198         dev->base_addr = (unsigned long __force) ioaddr;
1199         dev->irq = irq;
1200 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.c linux-2.6.17-owrt/drivers/net/rc32434_eth.c
1201 --- linux-2.6.17/drivers/net/rc32434_eth.c      1970-01-01 01:00:00.000000000 +0100
1202 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.c 2006-06-18 12:44:28.000000000 +0200
1203 @@ -0,0 +1,1268 @@
1204 +/**************************************************************************
1205 + *
1206 + *  BRIEF MODULE DESCRIPTION
1207 + *     Driver for the IDT RC32434 on-chip ethernet controller.
1208 + *
1209 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
1210 + *
1211 + *  This program is free software; you can redistribute  it and/or modify it
1212 + *  under  the terms of  the GNU General  Public License as published by the
1213 + *  Free Software Foundation;  either version 2 of the  License, or (at your
1214 + *  option) any later version.
1215 + *
1216 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
1217 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
1218 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
1219 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
1220 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1221 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
1222 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1223 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
1224 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1225 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1226 + *
1227 + *  You should have received a copy of the  GNU General Public License along
1228 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
1229 + *  675 Mass Ave, Cambridge, MA 02139, USA.
1230 + *
1231 + *
1232 + **************************************************************************
1233 + * May 2004 rkt, neb
1234 + *
1235 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1236 + *
1237 + * Aug 2004 Sadik
1238 + *
1239 + * Added NAPI
1240 + *
1241 + **************************************************************************
1242 + */
1243 +
1244 +#include <linux/config.h>
1245 +#include <linux/module.h>
1246 +#include <linux/kernel.h>
1247 +#include <linux/moduleparam.h>
1248 +#include <linux/sched.h>
1249 +#include <linux/ctype.h>
1250 +#include <linux/types.h>
1251 +#include <linux/fcntl.h>
1252 +#include <linux/interrupt.h>
1253 +#include <linux/ptrace.h>
1254 +#include <linux/init.h>
1255 +#include <linux/ioport.h>
1256 +#include <linux/proc_fs.h>
1257 +#include <linux/in.h>
1258 +#include <linux/slab.h>
1259 +#include <linux/string.h>
1260 +#include <linux/delay.h>
1261 +#include <linux/netdevice.h>
1262 +#include <linux/etherdevice.h>
1263 +#include <linux/skbuff.h>
1264 +#include <linux/errno.h>
1265 +#include <asm/bootinfo.h>
1266 +#include <asm/system.h>
1267 +#include <asm/bitops.h>
1268 +#include <asm/pgtable.h>
1269 +#include <asm/segment.h>
1270 +#include <asm/io.h>
1271 +#include <asm/dma.h>
1272 +
1273 +#include "rc32434_eth.h"
1274 +
1275 +#define DRIVER_VERSION "(mar2904)"
1276 +
1277 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1278 +
1279 +
1280 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1281 +                                  ((dev)->dev_addr[1]))
1282 +#define STATION_ADDRESS_LOW(dev)  (((dev)->dev_addr[2] << 24) | \
1283 +                                  ((dev)->dev_addr[3] << 16) | \
1284 +                                  ((dev)->dev_addr[4] << 8)  | \
1285 +                                  ((dev)->dev_addr[5]))
1286 +
1287 +#define MII_CLOCK 1250000                              /* no more than 2.5MHz */
1288 +static char mac0[18] = "08:00:06:05:40:01";
1289 +
1290 +MODULE_PARM(mac0, "c18");
1291 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1292 +
1293 +static struct rc32434_if_t {
1294 +       char *name;
1295 +       struct net_device *dev;
1296 +       char* mac_str;
1297 +       int weight;
1298 +       u32 iobase;
1299 +       u32 rxdmabase;
1300 +       u32 txdmabase;
1301 +       int rx_dma_irq;
1302 +       int tx_dma_irq;
1303 +       int rx_ovr_irq;
1304 +       int tx_und_irq;
1305 +} rc32434_iflist[] =
1306 +{
1307 +       {
1308 +               "rc32434_eth0",      NULL,       mac0,
1309 +               64,
1310 +               ETH0_PhysicalAddress,
1311 +               ETH0_RX_DMA_ADDR,
1312 +               ETH0_TX_DMA_ADDR,
1313 +               ETH0_DMA_RX_IRQ,
1314 +               ETH0_DMA_TX_IRQ,
1315 +               ETH0_RX_OVR_IRQ,
1316 +               ETH0_TX_UND_IRQ
1317 +       }
1318 +};
1319 +
1320 +
1321 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1322 +{
1323 +       int i, j;
1324 +       unsigned char result, value;
1325 +
1326 +       for (i=0; i<6; i++) {
1327 +               result = 0;
1328 +               if (i != 5 && *(macstr+2) != ':') {
1329 +                       ERR("invalid mac address format: %d %c\n",
1330 +                           i, *(macstr+2));
1331 +                       return -EINVAL;
1332 +               }
1333 +               for (j=0; j<2; j++) {
1334 +                       if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1335 +                                                 toupper(*macstr)-'A'+10) < 16) {
1336 +                               result = result*16 + value;
1337 +                               macstr++;
1338 +                       }
1339 +                       else {
1340 +                               ERR("invalid mac address "
1341 +                                   "character: %c\n", *macstr);
1342 +                               return -EINVAL;
1343 +                       }
1344 +               }
1345 +
1346 +               macstr++;
1347 +               dev->dev_addr[i] = result;
1348 +       }
1349 +
1350 +       return 0;
1351 +}
1352 +
1353 +
1354 +
1355 +static inline void rc32434_abort_tx(struct net_device *dev)
1356 +{
1357 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1358 +       rc32434_abort_dma(dev, lp->tx_dma_regs);
1359 +
1360 +}
1361 +
1362 +static inline void rc32434_abort_rx(struct net_device *dev)
1363 +{
1364 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1365 +       rc32434_abort_dma(dev, lp->rx_dma_regs);
1366 +
1367 +}
1368 +
1369 +static inline void rc32434_start_tx(struct rc32434_local *lp,  volatile DMAD_t td)
1370 +{
1371 +       rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1372 +}
1373 +
1374 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1375 +{
1376 +       rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1377 +}
1378 +
1379 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1380 +{
1381 +       rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1382 +}
1383 +
1384 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1385 +{
1386 +       rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1387 +}
1388 +
1389 +#ifdef RC32434_PROC_DEBUG
1390 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1391 +                            int length, int *eof, void *data)
1392 +{
1393 +       struct net_device *dev = (struct net_device *)data;
1394 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1395 +       int len = 0;
1396 +
1397 +       /* print out header */
1398 +       len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1399 +       len += sprintf (buf + len,
1400 +                       "DMA halt count      = %10d, DMA run count = %10d\n",
1401 +                       lp->dma_halt_cnt, lp->dma_run_cnt);
1402 +
1403 +       if (fpos >= len) {
1404 +               *start = buf;
1405 +               *eof = 1;
1406 +               return 0;
1407 +       }
1408 +       *start = buf + fpos;
1409 +
1410 +       if ((len -= fpos) > length)
1411 +               return length;
1412 +       *eof = 1;
1413 +
1414 +       return len;
1415 +
1416 +}
1417 +#endif
1418 +
1419 +
1420 +/*
1421 + * Restart the RC32434 ethernet controller.
1422 + */
1423 +static int rc32434_restart(struct net_device *dev)
1424 +{
1425 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1426 +
1427 +       /*
1428 +        * Disable interrupts
1429 +        */
1430 +       disable_irq(lp->rx_irq);
1431 +       disable_irq(lp->tx_irq);
1432 +#ifdef RC32434_REVISION
1433 +       disable_irq(lp->ovr_irq);
1434 +#endif
1435 +       disable_irq(lp->und_irq);
1436 +
1437 +       /* Mask F E bit in Tx DMA */
1438 +       rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1439 +       /* Mask D H E bit in Rx DMA */
1440 +       rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1441 +
1442 +       rc32434_init(dev);
1443 +       rc32434_multicast_list(dev);
1444 +
1445 +       enable_irq(lp->und_irq);
1446 +#ifdef RC32434_REVISION
1447 +       enable_irq(lp->ovr_irq);
1448 +#endif
1449 +       enable_irq(lp->tx_irq);
1450 +       enable_irq(lp->rx_irq);
1451 +
1452 +       return 0;
1453 +}
1454 +
1455 +int rc32434_init_module(void)
1456 +{
1457 +#ifdef CONFIG_MACH_ARUBA
1458 +       if (mips_machtype != MACH_ARUBA_AP70)
1459 +               return 1;
1460 +#endif
1461 +
1462 +       printk(KERN_INFO DRIVER_NAME " \n");
1463 +       return rc32434_probe(0);
1464 +}
1465 +
1466 +static int rc32434_probe(int port_num)
1467 +{
1468 +       struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1469 +       struct rc32434_local *lp = NULL;
1470 +       struct net_device *dev = NULL;
1471 +       int i, retval,err;
1472 +
1473 +       dev = alloc_etherdev(sizeof(struct rc32434_local));
1474 +       if(!dev) {
1475 +               ERR("rc32434_eth: alloc_etherdev failed\n");
1476 +               return -1;
1477 +       }
1478 +
1479 +       SET_MODULE_OWNER(dev);
1480 +       bif->dev = dev;
1481 +
1482 +#ifdef CONFIG_MACH_ARUBA
1483 +       {
1484 +               extern char * getenv(char *e);
1485 +               memcpy(bif->mac_str, getenv("ethaddr"), 17);
1486 +       }
1487 +#endif
1488 +
1489 +       printk("mac: %s\n", bif->mac_str);
1490 +       if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1491 +               ERR("MAC address parse failed\n");
1492 +               free_netdev(dev);
1493 +               return -1;
1494 +       }
1495 +
1496 +
1497 +       /* Initialize the device structure. */
1498 +       if (dev->priv == NULL) {
1499 +               lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1500 +               memset(lp, 0, sizeof(struct rc32434_local));
1501 +       }
1502 +       else {
1503 +               lp = (struct rc32434_local *)dev->priv;
1504 +       }
1505 +
1506 +       lp->rx_irq = bif->rx_dma_irq;
1507 +       lp->tx_irq = bif->tx_dma_irq;
1508 +       lp->ovr_irq = bif->rx_ovr_irq;
1509 +       lp->und_irq = bif->tx_und_irq;
1510 +
1511 +       lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1512 +
1513 +       if (!lp->eth_regs) {
1514 +               ERR("Can't remap eth registers\n");
1515 +               retval = -ENXIO;
1516 +               goto probe_err_out;
1517 +       }
1518 +
1519 +       lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1520 +
1521 +       if (!lp->rx_dma_regs) {
1522 +               ERR("Can't remap Rx DMA registers\n");
1523 +               retval = -ENXIO;
1524 +               goto probe_err_out;
1525 +       }
1526 +       lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1527 +
1528 +       if (!lp->tx_dma_regs) {
1529 +               ERR("Can't remap Tx DMA registers\n");
1530 +               retval = -ENXIO;
1531 +               goto probe_err_out;
1532 +       }
1533 +
1534 +#ifdef RC32434_PROC_DEBUG
1535 +       lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1536 +                                        rc32434_read_proc, dev);
1537 +#endif
1538 +
1539 +       lp->td_ring =   (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1540 +       if (!lp->td_ring) {
1541 +               ERR("Can't allocate descriptors\n");
1542 +               retval = -ENOMEM;
1543 +               goto probe_err_out;
1544 +       }
1545 +
1546 +       dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1547 +
1548 +       /* now convert TD_RING pointer to KSEG1 */
1549 +       lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1550 +       lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1551 +
1552 +
1553 +       spin_lock_init(&lp->lock);
1554 +
1555 +       dev->base_addr = bif->iobase;
1556 +       /* just use the rx dma irq */
1557 +       dev->irq = bif->rx_dma_irq;
1558 +
1559 +       dev->priv = lp;
1560 +
1561 +       dev->open = rc32434_open;
1562 +       dev->stop = rc32434_close;
1563 +       dev->hard_start_xmit = rc32434_send_packet;
1564 +       dev->get_stats  = rc32434_get_stats;
1565 +       dev->set_multicast_list = &rc32434_multicast_list;
1566 +       dev->tx_timeout = rc32434_tx_timeout;
1567 +       dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1568 +
1569 +#ifdef CONFIG_IDT_USE_NAPI
1570 +       dev->poll = rc32434_poll;
1571 +       dev->weight = bif->weight;
1572 +       printk("Using NAPI with weight %d\n",dev->weight);
1573 +#else
1574 +       lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1575 +       tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1576 +#endif
1577 +       lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1578 +       tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1579 +
1580 +       if ((err = register_netdev(dev))) {
1581 +               printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1582 +               free_netdev(dev);
1583 +               retval = -EINVAL;
1584 +               goto probe_err_out;
1585 +       }
1586 +
1587 +       INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1588 +       for (i = 0; i < 6; i++) {
1589 +               printk("%2.2x", dev->dev_addr[i]);
1590 +               if (i<5)
1591 +                       printk(":");
1592 +       }
1593 +       printk("\n");
1594 +
1595 +       return 0;
1596 +
1597 + probe_err_out:
1598 +       rc32434_cleanup_module();
1599 +       ERR(" failed.  Returns %d\n", retval);
1600 +       return retval;
1601 +
1602 +}
1603 +
1604 +
1605 +static void rc32434_cleanup_module(void)
1606 +{
1607 +       int i;
1608 +
1609 +       for (i = 0; rc32434_iflist[i].iobase; i++) {
1610 +               struct rc32434_if_t * bif = &rc32434_iflist[i];
1611 +               if (bif->dev != NULL) {
1612 +                       struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1613 +                       if (lp != NULL) {
1614 +                               if (lp->eth_regs)
1615 +                                       iounmap((void*)lp->eth_regs);
1616 +                               if (lp->rx_dma_regs)
1617 +                                       iounmap((void*)lp->rx_dma_regs);
1618 +                               if (lp->tx_dma_regs)
1619 +                                       iounmap((void*)lp->tx_dma_regs);
1620 +                               if (lp->td_ring)
1621 +                                       kfree((void*)KSEG0ADDR(lp->td_ring));
1622 +
1623 +#ifdef RC32434_PROC_DEBUG
1624 +                               if (lp->ps) {
1625 +                                       remove_proc_entry(bif->name, proc_net);
1626 +                               }
1627 +#endif
1628 +                               kfree(lp);
1629 +                       }
1630 +
1631 +                       unregister_netdev(bif->dev);
1632 +                       free_netdev(bif->dev);
1633 +                       kfree(bif->dev);
1634 +               }
1635 +       }
1636 +}
1637 +
1638 +
1639 +
1640 +static int rc32434_open(struct net_device *dev)
1641 +{
1642 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1643 +
1644 +       /* Initialize */
1645 +       if (rc32434_init(dev)) {
1646 +               ERR("Error: cannot open the Ethernet device\n");
1647 +               return -EAGAIN;
1648 +       }
1649 +
1650 +       /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1651 +       if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1652 +                 SA_SHIRQ | SA_INTERRUPT,
1653 +                       "rc32434 ethernet Rx", dev)) {
1654 +               ERR(": unable to get Rx DMA IRQ %d\n",
1655 +                   lp->rx_irq);
1656 +               return -EAGAIN;
1657 +       }
1658 +       if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1659 +                 SA_SHIRQ | SA_INTERRUPT,
1660 +                       "rc32434 ethernet Tx", dev)) {
1661 +               ERR(": unable to get Tx DMA IRQ %d\n",
1662 +                   lp->tx_irq);
1663 +               free_irq(lp->rx_irq, dev);
1664 +               return -EAGAIN;
1665 +       }
1666 +
1667 +#ifdef RC32434_REVISION
1668 +       /* Install handler for overrun error. */
1669 +       if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1670 +                       SA_SHIRQ | SA_INTERRUPT,
1671 +                       "Ethernet Overflow", dev)) {
1672 +               ERR(": unable to get OVR IRQ %d\n",
1673 +                   lp->ovr_irq);
1674 +               free_irq(lp->rx_irq, dev);
1675 +               free_irq(lp->tx_irq, dev);
1676 +               return -EAGAIN;
1677 +       }
1678 +#endif
1679 +
1680 +       /* Install handler for underflow error. */
1681 +       if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1682 +                       SA_SHIRQ | SA_INTERRUPT,
1683 +                       "Ethernet Underflow", dev)) {
1684 +               ERR(": unable to get UND IRQ %d\n",
1685 +                   lp->und_irq);
1686 +               free_irq(lp->rx_irq, dev);
1687 +               free_irq(lp->tx_irq, dev);
1688 +#ifdef RC32434_REVISION
1689 +               free_irq(lp->ovr_irq, dev);
1690 +#endif
1691 +               return -EAGAIN;
1692 +       }
1693 +
1694 +
1695 +       return 0;
1696 +}
1697 +
1698 +
1699 +
1700 +
1701 +static int rc32434_close(struct net_device *dev)
1702 +{
1703 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1704 +       u32 tmp;
1705 +
1706 +       /* Disable interrupts */
1707 +       disable_irq(lp->rx_irq);
1708 +       disable_irq(lp->tx_irq);
1709 +#ifdef RC32434_REVISION
1710 +       disable_irq(lp->ovr_irq);
1711 +#endif
1712 +       disable_irq(lp->und_irq);
1713 +
1714 +       tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1715 +       tmp = tmp | DMASM_f_m | DMASM_e_m;
1716 +       rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1717 +
1718 +       tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1719 +       tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1720 +       rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1721 +
1722 +       free_irq(lp->rx_irq, dev);
1723 +       free_irq(lp->tx_irq, dev);
1724 +#ifdef RC32434_REVISION
1725 +       free_irq(lp->ovr_irq, dev);
1726 +#endif
1727 +       free_irq(lp->und_irq, dev);
1728 +       return 0;
1729 +}
1730 +
1731 +
1732 +/* transmit packet */
1733 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1734 +{
1735 +       struct rc32434_local            *lp = (struct rc32434_local *)dev->priv;
1736 +       unsigned long                   flags;
1737 +       u32                                     length;
1738 +       DMAD_t                          td;
1739 +
1740 +
1741 +       spin_lock_irqsave(&lp->lock, flags);
1742 +
1743 +       td = &lp->td_ring[lp->tx_chain_tail];
1744 +
1745 +       /* stop queue when full, drop pkts if queue already full */
1746 +       if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1747 +               lp->tx_full = 1;
1748 +
1749 +               if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1750 +                       netif_stop_queue(dev);
1751 +               }
1752 +               else {
1753 +                       lp->stats.tx_dropped++;
1754 +                       dev_kfree_skb_any(skb);
1755 +                       spin_unlock_irqrestore(&lp->lock, flags);
1756 +                       return 1;
1757 +               }
1758 +       }
1759 +
1760 +       lp->tx_count ++;
1761 +
1762 +       lp->tx_skb[lp->tx_chain_tail] = skb;
1763 +
1764 +       length = skb->len;
1765 +
1766 +       /* Setup the transmit descriptor. */
1767 +       td->ca = CPHYSADDR(skb->data);
1768 +
1769 +       if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1770 +               if( lp->tx_chain_status == empty ) {
1771 +                       td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /*  Update tail      */
1772 +                       lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /*   Move tail       */
1773 +                       rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR    */
1774 +                       lp->tx_chain_head = lp->tx_chain_tail;                                                  /* Move head to tail */
1775 +               }
1776 +               else {
1777 +                       td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m;                                 /* Update tail */
1778 +                       lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &=  ~(DMAD_cof_m);          /* Link to prev */
1779 +                       lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link =  CPHYSADDR(td);              /* Link to prev */
1780 +                       lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
1781 +                       rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1782 +                       lp->tx_chain_head = lp->tx_chain_tail;                                                  /* Move head to tail */
1783 +                       lp->tx_chain_status = empty;
1784 +               }
1785 +       }
1786 +       else {
1787 +               if( lp->tx_chain_status == empty ) {
1788 +                       td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /* Update tail */
1789 +                       lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
1790 +                       lp->tx_chain_status = filled;
1791 +               }
1792 +               else {
1793 +                       td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /* Update tail */
1794 +                       lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &=  ~(DMAD_cof_m);          /* Link to prev */
1795 +                       lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link =  CPHYSADDR(td);              /* Link to prev */
1796 +                       lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
1797 +               }
1798 +       }
1799 +
1800 +       dev->trans_start = jiffies;
1801 +
1802 +       spin_unlock_irqrestore(&lp->lock, flags);
1803 +
1804 +       return 0;
1805 +}
1806 +
1807 +
1808 +/* Ethernet MII-PHY Handler */
1809 +static void rc32434_mii_handler(unsigned long data)
1810 +{
1811 +       struct net_device *dev = (struct net_device *)data;
1812 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1813 +       unsigned long   flags;
1814 +       unsigned long duplex_status;
1815 +       int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1816 +
1817 +       spin_lock_irqsave(&lp->lock, flags);
1818 +
1819 +       /* Two ports are using the same MII, the difference is the PHY address */
1820 +       rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1821 +       rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1822 +       rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1823 +       rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1824 +       while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1825 +
1826 +       ERR("irq:%x             port_addr:%x    RDD:%x\n",
1827 +           lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1828 +       duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1829 +       if(duplex_status != lp->duplex_mode) {
1830 +               ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1831 +               lp->duplex_mode = duplex_status;
1832 +               rc32434_restart(dev);
1833 +       }
1834 +
1835 +       lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1836 +       add_timer(&lp->mii_phy_timer);
1837 +
1838 +       spin_unlock_irqrestore(&lp->lock, flags);
1839 +
1840 +}
1841 +
1842 +#ifdef RC32434_REVISION
1843 +/* Ethernet Rx Overflow interrupt */
1844 +static irqreturn_t
1845 +rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1846 +{
1847 +       struct net_device *dev = (struct net_device *)dev_id;
1848 +       struct rc32434_local *lp;
1849 +       unsigned int ovr;
1850 +       irqreturn_t retval = IRQ_NONE;
1851 +
1852 +       ASSERT(dev != NULL);
1853 +
1854 +       lp = (struct rc32434_local *)dev->priv;
1855 +       spin_lock(&lp->lock);
1856 +       ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1857 +
1858 +       if(ovr & ETHINTFC_ovr_m) {
1859 +               netif_stop_queue(dev);
1860 +
1861 +               /* clear OVR bit */
1862 +               rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1863 +
1864 +               /* Restart interface */
1865 +               rc32434_restart(dev);
1866 +               retval = IRQ_HANDLED;
1867 +       }
1868 +       spin_unlock(&lp->lock);
1869 +
1870 +       return retval;
1871 +}
1872 +
1873 +#endif
1874 +
1875 +
1876 +/* Ethernet Tx Underflow interrupt */
1877 +static irqreturn_t
1878 +rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1879 +{
1880 +       struct net_device *dev = (struct net_device *)dev_id;
1881 +       struct rc32434_local *lp;
1882 +       unsigned int und;
1883 +       irqreturn_t retval = IRQ_NONE;
1884 +
1885 +       ASSERT(dev != NULL);
1886 +
1887 +       lp = (struct rc32434_local *)dev->priv;
1888 +
1889 +       spin_lock(&lp->lock);
1890 +
1891 +       und = rc32434_readl(&lp->eth_regs->ethintfc);
1892 +
1893 +       if(und & ETHINTFC_und_m) {
1894 +               netif_stop_queue(dev);
1895 +
1896 +               rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1897 +
1898 +               /* Restart interface */
1899 +               rc32434_restart(dev);
1900 +               retval = IRQ_HANDLED;
1901 +       }
1902 +
1903 +       spin_unlock(&lp->lock);
1904 +
1905 +       return retval;
1906 +}
1907 +
1908 +
1909 +/* Ethernet Rx DMA interrupt */
1910 +static irqreturn_t
1911 +rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1912 +{
1913 +       struct net_device *dev = (struct net_device *)dev_id;
1914 +       struct rc32434_local* lp;
1915 +       volatile u32 dmas,dmasm;
1916 +       irqreturn_t retval;
1917 +
1918 +       ASSERT(dev != NULL);
1919 +
1920 +       lp = (struct rc32434_local *)dev->priv;
1921 +
1922 +       spin_lock(&lp->lock);
1923 +       dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1924 +       if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1925 +               /* Mask D H E bit in Rx DMA */
1926 +               dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1927 +               rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1928 +#ifdef CONFIG_IDT_USE_NAPI
1929 +               if(netif_rx_schedule_prep(dev))
1930 +                        __netif_rx_schedule(dev);
1931 +#else
1932 +               tasklet_hi_schedule(lp->rx_tasklet);
1933 +#endif
1934 +
1935 +               if (dmas & DMAS_e_m)
1936 +                       ERR(": DMA error\n");
1937 +
1938 +               retval = IRQ_HANDLED;
1939 +       }
1940 +       else
1941 +               retval = IRQ_NONE;
1942 +
1943 +       spin_unlock(&lp->lock);
1944 +       return retval;
1945 +}
1946 +
1947 +#ifdef CONFIG_IDT_USE_NAPI
1948 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1949 +#else
1950 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1951 +#endif
1952 +{
1953 +       struct net_device *dev = (struct net_device *)rx_data_dev;
1954 +       struct rc32434_local* lp = netdev_priv(dev);
1955 +       volatile DMAD_t  rd = &lp->rd_ring[lp->rx_next_done];
1956 +       struct sk_buff *skb, *skb_new;
1957 +       u8* pkt_buf;
1958 +       u32 devcs, count, pkt_len, pktuncrc_len;
1959 +       volatile u32 dmas;
1960 +#ifdef CONFIG_IDT_USE_NAPI
1961 +       u32 received = 0;
1962 +       int rx_work_limit = min(*budget,dev->quota);
1963 +#else
1964 +       unsigned long   flags;
1965 +       spin_lock_irqsave(&lp->lock, flags);
1966 +#endif
1967 +
1968 +       while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1969 +#ifdef CONFIG_IDT_USE_NAPI
1970 +               if(--rx_work_limit <0)
1971 +                {
1972 +                        break;
1973 +                }
1974 +#endif
1975 +               /* init the var. used for the later operations within the while loop */
1976 +               skb_new = NULL;
1977 +               devcs = rd->devcs;
1978 +               pkt_len = RCVPKT_LENGTH(devcs);
1979 +               skb = lp->rx_skb[lp->rx_next_done];
1980 +
1981 +               if (count < 64) {
1982 +                       lp->stats.rx_errors++;
1983 +                       lp->stats.rx_dropped++;
1984 +               }
1985 +               else if ((devcs & ( ETHRX_ld_m)) !=     ETHRX_ld_m) {
1986 +                       /* check that this is a whole packet */
1987 +                       /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
1988 +                       lp->stats.rx_errors++;
1989 +                       lp->stats.rx_dropped++;
1990 +               }
1991 +               else if ( (devcs & ETHRX_rok_m)  ) {
1992 +
1993 +                       {
1994 +                               /* must be the (first and) last descriptor then */
1995 +                               pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
1996 +
1997 +                               pktuncrc_len = pkt_len - 4;
1998 +                               /* invalidate the cache */
1999 +                               dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
2000 +
2001 +                               /* Malloc up new buffer. */
2002 +                               skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
2003 +
2004 +                               if (skb_new != NULL){
2005 +                                       /* Make room */
2006 +                                       skb_put(skb, pktuncrc_len);
2007 +
2008 +                                       skb->protocol = eth_type_trans(skb, dev);
2009 +
2010 +                                       /* pass the packet to upper layers */
2011 +#ifdef CONFIG_IDT_USE_NAPI
2012 +                                       netif_receive_skb(skb);
2013 +#else
2014 +                                       netif_rx(skb);
2015 +#endif
2016 +
2017 +                                       dev->last_rx = jiffies;
2018 +                                       lp->stats.rx_packets++;
2019 +                                       lp->stats.rx_bytes += pktuncrc_len;
2020 +
2021 +                                       if (IS_RCV_MP(devcs))
2022 +                                               lp->stats.multicast++;
2023 +
2024 +                                       /* 16 bit align */
2025 +                                       skb_reserve(skb_new, 2);
2026 +
2027 +                                       skb_new->dev = dev;
2028 +                                       lp->rx_skb[lp->rx_next_done] = skb_new;
2029 +                               }
2030 +                               else {
2031 +                                       ERR("no memory, dropping rx packet.\n");
2032 +                                       lp->stats.rx_errors++;
2033 +                                       lp->stats.rx_dropped++;
2034 +                               }
2035 +                       }
2036 +
2037 +               }
2038 +               else {
2039 +                       /* This should only happen if we enable accepting broken packets */
2040 +                       lp->stats.rx_errors++;
2041 +                       lp->stats.rx_dropped++;
2042 +
2043 +                       /* add statistics counters */
2044 +                       if (IS_RCV_CRC_ERR(devcs)) {
2045 +                               DBG(2, "RX CRC error\n");
2046 +                               lp->stats.rx_crc_errors++;
2047 +                       }
2048 +                       else if (IS_RCV_LOR_ERR(devcs)) {
2049 +                               DBG(2, "RX LOR error\n");
2050 +                               lp->stats.rx_length_errors++;
2051 +                       }
2052 +                       else if (IS_RCV_LE_ERR(devcs)) {
2053 +                               DBG(2, "RX LE error\n");
2054 +                               lp->stats.rx_length_errors++;
2055 +                       }
2056 +                       else if (IS_RCV_OVR_ERR(devcs)) {
2057 +                               lp->stats.rx_over_errors++;
2058 +                       }
2059 +                       else if (IS_RCV_CV_ERR(devcs)) {
2060 +                               /* code violation */
2061 +                               DBG(2, "RX CV error\n");
2062 +                               lp->stats.rx_frame_errors++;
2063 +                       }
2064 +                       else if (IS_RCV_CES_ERR(devcs)) {
2065 +                               DBG(2, "RX Preamble error\n");
2066 +                       }
2067 +               }
2068 +
2069 +               rd->devcs = 0;
2070 +
2071 +               /* restore descriptor's curr_addr */
2072 +               if(skb_new)
2073 +                       rd->ca = CPHYSADDR(skb_new->data);
2074 +               else
2075 +                       rd->ca = CPHYSADDR(skb->data);
2076 +
2077 +               rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2078 +               lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &=  ~(DMAD_cod_m);
2079 +
2080 +               lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2081 +               rd = &lp->rd_ring[lp->rx_next_done];
2082 +               rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2083 +       }
2084 +#ifdef CONFIG_IDT_USE_NAPI
2085 +        dev->quota -= received;
2086 +        *budget =- received;
2087 +        if(rx_work_limit < 0)
2088 +                goto not_done;
2089 +#endif
2090 +
2091 +       dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2092 +
2093 +       if(dmas & DMAS_h_m) {
2094 +               rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2095 +#ifdef RC32434_PROC_DEBUG
2096 +               lp->dma_halt_cnt++;
2097 +#endif
2098 +               rd->devcs = 0;
2099 +               skb = lp->rx_skb[lp->rx_next_done];
2100 +               rd->ca = CPHYSADDR(skb->data);
2101 +               rc32434_chain_rx(lp,rd);
2102 +       }
2103 +
2104 +#ifdef CONFIG_IDT_USE_NAPI
2105 +       netif_rx_complete(dev);
2106 +#endif
2107 +       /* Enable D H E bit in Rx DMA */
2108 +       rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2109 +#ifdef CONFIG_IDT_USE_NAPI
2110 +       return 0;
2111 + not_done:
2112 +       return 1;
2113 +#else
2114 +       spin_unlock_irqrestore(&lp->lock, flags);
2115 +       return;
2116 +#endif
2117 +
2118 +
2119 +}
2120 +
2121 +
2122 +
2123 +/* Ethernet Tx DMA interrupt */
2124 +static irqreturn_t
2125 +rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2126 +{
2127 +       struct net_device *dev = (struct net_device *)dev_id;
2128 +       struct rc32434_local *lp;
2129 +       volatile u32 dmas,dmasm;
2130 +       irqreturn_t retval;
2131 +
2132 +       ASSERT(dev != NULL);
2133 +
2134 +       lp = (struct rc32434_local *)dev->priv;
2135 +
2136 +       spin_lock(&lp->lock);
2137 +
2138 +       dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2139 +
2140 +       if (dmas & (DMAS_f_m | DMAS_e_m)) {
2141 +               dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2142 +               /* Mask F E bit in Tx DMA */
2143 +               rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2144 +
2145 +               tasklet_hi_schedule(lp->tx_tasklet);
2146 +
2147 +               if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2148 +                       rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2149 +                       lp->tx_chain_status = empty;
2150 +                       lp->tx_chain_head = lp->tx_chain_tail;
2151 +                       dev->trans_start = jiffies;
2152 +               }
2153 +
2154 +               if (dmas & DMAS_e_m)
2155 +                       ERR(": DMA error\n");
2156 +
2157 +               retval = IRQ_HANDLED;
2158 +       }
2159 +       else
2160 +               retval = IRQ_NONE;
2161 +
2162 +       spin_unlock(&lp->lock);
2163 +
2164 +       return retval;
2165 +}
2166 +
2167 +
2168 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2169 +{
2170 +       struct net_device *dev = (struct net_device *)tx_data_dev;
2171 +       struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2172 +       volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2173 +       u32 devcs;
2174 +       unsigned long   flags;
2175 +       volatile u32 dmas;
2176 +
2177 +       spin_lock_irqsave(&lp->lock, flags);
2178 +
2179 +       /* process all desc that are done */
2180 +       while(IS_DMA_FINISHED(td->control)) {
2181 +               if(lp->tx_full == 1) {
2182 +                       netif_wake_queue(dev);
2183 +                       lp->tx_full = 0;
2184 +               }
2185 +
2186 +               devcs = lp->td_ring[lp->tx_next_done].devcs;
2187 +               if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2188 +                       lp->stats.tx_errors++;
2189 +                       lp->stats.tx_dropped++;
2190 +
2191 +                       /* should never happen */
2192 +                       DBG(1, __FUNCTION__ ": split tx ignored\n");
2193 +               }
2194 +               else if (IS_TX_TOK(devcs)) {
2195 +                       lp->stats.tx_packets++;
2196 +               }
2197 +               else {
2198 +                       lp->stats.tx_errors++;
2199 +                       lp->stats.tx_dropped++;
2200 +
2201 +                       /* underflow */
2202 +                       if (IS_TX_UND_ERR(devcs))
2203 +                               lp->stats.tx_fifo_errors++;
2204 +
2205 +                       /* oversized frame */
2206 +                       if (IS_TX_OF_ERR(devcs))
2207 +                               lp->stats.tx_aborted_errors++;
2208 +
2209 +                       /* excessive deferrals */
2210 +                       if (IS_TX_ED_ERR(devcs))
2211 +                               lp->stats.tx_carrier_errors++;
2212 +
2213 +                       /* collisions: medium busy */
2214 +                       if (IS_TX_EC_ERR(devcs))
2215 +                               lp->stats.collisions++;
2216 +
2217 +                       /* late collision */
2218 +                       if (IS_TX_LC_ERR(devcs))
2219 +                               lp->stats.tx_window_errors++;
2220 +
2221 +               }
2222 +
2223 +               /* We must always free the original skb */
2224 +               if (lp->tx_skb[lp->tx_next_done] != NULL) {
2225 +                       dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2226 +                       lp->tx_skb[lp->tx_next_done] = NULL;
2227 +               }
2228 +
2229 +               lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2230 +               lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2231 +               lp->td_ring[lp->tx_next_done].link = 0;
2232 +               lp->td_ring[lp->tx_next_done].ca = 0;
2233 +               lp->tx_count --;
2234 +
2235 +               /* go on to next transmission */
2236 +               lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2237 +               td = &lp->td_ring[lp->tx_next_done];
2238 +
2239 +       }
2240 +
2241 +       dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2242 +       rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2243 +
2244 +       /* Enable F E bit in Tx DMA */
2245 +       rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2246 +       spin_unlock_irqrestore(&lp->lock, flags);
2247 +
2248 +}
2249 +
2250 +
2251 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2252 +{
2253 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2254 +       return &lp->stats;
2255 +}
2256 +
2257 +
2258 +/*
2259 + * Set or clear the multicast filter for this adaptor.
2260 + */
2261 +static void rc32434_multicast_list(struct net_device *dev)
2262 +{
2263 +       /* listen to broadcasts always and to treat     */
2264 +       /*       IFF bits independantly */
2265 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2266 +       unsigned long flags;
2267 +       u32 recognise = ETHARC_ab_m;            /* always accept broadcasts */
2268 +
2269 +       if (dev->flags & IFF_PROMISC)                   /* set promiscuous mode */
2270 +               recognise |= ETHARC_pro_m;
2271 +
2272 +       if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2273 +               recognise |= ETHARC_am_m;               /* all multicast & bcast */
2274 +       else if (dev->mc_count > 0) {
2275 +               DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2276 +               recognise |= ETHARC_am_m;               /* for the time being */
2277 +       }
2278 +
2279 +       spin_lock_irqsave(&lp->lock, flags);
2280 +       rc32434_writel(recognise, &lp->eth_regs->etharc);
2281 +       spin_unlock_irqrestore(&lp->lock, flags);
2282 +}
2283 +
2284 +
2285 +static void rc32434_tx_timeout(struct net_device *dev)
2286 +{
2287 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2288 +       unsigned long flags;
2289 +
2290 +       spin_lock_irqsave(&lp->lock, flags);
2291 +       rc32434_restart(dev);
2292 +       spin_unlock_irqrestore(&lp->lock, flags);
2293 +
2294 +}
2295 +
2296 +
2297 +/*
2298 + * Initialize the RC32434 ethernet controller.
2299 + */
2300 +static int rc32434_init(struct net_device *dev)
2301 +{
2302 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2303 +       int i, j;
2304 +
2305 +       /* Disable DMA */
2306 +       rc32434_abort_tx(dev);
2307 +       rc32434_abort_rx(dev);
2308 +
2309 +       /* reset ethernet logic */
2310 +       rc32434_writel(0, &lp->eth_regs->ethintfc);
2311 +       while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2312 +               dev->trans_start = jiffies;
2313 +
2314 +       /* Enable Ethernet Interface */
2315 +       rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2316 +
2317 +#ifndef CONFIG_IDT_USE_NAPI
2318 +       tasklet_disable(lp->rx_tasklet);
2319 +#endif
2320 +       tasklet_disable(lp->tx_tasklet);
2321 +
2322 +       /* Initialize the transmit Descriptors */
2323 +       for (i = 0; i < RC32434_NUM_TDS; i++) {
2324 +               lp->td_ring[i].control = DMAD_iof_m;
2325 +               lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2326 +               lp->td_ring[i].ca = 0;
2327 +               lp->td_ring[i].link = 0;
2328 +               if (lp->tx_skb[i] != NULL) {
2329 +                       dev_kfree_skb_any(lp->tx_skb[i]);
2330 +                       lp->tx_skb[i] = NULL;
2331 +               }
2332 +       }
2333 +       lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =      lp->tx_full = lp->tx_count = 0;
2334 +       lp->    tx_chain_status = empty;
2335 +
2336 +       /*
2337 +        * Initialize the receive descriptors so that they
2338 +        * become a circular linked list, ie. let the last
2339 +        * descriptor point to the first again.
2340 +        */
2341 +       for (i=0; i<RC32434_NUM_RDS; i++) {
2342 +               struct sk_buff *skb = lp->rx_skb[i];
2343 +
2344 +               if (lp->rx_skb[i] == NULL) {
2345 +                       skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2346 +                       if (skb == NULL) {
2347 +                               ERR("No memory in the system\n");
2348 +                               for (j = 0; j < RC32434_NUM_RDS; j ++)
2349 +                                       if (lp->rx_skb[j] != NULL)
2350 +                                               dev_kfree_skb_any(lp->rx_skb[j]);
2351 +
2352 +                               return 1;
2353 +                       }
2354 +                       else {
2355 +                               skb->dev = dev;
2356 +                               skb_reserve(skb, 2);
2357 +                               lp->rx_skb[i] = skb;
2358 +                               lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2359 +
2360 +                       }
2361 +               }
2362 +               lp->rd_ring[i].control =        DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2363 +               lp->rd_ring[i].devcs = 0;
2364 +               lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2365 +               lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2366 +
2367 +       }
2368 +       /* loop back */
2369 +       lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2370 +       lp->rx_next_done   = 0;
2371 +
2372 +       lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2373 +       lp->rx_chain_head = 0;
2374 +       lp->rx_chain_tail = 0;
2375 +       lp->rx_chain_status = empty;
2376 +
2377 +       rc32434_writel(0, &lp->rx_dma_regs->dmas);
2378 +       /* Start Rx DMA */
2379 +       rc32434_start_rx(lp, &lp->rd_ring[0]);
2380 +
2381 +       /* Enable F E bit in Tx DMA */
2382 +       rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2383 +       /* Enable D H E bit in Rx DMA */
2384 +       rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2385 +
2386 +       /* Accept only packets destined for this Ethernet device address */
2387 +       rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2388 +
2389 +       /* Set all Ether station address registers to their initial values */
2390 +       rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2391 +       rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2392 +
2393 +       rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2394 +       rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2395 +
2396 +       rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2397 +       rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2398 +
2399 +       rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2400 +       rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2401 +
2402 +
2403 +       /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2404 +       rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2405 +       //ETHMAC2_flc_m         ETHMAC2_fd_m    lp->duplex_mode
2406 +
2407 +       /* Back to back inter-packet-gap */
2408 +       rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2409 +       /* Non - Back to back inter-packet-gap */
2410 +       rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2411 +
2412 +       /* Management Clock Prescaler Divisor */
2413 +       /* Clock independent setting */
2414 +       rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2415 +                      &lp->eth_regs->ethmcp);
2416 +
2417 +       /* don't transmit until fifo contains 48b */
2418 +       rc32434_writel(48, &lp->eth_regs->ethfifott);
2419 +
2420 +       rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2421 +
2422 +#ifndef CONFIG_IDT_USE_NAPI
2423 +       tasklet_enable(lp->rx_tasklet);
2424 +#endif
2425 +       tasklet_enable(lp->tx_tasklet);
2426 +
2427 +       netif_start_queue(dev);
2428 +
2429 +
2430 +       return 0;
2431 +
2432 +}
2433 +
2434 +
2435 +#ifndef MODULE
2436 +
2437 +static int __init rc32434_setup(char *options)
2438 +{
2439 +       /* no options yet */
2440 +       return 1;
2441 +}
2442 +
2443 +static int __init rc32434_setup_ethaddr0(char *options)
2444 +{
2445 +       memcpy(mac0, options, 17);
2446 +       mac0[17]= '\0';
2447 +       return 1;
2448 +}
2449 +
2450 +__setup("rc32434eth=", rc32434_setup);
2451 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2452 +
2453 +
2454 +#endif /* MODULE */
2455 +
2456 +module_init(rc32434_init_module);
2457 +module_exit(rc32434_cleanup_module);
2458 +
2459 +
2460 +
2461 +
2462 +
2463 +
2464 +
2465 +
2466 +
2467 +
2468 +
2469 +
2470 +
2471 +
2472 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.h linux-2.6.17-owrt/drivers/net/rc32434_eth.h
2473 --- linux-2.6.17/drivers/net/rc32434_eth.h      1970-01-01 01:00:00.000000000 +0100
2474 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.h 2006-06-18 12:44:28.000000000 +0200
2475 @@ -0,0 +1,187 @@
2476 +/**************************************************************************
2477 + *
2478 + *  BRIEF MODULE DESCRIPTION
2479 + *     Definitions for IDT RC32434 on-chip ethernet controller.
2480 + *
2481 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
2482 + *
2483 + *  This program is free software; you can redistribute  it and/or modify it
2484 + *  under  the terms of  the GNU General  Public License as published by the
2485 + *  Free Software Foundation;  either version 2 of the  License, or (at your
2486 + *  option) any later version.
2487 + *
2488 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
2489 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
2490 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
2491 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
2492 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2493 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
2494 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2495 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
2496 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2497 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2498 + *
2499 + *  You should have received a copy of the  GNU General Public License along
2500 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
2501 + *  675 Mass Ave, Cambridge, MA 02139, USA.
2502 + *
2503 + *
2504 + **************************************************************************
2505 + * May 2004 rkt, neb
2506 + *
2507 + * Initial Release
2508 + *
2509 + * Aug 2004
2510 + *
2511 + * Added NAPI
2512 + *
2513 + **************************************************************************
2514 + */
2515 +
2516 +
2517 +#include  <asm/idt-boards/rc32434/rc32434.h>
2518 +#include  <asm/idt-boards/rc32434/rc32434_dma_v.h>
2519 +#include  <asm/idt-boards/rc32434/rc32434_eth_v.h>
2520 +
2521 +#define RC32434_DEBUG  2
2522 +//#define RC32434_PROC_DEBUG
2523 +#undef RC32434_DEBUG
2524 +
2525 +#ifdef RC32434_DEBUG
2526 +
2527 +/* use 0 for production, 1 for verification, >2 for debug */
2528 +static int rc32434_debug = RC32434_DEBUG;
2529 +#define ASSERT(expr) \
2530 +       if(!(expr)) {   \
2531 +               printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2532 +               #expr,__FILE__,__FUNCTION__,__LINE__);          }
2533 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2534 +#else
2535 +#define ASSERT(expr) do {} while (0)
2536 +#define DBG(lvl, format, arg...) do {} while (0)
2537 +#endif
2538 +
2539 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2540 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2541 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2542 +
2543 +#define ETH0_DMA_RX_IRQ        GROUP1_IRQ_BASE + 0
2544 +#define ETH0_DMA_TX_IRQ        GROUP1_IRQ_BASE + 1
2545 +#define ETH0_RX_OVR_IRQ        GROUP3_IRQ_BASE + 9
2546 +#define ETH0_TX_UND_IRQ        GROUP3_IRQ_BASE + 10
2547 +
2548 +#define ETH0_RX_DMA_ADDR  (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2549 +#define ETH0_TX_DMA_ADDR  (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2550 +
2551 +/* the following must be powers of two */
2552 +#ifdef CONFIG_IDT_USE_NAPI
2553 +#define RC32434_NUM_RDS    64                  /* number of receive descriptors */
2554 +#define RC32434_NUM_TDS    64                  /* number of transmit descriptors */
2555 +#else
2556 +#define RC32434_NUM_RDS    128                 /* number of receive descriptors */
2557 +#define RC32434_NUM_TDS    128                 /* number of transmit descriptors */
2558 +#endif
2559 +
2560 +#define RC32434_RBSIZE     1536                /* size of one resource buffer = Ether MTU */
2561 +#define RC32434_RDS_MASK   (RC32434_NUM_RDS-1)
2562 +#define RC32434_TDS_MASK   (RC32434_NUM_TDS-1)
2563 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2564 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2565 +
2566 +#define RC32434_TX_TIMEOUT HZ * 100
2567 +
2568 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2569 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2570 +
2571 +enum status    { filled,       empty};
2572 +#define IS_DMA_FINISHED(X)   (((X) & (DMAD_f_m)) != 0)
2573 +#define IS_DMA_DONE(X)   (((X) & (DMAD_d_m)) != 0)
2574 +
2575 +
2576 +/* Information that need to be kept for each board. */
2577 +struct rc32434_local {
2578 +       ETH_t  eth_regs;
2579 +       DMA_Chan_t  rx_dma_regs;
2580 +       DMA_Chan_t  tx_dma_regs;
2581 +       volatile DMAD_t   td_ring;                      /* transmit descriptor ring */
2582 +       volatile DMAD_t   rd_ring;                      /* receive descriptor ring  */
2583 +
2584 +       struct sk_buff* tx_skb[RC32434_NUM_TDS];        /* skbuffs for pkt to trans */
2585 +       struct sk_buff* rx_skb[RC32434_NUM_RDS];        /* skbuffs for pkt to trans */
2586 +
2587 +#ifndef CONFIG_IDT_USE_NAPI
2588 +       struct tasklet_struct * rx_tasklet;
2589 +#endif
2590 +       struct tasklet_struct * tx_tasklet;
2591 +
2592 +       int     rx_next_done;
2593 +       int     rx_chain_head;
2594 +       int     rx_chain_tail;
2595 +       enum status     rx_chain_status;
2596 +
2597 +       int     tx_next_done;
2598 +       int     tx_chain_head;
2599 +       int     tx_chain_tail;
2600 +       enum status     tx_chain_status;
2601 +       int tx_count;
2602 +       int     tx_full;
2603 +
2604 +       struct timer_list    mii_phy_timer;
2605 +       unsigned long duplex_mode;
2606 +
2607 +       int     rx_irq;
2608 +       int    tx_irq;
2609 +       int    ovr_irq;
2610 +       int    und_irq;
2611 +
2612 +       struct net_device_stats stats;
2613 +       spinlock_t lock;
2614 +
2615 +       /* debug /proc entry */
2616 +       struct proc_dir_entry *ps;
2617 +       int dma_halt_cnt;  int dma_run_cnt;
2618 +};
2619 +
2620 +extern unsigned int idt_cpu_freq;
2621 +
2622 +/* Index to functions, as function prototypes. */
2623 +static int rc32434_open(struct net_device *dev);
2624 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2625 +static void rc32434_mii_handler(unsigned long data);
2626 +static irqreturn_t  rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2627 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2628 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2629 +#ifdef RC32434_REVISION
2630 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2631 +#endif
2632 +static int  rc32434_close(struct net_device *dev);
2633 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2634 +static void rc32434_multicast_list(struct net_device *dev);
2635 +static int  rc32434_init(struct net_device *dev);
2636 +static void rc32434_tx_timeout(struct net_device *dev);
2637 +
2638 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2639 +#ifdef CONFIG_IDT_USE_NAPI
2640 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2641 +#else
2642 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2643 +#endif
2644 +static void rc32434_cleanup_module(void);
2645 +static int rc32434_probe(int port_num);
2646 +int rc32434_init_module(void);
2647 +
2648 +
2649 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2650 +{
2651 +       if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2652 +               rc32434_writel(0x10, &ch->dmac);
2653 +
2654 +               while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2655 +                       dev->trans_start = jiffies;
2656 +
2657 +               rc32434_writel(0, &ch->dmas);
2658 +       }
2659 +
2660 +       rc32434_writel(0, &ch->dmadptr);
2661 +       rc32434_writel(0, &ch->dmandptr);
2662 +}
2663 diff -Nur linux-2.6.17/include/asm-mips/bootinfo.h linux-2.6.17-owrt/include/asm-mips/bootinfo.h
2664 --- linux-2.6.17/include/asm-mips/bootinfo.h    2006-06-18 03:49:35.000000000 +0200
2665 +++ linux-2.6.17-owrt/include/asm-mips/bootinfo.h       2006-06-18 12:44:28.000000000 +0200
2666 @@ -218,6 +218,17 @@
2667  #define MACH_GROUP_TITAN       22      /* PMC-Sierra Titan             */
2668  #define  MACH_TITAN_YOSEMITE   1       /* PMC-Sierra Yosemite          */
2669
2670 +
2671 +/*
2672 + * Valid machtype for group ARUBA
2673 + */
2674 +#define MACH_GROUP_ARUBA       23
2675 +#define  MACH_ARUBA_UNKNOWN    0
2676 +#define  MACH_ARUBA_AP60       1
2677 +#define  MACH_ARUBA_AP65       2
2678 +#define  MACH_ARUBA_AP70       3
2679 +#define  MACH_ARUBA_AP40       4
2680 +
2681  #define CL_SIZE                        COMMAND_LINE_SIZE
2682
2683  const char *get_system_type(void);
2684 diff -Nur linux-2.6.17/include/asm-mips/cpu.h linux-2.6.17-owrt/include/asm-mips/cpu.h
2685 --- linux-2.6.17/include/asm-mips/cpu.h 2006-06-18 03:49:35.000000000 +0200
2686 +++ linux-2.6.17-owrt/include/asm-mips/cpu.h    2006-06-18 12:45:56.000000000 +0200
2687 @@ -54,6 +54,9 @@
2688  #define PRID_IMP_R14000                0x0f00
2689  #define PRID_IMP_R8000         0x1000
2690  #define PRID_IMP_PR4450                0x1200
2691 +#define PRID_IMP_RC32334       0x1800
2692 +#define PRID_IMP_RC32355       0x1900
2693 +#define PRID_IMP_RC32365       0x1900
2694  #define PRID_IMP_R4600         0x2000
2695  #define PRID_IMP_R4700         0x2100
2696  #define PRID_IMP_TX39          0x2200
2697 @@ -200,7 +203,8 @@
2698  #define CPU_SB1A               62
2699  #define CPU_74K                        63
2700  #define CPU_R14000             64
2701 -#define CPU_LAST               64
2702 +#define CPU_RC32300            65
2703 +#define CPU_LAST               65
2704
2705  /*
2706   * ISA Level encodings
2707 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2708 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h  1970-01-01 01:00:00.000000000 +0100
2709 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h     2006-06-18 12:44:28.000000000 +0200
2710 @@ -0,0 +1,142 @@
2711 +/**************************************************************************
2712 + *
2713 + *  BRIEF MODULE DESCRIPTION
2714 + *   RC32300 helper routines
2715 + *
2716 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
2717 + *
2718 + *  This program is free software; you can redistribute  it and/or modify it
2719 + *  under  the terms of  the GNU General  Public License as published by the
2720 + *  Free Software Foundation;  either version 2 of the  License, or (at your
2721 + *  option) any later version.
2722 + *
2723 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
2724 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
2725 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
2726 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
2727 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2728 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
2729 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2730 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
2731 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2732 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2733 + *
2734 + *  You should have received a copy of the  GNU General Public License along
2735 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
2736 + *  675 Mass Ave, Cambridge, MA 02139, USA.
2737 + *
2738 + *
2739 + **************************************************************************
2740 + * May 2004 P. Sadik.
2741 + *
2742 + * Initial Release
2743 + *
2744 + *
2745 + *
2746 + **************************************************************************
2747 + */
2748 +
2749 +#ifndef __IDT_RC32300_H__
2750 +#define __IDT_RC32300_H__
2751 +
2752 +#include <linux/delay.h>
2753 +#include <asm/io.h>
2754 +
2755 +
2756 +/* cpu pipeline flush */
2757 +static inline void rc32300_sync(void)
2758 +{
2759 +       __asm__ volatile ("sync");
2760 +}
2761 +
2762 +static inline void rc32300_sync_udelay(int us)
2763 +{
2764 +       __asm__ volatile ("sync");
2765 +       udelay(us);
2766 +}
2767 +
2768 +static inline void rc32300_sync_delay(int ms)
2769 +{
2770 +       __asm__ volatile ("sync");
2771 +       mdelay(ms);
2772 +}
2773 +
2774 +/*
2775 + * Macros to access internal RC32300 registers. No byte
2776 + * swapping should be done when accessing the internal
2777 + * registers.
2778 + */
2779 +
2780 +static inline u8 rc32300_readb(unsigned long pa)
2781 +{
2782 +       return *((volatile u8 *)KSEG1ADDR(pa));
2783 +}
2784 +static inline u16 rc32300_readw(unsigned long pa)
2785 +{
2786 +       return *((volatile u16 *)KSEG1ADDR(pa));
2787 +}
2788 +static inline u32 rc32300_readl(unsigned long pa)
2789 +{
2790 +       return *((volatile u32 *)KSEG1ADDR(pa));
2791 +}
2792 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2793 +{
2794 +       *((volatile u8 *)KSEG1ADDR(pa)) = val;
2795 +}
2796 +static inline void rc32300_writew(u16 val, unsigned long pa)
2797 +{
2798 +       *((volatile u16 *)KSEG1ADDR(pa)) = val;
2799 +}
2800 +static inline void rc32300_writel(u32 val, unsigned long pa)
2801 +{
2802 +       *((volatile u32 *)KSEG1ADDR(pa)) = val;
2803 +}
2804 +
2805 +
2806 +#define local_readb __raw_readb
2807 +#define local_readw __raw_readw
2808 +#define local_readl __raw_readl
2809 +
2810 +#define local_writeb __raw_writeb
2811 +#define local_writew __raw_writew
2812 +#define local_writel __raw_writel
2813 +
2814 +
2815 +/*
2816 + * C access to CLZ and CLO instructions
2817 + * (count leading zeroes/ones).
2818 + */
2819 +static inline int rc32300_clz(unsigned long val)
2820 +{
2821 +       int ret;
2822 +       __asm__ volatile (
2823 +               ".set\tnoreorder\n\t"
2824 +               ".set\tnoat\n\t"
2825 +               ".set\tmips32\n\t"
2826 +               "clz\t%0,%1\n\t"
2827 +               ".set\tmips0\n\t"
2828 +               ".set\tat\n\t"
2829 +               ".set\treorder"
2830 +               : "=r" (ret)
2831 +               : "r" (val));
2832 +
2833 +       return ret;
2834 +}
2835 +static inline int rc32300_clo(unsigned long val)
2836 +{
2837 +       int ret;
2838 +       __asm__ volatile (
2839 +                   ".set\tnoreorder\n\t"
2840 +                   ".set\tnoat\n\t"
2841 +                   ".set\tmips32\n\t"
2842 +                   "clo\t%0,%1\n\t"
2843 +                   ".set\tmips0\n\t"
2844 +                   ".set\tat\n\t"
2845 +                   ".set\treorder"
2846 +                   : "=r" (ret)
2847 +                   : "r" (val));
2848 +
2849 +       return ret;
2850 +}
2851 +
2852 +#endif  // __IDT_RC32300_H__
2853 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2854 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h  1970-01-01 01:00:00.000000000 +0100
2855 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h     2006-06-18 12:44:28.000000000 +0200
2856 @@ -0,0 +1,207 @@
2857 +/**************************************************************************
2858 + *
2859 + *  BRIEF MODULE DESCRIPTION
2860 + *   Definitions for IDT RC32334 CPU.
2861 + *
2862 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
2863 + *
2864 + *  This program is free software; you can redistribute  it and/or modify it
2865 + *  under  the terms of  the GNU General  Public License as published by the
2866 + *  Free Software Foundation;  either version 2 of the  License, or (at your
2867 + *  option) any later version.
2868 + *
2869 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
2870 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
2871 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
2872 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
2873 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2874 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
2875 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2876 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
2877 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2878 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2879 + *
2880 + *  You should have received a copy of the  GNU General Public License along
2881 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
2882 + *  675 Mass Ave, Cambridge, MA 02139, USA.
2883 + *
2884 + *
2885 + **************************************************************************
2886 + * May 2004 P. Sadik.
2887 + *
2888 + * Initial Release
2889 + *
2890 + *
2891 + *
2892 + **************************************************************************
2893 + */
2894 +
2895 +
2896 +#ifndef __IDT_RC32334_H__
2897 +#define __IDT_RC32334_H__
2898 +
2899 +#include <linux/delay.h>
2900 +#include <asm/io.h>
2901 +
2902 +/* Base address of internal registers */
2903 +#define RC32334_REG_BASE   0x18000000
2904 +
2905 +/* CPU and IP Bus Control */
2906 +#define CPU_PORT_WIDTH     0xffffe200 // virtual!
2907 +#define CPU_BTA            0xffffe204 // virtual!
2908 +#define CPU_BUSERR_ADDR    0xffffe208 // virtual!
2909 +#define CPU_IP_BTA         (RC32334_REG_BASE + 0x0000)
2910 +#define CPU_IP_ADDR_LATCH  (RC32334_REG_BASE + 0x0004)
2911 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2912 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2913 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2914 +#define CPU_IP_SYSID       (RC32334_REG_BASE + 0x0018)
2915 +
2916 +/* Memory Controller */
2917 +#define MEM_BASE_BANK0     (RC32334_REG_BASE + 0x0080)
2918 +#define MEM_MASK_BANK0     (RC32334_REG_BASE + 0x0084)
2919 +#define MEM_CNTL_BANK0     (RC32334_REG_BASE + 0x0200)
2920 +#define MEM_BASE_BANK1     (RC32334_REG_BASE + 0x0088)
2921 +#define MEM_MASK_BANK1     (RC32334_REG_BASE + 0x008c)
2922 +#define MEM_CNTL_BANK1     (RC32334_REG_BASE + 0x0204)
2923 +#define MEM_CNTL_BANK2     (RC32334_REG_BASE + 0x0208)
2924 +#define MEM_CNTL_BANK3     (RC32334_REG_BASE + 0x020c)
2925 +#define MEM_CNTL_BANK4     (RC32334_REG_BASE + 0x0210)
2926 +#define MEM_CNTL_BANK5     (RC32334_REG_BASE + 0x0214)
2927 +
2928 +/* PCI Controller */
2929 +#define PCI_INTR_PEND      (RC32334_REG_BASE + 0x05b0)
2930 +#define PCI_INTR_MASK      (RC32334_REG_BASE + 0x05b4)
2931 +#define PCI_INTR_CLEAR     (RC32334_REG_BASE + 0x05b8)
2932 +#define CPU2PCI_INTR_PEND  (RC32334_REG_BASE + 0x05c0)
2933 +#define CPU2PCI_INTR_MASK  (RC32334_REG_BASE + 0x05c4)
2934 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2935 +#define PCI2CPU_INTR_PEND  (RC32334_REG_BASE + 0x05d0)
2936 +#define PCI2CPU_INTR_MASK  (RC32334_REG_BASE + 0x05d4)
2937 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2938 +#define PCI_MEM1_BASE      (RC32334_REG_BASE + 0x20b0)
2939 +#define PCI_MEM2_BASE      (RC32334_REG_BASE + 0x20b8)
2940 +#define PCI_MEM3_BASE      (RC32334_REG_BASE + 0x20c0)
2941 +#define PCI_IO1_BASE       (RC32334_REG_BASE + 0x20c8)
2942 +#define PCI_ARBITRATION    (RC32334_REG_BASE + 0x20e0)
2943 +#define PCI_CPU_MEM1_BASE  (RC32334_REG_BASE + 0x20e8)
2944 +#define PCI_CPU_IO_BASE    (RC32334_REG_BASE + 0x2100)
2945 +#define PCI_CFG_CNTL      (RC32334_REG_BASE + 0x2cf8)
2946 +#define PCI_CFG_DATA      (RC32334_REG_BASE + 0x2cfc)
2947 +
2948 +/* Timers */
2949 +#define TIMER0_CNTL        (RC32334_REG_BASE + 0x0700)
2950 +#define TIMER0_COUNT       (RC32334_REG_BASE + 0x0704)
2951 +#define TIMER0_COMPARE     (RC32334_REG_BASE + 0x0708)
2952 +#define TIMER_REG_OFFSET   0x10
2953 +
2954 +/* Programmable I/O */
2955 +#define PIO_DATA0          (RC32334_REG_BASE + 0x0600)
2956 +#define PIO_DATA1          (RC32334_REG_BASE + 0x0610)
2957 +
2958 +/*
2959 + * DMA
2960 + *
2961 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2962 + *
2963 + * DMA0: 18001400
2964 + * DMA1: 18001440
2965 + * DMA2: 18001900
2966 + * DMA3: 18001940
2967 + * NB: dma number must be immediate value or variable.
2968 + *      It MUST NOT be a function since it would get called twice!
2969 + */
2970 +#define DMA_IO(n)       (((n)>1?0x500:0)+((n)&1?0x40:0))
2971 +
2972 +#define RC32300_IO_DMA(n)       (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2973 +#define RC32300_DMA_CONFREG(n)  RC32300_IO_DMA(n)
2974 +#define RC32300_DMA_BASEREG(n)  (RC32300_IO_DMA(n)+0x4)
2975 +
2976 +#define RC32300_DMA_CURRREG(n)  (RC32300_IO_DMA(n)+0x8)
2977 +#define RC32300_DMA_STATREG(n)  (RC32300_IO_DMA(n)+0x10)
2978 +#define RC32300_DMA_SRCREG(n)   (RC32300_IO_DMA(n)+0x14)
2979 +#define RC32300_DMA_DSTREG(n)   (RC32300_IO_DMA(n)+0x18)
2980 +#define RC32300_DMA_NEXTREG(n)  (RC32300_IO_DMA(n)+0x1c)
2981 +
2982 +#define RC32300_DMA_IRQ(n)  (GROUP7_IRQ_BASE+5*(n))
2983 +
2984 +/* Expansion Interrupt Controller */
2985 +#define IC_GROUP0_PEND     (RC32334_REG_BASE + 0x0500)
2986 +#define IC_GROUP0_MASK     (RC32334_REG_BASE + 0x0504)
2987 +#define IC_GROUP0_CLEAR    (RC32334_REG_BASE + 0x0508)
2988 +#define IC_GROUP_OFFSET    0x10
2989 +
2990 +#define NUM_INTR_GROUPS    15
2991 +/*
2992 + * The IRQ mapping is as follows:
2993 + *
2994 + *    IRQ         Mapped To
2995 + *    ---     -------------------
2996 + *     0      SW0  (IP0) SW0 intr
2997 + *     1      SW1  (IP1) SW1 intr
2998 + *     2      Int0 (IP2) board-specific
2999 + *     3      Int1 (IP3) board-specific
3000 + *     4      Int2 (IP4) board-specific
3001 + *     -      Int3 (IP5) not used, mapped to IRQ's 8 and up
3002 + *     6      Int4 (IP6) board-specific
3003 + *     7      Int5 (IP7) CP0 Timer
3004 + *
3005 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
3006 + * internally on the RC32334 is routed to the Expansion
3007 + * Interrupt Controller.
3008 + */
3009 +#define MIPS_CPU_TIMER_IRQ 7
3010 +
3011 +#define GROUP1_IRQ_BASE  8                       // bus error
3012 +#define GROUP2_IRQ_BASE  (GROUP1_IRQ_BASE + 1)   // PIO active low
3013 +#define GROUP3_IRQ_BASE  (GROUP2_IRQ_BASE + 12)  // PIO active high
3014 +#define GROUP4_IRQ_BASE  (GROUP3_IRQ_BASE + 8)   // Timer Rollovers
3015 +#define GROUP5_IRQ_BASE  (GROUP4_IRQ_BASE + 8)   // UART0
3016 +#define GROUP6_IRQ_BASE  (GROUP5_IRQ_BASE + 3)   // UART1
3017 +#define GROUP7_IRQ_BASE  (GROUP6_IRQ_BASE + 3)   // DMA Ch0
3018 +#define GROUP8_IRQ_BASE  (GROUP7_IRQ_BASE + 5)   // DMA Ch1
3019 +#define GROUP9_IRQ_BASE  (GROUP8_IRQ_BASE + 5)   // DMA Ch2
3020 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5)   // DMA Ch3
3021 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5)  // PCI Ctlr errors
3022 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4)  // PCI Satellite Mode
3023 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
3024 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4)  // SPI
3025 +
3026 +#define RC32334_NR_IRQS  (GROUP14_IRQ_BASE + 1)
3027 +
3028 +/* 16550 UARTs */
3029 +#ifdef __MIPSEB__
3030 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
3031 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
3032 +#else
3033 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
3034 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
3035 +#endif
3036 +
3037 +#define RC32300_UART0_IRQ  GROUP5_IRQ_BASE
3038 +#define RC32300_UART1_IRQ  GROUP6_IRQ_BASE
3039 +
3040 +#define IDT_CLOCK_MULT 2
3041 +
3042 +/* NVRAM */
3043 +#define NVRAM_BASE         0x12000000
3044 +#define NVRAM_ENVSIZE_OFF  4
3045 +#define NVRAM_ENVSTART_OFF 0x40
3046 +
3047 +/* LCD 4-digit display */
3048 +#define LCD_CLEAR          0x14000400
3049 +#define LCD_DIGIT0         0x1400000f
3050 +#define LCD_DIGIT1         0x14000008
3051 +#define LCD_DIGIT2         0x14000007
3052 +#define LCD_DIGIT3         0x14000003
3053 +
3054 +/* Interrupts routed on 79S334A board (see rc32334.h) */
3055 +#define RC32334_SCC8530_IRQ  2
3056 +#define RC32334_PCI_INTA_IRQ 3
3057 +#define RC32334_PCI_INTB_IRQ 4
3058 +#define RC32334_PCI_INTC_IRQ 6
3059 +#define RC32334_PCI_INTD_IRQ 7
3060 +
3061 +#define RAM_SIZE       (32*1024*1024)
3062 +
3063 +#endif // __IDT_RC32334_H__
3064 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3065 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h      1970-01-01 01:00:00.000000000 +0100
3066 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-06-18 12:44:28.000000000 +0200
3067 @@ -0,0 +1,206 @@
3068 +/**************************************************************************
3069 + *
3070 + *  BRIEF MODULE DESCRIPTION
3071 + *     DMA controller defines on IDT RC32355
3072 + *
3073 + *  Copyright 2004 IDT Inc.
3074 + *  Author: Integrated Device Technology Inc. rischelp@idt.com
3075 + *
3076 + *
3077 + *  This program is free software; you can redistribute  it and/or modify it
3078 + *  under  the terms of  the GNU General  Public License as published by the
3079 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3080 + *  option) any later version.
3081 + *
3082 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3083 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3084 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3085 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3086 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3087 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3088 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3089 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3090 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3091 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3092 + *
3093 + *  You should have received a copy of the  GNU General Public License along
3094 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3095 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3096 + *
3097 + *
3098 + *  May 2004 rkt
3099 + *  Initial Release
3100 + *
3101 + **************************************************************************
3102 + */
3103 +
3104 +#ifndef BANYAN_DMA_H
3105 +#define BANYAN_DMA_H
3106 +#include  <asm/idt-boards/rc32300/rc32300.h>
3107 +
3108 +/*
3109 + * An image of one RC32355 dma channel registers
3110 + */
3111 +typedef struct {
3112 +       u32 dmac;
3113 +       u32 dmas;
3114 +       u32 dmasm;
3115 +       u32 dmadptr;
3116 +       u32 dmandptr;
3117 +} rc32355_dma_ch_t;
3118 +
3119 +/*
3120 + * An image of all RC32355 dma channel registers
3121 + */
3122 +typedef struct {
3123 +       rc32355_dma_ch_t ch[16];
3124 +} rc32355_dma_regs_t;
3125 +
3126 +
3127 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3128 +
3129 +
3130 +/* DMAC register layout */
3131 +
3132 +#define DMAC_RUN       0x1     /* Halts processing when cleared        */
3133 +#define DMAC_DM                0x2     /* Done Mask, ignore DMA events         */
3134 +#define DMAC_MODE_MASK 0xC     /* DMA operating mode                   */
3135 +
3136 +#define DMAC_MODE_AUTO 0x0     /* DMA Auto Request Mode                */
3137 +#define DMAC_MODE_BURST        0x4     /* DMA Burst Request Mode               */
3138 +#define DMAC_MODE_TFER 0x8     /* DMA Transfer Request Mode            */
3139 +
3140 +/* DMAS and DMASM register layout */
3141 +
3142 +#define DMAS_F         0x01    /* Finished */
3143 +#define DMAS_D         0x02    /* Done */
3144 +#define DMAS_C         0x04    /* Chain */
3145 +#define DMAS_E         0x08    /* Error */
3146 +#define DMAS_H         0x10    /* Halt */
3147 +
3148 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3149 +#define DMA_HALT_TIMEOUT 500
3150 +
3151 +
3152 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3153 +{
3154 +       int timeout=1;
3155 +
3156 +       if (local_readl(&ch->dmac) & DMAC_RUN) {
3157 +               local_writel(0, &ch->dmac);
3158 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3159 +                       if (local_readl(&ch->dmas) & DMAS_H) {
3160 +                               local_writel(0, &ch->dmas);
3161 +                               break;
3162 +                       }
3163 +               }
3164 +       }
3165 +
3166 +       return timeout ? 0 : 1;
3167 +}
3168 +
3169 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3170 +{
3171 +       local_writel(0, &ch->dmandptr);
3172 +       local_writel(dma_addr, &ch->dmadptr);
3173 +}
3174 +
3175 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3176 +{
3177 +       local_writel(dma_addr, &ch->dmandptr);
3178 +}
3179 +
3180 +
3181 +/* The following can be used to describe DMA channels 0 to 15, and the */
3182 +/* sub device's needed to select them in the DMADESC_DS_MASK field     */
3183 +
3184 +#define DMA_CHAN_ATM01         0            /* ATM interface 0,1 chan  */
3185 +
3186 +#define DMA_CHAN_ATM0IN                0            /* ATM interface 0 input   */
3187 +#define DMA_DEV_ATM0IN         0            /* ATM interface 0 input   */
3188 +
3189 +#define DMA_CHAN_ATM1IN                0            /* ATM interface 1 input   */
3190 +#define DMA_DEV_ATM1IN         1            /* ATM interface 1 input   */
3191 +
3192 +#define DMA_CHAN_ATM0OUT       0            /* ATM interface 0 output  */
3193 +#define DMA_DEV_ATM0OUT                2            /* ATM interface 0 output  */
3194 +
3195 +#define DMA_CHAN_ATM1OUT       0            /* ATM interface 1 output  */
3196 +#define DMA_DEV_ATM1OUT                3            /* ATM interface 1 output  */
3197 +
3198 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3199 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1)  /* ATM VC cache entry      */
3200 +#define DMA_DEV_ATMVCC(entry)  0
3201 +
3202 +#define DMA_CHAN_MEMTOMEM      6            /* Memory to memory DMA    */
3203 +#define DMA_DEV_MEMTOMEM       1            /* Memory to memory DMA    */
3204 +
3205 +#define DMA_CHAN_ATMFMB0       7            /* ATM Frame Mode Buffer 0 */
3206 +#define DMA_DEV_ATMFMB0                1            /* ATM Frame Mode Buffer 0 */
3207 +
3208 +#define DMA_CHAN_ATMFMB1       8            /* ATM Frame Mode Buffer 1 */
3209 +#define DMA_DEV_ATMFMB1                1            /* ATM Frame Mode Buffer 1 */
3210 +
3211 +#define DMA_CHAN_ETHERIN       9            /* Ethernet input          */
3212 +#define DMA_DEV_ETHERIN                0            /* Ethernet input          */
3213 +
3214 +#define DMA_CHAN_ETHEROUT      10           /* Ethernet output         */
3215 +#define DMA_DEV_ETHEROUT       0            /* Ethernet output         */
3216 +
3217 +#define DMA_CHAN_TDMIN         11           /* TDM Bus input           */
3218 +#define DMA_DEV_TDMIN          0            /* TDM Bus input           */
3219 +
3220 +#define DMA_CHAN_TDMOUT                12           /* TDM Bus output          */
3221 +#define DMA_DEV_TDMOUT         0            /* TDM Bus output          */
3222 +
3223 +#define DMA_CHAN_USBIN         13           /* USB input               */
3224 +#define DMA_DEV_USBIN          0            /* USB input               */
3225 +
3226 +#define DMA_CHAN_USBOUT                14           /* USB output              */
3227 +#define DMA_DEV_USBOUT         0            /* USB output              */
3228 +
3229 +#define DMA_CHAN_EXTERN                15           /* External DMA            */
3230 +#define DMA_DEV_EXTERN         0            /* External DMA            */
3231 +
3232 +/*
3233 + * An RC32355 dma descriptor in system memory
3234 + */
3235 +typedef struct {
3236 +       u32 cmdstat;    /* control and status */
3237 +       u32 curr_addr;  /* current address of data */
3238 +       u32 devcs;      /* peripheral-specific control and status */
3239 +       u32 link;       /* link to next descriptor */
3240 +} rc32355_dma_desc_t;
3241 +
3242 +/* Values for the descriptor cmdstat word */
3243 +
3244 +#define DMADESC_F              0x80000000u  /* Finished bit            */
3245 +#define DMADESC_D              0x40000000u  /* Done bit                */
3246 +#define DMADESC_T              0x20000000u  /* Terminated bit          */
3247 +#define DMADESC_IOD            0x10000000u  /* Interrupt On Done       */
3248 +#define DMADESC_IOF            0x08000000u  /* Interrupt On Finished   */
3249 +#define DMADESC_COD            0x04000000u  /* Chain On Done           */
3250 +#define DMADESC_COF            0x02000000u  /* Chain On Finished       */
3251 +
3252 +#define DMADESC_DEVCMD_MASK    0x01C00000u  /* Device Command mask     */
3253 +#define DMADESC_DEVCMD_SHIFT   22           /* Device Command shift    */
3254 +
3255 +#define DMADESC_DS_MASK                0x00300000u  /* Device Select mask      */
3256 +#define DMADESC_DS_SHIFT       20           /* Device Select shift     */
3257 +
3258 +#define DMADESC_COUNT_MASK     0x0003FFFFu  /* Byte Count mask         */
3259 +#define DMADESC_COUNT_SHIFT    0            /* Byte Count shift        */
3260 +
3261 +#define IS_DMA_FINISHED(X)   ( ( (X) & DMADESC_F ) >> 31)   /* F Bit    */
3262 +#define IS_DMA_DONE(X)       ( ( (X) & DMADESC_D ) >> 30)   /* D Bit    */
3263 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29)   /* T Bit    */
3264 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3265 +
3266 +#define DMA_DEVCMD(devcmd) \
3267 +  (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3268 +#define DMA_DS(ds)         \
3269 +  (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3270 +#define DMA_COUNT(count)   \
3271 +  ((count) & DMADESC_COUNT_MASK)
3272 +
3273 +#endif /* RC32355_DMA_H */
3274 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3275 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h      1970-01-01 01:00:00.000000000 +0100
3276 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-06-18 12:44:28.000000000 +0200
3277 @@ -0,0 +1,442 @@
3278 +/**************************************************************************
3279 + *
3280 + *  BRIEF MODULE DESCRIPTION
3281 + *     Ethernet registers on IDT RC32355
3282 + *
3283 + *  Copyright 2004 IDT Inc.
3284 + *  Author: Integrated Device Technology Inc. rischelp@idt.com
3285 + *
3286 + *
3287 + *  This program is free software; you can redistribute  it and/or modify it
3288 + *  under  the terms of  the GNU General  Public License as published by the
3289 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3290 + *  option) any later version.
3291 + *
3292 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3293 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3294 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3295 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3296 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3297 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3298 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3299 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3300 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3301 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3302 + *
3303 + *  You should have received a copy of the  GNU General Public License along
3304 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3305 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3306 + *
3307 + *
3308 + *  May 2004 rkt
3309 + *  Initial Release
3310 + *
3311 + **************************************************************************
3312 + */
3313 +
3314 +
3315 +#ifndef RC32355_ETHER_H
3316 +#define RC32355_ETHER_H
3317 +
3318 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3319 +
3320 +/*
3321 + * A partial image of the RC32355 ethernet registers
3322 + */
3323 +typedef struct {
3324 +       u32 ethintfc;
3325 +       u32 ethfifott;
3326 +       u32 etharc;
3327 +       u32 ethhash0;
3328 +       u32 ethhash1;
3329 +       u32 ethfifost;
3330 +       u32 ethfifos;
3331 +       u32 ethodeops;
3332 +       u32 ethis;
3333 +       u32 ethos;
3334 +       u32 ethmcp;
3335 +       u32 _u1;
3336 +       u32 ethid;
3337 +       u32 _u2;
3338 +       u32 _u3;
3339 +       u32 _u4;
3340 +       u32 ethod;
3341 +       u32 _u5;
3342 +       u32 _u6;
3343 +       u32 _u7;
3344 +       u32 ethodeop;
3345 +       u32 _u8[43];
3346 +       u32 ethsal0;
3347 +       u32 ethsah0;
3348 +       u32 ethsal1;
3349 +       u32 ethsah1;
3350 +       u32 ethsal2;
3351 +       u32 ethsah2;
3352 +       u32 ethsal3;
3353 +       u32 ethsah3;
3354 +       u32 ethrbc;
3355 +       u32 ethrpc;
3356 +       u32 ethrupc;
3357 +       u32 ethrfc;
3358 +       u32 ethtbc;
3359 +       u32 ethgpf;
3360 +       u32 _u9[50];
3361 +       u32 ethmac1;
3362 +       u32 ethmac2;
3363 +       u32 ethipgt;
3364 +       u32 ethipgr;
3365 +       u32 ethclrt;
3366 +       u32 ethmaxf;
3367 +       u32 _u10;
3368 +       u32 ethmtest;
3369 +       u32 miimcfg;
3370 +       u32 miimcmd;
3371 +       u32 miimaddr;
3372 +       u32 miimwtd;
3373 +       u32 miimrdd;
3374 +       u32 miimind;
3375 +       u32 _u11;
3376 +       u32 _u12;
3377 +       u32 ethcfsa0;
3378 +       u32 ethcfsa1;
3379 +       u32 ethcfsa2;
3380 +} rc32355_eth_regs_t;
3381 +
3382 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3383 +
3384 +#define ETH_INTFC   (RC32355_ETH_BASE + 0x000) /* INTerFace Control  */
3385 +#define ETH_FIFOTT  (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold  */
3386 +#define ETH_ARC     (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl  */
3387 +#define ETH_HASH0   (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3388 +#define ETH_HASH1   (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3389 +#define ETH_FIFOST  (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3390 +#define ETH_FIFOS   (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3391 +#define ETH_ODEOPS  (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3392 +#define ETH_IS      (RC32355_ETH_BASE + 0x020) /* Input Status */
3393 +#define ETH_OS      (RC32355_ETH_BASE + 0x024) /* Output Status  */
3394 +#define ETH_MCP     (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3395 +#define ETH_ID      (RC32355_ETH_BASE + 0x030) /* Input Data register */
3396 +#define ETH_OD      (RC32355_ETH_BASE + 0x040) /* Output Data register */
3397 +#define ETH_ODEOP   (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3398 +
3399 +/* for n in { 0, 1, 2, 3 } */
3400 +#define ETH_SAL(n)  (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3401 +#define ETH_SAH(n)  (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3402 +
3403 +#define ETH_RBC     (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3404 +#define ETH_RPC     (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3405 +#define ETH_RUPC    (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3406 +#define ETH_RFC     (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3407 +#define ETH_TBC     (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3408 +#define ETH_GPF     (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3409 +#define ETH_MAC1    (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3410 +#define ETH_MAC2    (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3411 +#define ETH_IPGT    (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3412 +#define ETH_IPGR    (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3413 +#define ETH_CLRT    (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3414 +#define ETH_MAXF    (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3415 +#define ETH_MTEST   (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3416 +
3417 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3418 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command  */
3419 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3420 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3421 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3422 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3423 +
3424 +/* for n in { 0, 1, 2 } */
3425 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4))  /* Station Addr */
3426 +
3427 +
3428 +/*
3429 + * Register Interpretations follow
3430 + */
3431 +
3432 +/******************************************************************************
3433 + * ETHINTFC register
3434 + *****************************************************************************/
3435 +
3436 +#define ETHERINTFC_EN            (1<<0)
3437 +#define ETHERINTFC_ITS           (1<<1)
3438 +#define ETHERINTFC_RES           (1<<2)
3439 +#define ETHERINTFC_RIP           (1<<2)
3440 +#define ETHERINTFC_JAM           (1<<3)
3441 +
3442 +/******************************************************************************
3443 + * ETHFIFOTT register
3444 + *****************************************************************************/
3445 +
3446 +#define ETHERFIFOTT_TTH(v)      (((v)&0x3f)<<0)
3447 +
3448 +/******************************************************************************
3449 + * ETHARC register
3450 + *****************************************************************************/
3451 +
3452 +#define ETHERARC_PRO             (1<<0)
3453 +#define ETHERARC_AM              (1<<1)
3454 +#define ETHERARC_AFM             (1<<2)
3455 +#define ETHERARC_AB              (1<<3)
3456 +
3457 +/******************************************************************************
3458 + * ETHHASH registers
3459 + *****************************************************************************/
3460 +
3461 +#define ETHERHASH0(v)            (((v)&0xffff)<<0)
3462 +#define ETHERHASH1(v)            (((v)&0xffff)<<0)
3463 +
3464 +/******************************************************************************
3465 + * ETHSA registers
3466 + *****************************************************************************/
3467 +
3468 +#define ETHERSAL0(v)             (((v)&0xffff)<<0)
3469 +#define ETHERSAL1(v)             (((v)&0xffff)<<0)
3470 +#define ETHERSAL2(v)             (((v)&0xffff)<<0)
3471 +#define ETHERSAL3(v)             (((v)&0xffff)<<0)
3472 +#define ETHERSAH0(v)             (((v)&0xff)<<0)
3473 +#define ETHERSAH1(v)             (((v)&0xff)<<0)
3474 +#define ETHERSAH2(v)             (((v)&0xff)<<0)
3475 +#define ETHERSAH3(v)             (((v)&0xff)<<0)
3476 +
3477 +/******************************************************************************
3478 + * ETHFIFOST register
3479 + *****************************************************************************/
3480 +
3481 +#define ETHERFIFOST_IRTH(v)      (((v)&0x3f)<<0)
3482 +#define ETHERFIFOST_ORTH(v)      (((v)&0x3f)<<16)
3483 +
3484 +/******************************************************************************
3485 + * ETHFIFOS register
3486 + *****************************************************************************/
3487 +
3488 +#define ETHERFIFOS_IR            (1<<0)
3489 +#define ETHERFIFOS_OR            (1<<1)
3490 +#define ETHERFIFOS_OVR           (1<<2)
3491 +#define ETHERFIFOS_UND           (1<<3)
3492 +
3493 +/******************************************************************************
3494 + * DATA registers
3495 + *****************************************************************************/
3496 +
3497 +#define ETHERID(v)               (((v)&0xffff)<<0)
3498 +#define ETHEROD(v)               (((v)&0xffff)<<0)
3499 +
3500 +/******************************************************************************
3501 + * ETHODEOPS register
3502 + *****************************************************************************/
3503 +
3504 +#define ETHERODEOPS_SIZE(v)      (((v)&0x3)<<0)
3505 +
3506 +/******************************************************************************
3507 + * ETHODEOP register
3508 + *****************************************************************************/
3509 +
3510 +#define ETHERODEOP(v)            (((v)&0xffff)<<0)
3511 +
3512 +/******************************************************************************
3513 + * ETHIS register
3514 + *****************************************************************************/
3515 +
3516 +#define ETHERIS_EOP              (1<<0)
3517 +#define ETHERIS_ROK              (1<<2)
3518 +#define ETHERIS_FM               (1<<3)
3519 +#define ETHERIS_MP               (1<<4)
3520 +#define ETHERIS_BP               (1<<5)
3521 +#define ETHERIS_VLT              (1<<6)
3522 +#define ETHERIS_CF               (1<<7)
3523 +#define ETHERIS_OVR              (1<<8)
3524 +#define ETHERIS_CRC              (1<<9)
3525 +#define ETHERIS_CV               (1<<10)
3526 +#define ETHERIS_DB               (1<<11)
3527 +#define ETHERIS_LE               (1<<12)
3528 +#define ETHERIS_LOR              (1<<13)
3529 +#define ETHERIS_SIZE(v)          (((v)&0x3)<<14)
3530 +#define ETHERIS_LENGTH(v)        (((v)&0xff)<<16)
3531 +
3532 +/******************************************************************************
3533 + * ETHOS register
3534 + *****************************************************************************/
3535 +
3536 +#define ETHEROS_T                (1<<0)
3537 +#define ETHEROS_TOK              (1<<6)
3538 +#define ETHEROS_MP               (1<<7)
3539 +#define ETHEROS_BP               (1<<8)
3540 +#define ETHEROS_UND              (1<<9)
3541 +#define ETHEROS_OF               (1<<10)
3542 +#define ETHEROS_ED               (1<<11)
3543 +#define ETHEROS_EC               (1<<12)
3544 +#define ETHEROS_LC               (1<<13)
3545 +#define ETHEROS_TD               (1<<14)
3546 +#define ETHEROS_CRC              (1<<15)
3547 +#define ETHEROS_LE               (1<<16)
3548 +#define ETHEROS_CC(v)            (((v)&0xf)<<17)
3549 +#define ETHEROS_PFD              (1<<21)
3550 +
3551 +/******************************************************************************
3552 + * Statistics registers
3553 + *****************************************************************************/
3554 +
3555 +#define ETHERRBC(v)              (((v)&0xffff)<<0)
3556 +#define ETHERRPC(v)              (((v)&0xffff)<<0)
3557 +#define ETHERRUPC(v)             (((v)&0xffff)<<0)
3558 +#define ETHERRFC(v)              (((v)&0xffff)<<0)
3559 +#define ETHERTBC(v)              (((v)&0xffff)<<0)
3560 +
3561 +/******************************************************************************
3562 + * ETHGPF register
3563 + *****************************************************************************/
3564 +
3565 +#define ETHERGPF_PTV(v)          (((v)&0xff)<<0)
3566 +
3567 +/******************************************************************************
3568 + * MAC registers
3569 + *****************************************************************************/
3570 +//ETHMAC1
3571 +#define ETHERMAC1_RE             (1<<0)
3572 +#define ETHERMAC1_PAF            (1<<1)
3573 +#define ETHERMAC1_RFC            (1<<2)
3574 +#define ETHERMAC1_TFC            (1<<3)
3575 +#define ETHERMAC1_LB             (1<<4)
3576 +#define ETHERMAC1_MR             (1<<15)
3577 +
3578 +//ETHMAC2
3579 +#define ETHERMAC2_FD             (1<<0)
3580 +#define ETHERMAC2_FLC            (1<<1)
3581 +#define ETHERMAC2_HFE            (1<<2)
3582 +#define ETHERMAC2_DC             (1<<3)
3583 +#define ETHERMAC2_CEN            (1<<4)
3584 +#define ETHERMAC2_PE             (1<<5)
3585 +#define ETHERMAC2_VPE            (1<<6)
3586 +#define ETHERMAC2_APE            (1<<7)
3587 +#define ETHERMAC2_PPE            (1<<8)
3588 +#define ETHERMAC2_LPE            (1<<9)
3589 +#define ETHERMAC2_NB             (1<<12)
3590 +#define ETHERMAC2_BP             (1<<13)
3591 +#define ETHERMAC2_ED             (1<<14)
3592 +
3593 +//ETHIPGT
3594 +#define ETHERIPGT(v)             (((v)&0x3f)<<0)
3595 +
3596 +//ETHIPGR
3597 +#define ETHERIPGR_IPGR1(v)       (((v)&0x3f)<<0)
3598 +#define ETHERIPGR_IPGR2(v)       (((v)&0x3f)<<8)
3599 +
3600 +//ETHCLRT
3601 +#define ETHERCLRT_MAXRET(v)      (((v)&0x3f)<<0)
3602 +#define ETHERCLRT_COLWIN(v)      (((v)&0x3f)<<8)
3603 +
3604 +//ETHMAXF
3605 +#define ETHERMAXF(v)             (((v)&0x3f)<<0)
3606 +
3607 +//ETHMTEST
3608 +#define ETHERMTEST_TB            (1<<2)
3609 +
3610 +//ETHMCP
3611 +#define ETHERMCP_DIV(v)          (((v)&0xff)<<0)
3612 +
3613 +//MIIMCFG
3614 +#define ETHERMIIMCFG_CS(v)          (((v)&0x3)<<2)
3615 +#define ETHERMIIMCFG_R              (1<<15)
3616 +
3617 +//MIIMCMD
3618 +#define ETHERMIIMCMD_RD             (1<<0)
3619 +#define ETHERMIIMCMD_SCN            (1<<1)
3620 +
3621 +//MIIMADDR
3622 +#define ETHERMIIMADDR_REGADDR(v)    (((v)&0x1f)<<0)
3623 +#define ETHERMIIMADDR_PHYADDR(v)    (((v)&0x1f)<<8)
3624 +
3625 +//MIIMWTD
3626 +#define ETHERMIIMWTD(v)             (((v)&0xff)<<0)
3627 +
3628 +//MIIMRDD
3629 +#define ETHERMIIMRDD(v)             (((v)&0xff)<<0)
3630 +
3631 +//MIIMIND
3632 +#define ETHERMIIMIND_BSY            (1<<0)
3633 +#define ETHERMIIMIND_SCN            (1<<1)
3634 +#define ETHERMIIMIND_NV             (1<<2)
3635 +
3636 +//DMA DEVCS IN
3637 +#define ETHERDMA_IN_LENGTH(v)  (((v)&0xffff)<<16)
3638 +#define ETHERDMA_IN_CES                (1<<14)
3639 +#define ETHERDMA_IN_LOR                (1<<13)
3640 +#define ETHERDMA_IN_LE         (1<<12)
3641 +#define ETHERDMA_IN_DB         (1<<11)
3642 +#define ETHERDMA_IN_CV         (1<<10)
3643 +#define ETHERDMA_IN_CRC                (1<<9)
3644 +#define ETHERDMA_IN_OVR                (1<<8)
3645 +#define ETHERDMA_IN_CF         (1<<7)
3646 +#define ETHERDMA_IN_VLT                (1<<6)
3647 +#define ETHERDMA_IN_BP         (1<<5)
3648 +#define ETHERDMA_IN_MP         (1<<4)
3649 +#define ETHERDMA_IN_FM         (1<<3)
3650 +#define ETHERDMA_IN_ROK                (1<<2)
3651 +#define ETHERDMA_IN_LD         (1<<1)
3652 +#define ETHERDMA_IN_FD         (1<<0)
3653 +
3654 +//DMA DEVCS OUT
3655 +#define ETHERDMA_OUT_CC(v)     (((v)&0xf)<<17)
3656 +#define ETHERDMA_OUT_CNT         0x001e0000
3657 +#define ETHERDMA_OUT_SHFT       17
3658 +#define ETHERDMA_OUT_LE                (1<<16)
3659 +
3660 +#define ETHERDMA_OUT_CRC       (1<<15)
3661 +#define ETHERDMA_OUT_TD                (1<<14)
3662 +#define ETHERDMA_OUT_LC                (1<<13)
3663 +#define ETHERDMA_OUT_EC                (1<<12)
3664 +#define ETHERDMA_OUT_ED                (1<<11)
3665 +#define ETHERDMA_OUT_OF                (1<<10)
3666 +#define ETHERDMA_OUT_UND       (1<<9)
3667 +#define ETHERDMA_OUT_BP                (1<<8)
3668 +#define ETHERDMA_OUT_MP                (1<<7)
3669 +#define ETHERDMA_OUT_TOK       (1<<6)
3670 +#define ETHERDMA_OUT_HEN       (1<<5)
3671 +#define ETHERDMA_OUT_CEN       (1<<4)
3672 +#define ETHERDMA_OUT_PEN       (1<<3)
3673 +#define ETHERDMA_OUT_OEN       (1<<2)
3674 +#define ETHERDMA_OUT_LD                (1<<1)
3675 +#define ETHERDMA_OUT_FD                (1<<0)
3676 +
3677 +#define RCV_ERRS \
3678 +  (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
3679 +#define TX_ERRS  \
3680 +  (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
3681 +   ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
3682 +
3683 +#define IS_RCV_ROK(X)        (((X) & (1<<2)) >> 2)       /* Receive Okay     */
3684 +#define IS_RCV_FM(X)         (((X) & (1<<3)) >> 3)       /* Is Filter Match  */
3685 +#define IS_RCV_MP(X)         (((X) & (1<<4)) >> 4)       /* Is it MP         */
3686 +#define IS_RCV_BP(X)         (((X) & (1<<5)) >> 5)       /* Is it BP         */
3687 +#define IS_RCV_VLT(X)        (((X) & (1<<6)) >> 6)       /* VLAN Tag Detect  */
3688 +#define IS_RCV_CF(X)         (((X) & (1<<7)) >> 7)       /* Control Frame    */
3689 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<8)) >> 8)       /* Receive Overflow */
3690 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<9)) >> 9)       /* CRC Error        */
3691 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<10))>>10)       /* Code Violation   */
3692 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<11))>>11)       /* Dribble Bits     */
3693 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<12))>>12)       /* Length error     */
3694 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<13))>>13)       /* Length Out of
3695 +                                                            Range            */
3696 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<14))>>14)       /* Preamble error   */
3697 +#define RCVPKT_LENGTH(X)     (((X) & 0xFFFF0000)>>16)    /* Length of the
3698 +                                                            received packet  */
3699 +
3700 +#define IS_TX_TOK(X)         (((X) & (1<<6) ) >> 6 )     /* Transmit Okay    */
3701 +#define IS_TX_MP(X)          (((X) & (1<<7) ) >> 7 )     /* Multicast        */
3702 +
3703 +#define IS_TX_BP(X)          (((X) & (1<<8) ) >> 8 )     /* Broadcast        */
3704 +#define IS_TX_UND_ERR(X)     (((X) & (1<<9) ) >> 9 )     /* Transmit FIFO
3705 +                                                            Underflow        */
3706 +#define IS_TX_OF_ERR(X)      (((X) & (1<<10)) >>10 )     /* Oversized frame  */
3707 +#define IS_TX_ED_ERR(X)      (((X) & (1<<11)) >>11 )     /* Excessive
3708 +                                                           deferral        */
3709 +#define IS_TX_EC_ERR(X)      (((X) & (1<<12)) >>12 )     /* Excessive
3710 +                                                           collisions      */
3711 +#define IS_TX_LC_ERR(X)      (((X) & (1<<13)) >>13 )     /* Late Collision   */
3712 +#define IS_TX_TD_ERR(X)      (((X) & (1<<14)) >>14 )     /* Transmit deferred*/
3713 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<15)) >>15 )     /* CRC Error        */
3714 +#define IS_TX_LE_ERR(X)      (((X) & (1<<16)) >>16 )     /* Length Error     */
3715 +
3716 +#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17)  /* Collision Count  */
3717 +
3718 +#endif /* RC32355_ETHER_H */
3719 +
3720 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h
3721 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355.h  1970-01-01 01:00:00.000000000 +0100
3722 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h     2006-06-18 12:44:28.000000000 +0200
3723 @@ -0,0 +1,177 @@
3724 +/**************************************************************************
3725 + *
3726 + *  BRIEF MODULE DESCRIPTION
3727 + *     Definitions for IDT RC32355 CPU.
3728 + *
3729 + *  Copyright 2004 IDT Inc.
3730 + *  Author: Integrated Device Technology Inc. rischelp@idt.com
3731 + *
3732 + *
3733 + *  This program is free software; you can redistribute  it and/or modify it
3734 + *  under  the terms of  the GNU General  Public License as published by the
3735 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3736 + *  option) any later version.
3737 + *
3738 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3739 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3740 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3741 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3742 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3743 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3744 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3745 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3746 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3747 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3748 + *
3749 + *  You should have received a copy of the  GNU General Public License along
3750 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3751 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3752 + *
3753 + *
3754 + *  May 2004 rkt
3755 + *  Initial Release
3756 + *
3757 + **************************************************************************
3758 + */
3759 +
3760 +
3761 +#ifndef _RC32355_H_
3762 +#define _RC32355_H_
3763 +
3764 +#include <linux/delay.h>
3765 +#include <asm/io.h>
3766 +
3767 +/* Base address of internal registers */
3768 +#define RC32355_REG_BASE   0x18000000
3769 +
3770 +/* System ID Registers */
3771 +#define CPU_SYSID          (RC32355_REG_BASE + 0x00018)
3772 +#define CPU_BTADDR         (RC32355_REG_BASE + 0x0001c)
3773 +#define CPU_REV            (RC32355_REG_BASE + 0x0002c)
3774 +
3775 +/* Reset Controller */
3776 +#define RESET_CNTL         (RC32355_REG_BASE + 0x08000)
3777 +
3778 +/* Device Controller */
3779 +#define DEV0_BASE          (RC32355_REG_BASE + 0x10000)
3780 +#define DEV0_MASK          (RC32355_REG_BASE + 0x10004)
3781 +#define DEV0_CNTL          (RC32355_REG_BASE + 0x10008)
3782 +#define DEV0_TIMING        (RC32355_REG_BASE + 0x1000c)
3783 +#define DEV_REG_OFFSET     0x10
3784 +
3785 +/* SDRAM Controller */
3786 +#define SDRAM0_BASE        (RC32355_REG_BASE + 0x18000)
3787 +#define SDRAM0_MASK        (RC32355_REG_BASE + 0x18004)
3788 +#define SDRAM1_BASE        (RC32355_REG_BASE + 0x18008)
3789 +#define SDRAM1_MASK        (RC32355_REG_BASE + 0x1800c)
3790 +#define SDRAM_CNTL         (RC32355_REG_BASE + 0x18010)
3791 +
3792 +/* Bus Arbiter */
3793 +#define BUS_ARB_CNTL0      (RC32355_REG_BASE + 0x20000)
3794 +#define BUS_ARB_CNTL1      (RC32355_REG_BASE + 0x20004)
3795 +
3796 +/* Counters/Timers */
3797 +#define TIMER0_COUNT       (RC32355_REG_BASE + 0x28000)
3798 +#define TIMER0_COMPARE     (RC32355_REG_BASE + 0x28004)
3799 +#define TIMER0_CNTL        (RC32355_REG_BASE + 0x28008)
3800 +#define TIMER_REG_OFFSET   0x0C
3801 +
3802 +/* System Integrity */
3803 +
3804 +/* Interrupt Controller */
3805 +#define IC_GROUP0_PEND     (RC32355_REG_BASE + 0x30000)
3806 +#define IC_GROUP0_MASK     (RC32355_REG_BASE + 0x30004)
3807 +#define IC_GROUP_OFFSET    0x08
3808 +
3809 +#define NUM_INTR_GROUPS    5
3810 +/*
3811 + * The IRQ mapping is as follows:
3812 + *
3813 + *    IRQ         Mapped To
3814 + *    ---     -------------------
3815 + *     0      SW0  (IP0) SW0 intr
3816 + *     1      SW1  (IP1) SW1 intr
3817 + *     -      Int0 (IP2) mapped to GROUP0_IRQ_BASE
3818 + *     -      Int1 (IP3) mapped to GROUP1_IRQ_BASE
3819 + *     -      Int2 (IP4) mapped to GROUP2_IRQ_BASE
3820 + *     -      Int3 (IP5) mapped to GROUP3_IRQ_BASE
3821 + *     -      Int4 (IP6) mapped to GROUP4_IRQ_BASE
3822 + *     7      Int5 (IP7) CP0 Timer
3823 + *
3824 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
3825 + * internally on the RC32355 is routed to the Expansion
3826 + * Interrupt Controller.
3827 + */
3828 +#define MIPS_CPU_TIMER_IRQ 7
3829 +
3830 +#define GROUP0_IRQ_BASE  8                      // Counter/Timers, UCW
3831 +#define GROUP1_IRQ_BASE  (GROUP0_IRQ_BASE + 32) // DMA
3832 +#define GROUP2_IRQ_BASE  (GROUP1_IRQ_BASE + 32) // ATM
3833 +#define GROUP3_IRQ_BASE  (GROUP2_IRQ_BASE + 32) // TDM, Eth, USB, UARTs, I2C
3834 +#define GROUP4_IRQ_BASE  (GROUP3_IRQ_BASE + 32) // GPIO
3835 +
3836 +#define RC32355_NR_IRQS  (GROUP4_IRQ_BASE + 32)
3837 +
3838 +/* DMA - see rc32355_dma.h for full list of registers */
3839 +
3840 +#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
3841 +#define DMA_CHAN_OFFSET  0x14
3842 +
3843 +/* GPIO Controller */
3844 +
3845 +/* TDM Bus */
3846 +
3847 +/* 16550 UARTs */
3848 +#ifdef __MIPSEB__
3849 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
3850 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
3851 +#else
3852 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
3853 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
3854 +#endif
3855 +
3856 +#define RC32300_UART0_IRQ  (GROUP3_IRQ_BASE + 14)
3857 +#define RC32300_UART1_IRQ  (GROUP3_IRQ_BASE + 17)
3858 +
3859 +/* ATM */
3860 +
3861 +/* Ethernet - see rc32355_eth.h for full list of registers */
3862 +
3863 +#define RC32355_ETH_BASE   (RC32355_REG_BASE + 0x60000)
3864 +
3865 +
3866 +#define IDT_CLOCK_MULT 2
3867 +
3868 +/* Memory map of 79EB355 board */
3869 +
3870 +/* DRAM */
3871 +#define RAM_BASE        0x00000000
3872 +#define RAM_SIZE       (32*1024*1024)
3873 +
3874 +/* SRAM (device 1) */
3875 +#define SRAM_BASE       0x02000000
3876 +#define SRAM_SIZE       0x00100000
3877 +
3878 +/* FLASH (device 2) */
3879 +#define FLASH_BASE      0x0C000000
3880 +#define FLASH_SIZE      0x00C00000
3881 +
3882 +/* ATM PHY (device 4) */
3883 +#define ATM_PHY_BASE    0x14000000
3884 +
3885 +/* TDM switch (device 3) */
3886 +#define TDM_BASE        0x1A000000
3887 +
3888 +/* LCD panel (device 3) */
3889 +#define LCD_BASE        0x1A002000
3890 +
3891 +/* RTC (DS1511W) (device 3) */
3892 +#define RTC_BASE        0x1A004000
3893 +
3894 +/* NVRAM (256 bytes internal to the DS1511 RTC) */
3895 +#define NVRAM_ADDR      RTC_BASE + 0x10
3896 +#define NVRAM_DATA      RTC_BASE + 0x13
3897 +#define NVRAM_ENVSIZE_OFF  4
3898 +#define NVRAM_ENVSTART_OFF 32
3899 +
3900 +#endif /* _RC32355_H_ */
3901 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h
3902 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma.h      1970-01-01 01:00:00.000000000 +0100
3903 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 2006-06-18 12:44:28.000000000 +0200
3904 @@ -0,0 +1,226 @@
3905 +/**************************************************************************
3906 + *
3907 + *  BRIEF MODULE DESCRIPTION
3908 + *   RC32365/336 DMA hardware abstraction.
3909 + *
3910 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
3911 + *
3912 + *  This program is free software; you can redistribute  it and/or modify it
3913 + *  under  the terms of  the GNU General  Public License as published by the
3914 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3915 + *  option) any later version.
3916 + *
3917 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3918 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3919 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3920 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3921 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3922 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3923 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3924 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3925 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3926 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3927 + *
3928 + *  You should have received a copy of the  GNU General Public License along
3929 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3930 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3931 + *
3932 + *
3933 + **************************************************************************
3934 + * May 2004 P. Sadik.
3935 + *
3936 + * Initial Release
3937 + *
3938 + *
3939 + *
3940 + **************************************************************************
3941 + */
3942 +
3943 +#ifndef __IDT_RC32365_DMA_H__
3944 +#define __IDT_RC32365_DMA_H__
3945 +
3946 +enum
3947 +{
3948 +       DMA0_PhysicalAddress    = 0x18038000,
3949 +       DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
3950 +
3951 +       DMA0_VirtualAddress     = 0xb8038000,
3952 +       DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
3953 +} ;
3954 +
3955 +/*
3956 + * DMA descriptor (in physical memory).
3957 + */
3958 +
3959 +typedef struct DMAD_s
3960 +{
3961 +       u32                     control ;       // Control. use DMAD_*
3962 +       u32                     ca ;            // Current Address.
3963 +       u32                     devcs ;         // Device control and status.
3964 +       u32                     link ;          // Next descriptor in chain.
3965 +} volatile *DMAD_t ;
3966 +
3967 +enum
3968 +{
3969 +       DMAD_size               = sizeof (struct DMAD_s),
3970 +       DMAD_count_b            = 0,            // in DMAD_t -> control
3971 +       DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
3972 +       DMAD_ds_b               = 20,           // in DMAD_t -> control
3973 +       DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
3974 +       DMAD_ds_extToMem0_v     = 0,
3975 +       DMAD_ds_memToExt0_v     = 1,
3976 +       DMAD_ds_extToMem1_v     = 0,
3977 +       DMAD_ds_memToExt1_v     = 1,
3978 +       DMAD_ds_ethRcv0_v       = 0,
3979 +       DMAD_ds_ethXmt0_v       = 0,
3980 +       DMAD_ds_ethRcv1_v       = 0,
3981 +       DMAD_ds_ethXmt2_v       = 0,
3982 +       DMAD_ds_memToFifo_v     = 0,
3983 +       DMAD_ds_fifoToMem_v     = 0,
3984 +       DMAD_ds_rng_de_v           = 1,//randomNumberGenerator on LC/DE
3985 +       DMAD_ds_pciToMem_v      = 0,
3986 +       DMAD_ds_memToPci_v      = 0,
3987 +       DMAD_ds_securityInput_v = 0,
3988 +       DMAD_ds_securityOutput_v = 0,
3989 +       DMAD_ds_rng_se_v        = 0,//randomNumberGenerator on SE
3990 +
3991 +       DMAD_devcmd_b           = 22,           // in DMAD_t -> control
3992 +       DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
3993 +       DMAD_devcmd_byte_v      = 0,    //memory-to-memory
3994 +       DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
3995 +       DMAD_devcmd_word_v      = 2,    //memory-to-memory
3996 +       DMAD_devcmd_2words_v    = 3,    //memory-to-memory
3997 +       DMAD_devcmd_4words_v    = 4,    //memory-to-memory
3998 +       DMAD_devcmd_6words_v    = 5,    //memory-to-memory
3999 +       DMAD_devcmd_8words_v    = 6,    //memory-to-memory
4000 +       DMAD_devcmd_16words_v   = 7,    //memory-to-memory
4001 +       DMAD_cof_b              = 25,           // chain on finished
4002 +       DMAD_cof_m              = 0x02000000,   //
4003 +       DMAD_cod_b              = 26,           // chain on done
4004 +       DMAD_cod_m              = 0x04000000,   //
4005 +       DMAD_iof_b              = 27,           // interrupt on finished
4006 +       DMAD_iof_m              = 0x08000000,   //
4007 +       DMAD_iod_b              = 28,           // interrupt on done
4008 +       DMAD_iod_m              = 0x10000000,   //
4009 +       DMAD_t_b                = 29,           // terminated
4010 +       DMAD_t_m                = 0x20000000,   //
4011 +       DMAD_d_b                = 30,           // done
4012 +       DMAD_d_m                = 0x40000000,   //
4013 +       DMAD_f_b                = 31,           // finished
4014 +       DMAD_f_m                = 0x80000000,   //
4015 +} ;
4016 +
4017 +/*
4018 + * DMA register (within Internal Register Map).
4019 + */
4020 +
4021 +struct DMA_Chan_s
4022 +{
4023 +       u32             dmac ;          // Control.
4024 +       u32             dmas ;          // Status.
4025 +       u32             dmasm ;         // Mask.
4026 +       u32             dmadptr ;       // Descriptor pointer.
4027 +       u32             dmandptr ;      // Next descriptor pointer.
4028 +};
4029 +
4030 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
4031 +
4032 +//DMA_Channels   use DMACH_count instead
4033 +
4034 +enum
4035 +{
4036 +       DMAC_run_b      = 0,            //
4037 +       DMAC_run_m      = 0x00000001,   //
4038 +       DMAC_dm_b       = 1,            // done mask
4039 +       DMAC_dm_m       = 0x00000002,   //
4040 +       DMAC_mode_b     = 2,            //
4041 +       DMAC_mode_m     = 0x0000000c,   //
4042 +       DMAC_mode_auto_v        = 0,
4043 +       DMAC_mode_burst_v       = 1,
4044 +       DMAC_mode_transfer_v    = 2, //usually used
4045 +       DMAC_mode_reserved_v    = 3,
4046 +       DMAC_a_b        = 4,            //
4047 +       DMAC_a_m        = 0x00000010,   //
4048 +
4049 +       DMAS_f_b        = 0,            // finished (sticky)
4050 +       DMAS_f_m        = 0x00000001,   //
4051 +       DMAS_d_b        = 1,            // done (sticky)
4052 +       DMAS_d_m        = 0x00000002,   //
4053 +       DMAS_c_b        = 2,            // chain (sticky)
4054 +       DMAS_c_m        = 0x00000004,   //
4055 +       DMAS_e_b        = 3,            // error (sticky)
4056 +       DMAS_e_m        = 0x00000008,   //
4057 +       DMAS_h_b        = 4,            // halt (sticky)
4058 +       DMAS_h_m        = 0x00000010,   //
4059 +
4060 +       DMASM_f_b       = 0,            // finished (1=mask)
4061 +       DMASM_f_m       = 0x00000001,   //
4062 +       DMASM_d_b       = 1,            // done (1=mask)
4063 +       DMASM_d_m       = 0x00000002,   //
4064 +       DMASM_c_b       = 2,            // chain (1=mask)
4065 +       DMASM_c_m       = 0x00000004,   //
4066 +       DMASM_e_b       = 3,            // error (1=mask)
4067 +       DMASM_e_m       = 0x00000008,   //
4068 +       DMASM_h_b       = 4,            // halt (1=mask)
4069 +       DMASM_h_m       = 0x00000010,   //
4070 +} ;
4071 +
4072 +/*
4073 + * DMA channel definitions
4074 + */
4075 +
4076 +enum
4077 +{
4078 +       DMACH_ethRcv0 = 0,
4079 +       DMACH_ethXmt0 = 1,
4080 +       DMACH_ethRcv1 = 2,
4081 +       DMACH_ethXmt2 = 3,
4082 +       DMACH_pciToMem = 4,
4083 +       DMACH_memToPci = 5,
4084 +       DMACH_securityInput = 6,
4085 +       DMACH_securityOutput = 7,
4086 +       DMACH_rng = 8,
4087 +
4088 +       DMACH_count //must be last
4089 +};
4090 +
4091 +
4092 +typedef struct DMAC_s
4093 +{
4094 +       struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
4095 +} volatile *DMA_t ;
4096 +
4097 +
4098 +/*
4099 + * External DMA parameters
4100 +*/
4101 +
4102 +enum
4103 +{
4104 +       DMADEVCMD_ts_b  = 0,            // ts field in devcmd
4105 +       DMADEVCMD_ts_m  = 0x00000007,   // ts field in devcmd
4106 +       DMADEVCMD_ts_byte_v     = 0,
4107 +       DMADEVCMD_ts_halfword_v = 1,
4108 +       DMADEVCMD_ts_word_v     = 2,
4109 +       DMADEVCMD_ts_2word_v    = 3,
4110 +       DMADEVCMD_ts_4word_v    = 4,
4111 +       DMADEVCMD_ts_6word_v    = 5,
4112 +       DMADEVCMD_ts_8word_v    = 6,
4113 +       DMADEVCMD_ts_16word_v   = 7
4114 +};
4115 +
4116 +
4117 +#if 1  // aws - Compatibility.
4118 +#      define  EXTDMA_ts_b             DMADEVCMD_ts_b
4119 +#      define  EXTDMA_ts_m             DMADEVCMD_ts_m
4120 +#      define  EXTDMA_ts_byte_v        DMADEVCMD_ts_byte_v
4121 +#      define  EXTDMA_ts_halfword_v    DMADEVCMD_ts_halfword_v
4122 +#      define  EXTDMA_ts_word_v        DMADEVCMD_ts_word_v
4123 +#      define  EXTDMA_ts_2word_v       DMADEVCMD_ts_2word_v
4124 +#      define  EXTDMA_ts_4word_v       DMADEVCMD_ts_4word_v
4125 +#      define  EXTDMA_ts_6word_v       DMADEVCMD_ts_6word_v
4126 +#      define  EXTDMA_ts_8word_v       DMADEVCMD_ts_8word_v
4127 +#      define  EXTDMA_ts_16word_v      DMADEVCMD_ts_16word_v
4128 +#endif // aws - Compatibility.
4129 +
4130 +#endif // __IDT_RC32365_DMA_H__
4131 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h
4132 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h    1970-01-01 01:00:00.000000000 +0100
4133 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h       2006-06-18 12:44:28.000000000 +0200
4134 @@ -0,0 +1,86 @@
4135 +/**************************************************************************
4136 + *
4137 + *  BRIEF MODULE DESCRIPTION
4138 + *   RC32365/336 DMA interface routines.
4139 + *
4140 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4141 + *
4142 + *  This program is free software; you can redistribute  it and/or modify it
4143 + *  under  the terms of  the GNU General  Public License as published by the
4144 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4145 + *  option) any later version.
4146 + *
4147 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4148 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4149 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4150 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4151 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4152 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4153 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4154 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4155 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4156 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4157 + *
4158 + *  You should have received a copy of the  GNU General Public License along
4159 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4160 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4161 + *
4162 + *
4163 + **************************************************************************
4164 + * May 2004 P. Sadik.
4165 + *
4166 + * Initial Release
4167 + *
4168 + *
4169 + *
4170 + **************************************************************************
4171 + */
4172 +
4173 +#ifndef __IDT_RC32365_DMA_V_H__
4174 +#define __IDT_RC32365_DMA_V_H__
4175 +
4176 +
4177 +#include  <asm/idt-boards/rc32300/rc32300.h>
4178 +#include  <asm/idt-boards/rc32300/rc32365_dma.h>
4179 +#include  <asm/idt-boards/rc32300/rc32365.h>
4180 +
4181 +#define DMA_CHAN_OFFSET  0x14
4182 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
4183 +#define IS_DMA_FINISHED(X)   (((X) & (DMAD_f_m)) != 0)
4184 +#define IS_DMA_DONE(X)   (((X) & (DMAD_d_m)) != 0)
4185 +
4186 +#define DMA_COUNT(count)   \
4187 +  ((count) & DMAD_count_m)
4188 +
4189 +#define DMA_HALT_TIMEOUT 500
4190 +
4191 +static inline int rc32365_halt_dma(DMA_Chan_t ch)
4192 +{
4193 +       int timeout=1;
4194 +       if (local_readl(&ch->dmac) & DMAC_run_m) {
4195 +               local_writel(0, &ch->dmac);
4196 +
4197 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
4198 +                       if (local_readl(&ch->dmas) & DMAS_h_m) {
4199 +                               local_writel(0, &ch->dmas);
4200 +                               break;
4201 +                       }
4202 +               }
4203 +
4204 +       }
4205 +
4206 +       return timeout ? 0 : 1;
4207 +}
4208 +
4209 +
4210 +static inline void rc32365_start_dma(DMA_Chan_t ch, u32 dma_addr)
4211 +{
4212 +       local_writel(0, &ch->dmandptr);
4213 +       local_writel(dma_addr, &ch->dmadptr);
4214 +}
4215 +
4216 +static inline void rc32365_chain_dma(DMA_Chan_t ch, u32 dma_addr)
4217 +{
4218 +       local_writel(dma_addr, &ch->dmandptr);
4219 +}
4220 +#endif //__IDT_RC32365_DMA_V_H__
4221 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h
4222 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth.h      1970-01-01 01:00:00.000000000 +0100
4223 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 2006-06-18 12:44:28.000000000 +0200
4224 @@ -0,0 +1,344 @@
4225 +/**************************************************************************
4226 + *
4227 + *  BRIEF MODULE DESCRIPTION
4228 + *   RC32365/336 Ethernet hardware abstraction.
4229 + *
4230 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4231 + *
4232 + *  This program is free software; you can redistribute  it and/or modify it
4233 + *  under  the terms of  the GNU General  Public License as published by the
4234 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4235 + *  option) any later version.
4236 + *
4237 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4238 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4239 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4240 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4241 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4242 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4243 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4244 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4245 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4246 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4247 + *
4248 + *  You should have received a copy of the  GNU General Public License along
4249 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4250 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4251 + *
4252 + *
4253 + **************************************************************************
4254 + * May 2004 P. Sadik.
4255 + *
4256 + * Initial Release
4257 + *
4258 + *
4259 + *
4260 + **************************************************************************
4261 + */
4262 +
4263 +#ifndef        __IDT_RC32365_ETH_H__
4264 +#define        __IDT_RC32365_ETH_H__
4265 +
4266 +enum
4267 +{
4268 +       ETH0_PhysicalAddress    = 0x18058000,
4269 +       ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
4270 +       ETH0_VirtualAddress     = 0xb8058000,
4271 +
4272 +       ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
4273 +
4274 +       ETH1_PhysicalAddress    = 0x18060000,
4275 +       ETH1_VirtualAddress     = 0xb8060000,                   // Default
4276 +} ;
4277 +
4278 +typedef struct
4279 +{
4280 +       u32 ethintfc            ;
4281 +       u32 ethfifott           ;
4282 +       u32 etharc              ;
4283 +       u32 ethhash0            ;
4284 +       u32 ethhash1            ;
4285 +       u32 ethu0 [4]           ;       // Reserved.
4286 +       u32 ethpfs              ;
4287 +       u32 ethmcp              ;
4288 +       u32 eth_u1 [10]         ;       // Reserved.
4289 +       u32 ethspare            ;
4290 +       u32 eth_u2 [42]         ;       // Reserved.
4291 +       u32 ethsal0             ;
4292 +       u32 ethsah0             ;
4293 +       u32 ethsal1             ;
4294 +       u32 ethsah1             ;
4295 +       u32 ethsal2             ;
4296 +       u32 ethsah2             ;
4297 +       u32 ethsal3             ;
4298 +       u32 ethsah3             ;
4299 +       u32 ethrbc              ;
4300 +       u32 ethrpc              ;
4301 +       u32 ethrupc             ;
4302 +       u32 ethrfc              ;
4303 +       u32 ethtbc              ;
4304 +       u32 ethgpf              ;
4305 +       u32 eth_u9 [50]         ;       // Reserved.
4306 +       u32 ethmac1             ;
4307 +       u32 ethmac2             ;
4308 +       u32 ethipgt             ;
4309 +       u32 ethipgr             ;
4310 +       u32 ethclrt             ;
4311 +       u32 ethmaxf             ;
4312 +       u32 eth_u10             ;       // Reserved.
4313 +       u32 ethmtest            ;
4314 +       u32 miimcfg             ;
4315 +       u32 miimcmd             ;
4316 +       u32 miimaddr            ;
4317 +       u32 miimwtd             ;
4318 +       u32 miimrdd             ;
4319 +       u32 miimind             ;
4320 +       u32 eth_u11             ;       // Reserved.
4321 +       u32 eth_u12             ;       // Reserved.
4322 +       u32 ethcfsa0            ;
4323 +       u32 ethcfsa1            ;
4324 +       u32 ethcfsa2            ;
4325 +} volatile *ETH_t;
4326 +
4327 +enum
4328 +{
4329 +       ETHINTFC_en_b           = 0,
4330 +       ETHINTFC_en_m           = 0x00000001,
4331 +       ETHINTFC_its_b          = 1,
4332 +       ETHINTFC_its_m          = 0x00000002,
4333 +       ETHINTFC_rip_b          = 2,
4334 +       ETHINTFC_rip_m          = 0x00000004,
4335 +       ETHINTFC_jam_b          = 3,
4336 +       ETHINTFC_jam_m          = 0x00000008,
4337 +       ETHINTFC_ovr_b          = 4,
4338 +       ETHINTFC_ovr_m          = 0x00000010,
4339 +       ETHINTFC_und_b          = 5,
4340 +       ETHINTFC_und_m          = 0x00000020,
4341 +
4342 +       ETHFIFOTT_tth_b         = 0,
4343 +       ETHFIFOTT_tth_m         = 0x0000007f,
4344 +
4345 +       ETHARC_pro_b            = 0,
4346 +       ETHARC_pro_m            = 0x00000001,
4347 +       ETHARC_am_b             = 1,
4348 +       ETHARC_am_m             = 0x00000002,
4349 +       ETHARC_afm_b            = 2,
4350 +       ETHARC_afm_m            = 0x00000004,
4351 +       ETHARC_ab_b             = 3,
4352 +       ETHARC_ab_m             = 0x00000008,
4353 +
4354 +       ETHSAL_byte5_b          = 0,
4355 +       ETHSAL_byte5_m          = 0x000000ff,
4356 +       ETHSAL_byte4_b          = 8,
4357 +       ETHSAL_byte4_m          = 0x0000ff00,
4358 +       ETHSAL_byte3_b          = 16,
4359 +       ETHSAL_byte3_m          = 0x00ff0000,
4360 +       ETHSAL_byte2_b          = 24,
4361 +       ETHSAL_byte2_m          = 0xff000000,
4362 +
4363 +       ETHSAH_byte1_b          = 0,
4364 +       ETHSAH_byte1_m          = 0x000000ff,
4365 +       ETHSAH_byte0_b          = 8,
4366 +       ETHSAH_byte0_m          = 0x0000ff00,
4367 +
4368 +       ETHGPF_ptv_b            = 0,
4369 +       ETHGPF_ptv_m            = 0x0000ffff,
4370 +
4371 +       ETHPFS_pfd_b            = 0,
4372 +       ETHPFS_pfd_m            = 0x00000001,
4373 +
4374 +       ETHCFSA0_cfsa4_b        = 0,
4375 +       ETHCFSA0_cfsa4_m        = 0x000000ff,
4376 +       ETHCFSA0_cfsa5_b        = 8,
4377 +       ETHCFSA0_cfsa5_m        = 0x0000ff00,
4378 +
4379 +       ETHCFSA1_cfsa2_b        = 0,
4380 +       ETHCFSA1_cfsa2_m        = 0x000000ff,
4381 +       ETHCFSA1_cfsa3_b        = 8,
4382 +       ETHCFSA1_cfsa3_m        = 0x0000ff00,
4383 +
4384 +       ETHCFSA2_cfsa0_b        = 0,
4385 +       ETHCFSA2_cfsa0_m        = 0x000000ff,
4386 +       ETHCFSA2_cfsa1_b        = 8,
4387 +       ETHCFSA2_cfsa1_m        = 0x0000ff00,
4388 +
4389 +       ETHMAC1_re_b            = 0,
4390 +       ETHMAC1_re_m            = 0x00000001,
4391 +       ETHMAC1_paf_b           = 1,
4392 +       ETHMAC1_paf_m           = 0x00000002,
4393 +       ETHMAC1_rfc_b           = 2,
4394 +       ETHMAC1_rfc_m           = 0x00000004,
4395 +       ETHMAC1_tfc_b           = 3,
4396 +       ETHMAC1_tfc_m           = 0x00000008,
4397 +       ETHMAC1_lb_b            = 4,
4398 +       ETHMAC1_lb_m            = 0x00000010,
4399 +       ETHMAC1_mr_b            = 31,
4400 +       ETHMAC1_mr_m            = 0x80000000,
4401 +
4402 +       ETHMAC2_fd_b            = 0,
4403 +       ETHMAC2_fd_m            = 0x00000001,
4404 +       ETHMAC2_flc_b           = 1,
4405 +       ETHMAC2_flc_m           = 0x00000002,
4406 +       ETHMAC2_hfe_b           = 2,
4407 +       ETHMAC2_hfe_m           = 0x00000004,
4408 +       ETHMAC2_dc_b            = 3,
4409 +       ETHMAC2_dc_m            = 0x00000008,
4410 +       ETHMAC2_cen_b           = 4,
4411 +       ETHMAC2_cen_m           = 0x00000010,
4412 +       ETHMAC2_pe_b            = 5,
4413 +       ETHMAC2_pe_m            = 0x00000020,
4414 +       ETHMAC2_vpe_b           = 6,
4415 +       ETHMAC2_vpe_m           = 0x00000040,
4416 +       ETHMAC2_ape_b           = 7,
4417 +       ETHMAC2_ape_m           = 0x00000080,
4418 +       ETHMAC2_ppe_b           = 8,
4419 +       ETHMAC2_ppe_m           = 0x00000100,
4420 +       ETHMAC2_lpe_b           = 9,
4421 +       ETHMAC2_lpe_m           = 0x00000200,
4422 +       ETHMAC2_nb_b            = 12,
4423 +       ETHMAC2_nb_m            = 0x00001000,
4424 +       ETHMAC2_bp_b            = 13,
4425 +       ETHMAC2_bp_m            = 0x00002000,
4426 +       ETHMAC2_ed_b            = 14,
4427 +       ETHMAC2_ed_m            = 0x00004000,
4428 +
4429 +       ETHIPGT_ipgt_b          = 0,
4430 +       ETHIPGT_ipgt_m          = 0x0000007f,
4431 +
4432 +       ETHIPGR_ipgr2_b         = 0,
4433 +       ETHIPGR_ipgr2_m         = 0x0000007f,
4434 +       ETHIPGR_ipgr1_b         = 8,
4435 +       ETHIPGR_ipgr1_m         = 0x00007f00,
4436 +
4437 +       ETHCLRT_maxret_b        = 0,
4438 +       ETHCLRT_maxret_m        = 0x0000000f,
4439 +       ETHCLRT_colwin_b        = 8,
4440 +       ETHCLRT_colwin_m        = 0x00003f00,
4441 +
4442 +       ETHMAXF_maxf_b          = 0,
4443 +       ETHMAXF_maxf_m          = 0x0000ffff,
4444 +
4445 +       ETHMTEST_tb_b           = 2,
4446 +       ETHMTEST_tb_m           = 0x00000004,
4447 +
4448 +       ETHMCP_div_b            = 0,
4449 +       ETHMCP_div_m            = 0x000000ff,
4450 +
4451 +       MIIMCFG_rsv_b           = 0,
4452 +       MIIMCFG_rsv_m           = 0x0000000c,
4453 +
4454 +       MIIMCMD_rd_b            = 0,
4455 +       MIIMCMD_rd_m            = 0x00000001,
4456 +       MIIMCMD_scn_b           = 1,
4457 +       MIIMCMD_scn_m           = 0x00000002,
4458 +
4459 +       MIIMADDR_regaddr_b      = 0,
4460 +       MIIMADDR_regaddr_m      = 0x0000001f,
4461 +       MIIMADDR_phyaddr_b      = 8,
4462 +       MIIMADDR_phyaddr_m      = 0x00001f00,
4463 +
4464 +       MIIMWTD_wdata_b         = 0,
4465 +       MIIMWTD_wdata_m         = 0x0000ffff,
4466 +
4467 +       MIIMRDD_rdata_b         = 0,
4468 +       MIIMRDD_rdata_m         = 0x0000ffff,
4469 +
4470 +       MIIMIND_bsy_b           = 0,
4471 +       MIIMIND_bsy_m           = 0x00000001,
4472 +       MIIMIND_scn_b           = 1,
4473 +       MIIMIND_scn_m           = 0x00000002,
4474 +       MIIMIND_nv_b            = 2,
4475 +       MIIMIND_nv_m            = 0x00000004,
4476 +
4477 +} ;
4478 +
4479 +/*
4480 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
4481 + */
4482 +enum
4483 +{
4484 +       ETHRX_fd_b              = 0,
4485 +       ETHRX_fd_m              = 0x00000001,
4486 +       ETHRX_ld_b              = 1,
4487 +       ETHRX_ld_m              = 0x00000002,
4488 +       ETHRX_rok_b             = 2,
4489 +       ETHRX_rok_m             = 0x00000004,
4490 +       ETHRX_fm_b              = 3,
4491 +       ETHRX_fm_m              = 0x00000008,
4492 +       ETHRX_mp_b              = 4,
4493 +       ETHRX_mp_m              = 0x00000010,
4494 +       ETHRX_bp_b              = 5,
4495 +       ETHRX_bp_m              = 0x00000020,
4496 +       ETHRX_vlt_b             = 6,
4497 +       ETHRX_vlt_m             = 0x00000040,
4498 +       ETHRX_cf_b              = 7,
4499 +       ETHRX_cf_m              = 0x00000080,
4500 +       ETHRX_ovr_b             = 8,
4501 +       ETHRX_ovr_m             = 0x00000100,
4502 +       ETHRX_crc_b             = 9,
4503 +       ETHRX_crc_m             = 0x00000200,
4504 +       ETHRX_cv_b              = 10,
4505 +       ETHRX_cv_m              = 0x00000400,
4506 +       ETHRX_db_b              = 11,
4507 +       ETHRX_db_m              = 0x00000800,
4508 +       ETHRX_le_b              = 12,
4509 +       ETHRX_le_m              = 0x00001000,
4510 +       ETHRX_lor_b             = 13,
4511 +       ETHRX_lor_m             = 0x00002000,
4512 +       ETHRX_ces_b             = 14,
4513 +       ETHRX_ces_m             = 0x00004000,
4514 +       ETHRX_length_b          = 16,
4515 +       ETHRX_length_m          = 0xffff0000,
4516 +
4517 +       ETHTX_fd_b              = 0,
4518 +       ETHTX_fd_m              = 0x00000001,
4519 +       ETHTX_ld_b              = 1,
4520 +       ETHTX_ld_m              = 0x00000002,
4521 +       ETHTX_oen_b             = 2,
4522 +       ETHTX_oen_m             = 0x00000004,
4523 +       ETHTX_pen_b             = 3,
4524 +       ETHTX_pen_m             = 0x00000008,
4525 +       ETHTX_cen_b             = 4,
4526 +       ETHTX_cen_m             = 0x00000010,
4527 +       ETHTX_hen_b             = 5,
4528 +       ETHTX_hen_m             = 0x00000020,
4529 +       ETHTX_tok_b             = 6,
4530 +       ETHTX_tok_m             = 0x00000040,
4531 +       ETHTX_mp_b              = 7,
4532 +       ETHTX_mp_m              = 0x00000080,
4533 +       ETHTX_bp_b              = 8,
4534 +       ETHTX_bp_m              = 0x00000100,
4535 +       ETHTX_und_b             = 9,
4536 +       ETHTX_und_m             = 0x00000200,
4537 +       ETHTX_of_b              = 10,
4538 +       ETHTX_of_m              = 0x00000400,
4539 +       ETHTX_ed_b              = 11,
4540 +       ETHTX_ed_m              = 0x00000800,
4541 +       ETHTX_ec_b              = 12,
4542 +       ETHTX_ec_m              = 0x00001000,
4543 +       ETHTX_lc_b              = 13,
4544 +       ETHTX_lc_m              = 0x00002000,
4545 +       ETHTX_td_b              = 14,
4546 +       ETHTX_td_m              = 0x00004000,
4547 +       ETHTX_crc_b             = 15,
4548 +       ETHTX_crc_m             = 0x00008000,
4549 +       ETHTX_le_b              = 16,
4550 +       ETHTX_le_m              = 0x00010000,
4551 +       ETHTX_cc_b              = 17,
4552 +       ETHTX_cc_m              = 0x001E0000,
4553 +} ;
4554 +
4555 +enum
4556 +{
4557 +       ETH0_IPABMC_PhysicalAddress     = 0x18040010,
4558 +       ETH0_IPABMC_VirtualAddress      = 0xb8040000,
4559 +       ETH1_IPABMC_PhysicalAddress     = 0x18040018,
4560 +       ETH1_IPABMC_VirtualAddress      = 0xb8040018,
4561 +} ;
4562 +
4563 +typedef struct
4564 +{
4565 +       u32 ipabmcrx            ;
4566 +       u32 ipabmctx            ;
4567 +}volatile *IPABM_ETH_t;
4568 +#endif //__IDT_RC32365_ETH_H__
4569 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h
4570 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h    1970-01-01 01:00:00.000000000 +0100
4571 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h       2006-06-18 12:44:28.000000000 +0200
4572 @@ -0,0 +1,72 @@
4573 +/**************************************************************************
4574 + *
4575 + *  BRIEF MODULE DESCRIPTION
4576 + *   RC32365/336 Ethernet status checking.
4577 + *
4578 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4579 + *
4580 + *  This program is free software; you can redistribute  it and/or modify it
4581 + *  under  the terms of  the GNU General  Public License as published by the
4582 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4583 + *  option) any later version.
4584 + *
4585 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4586 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4587 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4588 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4589 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4590 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4591 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4592 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4593 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4594 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4595 + *
4596 + *  You should have received a copy of the  GNU General Public License along
4597 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4598 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4599 + *
4600 + *
4601 + **************************************************************************
4602 + * May 2004 P. Sadik.
4603 + *
4604 + * Initial Release
4605 + *
4606 + *
4607 + *
4608 + **************************************************************************
4609 + */
4610 +
4611 +#ifndef __IDT_RC32365_ETH_V_H__
4612 +#define __IDT_RC32365_ETH_V_H__
4613 +#include  <asm/idt-boards/rc32300/rc32365_eth.h>
4614 +
4615 +#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
4616 +#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
4617 +#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
4618 +#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
4619 +#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
4620 +#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
4621 +#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
4622 +#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
4623 +#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
4624 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
4625 +#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
4626 +
4627 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
4628 +
4629 +#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
4630 +#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
4631 +#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
4632 +#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
4633 +#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
4634 +#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
4635 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
4636 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
4637 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
4638 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
4639 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
4640 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
4641 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
4642 +#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
4643 +
4644 +#endif //__IDT_RC32365_ETH_V_H__
4645 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h
4646 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h     1970-01-01 01:00:00.000000000 +0100
4647 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h        2006-06-18 12:44:28.000000000 +0200
4648 @@ -0,0 +1,181 @@
4649 +/**************************************************************************
4650 + *
4651 + *  BRIEF MODULE DESCRIPTION
4652 + *   RC32365/336 GPIO hardware abstraction.
4653 + *
4654 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4655 + *
4656 + *  This program is free software; you can redistribute  it and/or modify it
4657 + *  under  the terms of  the GNU General  Public License as published by the
4658 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4659 + *  option) any later version.
4660 + *
4661 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4662 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4663 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4664 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4665 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4666 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4667 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4668 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4669 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4670 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4671 + *
4672 + *  You should have received a copy of the  GNU General Public License along
4673 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4674 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4675 + *
4676 + *
4677 + **************************************************************************
4678 + * May 2004 P. Sadik.
4679 + *
4680 + * Initial Release
4681 + *
4682 + *
4683 + *
4684 + **************************************************************************
4685 + */
4686 +
4687 +#ifndef        __IDT_RC32365_GPIO_H__
4688 +#define        __IDT_RC32365_GPIO_H__
4689 +
4690 +enum
4691 +{
4692 +       GPIO0_PhysicalAddress   = 0x18048000,
4693 +       GPIO_PhysicalAddress    = GPIO0_PhysicalAddress,        // Default
4694 +
4695 +       GPIO0_VirtualAddress    = 0xb8048000,
4696 +       GPIO_VirtualAddress     = GPIO0_VirtualAddress,         // Default
4697 +} ;
4698 +
4699 +typedef struct
4700 +{
4701 +       u32   gpiofunc;   /* GPIO Function Register
4702 +                          * gpiofunc[x]==0 bit = gpio
4703 +                          * func[x]==1  bit = altfunc
4704 +                          */
4705 +       u32   gpiocfg;    /* GPIO Configuration Register
4706 +                          * gpiocfg[x]==0 bit = input
4707 +                          * gpiocfg[x]==1 bit = output
4708 +                          */
4709 +       u32   gpiod;        /* GPIO Data Register
4710 +                            * gpiod[x] read/write gpio pinX status
4711 +                            */
4712 +       u32   gpioilevel; /* GPIO Interrupt Status Register
4713 +                          * interrupt level (see gpioistat)
4714 +                          */
4715 +       u32   gpioistat;  /* Gpio Interrupt Status Register
4716 +                          * istat[x] = (gpiod[x] == level[x])
4717 +                          * cleared in ISR (STICKY bits)
4718 +                          */
4719 +       u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
4720 +} volatile * GPIO_t ;
4721 +
4722 +typedef enum
4723 +{
4724 +       GPIO_gpio_v         = 0,                // gpiofunc use pin as GPIO.
4725 +       GPIO_alt_v          = 1,                // gpiofunc use pin as alt.
4726 +       GPIO_input_v        = 0,                // gpiocfg use pin as input.
4727 +       GPIO_output_v       = 1,                // gpiocfg use pin as output.
4728 +       GPIO_pin0_b         = 0,
4729 +       GPIO_pin0_m         = 0x00000001,
4730 +       GPIO_pin1_b         = 1,
4731 +       GPIO_pin1_m         = 0x00000002,
4732 +       GPIO_pin2_b         = 2,
4733 +       GPIO_pin2_m         = 0x00000004,
4734 +       GPIO_pin3_b         = 3,
4735 +       GPIO_pin3_m         = 0x00000008,
4736 +       GPIO_pin4_b         = 4,
4737 +       GPIO_pin4_m         = 0x00000010,
4738 +       GPIO_pin5_b         = 5,
4739 +       GPIO_pin5_m         = 0x00000020,
4740 +       GPIO_pin6_b         = 6,
4741 +       GPIO_pin6_m         = 0x00000040,
4742 +       GPIO_pin7_b         = 7,
4743 +       GPIO_pin7_m         = 0x00000080,
4744 +       GPIO_pin8_b         = 8,
4745 +       GPIO_pin8_m         = 0x00000100,
4746 +       GPIO_pin9_b         = 9,
4747 +       GPIO_pin9_m         = 0x00000200,
4748 +       GPIO_pin10_b        = 10,
4749 +       GPIO_pin10_m        = 0x00000400,
4750 +       GPIO_pin11_b        = 11,
4751 +       GPIO_pin11_m        = 0x00000800,
4752 +       GPIO_pin12_b        = 12,
4753 +       GPIO_pin12_m        = 0x00001000,
4754 +       GPIO_pin13_b        = 13,
4755 +       GPIO_pin13_m        = 0x00002000,
4756 +       GPIO_pin14_b        = 14,
4757 +       GPIO_pin14_m        = 0x00004000,
4758 +       GPIO_pin15_b        = 15,
4759 +       GPIO_pin15_m        = 0x00008000,
4760 +
4761 +// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
4762 +
4763 +       GPIO_u0sout_b       = GPIO_pin0_b,              // UART 0 serial out.
4764 +       GPIO_u0sout_m       = GPIO_pin0_m,
4765 +       GPIO_u0sout_cfg_v   = GPIO_output_v,
4766 +
4767 +       GPIO_u0sinp_b       = GPIO_pin1_b,                      // UART 0 serial in.
4768 +       GPIO_u0sinp_m       = GPIO_pin1_m,
4769 +       GPIO_u0sinp_cfg_v   = GPIO_input_v,
4770 +
4771 +       GPIO_maddr22_b      = GPIO_pin2_b,      // M&P bus bit 22.
4772 +       GPIO_maddr22_m      = GPIO_pin2_m,
4773 +       GPIO_maddr22_cfg_v  = GPIO_output_v,
4774 +
4775 +       GPIO_maddr23_b      = GPIO_pin3_b,      // M&P bus bit 23.
4776 +       GPIO_maddr23_m      = GPIO_pin3_m,
4777 +       GPIO_maddr23_cfg_v  = GPIO_output_v,
4778 +
4779 +       GPIO_maddr24_b      = GPIO_pin4_b,      // M&P bus bit 24.
4780 +       GPIO_maddr24_m      = GPIO_pin4_m,
4781 +       GPIO_maddr24_cfg_v  = GPIO_output_v,
4782 +
4783 +       GPIO_maddr25_b      = GPIO_pin5_b,      // M&P bus bit 25.
4784 +       GPIO_maddr25_m      = GPIO_pin5_m,
4785 +       GPIO_maddr25_cfg_v  = GPIO_output_v,
4786 +
4787 +       GPIO_rngclk_b       = GPIO_pin6_b,      // reserved.
4788 +       GPIO_rngclk_m       = GPIO_pin6_m,
4789 +       GPIO_rngclk_cfg_v   = GPIO_input_v,
4790 +
4791 +       GPIO_sdckenp_b      = GPIO_pin7_b,      // reserved.
4792 +       GPIO_sdckenp_m      = GPIO_pin7_m,
4793 +       GPIO_sdckenp_cfg_v  = GPIO_output_v,
4794 +
4795 +       GPIO_cen1_b         = GPIO_pin8_b,      // reserved.
4796 +       GPIO_cen1_m         = GPIO_pin8_m,
4797 +       GPIO_cen1_cfg_v     = GPIO_output_v,
4798 +
4799 +       GPIO_cen2_b         = GPIO_pin9_b,      // reserved.
4800 +       GPIO_cen2_m         = GPIO_pin9_m,
4801 +       GPIO_cen2_cfg_v     = GPIO_output_v,
4802 +
4803 +       GPIO_regn_b         = GPIO_pin10_b,     // reserved.
4804 +       GPIO_regn_m         = GPIO_pin10_m,
4805 +       GPIO_regn_cfg_v     = GPIO_output_v,
4806 +
4807 +       GPIO_iordn_b        = GPIO_pin11_b,     // reserved.
4808 +       GPIO_iordn_m        = GPIO_pin11_m,
4809 +       GPIO_iordn_cfg_v    = GPIO_output_v,
4810 +
4811 +       GPIO_iowrn_b        = GPIO_pin12_b,     // reserved.
4812 +       GPIO_iowrn_m        = GPIO_pin12_m,
4813 +       GPIO_iowrn_cfg_v    = GPIO_output_v,
4814 +
4815 +       GPIO_pcireqn2_b     = GPIO_pin13_b,     // PCI messaging int.
4816 +       GPIO_pcireqn2_m     = GPIO_pin13_m,
4817 +       GPIO_pcireqn2_cfg_v = GPIO_input_v,
4818 +
4819 +       GPIO_pcigntn2_b     = GPIO_pin14_b,     // PCI messaging int.
4820 +       GPIO_pcigntn2_m     = GPIO_pin14_m,
4821 +       GPIO_pcigntn2_cfg_v = GPIO_output_v,
4822 +
4823 +       GPIO_pcimuintn_b    = GPIO_pin15_b,     // PCI messaging int.
4824 +       GPIO_pcimuintn_m    = GPIO_pin15_m,
4825 +       GPIO_pcimuintn_cfg_v= GPIO_output_v,
4826 +
4827 +} GPIO_DEFS_t;
4828 +
4829 +#endif //__IDT_RC32365_GPIO_H__
4830 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h
4831 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h   1970-01-01 01:00:00.000000000 +0100
4832 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h      2006-06-18 12:44:28.000000000 +0200
4833 @@ -0,0 +1,91 @@
4834 +/**************************************************************************
4835 + *
4836 + *  BRIEF MODULE DESCRIPTION
4837 + *   Routines to set/clear/toggle GPIO on RC32365
4838 + *
4839 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4840 + *
4841 + *  This program is free software; you can redistribute  it and/or modify it
4842 + *  under  the terms of  the GNU General  Public License as published by the
4843 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4844 + *  option) any later version.
4845 + *
4846 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4847 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4848 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4849 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4850 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4851 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4852 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4853 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4854 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4855 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4856 + *
4857 + *  You should have received a copy of the  GNU General Public License along
4858 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4859 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4860 + *
4861 + *
4862 + **************************************************************************
4863 + * May 2004 P. Sadik.
4864 + *
4865 + * Initial Release
4866 + *
4867 + *
4868 + *
4869 + **************************************************************************
4870 + */
4871 +#ifndef        __IDT_RC32365_GPIO_V_H__
4872 +#define        __IDT_RC32365_GPIO_V_H__
4873 +
4874 +
4875 +#ifdef _LANGUAGE_ASSEMBLY
4876 +#define SET_GPIO(pin) \
4877 +       lui t5,0xb804 ; \
4878 +       ori t5,t5,0x8000 ; \
4879 +       lw  t4,8(t5) ; \
4880 +       ori t4,t4,pin ; \
4881 +       sw  t4,8(t5) ;
4882 +
4883 +#define CLEAR_GPIO(pin) \
4884 +       lui t5,0xb804 ; \
4885 +       ori t5,t5,0x8000 ; \
4886 +       lw  t4,8(t5) ; \
4887 +        lui t6,0xFFFF; \
4888 +        ori t6,t6,0xFFFF; \
4889 +       xori t6,t6,pin ; \
4890 +        and  t4,t6 ; \
4891 +       sw  t4,8(t5) ;
4892 +
4893 +#define TOGGLE_GPIO(pin) \
4894 +       lui t5,0xb804 ; \
4895 +       ori t5,t5,0x8000 ; \
4896 +       lw  t4,8(t5) ; \
4897 +       xori t4,t4,pin ; \
4898 +       sw  t4,8(t5) ;
4899 +
4900 +#else // !_LANGUAGE_ASSEMBLY
4901 +#include  <asm/rc32300/types.h>
4902 +#include  <asm/rc32300/rc32365_gpio.h>
4903 +#include  <asm/rc32300/rc32365.h>
4904 +
4905 +static inline void set_gpio(unsigned long pin)
4906 +{
4907 +  idt_gpio->gpiod |= pin;
4908 +}
4909 +
4910 +static inline void clear_gpio(unsigned long pin)
4911 +{
4912 +  idt_gpio->gpiod &= ~pin;
4913 +}
4914 +static inline void toggle_gpio(unsigned long pin)
4915 +{
4916 +  idt_gpio->gpiod ^= pin;
4917 +}
4918 +#define SET_GPIO(pin) set_gpio(pin)
4919 +#define CLEAR_GPIO(pin) clear_gpio(pin)
4920 +#define TOGGLE_GPIO(pin) toggle_gpio(pin)
4921 +#endif // _LANGUAGE_ASSEMBLY
4922 +
4923 +#endif //__IDT_RC32365_GPIO_V_H__
4924 +
4925 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h
4926 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365.h  1970-01-01 01:00:00.000000000 +0100
4927 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h     2006-06-18 12:44:28.000000000 +0200
4928 @@ -0,0 +1,160 @@
4929 +/**************************************************************************
4930 + *
4931 + *  BRIEF MODULE DESCRIPTION
4932 + *   Definitions for IDT RC32365 CPU.
4933 + *
4934 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4935 + *
4936 + *  This program is free software; you can redistribute  it and/or modify it
4937 + *  under  the terms of  the GNU General  Public License as published by the
4938 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4939 + *  option) any later version.
4940 + *
4941 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4942 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4943 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4944 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4945 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4946 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4947 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4948 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4949 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4950 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4951 + *
4952 + *  You should have received a copy of the  GNU General Public License along
4953 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4954 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4955 + *
4956 + *
4957 + **************************************************************************
4958 + * May 2004 P. Sadik.
4959 + *
4960 + * Initial Release
4961 + *
4962 + *
4963 + *
4964 + **************************************************************************
4965 + */
4966 +
4967 +#ifndef __IDT_RC32365_H__
4968 +#define __IDT_RC32365_H__
4969 +
4970 +extern unsigned int cedar_za;
4971 +
4972 +/* Base address of internal registers */
4973 +#define RC32365_REG_BASE   0x18000000
4974 +
4975 +/* System ID Registers */
4976 +#define CPU_SYSID          (RC32365_REG_BASE + 0x00018)
4977 +#define CPU_DEVTYPE        (RC32365_REG_BASE + 0x0001c)
4978 +
4979 +/* Reset Controller */
4980 +#define RESET_CNTL         (RC32365_REG_BASE + 0x08000)
4981 +#define BOOT_VECTOR        (RC32365_REG_BASE + 0x08004)
4982 +
4983 +/* Device Controller */
4984 +#define DEV0_BASE          (RC32365_REG_BASE + 0x10000)
4985 +#define DEV0_MASK          (RC32365_REG_BASE + 0x10004)
4986 +#define DEV0_CNTL          (RC32365_REG_BASE + 0x10008)
4987 +#define DEV0_TIMING        (RC32365_REG_BASE + 0x1000c)
4988 +#define DEV_REG_OFFSET     0x10
4989 +
4990 +/* SDRAM Controller */
4991 +#define SDRAM0_BASE        (RC32365_REG_BASE + 0x18000)
4992 +#define SDRAM0_MASK        (RC32365_REG_BASE + 0x18004)
4993 +#define SDRAM1_BASE        (RC32365_REG_BASE + 0x18008)
4994 +#define SDRAM1_MASK        (RC32365_REG_BASE + 0x1800c)
4995 +#define SDRAM_CNTL         (RC32365_REG_BASE + 0x18010)
4996 +
4997 +/* Counters/Timers */
4998 +#define TIMER0_COUNT       (RC32365_REG_BASE + 0x20000)
4999 +#define TIMER0_COMPARE     (RC32365_REG_BASE + 0x20004)
5000 +#define TIMER0_CNTL        (RC32365_REG_BASE + 0x20008)
5001 +#define TIMER0_SELECT      (RC32365_REG_BASE + 0x2000c)
5002 +#define TIMER_REG_OFFSET   0x10
5003 +
5004 +/* System Integrity */
5005 +
5006 +/* Interrupt Controller */
5007 +#define IC_GROUP0_PEND     (RC32365_REG_BASE + 0x30000)
5008 +#define IC_GROUP0_TEST     (RC32365_REG_BASE + 0x30004)
5009 +#define IC_GROUP0_MASK     (RC32365_REG_BASE + 0x30008)
5010 +#define IC_GROUP_OFFSET    0x0c
5011 +
5012 +#define NUM_INTR_GROUPS    5
5013 +/*
5014 + * The IRQ mapping is as follows:
5015 + *
5016 + *    IRQ         Mapped To
5017 + *    ---     -------------------
5018 + *     0      SW0  (IP0) SW0 intr
5019 + *     1      SW1  (IP1) SW1 intr
5020 + *     -      Int0 (IP2) mapped to GROUP0_IRQ_BASE
5021 + *     -      Int1 (IP3) mapped to GROUP1_IRQ_BASE
5022 + *     -      Int2 (IP4) mapped to GROUP2_IRQ_BASE
5023 + *     -      Int3 (IP5) mapped to GROUP3_IRQ_BASE
5024 + *     -      Int4 (IP6) mapped to GROUP4_IRQ_BASE
5025 + *     7      Int5 (IP7) CP0 Timer
5026 + *
5027 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
5028 + * internally on the RC32365 is routed to the Expansion
5029 + * Interrupt Controller.
5030 + */
5031 +#define MIPS_CPU_TIMER_IRQ 7
5032 +
5033 +#define GROUP0_IRQ_BASE  8                      // Counter/Timers, UCW
5034 +#define GROUP1_IRQ_BASE  (GROUP0_IRQ_BASE + 32) // DMA
5035 +#define GROUP2_IRQ_BASE  (GROUP1_IRQ_BASE + 32) // RNG, SEC
5036 +#define GROUP3_IRQ_BASE  (GROUP2_IRQ_BASE + 32) // Eth, PCI, UARTs
5037 +#define GROUP4_IRQ_BASE  (GROUP3_IRQ_BASE + 32) // GPIO
5038 +
5039 +#define RC32365_NR_IRQS  (GROUP4_IRQ_BASE + 32)
5040 +
5041 +/* DMA - see rc32365_dma.h for full list of registers */
5042 +
5043 +#define RC32365_DMA_BASE (RC32365_REG_BASE + 0x38000)
5044 +#define DMA_CHAN_OFFSET  0x14
5045 +
5046 +/* GPIO Controller */
5047 +#define idt_gpio              ((volatile GPIO_t) GPIO0_VirtualAddress)
5048 +
5049 +/* 16550 UARTs */
5050 +#ifdef __MIPSEB__
5051 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50003)
5052 +#else
5053 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50000)
5054 +#endif
5055 +#define RC32300_UART0_IRQ  (GROUP3_IRQ_BASE + 0)
5056 +
5057 +/* Ethernet - see rc32365_eth.h for full list of registers */
5058 +
5059 +#define RC32365_ETH_BASE   (RC32365_REG_BASE + 0x58000)
5060 +
5061 +#define IDT_CLOCK_MULT     2
5062 +
5063 +/* FLASH (device 1) */
5064 +#define FLASH_BASE         0x08000000
5065 +#define FLASH_SIZE         0x00800000
5066 +
5067 +/* LCD 4-digit display (device 2) */
5068 +#define LCD_DIGIT0         0x0C000003
5069 +#define LCD_DIGIT1         0x0C000002
5070 +#define LCD_DIGIT2         0x0C000001
5071 +#define LCD_DIGIT3         0x0C000000
5072 +
5073 +/* RTC (DS1553) (device 2) */
5074 +#define RTC_BASE           0x0c800000
5075 +/* NVRAM */
5076 +#define NVRAM_BASE         RTC_BASE
5077 +#define NVRAM_ENVSIZE_OFF  4
5078 +#define NVRAM_ENVSTART_OFF 32
5079 +
5080 +/* Interrupts routed on 79EB365 board */
5081 +#define RC32365_PCI_INTA_IRQ (GROUP4_IRQ_BASE +  8)
5082 +#define RC32365_PCI_INTB_IRQ (GROUP4_IRQ_BASE +  9)
5083 +#define RC32365_PCI_INTC_IRQ (GROUP4_IRQ_BASE + 10)
5084 +#define RC32365_PCI_INTD_IRQ (GROUP4_IRQ_BASE + 11)
5085 +
5086 +#define RAM_SIZE          (32 * 1024 * 1024)
5087 +
5088 +#endif //__IDT_RC32365_H__
5089 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h
5090 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci.h      1970-01-01 01:00:00.000000000 +0100
5091 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 2006-06-18 12:44:28.000000000 +0200
5092 @@ -0,0 +1,515 @@
5093 +/**************************************************************************
5094 + *
5095 + *  BRIEF MODULE DESCRIPTION
5096 + *   Datatype declaration for IDT 79EB365/336 PCI
5097 + *
5098 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
5099 + *
5100 + *  This program is free software; you can redistribute  it and/or modify it
5101 + *  under  the terms of  the GNU General  Public License as published by the
5102 + *  Free Software Foundation;  either version 2 of the  License, or (at your
5103 + *  option) any later version.
5104 + *
5105 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
5106 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
5107 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
5108 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
5109 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5110 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
5111 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5112 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
5113 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5114 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5115 + *
5116 + *  You should have received a copy of the  GNU General Public License along
5117 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
5118 + *  675 Mass Ave, Cambridge, MA 02139, USA.
5119 + *
5120 + *
5121 + **************************************************************************
5122 + * May 2004 P. Sadik.
5123 + *
5124 + * Initial Release
5125 + *
5126 + *
5127 + *
5128 + **************************************************************************
5129 + */
5130 +
5131 +#ifndef __IDT_RC32365_PCI_H__
5132 +#define __IDT_RC32365_PCI_H__
5133 +
5134 +enum
5135 +{
5136 +       PCI0_PhysicalAddress    = 0x18068000,
5137 +       PCI_PhysicalAddress     = PCI0_PhysicalAddress,
5138 +
5139 +       PCI0_VirtualAddress     = 0xb8068000,
5140 +       PCI_VirtualAddress      = PCI0_VirtualAddress,
5141 +} ;
5142 +
5143 +enum
5144 +{
5145 +       PCI_LbaCount    = 4,            // Local base addresses.
5146 +} ;
5147 +
5148 +typedef struct
5149 +{
5150 +       u32     a ;             // Address.
5151 +       u32     c ;             // Control.
5152 +       u32     m ;             // mapping.
5153 +} PCI_Map_s ;
5154 +
5155 +typedef struct
5156 +{
5157 +       u32             pcic ;
5158 +       u32             pcis ;
5159 +       u32             pcism ;
5160 +       u32             pcicfga ;
5161 +       u32             pcicfgd ;
5162 +       PCI_Map_s       pcilba [PCI_LbaCount] ;
5163 +       u32             pcidac ;
5164 +       u32             pcidas ;
5165 +       u32             pcidasm ;
5166 +       u32             pcidad ;
5167 +       u32             pcidma8c ;
5168 +       u32             pcidma9c ;
5169 +       u32             pcitc ;
5170 +} volatile *PCI_t ;
5171 +
5172 +// PCI messaging unit.
5173 +enum
5174 +{
5175 +       PCIM_Count      = 2,
5176 +} ;
5177 +typedef struct
5178 +{
5179 +       u32             pciim [PCIM_Count] ;
5180 +       u32             pciom [PCIM_Count] ;
5181 +       u32             pciid ;
5182 +       u32             pciiic ;
5183 +       u32             pciiim ;
5184 +       u32             pciiod ;
5185 +       u32             pciioic ;
5186 +       u32             pciioim ;
5187 +} volatile *PCIM_t ;
5188 +
5189 +/*******************************************************************************
5190 + *
5191 + * PCI Control Register
5192 + *
5193 + ******************************************************************************/
5194 +enum
5195 +{
5196 +       PCIC_en_b       = 0,
5197 +       PCIC_en_m       = 0x00000001,
5198 +       PCIC_tnr_b      = 1,
5199 +       PCIC_tnr_m      = 0x00000002,
5200 +       PCIC_sce_b      = 2,
5201 +       PCIC_sce_m      = 0x00000004,
5202 +       PCIC_ien_b      = 3,
5203 +       PCIC_ien_m      = 0x00000008,
5204 +       PCIC_aaa_b      = 4,
5205 +       PCIC_aaa_m      = 0x00000010,
5206 +       PCIC_eap_b      = 5,
5207 +       PCIC_eap_m      = 0x00000020,
5208 +       PCIC_pcim_b     = 6,
5209 +       PCIC_pcim_m     = 0x000001c0,
5210 +               PCIC_pcim_disabled_v    = 0,
5211 +               PCIC_pcim_tnr_v         = 1,    // Satellite - target not ready
5212 +               PCIC_pcim_suspend_v     = 2,    // Satellite - suspended CPU.
5213 +               PCIC_pcim_extern_v      = 3,    // Host - external arbiter.
5214 +               PCIC_pcim_fixed_v       = 4,    // Host - fixed priority arb.
5215 +               PCIC_pcim_roundrobin_v  = 5,    // Host - round robin priority.
5216 +               PCIC_pcim_reserved6_v   = 6,
5217 +               PCIC_pcim_reserved7_v   = 7,
5218 +       PCIC_igm_b      = 9,
5219 +       PCIC_igm_m      = 0x00000200,
5220 +} ;
5221 +
5222 +/*******************************************************************************
5223 + *
5224 + * PCI Status Register
5225 + *
5226 + ******************************************************************************/
5227 +enum {
5228 +       PCIS_eed_b      = 0,
5229 +       PCIS_eed_m      = 0x00000001,
5230 +       PCIS_wr_b       = 1,
5231 +       PCIS_wr_m       = 0x00000002,
5232 +       PCIS_nmi_b      = 2,
5233 +       PCIS_nmi_m      = 0x00000004,
5234 +       PCIS_ii_b       = 3,
5235 +       PCIS_ii_m       = 0x00000008,
5236 +       PCIS_cwe_b      = 4,
5237 +       PCIS_cwe_m      = 0x00000010,
5238 +       PCIS_cre_b      = 5,
5239 +       PCIS_cre_m      = 0x00000020,
5240 +       PCIS_mdpe_b     = 6,
5241 +       PCIS_mdpe_m     = 0x00000040,
5242 +       PCIS_sta_b      = 7,
5243 +       PCIS_sta_m      = 0x00000080,
5244 +       PCIS_rta_b      = 8,
5245 +       PCIS_rta_m      = 0x00000100,
5246 +       PCIS_rma_b      = 9,
5247 +       PCIS_rma_m      = 0x00000200,
5248 +       PCIS_sse_b      = 10,
5249 +       PCIS_sse_m      = 0x00000400,
5250 +       PCIS_ose_b      = 11,
5251 +       PCIS_ose_m      = 0x00000800,
5252 +       PCIS_pe_b       = 12,
5253 +       PCIS_pe_m       = 0x00001000,
5254 +       PCIS_tae_b      = 13,
5255 +       PCIS_tae_m      = 0x00002000,
5256 +       PCIS_rle_b      = 14,
5257 +       PCIS_rle_m      = 0x00004000,
5258 +       PCIS_bme_b      = 15,
5259 +       PCIS_bme_m      = 0x00008000,
5260 +       PCIS_prd_b      = 16,
5261 +       PCIS_prd_m      = 0x00010000,
5262 +       PCIS_rip_b      = 17,
5263 +       PCIS_rip_m      = 0x00020000,
5264 +} ;
5265 +
5266 +/*******************************************************************************
5267 + *
5268 + * PCI Status Mask Register
5269 + *
5270 + ******************************************************************************/
5271 +enum {
5272 +       PCISM_eed_b             = 0,
5273 +       PCISM_eed_m             = 0x00000001,
5274 +       PCISM_wr_b              = 1,
5275 +       PCISM_wr_m              = 0x00000002,
5276 +       PCISM_nmi_b             = 2,
5277 +       PCISM_nmi_m             = 0x00000004,
5278 +       PCISM_ii_b              = 3,
5279 +       PCISM_ii_m              = 0x00000008,
5280 +       PCISM_cwe_b             = 4,
5281 +       PCISM_cwe_m             = 0x00000010,
5282 +       PCISM_cre_b             = 5,
5283 +       PCISM_cre_m             = 0x00000020,
5284 +       PCISM_mdpe_b            = 6,
5285 +       PCISM_mdpe_m            = 0x00000040,
5286 +       PCISM_sta_b             = 7,
5287 +       PCISM_sta_m             = 0x00000080,
5288 +       PCISM_rta_b             = 8,
5289 +       PCISM_rta_m             = 0x00000100,
5290 +       PCISM_rma_b             = 9,
5291 +       PCISM_rma_m             = 0x00000200,
5292 +       PCISM_sse_b             = 10,
5293 +       PCISM_sse_m             = 0x00000400,
5294 +       PCISM_ose_b             = 11,
5295 +       PCISM_ose_m             = 0x00000800,
5296 +       PCISM_pe_b              = 12,
5297 +       PCISM_pe_m              = 0x00001000,
5298 +       PCISM_tae_b             = 13,
5299 +       PCISM_tae_m             = 0x00002000,
5300 +       PCISM_rle_b             = 14,
5301 +       PCISM_rle_m             = 0x00004000,
5302 +       PCISM_bme_b             = 15,
5303 +       PCISM_bme_m             = 0x00008000,
5304 +       PCISM_prd_b             = 16,
5305 +       PCISM_prd_m             = 0x00010000,
5306 +       PCISM_rip_b             = 17,
5307 +       PCISM_rip_m             = 0x00020000,
5308 +} ;
5309 +
5310 +/*******************************************************************************
5311 + *
5312 + * PCI Configuration Address Register
5313 + *
5314 + ******************************************************************************/
5315 +enum {
5316 +       PCICFGA_reg_b           = 2,
5317 +       PCICFGA_reg_m           = 0x000000fc,
5318 +       PCICFGA_reg_id_v        = 0x00>>2, //use PCFGID_
5319 +       PCICFGA_reg_04_v        = 0x04>>2, //use PCFG04_
5320 +       PCICFGA_reg_08_v        = 0x08>>2, //use PCFG08_
5321 +       PCICFGA_reg_0C_v        = 0x0C>>2, //use PCFG0C_
5322 +       PCICFGA_reg_pba0_v      = 0x10>>2, //use PCIPBA_
5323 +       PCICFGA_reg_pba1_v      = 0x14>>2, //use PCIPBA_
5324 +       PCICFGA_reg_pba2_v      = 0x18>>2, //use PCIPBA_
5325 +       PCICFGA_reg_pba3_v      = 0x1c>>2, //use PCIPBA_
5326 +       PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
5327 +       PCICFGA_reg_3C_v        = 0x3C>>2, //use PCFG3C_
5328 +       PCICFGA_reg_pba0c_v     = 0x44>>2, //use PCIPBAC_
5329 +       PCICFGA_reg_pba0m_v     = 0x48>>2,
5330 +       PCICFGA_reg_pba1c_v     = 0x4c>>2, //use PCIPBAC_
5331 +       PCICFGA_reg_pba1m_v     = 0x50>>2,
5332 +       PCICFGA_reg_pba2c_v     = 0x54>>2, //use PCIPBAC_
5333 +       PCICFGA_reg_pba2m_v     = 0x58>>2,
5334 +       PCICFGA_reg_pba3c_v     = 0x5c>>2, //use PCIPBAC_
5335 +       PCICFGA_reg_pba3m_v     = 0x60>>2,
5336 +       PCICFGA_reg_pmgt_v      = 0x64>>2,
5337 +       PCICFGA_func_b          = 8,
5338 +       PCICFGA_func_m          = 0x00000700,
5339 +       PCICFGA_dev_b           = 11,
5340 +       PCICFGA_dev_m           = 0x0000f800,
5341 +       PCICFGA_dev_internal_v  = 0,
5342 +       PCICFGA_bus_b           = 16,
5343 +       PCICFGA_bus_m           = 0x00ff0000,
5344 +       PCICFGA_bus_type0_v     = 0,    //local bus
5345 +       PCICFGA_en_b            = 31,           // read only
5346 +       PCICFGA_en_m            = 0x80000000,
5347 +} ;
5348 +
5349 +enum {
5350 +       PCFGID_vendor_b         = 0,
5351 +       PCFGID_vendor_m         = 0x0000ffff,
5352 +       PCFGID_vendor_IDT_v             = 0x111d,
5353 +       PCFGID_device_b         = 16,
5354 +       PCFGID_device_m         = 0xffff0000,
5355 +       PCFGID_device_Acaciade_v        = 0x0207,
5356 +
5357 +       PCFG04_command_ioena_b          = 1,
5358 +       PCFG04_command_ioena_m          = 0x00000001,
5359 +       PCFG04_command_memena_b         = 2,
5360 +       PCFG04_command_memena_m         = 0x00000002,
5361 +       PCFG04_command_bmena_b          = 3,
5362 +       PCFG04_command_bmena_m          = 0x00000004,
5363 +       PCFG04_command_mwinv_b          = 5,
5364 +       PCFG04_command_mwinv_m          = 0x00000010,
5365 +       PCFG04_command_parena_b         = 7,
5366 +       PCFG04_command_parena_m         = 0x00000040,
5367 +       PCFG04_command_serrena_b        = 9,
5368 +       PCFG04_command_serrena_m        = 0x00000100,
5369 +       PCFG04_command_fastbbena_b      = 10,
5370 +       PCFG04_command_fastbbena_m      = 0x00000200,
5371 +       PCFG04_status_b                 = 16,
5372 +       PCFG04_status_m                 = 0xffff0000,
5373 +       PCFG04_status_66MHz_b           = 21,   // 66 MHz enable
5374 +       PCFG04_status_66MHz_m           = 0x00200000,
5375 +       PCFG04_status_fbb_b             = 23,
5376 +       PCFG04_status_fbb_m             = 0x00800000,
5377 +       PCFG04_status_mdpe_b            = 24,
5378 +       PCFG04_status_mdpe_m            = 0x01000000,
5379 +       PCFG04_status_dst_b             = 25,
5380 +       PCFG04_status_dst_m             = 0x06000000,
5381 +       PCFG04_status_sta_b             = 27,
5382 +       PCFG04_status_sta_m             = 0x08000000,
5383 +       PCFG04_status_rta_b             = 28,
5384 +       PCFG04_status_rta_m             = 0x10000000,
5385 +       PCFG04_status_rma_b             = 29,
5386 +       PCFG04_status_rma_m             = 0x20000000,
5387 +       PCFG04_status_sse_b             = 30,
5388 +       PCFG04_status_sse_m             = 0x40000000,
5389 +       PCFG04_status_pe_b              = 31,
5390 +       PCFG04_status_pe_m              = 0x40000000,
5391 +
5392 +       PCFG08_revId_b                  = 0,
5393 +       PCFG08_revId_m                  = 0x000000ff,
5394 +       PCFG08_classCode_b              = 0,
5395 +       PCFG08_classCode_m              = 0xffffff00,
5396 +       PCFG08_classCode_bridge_v       = 06,
5397 +       PCFG08_classCode_proc_v         = 0x0b3000, // processor-MIPS
5398 +       PCFG0C_cacheline_b              = 0,
5399 +       PCFG0C_cacheline_m              = 0x000000ff,
5400 +       PCFG0C_masterLatency_b          = 8,
5401 +       PCFG0C_masterLatency_m          = 0x0000ff00,
5402 +       PCFG0C_headerType_b             = 16,
5403 +       PCFG0C_headerType_m             = 0x00ff0000,
5404 +       PCFG0C_bist_b                   = 24,
5405 +       PCFG0C_bist_m                   = 0xff000000,
5406 +
5407 +       PCIPBA_msi_b                    = 0,
5408 +       PCIPBA_msi_m                    = 0x00000001,
5409 +       PCIPBA_p_b                      = 3,
5410 +       PCIPBA_p_m                      = 0x00000004,
5411 +       PCIPBA_baddr_b                  = 8,
5412 +       PCIPBA_baddr_m                  = 0xffffff00,
5413 +
5414 +       PCFGSS_vendorId_b               = 0,
5415 +       PCFGSS_vendorId_m               = 0x0000ffff,
5416 +       PCFGSS_id_b                     = 16,
5417 +       PCFGSS_id_m                     = 0xffff0000,
5418 +
5419 +       PCFG3C_interruptLine_b          = 0,
5420 +       PCFG3C_interruptLine_m          = 0x000000ff,
5421 +       PCFG3C_interruptPin_b           = 8,
5422 +       PCFG3C_interruptPin_m           = 0x0000ff00,
5423 +       PCFG3C_minGrant_b               = 16,
5424 +       PCFG3C_minGrant_m               = 0x00ff0000,
5425 +       PCFG3C_maxLat_b                 = 24,
5426 +       PCFG3C_maxLat_m                 = 0xff000000,
5427 +
5428 +       PCIPBAC_msi_b                   = 0,
5429 +       PCIPBAC_msi_m                   = 0x00000001,
5430 +       PCIPBAC_p_b                     = 1,
5431 +       PCIPBAC_p_m                     = 0x00000002,
5432 +       PCIPBAC_size_b                  = 2,
5433 +       PCIPBAC_size_m                  = 0x0000007c,
5434 +       PCIPBAC_sb_b                    = 7,
5435 +       PCIPBAC_sb_m                    = 0x00000080,
5436 +       PCIPBAC_pp_b                    = 8,
5437 +       PCIPBAC_pp_m                    = 0x00000100,
5438 +       PCIPBAC_mr_b                    = 9,
5439 +       PCIPBAC_mr_m                    = 0x00000600,
5440 +       PCIPBAC_mr_read_v       =0,     //no prefetching
5441 +       PCIPBAC_mr_readLine_v   =1,
5442 +       PCIPBAC_mr_readMult_v   =2,
5443 +       PCIPBAC_mrl_b                   = 11,
5444 +       PCIPBAC_mrl_m                   = 0x00000800,
5445 +       PCIPBAC_mrm_b                   = 12,
5446 +       PCIPBAC_mrm_m                   = 0x00001000,
5447 +       PCIPBAC_trp_b                   = 13,
5448 +       PCIPBAC_trp_m                   = 0x00002000,
5449 +
5450 +       PCFG40_trdyTimeout_b            = 0,
5451 +       PCFG40_trdyTimeout_m            = 0x000000ff,
5452 +       PCFG40_retryLim_b               = 8,
5453 +       PCFG40_retryLim_m               = 0x0000ff00,
5454 +};
5455 +
5456 +/*******************************************************************************
5457 + *
5458 + * PCI Local Base Address [0|1|2|3] Register
5459 + *
5460 + ******************************************************************************/
5461 +enum {
5462 +       PCILBA_baddr_b          = 0,            // In PCI_t -> pcilba [] .a
5463 +       PCILBA_baddr_m          = 0xffffff00,
5464 +} ;
5465 +/*******************************************************************************
5466 + *
5467 + * PCI Local Base Address Control Register
5468 + *
5469 + ******************************************************************************/
5470 +enum {
5471 +       PCILBAC_msi_b           = 0,            // In pPci->pcilba[i].c
5472 +       PCILBAC_msi_m           = 0x00000001,
5473 +       PCILBAC_msi_mem_v       = 0,
5474 +       PCILBAC_msi_io_v        = 1,
5475 +       PCILBAC_size_b          = 2,    // In pPci->pcilba[i].c
5476 +       PCILBAC_size_m          = 0x0000007c,
5477 +       PCILBAC_sb_b            = 7,    // In pPci->pcilba[i].c
5478 +       PCILBAC_sb_m            = 0x00000080,
5479 +       PCILBAC_rt_b            = 8,    // In pPci->pcilba[i].c
5480 +       PCILBAC_rt_m            = 0x00000100,
5481 +       PCILBAC_rt_noprefetch_v = 0, // mem read
5482 +       PCILBAC_rt_prefetch_v   = 1, // mem readline
5483 +} ;
5484 +
5485 +/*******************************************************************************
5486 + *
5487 + * PCI Local Base Address [0|1|2|3] Mapping Register
5488 + *
5489 + ******************************************************************************/
5490 +enum {
5491 +       PCILBAM_maddr_b         = 8,
5492 +       PCILBAM_maddr_m         = 0xffffff00,
5493 +} ;
5494 +
5495 +/*******************************************************************************
5496 + *
5497 + * PCI Decoupled Access Control Register
5498 + *
5499 + ******************************************************************************/
5500 +enum {
5501 +       PCIDAC_den_b            = 0,
5502 +       PCIDAC_den_m            = 0x00000001,
5503 +} ;
5504 +
5505 +/*******************************************************************************
5506 + *
5507 + * PCI Decoupled Access Status Register
5508 + *
5509 + ******************************************************************************/
5510 +enum {
5511 +       PCIDAS_d_b      = 0,
5512 +       PCIDAS_d_m      = 0x00000001,
5513 +       PCIDAS_b_b      = 1,
5514 +       PCIDAS_b_m      = 0x00000002,
5515 +       PCIDAS_e_b      = 2,
5516 +       PCIDAS_e_m      = 0x00000004,
5517 +       PCIDAS_ofe_b    = 3,
5518 +       PCIDAS_ofe_m    = 0x00000008,
5519 +       PCIDAS_off_b    = 4,
5520 +       PCIDAS_off_m    = 0x00000010,
5521 +       PCIDAS_ife_b    = 5,
5522 +       PCIDAS_ife_m    = 0x00000020,
5523 +       PCIDAS_iff_b    = 6,
5524 +       PCIDAS_iff_m    = 0x00000040,
5525 +} ;
5526 +
5527 +/*******************************************************************************
5528 + *
5529 + * PCI DMA Channel 8 Configuration Register
5530 + *
5531 + ******************************************************************************/
5532 +enum
5533 +{
5534 +       PCIDMA8C_mbs_b  = 0,            // Maximum Burst Size.
5535 +       PCIDMA8C_mbs_m  = 0x00000fff,   // { pcidma8c }
5536 +       PCIDMA8C_our_b  = 12,           // Optimize Unaligned Burst Reads.
5537 +       PCIDMA8C_our_m  = 0x00001000,   // { pcidma8c }
5538 +} ;
5539 +
5540 +/*******************************************************************************
5541 + *
5542 + * PCI DMA Channel 9 Configuration Register
5543 + *
5544 + ******************************************************************************/
5545 +enum
5546 +{
5547 +       PCIDMA9C_mbs_b  = 0,            // Maximum Burst Size.
5548 +       PCIDMA9C_mbs_m  = 0x00000fff, // { pcidma9c }
5549 +} ;
5550 +
5551 +/*******************************************************************************
5552 + *
5553 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
5554 + *
5555 + ******************************************************************************/
5556 +enum {
5557 +       PCIDMAD_pt_b            = 22,           // in DEVCMD field (descriptor)
5558 +       PCIDMAD_pt_m            = 0x00c00000,   // preferred transaction field
5559 +       // These are for reads (DMA channel 8)
5560 +       PCIDMAD_devcmd_mr_v     = 0,    //memory read
5561 +       PCIDMAD_devcmd_mrl_v    = 1,    //memory read line
5562 +       PCIDMAD_devcmd_mrm_v    = 2,    //memory read multiple
5563 +       PCIDMAD_devcmd_ior_v    = 3,    //I/O read
5564 +       // These are for writes (DMA channel 9)
5565 +       PCIDMAD_devcmd_mw_v     = 0,    //memory write
5566 +       PCIDMAD_devcmd_mwi_v    = 1,    //memory write invalidate
5567 +       PCIDMAD_devcmd_iow_v    = 3,    //I/O write
5568 +
5569 +       // Swap byte field applies to both DMA channel 8 and 9
5570 +       PCIDMAD_sb_b            = 24,           // in DEVCMD field (descriptor)
5571 +       PCIDMAD_sb_m            = 0x01000000,   // swap byte field
5572 +} ;
5573 +
5574 +
5575 +/*******************************************************************************
5576 + *
5577 + * PCI Target Control Register
5578 + *
5579 + ******************************************************************************/
5580 +enum
5581 +{
5582 +       PCITC_rtimer_b          = 0,            // In PCITC_t -> pcitc
5583 +       PCITC_rtimer_m          = 0x000000ff,
5584 +       PCITC_dtimer_b          = 8,            // In PCITC_t -> pcitc
5585 +       PCITC_dtimer_m          = 0x0000ff00,
5586 +       PCITC_rdr_b             = 18,           // In PCITC_t -> pcitc
5587 +       PCITC_rdr_m             = 0x00040000,
5588 +       PCITC_ddt_b             = 19,           // In PCITC_t -> pcitc
5589 +       PCITC_ddt_m             = 0x00080000,
5590 +} ;
5591 +/*******************************************************************************
5592 + *
5593 + * PCI messaging unit [applies to both inbound and outbound registers ]
5594 + *
5595 + ******************************************************************************/
5596 +enum
5597 +{
5598 +       PCIM_m0_b       = 0,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5599 +       PCIM_m0_m       = 0x00000001,   // inbound or outbound message 0
5600 +       PCIM_m1_b       = 1,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5601 +       PCIM_m1_m       = 0x00000002,   // inbound or outbound message 1
5602 +       PCIM_db_b       = 2,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5603 +       PCIM_db_m       = 0x00000004,   // inbound or outbound doorbell
5604 +};
5605 +
5606 +
5607 +#endif // __IDT_RC32365_PCI_H__
5608 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h
5609 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h    1970-01-01 01:00:00.000000000 +0100
5610 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h       2006-06-18 12:44:28.000000000 +0200
5611 @@ -0,0 +1,217 @@
5612 +/**************************************************************************
5613 + *
5614 + *  BRIEF MODULE DESCRIPTION
5615 + *   PCI header values for IDT 79EB365/336
5616 + *
5617 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
5618 + *
5619 + *  This program is free software; you can redistribute  it and/or modify it
5620 + *  under  the terms of  the GNU General  Public License as published by the
5621 + *  Free Software Foundation;  either version 2 of the  License, or (at your
5622 + *  option) any later version.
5623 + *
5624 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
5625 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
5626 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
5627 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
5628 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5629 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
5630 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5631 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
5632 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5633 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5634 + *
5635 + *  You should have received a copy of the  GNU General Public License along
5636 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
5637 + *  675 Mass Ave, Cambridge, MA 02139, USA.
5638 + *
5639 + *
5640 + **************************************************************************
5641 + * May 2004 P. Sadik.
5642 + *
5643 + * Initial Release
5644 + *
5645 + *
5646 + *
5647 + **************************************************************************
5648 + */
5649 +
5650 +#ifndef __IDT_RC32365_PCI_V_H__
5651 +#define __IDT_RC32365_PCI_V_H__
5652 +
5653 +
5654 +#define PCI_MSG_VirtualAddress 0xB806C010
5655 +#define rc32365_pci ((volatile PCI_t) PCI0_VirtualAddress)
5656 +#define rc32365_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
5657 +
5658 +#define PCIM_SHFT              0x6
5659 +#define PCIM_BIT_LEN           0x7
5660 +#define PCIM_H_EA              0x3
5661 +#define PCIM_H_IA_FIX          0x4
5662 +#define PCIM_H_IA_RR           0x5
5663 +
5664 +#define PCI_ADDR_START         0x50000000
5665 +
5666 +#define CPUTOPCI_MEM_WIN       0x02000000
5667 +#define CPUTOPCI_IO_WIN                0x00100000
5668 +#define PCILBA_SIZE_SHFT       2
5669 +#define PCILBA_SIZE_MASK       0x1F
5670 +#define SIZE_256MB             0x1C
5671 +#define SIZE_128MB             0x1B
5672 +#define SIZE_64MB               0x1A
5673 +#define SIZE_32MB              0x19
5674 +#define SIZE_16MB               0x18
5675 +#define SIZE_4MB               0x16
5676 +#define SIZE_2MB               0x15
5677 +#define SIZE_1MB               0x14
5678 +#define CEDAR_CONFIG0_ADDR     0x80000000
5679 +#define CEDAR_CONFIG1_ADDR     0x80000004
5680 +#define CEDAR_CONFIG2_ADDR     0x80000008
5681 +#define CEDAR_CONFIG3_ADDR     0x8000000C
5682 +#define CEDAR_CONFIG4_ADDR     0x80000010
5683 +#define CEDAR_CONFIG5_ADDR     0x80000014
5684 +#define CEDAR_CONFIG6_ADDR     0x80000018
5685 +#define CEDAR_CONFIG7_ADDR     0x8000001C
5686 +#define CEDAR_CONFIG8_ADDR     0x80000020
5687 +#define CEDAR_CONFIG9_ADDR     0x80000024
5688 +#define CEDAR_CONFIG10_ADDR    0x80000028
5689 +#define CEDAR_CONFIG11_ADDR    0x8000002C
5690 +#define CEDAR_CONFIG12_ADDR    0x80000030
5691 +#define CEDAR_CONFIG13_ADDR    0x80000034
5692 +#define CEDAR_CONFIG14_ADDR    0x80000038
5693 +#define CEDAR_CONFIG15_ADDR    0x8000003C
5694 +#define CEDAR_CONFIG16_ADDR    0x80000040
5695 +#define CEDAR_CONFIG17_ADDR    0x80000044
5696 +#define CEDAR_CONFIG18_ADDR    0x80000048
5697 +#define CEDAR_CONFIG19_ADDR    0x8000004C
5698 +#define CEDAR_CONFIG20_ADDR    0x80000050
5699 +#define CEDAR_CONFIG21_ADDR    0x80000054
5700 +#define CEDAR_CONFIG22_ADDR    0x80000058
5701 +#define CEDAR_CONFIG23_ADDR    0x8000005C
5702 +#define CEDAR_CONFIG24_ADDR    0x80000060
5703 +#define CEDAR_CONFIG25_ADDR    0x80000064
5704 +#define CEDAR_CMD             (PCFG04_command_ioena_m  | \
5705 +                               PCFG04_command_memena_m | \
5706 +                               PCFG04_command_bmena_m  | \
5707 +                               PCFG04_command_mwinv_m  | \
5708 +                               PCFG04_command_parena_m | \
5709 +                               PCFG04_command_serrena_m )
5710 +
5711 +#define CEDAR_STAT            (PCFG04_status_mdpe_m | \
5712 +                               PCFG04_status_sta_m  | \
5713 +                               PCFG04_status_rta_m  | \
5714 +                               PCFG04_status_rma_m  | \
5715 +                               PCFG04_status_sse_m  | \
5716 +                               PCFG04_status_pe_m)
5717 +
5718 +#define CEDAR_CNFG1          ((CEDAR_STAT << 16) | \
5719 +                                CEDAR_CMD)
5720 +
5721 +#define CEDAR_REVID            0
5722 +#define CEDAR_CLASS_CODE       0
5723 +#define CEDAR_CNFG2          ((CEDAR_CLASS_CODE << 8) | \
5724 +                               CEDAR_REVID)
5725 +
5726 +#define CEDAR_CACHE_LINE_SIZE  4
5727 +#define CEDAR_MASTER_LAT       0x3c
5728 +#define CEDAR_HEADER_TYPE      0
5729 +#define CEDAR_BIST             0
5730 +
5731 +#define CEDAR_CNFG3           ((CEDAR_BIST        << 24) | \
5732 +                              (CEDAR_HEADER_TYPE << 16) | \
5733 +                              (CEDAR_MASTER_LAT  <<  8) | \
5734 +                               CEDAR_CACHE_LINE_SIZE)
5735 +
5736 +#define CEDAR_BAR0             0x00000008 /* 128 MB Memory */
5737 +#define CEDAR_BAR1             0x18800001 /* 1 MB IO */
5738 +#define CEDAR_BAR2             0x18000001 /* 2 MB IO window for Cedar
5739 +                                             internal Registers */
5740 +#define CEDAR_BAR3             0x48000008 /* Spare 128 MB Memory */
5741 +
5742 +#define CEDAR_CNFG4            CEDAR_BAR0
5743 +#define CEDAR_CNFG5             CEDAR_BAR1
5744 +#define CEDAR_CNFG6            CEDAR_BAR2
5745 +#define CEDAR_CNFG7            CEDAR_BAR3
5746 +
5747 +#define CEDAR_SUBSYS_VENDOR_ID  0
5748 +#define CEDAR_SUBSYSTEM_ID     0
5749 +#define CEDAR_CNFG8            0
5750 +#define CEDAR_CNFG9            0
5751 +#define CEDAR_CNFG10           0
5752 +#define CEDAR_CNFG11         ((CEDAR_SUBSYS_VENDOR_ID << 16) | \
5753 +                               CEDAR_SUBSYSTEM_ID)
5754 +#define CEDAR_INT_LINE         1
5755 +#define CEDAR_INT_PIN          1
5756 +#define CEDAR_MIN_GNT          8
5757 +#define CEDAR_MAX_LAT          0x38
5758 +#define CEDAR_CNFG12           0
5759 +#define CEDAR_CNFG13           0
5760 +#define CEDAR_CNFG14           0
5761 +#define CEDAR_CNFG15         ((CEDAR_MAX_LAT << 24) | \
5762 +                              (CEDAR_MIN_GNT << 16) | \
5763 +                              (CEDAR_INT_PIN <<  8) | \
5764 +                               CEDAR_INT_LINE)
5765 +#define        CEDAR_RETRY_LIMIT       0x80
5766 +#define CEDAR_TRDY_LIMIT       0x80
5767 +#define CEDAR_CNFG16          ((CEDAR_RETRY_LIMIT << 8) | \
5768 +                               CEDAR_TRDY_LIMIT)
5769 +#define PCI_PBAxC_R            0x0
5770 +#define PCI_PBAxC_RL           0x1
5771 +#define PCI_PBAxC_RM           0x2
5772 +#define SIZE_SHFT              2
5773 +#ifdef __MIPSEB__
5774 +#define CEDAR_PBA0C           (((1 & 0x3) << PCIPBAC_mr_b) | \
5775 +                               PCIPBAC_pp_m | \
5776 +                               PCIPBAC_sb_m | \
5777 +                              (SIZE_128MB << SIZE_SHFT) | \
5778 +                               PCIPBAC_p_m)
5779 +#else
5780 +
5781 +#define CEDAR_PBA0C           (((1 & 0x3) << PCIPBAC_mr_b) | \
5782 +                               PCIPBAC_pp_m | \
5783 +                              (SIZE_128MB << SIZE_SHFT) | \
5784 +                               PCIPBAC_p_m)
5785 +#endif
5786 +#define CEDAR_CNFG17           CEDAR_PBA0C
5787 +#define CEDAR_PBA0M            0x0
5788 +#define CEDAR_CNFG18           CEDAR_PBA0M
5789 +
5790 +#ifdef __MIPSEB__
5791 +#define CEDAR_PBA1C          ((SIZE_1MB << SIZE_SHFT) | \
5792 +                               PCIPBAC_sb_m | \
5793 +                               PCIPBAC_msi_m)
5794 +#else
5795 +#define CEDAR_PBA1C          ((SIZE_1MB << SIZE_SHFT) | \
5796 +                               PCIPBAC_msi_m)
5797 +#endif
5798 +#define CEDAR_CNFG19           CEDAR_PBA1C
5799 +#define CEDAR_PBA1M            0x0
5800 +#define CEDAR_CNFG20           CEDAR_PBA1M
5801 +
5802 +#ifdef __MIPSEB__
5803 +#define CEDAR_PBA2C          ((SIZE_2MB << SIZE_SHFT) |  \
5804 +                               PCIPBAC_sb_m | \
5805 +                               PCIPBAC_msi_m)
5806 +#else
5807 +#define CEDAR_PBA2C          ((SIZE_2MB << SIZE_SHFT) |  \
5808 +                               PCIPBAC_msi_m)
5809 +#endif
5810 +
5811 +#define CEDAR_CNFG21           CEDAR_PBA2C
5812 +#define CEDAR_PBA2M            0x18000000
5813 +#define CEDAR_CNFG22           CEDAR_PBA2M
5814 +
5815 +#ifdef __MIPSEB__
5816 +#define CEDAR_PBA3C            PCIPBAC_sb_m
5817 +#else
5818 +#define CEDAR_PBA3C            0
5819 +#endif
5820 +
5821 +#define CEDAR_CNFG23           CEDAR_PBA3C
5822 +#define CEDAR_PBA3M            0
5823 +#define CEDAR_CNFG24           CEDAR_PBA3M
5824 +
5825 +#define        PCITC_DTIMER_VAL        8
5826 +#define PCITC_RTIMER_VAL       0x10
5827 +
5828 +#endif //__IDT_RC32365_PCI_V_H__
5829 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h
5830 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma.h      1970-01-01 01:00:00.000000000 +0100
5831 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 2006-06-18 12:44:28.000000000 +0200
5832 @@ -0,0 +1,205 @@
5833 +/**************************************************************************
5834 + *
5835 + *  BRIEF MODULE DESCRIPTION
5836 + *   DMA register definition
5837 + *
5838 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
5839 + *
5840 + *  This program is free software; you can redistribute  it and/or modify it
5841 + *  under  the terms of  the GNU General  Public License as published by the
5842 + *  Free Software Foundation;  either version 2 of the  License, or (at your
5843 + *  option) any later version.
5844 + *
5845 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
5846 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
5847 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
5848 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
5849 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5850 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
5851 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5852 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
5853 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5854 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5855 + *
5856 + *  You should have received a copy of the  GNU General Public License along
5857 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
5858 + *  675 Mass Ave, Cambridge, MA 02139, USA.
5859 + *
5860 + *
5861 + **************************************************************************
5862 + * May 2004 rkt, neb
5863 + *
5864 + * Initial Release
5865 + *
5866 + *
5867 + *
5868 + **************************************************************************
5869 + */
5870 +
5871 +#ifndef __IDT_DMA_H__
5872 +#define __IDT_DMA_H__
5873 +
5874 +enum
5875 +{
5876 +       DMA0_PhysicalAddress    = 0x18040000,
5877 +       DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
5878 +
5879 +       DMA0_VirtualAddress     = 0xb8040000,
5880 +       DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
5881 +} ;
5882 +
5883 +/*
5884 + * DMA descriptor (in physical memory).
5885 + */
5886 +
5887 +typedef struct DMAD_s
5888 +{
5889 +       u32                     control ;       // Control. use DMAD_*
5890 +       u32                     ca ;            // Current Address.
5891 +       u32                     devcs ;         // Device control and status.
5892 +       u32                     link ;          // Next descriptor in chain.
5893 +} volatile *DMAD_t ;
5894 +
5895 +enum
5896 +{
5897 +       DMAD_size               = sizeof (struct DMAD_s),
5898 +       DMAD_count_b            = 0,            // in DMAD_t -> control
5899 +       DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
5900 +       DMAD_ds_b               = 20,           // in DMAD_t -> control
5901 +       DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
5902 +               DMAD_ds_ethRcv0_v       = 0,
5903 +               DMAD_ds_ethXmt0_v       = 0,
5904 +               DMAD_ds_memToFifo_v     = 0,
5905 +               DMAD_ds_fifoToMem_v     = 0,
5906 +               DMAD_ds_pciToMem_v      = 0,
5907 +               DMAD_ds_memToPci_v      = 0,
5908 +
5909 +       DMAD_devcmd_b           = 22,           // in DMAD_t -> control
5910 +       DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
5911 +               DMAD_devcmd_byte_v      = 0,    //memory-to-memory
5912 +               DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
5913 +               DMAD_devcmd_word_v      = 2,    //memory-to-memory
5914 +               DMAD_devcmd_2words_v    = 3,    //memory-to-memory
5915 +               DMAD_devcmd_4words_v    = 4,    //memory-to-memory
5916 +               DMAD_devcmd_6words_v    = 5,    //memory-to-memory
5917 +               DMAD_devcmd_8words_v    = 6,    //memory-to-memory
5918 +               DMAD_devcmd_16words_v   = 7,    //memory-to-memory
5919 +       DMAD_cof_b              = 25,           // chain on finished
5920 +       DMAD_cof_m              = 0x02000000,   //
5921 +       DMAD_cod_b              = 26,           // chain on done
5922 +       DMAD_cod_m              = 0x04000000,   //
5923 +       DMAD_iof_b              = 27,           // interrupt on finished
5924 +       DMAD_iof_m              = 0x08000000,   //
5925 +       DMAD_iod_b              = 28,           // interrupt on done
5926 +       DMAD_iod_m              = 0x10000000,   //
5927 +       DMAD_t_b                = 29,           // terminated
5928 +       DMAD_t_m                = 0x20000000,   //
5929 +       DMAD_d_b                = 30,           // done
5930 +       DMAD_d_m                = 0x40000000,   //
5931 +       DMAD_f_b                = 31,           // finished
5932 +       DMAD_f_m                = 0x80000000,   //
5933 +} ;
5934 +
5935 +/*
5936 + * DMA register (within Internal Register Map).
5937 + */
5938 +
5939 +struct DMA_Chan_s
5940 +{
5941 +       u32             dmac ;          // Control.
5942 +       u32             dmas ;          // Status.
5943 +       u32             dmasm ;         // Mask.
5944 +       u32             dmadptr ;       // Descriptor pointer.
5945 +       u32             dmandptr ;      // Next descriptor pointer.
5946 +};
5947 +
5948 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
5949 +
5950 +//DMA_Channels   use DMACH_count instead
5951 +
5952 +enum
5953 +{
5954 +       DMAC_run_b      = 0,            //
5955 +       DMAC_run_m      = 0x00000001,   //
5956 +       DMAC_dm_b       = 1,            // done mask
5957 +       DMAC_dm_m       = 0x00000002,   //
5958 +       DMAC_mode_b     = 2,            //
5959 +       DMAC_mode_m     = 0x0000000c,   //
5960 +               DMAC_mode_auto_v        = 0,
5961 +               DMAC_mode_burst_v       = 1,
5962 +               DMAC_mode_transfer_v    = 2, //usually used
5963 +               DMAC_mode_reserved_v    = 3,
5964 +       DMAC_a_b        = 4,            //
5965 +       DMAC_a_m        = 0x00000010,   //
5966 +
5967 +       DMAS_f_b        = 0,            // finished (sticky)
5968 +       DMAS_f_m        = 0x00000001,   //
5969 +       DMAS_d_b        = 1,            // done (sticky)
5970 +       DMAS_d_m        = 0x00000002,   //
5971 +       DMAS_c_b        = 2,            // chain (sticky)
5972 +       DMAS_c_m        = 0x00000004,   //
5973 +       DMAS_e_b        = 3,            // error (sticky)
5974 +       DMAS_e_m        = 0x00000008,   //
5975 +       DMAS_h_b        = 4,            // halt (sticky)
5976 +       DMAS_h_m        = 0x00000010,   //
5977 +
5978 +       DMASM_f_b       = 0,            // finished (1=mask)
5979 +       DMASM_f_m       = 0x00000001,   //
5980 +       DMASM_d_b       = 1,            // done (1=mask)
5981 +       DMASM_d_m       = 0x00000002,   //
5982 +       DMASM_c_b       = 2,            // chain (1=mask)
5983 +       DMASM_c_m       = 0x00000004,   //
5984 +       DMASM_e_b       = 3,            // error (1=mask)
5985 +       DMASM_e_m       = 0x00000008,   //
5986 +       DMASM_h_b       = 4,            // halt (1=mask)
5987 +       DMASM_h_m       = 0x00000010,   //
5988 +} ;
5989 +
5990 +/*
5991 + * DMA channel definitions
5992 + */
5993 +
5994 +enum
5995 +{
5996 +       DMACH_ethRcv0 = 0,
5997 +       DMACH_ethXmt0 = 1,
5998 +       DMACH_memToFifo = 2,
5999 +       DMACH_fifoToMem = 3,
6000 +       DMACH_pciToMem = 4,
6001 +       DMACH_memToPci = 5,
6002 +
6003 +       DMACH_count //must be last
6004 +};
6005 +
6006 +
6007 +typedef struct DMAC_s
6008 +{
6009 +       struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
6010 +} volatile *DMA_t ;
6011 +
6012 +
6013 +/*
6014 + * External DMA parameters
6015 +*/
6016 +
6017 +enum
6018 +{
6019 +       DMADEVCMD_ts_b  = 0,            // ts field in devcmd
6020 +       DMADEVCMD_ts_m  = 0x00000007,   // ts field in devcmd
6021 +               DMADEVCMD_ts_byte_v     = 0,
6022 +               DMADEVCMD_ts_halfword_v = 1,
6023 +               DMADEVCMD_ts_word_v     = 2,
6024 +               DMADEVCMD_ts_2word_v    = 3,
6025 +               DMADEVCMD_ts_4word_v    = 4,
6026 +               DMADEVCMD_ts_6word_v    = 5,
6027 +               DMADEVCMD_ts_8word_v    = 6,
6028 +               DMADEVCMD_ts_16word_v   = 7
6029 +};
6030 +
6031 +
6032 +#endif // __IDT_DMA_H__
6033 +
6034 +
6035 +
6036 +
6037 +
6038 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h
6039 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h    1970-01-01 01:00:00.000000000 +0100
6040 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h       2006-06-18 12:44:28.000000000 +0200
6041 @@ -0,0 +1,89 @@
6042 +/**************************************************************************
6043 + *
6044 + *  BRIEF MODULE DESCRIPTION
6045 + *   Definitions for DMA controller.
6046 + *
6047 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6048 + *
6049 + *  This program is free software; you can redistribute  it and/or modify it
6050 + *  under  the terms of  the GNU General  Public License as published by the
6051 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6052 + *  option) any later version.
6053 + *
6054 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6055 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6056 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6057 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6058 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6059 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6060 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6061 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6062 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6063 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6064 + *
6065 + *  You should have received a copy of the  GNU General Public License along
6066 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6067 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6068 + *
6069 + *
6070 + **************************************************************************
6071 + * May 2004 rkt, neb.
6072 + *
6073 + * Initial Release
6074 + *
6075 + *
6076 + *
6077 + **************************************************************************
6078 + */
6079 +
6080 +#ifndef __IDT_DMA_V_H__
6081 +#define __IDT_DMA_V_H__
6082 +
6083 +#include  <asm/idt-boards/rc32434/rc32434_dma.h>
6084 +#include  <asm/idt-boards/rc32434/rc32434.h>
6085 +
6086 +#define DMA_CHAN_OFFSET  0x14
6087 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
6088 +#define DMA_COUNT(count)   \
6089 +  ((count) & DMAD_count_m)
6090 +
6091 +#define DMA_HALT_TIMEOUT 500
6092 +
6093 +
6094 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
6095 +{
6096 +       int timeout=1;
6097 +       if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
6098 +               rc32434_writel(0, &ch->dmac);
6099 +
6100 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
6101 +                       if (rc32434_readl(&ch->dmas) & DMAS_h_m) {
6102 +                               rc32434_writel(0, &ch->dmas);
6103 +                               break;
6104 +                       }
6105 +               }
6106 +
6107 +       }
6108 +
6109 +       return timeout ? 0 : 1;
6110 +}
6111 +
6112 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
6113 +{
6114 +       rc32434_writel(0, &ch->dmandptr);
6115 +       rc32434_writel(dma_addr, &ch->dmadptr);
6116 +}
6117 +
6118 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
6119 +{
6120 +       rc32434_writel(dma_addr, &ch->dmandptr);
6121 +}
6122 +
6123 +#endif // __IDT_DMA_V_H__
6124 +
6125 +
6126 +
6127 +
6128 +
6129 +
6130 +
6131 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h
6132 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth.h      1970-01-01 01:00:00.000000000 +0100
6133 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 2006-06-18 12:44:28.000000000 +0200
6134 @@ -0,0 +1,333 @@
6135 +/**************************************************************************
6136 + *
6137 + *  BRIEF MODULE DESCRIPTION
6138 + *   Ethernet register definition
6139 + *
6140 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6141 + *
6142 + *  This program is free software; you can redistribute  it and/or modify it
6143 + *  under  the terms of  the GNU General  Public License as published by the
6144 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6145 + *  option) any later version.
6146 + *
6147 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6148 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6149 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6150 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6151 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6152 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6153 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6154 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6155 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6156 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6157 + *
6158 + *  You should have received a copy of the  GNU General Public License along
6159 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6160 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6161 + *
6162 + *
6163 + **************************************************************************
6164 + * May 2004 rkt, neb.
6165 + *
6166 + * Initial Release
6167 + *
6168 + *
6169 + *
6170 + **************************************************************************
6171 + */
6172 +
6173 +#ifndef        __IDT_ETH_H__
6174 +#define        __IDT_ETH_H__
6175 +
6176 +
6177 +enum
6178 +{
6179 +       ETH0_PhysicalAddress    = 0x18060000,
6180 +       ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
6181 +
6182 +       ETH0_VirtualAddress     = 0xb8060000,
6183 +       ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
6184 +} ;
6185 +
6186 +typedef struct
6187 +{
6188 +       u32 ethintfc            ;
6189 +       u32 ethfifott           ;
6190 +       u32 etharc              ;
6191 +       u32 ethhash0            ;
6192 +       u32 ethhash1            ;
6193 +       u32 ethu0 [4]           ;       // Reserved.
6194 +       u32 ethpfs              ;
6195 +       u32 ethmcp              ;
6196 +       u32 eth_u1 [10]         ;       // Reserved.
6197 +       u32 ethspare            ;
6198 +       u32 eth_u2 [42]         ;       // Reserved.
6199 +       u32 ethsal0             ;
6200 +       u32 ethsah0             ;
6201 +       u32 ethsal1             ;
6202 +       u32 ethsah1             ;
6203 +       u32 ethsal2             ;
6204 +       u32 ethsah2             ;
6205 +       u32 ethsal3             ;
6206 +       u32 ethsah3             ;
6207 +       u32 ethrbc              ;
6208 +       u32 ethrpc              ;
6209 +       u32 ethrupc             ;
6210 +       u32 ethrfc              ;
6211 +       u32 ethtbc              ;
6212 +       u32 ethgpf              ;
6213 +       u32 eth_u9 [50]         ;       // Reserved.
6214 +       u32 ethmac1             ;
6215 +       u32 ethmac2             ;
6216 +       u32 ethipgt             ;
6217 +       u32 ethipgr             ;
6218 +       u32 ethclrt             ;
6219 +       u32 ethmaxf             ;
6220 +       u32 eth_u10             ;       // Reserved.
6221 +       u32 ethmtest            ;
6222 +       u32 miimcfg             ;
6223 +       u32 miimcmd             ;
6224 +       u32 miimaddr            ;
6225 +       u32 miimwtd             ;
6226 +       u32 miimrdd             ;
6227 +       u32 miimind             ;
6228 +       u32 eth_u11             ;       // Reserved.
6229 +       u32 eth_u12             ;       // Reserved.
6230 +       u32 ethcfsa0            ;
6231 +       u32 ethcfsa1            ;
6232 +       u32 ethcfsa2            ;
6233 +} volatile *ETH_t;
6234 +
6235 +enum
6236 +{
6237 +       ETHINTFC_en_b           = 0,
6238 +       ETHINTFC_en_m           = 0x00000001,
6239 +       ETHINTFC_its_b          = 1,
6240 +       ETHINTFC_its_m          = 0x00000002,
6241 +       ETHINTFC_rip_b          = 2,
6242 +       ETHINTFC_rip_m          = 0x00000004,
6243 +       ETHINTFC_jam_b          = 3,
6244 +       ETHINTFC_jam_m          = 0x00000008,
6245 +       ETHINTFC_ovr_b          = 4,
6246 +       ETHINTFC_ovr_m          = 0x00000010,
6247 +       ETHINTFC_und_b          = 5,
6248 +       ETHINTFC_und_m          = 0x00000020,
6249 +
6250 +       ETHFIFOTT_tth_b         = 0,
6251 +       ETHFIFOTT_tth_m         = 0x0000007f,
6252 +
6253 +       ETHARC_pro_b            = 0,
6254 +       ETHARC_pro_m            = 0x00000001,
6255 +       ETHARC_am_b             = 1,
6256 +       ETHARC_am_m             = 0x00000002,
6257 +       ETHARC_afm_b            = 2,
6258 +       ETHARC_afm_m            = 0x00000004,
6259 +       ETHARC_ab_b             = 3,
6260 +       ETHARC_ab_m             = 0x00000008,
6261 +
6262 +       ETHSAL_byte5_b          = 0,
6263 +       ETHSAL_byte5_m          = 0x000000ff,
6264 +       ETHSAL_byte4_b          = 8,
6265 +       ETHSAL_byte4_m          = 0x0000ff00,
6266 +       ETHSAL_byte3_b          = 16,
6267 +       ETHSAL_byte3_m          = 0x00ff0000,
6268 +       ETHSAL_byte2_b          = 24,
6269 +       ETHSAL_byte2_m          = 0xff000000,
6270 +
6271 +       ETHSAH_byte1_b          = 0,
6272 +       ETHSAH_byte1_m          = 0x000000ff,
6273 +       ETHSAH_byte0_b          = 8,
6274 +       ETHSAH_byte0_m          = 0x0000ff00,
6275 +
6276 +       ETHGPF_ptv_b            = 0,
6277 +       ETHGPF_ptv_m            = 0x0000ffff,
6278 +
6279 +       ETHPFS_pfd_b            = 0,
6280 +       ETHPFS_pfd_m            = 0x00000001,
6281 +
6282 +       ETHCFSA0_cfsa4_b        = 0,
6283 +       ETHCFSA0_cfsa4_m        = 0x000000ff,
6284 +       ETHCFSA0_cfsa5_b        = 8,
6285 +       ETHCFSA0_cfsa5_m        = 0x0000ff00,
6286 +
6287 +       ETHCFSA1_cfsa2_b        = 0,
6288 +       ETHCFSA1_cfsa2_m        = 0x000000ff,
6289 +       ETHCFSA1_cfsa3_b        = 8,
6290 +       ETHCFSA1_cfsa3_m        = 0x0000ff00,
6291 +
6292 +       ETHCFSA2_cfsa0_b        = 0,
6293 +       ETHCFSA2_cfsa0_m        = 0x000000ff,
6294 +       ETHCFSA2_cfsa1_b        = 8,
6295 +       ETHCFSA2_cfsa1_m        = 0x0000ff00,
6296 +
6297 +       ETHMAC1_re_b            = 0,
6298 +       ETHMAC1_re_m            = 0x00000001,
6299 +       ETHMAC1_paf_b           = 1,
6300 +       ETHMAC1_paf_m           = 0x00000002,
6301 +       ETHMAC1_rfc_b           = 2,
6302 +       ETHMAC1_rfc_m           = 0x00000004,
6303 +       ETHMAC1_tfc_b           = 3,
6304 +       ETHMAC1_tfc_m           = 0x00000008,
6305 +       ETHMAC1_lb_b            = 4,
6306 +       ETHMAC1_lb_m            = 0x00000010,
6307 +       ETHMAC1_mr_b            = 31,
6308 +       ETHMAC1_mr_m            = 0x80000000,
6309 +
6310 +       ETHMAC2_fd_b            = 0,
6311 +       ETHMAC2_fd_m            = 0x00000001,
6312 +       ETHMAC2_flc_b           = 1,
6313 +       ETHMAC2_flc_m           = 0x00000002,
6314 +       ETHMAC2_hfe_b           = 2,
6315 +       ETHMAC2_hfe_m           = 0x00000004,
6316 +       ETHMAC2_dc_b            = 3,
6317 +       ETHMAC2_dc_m            = 0x00000008,
6318 +       ETHMAC2_cen_b           = 4,
6319 +       ETHMAC2_cen_m           = 0x00000010,
6320 +       ETHMAC2_pe_b            = 5,
6321 +       ETHMAC2_pe_m            = 0x00000020,
6322 +       ETHMAC2_vpe_b           = 6,
6323 +       ETHMAC2_vpe_m           = 0x00000040,
6324 +       ETHMAC2_ape_b           = 7,
6325 +       ETHMAC2_ape_m           = 0x00000080,
6326 +       ETHMAC2_ppe_b           = 8,
6327 +       ETHMAC2_ppe_m           = 0x00000100,
6328 +       ETHMAC2_lpe_b           = 9,
6329 +       ETHMAC2_lpe_m           = 0x00000200,
6330 +       ETHMAC2_nb_b            = 12,
6331 +       ETHMAC2_nb_m            = 0x00001000,
6332 +       ETHMAC2_bp_b            = 13,
6333 +       ETHMAC2_bp_m            = 0x00002000,
6334 +       ETHMAC2_ed_b            = 14,
6335 +       ETHMAC2_ed_m            = 0x00004000,
6336 +
6337 +       ETHIPGT_ipgt_b          = 0,
6338 +       ETHIPGT_ipgt_m          = 0x0000007f,
6339 +
6340 +       ETHIPGR_ipgr2_b         = 0,
6341 +       ETHIPGR_ipgr2_m         = 0x0000007f,
6342 +       ETHIPGR_ipgr1_b         = 8,
6343 +       ETHIPGR_ipgr1_m         = 0x00007f00,
6344 +
6345 +       ETHCLRT_maxret_b        = 0,
6346 +       ETHCLRT_maxret_m        = 0x0000000f,
6347 +       ETHCLRT_colwin_b        = 8,
6348 +       ETHCLRT_colwin_m        = 0x00003f00,
6349 +
6350 +       ETHMAXF_maxf_b          = 0,
6351 +       ETHMAXF_maxf_m          = 0x0000ffff,
6352 +
6353 +       ETHMTEST_tb_b           = 2,
6354 +       ETHMTEST_tb_m           = 0x00000004,
6355 +
6356 +       ETHMCP_div_b            = 0,
6357 +       ETHMCP_div_m            = 0x000000ff,
6358 +
6359 +       MIIMCFG_rsv_b           = 0,
6360 +       MIIMCFG_rsv_m           = 0x0000000c,
6361 +
6362 +       MIIMCMD_rd_b            = 0,
6363 +       MIIMCMD_rd_m            = 0x00000001,
6364 +       MIIMCMD_scn_b           = 1,
6365 +       MIIMCMD_scn_m           = 0x00000002,
6366 +
6367 +       MIIMADDR_regaddr_b      = 0,
6368 +       MIIMADDR_regaddr_m      = 0x0000001f,
6369 +       MIIMADDR_phyaddr_b      = 8,
6370 +       MIIMADDR_phyaddr_m      = 0x00001f00,
6371 +
6372 +       MIIMWTD_wdata_b         = 0,
6373 +       MIIMWTD_wdata_m         = 0x0000ffff,
6374 +
6375 +       MIIMRDD_rdata_b         = 0,
6376 +       MIIMRDD_rdata_m         = 0x0000ffff,
6377 +
6378 +       MIIMIND_bsy_b           = 0,
6379 +       MIIMIND_bsy_m           = 0x00000001,
6380 +       MIIMIND_scn_b           = 1,
6381 +       MIIMIND_scn_m           = 0x00000002,
6382 +       MIIMIND_nv_b            = 2,
6383 +       MIIMIND_nv_m            = 0x00000004,
6384 +
6385 +} ;
6386 +
6387 +/*
6388 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
6389 + */
6390 +enum
6391 +{
6392 +       ETHRX_fd_b              = 0,
6393 +       ETHRX_fd_m              = 0x00000001,
6394 +       ETHRX_ld_b              = 1,
6395 +       ETHRX_ld_m              = 0x00000002,
6396 +       ETHRX_rok_b             = 2,
6397 +       ETHRX_rok_m             = 0x00000004,
6398 +       ETHRX_fm_b              = 3,
6399 +       ETHRX_fm_m              = 0x00000008,
6400 +       ETHRX_mp_b              = 4,
6401 +       ETHRX_mp_m              = 0x00000010,
6402 +       ETHRX_bp_b              = 5,
6403 +       ETHRX_bp_m              = 0x00000020,
6404 +       ETHRX_vlt_b             = 6,
6405 +       ETHRX_vlt_m             = 0x00000040,
6406 +       ETHRX_cf_b              = 7,
6407 +       ETHRX_cf_m              = 0x00000080,
6408 +       ETHRX_ovr_b             = 8,
6409 +       ETHRX_ovr_m             = 0x00000100,
6410 +       ETHRX_crc_b             = 9,
6411 +       ETHRX_crc_m             = 0x00000200,
6412 +       ETHRX_cv_b              = 10,
6413 +       ETHRX_cv_m              = 0x00000400,
6414 +       ETHRX_db_b              = 11,
6415 +       ETHRX_db_m              = 0x00000800,
6416 +       ETHRX_le_b              = 12,
6417 +       ETHRX_le_m              = 0x00001000,
6418 +       ETHRX_lor_b             = 13,
6419 +       ETHRX_lor_m             = 0x00002000,
6420 +       ETHRX_ces_b             = 14,
6421 +       ETHRX_ces_m             = 0x00004000,
6422 +       ETHRX_length_b          = 16,
6423 +       ETHRX_length_m          = 0xffff0000,
6424 +
6425 +       ETHTX_fd_b              = 0,
6426 +       ETHTX_fd_m              = 0x00000001,
6427 +       ETHTX_ld_b              = 1,
6428 +       ETHTX_ld_m              = 0x00000002,
6429 +       ETHTX_oen_b             = 2,
6430 +       ETHTX_oen_m             = 0x00000004,
6431 +       ETHTX_pen_b             = 3,
6432 +       ETHTX_pen_m             = 0x00000008,
6433 +       ETHTX_cen_b             = 4,
6434 +       ETHTX_cen_m             = 0x00000010,
6435 +       ETHTX_hen_b             = 5,
6436 +       ETHTX_hen_m             = 0x00000020,
6437 +       ETHTX_tok_b             = 6,
6438 +       ETHTX_tok_m             = 0x00000040,
6439 +       ETHTX_mp_b              = 7,
6440 +       ETHTX_mp_m              = 0x00000080,
6441 +       ETHTX_bp_b              = 8,
6442 +       ETHTX_bp_m              = 0x00000100,
6443 +       ETHTX_und_b             = 9,
6444 +       ETHTX_und_m             = 0x00000200,
6445 +       ETHTX_of_b              = 10,
6446 +       ETHTX_of_m              = 0x00000400,
6447 +       ETHTX_ed_b              = 11,
6448 +       ETHTX_ed_m              = 0x00000800,
6449 +       ETHTX_ec_b              = 12,
6450 +       ETHTX_ec_m              = 0x00001000,
6451 +       ETHTX_lc_b              = 13,
6452 +       ETHTX_lc_m              = 0x00002000,
6453 +       ETHTX_td_b              = 14,
6454 +       ETHTX_td_m              = 0x00004000,
6455 +       ETHTX_crc_b             = 15,
6456 +       ETHTX_crc_m             = 0x00008000,
6457 +       ETHTX_le_b              = 16,
6458 +       ETHTX_le_m              = 0x00010000,
6459 +       ETHTX_cc_b              = 17,
6460 +       ETHTX_cc_m              = 0x001E0000,
6461 +} ;
6462 +
6463 +#endif // __IDT_ETH_H__
6464 +
6465 +
6466 +
6467 +
6468 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h
6469 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h    1970-01-01 01:00:00.000000000 +0100
6470 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h       2006-06-18 12:44:28.000000000 +0200
6471 @@ -0,0 +1,77 @@
6472 +/**************************************************************************
6473 + *
6474 + *  BRIEF MODULE DESCRIPTION
6475 + *   Ethernet register definition
6476 + *
6477 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6478 + *
6479 + *  This program is free software; you can redistribute  it and/or modify it
6480 + *  under  the terms of  the GNU General  Public License as published by the
6481 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6482 + *  option) any later version.
6483 + *
6484 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6485 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6486 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6487 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6488 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6489 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6490 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6491 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6492 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6493 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6494 + *
6495 + *  You should have received a copy of the  GNU General Public License along
6496 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6497 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6498 + *
6499 + *
6500 + **************************************************************************
6501 + * May 2004 rkt, neb.
6502 + *
6503 + * Initial Release
6504 + *
6505 + *
6506 + *
6507 + **************************************************************************
6508 + */
6509 +
6510 +#ifndef        __IDT_ETH_V_H__
6511 +#define        __IDT_ETH_V_H__
6512 +
6513 +#include  <asm/idt-boards/rc32434/rc32434_eth.h>
6514 +
6515 +#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
6516 +#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
6517 +#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
6518 +#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
6519 +#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
6520 +#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
6521 +#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
6522 +#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
6523 +#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
6524 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
6525 +#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
6526 +
6527 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
6528 +
6529 +#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
6530 +#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
6531 +#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
6532 +#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
6533 +#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
6534 +#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
6535 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
6536 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
6537 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
6538 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
6539 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
6540 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
6541 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
6542 +#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
6543 +#endif // __IDT_ETH_V_H__
6544 +
6545 +
6546 +
6547 +
6548 +
6549 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h
6550 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h     1970-01-01 01:00:00.000000000 +0100
6551 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h        2006-06-18 12:44:28.000000000 +0200
6552 @@ -0,0 +1,167 @@
6553 +/**************************************************************************
6554 + *
6555 + *  BRIEF MODULE DESCRIPTION
6556 + *   GPIO register definition
6557 + *
6558 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6559 + *
6560 + *  This program is free software; you can redistribute  it and/or modify it
6561 + *  under  the terms of  the GNU General  Public License as published by the
6562 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6563 + *  option) any later version.
6564 + *
6565 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6566 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6567 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6568 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6569 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6570 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6571 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6572 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6573 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6574 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6575 + *
6576 + *  You should have received a copy of the  GNU General Public License along
6577 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6578 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6579 + *
6580 + *
6581 + **************************************************************************
6582 + * May 2004 rkt, neb.
6583 + *
6584 + * Initial Release
6585 + *
6586 + *
6587 + *
6588 + **************************************************************************
6589 + */
6590 +
6591 +#ifndef __IDT_GPIO_H__
6592 +#define __IDT_GPIO_H__
6593 +
6594 +enum
6595 +{
6596 +       GPIO0_PhysicalAddress   = 0x18050000,
6597 +       GPIO_PhysicalAddress    = GPIO0_PhysicalAddress,        // Default
6598 +
6599 +       GPIO0_VirtualAddress    = 0xb8050000,
6600 +       GPIO_VirtualAddress     = GPIO0_VirtualAddress,         // Default
6601 +} ;
6602 +
6603 +typedef struct
6604 +{
6605 +       u32   gpiofunc;   /* GPIO Function Register
6606 +                          * gpiofunc[x]==0 bit = gpio
6607 +                          * func[x]==1  bit = altfunc
6608 +                          */
6609 +       u32   gpiocfg;    /* GPIO Configuration Register
6610 +                          * gpiocfg[x]==0 bit = input
6611 +                          * gpiocfg[x]==1 bit = output
6612 +                          */
6613 +       u32   gpiod;      /* GPIO Data Register
6614 +                          * gpiod[x] read/write gpio pinX status
6615 +                          */
6616 +       u32   gpioilevel; /* GPIO Interrupt Status Register
6617 +                          * interrupt level (see gpioistat)
6618 +                          */
6619 +       u32   gpioistat;  /* Gpio Interrupt Status Register
6620 +                          * istat[x] = (gpiod[x] == level[x])
6621 +                          * cleared in ISR (STICKY bits)
6622 +                          */
6623 +       u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
6624 +} volatile * GPIO_t ;
6625 +
6626 +typedef enum
6627 +{
6628 +       GPIO_gpio_v             = 0,            // gpiofunc use pin as GPIO.
6629 +       GPIO_alt_v              = 1,            // gpiofunc use pin as alt.
6630 +       GPIO_input_v            = 0,            // gpiocfg use pin as input.
6631 +       GPIO_output_v           = 1,            // gpiocfg use pin as output.
6632 +       GPIO_pin0_b             = 0,
6633 +       GPIO_pin0_m             = 0x00000001,
6634 +       GPIO_pin1_b             = 1,
6635 +       GPIO_pin1_m             = 0x00000002,
6636 +       GPIO_pin2_b             = 2,
6637 +       GPIO_pin2_m             = 0x00000004,
6638 +       GPIO_pin3_b             = 3,
6639 +       GPIO_pin3_m             = 0x00000008,
6640 +       GPIO_pin4_b             = 4,
6641 +       GPIO_pin4_m             = 0x00000010,
6642 +       GPIO_pin5_b             = 5,
6643 +       GPIO_pin5_m             = 0x00000020,
6644 +       GPIO_pin6_b             = 6,
6645 +       GPIO_pin6_m             = 0x00000040,
6646 +       GPIO_pin7_b             = 7,
6647 +       GPIO_pin7_m             = 0x00000080,
6648 +       GPIO_pin8_b             = 8,
6649 +       GPIO_pin8_m             = 0x00000100,
6650 +       GPIO_pin9_b             = 9,
6651 +       GPIO_pin9_m             = 0x00000200,
6652 +       GPIO_pin10_b            = 10,
6653 +       GPIO_pin10_m            = 0x00000400,
6654 +       GPIO_pin11_b            = 11,
6655 +       GPIO_pin11_m            = 0x00000800,
6656 +       GPIO_pin12_b            = 12,
6657 +       GPIO_pin12_m            = 0x00001000,
6658 +       GPIO_pin13_b            = 13,
6659 +       GPIO_pin13_m            = 0x00002000,
6660 +
6661 +// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
6662 +
6663 +       GPIO_u0sout_b           = GPIO_pin0_b,          // UART 0 serial out.
6664 +       GPIO_u0sout_m           = GPIO_pin0_m,
6665 +               GPIO_u0sout_cfg_v       = GPIO_output_v,
6666 +       GPIO_u0sinp_b   = GPIO_pin1_b,                  // UART 0 serial in.
6667 +       GPIO_u0sinp_m   = GPIO_pin1_m,
6668 +               GPIO_u0sinp_cfg_v       = GPIO_input_v,
6669 +       GPIO_u0rtsn_b   = GPIO_pin2_b,                  // UART 0 req. to send.
6670 +       GPIO_u0rtsn_m   = GPIO_pin2_m,
6671 +               GPIO_u0rtsn_cfg_v       = GPIO_output_v,
6672 +       GPIO_u0ctsn_b   = GPIO_pin3_b,                  // UART 0 clear to send.
6673 +       GPIO_u0ctsn_m   = GPIO_pin3_m,
6674 +               GPIO_u0ctsn_cfg_v       = GPIO_input_v,
6675 +
6676 +       GPIO_maddr22_b          = GPIO_pin4_b,  // M&P bus bit 22.
6677 +       GPIO_maddr22_m          = GPIO_pin4_m,
6678 +               GPIO_maddr22_cfg_v      = GPIO_output_v,
6679 +
6680 +       GPIO_maddr23_b          = GPIO_pin5_b,  // M&P bus bit 23.
6681 +       GPIO_maddr23_m          = GPIO_pin5_m,
6682 +               GPIO_maddr23_cfg_v      = GPIO_output_v,
6683 +
6684 +       GPIO_maddr24_b          = GPIO_pin6_b,  // M&P bus bit 24.
6685 +       GPIO_maddr24_m          = GPIO_pin6_m,
6686 +               GPIO_maddr24_cfg_v      = GPIO_output_v,
6687 +
6688 +       GPIO_maddr25_b          = GPIO_pin7_b,  // M&P bus bit 25.
6689 +       GPIO_maddr25_m          = GPIO_pin7_m,
6690 +               GPIO_maddr25_cfg_v      = GPIO_output_v,
6691 +
6692 +       GPIO_cpudmadebug_b      = GPIO_pin8_b,  // CPU or DMA debug pin
6693 +       GPIO_cpudmadebug_m      = GPIO_pin8_m,
6694 +               GPIO_cpudmadebug_cfg_v  = GPIO_output_v,
6695 +
6696 +       GPIO_pcireq4_b  = GPIO_pin9_b,  // PCI Request 4
6697 +       GPIO_pcireq4_m  = GPIO_pin9_m,
6698 +               GPIO_pcireq4_cfg_v      = GPIO_input_v,
6699 +
6700 +       GPIO_pcigrant4_b        = GPIO_pin10_b,         // PCI Grant 4
6701 +       GPIO_pcigrant4_m        = GPIO_pin10_m,
6702 +               GPIO_pcigrant4_cfg_v    = GPIO_output_v,
6703 +
6704 +       GPIO_pcireq5_b  = GPIO_pin11_b,         // PCI Request 5
6705 +       GPIO_pcireq5_m  = GPIO_pin11_m,
6706 +               GPIO_pcireq5_cfg_v      = GPIO_input_v,
6707 +
6708 +       GPIO_pcigrant5_b        = GPIO_pin12_b,         // PCI Grant 5
6709 +       GPIO_pcigrant5_m        = GPIO_pin12_m,
6710 +               GPIO_pcigrant5_cfg_v    = GPIO_output_v,
6711 +
6712 +       GPIO_pcimuintn_b        = GPIO_pin13_b,         // PCI messaging int.
6713 +       GPIO_pcimuintn_m        = GPIO_pin13_m,
6714 +               GPIO_pcimuintn_cfg_v    = GPIO_output_v,
6715 +
6716 +} GPIO_DEFS_t;
6717 +
6718 +#endif // __IDT_GPIO_H__
6719 +
6720 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h
6721 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434.h  1970-01-01 01:00:00.000000000 +0100
6722 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h     2006-06-18 12:44:28.000000000 +0200
6723 @@ -0,0 +1,199 @@
6724 + /**************************************************************************
6725 + *
6726 + *  BRIEF MODULE DESCRIPTION
6727 + *   Definitions for IDT RC32434 CPU
6728 + *
6729 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6730 + *
6731 + *  This program is free software; you can redistribute  it and/or modify it
6732 + *  under  the terms of  the GNU General  Public License as published by the
6733 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6734 + *  option) any later version.
6735 + *
6736 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6737 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6738 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6739 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6740 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6741 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6742 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6743 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6744 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6745 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6746 + *
6747 + *  You should have received a copy of the  GNU General Public License along
6748 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6749 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6750 + *
6751 + *
6752 + **************************************************************************
6753 + * May 2004 rkt, neb.
6754 + *
6755 + * Initial Release
6756 + *
6757 + *
6758 + *
6759 + **************************************************************************
6760 + */
6761 +
6762 +#ifndef _RC32434_H_
6763 +#define _RC32434_H_
6764 +
6765 +#include <linux/config.h>
6766 +#include <linux/delay.h>
6767 +#include <asm/io.h>
6768 +#include <asm/idt-boards/rc32434/rc32434_timer.h>
6769 +
6770 +#define RC32434_REG_BASE   0x18000000
6771 +
6772 +
6773 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
6774 +#define idt_timer     ((volatile TIM_t)  TIM0_VirtualAddress)
6775 +#define idt_gpio         ((volatile GPIO_t) GPIO0_VirtualAddress)
6776 +
6777 +#define IDT_CLOCK_MULT 2
6778 +#define MIPS_CPU_TIMER_IRQ 7
6779 +/* Interrupt Controller */
6780 +#define IC_GROUP0_PEND     (RC32434_REG_BASE + 0x38000)
6781 +#define IC_GROUP0_MASK     (RC32434_REG_BASE + 0x38008)
6782 +#define IC_GROUP_OFFSET    0x0C
6783 +#define RTC_BASE           0xBA001FF0
6784 +
6785 +#define NUM_INTR_GROUPS    5
6786 +/* 16550 UARTs */
6787 +
6788 +#define GROUP0_IRQ_BASE 8              /* GRP2 IRQ numbers start here */
6789 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
6790 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
6791 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
6792 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
6793 +
6794 +#ifdef __MIPSEB__
6795 +
6796 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
6797 +#define EB434_UART1_BASE   (0x19800003)
6798 +
6799 +#else
6800 +
6801 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
6802 +#define EB434_UART1_BASE   (0x19800000)
6803 +
6804 +#endif
6805 +
6806 +#define RC32434_UART0_IRQ  GROUP3_IRQ_BASE + 0
6807 +#define EB434_UART1_IRQ    GROUP4_IRQ_BASE + 11
6808 +
6809 +#define RC32434_NR_IRQS  (GROUP4_IRQ_BASE + 32)
6810 +
6811 +/* cpu pipeline flush */
6812 +static inline void rc32434_sync(void)
6813 +{
6814 +        __asm__ volatile ("sync");
6815 +}
6816 +
6817 +static inline void rc32434_sync_udelay(int us)
6818 +{
6819 +        __asm__ volatile ("sync");
6820 +        udelay(us);
6821 +}
6822 +
6823 +static inline void rc32434_sync_delay(int ms)
6824 +{
6825 +        __asm__ volatile ("sync");
6826 +        mdelay(ms);
6827 +}
6828 +
6829 +
6830 +
6831 +/*
6832 + * Macros to access internal RC32434 registers. No byte
6833 + * swapping should be done when accessing the internal
6834 + * registers.
6835 + */
6836 +
6837 +#define rc32434_readb __raw_readb
6838 +#define rc32434_readw __raw_readw
6839 +#define rc32434_readl __raw_readl
6840 +
6841 +#define rc32434_writeb __raw_writeb
6842 +#define rc32434_writew __raw_writew
6843 +#define rc32434_writel __raw_writel
6844 +
6845 +#if 0
6846 +static inline u8 rc32434_readb(unsigned long pa)
6847 +{
6848 +       return *((volatile u8 *)KSEG1ADDR(pa));
6849 +}
6850 +static inline u16 rc32434_readw(unsigned long pa)
6851 +{
6852 +       return *((volatile u16 *)KSEG1ADDR(pa));
6853 +}
6854 +static inline u32 rc32434_readl(unsigned long pa)
6855 +{
6856 +       return *((volatile u32 *)KSEG1ADDR(pa));
6857 +}
6858 +static inline void rc32434_writeb(u8 val, unsigned long pa)
6859 +{
6860 +       *((volatile u8 *)KSEG1ADDR(pa)) = val;
6861 +}
6862 +static inline void rc32434_writew(u16 val, unsigned long pa)
6863 +{
6864 +       *((volatile u16 *)KSEG1ADDR(pa)) = val;
6865 +}
6866 +static inline void rc32434_writel(u32 val, unsigned long pa)
6867 +{
6868 +       *((volatile u32 *)KSEG1ADDR(pa)) = val;
6869 +}
6870 +
6871 +#endif
6872 +
6873 +
6874 +/*
6875 + * C access to CLZ and CLO instructions
6876 + * (count leading zeroes/ones).
6877 + */
6878 +static inline int rc32434_clz(unsigned long val)
6879 +{
6880 +       int ret;
6881 +        __asm__ volatile (
6882 +               ".set\tnoreorder\n\t"
6883 +               ".set\tnoat\n\t"
6884 +               ".set\tmips32\n\t"
6885 +               "clz\t%0,%1\n\t"
6886 +                ".set\tmips0\n\t"
6887 +                ".set\tat\n\t"
6888 +                ".set\treorder"
6889 +                : "=r" (ret)
6890 +               : "r" (val));
6891 +
6892 +       return ret;
6893 +}
6894 +static inline int rc32434_clo(unsigned long val)
6895 +{
6896 +       int ret;
6897 +        __asm__ volatile (
6898 +               ".set\tnoreorder\n\t"
6899 +               ".set\tnoat\n\t"
6900 +               ".set\tmips32\n\t"
6901 +               "clo\t%0,%1\n\t"
6902 +                ".set\tmips0\n\t"
6903 +                ".set\tat\n\t"
6904 +                ".set\treorder"
6905 +                : "=r" (ret)
6906 +               : "r" (val));
6907 +
6908 +       return ret;
6909 +}
6910 +#endif /* _RC32434_H_ */
6911 +
6912 +
6913 +
6914 +
6915 +
6916 +
6917 +
6918 +
6919 +
6920 +
6921 +
6922 +
6923 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_integ.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h
6924 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_integ.h    1970-01-01 01:00:00.000000000 +0100
6925 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h       2006-06-18 12:44:28.000000000 +0200
6926 @@ -0,0 +1,90 @@
6927 +/**************************************************************************
6928 + *
6929 + *  BRIEF MODULE DESCRIPTION
6930 + *   System Integrity register definition
6931 + *
6932 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6933 + *
6934 + *  This program is free software; you can redistribute  it and/or modify it
6935 + *  under  the terms of  the GNU General  Public License as published by the
6936 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6937 + *  option) any later version.
6938 + *
6939 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6940 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6941 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6942 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6943 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6944 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6945 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6946 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6947 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6948 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6949 + *
6950 + *  You should have received a copy of the  GNU General Public License along
6951 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6952 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6953 + *
6954 + *
6955 + **************************************************************************
6956 + * May 2004 rkt, neb
6957 + *
6958 + * Initial Release
6959 + *
6960 + *
6961 + *
6962 + **************************************************************************
6963 + */
6964 +
6965 +#ifndef __IDT_INTEG_H__
6966 +#define __IDT_INTEG_H__
6967 +
6968 +enum
6969 +{
6970 +       INTEG0_PhysicalAddress  = 0x18030000,
6971 +       INTEG_PhysicalAddress   = INTEG0_PhysicalAddress,       // Default
6972 +
6973 +       INTEG0_VirtualAddress   = 0xB8030000,
6974 +       INTEG_VirtualAddress    = INTEG0_VirtualAddress,        // Default
6975 +} ;
6976 +
6977 +// if you are looking for CEA, try rst.h
6978 +typedef struct
6979 +{
6980 +       u32 filler [0xc] ;              // 0x30 bytes unused.
6981 +       u32 errcs ;                     // sticky use ERRCS_
6982 +       u32 wtcount ;                   // Watchdog timer count reg.
6983 +       u32 wtcompare ;                 // Watchdog timer timeout value.
6984 +       u32 wtc ;                       // Watchdog timer control. use WTC_
6985 +} volatile *INTEG_t ;
6986 +
6987 +enum
6988 +{
6989 +       ERRCS_wto_b             = 0,            // In INTEG_t -> errcs
6990 +       ERRCS_wto_m             = 0x00000001,
6991 +       ERRCS_wne_b             = 1,            // In INTEG_t -> errcs
6992 +       ERRCS_wne_m             = 0x00000002,
6993 +       ERRCS_ucw_b             = 2,            // In INTEG_t -> errcs
6994 +       ERRCS_ucw_m             = 0x00000004,
6995 +       ERRCS_ucr_b             = 3,            // In INTEG_t -> errcs
6996 +       ERRCS_ucr_m             = 0x00000008,
6997 +       ERRCS_upw_b             = 4,            // In INTEG_t -> errcs
6998 +       ERRCS_upw_m             = 0x00000010,
6999 +       ERRCS_upr_b             = 5,            // In INTEG_t -> errcs
7000 +       ERRCS_upr_m             = 0x00000020,
7001 +       ERRCS_udw_b             = 6,            // In INTEG_t -> errcs
7002 +       ERRCS_udw_m             = 0x00000040,
7003 +       ERRCS_udr_b             = 7,            // In INTEG_t -> errcs
7004 +       ERRCS_udr_m             = 0x00000080,
7005 +       ERRCS_sae_b             = 8,            // In INTEG_t -> errcs
7006 +       ERRCS_sae_m             = 0x00000100,
7007 +       ERRCS_wre_b             = 9,            // In INTEG_t -> errcs
7008 +       ERRCS_wre_m             = 0x00000200,
7009 +
7010 +       WTC_en_b                = 0,            // In INTEG_t -> wtc
7011 +       WTC_en_m                = 0x00000001,
7012 +       WTC_to_b                = 1,            // In INTEG_t -> wtc
7013 +       WTC_to_m                = 0x00000002,
7014 +} ;
7015 +
7016 +#endif // __IDT_INTEG_H__
7017 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_int.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h
7018 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_int.h      1970-01-01 01:00:00.000000000 +0100
7019 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h 2006-06-18 12:44:28.000000000 +0200
7020 @@ -0,0 +1,174 @@
7021 +/**************************************************************************
7022 + *
7023 + *  BRIEF MODULE DESCRIPTION
7024 + *   Interrupt Controller register definition.
7025 + *
7026 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
7027 + *
7028 + *  This program is free software; you can redistribute  it and/or modify it
7029 + *  under  the terms of  the GNU General  Public License as published by the
7030 + *  Free Software Foundation;  either version 2 of the  License, or (at your
7031 + *  option) any later version.
7032 + *
7033 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
7034 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
7035 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
7036 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
7037 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7038 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
7039 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7040 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
7041 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7042 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7043 + *
7044 + *  You should have received a copy of the  GNU General Public License along
7045 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
7046 + *  675 Mass Ave, Cambridge, MA 02139, USA.
7047 + *
7048 + *
7049 + **************************************************************************
7050 + * May 2004 rkt, neb.
7051 + *
7052 + * Initial Release
7053 + *
7054 + *
7055 + *
7056 + **************************************************************************
7057 + */
7058 +
7059 +#ifndef __IDT_INT_H__
7060 +#define __IDT_INT_H__
7061 +
7062 +enum
7063 +{
7064 +       INT0_PhysicalAddress    = 0x18038000,
7065 +       INT_PhysicalAddress     = INT0_PhysicalAddress,         // Default
7066 +
7067 +       INT0_VirtualAddress     = 0xB8038000,
7068 +       INT_VirtualAddress      = INT0_VirtualAddress,          // Default
7069 +} ;
7070 +
7071 +struct INT_s
7072 +{
7073 +       u32             ipend ;         //Pending interrupts. use INT?_
7074 +       u32             itest ;         //Test bits.            use INT?_
7075 +       u32             imask ;         //Interrupt disabled when set. use INT?_
7076 +} ;
7077 +
7078 +enum
7079 +{
7080 +       IPEND2  = 0,                    // HW 2 interrupt to core. use INT2_
7081 +       IPEND3  = 1,                    // HW 3 interrupt to core. use INT3_
7082 +       IPEND4  = 2,                    // HW 4 interrupt to core. use INT4_
7083 +       IPEND5  = 3,                    // HW 5 interrupt to core. use INT5_
7084 +       IPEND6  = 4,                    // HW 6 interrupt to core. use INT6_
7085 +
7086 +       IPEND_count,                    // must be last (used in loops)
7087 +       IPEND_min       = IPEND2        // min IPEND (used in loops)
7088 +};
7089 +
7090 +typedef struct INTC_s
7091 +{
7092 +       struct INT_s    i [IPEND_count] ;// use i[IPEND?] = INT?_
7093 +       u32             nmips ;         // use NMIPS_
7094 +} volatile *INT_t ;
7095 +
7096 +enum
7097 +{
7098 +       INT2_timer0_b                   = 0,
7099 +       INT2_timer0_m                   = 0x00000001,
7100 +       INT2_timer1_b                   = 1,
7101 +       INT2_timer1_m                   = 0x00000002,
7102 +       INT2_timer2_b                   = 2,
7103 +       INT2_timer2_m                   = 0x00000004,
7104 +       INT2_refresh_b                  = 3,
7105 +       INT2_refresh_m                  = 0x00000008,
7106 +       INT2_watchdogTimeout_b          = 4,
7107 +       INT2_watchdogTimeout_m          = 0x00000010,
7108 +       INT2_undecodedCpuWrite_b        = 5,
7109 +       INT2_undecodedCpuWrite_m        = 0x00000020,
7110 +       INT2_undecodedCpuRead_b         = 6,
7111 +       INT2_undecodedCpuRead_m         = 0x00000040,
7112 +       INT2_undecodedPciWrite_b        = 7,
7113 +       INT2_undecodedPciWrite_m        = 0x00000080,
7114 +       INT2_undecodedPciRead_b         = 8,
7115 +       INT2_undecodedPciRead_m         = 0x00000100,
7116 +       INT2_undecodedDmaWrite_b        = 9,
7117 +       INT2_undecodedDmaWrite_m        = 0x00000200,
7118 +       INT2_undecodedDmaRead_b         = 10,
7119 +       INT2_undecodedDmaRead_m         = 0x00000400,
7120 +       INT2_ipBusSlaveAckError_b       = 11,
7121 +       INT2_ipBusSlaveAckError_m       = 0x00000800,
7122 +
7123 +       INT3_dmaChannel0_b              = 0,
7124 +       INT3_dmaChannel0_m              = 0x00000001,
7125 +       INT3_dmaChannel1_b              = 1,
7126 +       INT3_dmaChannel1_m              = 0x00000002,
7127 +       INT3_dmaChannel2_b              = 2,
7128 +       INT3_dmaChannel2_m              = 0x00000004,
7129 +       INT3_dmaChannel3_b              = 3,
7130 +       INT3_dmaChannel3_m              = 0x00000008,
7131 +       INT3_dmaChannel4_b              = 4,
7132 +       INT3_dmaChannel4_m              = 0x00000010,
7133 +       INT3_dmaChannel5_b              = 5,
7134 +       INT3_dmaChannel5_m              = 0x00000020,
7135 +
7136 +       INT5_uartGeneral0_b             = 0,
7137 +       INT5_uartGeneral0_m             = 0x00000001,
7138 +       INT5_uartTxrdy0_b               = 1,
7139 +       INT5_uartTxrdy0_m               = 0x00000002,
7140 +       INT5_uartRxrdy0_b               = 2,
7141 +       INT5_uartRxrdy0_m               = 0x00000004,
7142 +       INT5_pci_b                      = 3,
7143 +       INT5_pci_m                      = 0x00000008,
7144 +       INT5_pciDecoupled_b             = 4,
7145 +       INT5_pciDecoupled_m             = 0x00000010,
7146 +       INT5_spi_b                      = 5,
7147 +       INT5_spi_m                      = 0x00000020,
7148 +       INT5_deviceDecoupled_b          = 6,
7149 +       INT5_deviceDecoupled_m          = 0x00000040,
7150 +       INT5_eth0Ovr_b                  = 9,
7151 +       INT5_eth0Ovr_m                  = 0x00000200,
7152 +       INT5_eth0Und_b                  = 10,
7153 +       INT5_eth0Und_m                  = 0x00000400,
7154 +       INT5_eth0Pfd_b                  = 11,
7155 +       INT5_eth0Pfd_m                  = 0x00000800,
7156 +       INT5_nvram_b                    = 12,
7157 +       INT5_nvram_m                    = 0x00001000,
7158 +
7159 +       INT6_gpio0_b                    = 0,
7160 +       INT6_gpio0_m                    = 0x00000001,
7161 +       INT6_gpio1_b                    = 1,
7162 +       INT6_gpio1_m                    = 0x00000002,
7163 +       INT6_gpio2_b                    = 2,
7164 +       INT6_gpio2_m                    = 0x00000004,
7165 +       INT6_gpio3_b                    = 3,
7166 +       INT6_gpio3_m                    = 0x00000008,
7167 +       INT6_gpio4_b                    = 4,
7168 +       INT6_gpio4_m                    = 0x00000010,
7169 +       INT6_gpio5_b                    = 5,
7170 +       INT6_gpio5_m                    = 0x00000020,
7171 +       INT6_gpio6_b                    = 6,
7172 +       INT6_gpio6_m                    = 0x00000040,
7173 +       INT6_gpio7_b                    = 7,
7174 +       INT6_gpio7_m                    = 0x00000080,
7175 +       INT6_gpio8_b                    = 8,
7176 +       INT6_gpio8_m                    = 0x00000100,
7177 +       INT6_gpio9_b                    = 9,
7178 +       INT6_gpio9_m                    = 0x00000200,
7179 +       INT6_gpio10_b                   = 10,
7180 +       INT6_gpio10_m                   = 0x00000400,
7181 +       INT6_gpio11_b                   = 11,
7182 +       INT6_gpio11_m                   = 0x00000800,
7183 +       INT6_gpio12_b                   = 12,
7184 +       INT6_gpio12_m                   = 0x00001000,
7185 +       INT6_gpio13_b                   = 13,
7186 +       INT6_gpio13_m                   = 0x00002000,
7187 +
7188 +       NMIPS_gpio_b                    = 0,
7189 +       NMIPS_gpio_m                    = 0x00000001,
7190 +} ;
7191 +
7192 +#endif // __IDT_INT_H__
7193 +
7194 +
7195 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h
7196 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h    1970-01-01 01:00:00.000000000 +0100
7197 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h       2006-06-18 12:44:28.000000000 +0200
7198 @@ -0,0 +1,111 @@
7199 +/**************************************************************************
7200 + *
7201 + *  BRIEF MODULE DESCRIPTION
7202 + *   IP Arbiter register definitions
7203 + *
7204 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
7205 + *
7206 + *  This program is free software; you can redistribute  it and/or modify it
7207 + *  under  the terms of  the GNU General  Public License as published by the
7208 + *  Free Software Foundation;  either version 2 of the  License, or (at your
7209 + *  option) any later version.
7210 + *
7211 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
7212 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
7213 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
7214 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
7215 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7216 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
7217 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7218 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
7219 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7220 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7221 + *
7222 + *  You should have received a copy of the  GNU General Public License along
7223 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
7224 + *  675 Mass Ave, Cambridge, MA 02139, USA.
7225 + *
7226 + *
7227 + **************************************************************************
7228 + * May 2004 rkt,neb
7229 + *
7230 + * Initial Release
7231 + *
7232 + *
7233 + *
7234 + **************************************************************************
7235 + */
7236 +
7237 +#ifndef __IDT_IPARB_H__
7238 +#define __IDT_IPARB_H__
7239 +
7240 +enum
7241 +{
7242 +       IPARB0_PhysicalAddress  = 0x18048000,
7243 +       IPARB_PhysicalAddress   = IPARB0_PhysicalAddress,       // Default
7244 +
7245 +       IPARB0_VirtualAddress   = 0xB8048000,
7246 +       IPARB_VirtualAddress    = IPARB0_VirtualAddress,        // Default
7247 +} ;
7248 +
7249 +enum
7250 +{
7251 +       IPABMXC_ethernet0Receive        = 0,
7252 +       IPABMXC_ethernet0Transmit       = 1,
7253 +       IPABMXC_memoryToHoldFifo        = 2,
7254 +       IPABMXC_holdFifoToMemory        = 3,
7255 +       IPABMXC_pciToMemory             = 4,
7256 +       IPABMXC_memoryToPci             = 5,
7257 +       IPABMXC_pciTarget               = 6,
7258 +       IPABMXC_pciTargetStart          = 7,
7259 +       IPABMXC_cpuToIpBus              = 8,
7260 +
7261 +       IPABMXC_Count,                          // Must be last in list !
7262 +       IPABMXC_Min                     = IPABMXC_ethernet0Receive,
7263 +
7264 +       IPAPXC_PriorityCount    = 4,            // 3-highest, 0-lowest.
7265 +} ;
7266 +
7267 +typedef struct
7268 +{
7269 +       u32     ipapc [IPAPXC_PriorityCount] ;  // ipapc[IPAPXC_] = IPAPC_
7270 +       u32     ipabmc [IPABMXC_Count] ;        // ipabmc[IPABMXC_] = IPABMC_
7271 +       u32     ipac ;                          // use IPAC_
7272 +       u32     ipaitcc;                        // use IPAITCC_
7273 +       u32     ipaspare ;
7274 +} volatile * IPARB_t ;
7275 +
7276 +enum
7277 +{
7278 +       IPAC_dp_b                       = 0,
7279 +       IPAC_dp_m                       = 0x00000001,
7280 +       IPAC_dep_b                      = 1,
7281 +       IPAC_dep_m                      = 0x00000002,
7282 +       IPAC_drm_b                      = 2,
7283 +       IPAC_drm_m                      = 0x00000004,
7284 +       IPAC_dwm_b                      = 3,
7285 +       IPAC_dwm_m                      = 0x00000008,
7286 +       IPAC_msk_b                      = 4,
7287 +       IPAC_msk_m                      = 0x00000010,
7288 +
7289 +       IPAPC_ptc_b                     = 0,
7290 +       IPAPC_ptc_m                     = 0x00003fff,
7291 +       IPAPC_mf_b                      = 14,
7292 +       IPAPC_mf_m                      = 0x00004000,
7293 +       IPAPC_cptc_b                    = 16,
7294 +       IPAPC_cptc_m                    = 0x3fff0000,
7295 +
7296 +       IPAITCC_itcc                    = 0,
7297 +       IPAITCC_itcc,                   = 0x000001ff,
7298 +
7299 +       IPABMC_mtc_b                    = 0,
7300 +       IPABMC_mtc_m                    = 0x00000fff,
7301 +       IPABMC_p_b                      = 12,
7302 +       IPABMC_p_m                      = 0x00003000,
7303 +       IPABMC_msk_b                    = 14,
7304 +       IPABMC_msk_m                    = 0x00004000,
7305 +       IPABMC_cmtc_b                   = 16,
7306 +       IPABMC_cmtc_m                   = 0x0fff0000,
7307 +};
7308 +
7309 +#endif // __IDT_IPARB_H__
7310 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h
7311 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_pci.h      1970-01-01 01:00:00.000000000 +0100
7312 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 2006-06-18 12:44:28.000000000 +0200
7313 @@ -0,0 +1,695 @@
7314 +/**************************************************************************
7315 + *
7316 + *  BRIEF MODULE DESCRIPTION
7317 + *   PCI register definitio
7318 + *
7319 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
7320 + *
7321 + *  This program is free software; you can redistribute  it and/or modify it
7322 + *  under  the terms of  the GNU General  Public License as published by the
7323 + *  Free Software Foundation;  either version 2 of the  License, or (at your
7324 + *  option) any later version.
7325 + *
7326 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
7327 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
7328 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
7329 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
7330 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7331 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
7332 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7333 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
7334 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7335 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7336 + *
7337 + *  You should have received a copy of the  GNU General Public License along
7338 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
7339 + *  675 Mass Ave, Cambridge, MA 02139, USA.
7340 + *
7341 + *
7342 + **************************************************************************
7343 + * May 2004 rkt, neb.
7344 + *
7345 + * Initial Release
7346 + *
7347 + *
7348 + *
7349 + **************************************************************************
7350 + */
7351 +
7352 +#ifndef __IDT_PCI_H__
7353 +#define __IDT_PCI_H__
7354 +
7355 +enum
7356 +{
7357 +       PCI0_PhysicalAddress    = 0x18080000,
7358 +       PCI_PhysicalAddress     = PCI0_PhysicalAddress,
7359 +
7360 +       PCI0_VirtualAddress     = 0xB8080000,
7361 +       PCI_VirtualAddress      = PCI0_VirtualAddress,
7362 +} ;
7363 +
7364 +enum
7365 +{
7366 +       PCI_LbaCount    = 4,            // Local base addresses.
7367 +} ;
7368 +
7369 +typedef struct
7370 +{
7371 +       u32     a ;             // Address.
7372 +       u32     c ;             // Control.
7373 +       u32     m ;             // mapping.
7374 +} PCI_Map_s ;
7375 +
7376 +typedef struct
7377 +{
7378 +       u32             pcic ;
7379 +       u32             pcis ;
7380 +       u32             pcism ;
7381 +       u32             pcicfga ;
7382 +       u32             pcicfgd ;
7383 +       PCI_Map_s       pcilba [PCI_LbaCount] ;
7384 +       u32             pcidac ;
7385 +       u32             pcidas ;
7386 +       u32             pcidasm ;
7387 +       u32             pcidad ;
7388 +       u32             pcidma8c ;
7389 +       u32             pcidma9c ;
7390 +       u32             pcitc ;
7391 +} volatile *PCI_t ;
7392 +
7393 +// PCI messaging unit.
7394 +enum
7395 +{
7396 +       PCIM_Count      = 2,
7397 +} ;
7398 +typedef struct
7399 +{
7400 +       u32             pciim [PCIM_Count] ;
7401 +       u32             pciom [PCIM_Count] ;
7402 +       u32             pciid ;
7403 +       u32             pciiic ;
7404 +       u32             pciiim ;
7405 +       u32             pciiod ;
7406 +       u32             pciioic ;
7407 +       u32             pciioim ;
7408 +} volatile *PCIM_t ;
7409 +
7410 +/*******************************************************************************
7411 + *
7412 + * PCI Control Register
7413 + *
7414 + ******************************************************************************/
7415 +enum
7416 +{
7417 +       PCIC_en_b       = 0,
7418 +       PCIC_en_m       = 0x00000001,
7419 +       PCIC_tnr_b      = 1,
7420 +       PCIC_tnr_m      = 0x00000002,
7421 +       PCIC_sce_b      = 2,
7422 +       PCIC_sce_m      = 0x00000004,
7423 +       PCIC_ien_b      = 3,
7424 +       PCIC_ien_m      = 0x00000008,
7425 +       PCIC_aaa_b      = 4,
7426 +       PCIC_aaa_m      = 0x00000010,
7427 +       PCIC_eap_b      = 5,
7428 +       PCIC_eap_m      = 0x00000020,
7429 +       PCIC_pcim_b     = 6,
7430 +       PCIC_pcim_m     = 0x000001c0,
7431 +               PCIC_pcim_disabled_v    = 0,
7432 +               PCIC_pcim_tnr_v         = 1,    // Satellite - target not ready
7433 +               PCIC_pcim_suspend_v     = 2,    // Satellite - suspended CPU.
7434 +               PCIC_pcim_extern_v      = 3,    // Host - external arbiter.
7435 +               PCIC_pcim_fixed_v       = 4,    // Host - fixed priority arb.
7436 +               PCIC_pcim_roundrobin_v  = 5,    // Host - round robin priority.
7437 +               PCIC_pcim_reserved6_v   = 6,
7438 +               PCIC_pcim_reserved7_v   = 7,
7439 +       PCIC_igm_b      = 9,
7440 +       PCIC_igm_m      = 0x00000200,
7441 +} ;
7442 +
7443 +/*******************************************************************************
7444 + *
7445 + * PCI Status Register
7446 + *
7447 + ******************************************************************************/
7448 +enum {
7449 +       PCIS_eed_b      = 0,
7450 +       PCIS_eed_m      = 0x00000001,
7451 +       PCIS_wr_b       = 1,
7452 +       PCIS_wr_m       = 0x00000002,
7453 +       PCIS_nmi_b      = 2,
7454 +       PCIS_nmi_m      = 0x00000004,
7455 +       PCIS_ii_b       = 3,
7456 +       PCIS_ii_m       = 0x00000008,
7457 +       PCIS_cwe_b      = 4,
7458 +       PCIS_cwe_m      = 0x00000010,
7459 +       PCIS_cre_b      = 5,
7460 +       PCIS_cre_m      = 0x00000020,
7461 +       PCIS_mdpe_b     = 6,
7462 +       PCIS_mdpe_m     = 0x00000040,
7463 +       PCIS_sta_b      = 7,
7464 +       PCIS_sta_m      = 0x00000080,
7465 +       PCIS_rta_b      = 8,
7466 +       PCIS_rta_m      = 0x00000100,
7467 +       PCIS_rma_b      = 9,
7468 +       PCIS_rma_m      = 0x00000200,
7469 +       PCIS_sse_b      = 10,
7470 +       PCIS_sse_m      = 0x00000400,
7471 +       PCIS_ose_b      = 11,
7472 +       PCIS_ose_m      = 0x00000800,
7473 +       PCIS_pe_b       = 12,
7474 +       PCIS_pe_m       = 0x00001000,
7475 +       PCIS_tae_b      = 13,
7476 +       PCIS_tae_m      = 0x00002000,
7477 +       PCIS_rle_b      = 14,
7478 +       PCIS_rle_m      = 0x00004000,
7479 +       PCIS_bme_b      = 15,
7480 +       PCIS_bme_m      = 0x00008000,
7481 +       PCIS_prd_b      = 16,
7482 +       PCIS_prd_m      = 0x00010000,
7483 +       PCIS_rip_b      = 17,
7484 +       PCIS_rip_m      = 0x00020000,
7485 +} ;
7486 +
7487 +/*******************************************************************************
7488 + *
7489 + * PCI Status Mask Register
7490 + *
7491 + ******************************************************************************/
7492 +enum {
7493 +       PCISM_eed_b             = 0,
7494 +       PCISM_eed_m             = 0x00000001,
7495 +       PCISM_wr_b              = 1,
7496 +       PCISM_wr_m              = 0x00000002,
7497 +       PCISM_nmi_b             = 2,
7498 +       PCISM_nmi_m             = 0x00000004,
7499 +       PCISM_ii_b              = 3,
7500 +       PCISM_ii_m              = 0x00000008,
7501 +       PCISM_cwe_b             = 4,
7502 +       PCISM_cwe_m             = 0x00000010,
7503 +       PCISM_cre_b             = 5,
7504 +       PCISM_cre_m             = 0x00000020,
7505 +       PCISM_mdpe_b            = 6,
7506 +       PCISM_mdpe_m            = 0x00000040,
7507 +       PCISM_sta_b             = 7,
7508 +       PCISM_sta_m             = 0x00000080,
7509 +       PCISM_rta_b             = 8,
7510 +       PCISM_rta_m             = 0x00000100,
7511 +       PCISM_rma_b             = 9,
7512 +       PCISM_rma_m             = 0x00000200,
7513 +       PCISM_sse_b             = 10,
7514 +       PCISM_sse_m             = 0x00000400,
7515 +       PCISM_ose_b             = 11,
7516 +       PCISM_ose_m             = 0x00000800,
7517 +       PCISM_pe_b              = 12,
7518 +       PCISM_pe_m              = 0x00001000,
7519 +       PCISM_tae_b             = 13,
7520 +       PCISM_tae_m             = 0x00002000,
7521 +       PCISM_rle_b             = 14,
7522 +       PCISM_rle_m             = 0x00004000,
7523 +       PCISM_bme_b             = 15,
7524 +       PCISM_bme_m             = 0x00008000,
7525 +       PCISM_prd_b             = 16,
7526 +       PCISM_prd_m             = 0x00010000,
7527 +       PCISM_rip_b             = 17,
7528 +       PCISM_rip_m             = 0x00020000,
7529 +} ;
7530 +
7531 +/*******************************************************************************
7532 + *
7533 + * PCI Configuration Address Register
7534 + *
7535 + ******************************************************************************/
7536 +enum {
7537 +       PCICFGA_reg_b           = 2,
7538 +       PCICFGA_reg_m           = 0x000000fc,
7539 +               PCICFGA_reg_id_v        = 0x00>>2, //use PCFGID_
7540 +               PCICFGA_reg_04_v        = 0x04>>2, //use PCFG04_
7541 +               PCICFGA_reg_08_v        = 0x08>>2, //use PCFG08_
7542 +               PCICFGA_reg_0C_v        = 0x0C>>2, //use PCFG0C_
7543 +               PCICFGA_reg_pba0_v      = 0x10>>2, //use PCIPBA_
7544 +               PCICFGA_reg_pba1_v      = 0x14>>2, //use PCIPBA_
7545 +               PCICFGA_reg_pba2_v      = 0x18>>2, //use PCIPBA_
7546 +               PCICFGA_reg_pba3_v      = 0x1c>>2, //use PCIPBA_
7547 +               PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
7548 +               PCICFGA_reg_3C_v        = 0x3C>>2, //use PCFG3C_
7549 +               PCICFGA_reg_pba0c_v     = 0x44>>2, //use PCIPBAC_
7550 +               PCICFGA_reg_pba0m_v     = 0x48>>2,
7551 +               PCICFGA_reg_pba1c_v     = 0x4c>>2, //use PCIPBAC_
7552 +               PCICFGA_reg_pba1m_v     = 0x50>>2,
7553 +               PCICFGA_reg_pba2c_v     = 0x54>>2, //use PCIPBAC_
7554 +               PCICFGA_reg_pba2m_v     = 0x58>>2,
7555 +               PCICFGA_reg_pba3c_v     = 0x5c>>2, //use PCIPBAC_
7556 +               PCICFGA_reg_pba3m_v     = 0x60>>2,
7557 +               PCICFGA_reg_pmgt_v      = 0x64>>2,
7558 +       PCICFGA_func_b          = 8,
7559 +       PCICFGA_func_m          = 0x00000700,
7560 +       PCICFGA_dev_b           = 11,
7561 +       PCICFGA_dev_m           = 0x0000f800,
7562 +               PCICFGA_dev_internal_v  = 0,
7563 +       PCICFGA_bus_b           = 16,
7564 +       PCICFGA_bus_m           = 0x00ff0000,
7565 +               PCICFGA_bus_type0_v     = 0,    //local bus
7566 +       PCICFGA_en_b            = 31,           // read only
7567 +       PCICFGA_en_m            = 0x80000000,
7568 +} ;
7569 +
7570 +enum {
7571 +       PCFGID_vendor_b         = 0,
7572 +       PCFGID_vendor_m         = 0x0000ffff,
7573 +               PCFGID_vendor_IDT_v             = 0x111d,
7574 +       PCFGID_device_b         = 16,
7575 +       PCFGID_device_m         = 0xffff0000,
7576 +               PCFGID_device_Korinade_v        = 0x0214,
7577 +
7578 +       PCFG04_command_ioena_b          = 1,
7579 +       PCFG04_command_ioena_m          = 0x00000001,
7580 +       PCFG04_command_memena_b         = 2,
7581 +       PCFG04_command_memena_m         = 0x00000002,
7582 +       PCFG04_command_bmena_b          = 3,
7583 +       PCFG04_command_bmena_m          = 0x00000004,
7584 +       PCFG04_command_mwinv_b          = 5,
7585 +       PCFG04_command_mwinv_m          = 0x00000010,
7586 +       PCFG04_command_parena_b         = 7,
7587 +       PCFG04_command_parena_m         = 0x00000040,
7588 +       PCFG04_command_serrena_b        = 9,
7589 +       PCFG04_command_serrena_m        = 0x00000100,
7590 +       PCFG04_command_fastbbena_b      = 10,
7591 +       PCFG04_command_fastbbena_m      = 0x00000200,
7592 +       PCFG04_status_b                 = 16,
7593 +       PCFG04_status_m                 = 0xffff0000,
7594 +       PCFG04_status_66MHz_b           = 21,   // 66 MHz enable
7595 +       PCFG04_status_66MHz_m           = 0x00200000,
7596 +       PCFG04_status_fbb_b             = 23,
7597 +       PCFG04_status_fbb_m             = 0x00800000,
7598 +       PCFG04_status_mdpe_b            = 24,
7599 +       PCFG04_status_mdpe_m            = 0x01000000,
7600 +       PCFG04_status_dst_b             = 25,
7601 +       PCFG04_status_dst_m             = 0x06000000,
7602 +       PCFG04_status_sta_b             = 27,
7603 +       PCFG04_status_sta_m             = 0x08000000,
7604 +       PCFG04_status_rta_b             = 28,
7605 +       PCFG04_status_rta_m             = 0x10000000,
7606 +       PCFG04_status_rma_b             = 29,
7607 +       PCFG04_status_rma_m             = 0x20000000,
7608 +       PCFG04_status_sse_b             = 30,
7609 +       PCFG04_status_sse_m             = 0x40000000,
7610 +       PCFG04_status_pe_b              = 31,
7611 +       PCFG04_status_pe_m              = 0x40000000,
7612 +
7613 +       PCFG08_revId_b                  = 0,
7614 +       PCFG08_revId_m                  = 0x000000ff,
7615 +       PCFG08_classCode_b              = 0,
7616 +       PCFG08_classCode_m              = 0xffffff00,
7617 +               PCFG08_classCode_bridge_v       = 06,
7618 +               PCFG08_classCode_proc_v         = 0x0b3000, // processor-MIPS
7619 +       PCFG0C_cacheline_b              = 0,
7620 +       PCFG0C_cacheline_m              = 0x000000ff,
7621 +       PCFG0C_masterLatency_b          = 8,
7622 +       PCFG0C_masterLatency_m          = 0x0000ff00,
7623 +       PCFG0C_headerType_b             = 16,
7624 +       PCFG0C_headerType_m             = 0x00ff0000,
7625 +       PCFG0C_bist_b                   = 24,
7626 +       PCFG0C_bist_m                   = 0xff000000,
7627 +
7628 +       PCIPBA_msi_b                    = 0,
7629 +       PCIPBA_msi_m                    = 0x00000001,
7630 +       PCIPBA_p_b                      = 3,
7631 +       PCIPBA_p_m                      = 0x00000004,
7632 +       PCIPBA_baddr_b                  = 8,
7633 +       PCIPBA_baddr_m                  = 0xffffff00,
7634 +
7635 +       PCFGSS_vendorId_b               = 0,
7636 +       PCFGSS_vendorId_m               = 0x0000ffff,
7637 +       PCFGSS_id_b                     = 16,
7638 +       PCFGSS_id_m                     = 0xffff0000,
7639 +
7640 +       PCFG3C_interruptLine_b          = 0,
7641 +       PCFG3C_interruptLine_m          = 0x000000ff,
7642 +       PCFG3C_interruptPin_b           = 8,
7643 +       PCFG3C_interruptPin_m           = 0x0000ff00,
7644 +       PCFG3C_minGrant_b               = 16,
7645 +       PCFG3C_minGrant_m               = 0x00ff0000,
7646 +       PCFG3C_maxLat_b                 = 24,
7647 +       PCFG3C_maxLat_m                 = 0xff000000,
7648 +
7649 +       PCIPBAC_msi_b                   = 0,
7650 +       PCIPBAC_msi_m                   = 0x00000001,
7651 +       PCIPBAC_p_b                     = 1,
7652 +       PCIPBAC_p_m                     = 0x00000002,
7653 +       PCIPBAC_size_b                  = 2,
7654 +       PCIPBAC_size_m                  = 0x0000007c,
7655 +       PCIPBAC_sb_b                    = 7,
7656 +       PCIPBAC_sb_m                    = 0x00000080,
7657 +       PCIPBAC_pp_b                    = 8,
7658 +       PCIPBAC_pp_m                    = 0x00000100,
7659 +       PCIPBAC_mr_b                    = 9,
7660 +       PCIPBAC_mr_m                    = 0x00000600,
7661 +               PCIPBAC_mr_read_v       =0,     //no prefetching
7662 +               PCIPBAC_mr_readLine_v   =1,
7663 +               PCIPBAC_mr_readMult_v   =2,
7664 +       PCIPBAC_mrl_b                   = 11,
7665 +       PCIPBAC_mrl_m                   = 0x00000800,
7666 +       PCIPBAC_mrm_b                   = 12,
7667 +       PCIPBAC_mrm_m                   = 0x00001000,
7668 +       PCIPBAC_trp_b                   = 13,
7669 +       PCIPBAC_trp_m                   = 0x00002000,
7670 +
7671 +       PCFG40_trdyTimeout_b            = 0,
7672 +       PCFG40_trdyTimeout_m            = 0x000000ff,
7673 +       PCFG40_retryLim_b               = 8,
7674 +       PCFG40_retryLim_m               = 0x0000ff00,
7675 +};
7676 +
7677 +/*******************************************************************************
7678 + *
7679 + * PCI Local Base Address [0|1|2|3] Register
7680 + *
7681 + ******************************************************************************/
7682 +enum {
7683 +       PCILBA_baddr_b          = 0,            // In PCI_t -> pcilba [] .a
7684 +       PCILBA_baddr_m          = 0xffffff00,
7685 +} ;
7686 +/*******************************************************************************
7687 + *
7688 + * PCI Local Base Address Control Register
7689 + *
7690 + ******************************************************************************/
7691 +enum {
7692 +       PCILBAC_msi_b           = 0,            // In pPci->pcilba[i].c
7693 +       PCILBAC_msi_m           = 0x00000001,
7694 +               PCILBAC_msi_mem_v       = 0,
7695 +               PCILBAC_msi_io_v        = 1,
7696 +       PCILBAC_size_b          = 2,    // In pPci->pcilba[i].c
7697 +       PCILBAC_size_m          = 0x0000007c,
7698 +       PCILBAC_sb_b            = 7,    // In pPci->pcilba[i].c
7699 +       PCILBAC_sb_m            = 0x00000080,
7700 +       PCILBAC_rt_b            = 8,    // In pPci->pcilba[i].c
7701 +       PCILBAC_rt_m            = 0x00000100,
7702 +               PCILBAC_rt_noprefetch_v = 0, // mem read
7703 +               PCILBAC_rt_prefetch_v   = 1, // mem readline
7704 +} ;
7705 +
7706 +/*******************************************************************************
7707 + *
7708 + * PCI Local Base Address [0|1|2|3] Mapping Register
7709 + *
7710 + ******************************************************************************/
7711 +enum {
7712 +       PCILBAM_maddr_b         = 8,
7713 +       PCILBAM_maddr_m         = 0xffffff00,
7714 +} ;
7715 +
7716 +/*******************************************************************************
7717 + *
7718 + * PCI Decoupled Access Control Register
7719 + *
7720 + ******************************************************************************/
7721 +enum {
7722 +       PCIDAC_den_b            = 0,
7723 +       PCIDAC_den_m            = 0x00000001,
7724 +} ;
7725 +
7726 +/*******************************************************************************
7727 + *
7728 + * PCI Decoupled Access Status Register
7729 + *
7730 + ******************************************************************************/
7731 +enum {
7732 +       PCIDAS_d_b      = 0,
7733 +       PCIDAS_d_m      = 0x00000001,
7734 +       PCIDAS_b_b      = 1,
7735 +       PCIDAS_b_m      = 0x00000002,
7736 +       PCIDAS_e_b      = 2,
7737 +       PCIDAS_e_m      = 0x00000004,
7738 +       PCIDAS_ofe_b    = 3,
7739 +       PCIDAS_ofe_m    = 0x00000008,
7740 +       PCIDAS_off_b    = 4,
7741 +       PCIDAS_off_m    = 0x00000010,
7742 +       PCIDAS_ife_b    = 5,
7743 +       PCIDAS_ife_m    = 0x00000020,
7744 +       PCIDAS_iff_b    = 6,
7745 +       PCIDAS_iff_m    = 0x00000040,
7746 +} ;
7747 +
7748 +/*******************************************************************************
7749 + *
7750 + * PCI DMA Channel 8 Configuration Register
7751 + *
7752 + ******************************************************************************/
7753 +enum
7754 +{
7755 +       PCIDMA8C_mbs_b  = 0,            // Maximum Burst Size.
7756 +       PCIDMA8C_mbs_m  = 0x00000fff,   // { pcidma8c }
7757 +       PCIDMA8C_our_b  = 12,           // Optimize Unaligned Burst Reads.
7758 +       PCIDMA8C_our_m  = 0x00001000,   // { pcidma8c }
7759 +} ;
7760 +
7761 +/*******************************************************************************
7762 + *
7763 + * PCI DMA Channel 9 Configuration Register
7764 + *
7765 + ******************************************************************************/
7766 +enum
7767 +{
7768 +       PCIDMA9C_mbs_b  = 0,            // Maximum Burst Size.
7769 +       PCIDMA9C_mbs_m  = 0x00000fff, // { pcidma9c }
7770 +} ;
7771 +
7772 +/*******************************************************************************
7773 + *
7774 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
7775 + *
7776 + ******************************************************************************/
7777 +enum {
7778 +       PCIDMAD_pt_b            = 22,           // in DEVCMD field (descriptor)
7779 +       PCIDMAD_pt_m            = 0x00c00000,   // preferred transaction field
7780 +               // These are for reads (DMA channel 8)
7781 +               PCIDMAD_devcmd_mr_v     = 0,    //memory read
7782 +               PCIDMAD_devcmd_mrl_v    = 1,    //memory read line
7783 +               PCIDMAD_devcmd_mrm_v    = 2,    //memory read multiple
7784 +               PCIDMAD_devcmd_ior_v    = 3,    //I/O read
7785 +               // These are for writes (DMA channel 9)
7786 +               PCIDMAD_devcmd_mw_v     = 0,    //memory write
7787 +               PCIDMAD_devcmd_mwi_v    = 1,    //memory write invalidate
7788 +               PCIDMAD_devcmd_iow_v    = 3,    //I/O write
7789 +
7790 +       // Swap byte field applies to both DMA channel 8 and 9
7791 +       PCIDMAD_sb_b            = 24,           // in DEVCMD field (descriptor)
7792 +       PCIDMAD_sb_m            = 0x01000000,   // swap byte field
7793 +} ;
7794 +
7795 +
7796 +/*******************************************************************************
7797 + *
7798 + * PCI Target Control Register
7799 + *
7800 + ******************************************************************************/
7801 +enum
7802 +{
7803 +       PCITC_rtimer_b          = 0,            // In PCITC_t -> pcitc
7804 +       PCITC_rtimer_m          = 0x000000ff,
7805 +       PCITC_dtimer_b          = 8,            // In PCITC_t -> pcitc
7806 +       PCITC_dtimer_m          = 0x0000ff00,
7807 +       PCITC_rdr_b             = 18,           // In PCITC_t -> pcitc
7808 +       PCITC_rdr_m             = 0x00040000,
7809 +       PCITC_ddt_b             = 19,           // In PCITC_t -> pcitc
7810 +       PCITC_ddt_m             = 0x00080000,
7811 +} ;
7812 +/*******************************************************************************
7813 + *
7814 + * PCI messaging unit [applies to both inbound and outbound registers ]
7815 + *
7816 + ******************************************************************************/
7817 +enum
7818 +{
7819 +       PCIM_m0_b       = 0,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7820 +       PCIM_m0_m       = 0x00000001,   // inbound or outbound message 0
7821 +       PCIM_m1_b       = 1,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7822 +       PCIM_m1_m       = 0x00000002,   // inbound or outbound message 1
7823 +       PCIM_db_b       = 2,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7824 +       PCIM_db_m       = 0x00000004,   // inbound or outbound doorbell
7825 +};
7826 +
7827 +
7828 +
7829 +
7830 +
7831 +
7832 +#define PCI_MSG_VirtualAddress      0xB8088010
7833 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
7834 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
7835 +
7836 +#define PCIM_SHFT              0x6
7837 +#define PCIM_BIT_LEN           0x7
7838 +#define PCIM_H_EA              0x3
7839 +#define PCIM_H_IA_FIX          0x4
7840 +#define PCIM_H_IA_RR           0x5
7841 +#if 0
7842 +#define PCI_ADDR_START         0x13000000
7843 +#endif
7844 +
7845 +#define PCI_ADDR_START         0x50000000
7846 +
7847 +#define CPUTOPCI_MEM_WIN       0x02000000
7848 +#define CPUTOPCI_IO_WIN                0x00100000
7849 +#define PCILBA_SIZE_SHFT       2
7850 +#define PCILBA_SIZE_MASK       0x1F
7851 +#define SIZE_256MB             0x1C
7852 +#define SIZE_128MB             0x1B
7853 +#define SIZE_64MB               0x1A
7854 +#define SIZE_32MB              0x19
7855 +#define SIZE_16MB               0x18
7856 +#define SIZE_4MB               0x16
7857 +#define SIZE_2MB               0x15
7858 +#define SIZE_1MB               0x14
7859 +#define KORINA_CONFIG0_ADDR    0x80000000
7860 +#define KORINA_CONFIG1_ADDR    0x80000004
7861 +#define KORINA_CONFIG2_ADDR    0x80000008
7862 +#define KORINA_CONFIG3_ADDR    0x8000000C
7863 +#define KORINA_CONFIG4_ADDR    0x80000010
7864 +#define KORINA_CONFIG5_ADDR    0x80000014
7865 +#define KORINA_CONFIG6_ADDR    0x80000018
7866 +#define KORINA_CONFIG7_ADDR    0x8000001C
7867 +#define KORINA_CONFIG8_ADDR    0x80000020
7868 +#define KORINA_CONFIG9_ADDR    0x80000024
7869 +#define KORINA_CONFIG10_ADDR   0x80000028
7870 +#define KORINA_CONFIG11_ADDR   0x8000002C
7871 +#define KORINA_CONFIG12_ADDR   0x80000030
7872 +#define KORINA_CONFIG13_ADDR   0x80000034
7873 +#define KORINA_CONFIG14_ADDR   0x80000038
7874 +#define KORINA_CONFIG15_ADDR   0x8000003C
7875 +#define KORINA_CONFIG16_ADDR   0x80000040
7876 +#define KORINA_CONFIG17_ADDR   0x80000044
7877 +#define KORINA_CONFIG18_ADDR   0x80000048
7878 +#define KORINA_CONFIG19_ADDR   0x8000004C
7879 +#define KORINA_CONFIG20_ADDR   0x80000050
7880 +#define KORINA_CONFIG21_ADDR   0x80000054
7881 +#define KORINA_CONFIG22_ADDR   0x80000058
7882 +#define KORINA_CONFIG23_ADDR   0x8000005C
7883 +#define KORINA_CONFIG24_ADDR   0x80000060
7884 +#define KORINA_CONFIG25_ADDR   0x80000064
7885 +#define KORINA_CMD             (PCFG04_command_ioena_m | \
7886 +                                PCFG04_command_memena_m | \
7887 +                                PCFG04_command_bmena_m | \
7888 +                                PCFG04_command_mwinv_m | \
7889 +                                PCFG04_command_parena_m | \
7890 +                                PCFG04_command_serrena_m )
7891 +
7892 +#define KORINA_STAT            (PCFG04_status_mdpe_m | \
7893 +                                PCFG04_status_sta_m  | \
7894 +                                PCFG04_status_rta_m  | \
7895 +                                PCFG04_status_rma_m  | \
7896 +                                PCFG04_status_sse_m  | \
7897 +                                PCFG04_status_pe_m)
7898 +
7899 +#define KORINA_CNFG1           ((KORINA_STAT<<16)|KORINA_CMD)
7900 +
7901 +#define KORINA_REVID           0
7902 +#define KORINA_CLASS_CODE      0
7903 +#define KORINA_CNFG2           ((KORINA_CLASS_CODE<<8) | \
7904 +                                 KORINA_REVID)
7905 +
7906 +#define KORINA_CACHE_LINE_SIZE 4
7907 +#define KORINA_MASTER_LAT      0x3c
7908 +#define KORINA_HEADER_TYPE     0
7909 +#define KORINA_BIST            0
7910 +
7911 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
7912 +                     (KORINA_HEADER_TYPE<<16) | \
7913 +                     (KORINA_MASTER_LAT<<8) | \
7914 +                     KORINA_CACHE_LINE_SIZE )
7915 +
7916 +#define KORINA_BAR0    0x00000008 /* 128 MB Memory */
7917 +#define KORINA_BAR1    0x18800001 /* 1 MB IO */
7918 +#define KORINA_BAR2    0x18000001 /* 2 MB IO window for Korina
7919 +                                       internal Registers */
7920 +#define KORINA_BAR3    0x48000008 /* Spare 128 MB Memory */
7921 +
7922 +#define KORINA_CNFG4   KORINA_BAR0
7923 +#define KORINA_CNFG5    KORINA_BAR1
7924 +#define KORINA_CNFG6   KORINA_BAR2
7925 +#define KORINA_CNFG7   KORINA_BAR3
7926 +
7927 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
7928 +#define KORINA_SUBSYSTEM_ID    0x0214
7929 +#define KORINA_CNFG8           0
7930 +#define KORINA_CNFG9           0
7931 +#define KORINA_CNFG10          0
7932 +#define KORINA_CNFG11  ((KORINA_SUBSYS_VENDOR_ID<<16) | \
7933 +                         KORINA_SUBSYSTEM_ID)
7934 +#define KORINA_INT_LINE                1
7935 +#define KORINA_INT_PIN         1
7936 +#define KORINA_MIN_GNT         8
7937 +#define KORINA_MAX_LAT         0x38
7938 +#define KORINA_CNFG12          0
7939 +#define KORINA_CNFG13          0
7940 +#define KORINA_CNFG14          0
7941 +#define KORINA_CNFG15  ((KORINA_MAX_LAT<<24) | \
7942 +                        (KORINA_MIN_GNT<<16) | \
7943 +                        (KORINA_INT_PIN<<8)  | \
7944 +                         KORINA_INT_LINE)
7945 +#define        KORINA_RETRY_LIMIT      0x80
7946 +#define KORINA_TRDY_LIMIT      0x80
7947 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
7948 +                       KORINA_TRDY_LIMIT)
7949 +#define PCI_PBAxC_R            0x0
7950 +#define PCI_PBAxC_RL           0x1
7951 +#define PCI_PBAxC_RM           0x2
7952 +#define SIZE_SHFT              2
7953 +
7954 +#if defined(__MIPSEB__)
7955 +#define KORINA_PBA0C   ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
7956 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7957 +                         PCIPBAC_pp_m | \
7958 +                         (SIZE_128MB<<SIZE_SHFT) | \
7959 +                          PCIPBAC_p_m)
7960 +#else
7961 +#define KORINA_PBA0C   ( PCIPBAC_mrl_m | \
7962 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7963 +                         PCIPBAC_pp_m | \
7964 +                         (SIZE_128MB<<SIZE_SHFT) | \
7965 +                          PCIPBAC_p_m)
7966 +#endif
7967 +#define KORINA_CNFG17  KORINA_PBA0C
7968 +#define KORINA_PBA0M   0x0
7969 +#define KORINA_CNFG18  KORINA_PBA0M
7970 +
7971 +#if defined(__MIPSEB__)
7972 +#define KORINA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7973 +                         PCIPBAC_msi_m)
7974 +#else
7975 +#define KORINA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | \
7976 +                         PCIPBAC_msi_m)
7977 +#endif
7978 +#define KORINA_CNFG19  KORINA_PBA1C
7979 +#define KORINA_PBA1M   0x0
7980 +#define KORINA_CNFG20  KORINA_PBA1M
7981 +
7982 +#if defined(__MIPSEB__)
7983 +#define KORINA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7984 +                         PCIPBAC_msi_m)
7985 +#else
7986 +#define KORINA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | \
7987 +                         PCIPBAC_msi_m)
7988 +#endif
7989 +#define KORINA_CNFG21  KORINA_PBA2C
7990 +#define KORINA_PBA2M   0x18000000
7991 +#define KORINA_CNFG22  KORINA_PBA2M
7992 +#define KORINA_PBA3C   0
7993 +#define KORINA_CNFG23  KORINA_PBA3C
7994 +#define KORINA_PBA3M   0
7995 +#define KORINA_CNFG24  KORINA_PBA3M
7996 +
7997 +
7998 +
7999 +#define        PCITC_DTIMER_VAL        8
8000 +#define PCITC_RTIMER_VAL       0x10
8001 +
8002 +
8003 +
8004 +
8005 +#endif // __IDT_PCI_H__
8006 +
8007 +
8008 +
8009 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_rst.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h
8010 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_rst.h      1970-01-01 01:00:00.000000000 +0100
8011 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 2006-06-18 12:44:28.000000000 +0200
8012 @@ -0,0 +1,119 @@
8013 +/**************************************************************************
8014 + *
8015 + *  BRIEF MODULE DESCRIPTION
8016 + *   Reset register definitions.
8017 + *
8018 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8019 + *
8020 + *  This program is free software; you can redistribute  it and/or modify it
8021 + *  under  the terms of  the GNU General  Public License as published by the
8022 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8023 + *  option) any later version.
8024 + *
8025 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8026 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8027 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8028 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8029 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8030 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8031 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8032 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8033 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8034 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8035 + *
8036 + *  You should have received a copy of the  GNU General Public License along
8037 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8038 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8039 + *
8040 + *
8041 + **************************************************************************
8042 + * May 2004 rkt, neb.
8043 + *
8044 + * Initial Release
8045 + *
8046 + *
8047 + *
8048 + **************************************************************************
8049 + */
8050 +
8051 +#ifndef __IDT_RST_H__
8052 +#define __IDT_RST_H__
8053 +
8054 +enum
8055 +{
8056 +       RST0_PhysicalAddress    = 0x18000000,
8057 +       RST_PhysicalAddress     = RST0_PhysicalAddress,         // Default
8058 +
8059 +       RST0_VirtualAddress     = 0xb8000000,
8060 +       RST_VirtualAddress      = RST0_VirtualAddress,          // Default
8061 +} ;
8062 +
8063 +typedef struct RST_s
8064 +{
8065 +       u32     filler [0x0006] ;
8066 +       u32     sysid ;
8067 +       u32     filler2 [0x2000-8] ;            // Pad out to offset 0x8000
8068 +       u32     reset ;
8069 +       u32     bcv ;
8070 +       u32     cea ;
8071 +} volatile * RST_t ;
8072 +
8073 +enum
8074 +{
8075 +       SYSID_rev_b             = 0,
8076 +       SYSID_rev_m             = 0x000000ff,
8077 +       SYSID_imp_b             = 8,
8078 +       SYSID_imp_m             = 0x000fff00,
8079 +       SYSID_vendor_b          = 8,
8080 +       SYSID_vendor_m          = 0xfff00000,
8081 +
8082 +       BCV_pll_b               = 0,
8083 +       BCV_pll_m               = 0x0000000f,
8084 +               BCV_pll_PLLBypass_v     = 0x0,  // PCLK=1*CLK.
8085 +               BCV_pll_Mul3_v          = 0x1,  // PCLK=3*CLK.
8086 +               BCV_pll_Mul4_v          = 0x2,  // PCLK=4*CLK.
8087 +               BCV_pll_SlowMul5_v      = 0x3,  // PCLK=5*CLK.
8088 +               BCV_pll_Mul5_v          = 0x4,  // PCLK=5*CLK.
8089 +               BCV_pll_SlowMul6_v      = 0x5,  // PCLK=6*CLK.
8090 +               BCV_pll_Mul6_v          = 0x6,  // PCLK=6*CLK.
8091 +               BCV_pll_Mul8_v          = 0x7,  // PCLK=8*CLK.
8092 +               BCV_pll_Mul10_v         = 0x8,  // PCLK=10*CLK.
8093 +               BCV_pll_Res9_v          = 0x9,
8094 +               BCV_pll_Res10_v         = 0xa,
8095 +               BCV_pll_Res11_v         = 0xb,
8096 +               BCV_pll_Res12_v         = 0xc,
8097 +               BCV_pll_Res13_v         = 0xd,
8098 +               BCV_pll_Res14_v         = 0xe,
8099 +               BCV_pll_Res15_v         = 0xf,
8100 +       BCV_clkDiv_b            = 4,
8101 +       BCV_clkDiv_m            = 0x00000030,
8102 +               BCV_clkDiv_Div1_v       = 0x0,
8103 +               BCV_clkDiv_Div2_v       = 0x1,
8104 +               BCV_clkDiv_Div4_v       = 0x2,
8105 +               BCV_clkDiv_Res3_v       = 0x3,
8106 +       BCV_bigEndian_b         = 6,
8107 +       BCV_bigEndian_m         = 0x00000040,
8108 +       BCV_resetFast_b         = 7,
8109 +       BCV_resetFast_m         = 0x00000080,
8110 +       BCV_pciMode_b           = 8,
8111 +       BCV_pciMode_m           = 0x00000700,
8112 +               BCV_pciMode_disabled_v  = 0,    // PCI is disabled.
8113 +               BCV_pciMode_tnr_v       = 1,    // satellite Target Not Ready.
8114 +               BCV_pciMode_suspended_v = 2,    // satellite with suspended CPU.
8115 +               BCV_pciMode_external_v  = 3,    // host, external arbiter.
8116 +               BCV_pciMode_fixed_v     = 4,    // host, fixed priority arbiter.
8117 +               BCV_pciMode_roundRobin_v= 5,    // host, round robin arbiter.
8118 +               BCV_pciMode_res6_v      = 6,
8119 +               BCV_pciMode_res7_v      = 7,
8120 +       BCV_watchDisable_b      = 11,
8121 +       BCV_watchDisable_m      = 0x00000800,
8122 +       BCV_res12_b             = 12,
8123 +       BCV_res12_m             = 0x00001000,
8124 +       BCV_res13_b             = 13,
8125 +       BCV_res13_m             = 0x00002000,
8126 +       BCV_res14_b             = 14,
8127 +       BCV_res14_m             = 0x00004000,
8128 +       BCV_res15_b             = 15,
8129 +       BCV_res15_m             = 0x00008000,
8130 +} ;
8131 +#endif // __IDT_RST_H__
8132 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_spi.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h
8133 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_spi.h      1970-01-01 01:00:00.000000000 +0100
8134 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 2006-06-18 12:44:28.000000000 +0200
8135 @@ -0,0 +1,120 @@
8136 +/**************************************************************************
8137 + *
8138 + *  BRIEF MODULE DESCRIPTION
8139 + *   Serial Peripheral Interface register definitions.
8140 + *
8141 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8142 + *
8143 + *  This program is free software; you can redistribute  it and/or modify it
8144 + *  under  the terms of  the GNU General  Public License as published by the
8145 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8146 + *  option) any later version.
8147 + *
8148 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8149 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8150 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8151 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8152 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8153 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8154 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8155 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8156 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8157 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8158 + *
8159 + *  You should have received a copy of the  GNU General Public License along
8160 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8161 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8162 + *
8163 + *
8164 + **************************************************************************
8165 + * May 2004 rkt, neb.
8166 + *
8167 + * Initial Release
8168 + *
8169 + *
8170 + *
8171 + **************************************************************************
8172 + */
8173 +
8174 +#ifndef __IDT_SPI_H__
8175 +#define __IDT_SPI_H__
8176 +
8177 +enum
8178 +{
8179 +       SPI0_PhysicalAddress    = 0x18070000,
8180 +       SPI_PhysicalAddress     = SPI0_PhysicalAddress,
8181 +
8182 +       SPI0_VirtualAddress     = 0xB8070000,
8183 +       SPI_VirtualAddress      = SPI0_VirtualAddress,
8184 +} ;
8185 +
8186 +typedef struct
8187 +{
8188 +       u32 spcp ;      // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
8189 +       u32 spc ;       // spi control reg use SPC_
8190 +       u32 sps ;       // spi status reg use SPS_
8191 +       u32 spd ;       // spi data reg use SPD_
8192 +       u32 siofunc ;   // serial IO function use SIOFUNC_
8193 +       u32 siocfg ;    // serial IO config use SIOCFG_
8194 +       u32 siod;       // serial IO data use SIOD_
8195 +} volatile *SPI_t ;
8196 +
8197 +enum
8198 +{
8199 +       SPCP_div_b       = 0,
8200 +       SPCP_div_m       = 0x000000ff,
8201 +       SPC_spr_b       = 0,
8202 +       SPC_spr_m       = 0x00000003,
8203 +            SPC_spr_div2_v  = 0,
8204 +            SPC_spr_div4_v  = 1,
8205 +            SPC_spr_div16_v = 2,
8206 +            SPC_spr_div32_v = 3,
8207 +       SPC_cpha_b      = 2,
8208 +       SPC_cpha_m      = 0x00000004,
8209 +       SPC_cpol_b      = 3,
8210 +       SPC_cpol_m      = 0x00000008,
8211 +       SPC_mstr_b      = 4,
8212 +       SPC_mstr_m      = 0x00000010,
8213 +       SPC_spe_b       = 6,
8214 +       SPC_spe_m       = 0x00000040,
8215 +       SPC_spie_b      = 7,
8216 +       SPC_spie_m      = 0x00000080,
8217 +
8218 +       SPS_modf_b      = 4,
8219 +       SPS_modf_m      = 0x00000010,
8220 +       SPS_wcol_b      = 6,
8221 +       SPS_wcol_m      = 0x00000040,
8222 +       SPS_spif_b      = 7,
8223 +       SPS_spif_m      = 0x00000070,
8224 +
8225 +       SPD_data_b      = 0,
8226 +       SPD_data_m      = 0x000000ff,
8227 +
8228 +       SIOFUNC_sdo_b       = 0,
8229 +       SIOFUNC_sdo_m       = 0x00000001,
8230 +       SIOFUNC_sdi_b       = 1,
8231 +       SIOFUNC_sdi_m       = 0x00000002,
8232 +       SIOFUNC_sck_b       = 2,
8233 +       SIOFUNC_sck_m       = 0x00000004,
8234 +       SIOFUNC_pci_b       = 3,
8235 +       SIOFUNC_pci_m       = 0x00000008,
8236 +
8237 +       SIOCFG_sdo_b       = 0,
8238 +       SIOCFG_sdo_m       = 0x00000001,
8239 +       SIOCFG_sdi_b       = 1,
8240 +       SIOCFG_sdi_m       = 0x00000002,
8241 +       SIOCFG_sck_b       = 2,
8242 +       SIOCFG_sck_m       = 0x00000004,
8243 +       SIOCFG_pci_b       = 3,
8244 +       SIOCFG_pci_m       = 0x00000008,
8245 +
8246 +       SIOD_sdo_b       = 0,
8247 +       SIOD_sdo_m       = 0x00000001,
8248 +       SIOD_sdi_b       = 1,
8249 +       SIOD_sdi_m       = 0x00000002,
8250 +       SIOD_sck_b       = 2,
8251 +       SIOD_sck_m       = 0x00000004,
8252 +       SIOD_pci_b       = 3,
8253 +       SIOD_pci_m       = 0x00000008,
8254 +} ;
8255 +#endif // __IDT_SPI_H__
8256 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_timer.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h
8257 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_timer.h    1970-01-01 01:00:00.000000000 +0100
8258 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h       2006-06-18 12:44:28.000000000 +0200
8259 @@ -0,0 +1,91 @@
8260 +/**************************************************************************
8261 + *
8262 + *  BRIEF MODULE DESCRIPTION
8263 + *   Definitions for timer registers
8264 + *
8265 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8266 + *
8267 + *  This program is free software; you can redistribute  it and/or modify it
8268 + *  under  the terms of  the GNU General  Public License as published by the
8269 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8270 + *  option) any later version.
8271 + *
8272 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8273 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8274 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8275 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8276 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8277 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8278 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8279 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8280 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8281 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8282 + *
8283 + *  You should have received a copy of the  GNU General Public License along
8284 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8285 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8286 + *
8287 + *
8288 + **************************************************************************
8289 + * May 2004 rkt,neb.
8290 + *
8291 + * Initial Release
8292 + *
8293 + *
8294 + *
8295 + **************************************************************************
8296 + */
8297 +
8298 +#ifndef __IDT_TIM_H__
8299 +#define __IDT_TIM_H__
8300 +
8301 +enum
8302 +{
8303 +       TIM0_PhysicalAddress    = 0x18028000,
8304 +       TIM_PhysicalAddress     = TIM0_PhysicalAddress,         // Default
8305 +
8306 +       TIM0_VirtualAddress     = 0xb8028000,
8307 +       TIM_VirtualAddress      = TIM0_VirtualAddress,          // Default
8308 +} ;
8309 +
8310 +enum
8311 +{
8312 +       TIM_Count = 3,
8313 +} ;
8314 +
8315 +struct TIM_CNTR_s
8316 +{
8317 +  u32 count ;
8318 +  u32 compare ;
8319 +  u32 ctc ;    //use CTC_
8320 +} ;
8321 +
8322 +typedef struct TIM_s
8323 +{
8324 +  struct TIM_CNTR_s    tim [TIM_Count] ;
8325 +  u32                  rcount ;        //use RCOUNT_
8326 +  u32                  rcompare ;      //use RCOMPARE_
8327 +  u32                  rtc ;           //use RTC_
8328 +} volatile * TIM_t ;
8329 +
8330 +enum
8331 +{
8332 +  CTC_en_b     = 0,
8333 +  CTC_en_m     = 0x00000001,
8334 +  CTC_to_b     = 1,
8335 +  CTC_to_m     = 0x00000002,
8336 +
8337 +  RCOUNT_count_b               = 0,
8338 +  RCOUNT_count_m               = 0x0000ffff,
8339 +  RCOMPARE_compare_b   = 0,
8340 +  RCOMPARE_compare_m   = 0x0000ffff,
8341 +  RTC_ce_b             = 0,
8342 +  RTC_ce_m             = 0x00000001,
8343 +  RTC_to_b             = 1,
8344 +  RTC_to_m             = 0x00000002,
8345 +  RTC_rqe_b            = 2,
8346 +  RTC_rqe_m            = 0x00000004,
8347 +
8348 +} ;
8349 +#endif // __IDT_TIM_H__
8350 +
8351 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_uart.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h
8352 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_uart.h     1970-01-01 01:00:00.000000000 +0100
8353 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h        2006-06-18 12:44:28.000000000 +0200
8354 @@ -0,0 +1,189 @@
8355 +/**************************************************************************
8356 + *
8357 + *  BRIEF MODULE DESCRIPTION
8358 + *   UART register definitions
8359 + *
8360 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8361 + *
8362 + *  This program is free software; you can redistribute  it and/or modify it
8363 + *  under  the terms of  the GNU General  Public License as published by the
8364 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8365 + *  option) any later version.
8366 + *
8367 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8368 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8369 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8370 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8371 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8372 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8373 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8374 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8375 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8376 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8377 + *
8378 + *  You should have received a copy of the  GNU General Public License along
8379 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8380 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8381 + *
8382 + *
8383 + **************************************************************************
8384 + * May 2004 rkt, neb.
8385 + *
8386 + * Initial Release
8387 + *
8388 + *
8389 + *
8390 + **************************************************************************
8391 + */
8392 +
8393 +#ifndef __IDT_UART_H__
8394 +#define __IDT_UART_H__
8395 +
8396 +enum
8397 +{
8398 +       UART0_PhysicalAddress   = 0x1c000000,
8399 +       UART_PhysicalAddress    = UART0_PhysicalAddress,        // Default
8400 +
8401 +       UART0_VirtualAddress    = 0xbc000000,
8402 +       UART_VirtualAddress     = UART0_VirtualAddress,         // Default
8403 +} ;
8404 +
8405 +/*
8406 + * Register definitions are in bytes so we can handle endian problems.
8407 + */
8408 +
8409 +typedef struct UART_s
8410 +{
8411 +       union
8412 +       {
8413 +               u32 const       uartrb ;        // 0x00 - DLAB=0, read.
8414 +               u32             uartth ;        // 0x00 - DLAB=0, write.
8415 +               u32             uartdll ;       // 0x00 - DLAB=1, read/write.
8416 +       } ;
8417 +
8418 +       union
8419 +       {
8420 +               u32             uartie ;        // 0x04 - DLAB=0, read/write.
8421 +               u32             uartdlh ;       // 0x04 - DLAB=1, read/write.
8422 +       } ;
8423 +       union
8424 +       {
8425 +               u32 const       uartii ;        // 0x08 - DLAB=0, read.
8426 +               u32             uartfc ;        // 0x08 - DLAB=0, write.
8427 +       } ;
8428 +
8429 +       u32             uartlc ;                // 0x0c
8430 +       u32             uartmc ;                // 0x10
8431 +       u32             uartls ;                // 0x14
8432 +       u32             uartms ;                // 0x18
8433 +       u32             uarts ;                 // 0x1c
8434 +} volatile *UART_t ;
8435 +
8436 +// Reset registers.
8437 +typedef u32    volatile *UARTRR_t ;
8438 +
8439 +enum
8440 +{
8441 +       UARTIE_rda_b    = 0,
8442 +       UARTIE_rda_m    = 0x00000001,
8443 +       UARTIE_the_b    = 1,
8444 +       UARTIE_the_m    = 0x00000002,
8445 +       UARTIE_rls_b    = 2,
8446 +       UARTIE_rls_m    = 0x00000004,
8447 +       UARTIE_ems_b    = 3,
8448 +       UARTIE_ems_m    = 0x00000008,
8449 +
8450 +       UARTII_pi_b     = 0,
8451 +       UARTII_pi_m     = 0x00000001,
8452 +       UARTII_iid_b    = 1,
8453 +       UARTII_iid_m    = 0x0000000e,
8454 +               UARTII_iid_ms_v         = 0,    // Modem stat-CTS,DSR,RI or DCD.
8455 +               UARTII_iid_thre_v       = 1,    // Trans. Holding Reg. empty.
8456 +               UARTII_iid_rda_v        = 2,    // Receive data available
8457 +               UARTII_iid_rls_v        = 3,    // Overrun, parity, etc, error.
8458 +               UARTII_iid_res4_v       = 4,    // reserved.
8459 +               UARTII_iid_res5_v       = 5,    // reserved.
8460 +               UARTII_iid_cto_v        = 6,    // Character timeout.
8461 +               UARTII_iid_res7_v       = 7,    // reserved.
8462 +
8463 +       UARTFC_en_b     = 0,
8464 +       UARTFC_en_m     = 0x00000001,
8465 +       UARTFC_rr_b     = 1,
8466 +       UARTFC_rr_m     = 0x00000002,
8467 +       UARTFC_tr_b     = 2,
8468 +       UARTFC_tr_m     = 0x00000004,
8469 +       UARTFC_dms_b    = 3,
8470 +       UARTFC_dms_m    = 0x00000008,
8471 +       UARTFC_rt_b     = 6,
8472 +       UARTFC_rt_m     = 0x000000c0,
8473 +               UARTFC_rt_1Byte_v       = 0,
8474 +               UARTFC_rt_4Byte_v       = 1,
8475 +               UARTFC_rt_8Byte_v       = 2,
8476 +               UARTFC_rt_14Byte_v      = 3,
8477 +
8478 +       UARTLC_wls_b    = 0,
8479 +       UARTLC_wls_m    = 0x00000003,
8480 +               UARTLC_wls_5Bits_v      = 0,
8481 +               UARTLC_wls_6Bits_v      = 1,
8482 +               UARTLC_wls_7Bits_v      = 2,
8483 +               UARTLC_wls_8Bits_v      = 3,
8484 +       UARTLC_stb_b    = 2,
8485 +       UARTLC_stb_m    = 0x00000004,
8486 +       UARTLC_pen_b    = 3,
8487 +       UARTLC_pen_m    = 0x00000008,
8488 +       UARTLC_eps_b    = 4,
8489 +       UARTLC_eps_m    = 0x00000010,
8490 +       UARTLC_sp_b     = 5,
8491 +       UARTLC_sp_m     = 0x00000020,
8492 +       UARTLC_sb_b     = 6,
8493 +       UARTLC_sb_m     = 0x00000040,
8494 +       UARTLC_dlab_b   = 7,
8495 +       UARTLC_dlab_m   = 0x00000080,
8496 +
8497 +       UARTMC_dtr_b    = 0,
8498 +       UARTMC_dtr_m    = 0x00000001,
8499 +       UARTMC_rts_b    = 1,
8500 +       UARTMC_rts_m    = 0x00000002,
8501 +       UARTMC_o1_b     = 2,
8502 +       UARTMC_o1_m     = 0x00000004,
8503 +       UARTMC_o2_b     = 3,
8504 +       UARTMC_o2_m     = 0x00000008,
8505 +       UARTMC_lp_b     = 4,
8506 +       UARTMC_lp_m     = 0x00000010,
8507 +
8508 +       UARTLS_dr_b     = 0,
8509 +       UARTLS_dr_m     = 0x00000001,
8510 +       UARTLS_oe_b     = 1,
8511 +       UARTLS_oe_m     = 0x00000002,
8512 +       UARTLS_pe_b     = 2,
8513 +       UARTLS_pe_m     = 0x00000004,
8514 +       UARTLS_fe_b     = 3,
8515 +       UARTLS_fe_m     = 0x00000008,
8516 +       UARTLS_bi_b     = 4,
8517 +       UARTLS_bi_m     = 0x00000010,
8518 +       UARTLS_thr_b    = 5,
8519 +       UARTLS_thr_m    = 0x00000020,
8520 +       UARTLS_te_b     = 6,
8521 +       UARTLS_te_m     = 0x00000040,
8522 +       UARTLS_rfe_b    = 7,
8523 +       UARTLS_rfe_m    = 0x00000080,
8524 +
8525 +       UARTMS_dcts_b   = 0,
8526 +       UARTMS_dcts_m   = 0x00000001,
8527 +       UARTMS_ddsr_b   = 1,
8528 +       UARTMS_ddsr_m   = 0x00000002,
8529 +       UARTMS_teri_b   = 2,
8530 +       UARTMS_teri_m   = 0x00000004,
8531 +       UARTMS_ddcd_b   = 3,
8532 +       UARTMS_ddcd_m   = 0x00000008,
8533 +       UARTMS_cts_b    = 4,
8534 +       UARTMS_cts_m    = 0x00000010,
8535 +       UARTMS_dsr_b    = 5,
8536 +       UARTMS_dsr_m    = 0x00000020,
8537 +       UARTMS_ri_b     = 6,
8538 +       UARTMS_ri_m     = 0x00000040,
8539 +       UARTMS_dcd_b    = 7,
8540 +       UARTMS_dcd_m    = 0x00000080,
8541 +} ;
8542 +
8543 +#endif // __IDT_UART_H__
8544 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h
8545 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma.h      1970-01-01 01:00:00.000000000 +0100
8546 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 2006-06-18 12:44:28.000000000 +0200
8547 @@ -0,0 +1,231 @@
8548 +/**************************************************************************
8549 + *
8550 + *  BRIEF MODULE DESCRIPTION
8551 + *   Register definitions for  IDT RC32438 DMA.
8552 + *
8553 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8554 + *
8555 + *  This program is free software; you can redistribute  it and/or modify it
8556 + *  under  the terms of  the GNU General  Public License as published by the
8557 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8558 + *  option) any later version.
8559 + *
8560 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8561 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8562 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8563 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8564 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8565 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8566 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8567 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8568 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8569 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8570 + *
8571 + *  You should have received a copy of the  GNU General Public License along
8572 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8573 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8574 + *
8575 + *
8576 + **************************************************************************
8577 + * May 2004 P. Sadik.
8578 + *
8579 + * Initial Release
8580 + *
8581 + *
8582 + *
8583 + **************************************************************************
8584 + */
8585 +#ifndef __IDT_RC32438_DMA_H__
8586 +#define __IDT_RC32438_DMA_H__
8587 +enum
8588 +{
8589 +       DMA0_PhysicalAddress    = 0x18040000,
8590 +       DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
8591 +
8592 +       DMA0_VirtualAddress     = 0xb8040000,
8593 +       DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
8594 +} ;
8595 +
8596 +/*
8597 + * DMA descriptor (in physical memory).
8598 + */
8599 +
8600 +typedef struct DMAD_s
8601 +{
8602 +       u32                     control ;       // Control. use DMAD_*
8603 +       u32                     ca ;            // Current Address.
8604 +       u32                     devcs ;         // Device control and status.
8605 +       u32                     link ;          // Next descriptor in chain.
8606 +} volatile *DMAD_t ;
8607 +
8608 +enum
8609 +{
8610 +       DMAD_size               = sizeof (struct DMAD_s),
8611 +       DMAD_count_b            = 0,            // in DMAD_t -> control
8612 +       DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
8613 +       DMAD_ds_b               = 20,           // in DMAD_t -> control
8614 +       DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
8615 +               DMAD_ds_extToMem0_v     = 0,
8616 +               DMAD_ds_memToExt0_v     = 1,
8617 +               DMAD_ds_extToMem1_v     = 0,
8618 +               DMAD_ds_memToExt1_v     = 1,
8619 +               DMAD_ds_ethRcv0_v       = 0,
8620 +               DMAD_ds_ethXmt0_v       = 0,
8621 +               DMAD_ds_ethRcv1_v       = 0,
8622 +               DMAD_ds_ethXmt2_v       = 0,
8623 +               DMAD_ds_memToFifo_v     = 0,
8624 +               DMAD_ds_fifoToMem_v     = 0,
8625 +               DMAD_ds_rng_de_v           = 1,//randomNumberGenerator on LC/DE
8626 +               DMAD_ds_pciToMem_v      = 0,
8627 +               DMAD_ds_memToPci_v      = 0,
8628 +               DMAD_ds_securityInput_v = 0,
8629 +               DMAD_ds_securityOutput_v = 0,
8630 +               DMAD_ds_rng_se_v        = 0,//randomNumberGenerator on SE
8631 +
8632 +       DMAD_devcmd_b           = 22,           // in DMAD_t -> control
8633 +       DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
8634 +               DMAD_devcmd_byte_v      = 0,    //memory-to-memory
8635 +               DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
8636 +               DMAD_devcmd_word_v      = 2,    //memory-to-memory
8637 +               DMAD_devcmd_2words_v    = 3,    //memory-to-memory
8638 +               DMAD_devcmd_4words_v    = 4,    //memory-to-memory
8639 +               DMAD_devcmd_6words_v    = 5,    //memory-to-memory
8640 +               DMAD_devcmd_8words_v    = 6,    //memory-to-memory
8641 +               DMAD_devcmd_16words_v   = 7,    //memory-to-memory
8642 +       DMAD_cof_b              = 25,           // chain on finished
8643 +       DMAD_cof_m              = 0x02000000,   //
8644 +       DMAD_cod_b              = 26,           // chain on done
8645 +       DMAD_cod_m              = 0x04000000,   //
8646 +       DMAD_iof_b              = 27,           // interrupt on finished
8647 +       DMAD_iof_m              = 0x08000000,   //
8648 +       DMAD_iod_b              = 28,           // interrupt on done
8649 +       DMAD_iod_m              = 0x10000000,   //
8650 +       DMAD_t_b                = 29,           // terminated
8651 +       DMAD_t_m                = 0x20000000,   //
8652 +       DMAD_d_b                = 30,           // done
8653 +       DMAD_d_m                = 0x40000000,   //
8654 +       DMAD_f_b                = 31,           // finished
8655 +       DMAD_f_m                = 0x80000000,   //
8656 +} ;
8657 +
8658 +/*
8659 + * DMA register (within Internal Register Map).
8660 + */
8661 +
8662 +struct DMA_Chan_s
8663 +{
8664 +       u32             dmac ;          // Control.
8665 +       u32             dmas ;          // Status.
8666 +       u32             dmasm ;         // Mask.
8667 +       u32             dmadptr ;       // Descriptor pointer.
8668 +       u32             dmandptr ;      // Next descriptor pointer.
8669 +};
8670 +
8671 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
8672 +
8673 +//DMA_Channels   use DMACH_count instead
8674 +
8675 +enum
8676 +{
8677 +       DMAC_run_b      = 0,            //
8678 +       DMAC_run_m      = 0x00000001,   //
8679 +       DMAC_dm_b       = 1,            // done mask
8680 +       DMAC_dm_m       = 0x00000002,   //
8681 +       DMAC_mode_b     = 2,            //
8682 +       DMAC_mode_m     = 0x0000000c,   //
8683 +               DMAC_mode_auto_v        = 0,
8684 +               DMAC_mode_burst_v       = 1,
8685 +               DMAC_mode_transfer_v    = 2, //usually used
8686 +               DMAC_mode_reserved_v    = 3,
8687 +       DMAC_a_b        = 4,            //
8688 +       DMAC_a_m        = 0x00000010,   //
8689 +
8690 +       DMAS_f_b        = 0,            // finished (sticky)
8691 +       DMAS_f_m        = 0x00000001,   //
8692 +       DMAS_d_b        = 1,            // done (sticky)
8693 +       DMAS_d_m        = 0x00000002,   //
8694 +       DMAS_c_b        = 2,            // chain (sticky)
8695 +       DMAS_c_m        = 0x00000004,   //
8696 +       DMAS_e_b        = 3,            // error (sticky)
8697 +       DMAS_e_m        = 0x00000008,   //
8698 +       DMAS_h_b        = 4,            // halt (sticky)
8699 +       DMAS_h_m        = 0x00000010,   //
8700 +
8701 +       DMASM_f_b       = 0,            // finished (1=mask)
8702 +       DMASM_f_m       = 0x00000001,   //
8703 +       DMASM_d_b       = 1,            // done (1=mask)
8704 +       DMASM_d_m       = 0x00000002,   //
8705 +       DMASM_c_b       = 2,            // chain (1=mask)
8706 +       DMASM_c_m       = 0x00000004,   //
8707 +       DMASM_e_b       = 3,            // error (1=mask)
8708 +       DMASM_e_m       = 0x00000008,   //
8709 +       DMASM_h_b       = 4,            // halt (1=mask)
8710 +       DMASM_h_m       = 0x00000010,   //
8711 +} ;
8712 +
8713 +/*
8714 + * DMA channel definitions
8715 + */
8716 +
8717 +enum
8718 +{
8719 +       DMACH_extToMem0 = 0,
8720 +       DMACH_memToExt0 = 0,
8721 +       DMACH_extToMem1 = 1,
8722 +       DMACH_memToExt1 = 1,
8723 +       DMACH_ethRcv0 = 2,
8724 +       DMACH_ethXmt0 = 3,
8725 +       DMACH_ethRcv1 = 4,
8726 +       DMACH_ethXmt2 = 5,
8727 +       DMACH_memToFifo = 6,
8728 +       DMACH_fifoToMem = 7,
8729 +       DMACH_rng_de = 7,//randomNumberGenerator on LC/DE
8730 +       DMACH_pciToMem = 8,
8731 +       DMACH_memToPci = 9,
8732 +       DMACH_securityInput = 10,
8733 +       DMACH_securityOutput = 11,
8734 +       DMACH_rng_se = 12, //randomNumberGenerator on SE
8735 +
8736 +       DMACH_count //must be last
8737 +};
8738 +
8739 +
8740 +typedef struct DMAC_s
8741 +{
8742 +       struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
8743 +} volatile *DMA_t ;
8744 +
8745 +
8746 +/*
8747 + * External DMA parameters
8748 +*/
8749 +
8750 +enum
8751 +{
8752 +       DMADEVCMD_ts_b  = 0,            // ts field in devcmd
8753 +       DMADEVCMD_ts_m  = 0x00000007,   // ts field in devcmd
8754 +               DMADEVCMD_ts_byte_v     = 0,
8755 +               DMADEVCMD_ts_halfword_v = 1,
8756 +               DMADEVCMD_ts_word_v     = 2,
8757 +               DMADEVCMD_ts_2word_v    = 3,
8758 +               DMADEVCMD_ts_4word_v    = 4,
8759 +               DMADEVCMD_ts_6word_v    = 5,
8760 +               DMADEVCMD_ts_8word_v    = 6,
8761 +               DMADEVCMD_ts_16word_v   = 7
8762 +};
8763 +
8764 +
8765 +#if 1  // aws - Compatibility.
8766 +#      define  EXTDMA_ts_b             DMADEVCMD_ts_b
8767 +#      define  EXTDMA_ts_m             DMADEVCMD_ts_m
8768 +#      define  EXTDMA_ts_byte_v        DMADEVCMD_ts_byte_v
8769 +#      define  EXTDMA_ts_halfword_v    DMADEVCMD_ts_halfword_v
8770 +#      define  EXTDMA_ts_word_v        DMADEVCMD_ts_word_v
8771 +#      define  EXTDMA_ts_2word_v       DMADEVCMD_ts_2word_v
8772 +#      define  EXTDMA_ts_4word_v       DMADEVCMD_ts_4word_v
8773 +#      define  EXTDMA_ts_6word_v       DMADEVCMD_ts_6word_v
8774 +#      define  EXTDMA_ts_8word_v       DMADEVCMD_ts_8word_v
8775 +#      define  EXTDMA_ts_16word_v      DMADEVCMD_ts_16word_v
8776 +#endif // aws - Compatibility.
8777 +
8778 +#endif //__IDT_RC32438_DMA_H__
8779 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h
8780 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h    1970-01-01 01:00:00.000000000 +0100
8781 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h       2006-06-18 12:44:28.000000000 +0200
8782 @@ -0,0 +1,82 @@
8783 +/**************************************************************************
8784 + *
8785 + *  BRIEF MODULE DESCRIPTION
8786 + *   DMA operations for IDT RC32438.
8787 + *
8788 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8789 + *
8790 + *  This program is free software; you can redistribute  it and/or modify it
8791 + *  under  the terms of  the GNU General  Public License as published by the
8792 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8793 + *  option) any later version.
8794 + *
8795 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8796 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8797 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8798 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8799 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8800 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8801 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8802 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8803 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8804 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8805 + *
8806 + *  You should have received a copy of the  GNU General Public License along
8807 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8808 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8809 + *
8810 + *
8811 + **************************************************************************
8812 + * May 2004 P. Sadik.
8813 + *
8814 + * Initial Release
8815 + *
8816 + *
8817 + *
8818 + **************************************************************************
8819 + */
8820 +
8821 +#ifndef __IDT_RC32438_DMA_V_H__
8822 +#define __IDT_RC32438_DMA_V_H__
8823 +#include  <asm/idt-boards/rc32438/rc32438_dma.h>
8824 +
8825 +#define DMA_CHAN_OFFSET  0x14
8826 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
8827 +#define DMA_COUNT(count)   \
8828 +  ((count) & DMAD_count_m)
8829 +
8830 +#define DMA_HALT_TIMEOUT 500
8831 +
8832 +
8833 +static inline int rc32438_halt_dma(DMA_Chan_t ch)
8834 +{
8835 +       int timeout=1;
8836 +       if (rc32438_readl(&ch->dmac) & DMAC_run_m) {
8837 +               rc32438_writel(0, &ch->dmac);
8838 +
8839 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
8840 +                       if (rc32438_readl(&ch->dmas) & DMAS_h_m) {
8841 +                               rc32438_writel(0, &ch->dmas);
8842 +                               break;
8843 +                       }
8844 +               }
8845 +
8846 +       }
8847 +
8848 +       return timeout ? 0 : 1;
8849 +}
8850 +
8851 +
8852 +
8853 +
8854 +static inline void rc32438_start_dma(DMA_Chan_t ch, u32 dma_addr)
8855 +{
8856 +       rc32438_writel(0, &ch->dmandptr);
8857 +       rc32438_writel(dma_addr, &ch->dmadptr);
8858 +}
8859 +
8860 +static inline void rc32438_chain_dma(DMA_Chan_t ch, u32 dma_addr)
8861 +{
8862 +       rc32438_writel(dma_addr, &ch->dmandptr);
8863 +}
8864 +#endif //__IDT_RC32438_DMA_V_H__
8865 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h
8866 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth.h      1970-01-01 01:00:00.000000000 +0100
8867 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 2006-06-18 12:44:28.000000000 +0200
8868 @@ -0,0 +1,328 @@
8869 +/**************************************************************************
8870 + *
8871 + *  BRIEF MODULE DESCRIPTION
8872 + *   Definitions for IDT EB438 ethernet
8873 + *
8874 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8875 + *
8876 + *  This program is free software; you can redistribute  it and/or modify it
8877 + *  under  the terms of  the GNU General  Public License as published by the
8878 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8879 + *  option) any later version.
8880 + *
8881 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8882 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8883 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8884 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8885 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8886 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8887 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8888 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8889 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8890 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8891 + *
8892 + *  You should have received a copy of the  GNU General Public License along
8893 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8894 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8895 + *
8896 + *
8897 + **************************************************************************
8898 + * May 2004 P. Sadik.
8899 + *
8900 + * Initial Release
8901 + *
8902 + *
8903 + *
8904 + **************************************************************************
8905 + */
8906 +
8907 +#ifndef __IDT_RC32438_ETH_H__
8908 +#define __IDT_RC32438_ETH_H__
8909 +enum
8910 +{
8911 +       ETH0_PhysicalAddress    = 0x18058000,
8912 +       ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
8913 +
8914 +       ETH0_VirtualAddress     = 0xb8058000,
8915 +       ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
8916 +       ETH1_PhysicalAddress    = 0x18060000,
8917 +       ETH1_VirtualAddress     = 0xb8060000,                   // Default
8918 +} ;
8919 +
8920 +typedef struct
8921 +{
8922 +       u32 ethintfc            ;
8923 +       u32 ethfifott           ;
8924 +       u32 etharc              ;
8925 +       u32 ethhash0            ;
8926 +       u32 ethhash1            ;
8927 +       u32 ethu0 [4]           ;       // Reserved.
8928 +       u32 ethpfs              ;
8929 +       u32 ethmcp              ;
8930 +       u32 eth_u1 [10]         ;       // Reserved.
8931 +       u32 ethspare            ;
8932 +       u32 eth_u2 [42]         ;       // Reserved.
8933 +       u32 ethsal0             ;
8934 +       u32 ethsah0             ;
8935 +       u32 ethsal1             ;
8936 +       u32 ethsah1             ;
8937 +       u32 ethsal2             ;
8938 +       u32 ethsah2             ;
8939 +       u32 ethsal3             ;
8940 +       u32 ethsah3             ;
8941 +       u32 ethrbc              ;
8942 +       u32 ethrpc              ;
8943 +       u32 ethrupc             ;
8944 +       u32 ethrfc              ;
8945 +       u32 ethtbc              ;
8946 +       u32 ethgpf              ;
8947 +       u32 eth_u9 [50]         ;       // Reserved.
8948 +       u32 ethmac1             ;
8949 +       u32 ethmac2             ;
8950 +       u32 ethipgt             ;
8951 +       u32 ethipgr             ;
8952 +       u32 ethclrt             ;
8953 +       u32 ethmaxf             ;
8954 +       u32 eth_u10             ;       // Reserved.
8955 +       u32 ethmtest            ;
8956 +       u32 miimcfg             ;
8957 +       u32 miimcmd             ;
8958 +       u32 miimaddr            ;
8959 +       u32 miimwtd             ;
8960 +       u32 miimrdd             ;
8961 +       u32 miimind             ;
8962 +       u32 eth_u11             ;       // Reserved.
8963 +       u32 eth_u12             ;       // Reserved.
8964 +       u32 ethcfsa0            ;
8965 +       u32 ethcfsa1            ;
8966 +       u32 ethcfsa2            ;
8967 +} volatile *ETH_t;
8968 +
8969 +enum
8970 +{
8971 +       ETHINTFC_en_b           = 0,
8972 +       ETHINTFC_en_m           = 0x00000001,
8973 +       ETHINTFC_its_b          = 1,
8974 +       ETHINTFC_its_m          = 0x00000002,
8975 +       ETHINTFC_rip_b          = 2,
8976 +       ETHINTFC_rip_m          = 0x00000004,
8977 +       ETHINTFC_jam_b          = 3,
8978 +       ETHINTFC_jam_m          = 0x00000008,
8979 +       ETHINTFC_ovr_b          = 4,
8980 +       ETHINTFC_ovr_m          = 0x00000010,
8981 +       ETHINTFC_und_b          = 5,
8982 +       ETHINTFC_und_m          = 0x00000020,
8983 +
8984 +       ETHFIFOTT_tth_b         = 0,
8985 +       ETHFIFOTT_tth_m         = 0x0000007f,
8986 +
8987 +       ETHARC_pro_b            = 0,
8988 +       ETHARC_pro_m            = 0x00000001,
8989 +       ETHARC_am_b             = 1,
8990 +       ETHARC_am_m             = 0x00000002,
8991 +       ETHARC_afm_b            = 2,
8992 +       ETHARC_afm_m            = 0x00000004,
8993 +       ETHARC_ab_b             = 3,
8994 +       ETHARC_ab_m             = 0x00000008,
8995 +
8996 +       ETHSAL_byte5_b          = 0,
8997 +       ETHSAL_byte5_m          = 0x000000ff,
8998 +       ETHSAL_byte4_b          = 8,
8999 +       ETHSAL_byte4_m          = 0x0000ff00,
9000 +       ETHSAL_byte3_b          = 16,
9001 +       ETHSAL_byte3_m          = 0x00ff0000,
9002 +       ETHSAL_byte2_b          = 24,
9003 +       ETHSAL_byte2_m          = 0xff000000,
9004 +
9005 +       ETHSAH_byte1_b          = 0,
9006 +       ETHSAH_byte1_m          = 0x000000ff,
9007 +       ETHSAH_byte0_b          = 8,
9008 +       ETHSAH_byte0_m          = 0x0000ff00,
9009 +
9010 +       ETHGPF_ptv_b            = 0,
9011 +       ETHGPF_ptv_m            = 0x0000ffff,
9012 +
9013 +       ETHPFS_pfd_b            = 0,
9014 +       ETHPFS_pfd_m            = 0x00000001,
9015 +
9016 +       ETHCFSA0_cfsa4_b        = 0,
9017 +       ETHCFSA0_cfsa4_m        = 0x000000ff,
9018 +       ETHCFSA0_cfsa5_b        = 8,
9019 +       ETHCFSA0_cfsa5_m        = 0x0000ff00,
9020 +
9021 +       ETHCFSA1_cfsa2_b        = 0,
9022 +       ETHCFSA1_cfsa2_m        = 0x000000ff,
9023 +       ETHCFSA1_cfsa3_b        = 8,
9024 +       ETHCFSA1_cfsa3_m        = 0x0000ff00,
9025 +
9026 +       ETHCFSA2_cfsa0_b        = 0,
9027 +       ETHCFSA2_cfsa0_m        = 0x000000ff,
9028 +       ETHCFSA2_cfsa1_b        = 8,
9029 +       ETHCFSA2_cfsa1_m        = 0x0000ff00,
9030 +
9031 +       ETHMAC1_re_b            = 0,
9032 +       ETHMAC1_re_m            = 0x00000001,
9033 +       ETHMAC1_paf_b           = 1,
9034 +       ETHMAC1_paf_m           = 0x00000002,
9035 +       ETHMAC1_rfc_b           = 2,
9036 +       ETHMAC1_rfc_m           = 0x00000004,
9037 +       ETHMAC1_tfc_b           = 3,
9038 +       ETHMAC1_tfc_m           = 0x00000008,
9039 +       ETHMAC1_lb_b            = 4,
9040 +       ETHMAC1_lb_m            = 0x00000010,
9041 +       ETHMAC1_mr_b            = 31,
9042 +       ETHMAC1_mr_m            = 0x80000000,
9043 +
9044 +       ETHMAC2_fd_b            = 0,
9045 +       ETHMAC2_fd_m            = 0x00000001,
9046 +       ETHMAC2_flc_b           = 1,
9047 +       ETHMAC2_flc_m           = 0x00000002,
9048 +       ETHMAC2_hfe_b           = 2,
9049 +       ETHMAC2_hfe_m           = 0x00000004,
9050 +       ETHMAC2_dc_b            = 3,
9051 +       ETHMAC2_dc_m            = 0x00000008,
9052 +       ETHMAC2_cen_b           = 4,
9053 +       ETHMAC2_cen_m           = 0x00000010,
9054 +       ETHMAC2_pe_b            = 5,
9055 +       ETHMAC2_pe_m            = 0x00000020,
9056 +       ETHMAC2_vpe_b           = 6,
9057 +       ETHMAC2_vpe_m           = 0x00000040,
9058 +       ETHMAC2_ape_b           = 7,
9059 +       ETHMAC2_ape_m           = 0x00000080,
9060 +       ETHMAC2_ppe_b           = 8,
9061 +       ETHMAC2_ppe_m           = 0x00000100,
9062 +       ETHMAC2_lpe_b           = 9,
9063 +       ETHMAC2_lpe_m           = 0x00000200,
9064 +       ETHMAC2_nb_b            = 12,
9065 +       ETHMAC2_nb_m            = 0x00001000,
9066 +       ETHMAC2_bp_b            = 13,
9067 +       ETHMAC2_bp_m            = 0x00002000,
9068 +       ETHMAC2_ed_b            = 14,
9069 +       ETHMAC2_ed_m            = 0x00004000,
9070 +
9071 +       ETHIPGT_ipgt_b          = 0,
9072 +       ETHIPGT_ipgt_m          = 0x0000007f,
9073 +
9074 +       ETHIPGR_ipgr2_b         = 0,
9075 +       ETHIPGR_ipgr2_m         = 0x0000007f,
9076 +       ETHIPGR_ipgr1_b         = 8,
9077 +       ETHIPGR_ipgr1_m         = 0x00007f00,
9078 +
9079 +       ETHCLRT_maxret_b        = 0,
9080 +       ETHCLRT_maxret_m        = 0x0000000f,
9081 +       ETHCLRT_colwin_b        = 8,
9082 +       ETHCLRT_colwin_m        = 0x00003f00,
9083 +
9084 +       ETHMAXF_maxf_b          = 0,
9085 +       ETHMAXF_maxf_m          = 0x0000ffff,
9086 +
9087 +       ETHMTEST_tb_b           = 2,
9088 +       ETHMTEST_tb_m           = 0x00000004,
9089 +
9090 +       ETHMCP_div_b            = 0,
9091 +       ETHMCP_div_m            = 0x000000ff,
9092 +
9093 +       MIIMCFG_rsv_b           = 0,
9094 +       MIIMCFG_rsv_m           = 0x0000000c,
9095 +
9096 +       MIIMCMD_rd_b            = 0,
9097 +       MIIMCMD_rd_m            = 0x00000001,
9098 +       MIIMCMD_scn_b           = 1,
9099 +       MIIMCMD_scn_m           = 0x00000002,
9100 +
9101 +       MIIMADDR_regaddr_b      = 0,
9102 +       MIIMADDR_regaddr_m      = 0x0000001f,
9103 +       MIIMADDR_phyaddr_b      = 8,
9104 +       MIIMADDR_phyaddr_m      = 0x00001f00,
9105 +
9106 +       MIIMWTD_wdata_b         = 0,
9107 +       MIIMWTD_wdata_m         = 0x0000ffff,
9108 +
9109 +       MIIMRDD_rdata_b         = 0,
9110 +       MIIMRDD_rdata_m         = 0x0000ffff,
9111 +
9112 +       MIIMIND_bsy_b           = 0,
9113 +       MIIMIND_bsy_m           = 0x00000001,
9114 +       MIIMIND_scn_b           = 1,
9115 +       MIIMIND_scn_m           = 0x00000002,
9116 +       MIIMIND_nv_b            = 2,
9117 +       MIIMIND_nv_m            = 0x00000004,
9118 +
9119 +} ;
9120 +
9121 +/*
9122 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
9123 + */
9124 +enum
9125 +{
9126 +       ETHRX_fd_b              = 0,
9127 +       ETHRX_fd_m              = 0x00000001,
9128 +       ETHRX_ld_b              = 1,
9129 +       ETHRX_ld_m              = 0x00000002,
9130 +       ETHRX_rok_b             = 2,
9131 +       ETHRX_rok_m             = 0x00000004,
9132 +       ETHRX_fm_b              = 3,
9133 +       ETHRX_fm_m              = 0x00000008,
9134 +       ETHRX_mp_b              = 4,
9135 +       ETHRX_mp_m              = 0x00000010,
9136 +       ETHRX_bp_b              = 5,
9137 +       ETHRX_bp_m              = 0x00000020,
9138 +       ETHRX_vlt_b             = 6,
9139 +       ETHRX_vlt_m             = 0x00000040,
9140 +       ETHRX_cf_b              = 7,
9141 +       ETHRX_cf_m              = 0x00000080,
9142 +       ETHRX_ovr_b             = 8,
9143 +       ETHRX_ovr_m             = 0x00000100,
9144 +       ETHRX_crc_b             = 9,
9145 +       ETHRX_crc_m             = 0x00000200,
9146 +       ETHRX_cv_b              = 10,
9147 +       ETHRX_cv_m              = 0x00000400,
9148 +       ETHRX_db_b              = 11,
9149 +       ETHRX_db_m              = 0x00000800,
9150 +       ETHRX_le_b              = 12,
9151 +       ETHRX_le_m              = 0x00001000,
9152 +       ETHRX_lor_b             = 13,
9153 +       ETHRX_lor_m             = 0x00002000,
9154 +       ETHRX_ces_b             = 14,
9155 +       ETHRX_ces_m             = 0x00004000,
9156 +       ETHRX_length_b          = 16,
9157 +       ETHRX_length_m          = 0xffff0000,
9158 +
9159 +       ETHTX_fd_b              = 0,
9160 +       ETHTX_fd_m              = 0x00000001,
9161 +       ETHTX_ld_b              = 1,
9162 +       ETHTX_ld_m              = 0x00000002,
9163 +       ETHTX_oen_b             = 2,
9164 +       ETHTX_oen_m             = 0x00000004,
9165 +       ETHTX_pen_b             = 3,
9166 +       ETHTX_pen_m             = 0x00000008,
9167 +       ETHTX_cen_b             = 4,
9168 +       ETHTX_cen_m             = 0x00000010,
9169 +       ETHTX_hen_b             = 5,
9170 +       ETHTX_hen_m             = 0x00000020,
9171 +       ETHTX_tok_b             = 6,
9172 +       ETHTX_tok_m             = 0x00000040,
9173 +       ETHTX_mp_b              = 7,
9174 +       ETHTX_mp_m              = 0x00000080,
9175 +       ETHTX_bp_b              = 8,
9176 +       ETHTX_bp_m              = 0x00000100,
9177 +       ETHTX_und_b             = 9,
9178 +       ETHTX_und_m             = 0x00000200,
9179 +       ETHTX_of_b              = 10,
9180 +       ETHTX_of_m              = 0x00000400,
9181 +       ETHTX_ed_b              = 11,
9182 +       ETHTX_ed_m              = 0x00000800,
9183 +       ETHTX_ec_b              = 12,
9184 +       ETHTX_ec_m              = 0x00001000,
9185 +       ETHTX_lc_b              = 13,
9186 +       ETHTX_lc_m              = 0x00002000,
9187 +       ETHTX_td_b              = 14,
9188 +       ETHTX_td_m              = 0x00004000,
9189 +       ETHTX_crc_b             = 15,
9190 +       ETHTX_crc_m             = 0x00008000,
9191 +       ETHTX_le_b              = 16,
9192 +       ETHTX_le_m              = 0x00010000,
9193 +       ETHTX_cc_b              = 17,
9194 +       ETHTX_cc_m              = 0x001E0000,
9195 +} ;
9196 +#endif //__IDT_RC32438_ETH_H__
9197 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h
9198 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h    1970-01-01 01:00:00.000000000 +0100
9199 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h       2006-06-18 12:44:28.000000000 +0200
9200 @@ -0,0 +1,72 @@
9201 +/**************************************************************************
9202 + *
9203 + *  BRIEF MODULE DESCRIPTION
9204 + *   macros for IDT EB438 ethernet
9205 + *
9206 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
9207 + *
9208 + *  This program is free software; you can redistribute  it and/or modify it
9209 + *  under  the terms of  the GNU General  Public License as published by the
9210 + *  Free Software Foundation;  either version 2 of the  License, or (at your
9211 + *  option) any later version.
9212 + *
9213 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
9214 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9215 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
9216 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
9217 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9218 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
9219 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9220 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
9221 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9222 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9223 + *
9224 + *  You should have received a copy of the  GNU General Public License along
9225 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
9226 + *  675 Mass Ave, Cambridge, MA 02139, USA.
9227 + *
9228 + *
9229 + **************************************************************************
9230 + * May 2004 P. Sadik.
9231 + *
9232 + * Initial Release
9233 + *
9234 + *
9235 + *
9236 + **************************************************************************
9237 + */
9238 +
9239 +#ifndef __IDT_RC32438_ETH_V_H__
9240 +#define __IDT_RC32438_ETH_V_H__
9241 +#include  <asm/idt-boards/rc32438/rc32438_eth.h>
9242 +
9243 +#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
9244 +#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
9245 +#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
9246 +#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
9247 +#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
9248 +#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
9249 +#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
9250 +#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
9251 +#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
9252 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
9253 +#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
9254 +
9255 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
9256 +
9257 +#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
9258 +#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
9259 +#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
9260 +#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
9261 +#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
9262 +#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
9263 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
9264 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
9265 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
9266 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
9267 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
9268 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
9269 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
9270 +#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
9271 +
9272 +#endif //__IDT_RC32438_ETH_V_H__
9273 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h
9274 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h     1970-01-01 01:00:00.000000000 +0100
9275 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h        2006-06-18 12:44:28.000000000 +0200
9276 @@ -0,0 +1,257 @@
9277 +/**************************************************************************
9278 + *
9279 + *  BRIEF MODULE DESCRIPTION
9280 + *   Definitions for IDT RC32438 GPIO.
9281 + *
9282 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
9283 + *
9284 + *  This program is free software; you can redistribute  it and/or modify it
9285 + *  under  the terms of  the GNU General  Public License as published by the
9286 + *  Free Software Foundation;  either version 2 of the  License, or (at your
9287 + *  option) any later version.
9288 + *
9289 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
9290 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9291 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
9292 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
9293 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9294 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
9295 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9296 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
9297 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9298 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9299 + *
9300 + *  You should have received a copy of the  GNU General Public License along
9301 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
9302 + *  675 Mass Ave, Cambridge, MA 02139, USA.
9303 + *
9304 + *
9305 + **************************************************************************
9306 + * May 2004 P. Sadik.
9307 + *
9308 + * Initial Release
9309 + *
9310 + *
9311 + *
9312 + **************************************************************************
9313 + */
9314 +#ifndef __IDT_RC32438_GPIO_H__
9315 +#define __IDT_RC32438_GPIO_H__
9316 +enum
9317 +{
9318 +       GPIO0_PhysicalAddress   = 0x18048000,
9319 +       GPIO_PhysicalAddress    = GPIO0_PhysicalAddress,        // Default
9320 +
9321 +       GPIO0_VirtualAddress    = 0xb8048000,
9322 +       GPIO_VirtualAddress     = GPIO0_VirtualAddress,         // Default
9323 +} ;
9324 +
9325 +typedef struct
9326 +{
9327 +       u32   gpiofunc;   /* GPIO Function Register
9328 +                          * gpiofunc[x]==0 bit = gpio
9329 +                          * func[x]==1  bit = altfunc
9330 +                          */
9331 +       u32   gpiocfg;    /* GPIO Configuration Register
9332 +                          * gpiocfg[x]==0 bit = input
9333 +                          * gpiocfg[x]==1 bit = output
9334 +                          */
9335 +       u32   gpiod;      /* GPIO Data Register
9336 +                          * gpiod[x] read/write gpio pinX status
9337 +                          */
9338 +       u32   gpioilevel; /* GPIO Interrupt Status Register
9339 +                          * interrupt level (see gpioistat)
9340 +                          */
9341 +       u32   gpioistat;  /* Gpio Interrupt Status Register
9342 +                          * istat[x] = (gpiod[x] == level[x])
9343 +                          * cleared in ISR (STICKY bits)
9344 +                          */
9345 +       u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
9346 +} volatile * GPIO_t ;
9347 +
9348 +typedef enum
9349 +{
9350 +       GPIO_gpio_v             = 0,            // gpiofunc use pin as GPIO.
9351 +       GPIO_alt_v              = 1,            // gpiofunc use pin as alt.
9352 +       GPIO_input_v            = 0,            // gpiocfg use pin as input.
9353 +       GPIO_output_v           = 1,            // gpiocfg use pin as output.
9354 +       GPIO_pin0_b             = 0,
9355 +       GPIO_pin0_m             = 0x00000001,
9356 +       GPIO_pin1_b             = 1,
9357 +       GPIO_pin1_m             = 0x00000002,
9358 +       GPIO_pin2_b             = 2,
9359 +       GPIO_pin2_m             = 0x00000004,
9360 +       GPIO_pin3_b             = 3,
9361 +       GPIO_pin3_m             = 0x00000008,
9362 +       GPIO_pin4_b             = 4,
9363 +       GPIO_pin4_m             = 0x00000010,
9364 +       GPIO_pin5_b             = 5,
9365 +       GPIO_pin5_m             = 0x00000020,
9366 +       GPIO_pin6_b             = 6,
9367 +       GPIO_pin6_m             = 0x00000040,
9368 +       GPIO_pin7_b             = 7,
9369 +       GPIO_pin7_m             = 0x00000080,
9370 +       GPIO_pin8_b             = 8,
9371 +       GPIO_pin8_m             = 0x00000100,
9372 +       GPIO_pin9_b             = 9,
9373 +       GPIO_pin9_m             = 0x00000200,
9374 +       GPIO_pin10_b            = 10,
9375 +       GPIO_pin10_m            = 0x00000400,
9376 +       GPIO_pin11_b            = 11,
9377 +       GPIO_pin11_m            = 0x00000800,
9378 +       GPIO_pin12_b            = 12,
9379 +       GPIO_pin12_m            = 0x00001000,
9380 +       GPIO_pin13_b            = 13,
9381 +       GPIO_pin13_m            = 0x00002000,
9382 +       GPIO_pin14_b            = 14,
9383 +       GPIO_pin14_m            = 0x00004000,
9384 +       GPIO_pin15_b            = 15,
9385 +       GPIO_pin15_m            = 0x00008000,
9386 +       GPIO_pin16_b            = 16,
9387 +       GPIO_pin16_m            = 0x00010000,
9388 +       GPIO_pin17_b            = 17,
9389 +       GPIO_pin17_m            = 0x00020000,
9390 +       GPIO_pin18_b            = 18,
9391 +       GPIO_pin18_m            = 0x00040000,
9392 +       GPIO_pin19_b            = 19,
9393 +       GPIO_pin19_m            = 0x00080000,
9394 +       GPIO_pin20_b            = 20,
9395 +       GPIO_pin20_m            = 0x00100000,
9396 +       GPIO_pin21_b            = 21,
9397 +       GPIO_pin21_m            = 0x00200000,
9398 +       GPIO_pin22_b            = 22,
9399 +       GPIO_pin22_m            = 0x00400000,
9400 +       GPIO_pin23_b            = 23,
9401 +       GPIO_pin23_m            = 0x00800000,
9402 +       GPIO_pin24_b            = 24,
9403 +       GPIO_pin24_m            = 0x01000000,
9404 +       GPIO_pin25_b            = 25,
9405 +       GPIO_pin25_m            = 0x02000000,
9406 +       GPIO_pin26_b            = 26,
9407 +       GPIO_pin26_m            = 0x04000000,
9408 +       GPIO_pin27_b            = 27,
9409 +       GPIO_pin27_m            = 0x08000000,
9410 +       GPIO_pin28_b            = 28,
9411 +       GPIO_pin28_m            = 0x10000000,
9412 +       GPIO_pin29_b            = 29,
9413 +       GPIO_pin29_m            = 0x20000000,
9414 +       GPIO_pin30_b            = 30,
9415 +       GPIO_pin30_m            = 0x40000000,
9416 +       GPIO_pin31_b            = 31,
9417 +       GPIO_pin31_m            = 0x80000000,
9418 +
9419 +// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
9420 +
9421 +       GPIO_u0sout_b           = GPIO_pin0_b,          // UART 0 serial out.
9422 +       GPIO_u0sout_m           = GPIO_pin0_m,
9423 +               GPIO_u0sout_cfg_v       = GPIO_output_v,
9424 +       GPIO_u0sinp_b   = GPIO_pin1_b,                  // UART 0 serial in.
9425 +       GPIO_u0sinp_m   = GPIO_pin1_m,
9426 +               GPIO_u0sinp_cfg_v       = GPIO_input_v,
9427 +       GPIO_u0rin_b    = GPIO_pin2_b,                  // UART 0 ring indic.
9428 +       GPIO_u0rin_m    = GPIO_pin2_m,
9429 +               GPIO_u0rin_cfg_v        = GPIO_input_v,
9430 +       GPIO_u0dcdn_b   = GPIO_pin3_b,                  // UART 0 data carr.det.
9431 +       GPIO_u0dcdn_m   = GPIO_pin3_m,
9432 +               GPIO_u0dcdn_cfg_v       = GPIO_input_v,
9433 +       GPIO_u0dtrn_b   = GPIO_pin4_b,                  // UART 0 data term rdy.
9434 +       GPIO_u0dtrn_m   = GPIO_pin4_m,
9435 +               GPIO_u0dtrn_cfg_v       = GPIO_output_v,
9436 +       GPIO_u0dsrn_b   = GPIO_pin5_b,                  // UART 0 data set rdy.
9437 +       GPIO_u0dsrn_m   = GPIO_pin5_m,
9438 +               GPIO_u0dsrn_cfg_v       = GPIO_input_v,
9439 +       GPIO_u0rtsn_b   = GPIO_pin6_b,                  // UART 0 req. to send.
9440 +       GPIO_u0rtsn_m   = GPIO_pin6_m,
9441 +               GPIO_u0rtsn_cfg_v       = GPIO_output_v,
9442 +       GPIO_u0ctsn_b   = GPIO_pin7_b,                  // UART 0 clear to send.
9443 +       GPIO_u0ctsn_m   = GPIO_pin7_m,
9444 +               GPIO_u0ctsn_cfg_v       = GPIO_input_v,
9445 +
9446 +       GPIO_u1sout_b           = GPIO_pin8_b,          // UART 1 serial out.
9447 +       GPIO_u1sout_m           = GPIO_pin8_m,
9448 +               GPIO_u1sout_cfg_v       = GPIO_output_v,
9449 +       GPIO_u1sinp_b           = GPIO_pin9_b,          // UART 1 serial in.
9450 +       GPIO_u1sinp_m           = GPIO_pin9_m,
9451 +               GPIO_u1sinp_cfg_v       = GPIO_input_v,
9452 +       GPIO_u1dtrn_b           = GPIO_pin10_b,         // UART 1 data term rdy.
9453 +       GPIO_u1dtrn_m           = GPIO_pin10_m,
9454 +               GPIO_u1dtrn_cfg_v       = GPIO_output_v,
9455 +       GPIO_u1dsrn_b           = GPIO_pin11_b,         // UART 1 data set rdy.
9456 +       GPIO_u1dsrn_m           = GPIO_pin11_m,
9457 +               GPIO_u1dsrn_cfg_v       = GPIO_input_v,
9458 +       GPIO_u1rtsn_b           = GPIO_pin12_b,         // UART 1 req. to send.
9459 +       GPIO_u1rtsn_m           = GPIO_pin12_m,
9460 +               GPIO_u1rtsn_cfg_v       = GPIO_output_v,
9461 +       GPIO_u1ctsn_b           = GPIO_pin13_b,         // UART 1 clear to send.
9462 +       GPIO_u1ctsn_m           = GPIO_pin13_m,
9463 +               GPIO_u1ctsn_cfg_v       = GPIO_input_v,
9464 +
9465 +       GPIO_dmareqn0_b         = GPIO_pin14_b,         // Ext. DMA 0 request
9466 +       GPIO_dmareqn0_m         = GPIO_pin14_m,
9467 +               GPIO_dmareqn0_cfg_v     = GPIO_input_v,
9468 +
9469 +       GPIO_dmareqn1_b         = GPIO_pin15_b,         // Ext. DMA 1 request
9470 +       GPIO_dmareqn1_m         = GPIO_pin15_m,
9471 +               GPIO_dmareqn1_cfg_v     = GPIO_input_v,
9472 +
9473 +       GPIO_dmadonen0_b        = GPIO_pin16_b,         // Ext. DMA 0 done
9474 +       GPIO_dmadonen0_m        = GPIO_pin16_m,
9475 +               GPIO_dmadonen0_cfg_v    = GPIO_input_v,
9476 +
9477 +       GPIO_dmadonen1_b        = GPIO_pin17_b,         // Ext. DMA 1 done
9478 +       GPIO_dmadonen1_m        = GPIO_pin17_m,
9479 +               GPIO_dmadonen1_cfg_v    = GPIO_input_v,
9480 +
9481 +       GPIO_dmafinn0_b         = GPIO_pin18_b,         // Ext. DMA 0 finished
9482 +       GPIO_dmafinn0_m         = GPIO_pin18_m,
9483 +               GPIO_dmafinn0_cfg_v     = GPIO_output_v,
9484 +
9485 +       GPIO_dmafinn1_b         = GPIO_pin19_b,         // Ext. DMA 1 finished
9486 +       GPIO_dmafinn1_m         = GPIO_pin19_m,
9487 +               GPIO_dmafinn1_cfg_v     = GPIO_output_v,
9488 +
9489 +       GPIO_maddr22_b          = GPIO_pin20_b,         // M&P bus bit 22.
9490 +       GPIO_maddr22_m          = GPIO_pin20_m,
9491 +               GPIO_maddr22_cfg_v      = GPIO_output_v,
9492 +
9493 +       GPIO_maddr23_b          = GPIO_pin21_b,         // M&P bus bit 23.
9494 +       GPIO_maddr23_m          = GPIO_pin21_m,
9495 +               GPIO_maddr23_cfg_v      = GPIO_output_v,
9496 +
9497 +       GPIO_maddr24_b          = GPIO_pin22_b,         // M&P bus bit 24.
9498 +       GPIO_maddr24_m          = GPIO_pin22_m,
9499 +               GPIO_maddr24_cfg_v      = GPIO_output_v,
9500 +
9501 +       GPIO_maddr25_b          = GPIO_pin23_b,         // M&P bus bit 25.
9502 +       GPIO_maddr25_m          = GPIO_pin23_m,
9503 +               GPIO_maddr25_cfg_v      = GPIO_output_v,
9504 +
9505 +       GPIO_afspare6_b         = GPIO_pin24_b,         // reserved.
9506 +       GPIO_afspare6_m         = GPIO_pin24_m,
9507 +               GPIO_afspare6_cfg_v     = GPIO_input_v,
9508 +       GPIO_afspare5_b         = GPIO_pin25_b,         // reserved.
9509 +       GPIO_afspare5_m         = GPIO_pin25_m,
9510 +               GPIO_afspare5_cfg_v     = GPIO_input_v,
9511 +       GPIO_afspare4_b         = GPIO_pin26_b,         // reserved.
9512 +       GPIO_afspare4_m         = GPIO_pin26_m,
9513 +               GPIO_afspare4_cfg_v     = GPIO_input_v,
9514 +       GPIO_afspare3_b         = GPIO_pin27_b,         // reserved.
9515 +       GPIO_afspare3_m         = GPIO_pin27_m,
9516 +               GPIO_afspare3_cfg_v     = GPIO_input_v,
9517 +       GPIO_afspare2_b         = GPIO_pin28_b,         // reserved.
9518 +       GPIO_afspare2_m         = GPIO_pin28_m,
9519 +               GPIO_afspare2_cfg_v     = GPIO_input_v,
9520 +       GPIO_afspare1_b         = GPIO_pin29_b,         // reserved.
9521 +       GPIO_afspare1_m         = GPIO_pin29_m,
9522 +               GPIO_afspare1_cfg_v     = GPIO_input_v,
9523 +
9524 +       GPIO_pcimuintn_b        = GPIO_pin30_b,         // PCI messaging int.
9525 +       GPIO_pcimuintn_m        = GPIO_pin30_m,
9526 +               GPIO_pcimuintn_cfg_v    = GPIO_output_v,
9527 +
9528 +       GPIO_rngclk_b           = GPIO_pin31_b,         // RNG external clock
9529 +       GPIO_rngclk_m           = GPIO_pin31_m,
9530 +               GPIO_rncclk_cfg_v       = GPIO_input_v,
9531 +} GPIO_DEFS_t;
9532 +
9533 +#endif //__IDT_RC32438_GPIO_H__
9534 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h
9535 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438.h  1970-01-01 01:00:00.000000000 +0100
9536 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h     2006-06-18 12:44:28.000000000 +0200
9537 @@ -0,0 +1,152 @@
9538 +/**************************************************************************
9539 + *
9540 + *  BRIEF MODULE DESCRIPTION
9541 + *   Definitions for IDT RC32438 CPU.
9542 + *
9543 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
9544 + *
9545 + *  This program is free software; you can redistribute  it and/or modify it
9546 + *  under  the terms of  the GNU General  Public License as published by the
9547 + *  Free Software Foundation;  either version 2 of the  License, or (at your
9548 + *  option) any later version.
9549 + *
9550 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
9551 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9552 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
9553 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
9554 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9555 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
9556 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9557 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
9558 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9559 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9560 + *
9561 + *  You should have received a copy of the  GNU General Public License along
9562 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
9563 + *  675 Mass Ave, Cambridge, MA 02139, USA.
9564 + *
9565 + *
9566 + **************************************************************************
9567 + * May 2004 P. Sadik.
9568 + *
9569 + * Initial Release
9570 + *
9571 + *
9572 + *
9573 + **************************************************************************
9574 + */
9575 +
9576 +#ifndef __IDT_RC32438_H__
9577 +#define  __IDT_RC32438_H__
9578 +#include <linux/config.h>
9579 +#include <linux/delay.h>
9580 +#include <asm/io.h>
9581 +#include <asm/idt-boards/rc32438/rc32438_timer.h>
9582 +
9583 +#define RC32438_REG_BASE   0x18000000
9584 +
9585 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
9586 +#define idttimer     ((volatile TIM_t)  TIM0_VirtualAddress)
9587 +#define idt_gpio         ((volatile GPIO_t) GPIO0_VirtualAddress)
9588 +
9589 +#define IDT_CLOCK_MULT 2
9590 +#define MIPS_CPU_TIMER_IRQ 7
9591 +/* Interrupt Controller */
9592 +#define IC_GROUP0_PEND     (RC32438_REG_BASE + 0x38000)
9593 +#define IC_GROUP0_MASK     (RC32438_REG_BASE + 0x38008)
9594 +#define IC_GROUP_OFFSET    0x0C
9595 +#define RTC_BASE           0xAC0801FF0
9596 +
9597 +#define NUM_INTR_GROUPS    5
9598 +/* 16550 UARTs */
9599 +
9600 +#define GROUP0_IRQ_BASE 8              /* GRP2 IRQ numbers start here */
9601 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
9602 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
9603 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
9604 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
9605 +
9606 +#ifdef __MIPSEB__
9607 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50003)
9608 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50023)
9609 +#else
9610 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50000)
9611 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50020)
9612 +#endif
9613 +
9614 +#define RC32438_UART0_IRQ  GROUP3_IRQ_BASE + 0
9615 +#define RC32438_UART1_IRQ  GROUP3_IRQ_BASE + 3
9616 +
9617 +#define RC32438_NR_IRQS  (GROUP4_IRQ_BASE + 32)
9618 +
9619 +
9620 +
9621 +/* cpu pipeline flush */
9622 +static inline void rc32438_sync(void)
9623 +{
9624 +        __asm__ volatile ("sync");
9625 +}
9626 +
9627 +static inline void rc32438_sync_udelay(int us)
9628 +{
9629 +        __asm__ volatile ("sync");
9630 +        udelay(us);
9631 +}
9632 +
9633 +static inline void rc32438_sync_delay(int ms)
9634 +{
9635 +        __asm__ volatile ("sync");
9636 +        mdelay(ms);
9637 +}
9638 +
9639 +/*
9640 + * Macros to access internal RC32438 registers. No byte
9641 + * swapping should be done when accessing the internal
9642 + * registers.
9643 + */
9644 +
9645 +#define rc32438_readb __raw_readb
9646 +#define rc32438_readw __raw_readw
9647 +#define rc32438_readl __raw_readl
9648 +
9649 +#define rc32438_writeb __raw_writeb
9650 +#define rc32438_writew __raw_writew
9651 +#define rc32438_writel __raw_writel
9652 +
9653 +/*
9654 + * C access to CLZ and CLO instructions
9655 + * (count leading zeroes/ones).
9656 + */
9657 +static inline int rc32438_clz(unsigned long val)
9658 +{
9659 +       int ret;
9660 +        __asm__ volatile (
9661 +               ".set\tnoreorder\n\t"
9662 +               ".set\tnoat\n\t"
9663 +               ".set\tmips32\n\t"
9664 +               "clz\t%0,%1\n\t"
9665 +                ".set\tmips0\n\t"
9666 +                ".set\tat\n\t"
9667 +                ".set\treorder"
9668 +                : "=r" (ret)
9669 +               : "r" (val));
9670 +
9671 +       return ret;
9672 +}
9673 +static inline int rc32438_clo(unsigned long val)
9674 +{
9675 +       int ret;
9676 +        __asm__ volatile (
9677 +               ".set\tnoreorder\n\t"
9678 +               ".set\tnoat\n\t"
9679 +               ".set\tmips32\n\t"
9680 +               "clo\t%0,%1\n\t"
9681 +                ".set\tmips0\n\t"
9682 +                ".set\tat\n\t"
9683 +                ".set\treorder"
9684 +                : "=r" (ret)
9685 +               : "r" (val));
9686 +
9687 +       return ret;
9688 +}
9689 +#endif //__IDT_RC32438_H__
9690 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h
9691 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci.h      1970-01-01 01:00:00.000000000 +0100
9692 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 2006-06-18 12:44:28.000000000 +0200
9693 @@ -0,0 +1,510 @@
9694 +/**************************************************************************
9695 + *
9696 + *  BRIEF MODULE DESCRIPTION
9697 + *   Definitions for IDT RC32438 PCI.
9698 + *
9699 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
9700 + *
9701 + *  This program is free software; you can redistribute  it and/or modify it
9702 + *  under  the terms of  the GNU General  Public License as published by the
9703 + *  Free Software Foundation;  either version 2 of the  License, or (at your
9704 + *  option) any later version.
9705 + *
9706 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
9707 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9708 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
9709 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
9710 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9711 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
9712 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9713 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
9714 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9715 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9716 + *
9717 + *  You should have received a copy of the  GNU General Public License along
9718 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
9719 + *  675 Mass Ave, Cambridge, MA 02139, USA.
9720 + *
9721 + *
9722 + **************************************************************************
9723 + * May 2004 P. Sadik
9724 + *
9725 + * Initial Release
9726 + *
9727 + *
9728 + *
9729 + **************************************************************************
9730 + */
9731 +
9732 +enum
9733 +{
9734 +       PCI0_PhysicalAddress    = 0x18080000,
9735 +       PCI_PhysicalAddress     = PCI0_PhysicalAddress,
9736 +
9737 +       PCI0_VirtualAddress     = 0xb8080000,
9738 +       PCI_VirtualAddress      = PCI0_VirtualAddress,
9739 +} ;
9740 +
9741 +enum
9742 +{
9743 +       PCI_LbaCount    = 4,            // Local base addresses.
9744 +} ;
9745 +
9746 +typedef struct
9747 +{
9748 +       u32     a ;             // Address.
9749 +       u32     c ;             // Control.
9750 +       u32     m ;             // mapping.
9751 +} PCI_Map_s ;
9752 +
9753 +typedef struct
9754 +{
9755 +       u32             pcic ;
9756 +       u32             pcis ;
9757 +       u32             pcism ;
9758 +       u32             pcicfga ;
9759 +       u32             pcicfgd ;
9760 +       PCI_Map_s       pcilba [PCI_LbaCount] ;
9761 +       u32             pcidac ;
9762 +       u32             pcidas ;
9763 +       u32             pcidasm ;
9764 +       u32             pcidad ;
9765 +       u32             pcidma8c ;
9766 +       u32             pcidma9c ;
9767 +       u32             pcitc ;
9768 +} volatile *PCI_t ;
9769 +
9770 +// PCI messaging unit.
9771 +enum
9772 +{
9773 +       PCIM_Count      = 2,
9774 +} ;
9775 +typedef struct
9776 +{
9777 +       u32             pciim [PCIM_Count] ;
9778 +       u32             pciom [PCIM_Count] ;
9779 +       u32             pciid ;
9780 +       u32             pciiic ;
9781 +       u32             pciiim ;
9782 +       u32             pciiod ;
9783 +       u32             pciioic ;
9784 +       u32             pciioim ;
9785 +} volatile *PCIM_t ;
9786 +
9787 +/*******************************************************************************
9788 + *
9789 + * PCI Control Register
9790 + *
9791 + ******************************************************************************/
9792 +enum
9793 +{
9794 +       PCIC_en_b       = 0,
9795 +       PCIC_en_m       = 0x00000001,
9796 +       PCIC_tnr_b      = 1,
9797 +       PCIC_tnr_m      = 0x00000002,
9798 +       PCIC_sce_b      = 2,
9799 +       PCIC_sce_m      = 0x00000004,
9800 +       PCIC_ien_b      = 3,
9801 +       PCIC_ien_m      = 0x00000008,
9802 +       PCIC_aaa_b      = 4,
9803 +       PCIC_aaa_m      = 0x00000010,
9804 +       PCIC_eap_b      = 5,
9805 +       PCIC_eap_m      = 0x00000020,
9806 +       PCIC_pcim_b     = 6,
9807 +       PCIC_pcim_m     = 0x000001c0,
9808 +               PCIC_pcim_disabled_v    = 0,
9809 +               PCIC_pcim_tnr_v         = 1,    // Satellite - target not ready
9810 +               PCIC_pcim_suspend_v     = 2,    // Satellite - suspended CPU.
9811 +               PCIC_pcim_extern_v      = 3,    // Host - external arbiter.
9812 +               PCIC_pcim_fixed_v       = 4,    // Host - fixed priority arb.
9813 +               PCIC_pcim_roundrobin_v  = 5,    // Host - round robin priority.
9814 +               PCIC_pcim_reserved6_v   = 6,
9815 +               PCIC_pcim_reserved7_v   = 7,
9816 +       PCIC_igm_b      = 9,
9817 +       PCIC_igm_m      = 0x00000200,
9818 +} ;
9819 +
9820 +/*******************************************************************************
9821 + *
9822 + * PCI Status Register
9823 + *
9824 + ******************************************************************************/
9825 +enum {
9826 +       PCIS_eed_b      = 0,
9827 +       PCIS_eed_m      = 0x00000001,
9828 +       PCIS_wr_b       = 1,
9829 +       PCIS_wr_m       = 0x00000002,
9830 +       PCIS_nmi_b      = 2,
9831 +       PCIS_nmi_m      = 0x00000004,
9832 +       PCIS_ii_b       = 3,
9833 +       PCIS_ii_m       = 0x00000008,
9834 +       PCIS_cwe_b      = 4,
9835 +       PCIS_cwe_m      = 0x00000010,
9836 +       PCIS_cre_b      = 5,
9837 +       PCIS_cre_m      = 0x00000020,
9838 +       PCIS_mdpe_b     = 6,
9839 +       PCIS_mdpe_m     = 0x00000040,
9840 +       PCIS_sta_b      = 7,
9841 +       PCIS_sta_m      = 0x00000080,
9842 +       PCIS_rta_b      = 8,
9843 +       PCIS_rta_m      = 0x00000100,
9844 +       PCIS_rma_b      = 9,
9845 +       PCIS_rma_m      = 0x00000200,
9846 +       PCIS_sse_b      = 10,
9847 +       PCIS_sse_m      = 0x00000400,
9848 +       PCIS_ose_b      = 11,
9849 +       PCIS_ose_m      = 0x00000800,
9850 +       PCIS_pe_b       = 12,
9851 +       PCIS_pe_m       = 0x00001000,
9852 +       PCIS_tae_b      = 13,
9853 +       PCIS_tae_m      = 0x00002000,
9854 +       PCIS_rle_b      = 14,
9855 +       PCIS_rle_m      = 0x00004000,
9856 +       PCIS_bme_b      = 15,
9857 +       PCIS_bme_m      = 0x00008000,
9858 +       PCIS_prd_b      = 16,
9859 +       PCIS_prd_m      = 0x00010000,
9860 +       PCIS_rip_b      = 17,
9861 +       PCIS_rip_m      = 0x00020000,
9862 +} ;
9863 +
9864 +/*******************************************************************************
9865 + *
9866 + * PCI Status Mask Register
9867 + *
9868 + ******************************************************************************/
9869 +enum {
9870 +       PCISM_eed_b             = 0,
9871 +       PCISM_eed_m             = 0x00000001,
9872 +       PCISM_wr_b              = 1,
9873 +       PCISM_wr_m              = 0x00000002,
9874 +       PCISM_nmi_b             = 2,
9875 +       PCISM_nmi_m             = 0x00000004,
9876 +       PCISM_ii_b              = 3,
9877 +       PCISM_ii_m              = 0x00000008,
9878 +       PCISM_cwe_b             = 4,
9879 +       PCISM_cwe_m             = 0x00000010,
9880 +       PCISM_cre_b             = 5,
9881 +       PCISM_cre_m             = 0x00000020,
9882 +       PCISM_mdpe_b            = 6,
9883 +       PCISM_mdpe_m            = 0x00000040,
9884 +       PCISM_sta_b             = 7,
9885 +       PCISM_sta_m             = 0x00000080,
9886 +       PCISM_rta_b             = 8,
9887 +       PCISM_rta_m             = 0x00000100,
9888 +       PCISM_rma_b             = 9,
9889 +       PCISM_rma_m             = 0x00000200,
9890 +       PCISM_sse_b             = 10,
9891 +       PCISM_sse_m             = 0x00000400,
9892 +       PCISM_ose_b             = 11,
9893 +       PCISM_ose_m             = 0x00000800,
9894 +       PCISM_pe_b              = 12,
9895 +       PCISM_pe_m              = 0x00001000,
9896 +       PCISM_tae_b             = 13,
9897 +       PCISM_tae_m             = 0x00002000,
9898 +       PCISM_rle_b             = 14,
9899 +       PCISM_rle_m             = 0x00004000,
9900 +       PCISM_bme_b             = 15,
9901 +       PCISM_bme_m             = 0x00008000,
9902 +       PCISM_prd_b             = 16,
9903 +       PCISM_prd_m             = 0x00010000,
9904 +       PCISM_rip_b             = 17,
9905 +       PCISM_rip_m             = 0x00020000,
9906 +} ;
9907 +
9908 +/*******************************************************************************
9909 + *
9910 + * PCI Configuration Address Register
9911 + *
9912 + ******************************************************************************/
9913 +enum {
9914 +       PCICFGA_reg_b           = 2,
9915 +       PCICFGA_reg_m           = 0x000000fc,
9916 +               PCICFGA_reg_id_v        = 0x00>>2, //use PCFGID_
9917 +               PCICFGA_reg_04_v        = 0x04>>2, //use PCFG04_
9918 +               PCICFGA_reg_08_v        = 0x08>>2, //use PCFG08_
9919 +               PCICFGA_reg_0C_v        = 0x0C>>2, //use PCFG0C_
9920 +               PCICFGA_reg_pba0_v      = 0x10>>2, //use PCIPBA_
9921 +               PCICFGA_reg_pba1_v      = 0x14>>2, //use PCIPBA_
9922 +               PCICFGA_reg_pba2_v      = 0x18>>2, //use PCIPBA_
9923 +               PCICFGA_reg_pba3_v      = 0x1c>>2, //use PCIPBA_
9924 +               PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
9925 +               PCICFGA_reg_3C_v        = 0x3C>>2, //use PCFG3C_
9926 +               PCICFGA_reg_pba0c_v     = 0x44>>2, //use PCIPBAC_
9927 +               PCICFGA_reg_pba0m_v     = 0x48>>2,
9928 +               PCICFGA_reg_pba1c_v     = 0x4c>>2, //use PCIPBAC_
9929 +               PCICFGA_reg_pba1m_v     = 0x50>>2,
9930 +               PCICFGA_reg_pba2c_v     = 0x54>>2, //use PCIPBAC_
9931 +               PCICFGA_reg_pba2m_v     = 0x58>>2,
9932 +               PCICFGA_reg_pba3c_v     = 0x5c>>2, //use PCIPBAC_
9933 +               PCICFGA_reg_pba3m_v     = 0x60>>2,
9934 +               PCICFGA_reg_pmgt_v      = 0x64>>2,
9935 +       PCICFGA_func_b          = 8,
9936 +       PCICFGA_func_m          = 0x00000700,
9937 +       PCICFGA_dev_b           = 11,
9938 +       PCICFGA_dev_m           = 0x0000f800,
9939 +               PCICFGA_dev_internal_v  = 0,
9940 +       PCICFGA_bus_b           = 16,
9941 +       PCICFGA_bus_m           = 0x00ff0000,
9942 +               PCICFGA_bus_type0_v     = 0,    //local bus
9943 +       PCICFGA_en_b            = 31,           // read only
9944 +       PCICFGA_en_m            = 0x80000000,
9945 +} ;
9946 +
9947 +enum {
9948 +       PCFGID_vendor_b         = 0,
9949 +       PCFGID_vendor_m         = 0x0000ffff,
9950 +               PCFGID_vendor_IDT_v             = 0x111d,
9951 +       PCFGID_device_b         = 16,
9952 +       PCFGID_device_m         = 0xffff0000,
9953 +               PCFGID_device_Acaciade_v        = 0x0207,
9954 +
9955 +       PCFG04_command_ioena_b          = 1,
9956 +       PCFG04_command_ioena_m          = 0x00000001,
9957 +       PCFG04_command_memena_b         = 2,
9958 +       PCFG04_command_memena_m         = 0x00000002,
9959 +       PCFG04_command_bmena_b          = 3,
9960 +       PCFG04_command_bmena_m          = 0x00000004,
9961 +       PCFG04_command_mwinv_b          = 5,
9962 +       PCFG04_command_mwinv_m          = 0x00000010,
9963 +       PCFG04_command_parena_b         = 7,
9964 +       PCFG04_command_parena_m         = 0x00000040,
9965 +       PCFG04_command_serrena_b        = 9,
9966 +       PCFG04_command_serrena_m        = 0x00000100,
9967 +       PCFG04_command_fastbbena_b      = 10,
9968 +       PCFG04_command_fastbbena_m      = 0x00000200,
9969 +       PCFG04_status_b                 = 16,
9970 +       PCFG04_status_m                 = 0xffff0000,
9971 +       PCFG04_status_66MHz_b           = 21,   // 66 MHz enable
9972 +       PCFG04_status_66MHz_m           = 0x00200000,
9973 +       PCFG04_status_fbb_b             = 23,
9974 +       PCFG04_status_fbb_m             = 0x00800000,
9975 +       PCFG04_status_mdpe_b            = 24,
9976 +       PCFG04_status_mdpe_m            = 0x01000000,
9977 +       PCFG04_status_dst_b             = 25,
9978 +       PCFG04_status_dst_m             = 0x06000000,
9979 +       PCFG04_status_sta_b             = 27,
9980 +       PCFG04_status_sta_m             = 0x08000000,
9981 +       PCFG04_status_rta_b             = 28,
9982 +       PCFG04_status_rta_m             = 0x10000000,
9983 +       PCFG04_status_rma_b             = 29,
9984 +       PCFG04_status_rma_m             = 0x20000000,
9985 +       PCFG04_status_sse_b             = 30,
9986 +       PCFG04_status_sse_m             = 0x40000000,
9987 +       PCFG04_status_pe_b              = 31,
9988 +       PCFG04_status_pe_m              = 0x40000000,
9989 +
9990 +       PCFG08_revId_b                  = 0,
9991 +       PCFG08_revId_m                  = 0x000000ff,
9992 +       PCFG08_classCode_b              = 0,
9993 +       PCFG08_classCode_m              = 0xffffff00,
9994 +               PCFG08_classCode_bridge_v       = 06,
9995 +               PCFG08_classCode_proc_v         = 0x0b3000, // processor-MIPS
9996 +       PCFG0C_cacheline_b              = 0,
9997 +       PCFG0C_cacheline_m              = 0x000000ff,
9998 +       PCFG0C_masterLatency_b          = 8,
9999 +       PCFG0C_masterLatency_m          = 0x0000ff00,
10000 +       PCFG0C_headerType_b             = 16,
10001 +       PCFG0C_headerType_m             = 0x00ff0000,
10002 +       PCFG0C_bist_b                   = 24,
10003 +       PCFG0C_bist_m                   = 0xff000000,
10004 +
10005 +       PCIPBA_msi_b                    = 0,
10006 +       PCIPBA_msi_m                    = 0x00000001,
10007 +       PCIPBA_p_b                      = 3,
10008 +       PCIPBA_p_m                      = 0x00000004,
10009 +       PCIPBA_baddr_b                  = 8,
10010 +       PCIPBA_baddr_m                  = 0xffffff00,
10011 +
10012 +       PCFGSS_vendorId_b               = 0,
10013 +       PCFGSS_vendorId_m               = 0x0000ffff,
10014 +       PCFGSS_id_b                     = 16,
10015 +       PCFGSS_id_m                     = 0xffff0000,
10016 +
10017 +       PCFG3C_interruptLine_b          = 0,
10018 +       PCFG3C_interruptLine_m          = 0x000000ff,
10019 +       PCFG3C_interruptPin_b           = 8,
10020 +       PCFG3C_interruptPin_m           = 0x0000ff00,
10021 +       PCFG3C_minGrant_b               = 16,
10022 +       PCFG3C_minGrant_m               = 0x00ff0000,
10023 +       PCFG3C_maxLat_b                 = 24,
10024 +       PCFG3C_maxLat_m                 = 0xff000000,
10025 +
10026 +       PCIPBAC_msi_b                   = 0,
10027 +       PCIPBAC_msi_m                   = 0x00000001,
10028 +       PCIPBAC_p_b                     = 1,
10029 +       PCIPBAC_p_m                     = 0x00000002,
10030 +       PCIPBAC_size_b                  = 2,
10031 +       PCIPBAC_size_m                  = 0x0000007c,
10032 +       PCIPBAC_sb_b                    = 7,
10033 +       PCIPBAC_sb_m                    = 0x00000080,
10034 +       PCIPBAC_pp_b                    = 8,
10035 +       PCIPBAC_pp_m                    = 0x00000100,
10036 +       PCIPBAC_mr_b                    = 9,
10037 +       PCIPBAC_mr_m                    = 0x00000600,
10038 +               PCIPBAC_mr_read_v       =0,     //no prefetching
10039 +               PCIPBAC_mr_readLine_v   =1,
10040 +               PCIPBAC_mr_readMult_v   =2,
10041 +       PCIPBAC_mrl_b                   = 11,
10042 +       PCIPBAC_mrl_m                   = 0x00000800,
10043 +       PCIPBAC_mrm_b                   = 12,
10044 +       PCIPBAC_mrm_m                   = 0x00001000,
10045 +       PCIPBAC_trp_b                   = 13,
10046 +       PCIPBAC_trp_m                   = 0x00002000,
10047 +
10048 +       PCFG40_trdyTimeout_b            = 0,
10049 +       PCFG40_trdyTimeout_m            = 0x000000ff,
10050 +       PCFG40_retryLim_b               = 8,
10051 +       PCFG40_retryLim_m               = 0x0000ff00,
10052 +};
10053 +
10054 +/*******************************************************************************
10055 + *
10056 + * PCI Local Base Address [0|1|2|3] Register
10057 + *
10058 + ******************************************************************************/
10059 +enum {
10060 +       PCILBA_baddr_b          = 0,            // In PCI_t -> pcilba [] .a
10061 +       PCILBA_baddr_m          = 0xffffff00,
10062 +} ;
10063 +/*******************************************************************************
10064 + *
10065 + * PCI Local Base Address Control Register
10066 + *
10067 + ******************************************************************************/
10068 +enum {
10069 +       PCILBAC_msi_b           = 0,            // In pPci->pcilba[i].c
10070 +       PCILBAC_msi_m           = 0x00000001,
10071 +               PCILBAC_msi_mem_v       = 0,
10072 +               PCILBAC_msi_io_v        = 1,
10073 +       PCILBAC_size_b          = 2,    // In pPci->pcilba[i].c
10074 +       PCILBAC_size_m          = 0x0000007c,
10075 +       PCILBAC_sb_b            = 7,    // In pPci->pcilba[i].c
10076 +       PCILBAC_sb_m            = 0x00000080,
10077 +       PCILBAC_rt_b            = 8,    // In pPci->pcilba[i].c
10078 +       PCILBAC_rt_m            = 0x00000100,
10079 +               PCILBAC_rt_noprefetch_v = 0, // mem read
10080 +               PCILBAC_rt_prefetch_v   = 1, // mem readline
10081 +} ;
10082 +
10083 +/*******************************************************************************
10084 + *
10085 + * PCI Local Base Address [0|1|2|3] Mapping Register
10086 + *
10087 + ******************************************************************************/
10088 +enum {
10089 +       PCILBAM_maddr_b         = 8,
10090 +       PCILBAM_maddr_m         = 0xffffff00,
10091 +} ;
10092 +
10093 +/*******************************************************************************
10094 + *
10095 + * PCI Decoupled Access Control Register
10096 + *
10097 + ******************************************************************************/
10098 +enum {
10099 +       PCIDAC_den_b            = 0,
10100 +       PCIDAC_den_m            = 0x00000001,
10101 +} ;
10102 +
10103 +/*******************************************************************************
10104 + *
10105 + * PCI Decoupled Access Status Register
10106 + *
10107 + ******************************************************************************/
10108 +enum {
10109 +       PCIDAS_d_b      = 0,
10110 +       PCIDAS_d_m      = 0x00000001,
10111 +       PCIDAS_b_b      = 1,
10112 +       PCIDAS_b_m      = 0x00000002,
10113 +       PCIDAS_e_b      = 2,
10114 +       PCIDAS_e_m      = 0x00000004,
10115 +       PCIDAS_ofe_b    = 3,
10116 +       PCIDAS_ofe_m    = 0x00000008,
10117 +       PCIDAS_off_b    = 4,
10118 +       PCIDAS_off_m    = 0x00000010,
10119 +       PCIDAS_ife_b    = 5,
10120 +       PCIDAS_ife_m    = 0x00000020,
10121 +       PCIDAS_iff_b    = 6,
10122 +       PCIDAS_iff_m    = 0x00000040,
10123 +} ;
10124 +
10125 +/*******************************************************************************
10126 + *
10127 + * PCI DMA Channel 8 Configuration Register
10128 + *
10129 + ******************************************************************************/
10130 +enum
10131 +{
10132 +       PCIDMA8C_mbs_b  = 0,            // Maximum Burst Size.
10133 +       PCIDMA8C_mbs_m  = 0x00000fff,   // { pcidma8c }
10134 +       PCIDMA8C_our_b  = 12,           // Optimize Unaligned Burst Reads.
10135 +       PCIDMA8C_our_m  = 0x00001000,   // { pcidma8c }
10136 +} ;
10137 +
10138 +/*******************************************************************************
10139 + *
10140 + * PCI DMA Channel 9 Configuration Register
10141 + *
10142 + ******************************************************************************/
10143 +enum
10144 +{
10145 +       PCIDMA9C_mbs_b  = 0,            // Maximum Burst Size.
10146 +       PCIDMA9C_mbs_m  = 0x00000fff, // { pcidma9c }
10147 +} ;
10148 +
10149 +/*******************************************************************************
10150 + *
10151 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
10152 + *
10153 + ******************************************************************************/
10154 +enum {
10155 +       PCIDMAD_pt_b            = 22,           // in DEVCMD field (descriptor)
10156 +       PCIDMAD_pt_m            = 0x00c00000,   // preferred transaction field
10157 +               // These are for reads (DMA channel 8)
10158 +               PCIDMAD_devcmd_mr_v     = 0,    //memory read
10159 +               PCIDMAD_devcmd_mrl_v    = 1,    //memory read line
10160 +               PCIDMAD_devcmd_mrm_v    = 2,    //memory read multiple
10161 +               PCIDMAD_devcmd_ior_v    = 3,    //I/O read
10162 +               // These are for writes (DMA channel 9)
10163 +               PCIDMAD_devcmd_mw_v     = 0,    //memory write
10164 +               PCIDMAD_devcmd_mwi_v    = 1,    //memory write invalidate
10165 +               PCIDMAD_devcmd_iow_v    = 3,    //I/O write
10166 +
10167 +       // Swap byte field applies to both DMA channel 8 and 9
10168 +       PCIDMAD_sb_b            = 24,           // in DEVCMD field (descriptor)
10169 +       PCIDMAD_sb_m            = 0x01000000,   // swap byte field
10170 +} ;
10171 +
10172 +
10173 +/*******************************************************************************
10174 + *
10175 + * PCI Target Control Register
10176 + *
10177 + ******************************************************************************/
10178 +enum
10179 +{
10180 +       PCITC_rtimer_b          = 0,            // In PCITC_t -> pcitc
10181 +       PCITC_rtimer_m          = 0x000000ff,
10182 +       PCITC_dtimer_b          = 8,            // In PCITC_t -> pcitc
10183 +       PCITC_dtimer_m          = 0x0000ff00,
10184 +       PCITC_rdr_b             = 18,           // In PCITC_t -> pcitc
10185 +       PCITC_rdr_m             = 0x00040000,
10186 +       PCITC_ddt_b             = 19,           // In PCITC_t -> pcitc
10187 +       PCITC_ddt_m             = 0x00080000,
10188 +} ;
10189 +/*******************************************************************************
10190 + *
10191 + * PCI messaging unit [applies to both inbound and outbound registers ]
10192 + *
10193 + ******************************************************************************/
10194 +enum
10195 +{
10196 +       PCIM_m0_b       = 0,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10197 +       PCIM_m0_m       = 0x00000001,   // inbound or outbound message 0
10198 +       PCIM_m1_b       = 1,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10199 +       PCIM_m1_m       = 0x00000002,   // inbound or outbound message 1
10200 +       PCIM_db_b       = 2,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10201 +       PCIM_db_m       = 0x00000004,   // inbound or outbound doorbell
10202 +};
10203 +
10204 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h
10205 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h    1970-01-01 01:00:00.000000000 +0100
10206 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h       2006-06-18 12:44:28.000000000 +0200
10207 @@ -0,0 +1,190 @@
10208 +/**************************************************************************
10209 + *
10210 + *  BRIEF MODULE DESCRIPTION
10211 + *   Definitions for IDT RC32438 PCI setup.
10212 + *
10213 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
10214 + *
10215 + *  This program is free software; you can redistribute  it and/or modify it
10216 + *  under  the terms of  the GNU General  Public License as published by the
10217 + *  Free Software Foundation;  either version 2 of the  License, or (at your
10218 + *  option) any later version.
10219 + *
10220 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
10221 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
10222 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
10223 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
10224 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10225 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
10226 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10227 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
10228 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10229 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10230 + *
10231 + *  You should have received a copy of the  GNU General Public License along
10232 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
10233 + *  675 Mass Ave, Cambridge, MA 02139, USA.
10234 + *
10235 + *
10236 + **************************************************************************
10237 + * May 2004 P. Sadik
10238 + *
10239 + * Initial Release
10240 + *
10241 + *
10242 + *
10243 + **************************************************************************
10244 + */
10245 +
10246 +#define PCI_MSG_VirtualAddress      0xB8088010
10247 +#define rc32438_pci ((volatile PCI_t) PCI0_VirtualAddress)
10248 +#define rc32438_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
10249 +
10250 +#define PCIM_SHFT              0x6
10251 +#define PCIM_BIT_LEN           0x7
10252 +#define PCIM_H_EA              0x3
10253 +#define PCIM_H_IA_FIX          0x4
10254 +#define PCIM_H_IA_RR           0x5
10255 +
10256 +#define PCI_ADDR_START         0x50000000
10257 +
10258 +#define CPUTOPCI_MEM_WIN       0x02000000
10259 +#define CPUTOPCI_IO_WIN                0x00100000
10260 +#define PCILBA_SIZE_SHFT       2
10261 +#define PCILBA_SIZE_MASK       0x1F
10262 +#define SIZE_256MB             0x1C
10263 +#define SIZE_128MB             0x1B
10264 +#define SIZE_64MB               0x1A
10265 +#define SIZE_32MB              0x19
10266 +#define SIZE_16MB               0x18
10267 +#define SIZE_4MB               0x16
10268 +#define SIZE_2MB               0x15
10269 +#define SIZE_1MB               0x14
10270 +#define ACACIA_CONFIG0_ADDR    0x80000000
10271 +#define ACACIA_CONFIG1_ADDR    0x80000004
10272 +#define ACACIA_CONFIG2_ADDR    0x80000008
10273 +#define ACACIA_CONFIG3_ADDR    0x8000000C
10274 +#define ACACIA_CONFIG4_ADDR    0x80000010
10275 +#define ACACIA_CONFIG5_ADDR    0x80000014
10276 +#define ACACIA_CONFIG6_ADDR    0x80000018
10277 +#define ACACIA_CONFIG7_ADDR    0x8000001C
10278 +#define ACACIA_CONFIG8_ADDR    0x80000020
10279 +#define ACACIA_CONFIG9_ADDR    0x80000024
10280 +#define ACACIA_CONFIG10_ADDR   0x80000028
10281 +#define ACACIA_CONFIG11_ADDR   0x8000002C
10282 +#define ACACIA_CONFIG12_ADDR   0x80000030
10283 +#define ACACIA_CONFIG13_ADDR   0x80000034
10284 +#define ACACIA_CONFIG14_ADDR   0x80000038
10285 +#define ACACIA_CONFIG15_ADDR   0x8000003C
10286 +#define ACACIA_CONFIG16_ADDR   0x80000040
10287 +#define ACACIA_CONFIG17_ADDR   0x80000044
10288 +#define ACACIA_CONFIG18_ADDR   0x80000048
10289 +#define ACACIA_CONFIG19_ADDR   0x8000004C
10290 +#define ACACIA_CONFIG20_ADDR   0x80000050
10291 +#define ACACIA_CONFIG21_ADDR   0x80000054
10292 +#define ACACIA_CONFIG22_ADDR   0x80000058
10293 +#define ACACIA_CONFIG23_ADDR   0x8000005C
10294 +#define ACACIA_CONFIG24_ADDR   0x80000060
10295 +#define ACACIA_CONFIG25_ADDR   0x80000064
10296 +#define ACACIA_CMD             (PCFG04_command_ioena_m | \
10297 +                                PCFG04_command_memena_m | \
10298 +                                PCFG04_command_bmena_m | \
10299 +                                PCFG04_command_mwinv_m | \
10300 +                                PCFG04_command_parena_m | \
10301 +                                PCFG04_command_serrena_m )
10302 +
10303 +#define ACACIA_STAT            (PCFG04_status_mdpe_m | \
10304 +                                PCFG04_status_sta_m  | \
10305 +                                PCFG04_status_rta_m  | \
10306 +                                PCFG04_status_rma_m  | \
10307 +                                PCFG04_status_sse_m  | \
10308 +                                PCFG04_status_pe_m)
10309 +
10310 +#define ACACIA_CNFG1           ((ACACIA_STAT<<16)|ACACIA_CMD)
10311 +
10312 +#define ACACIA_REVID           0
10313 +#define ACACIA_CLASS_CODE      0
10314 +#define ACACIA_CNFG2           ((ACACIA_CLASS_CODE<<8) | \
10315 +                                 ACACIA_REVID)
10316 +
10317 +#define ACACIA_CACHE_LINE_SIZE 4
10318 +#define ACACIA_MASTER_LAT      0x3c
10319 +#define ACACIA_HEADER_TYPE     0
10320 +#define ACACIA_BIST            0
10321 +
10322 +#define ACACIA_CNFG3 ((ACACIA_BIST << 24) | \
10323 +                     (ACACIA_HEADER_TYPE<<16) | \
10324 +                     (ACACIA_MASTER_LAT<<8) | \
10325 +                     ACACIA_CACHE_LINE_SIZE )
10326 +
10327 +#define ACACIA_BAR0    0x00000008 /* 128 MB Memory */
10328 +#define ACACIA_BAR1    0x18800001 /* 1 MB IO */
10329 +#define ACACIA_BAR2    0x18000001 /* 2 MB IO window for Acacia
10330 +                                       internal Registers */
10331 +#define ACACIA_BAR3    0x48000008 /* Spare 128 MB Memory */
10332 +
10333 +#define ACACIA_CNFG4   ACACIA_BAR0
10334 +#define ACACIA_CNFG5    ACACIA_BAR1
10335 +#define ACACIA_CNFG6   ACACIA_BAR2
10336 +#define ACACIA_CNFG7   ACACIA_BAR3
10337 +
10338 +#define ACACIA_SUBSYS_VENDOR_ID 0
10339 +#define ACACIA_SUBSYSTEM_ID    0
10340 +#define ACACIA_CNFG8           0
10341 +#define ACACIA_CNFG9           0
10342 +#define ACACIA_CNFG10          0
10343 +#define ACACIA_CNFG11  ((ACACIA_SUBSYS_VENDOR_ID<<16) | \
10344 +                         ACACIA_SUBSYSTEM_ID)
10345 +#define ACACIA_INT_LINE                1
10346 +#define ACACIA_INT_PIN         1
10347 +#define ACACIA_MIN_GNT         8
10348 +#define ACACIA_MAX_LAT         0x38
10349 +#define ACACIA_CNFG12          0
10350 +#define ACACIA_CNFG13          0
10351 +#define ACACIA_CNFG14          0
10352 +#define ACACIA_CNFG15  ((ACACIA_MAX_LAT<<24) | \
10353 +                        (ACACIA_MIN_GNT<<16) | \
10354 +                        (ACACIA_INT_PIN<<8)  | \
10355 +                         ACACIA_INT_LINE)
10356 +#define        ACACIA_RETRY_LIMIT      0x80
10357 +#define ACACIA_TRDY_LIMIT      0x80
10358 +#define ACACIA_CNFG16 ((ACACIA_RETRY_LIMIT<<8) | \
10359 +                       ACACIA_TRDY_LIMIT)
10360 +#define PCI_PBAxC_R            0x0
10361 +#define PCI_PBAxC_RL           0x1
10362 +#define PCI_PBAxC_RM           0x2
10363 +#define SIZE_SHFT              2
10364 +
10365 +#define ACACIA_PBA0C   ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
10366 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
10367 +                         PCIPBAC_pp_m | \
10368 +                         (SIZE_128MB<<SIZE_SHFT) | \
10369 +                          PCIPBAC_p_m)
10370 +
10371 +#define ACACIA_CNFG17  ACACIA_PBA0C
10372 +#define ACACIA_PBA0M   0x0
10373 +#define ACACIA_CNFG18  ACACIA_PBA0M
10374 +
10375 +#define ACACIA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10376 +                         PCIPBAC_msi_m)
10377 +
10378 +#define ACACIA_CNFG19  ACACIA_PBA1C
10379 +#define ACACIA_PBA1M   0x0
10380 +#define ACACIA_CNFG20  ACACIA_PBA1M
10381 +
10382 +#define ACACIA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10383 +                         PCIPBAC_msi_m)
10384 +
10385 +#define ACACIA_CNFG21  ACACIA_PBA2C
10386 +#define ACACIA_PBA2M   0x18000000
10387 +#define ACACIA_CNFG22  ACACIA_PBA2M
10388 +#define ACACIA_PBA3C   0
10389 +#define ACACIA_CNFG23  ACACIA_PBA3C
10390 +#define ACACIA_PBA3M   0
10391 +#define ACACIA_CNFG24  ACACIA_PBA3M
10392 +
10393 +
10394 +
10395 +#define        PCITC_DTIMER_VAL        8
10396 +#define PCITC_RTIMER_VAL       0x10
10397 +
10398 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_timer.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h
10399 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_timer.h    1970-01-01 01:00:00.000000000 +0100
10400 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h       2006-06-18 12:44:28.000000000 +0200
10401 @@ -0,0 +1,91 @@
10402 +/**************************************************************************
10403 + *
10404 + *  BRIEF MODULE DESCRIPTION
10405 + *    Timer register definition IDT RC32438 CPU.
10406 + *
10407 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
10408 + *
10409 + *  This program is free software; you can redistribute  it and/or modify it
10410 + *  under  the terms of  the GNU General  Public License as published by the
10411 + *  Free Software Foundation;  either version 2 of the  License, or (at your
10412 + *  option) any later version.
10413 + *
10414 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
10415 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
10416 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
10417 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
10418 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10419 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
10420 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10421 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
10422 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10423 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10424 + *
10425 + *  You should have received a copy of the  GNU General Public License along
10426 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
10427 + *  675 Mass Ave, Cambridge, MA 02139, USA.
10428 + *
10429 + *
10430 + **************************************************************************
10431 + * May 2004 P. Sadik.
10432 + *
10433 + * Initial Release
10434 + *
10435 + *
10436 + *
10437 + **************************************************************************
10438 + */
10439 +
10440 +#ifndef __IDT_RC32438_TIM_H__
10441 +#define __IDT_RC32438_TIM_H__
10442 +
10443 +enum
10444 +{
10445 +       TIM0_PhysicalAddress    = 0x18028000,
10446 +       TIM_PhysicalAddress     = TIM0_PhysicalAddress,         // Default
10447 +
10448 +       TIM0_VirtualAddress     = 0xb8028000,
10449 +       TIM_VirtualAddress      = TIM0_VirtualAddress,          // Default
10450 +} ;
10451 +
10452 +enum
10453 +{
10454 +       TIM_Count = 3,
10455 +} ;
10456 +
10457 +struct TIM_CNTR_s
10458 +{
10459 +       u32 count ;
10460 +       u32 compare ;
10461 +       u32 ctc ;       //use CTC_
10462 +} ;
10463 +
10464 +typedef struct TIM_s
10465 +{
10466 +       struct TIM_CNTR_s       tim [TIM_Count] ;
10467 +       u32                     rcount ;        //use RCOUNT_
10468 +       u32                     rcompare ;      //use RCOMPARE_
10469 +       u32                     rtc ;           //use RTC_
10470 +} volatile * TIM_t ;
10471 +
10472 +enum
10473 +{
10474 +       CTC_en_b        = 0,
10475 +       CTC_en_m        = 0x00000001,
10476 +       CTC_to_b        = 1,
10477 +       CTC_to_m        = 0x00000002,
10478 +
10479 +       RCOUNT_count_b          = 0,
10480 +       RCOUNT_count_m          = 0x0000ffff,
10481 +       RCOMPARE_compare_b      = 0,
10482 +       RCOMPARE_compare_m      = 0x0000ffff,
10483 +       RTC_ce_b                = 0,
10484 +       RTC_ce_m                = 0x00000001,
10485 +       RTC_to_b                = 1,
10486 +       RTC_to_m                = 0x00000002,
10487 +       RTC_rqe_b               = 2,
10488 +       RTC_rqe_m               = 0x00000004,
10489 +
10490 +} ;
10491 +#endif //__IDT_RC32438_TIM_H__
10492 +
10493 diff -Nur linux-2.6.17/include/asm-mips/mach-generic/irq.h linux-2.6.17-owrt/include/asm-mips/mach-generic/irq.h
10494 --- linux-2.6.17/include/asm-mips/mach-generic/irq.h    2006-06-18 03:49:35.000000000 +0200
10495 +++ linux-2.6.17-owrt/include/asm-mips/mach-generic/irq.h       2006-06-18 12:44:28.000000000 +0200
10496 @@ -8,6 +8,6 @@
10497  #ifndef __ASM_MACH_GENERIC_IRQ_H
10498  #define __ASM_MACH_GENERIC_IRQ_H
10499
10500 -#define NR_IRQS        128
10501 +#define NR_IRQS        256
10502
10503  #endif /* __ASM_MACH_GENERIC_IRQ_H */
10504 diff -Nur linux-2.6.17/include/linux/kernel.h linux-2.6.17-owrt/include/linux/kernel.h
10505 --- linux-2.6.17/include/linux/kernel.h 2006-06-18 03:49:35.000000000 +0200
10506 +++ linux-2.6.17-owrt/include/linux/kernel.h    2006-06-18 12:44:28.000000000 +0200
10507 @@ -329,6 +329,7 @@
10508  };
10509
10510  /* Force a compilation error if condition is true */
10511 +extern void BUILD_BUG(void);
10512  #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
10513
10514  /* Trap pasters of __FUNCTION__ at compile-time */