target/linux/aruba-2.6/patches/000-aruba.patch

   1 diff -Nur linux-2.6.17/arch/mips/aruba/Makefile linux-2.6.17-owrt/arch/mips/aruba/Makefile
   2 --- linux-2.6.17/arch/mips/aruba/Makefile       1970-01-01 01:00:00.000000000 +0100
   3 +++ linux-2.6.17-owrt/arch/mips/aruba/Makefile  2006-06-18 12:44:28.000000000 +0200
   4 @@ -0,0 +1,49 @@
   5 +###############################################################################
   6 +#
   7 +#  BRIEF MODULE DESCRIPTION
   8 +#     Makefile for IDT EB434 BSP
   9 +#
  10 +#  Copyright 2004 IDT Inc. (rischelp@idt.com)
  11 +#
  12 +#  This program is free software; you can redistribute  it and/or modify it
  13 +#  under  the terms of  the GNU General  Public License as published by the
  14 +#  Free Software Foundation;  either version 2 of the  License, or (at your
  15 +#  option) any later version.
  16 +#
  17 +#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  18 +#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  19 +#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  20 +#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  21 +#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22 +#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  23 +#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  24 +#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  25 +#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26 +#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 +#
  28 +#   You should have received a copy of the  GNU General Public License along
  29 +#   with this program; if not, write  to the Free Software Foundation, Inc.,
  30 +#   675 Mass Ave, Cambridge, MA 02139, USA.
  31 +#
  32 +#
  33 +###############################################################################
  34 +#  May 2004 rkt, neb
  35 +#
  36 +#  Initial Release
  37 +#
  38 +#
  39 +#
  40 +###############################################################################
  41 +
  42 +
  43 +# .S.s:
  44 +#      $(CPP) $(CFLAGS) $< -o $*.s
  45 +# .S.o:
  46 +#      $(CC) $(CFLAGS) -c $< -o $*.o
  47 +
  48 +obj-y   := prom.o setup.o irq.o time.o flash_lock.o
  49 +obj-$(CONFIG_SERIAL_8250)              += serial.o
  50 +
  51 +subdir-y         += nvram
  52 +obj-y            += nvram/built-in.o
  53 +
  54 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/Makefile linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile
  55 --- linux-2.6.17/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
  56 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile    2006-06-18 12:44:28.000000000 +0200
  57 @@ -0,0 +1,46 @@
  58 +###############################################################################
  59 +#
  60 +#  BRIEF MODULE DESCRIPTION
  61 +#     Makefile for IDT EB434 nvram access routines
  62 +#
  63 +#  Copyright 2004 IDT Inc. (rischelp@idt.com)
  64 +#
  65 +#  This program is free software; you can redistribute  it and/or modify it
  66 +#  under  the terms of  the GNU General  Public License as published by the
  67 +#  Free Software Foundation;  either version 2 of the  License, or (at your
  68 +#  option) any later version.
  69 +#
  70 +#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  71 +#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  72 +#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  73 +#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  74 +#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  75 +#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  76 +#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  77 +#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  78 +#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  79 +#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  80 +#
  81 +#   You should have received a copy of the  GNU General Public License along
  82 +#   with this program; if not, write  to the Free Software Foundation, Inc.,
  83 +#   675 Mass Ave, Cambridge, MA 02139, USA.
  84 +#
  85 +#
  86 +###############################################################################
  87 +#  May 2004  rkt, neb
  88 +#
  89 +#  Initial Release
  90 +#
  91 +#
  92 +#
  93 +###############################################################################
  94 +
  95 +obj-y   := nvram434.o
  96 +obj-m   := $(O_TARGET)
  97 +
  98 +
  99 +
 100 +
 101 +
 102 +
 103 +
 104 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.c linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c
 105 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.c       1970-01-01 01:00:00.000000000 +0100
 106 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c  2006-06-18 12:44:28.000000000 +0200
 107 @@ -0,0 +1,392 @@
 108 +/**************************************************************************
 109 + *
 110 + *  BRIEF MODULE DESCRIPTION
 111 + *     nvram interface routines.
 112 + *
 113 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 114 + *
 115 + *  This program is free software; you can redistribute  it and/or modify it
 116 + *  under  the terms of  the GNU General  Public License as published by the
 117 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 118 + *  option) any later version.
 119 + *
 120 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 121 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 122 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 123 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 124 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 125 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 126 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 127 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 128 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 129 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 130 + *
 131 + *  You should have received a copy of the  GNU General Public License along
 132 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 133 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 134 + *
 135 + *
 136 + **************************************************************************
 137 + * May 2004 rkt, neb
 138 + *
 139 + * Initial Release
 140 + *
 141 + *
 142 + *
 143 + **************************************************************************
 144 + */
 145 +
 146 +#include <linux/ctype.h>
 147 +#include <linux/string.h>
 148 +
 149 +//#include <asm/ds1553rtc.h>
 150 +#include "nvram434.h"
 151 +#define  NVRAM_BASE 0xbfff8000
 152 +
 153 +extern void setenv (char *e, char *v, int rewrite);
 154 +extern void unsetenv (char *e);
 155 +extern void mapenv (int (*func)(char *, char *));
 156 +extern char *getenv (char *s);
 157 +extern void purgeenv(void);
 158 +
 159 +static void nvram_initenv(void);
 160 +
 161 +static unsigned char
 162 +nvram_getbyte(int offs)
 163 +{
 164 +  return(*((unsigned char*)(NVRAM_BASE + offs)));
 165 +}
 166 +
 167 +static void
 168 +nvram_setbyte(int offs, unsigned char val)
 169 +{
 170 +  unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
 171 +
 172 +  *nvramDataPointer = val;
 173 +}
 174 +
 175 +/*
 176 + * BigEndian!
 177 + */
 178 +static unsigned short
 179 +nvram_getshort(int offs)
 180 +{
 181 +  return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
 182 +}
 183 +
 184 +static void
 185 +nvram_setshort(int offs, unsigned short val)
 186 +{
 187 +  nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
 188 +  nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
 189 +}
 190 +#if 0
 191 +static unsigned int
 192 +nvram_getint(int offs)
 193 +{
 194 +  unsigned int val;
 195 +  val = nvram_getbyte(offs) << 24;
 196 +  val |= nvram_getbyte(offs + 1) << 16;
 197 +  val |= nvram_getbyte(offs + 2) << 8;
 198 +  val |= nvram_getbyte(offs + 3);
 199 +  return(val);
 200 +}
 201 +
 202 +static void
 203 +nvram_setint(int offs, unsigned int val)
 204 +{
 205 +  nvram_setbyte(offs, val >> 24);
 206 +  nvram_setbyte(offs + 1, val >> 16);
 207 +  nvram_setbyte(offs + 2, val >> 8);
 208 +  nvram_setbyte(offs + 3, val);
 209 +}
 210 +#endif
 211 +/*
 212 + * calculate NVRAM checksum
 213 + */
 214 +static unsigned short
 215 +nvram_calcsum(void)
 216 +{
 217 +  unsigned short sum = NV_MAGIC;
 218 +  int     i;
 219 +
 220 +  for (i = ENV_BASE; i < ENV_TOP; i += 2)
 221 +    sum += nvram_getshort(i);
 222 +  return(sum);
 223 +}
 224 +
 225 +/*
 226 + * update the nvram checksum
 227 + */
 228 +static void
 229 +nvram_updatesum (void)
 230 +{
 231 +  nvram_setshort(NVOFF_CSUM, nvram_calcsum());
 232 +}
 233 +
 234 +/*
 235 + * test validity of nvram by checksumming it
 236 + */
 237 +static int
 238 +nvram_isvalid(void)
 239 +{
 240 +  static int  is_valid;
 241 +
 242 +  if (is_valid)
 243 +    return(1);
 244 +
 245 +  if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
 246 +       printk("nvram_isvalid FAILED\n");
 247 +    //nvram_initenv();
 248 +  }
 249 +  is_valid = 1;
 250 +  return(1);
 251 +}
 252 +
 253 +/* return nvram address of environment string */
 254 +static int
 255 +nvram_matchenv(char *s)
 256 +{
 257 +  int envsize, envp, n, i, varsize;
 258 +  char *var;
 259 +
 260 +  envsize = nvram_getshort(NVOFF_ENVSIZE);
 261 +
 262 +  if (envsize > ENV_AVAIL)
 263 +    return(0);     /* sanity */
 264 +
 265 +  envp = ENV_BASE;
 266 +
 267 +  if ((n = strlen (s)) > 255)
 268 +    return(0);
 269 +
 270 +  while (envsize > 0) {
 271 +    varsize = nvram_getbyte(envp);
 272 +    if (varsize == 0 || (envp + varsize) > ENV_TOP)
 273 +      return(0);   /* sanity */
 274 +    for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
 275 +      char c1 = nvram_getbyte(i);
 276 +      char c2 = *var;
 277 +      if (islower(c1))
 278 +        c1 = toupper(c1);
 279 +      if (islower(c2))
 280 +        c2 = toupper(c2);
 281 +      if (c1 != c2)
 282 +        break;
 283 +    }
 284 +    if (i > envp + n) {       /* match so far */
 285 +      if (n == varsize - 1)   /* match on boolean */
 286 +        return(envp);
 287 +      if (nvram_getbyte(i) == '=')  /* exact match on variable */
 288 +        return(envp);
 289 +    }
 290 +    envsize -= varsize;
 291 +    envp += varsize;
 292 +  }
 293 +  return(0);
 294 +}
 295 +
 296 +static void nvram_initenv(void)
 297 +{
 298 +  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
 299 +  nvram_setshort(NVOFF_ENVSIZE, 0);
 300 +
 301 +  nvram_updatesum();
 302 +}
 303 +
 304 +static void
 305 +nvram_delenv(char *s)
 306 +{
 307 +  int nenvp, envp, envsize, nbytes;
 308 +
 309 +  envp = nvram_matchenv(s);
 310 +  if (envp == 0)
 311 +    return;
 312 +
 313 +  nenvp = envp + nvram_getbyte(envp);
 314 +  envsize = nvram_getshort(NVOFF_ENVSIZE);
 315 +  nbytes = envsize - (nenvp - ENV_BASE);
 316 +  nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
 317 +  while (nbytes--) {
 318 +    nvram_setbyte(envp, nvram_getbyte(nenvp));
 319 +    envp++;
 320 +    nenvp++;
 321 +  }
 322 +  nvram_updatesum();
 323 +}
 324 +
 325 +static int
 326 +nvram_setenv(char *s, char *v)
 327 +{
 328 +  int ns, nv, total;
 329 +  int envp;
 330 +
 331 +  if (!nvram_isvalid())
 332 +    return(-1);
 333 +
 334 +  nvram_delenv(s);
 335 +  ns = strlen(s);
 336 +  if (ns == 0)
 337 +    return (-1);
 338 +  if (v && *v) {
 339 +    nv = strlen(v);
 340 +    total = ns + nv + 2;
 341 +  }
 342 +  else {
 343 +    nv = 0;
 344 +    total = ns + 1;
 345 +  }
 346 +  if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
 347 +    return(-1);
 348 +
 349 +  envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
 350 +
 351 +  nvram_setbyte(envp, (unsigned char) total);
 352 +  envp++;
 353 +
 354 +  while (ns--) {
 355 +    nvram_setbyte(envp, *s);
 356 +    envp++;
 357 +    s++;
 358 +  }
 359 +
 360 +  if (nv) {
 361 +    nvram_setbyte(envp, '=');
 362 +    envp++;
 363 +    while (nv--) {
 364 +      nvram_setbyte(envp, *v);
 365 +      envp++;
 366 +      v++;
 367 +    }
 368 +  }
 369 +  nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
 370 +  nvram_updatesum();
 371 +  return 0;
 372 +}
 373 +
 374 +static char *
 375 +nvram_getenv(char *s)
 376 +{
 377 +  static char buf[256];   /* FIXME: this cannot be static */
 378 +  int envp, ns, nbytes, i;
 379 +
 380 +  if (!nvram_isvalid())
 381 +    return "INVALID NVRAM"; //((char *)0);
 382 +
 383 +  envp = nvram_matchenv(s);
 384 +  if (envp == 0)
 385 +    return "NOT FOUND"; //((char *)0);
 386 +  ns = strlen(s);
 387 +  if (nvram_getbyte(envp) == ns + 1)  /* boolean */
 388 +    buf[0] = '\0';
 389 +  else {
 390 +    nbytes = nvram_getbyte(envp) - (ns + 2);
 391 +    envp += ns + 2;
 392 +    for (i = 0; i < nbytes; i++)
 393 +      buf[i] = nvram_getbyte(envp++);
 394 +    buf[i] = '\0';
 395 +  }
 396 +  return(buf);
 397 +}
 398 +
 399 +static void
 400 +nvram_unsetenv(char *s)
 401 +{
 402 +  if (!nvram_isvalid())
 403 +    return;
 404 +
 405 +  nvram_delenv(s);
 406 +}
 407 +
 408 +/*
 409 + * apply func to each string in environment
 410 + */
 411 +static void
 412 +nvram_mapenv(int (*func)(char *, char *))
 413 +{
 414 +  int envsize, envp, n, i, seeneql;
 415 +  char name[256], value[256];
 416 +  char c, *s;
 417 +
 418 +  if (!nvram_isvalid())
 419 +    return;
 420 +
 421 +  envsize = nvram_getshort(NVOFF_ENVSIZE);
 422 +  envp = ENV_BASE;
 423 +
 424 +  while (envsize > 0) {
 425 +    value[0] = '\0';
 426 +    seeneql = 0;
 427 +    s = name;
 428 +    n = nvram_getbyte(envp);
 429 +    for (i = envp + 1; i < envp + n; i++) {
 430 +      c = nvram_getbyte(i);
 431 +      if ((c == '=') && !seeneql) {
 432 +        *s = '\0';
 433 +        s = value;
 434 +        seeneql = 1;
 435 +        continue;
 436 +      }
 437 +      *s++ = c;
 438 +    }
 439 +    *s = '\0';
 440 +    (*func)(name, value);
 441 +    envsize -= n;
 442 +    envp += n;
 443 +  }
 444 +}
 445 +#if 0
 446 +static unsigned int
 447 +digit(char c)
 448 +{
 449 +  if ('0' <= c && c <= '9')
 450 +    return (c - '0');
 451 +  if ('A' <= c && c <= 'Z')
 452 +    return (10 + c - 'A');
 453 +  if ('a' <= c && c <= 'z')
 454 +    return (10 + c - 'a');
 455 +  return (~0);
 456 +}
 457 +#endif
 458 +/*
 459 + * Wrappers to allow 'special' environment variables to get processed
 460 + */
 461 +void
 462 +setenv(char *e, char *v, int rewrite)
 463 +{
 464 +  if (nvram_getenv(e) && !rewrite)
 465 +    return;
 466 +
 467 +  nvram_setenv(e, v);
 468 +}
 469 +
 470 +char *
 471 +getenv(char *e)
 472 +{
 473 +  return(nvram_getenv(e));
 474 +}
 475 +
 476 +void
 477 +unsetenv(char *e)
 478 +{
 479 +  nvram_unsetenv(e);
 480 +}
 481 +
 482 +void
 483 +purgeenv()
 484 +{
 485 +  int i;
 486 +  unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
 487 +
 488 +  for (i = ENV_BASE; i < ENV_TOP; i++)
 489 +    *nvramDataPointer++ = 0;
 490 +  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
 491 +  nvram_setshort(NVOFF_ENVSIZE, 0);
 492 +  nvram_setshort(NVOFF_CSUM, NV_MAGIC);
 493 +}
 494 +
 495 +void
 496 +mapenv(int (*func)(char *, char *))
 497 +{
 498 +  nvram_mapenv(func);
 499 +}
 500 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.h linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h
 501 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.h       1970-01-01 01:00:00.000000000 +0100
 502 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h  2006-06-18 12:44:28.000000000 +0200
 503 @@ -0,0 +1,66 @@
 504 +/**************************************************************************
 505 + *
 506 + *  BRIEF MODULE DESCRIPTION
 507 + *     nvram definitions.
 508 + *
 509 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 510 + *
 511 + *  This program is free software; you can redistribute  it and/or modify it
 512 + *  under  the terms of  the GNU General  Public License as published by the
 513 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 514 + *  option) any later version.
 515 + *
 516 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 517 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 518 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 519 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 520 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 521 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 522 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 523 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 524 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 525 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 526 + *
 527 + *  You should have received a copy of the  GNU General Public License along
 528 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 529 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 530 + *
 531 + *
 532 + **************************************************************************
 533 + * May 2004 rkt, neb
 534 + *
 535 + * Initial Release
 536 + *
 537 + *
 538 + *
 539 + **************************************************************************
 540 + */
 541 +
 542 +
 543 +#ifndef _NVRAM_
 544 +#define _NVRAM_
 545 +#define NVOFFSET        0                 /* use all of NVRAM */
 546 +
 547 +/* Offsets to reserved locations */
 548 +              /* size description */
 549 +#define NVOFF_MAGIC     (NVOFFSET + 0)    /* 2 magic value */
 550 +#define NVOFF_CSUM      (NVOFFSET + 2)    /* 2 NVRAM environment checksum */
 551 +#define NVOFF_ENVSIZE   (NVOFFSET + 4)    /* 2 size of 'environment' */
 552 +#define NVOFF_TEST      (NVOFFSET + 5)    /* 1 cold start test byte */
 553 +#define NVOFF_ETHADDR   (NVOFFSET + 6)    /* 6 decoded ethernet address */
 554 +#define NVOFF_UNUSED    (NVOFFSET + 12)   /* 0 current end of table */
 555 +
 556 +#define NV_MAGIC        0xdeaf            /* nvram magic number */
 557 +#define NV_RESERVED     6                 /* number of reserved bytes */
 558 +
 559 +#undef  NVOFF_ETHADDR
 560 +#define NVOFF_ETHADDR   (NVOFFSET + NV_RESERVED - 6)
 561 +
 562 +/* number of bytes available for environment */
 563 +#define ENV_BASE        (NVOFFSET + NV_RESERVED)
 564 +#define ENV_TOP         0x2000
 565 +#define ENV_AVAIL       (ENV_TOP - ENV_BASE)
 566 +
 567 +#endif /* _NVRAM_ */
 568 +
 569 +
 570 diff -Nur linux-2.6.17/arch/mips/aruba/prom.c linux-2.6.17-owrt/arch/mips/aruba/prom.c
 571 --- linux-2.6.17/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
 572 +++ linux-2.6.17-owrt/arch/mips/aruba/prom.c    2006-06-18 12:44:28.000000000 +0200
 573 @@ -0,0 +1,114 @@
 574 +/**************************************************************************
 575 + *
 576 + *  BRIEF MODULE DESCRIPTION
 577 + *     prom interface routines
 578 + *
 579 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 580 + *
 581 + *  This program is free software; you can redistribute  it and/or modify it
 582 + *  under  the terms of  the GNU General  Public License as published by the
 583 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 584 + *  option) any later version.
 585 + *
 586 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 587 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 588 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 589 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 590 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 591 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 592 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 593 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 594 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 595 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 596 + *
 597 + *  You should have received a copy of the  GNU General Public License along
 598 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 599 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 600 + *
 601 + *
 602 + **************************************************************************
 603 + * May 2004 rkt, neb
 604 + *
 605 + * Initial Release
 606 + *
 607 + *
 608 + *
 609 + **************************************************************************
 610 + */
 611 +
 612 +#include <linux/autoconf.h>
 613 +#include <linux/init.h>
 614 +#include <linux/mm.h>
 615 +#include <linux/module.h>
 616 +#include <linux/string.h>
 617 +#include <linux/console.h>
 618 +#include <asm/bootinfo.h>
 619 +#include <linux/bootmem.h>
 620 +#include <linux/ioport.h>
 621 +#include <linux/serial.h>
 622 +#include <linux/serialP.h>
 623 +#include <asm/serial.h>
 624 +#include <linux/ioport.h>
 625 +
 626 +unsigned int idt_cpu_freq;
 627 +EXPORT_SYMBOL(idt_cpu_freq);
 628 +
 629 +unsigned int arch_has_pci=0;
 630 +
 631 +/* Kernel Boot parameters */
 632 +static unsigned char bootparm[] =
 633 +       "mtdparts=physmap-flash.0:3520k@0x080000(zImage),2752k@0x140000(JFFS2),8k@0x3f8000(NVRAM) "
 634 +       "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2 ";
 635 +
 636 +
 637 +extern unsigned long mips_machgroup;
 638 +extern unsigned long mips_machtype;
 639 +
 640 +extern void setup_serial_port(void);
 641 +extern char * getenv(char *e);
 642 +
 643 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
 644 +#define RAM_SIZE        32*1024*1024
 645 +
 646 +char *__init prom_getcmdline(void)
 647 +{
 648 +       return &(arcs_cmdline[0]);
 649 +}
 650 +
 651 +void __init prom_init(void)
 652 +{
 653 +       char *boardname;
 654 +       sprintf(arcs_cmdline, "%s", bootparm);
 655 +
 656 +       /* set our arch type */
 657 +       mips_machgroup = MACH_GROUP_ARUBA;
 658 +       mips_machtype = MACH_ARUBA_UNKNOWN;
 659 +
 660 +       boardname=getenv("boardname");
 661 +
 662 +       if (!strcmp(boardname,"Muscat")) {
 663 +               mips_machtype = MACH_ARUBA_AP70;
 664 +               idt_cpu_freq = 133000000;
 665 +               arch_has_pci=1;
 666 +       } else if (!strcmp(boardname,"Mataro")) {
 667 +               mips_machtype = MACH_ARUBA_AP65;
 668 +               idt_cpu_freq = 110000000;
 669 +       } else if (!strcmp(boardname,"Merlot")) {
 670 +               mips_machtype = MACH_ARUBA_AP60;
 671 +               idt_cpu_freq = 90000000;
 672 +       }
 673 +
 674 +       /* turn on the console */
 675 +       setup_serial_port();
 676 +
 677 +       /*
 678 +        * give all RAM to boot allocator,
 679 +        * except where the kernel was loaded
 680 +        */
 681 +       add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
 682 +}
 683 +
 684 +void prom_free_prom_memory(void)
 685 +{
 686 +       printk("stubbed prom_free_prom_memory()\n");
 687 +}
 688 diff -Nur linux-2.6.17/arch/mips/aruba/serial.c linux-2.6.17-owrt/arch/mips/aruba/serial.c
 689 --- linux-2.6.17/arch/mips/aruba/serial.c       1970-01-01 01:00:00.000000000 +0100
 690 +++ linux-2.6.17-owrt/arch/mips/aruba/serial.c  2006-06-18 12:44:28.000000000 +0200
 691 @@ -0,0 +1,94 @@
 692 +/**************************************************************************
 693 + *
 694 + *  BRIEF MODULE DESCRIPTION
 695 + *     Serial port initialisation.
 696 + *
 697 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 698 + *
 699 + *  This program is free software; you can redistribute  it and/or modify it
 700 + *  under  the terms of  the GNU General  Public License as published by the
 701 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 702 + *  option) any later version.
 703 + *
 704 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 705 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 706 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 707 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 708 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 709 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 710 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 711 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 712 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 713 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 714 + *
 715 + *  You should have received a copy of the  GNU General Public License along
 716 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 717 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 718 + *
 719 + *
 720 + **************************************************************************
 721 + * May 2004 rkt, neb
 722 + *
 723 + * Initial Release
 724 + *
 725 + *
 726 + *
 727 + **************************************************************************
 728 + */
 729 +
 730 +
 731 +#include <linux/autoconf.h>
 732 +#include <linux/init.h>
 733 +#include <linux/sched.h>
 734 +#include <linux/pci.h>
 735 +#include <linux/interrupt.h>
 736 +#include <linux/tty.h>
 737 +#include <linux/serial.h>
 738 +#include <linux/serial_core.h>
 739 +
 740 +#include <asm/time.h>
 741 +#include <asm/cpu.h>
 742 +#include <asm/bootinfo.h>
 743 +#include <asm/irq.h>
 744 +#include <asm/serial.h>
 745 +
 746 +#include <asm/idt-boards/rc32434/rc32434.h>
 747 +
 748 +extern int __init early_serial_setup(struct uart_port *port);
 749 +
 750 +#define BASE_BAUD (1843200 / 16)
 751 +
 752 +extern unsigned int idt_cpu_freq;
 753 +
 754 +extern int __init setup_serial_port(void)
 755 +{
 756 +       static struct uart_port serial_req[2];
 757 +
 758 +       memset(serial_req, 0, sizeof(serial_req));
 759 +       serial_req[0].type       = PORT_16550A;
 760 +       serial_req[0].line       = 0;
 761 +       serial_req[0].flags      = STD_COM_FLAGS;
 762 +       serial_req[0].iotype     = SERIAL_IO_MEM;
 763 +       serial_req[0].regshift   = 2;
 764 +
 765 +       switch (mips_machtype) {
 766 +               case MACH_ARUBA_AP70:
 767 +                       serial_req[0].irq        = 104;
 768 +                       serial_req[0].mapbase    = KSEG1ADDR(0x18058003);
 769 +                       serial_req[0].membase    = (char *) KSEG1ADDR(0x18058003);
 770 +                       serial_req[0].uartclk    = idt_cpu_freq;
 771 +                       break;
 772 +               case MACH_ARUBA_AP65:
 773 +               case MACH_ARUBA_AP60:
 774 +               default:
 775 +                       serial_req[0].irq        = 12;
 776 +                       serial_req[0].mapbase    = KSEG1ADDR(0xbc000003);
 777 +                       serial_req[0].membase    = (char *) KSEG1ADDR(0xbc000003);
 778 +                       serial_req[0].uartclk    = idt_cpu_freq / 2;
 779 +                       break;
 780 +       }
 781 +
 782 +       early_serial_setup(&serial_req[0]);
 783 +
 784 +       return(0);
 785 +}
 786 diff -Nur linux-2.6.17/arch/mips/aruba/setup.c linux-2.6.17-owrt/arch/mips/aruba/setup.c
 787 --- linux-2.6.17/arch/mips/aruba/setup.c        1970-01-01 01:00:00.000000000 +0100
 788 +++ linux-2.6.17-owrt/arch/mips/aruba/setup.c   2006-06-18 12:44:28.000000000 +0200
 789 @@ -0,0 +1,128 @@
 790 +/**************************************************************************
 791 + *
 792 + *  BRIEF MODULE DESCRIPTION
 793 + *     setup routines for IDT EB434 boards
 794 + *
 795 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 796 + *
 797 + *  This program is free software; you can redistribute  it and/or modify it
 798 + *  under  the terms of  the GNU General  Public License as published by the
 799 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 800 + *  option) any later version.
 801 + *
 802 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 803 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 804 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 805 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 806 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 807 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 808 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 809 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 810 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 811 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 812 + *
 813 + *  You should have received a copy of the  GNU General Public License along
 814 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 815 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 816 + *
 817 + *
 818 + **************************************************************************
 819 + * May 2004 rkt, neb
 820 + *
 821 + * Initial Release
 822 + *
 823 + *
 824 + *
 825 + **************************************************************************
 826 + */
 827 +
 828 +#include <linux/init.h>
 829 +#include <linux/module.h>
 830 +#include <linux/mm.h>
 831 +#include <linux/sched.h>
 832 +#include <linux/irq.h>
 833 +#include <asm/bootinfo.h>
 834 +#include <asm/io.h>
 835 +#include <linux/ioport.h>
 836 +#include <asm/mipsregs.h>
 837 +#include <asm/pgtable.h>
 838 +#include <asm/reboot.h>
 839 +#include <asm/addrspace.h>     /* for KSEG1ADDR() */
 840 +#include <asm/idt-boards/rc32434/rc32434.h>
 841 +#include <linux/pm.h>
 842 +
 843 +extern char *__init prom_getcmdline(void);
 844 +
 845 +extern void (*board_time_init) (void);
 846 +extern void aruba_time_init(void);
 847 +extern void aruba_reset(void);
 848 +
 849 +#define epldMask ((volatile unsigned char *)0xB900000d)
 850 +
 851 +static void aruba_machine_restart(char *command)
 852 +{
 853 +       switch (mips_machtype) {
 854 +               case MACH_ARUBA_AP70:
 855 +                       *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
 856 +                       break;
 857 +               case MACH_ARUBA_AP65:
 858 +               case MACH_ARUBA_AP60:
 859 +               default:
 860 +                       /* Reset*/
 861 +                       *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
 862 +                       udelay(100);
 863 +                       *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
 864 +                       udelay(100);
 865 +                       *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
 866 +                       break;
 867 +       }
 868 +}
 869 +
 870 +static void aruba_machine_halt(void)
 871 +{
 872 +       for (;;) continue;
 873 +}
 874 +
 875 +extern char * getenv(char *e);
 876 +extern void unlock_ap60_70_flash(void);
 877 +
 878 +void __init plat_mem_setup(void)
 879 +{
 880 +       board_time_init = aruba_time_init;
 881 +
 882 +       _machine_restart = aruba_machine_restart;
 883 +       _machine_halt = aruba_machine_halt;
 884 +       pm_power_off = aruba_machine_halt;
 885 +
 886 +       set_io_port_base(KSEG1);
 887 +
 888 +       /* Enable PCI interrupts in EPLD Mask register */
 889 +       *epldMask = 0x0;
 890 +       *(epldMask + 1) = 0x0;
 891 +
 892 +       write_c0_wired(0);
 893 +       unlock_ap60_70_flash();
 894 +
 895 +       printk("BOARD - %s\n",getenv("boardname"));
 896 +}
 897 +
 898 +int page_is_ram(unsigned long pagenr)
 899 +{
 900 +       return 1;
 901 +}
 902 +
 903 +const char *get_system_type(void)
 904 +{
 905 +       switch (mips_machtype) {
 906 +               case MACH_ARUBA_AP70:
 907 +                       return "Aruba AP70";
 908 +               case MACH_ARUBA_AP65:
 909 +                       return "Aruba AP65";
 910 +               case MACH_ARUBA_AP60:
 911 +                       return "Aruba AP60/AP61";
 912 +               default:
 913 +                       return "Aruba UNKNOWN";
 914 +       }
 915 +}
 916 +
 917 +EXPORT_SYMBOL(get_system_type);
 918 diff -Nur linux-2.6.17/arch/mips/aruba/time.c linux-2.6.17-owrt/arch/mips/aruba/time.c
 919 --- linux-2.6.17/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
 920 +++ linux-2.6.17-owrt/arch/mips/aruba/time.c    2006-06-18 12:44:28.000000000 +0200
 921 @@ -0,0 +1,110 @@
 922 +/**************************************************************************
 923 + *
 924 + *  BRIEF MODULE DESCRIPTION
 925 + *     timer routines for IDT EB434 boards
 926 + *
 927 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 928 + *
 929 + *  This program is free software; you can redistribute  it and/or modify it
 930 + *  under  the terms of  the GNU General  Public License as published by the
 931 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 932 + *  option) any later version.
 933 + *
 934 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 935 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 936 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 937 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 938 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 939 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 940 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 941 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 942 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 943 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 944 + *
 945 + *  You should have received a copy of the  GNU General Public License along
 946 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 947 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 948 + *
 949 + *
 950 + **************************************************************************
 951 + * May 2004 rkt, neb
 952 + *
 953 + * Initial Release
 954 + *
 955 + *
 956 + *
 957 + **************************************************************************
 958 + */
 959 +
 960 +#include <linux/autoconf.h>
 961 +#include <linux/init.h>
 962 +#include <linux/kernel_stat.h>
 963 +#include <linux/sched.h>
 964 +#include <linux/spinlock.h>
 965 +#include <linux/mc146818rtc.h>
 966 +#include <linux/irq.h>
 967 +#include <linux/timex.h>
 968 +
 969 +#include <linux/param.h>
 970 +#include <asm/mipsregs.h>
 971 +#include <asm/ptrace.h>
 972 +#include <asm/time.h>
 973 +#include <asm/hardirq.h>
 974 +
 975 +#include <asm/mipsregs.h>
 976 +#include <asm/ptrace.h>
 977 +#include <asm/debug.h>
 978 +#include <asm/time.h>
 979 +
 980 +#include <asm/idt-boards/rc32434/rc32434.h>
 981 +
 982 +static unsigned long r4k_offset;       /* Amount to incr compare reg each time */
 983 +static unsigned long r4k_cur;  /* What counter should be at next timer irq */
 984 +
 985 +extern unsigned int idt_cpu_freq;
 986 +
 987 +static unsigned long __init cal_r4koff(void)
 988 +{
 989 +       mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
 990 +       return (mips_hpt_frequency / HZ);
 991 +}
 992 +
 993 +void __init aruba_time_init(void)
 994 +{
 995 +       unsigned int est_freq, flags;
 996 +       local_irq_save(flags);
 997 +
 998 +       printk("calculating r4koff... ");
 999 +       r4k_offset = cal_r4koff();
1000 +       printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
1001 +
1002 +       est_freq = 2 * r4k_offset * HZ;
1003 +       est_freq += 5000;       /* round */
1004 +       est_freq -= est_freq % 10000;
1005 +       printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
1006 +              (est_freq % 1000000) * 100 / 1000000);
1007 +       local_irq_restore(flags);
1008 +
1009 +}
1010 +
1011 +void __init plat_timer_setup(struct irqaction *irq)
1012 +{
1013 +       /* we are using the cpu counter for timer interrupts */
1014 +       setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1015 +
1016 +       /* to generate the first timer interrupt */
1017 +       r4k_cur = (read_c0_count() + r4k_offset);
1018 +       write_c0_compare(r4k_cur);
1019 +
1020 +}
1021 +
1022 +asmlinkage void aruba_timer_interrupt(struct pt_regs *regs)
1023 +{
1024 +       int irq = MIPS_CPU_TIMER_IRQ;
1025 +
1026 +       irq_enter();
1027 +       kstat_this_cpu.irqs[irq]++;
1028 +
1029 +       timer_interrupt(irq, NULL);
1030 +       irq_exit();
1031 +}
1032 diff -Nur linux-2.6.17/arch/mips/Kconfig linux-2.6.17-owrt/arch/mips/Kconfig
1033 --- linux-2.6.17/arch/mips/Kconfig      2006-06-18 03:49:35.000000000 +0200
1034 +++ linux-2.6.17-owrt/arch/mips/Kconfig 2006-06-18 12:44:28.000000000 +0200
1035 @@ -227,6 +227,17 @@
1036           either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1037           a kernel for this platform.
1038
1039 +config MACH_ARUBA
1040 +       bool "Support for the ARUBA product line"
1041 +       select DMA_NONCOHERENT
1042 +       select CPU_HAS_PREFETCH
1043 +       select HW_HAS_PCI
1044 +       select SWAP_IO_SPACE
1045 +       select SYS_SUPPORTS_32BIT_KERNEL
1046 +       select SYS_HAS_CPU_MIPS32_R1
1047 +       select SYS_SUPPORTS_BIG_ENDIAN
1048 +
1049 +
1050  config MACH_JAZZ
1051         bool "Jazz family of machines"
1052         select ARC
1053 diff -Nur linux-2.6.17/arch/mips/Makefile linux-2.6.17-owrt/arch/mips/Makefile
1054 --- linux-2.6.17/arch/mips/Makefile     2006-06-18 03:49:35.000000000 +0200
1055 +++ linux-2.6.17-owrt/arch/mips/Makefile        2006-06-18 12:44:28.000000000 +0200
1056 @@ -145,6 +145,14 @@
1057  #
1058
1059  #
1060 +# Aruba
1061 +#
1062 +
1063 +core-$(CONFIG_MACH_ARUBA)      += arch/mips/aruba/
1064 +cflags-$(CONFIG_MACH_ARUBA)    += -Iinclude/asm-mips/aruba
1065 +load-$(CONFIG_MACH_ARUBA)      += 0x80100000
1066 +
1067 +#
1068  # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1069  #
1070  core-$(CONFIG_MACH_JAZZ)       += arch/mips/jazz/
1071 diff -Nur linux-2.6.17/drivers/net/Kconfig linux-2.6.17-owrt/drivers/net/Kconfig
1072 --- linux-2.6.17/drivers/net/Kconfig    2006-06-18 03:49:35.000000000 +0200
1073 +++ linux-2.6.17-owrt/drivers/net/Kconfig       2006-06-18 12:44:28.000000000 +0200
1074 @@ -187,6 +187,13 @@
1075
1076  source "drivers/net/arm/Kconfig"
1077
1078 +config IDT_RC32434_ETH
1079 +        tristate "IDT RC32434 Local Ethernet support"
1080 +        depends on NET_ETHERNET
1081 +        help
1082 +        IDT RC32434 has one local ethernet port. Say Y here to enable it.
1083 +        To compile this driver as a module, choose M here.
1084 +
1085  config MACE
1086         tristate "MACE (Power Mac ethernet) support"
1087         depends on NET_ETHERNET && PPC_PMAC && PPC32
1088 diff -Nur linux-2.6.17/drivers/net/Makefile linux-2.6.17-owrt/drivers/net/Makefile
1089 --- linux-2.6.17/drivers/net/Makefile   2006-06-18 03:49:35.000000000 +0200
1090 +++ linux-2.6.17-owrt/drivers/net/Makefile      2006-06-18 12:44:28.000000000 +0200
1091 @@ -38,6 +38,7 @@
1092
1093  obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
1094
1095 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1096  obj-$(CONFIG_DGRS) += dgrs.o
1097  obj-$(CONFIG_VORTEX) += 3c59x.o
1098  obj-$(CONFIG_TYPHOON) += typhoon.o
1099 diff -Nur linux-2.6.17/drivers/net/natsemi.c linux-2.6.17-owrt/drivers/net/natsemi.c
1100 --- linux-2.6.17/drivers/net/natsemi.c  2006-06-18 03:49:35.000000000 +0200
1101 +++ linux-2.6.17-owrt/drivers/net/natsemi.c     2006-06-18 12:44:28.000000000 +0200
1102 @@ -771,6 +771,49 @@
1103  static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
1104  static struct ethtool_ops ethtool_ops;
1105
1106 +#ifdef CONFIG_MACH_ARUBA
1107 +
1108 +#include <linux/ctype.h>
1109 +
1110 +#ifndef ERR
1111 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
1112 +#endif
1113 +
1114 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1115 +{
1116 +        int i, j;
1117 +        unsigned char result, value;
1118 +
1119 +        for (i=0; i<6; i++) {
1120 +                result = 0;
1121 +                if (i != 5 && *(macstr+2) != ':') {
1122 +                        ERR("invalid mac address format: %d %c\n",
1123 +                            i, *(macstr+2));
1124 +                        return -EINVAL;
1125 +                }
1126 +                for (j=0; j<2; j++) {
1127 +                        if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1128 +                                                  toupper(*macstr)-'A'+10) < 16) {
1129 +                                result = result*16 + value;
1130 +                                macstr++;
1131 +                        }
1132 +                        else {
1133 +                                ERR("invalid mac address "
1134 +                                    "character: %c\n", *macstr);
1135 +                                return -EINVAL;
1136 +                        }
1137 +                }
1138 +
1139 +                macstr++;
1140 +                dev->dev_addr[i] = result;
1141 +        }
1142 +
1143 +       dev->dev_addr[5]++;
1144 +        return 0;
1145 +}
1146 +
1147 +#endif
1148 +
1149  static inline void __iomem *ns_ioaddr(struct net_device *dev)
1150  {
1151         return (void __iomem *) dev->base_addr;
1152 @@ -871,6 +914,7 @@
1153                 goto err_ioremap;
1154         }
1155
1156 +#ifndef CONFIG_MACH_ARUBA
1157         /* Work around the dropped serial bit. */
1158         prev_eedata = eeprom_read(ioaddr, 6);
1159         for (i = 0; i < 3; i++) {
1160 @@ -879,6 +923,19 @@
1161                 dev->dev_addr[i*2+1] = eedata >> 7;
1162                 prev_eedata = eedata;
1163         }
1164 +#else
1165 +       {
1166 +               char mac[32];
1167 +               unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
1168 +               extern char *getenv(char *e);
1169 +               memset(mac, 0, 32);
1170 +               memcpy(mac, getenv("ethaddr"), 17);
1171 +               if (parse_mac_addr(dev, mac)){
1172 +                       printk("%s: MAC address not found\n", __func__);
1173 +                       memcpy(dev->dev_addr, def_mac, 6);
1174 +               }
1175 +       }
1176 +#endif
1177
1178         dev->base_addr = (unsigned long __force) ioaddr;
1179         dev->irq = irq;
1180 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.c linux-2.6.17-owrt/drivers/net/rc32434_eth.c
1181 --- linux-2.6.17/drivers/net/rc32434_eth.c      1970-01-01 01:00:00.000000000 +0100
1182 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.c 2006-06-18 12:44:28.000000000 +0200
1183 @@ -0,0 +1,1273 @@
1184 +/**************************************************************************
1185 + *
1186 + *  BRIEF MODULE DESCRIPTION
1187 + *     Driver for the IDT RC32434 on-chip ethernet controller.
1188 + *
1189 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
1190 + *
1191 + *  This program is free software; you can redistribute  it and/or modify it
1192 + *  under  the terms of  the GNU General  Public License as published by the
1193 + *  Free Software Foundation;  either version 2 of the  License, or (at your
1194 + *  option) any later version.
1195 + *
1196 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
1197 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
1198 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
1199 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
1200 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1201 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
1202 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1203 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
1204 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1205 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1206 + *
1207 + *  You should have received a copy of the  GNU General Public License along
1208 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
1209 + *  675 Mass Ave, Cambridge, MA 02139, USA.
1210 + *
1211 + *
1212 + **************************************************************************
1213 + * May 2004 rkt, neb
1214 + *
1215 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1216 + *
1217 + * Aug 2004 Sadik
1218 + *
1219 + * Added NAPI
1220 + *
1221 + **************************************************************************
1222 + */
1223 +
1224 +#include <linux/autoconf.h>
1225 +#include <linux/version.h>
1226 +#include <linux/module.h>
1227 +#include <linux/kernel.h>
1228 +#include <linux/moduleparam.h>
1229 +#include <linux/sched.h>
1230 +#include <linux/ctype.h>
1231 +#include <linux/types.h>
1232 +#include <linux/fcntl.h>
1233 +#include <linux/interrupt.h>
1234 +#include <linux/ptrace.h>
1235 +#include <linux/init.h>
1236 +#include <linux/ioport.h>
1237 +#include <linux/proc_fs.h>
1238 +#include <linux/in.h>
1239 +#include <linux/slab.h>
1240 +#include <linux/string.h>
1241 +#include <linux/delay.h>
1242 +#include <linux/netdevice.h>
1243 +#include <linux/etherdevice.h>
1244 +#include <linux/skbuff.h>
1245 +#include <linux/errno.h>
1246 +#include <asm/bootinfo.h>
1247 +#include <asm/system.h>
1248 +#include <asm/bitops.h>
1249 +#include <asm/pgtable.h>
1250 +#include <asm/segment.h>
1251 +#include <asm/io.h>
1252 +#include <asm/dma.h>
1253 +
1254 +#include "rc32434_eth.h"
1255 +
1256 +#define DRIVER_VERSION "(mar2904)"
1257 +
1258 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1259 +
1260 +
1261 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1262 +                                  ((dev)->dev_addr[1]))
1263 +#define STATION_ADDRESS_LOW(dev)  (((dev)->dev_addr[2] << 24) | \
1264 +                                  ((dev)->dev_addr[3] << 16) | \
1265 +                                  ((dev)->dev_addr[4] << 8)  | \
1266 +                                  ((dev)->dev_addr[5]))
1267 +
1268 +#define MII_CLOCK 1250000                              /* no more than 2.5MHz */
1269 +static char mac0[18] = "08:00:06:05:40:01";
1270 +
1271 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52)
1272 +module_param_string(mac0, mac0, 18, 0);
1273 +#else
1274 +MODULE_PARM(mac0, "c18");
1275 +#endif
1276 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1277 +
1278 +static struct rc32434_if_t {
1279 +       char *name;
1280 +       struct net_device *dev;
1281 +       char* mac_str;
1282 +       int weight;
1283 +       u32 iobase;
1284 +       u32 rxdmabase;
1285 +       u32 txdmabase;
1286 +       int rx_dma_irq;
1287 +       int tx_dma_irq;
1288 +       int rx_ovr_irq;
1289 +       int tx_und_irq;
1290 +} rc32434_iflist[] =
1291 +{
1292 +       {
1293 +               "rc32434_eth0",      NULL,       mac0,
1294 +               64,
1295 +               ETH0_PhysicalAddress,
1296 +               ETH0_RX_DMA_ADDR,
1297 +               ETH0_TX_DMA_ADDR,
1298 +               ETH0_DMA_RX_IRQ,
1299 +               ETH0_DMA_TX_IRQ,
1300 +               ETH0_RX_OVR_IRQ,
1301 +               ETH0_TX_UND_IRQ
1302 +       }
1303 +};
1304 +
1305 +
1306 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1307 +{
1308 +       int i, j;
1309 +       unsigned char result, value;
1310 +
1311 +       for (i=0; i<6; i++) {
1312 +               result = 0;
1313 +               if (i != 5 && *(macstr+2) != ':') {
1314 +                       ERR("invalid mac address format: %d %c\n",
1315 +                           i, *(macstr+2));
1316 +                       return -EINVAL;
1317 +               }
1318 +               for (j=0; j<2; j++) {
1319 +                       if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1320 +                                                 toupper(*macstr)-'A'+10) < 16) {
1321 +                               result = result*16 + value;
1322 +                               macstr++;
1323 +                       }
1324 +                       else {
1325 +                               ERR("invalid mac address "
1326 +                                   "character: %c\n", *macstr);
1327 +                               return -EINVAL;
1328 +                       }
1329 +               }
1330 +
1331 +               macstr++;
1332 +               dev->dev_addr[i] = result;
1333 +       }
1334 +
1335 +       return 0;
1336 +}
1337 +
1338 +
1339 +
1340 +static inline void rc32434_abort_tx(struct net_device *dev)
1341 +{
1342 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1343 +       rc32434_abort_dma(dev, lp->tx_dma_regs);
1344 +
1345 +}
1346 +
1347 +static inline void rc32434_abort_rx(struct net_device *dev)
1348 +{
1349 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1350 +       rc32434_abort_dma(dev, lp->rx_dma_regs);
1351 +
1352 +}
1353 +
1354 +static inline void rc32434_start_tx(struct rc32434_local *lp,  volatile DMAD_t td)
1355 +{
1356 +       rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1357 +}
1358 +
1359 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1360 +{
1361 +       rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1362 +}
1363 +
1364 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1365 +{
1366 +       rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1367 +}
1368 +
1369 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1370 +{
1371 +       rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1372 +}
1373 +
1374 +#ifdef RC32434_PROC_DEBUG
1375 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1376 +                            int length, int *eof, void *data)
1377 +{
1378 +       struct net_device *dev = (struct net_device *)data;
1379 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1380 +       int len = 0;
1381 +
1382 +       /* print out header */
1383 +       len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1384 +       len += sprintf (buf + len,
1385 +                       "DMA halt count      = %10d, DMA run count = %10d\n",
1386 +                       lp->dma_halt_cnt, lp->dma_run_cnt);
1387 +
1388 +       if (fpos >= len) {
1389 +               *start = buf;
1390 +               *eof = 1;
1391 +               return 0;
1392 +       }
1393 +       *start = buf + fpos;
1394 +
1395 +       if ((len -= fpos) > length)
1396 +               return length;
1397 +       *eof = 1;
1398 +
1399 +       return len;
1400 +
1401 +}
1402 +#endif
1403 +
1404 +
1405 +/*
1406 + * Restart the RC32434 ethernet controller.
1407 + */
1408 +static int rc32434_restart(struct net_device *dev)
1409 +{
1410 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1411 +
1412 +       /*
1413 +        * Disable interrupts
1414 +        */
1415 +       disable_irq(lp->rx_irq);
1416 +       disable_irq(lp->tx_irq);
1417 +#ifdef RC32434_REVISION
1418 +       disable_irq(lp->ovr_irq);
1419 +#endif
1420 +       disable_irq(lp->und_irq);
1421 +
1422 +       /* Mask F E bit in Tx DMA */
1423 +       rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1424 +       /* Mask D H E bit in Rx DMA */
1425 +       rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1426 +
1427 +       rc32434_init(dev);
1428 +       rc32434_multicast_list(dev);
1429 +
1430 +       enable_irq(lp->und_irq);
1431 +#ifdef RC32434_REVISION
1432 +       enable_irq(lp->ovr_irq);
1433 +#endif
1434 +       enable_irq(lp->tx_irq);
1435 +       enable_irq(lp->rx_irq);
1436 +
1437 +       return 0;
1438 +}
1439 +
1440 +int rc32434_init_module(void)
1441 +{
1442 +#ifdef CONFIG_MACH_ARUBA
1443 +       if (mips_machtype != MACH_ARUBA_AP70)
1444 +               return 1;
1445 +#endif
1446 +
1447 +       printk(KERN_INFO DRIVER_NAME " \n");
1448 +       return rc32434_probe(0);
1449 +}
1450 +
1451 +static int rc32434_probe(int port_num)
1452 +{
1453 +       struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1454 +       struct rc32434_local *lp = NULL;
1455 +       struct net_device *dev = NULL;
1456 +       int i, retval,err;
1457 +
1458 +       dev = alloc_etherdev(sizeof(struct rc32434_local));
1459 +       if(!dev) {
1460 +               ERR("rc32434_eth: alloc_etherdev failed\n");
1461 +               return -1;
1462 +       }
1463 +
1464 +       SET_MODULE_OWNER(dev);
1465 +       bif->dev = dev;
1466 +
1467 +#ifdef CONFIG_MACH_ARUBA
1468 +       {
1469 +               extern char * getenv(char *e);
1470 +               memcpy(bif->mac_str, getenv("ethaddr"), 17);
1471 +       }
1472 +#endif
1473 +
1474 +       printk("mac: %s\n", bif->mac_str);
1475 +       if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1476 +               ERR("MAC address parse failed\n");
1477 +               free_netdev(dev);
1478 +               return -1;
1479 +       }
1480 +
1481 +
1482 +       /* Initialize the device structure. */
1483 +       if (dev->priv == NULL) {
1484 +               lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1485 +               memset(lp, 0, sizeof(struct rc32434_local));
1486 +       }
1487 +       else {
1488 +               lp = (struct rc32434_local *)dev->priv;
1489 +       }
1490 +
1491 +       lp->rx_irq = bif->rx_dma_irq;
1492 +       lp->tx_irq = bif->tx_dma_irq;
1493 +       lp->ovr_irq = bif->rx_ovr_irq;
1494 +       lp->und_irq = bif->tx_und_irq;
1495 +
1496 +       lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1497 +
1498 +       if (!lp->eth_regs) {
1499 +               ERR("Can't remap eth registers\n");
1500 +               retval = -ENXIO;
1501 +               goto probe_err_out;
1502 +       }
1503 +
1504 +       lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1505 +
1506 +       if (!lp->rx_dma_regs) {
1507 +               ERR("Can't remap Rx DMA registers\n");
1508 +               retval = -ENXIO;
1509 +               goto probe_err_out;
1510 +       }
1511 +       lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1512 +
1513 +       if (!lp->tx_dma_regs) {
1514 +               ERR("Can't remap Tx DMA registers\n");
1515 +               retval = -ENXIO;
1516 +               goto probe_err_out;
1517 +       }
1518 +
1519 +#ifdef RC32434_PROC_DEBUG
1520 +       lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1521 +                                        rc32434_read_proc, dev);
1522 +#endif
1523 +
1524 +       lp->td_ring =   (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1525 +       if (!lp->td_ring) {
1526 +               ERR("Can't allocate descriptors\n");
1527 +               retval = -ENOMEM;
1528 +               goto probe_err_out;
1529 +       }
1530 +
1531 +       dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1532 +
1533 +       /* now convert TD_RING pointer to KSEG1 */
1534 +       lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1535 +       lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1536 +
1537 +
1538 +       spin_lock_init(&lp->lock);
1539 +
1540 +       dev->base_addr = bif->iobase;
1541 +       /* just use the rx dma irq */
1542 +       dev->irq = bif->rx_dma_irq;
1543 +
1544 +       dev->priv = lp;
1545 +
1546 +       dev->open = rc32434_open;
1547 +       dev->stop = rc32434_close;
1548 +       dev->hard_start_xmit = rc32434_send_packet;
1549 +       dev->get_stats  = rc32434_get_stats;
1550 +       dev->set_multicast_list = &rc32434_multicast_list;
1551 +       dev->tx_timeout = rc32434_tx_timeout;
1552 +       dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1553 +
1554 +#ifdef CONFIG_IDT_USE_NAPI
1555 +       dev->poll = rc32434_poll;
1556 +       dev->weight = bif->weight;
1557 +       printk("Using NAPI with weight %d\n",dev->weight);
1558 +#else
1559 +       lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1560 +       tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1561 +#endif
1562 +       lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1563 +       tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1564 +
1565 +       if ((err = register_netdev(dev))) {
1566 +               printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1567 +               free_netdev(dev);
1568 +               retval = -EINVAL;
1569 +               goto probe_err_out;
1570 +       }
1571 +
1572 +       INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1573 +       for (i = 0; i < 6; i++) {
1574 +               printk("%2.2x", dev->dev_addr[i]);
1575 +               if (i<5)
1576 +                       printk(":");
1577 +       }
1578 +       printk("\n");
1579 +
1580 +       return 0;
1581 +
1582 + probe_err_out:
1583 +       rc32434_cleanup_module();
1584 +       ERR(" failed.  Returns %d\n", retval);
1585 +       return retval;
1586 +
1587 +}
1588 +
1589 +
1590 +static void rc32434_cleanup_module(void)
1591 +{
1592 +       int i;
1593 +
1594 +       for (i = 0; rc32434_iflist[i].iobase; i++) {
1595 +               struct rc32434_if_t * bif = &rc32434_iflist[i];
1596 +               if (bif->dev != NULL) {
1597 +                       struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1598 +                       if (lp != NULL) {
1599 +                               if (lp->eth_regs)
1600 +                                       iounmap((void*)lp->eth_regs);
1601 +                               if (lp->rx_dma_regs)
1602 +                                       iounmap((void*)lp->rx_dma_regs);
1603 +                               if (lp->tx_dma_regs)
1604 +                                       iounmap((void*)lp->tx_dma_regs);
1605 +                               if (lp->td_ring)
1606 +                                       kfree((void*)KSEG0ADDR(lp->td_ring));
1607 +
1608 +#ifdef RC32434_PROC_DEBUG
1609 +                               if (lp->ps) {
1610 +                                       remove_proc_entry(bif->name, proc_net);
1611 +                               }
1612 +#endif
1613 +                               kfree(lp);
1614 +                       }
1615 +
1616 +                       unregister_netdev(bif->dev);
1617 +                       free_netdev(bif->dev);
1618 +                       kfree(bif->dev);
1619 +               }
1620 +       }
1621 +}
1622 +
1623 +
1624 +
1625 +static int rc32434_open(struct net_device *dev)
1626 +{
1627 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1628 +
1629 +       /* Initialize */
1630 +       if (rc32434_init(dev)) {
1631 +               ERR("Error: cannot open the Ethernet device\n");
1632 +               return -EAGAIN;
1633 +       }
1634 +
1635 +       /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1636 +       if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1637 +                 SA_SHIRQ | SA_INTERRUPT,
1638 +                       "rc32434 ethernet Rx", dev)) {
1639 +               ERR(": unable to get Rx DMA IRQ %d\n",
1640 +                   lp->rx_irq);
1641 +               return -EAGAIN;
1642 +       }
1643 +       if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1644 +                 SA_SHIRQ | SA_INTERRUPT,
1645 +                       "rc32434 ethernet Tx", dev)) {
1646 +               ERR(": unable to get Tx DMA IRQ %d\n",
1647 +                   lp->tx_irq);
1648 +               free_irq(lp->rx_irq, dev);
1649 +               return -EAGAIN;
1650 +       }
1651 +
1652 +#ifdef RC32434_REVISION
1653 +       /* Install handler for overrun error. */
1654 +       if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1655 +                       SA_SHIRQ | SA_INTERRUPT,
1656 +                       "Ethernet Overflow", dev)) {
1657 +               ERR(": unable to get OVR IRQ %d\n",
1658 +                   lp->ovr_irq);
1659 +               free_irq(lp->rx_irq, dev);
1660 +               free_irq(lp->tx_irq, dev);
1661 +               return -EAGAIN;
1662 +       }
1663 +#endif
1664 +
1665 +       /* Install handler for underflow error. */
1666 +       if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1667 +                       SA_SHIRQ | SA_INTERRUPT,
1668 +                       "Ethernet Underflow", dev)) {
1669 +               ERR(": unable to get UND IRQ %d\n",
1670 +                   lp->und_irq);
1671 +               free_irq(lp->rx_irq, dev);
1672 +               free_irq(lp->tx_irq, dev);
1673 +#ifdef RC32434_REVISION
1674 +               free_irq(lp->ovr_irq, dev);
1675 +#endif
1676 +               return -EAGAIN;
1677 +       }
1678 +
1679 +
1680 +       return 0;
1681 +}
1682 +
1683 +
1684 +
1685 +
1686 +static int rc32434_close(struct net_device *dev)
1687 +{
1688 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1689 +       u32 tmp;
1690 +
1691 +       /* Disable interrupts */
1692 +       disable_irq(lp->rx_irq);
1693 +       disable_irq(lp->tx_irq);
1694 +#ifdef RC32434_REVISION
1695 +       disable_irq(lp->ovr_irq);
1696 +#endif
1697 +       disable_irq(lp->und_irq);
1698 +
1699 +       tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1700 +       tmp = tmp | DMASM_f_m | DMASM_e_m;
1701 +       rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1702 +
1703 +       tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1704 +       tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1705 +       rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1706 +
1707 +       free_irq(lp->rx_irq, dev);
1708 +       free_irq(lp->tx_irq, dev);
1709 +#ifdef RC32434_REVISION
1710 +       free_irq(lp->ovr_irq, dev);
1711 +#endif
1712 +       free_irq(lp->und_irq, dev);
1713 +       return 0;
1714 +}
1715 +
1716 +
1717 +/* transmit packet */
1718 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1719 +{
1720 +       struct rc32434_local            *lp = (struct rc32434_local *)dev->priv;
1721 +       unsigned long                   flags;
1722 +       u32                                     length;
1723 +       DMAD_t                          td;
1724 +
1725 +
1726 +       spin_lock_irqsave(&lp->lock, flags);
1727 +
1728 +       td = &lp->td_ring[lp->tx_chain_tail];
1729 +
1730 +       /* stop queue when full, drop pkts if queue already full */
1731 +       if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1732 +               lp->tx_full = 1;
1733 +
1734 +               if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1735 +                       netif_stop_queue(dev);
1736 +               }
1737 +               else {
1738 +                       lp->stats.tx_dropped++;
1739 +                       dev_kfree_skb_any(skb);
1740 +                       spin_unlock_irqrestore(&lp->lock, flags);
1741 +                       return 1;
1742 +               }
1743 +       }
1744 +
1745 +       lp->tx_count ++;
1746 +
1747 +       lp->tx_skb[lp->tx_chain_tail] = skb;
1748 +
1749 +       length = skb->len;
1750 +
1751 +       /* Setup the transmit descriptor. */
1752 +       td->ca = CPHYSADDR(skb->data);
1753 +
1754 +       if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1755 +               if( lp->tx_chain_status == empty ) {
1756 +                       td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /*  Update tail      */
1757 +                       lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /*   Move tail       */
1758 +                       rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR    */
1759 +                       lp->tx_chain_head = lp->tx_chain_tail;                                                  /* Move head to tail */
1760 +               }
1761 +               else {
1762 +                       td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m;                                 /* Update tail */
1763 +                       lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &=  ~(DMAD_cof_m);          /* Link to prev */
1764 +                       lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link =  CPHYSADDR(td);              /* Link to prev */
1765 +                       lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
1766 +                       rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1767 +                       lp->tx_chain_head = lp->tx_chain_tail;                                                  /* Move head to tail */
1768 +                       lp->tx_chain_status = empty;
1769 +               }
1770 +       }
1771 +       else {
1772 +               if( lp->tx_chain_status == empty ) {
1773 +                       td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /* Update tail */
1774 +                       lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
1775 +                       lp->tx_chain_status = filled;
1776 +               }
1777 +               else {
1778 +                       td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /* Update tail */
1779 +                       lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &=  ~(DMAD_cof_m);          /* Link to prev */
1780 +                       lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link =  CPHYSADDR(td);              /* Link to prev */
1781 +                       lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
1782 +               }
1783 +       }
1784 +
1785 +       dev->trans_start = jiffies;
1786 +
1787 +       spin_unlock_irqrestore(&lp->lock, flags);
1788 +
1789 +       return 0;
1790 +}
1791 +
1792 +
1793 +/* Ethernet MII-PHY Handler */
1794 +static void rc32434_mii_handler(unsigned long data)
1795 +{
1796 +       struct net_device *dev = (struct net_device *)data;
1797 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1798 +       unsigned long   flags;
1799 +       unsigned long duplex_status;
1800 +       int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1801 +
1802 +       spin_lock_irqsave(&lp->lock, flags);
1803 +
1804 +       /* Two ports are using the same MII, the difference is the PHY address */
1805 +       rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1806 +       rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1807 +       rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1808 +       rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1809 +       while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1810 +
1811 +       ERR("irq:%x             port_addr:%x    RDD:%x\n",
1812 +           lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1813 +       duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1814 +       if(duplex_status != lp->duplex_mode) {
1815 +               ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1816 +               lp->duplex_mode = duplex_status;
1817 +               rc32434_restart(dev);
1818 +       }
1819 +
1820 +       lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1821 +       add_timer(&lp->mii_phy_timer);
1822 +
1823 +       spin_unlock_irqrestore(&lp->lock, flags);
1824 +
1825 +}
1826 +
1827 +#ifdef RC32434_REVISION
1828 +/* Ethernet Rx Overflow interrupt */
1829 +static irqreturn_t
1830 +rc32434_ovr_interrupt(int irq, void *dev_id)
1831 +{
1832 +       struct net_device *dev = (struct net_device *)dev_id;
1833 +       struct rc32434_local *lp;
1834 +       unsigned int ovr;
1835 +       irqreturn_t retval = IRQ_NONE;
1836 +
1837 +       ASSERT(dev != NULL);
1838 +
1839 +       lp = (struct rc32434_local *)dev->priv;
1840 +       spin_lock(&lp->lock);
1841 +       ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1842 +
1843 +       if(ovr & ETHINTFC_ovr_m) {
1844 +               netif_stop_queue(dev);
1845 +
1846 +               /* clear OVR bit */
1847 +               rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1848 +
1849 +               /* Restart interface */
1850 +               rc32434_restart(dev);
1851 +               retval = IRQ_HANDLED;
1852 +       }
1853 +       spin_unlock(&lp->lock);
1854 +
1855 +       return retval;
1856 +}
1857 +
1858 +#endif
1859 +
1860 +
1861 +/* Ethernet Tx Underflow interrupt */
1862 +static irqreturn_t
1863 +rc32434_und_interrupt(int irq, void *dev_id)
1864 +{
1865 +       struct net_device *dev = (struct net_device *)dev_id;
1866 +       struct rc32434_local *lp;
1867 +       unsigned int und;
1868 +       irqreturn_t retval = IRQ_NONE;
1869 +
1870 +       ASSERT(dev != NULL);
1871 +
1872 +       lp = (struct rc32434_local *)dev->priv;
1873 +
1874 +       spin_lock(&lp->lock);
1875 +
1876 +       und = rc32434_readl(&lp->eth_regs->ethintfc);
1877 +
1878 +       if(und & ETHINTFC_und_m) {
1879 +               netif_stop_queue(dev);
1880 +
1881 +               rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1882 +
1883 +               /* Restart interface */
1884 +               rc32434_restart(dev);
1885 +               retval = IRQ_HANDLED;
1886 +       }
1887 +
1888 +       spin_unlock(&lp->lock);
1889 +
1890 +       return retval;
1891 +}
1892 +
1893 +
1894 +/* Ethernet Rx DMA interrupt */
1895 +static irqreturn_t
1896 +rc32434_rx_dma_interrupt(int irq, void *dev_id)
1897 +{
1898 +       struct net_device *dev = (struct net_device *)dev_id;
1899 +       struct rc32434_local* lp;
1900 +       volatile u32 dmas,dmasm;
1901 +       irqreturn_t retval;
1902 +
1903 +       ASSERT(dev != NULL);
1904 +
1905 +       lp = (struct rc32434_local *)dev->priv;
1906 +
1907 +       spin_lock(&lp->lock);
1908 +       dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1909 +       if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1910 +               /* Mask D H E bit in Rx DMA */
1911 +               dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1912 +               rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1913 +#ifdef CONFIG_IDT_USE_NAPI
1914 +               if(netif_rx_schedule_prep(dev))
1915 +                        __netif_rx_schedule(dev);
1916 +#else
1917 +               tasklet_hi_schedule(lp->rx_tasklet);
1918 +#endif
1919 +
1920 +               if (dmas & DMAS_e_m)
1921 +                       ERR(": DMA error\n");
1922 +
1923 +               retval = IRQ_HANDLED;
1924 +       }
1925 +       else
1926 +               retval = IRQ_NONE;
1927 +
1928 +       spin_unlock(&lp->lock);
1929 +       return retval;
1930 +}
1931 +
1932 +#ifdef CONFIG_IDT_USE_NAPI
1933 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1934 +#else
1935 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1936 +#endif
1937 +{
1938 +       struct net_device *dev = (struct net_device *)rx_data_dev;
1939 +       struct rc32434_local* lp = netdev_priv(dev);
1940 +       volatile DMAD_t  rd = &lp->rd_ring[lp->rx_next_done];
1941 +       struct sk_buff *skb, *skb_new;
1942 +       u8* pkt_buf;
1943 +       u32 devcs, count, pkt_len, pktuncrc_len;
1944 +       volatile u32 dmas;
1945 +#ifdef CONFIG_IDT_USE_NAPI
1946 +       u32 received = 0;
1947 +       int rx_work_limit = min(*budget,dev->quota);
1948 +#else
1949 +       unsigned long   flags;
1950 +       spin_lock_irqsave(&lp->lock, flags);
1951 +#endif
1952 +
1953 +       while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1954 +#ifdef CONFIG_IDT_USE_NAPI
1955 +               if(--rx_work_limit <0)
1956 +                {
1957 +                        break;
1958 +                }
1959 +#endif
1960 +               /* init the var. used for the later operations within the while loop */
1961 +               skb_new = NULL;
1962 +               devcs = rd->devcs;
1963 +               pkt_len = RCVPKT_LENGTH(devcs);
1964 +               skb = lp->rx_skb[lp->rx_next_done];
1965 +
1966 +               if (count < 64) {
1967 +                       lp->stats.rx_errors++;
1968 +                       lp->stats.rx_dropped++;
1969 +               }
1970 +               else if ((devcs & ( ETHRX_ld_m)) !=     ETHRX_ld_m) {
1971 +                       /* check that this is a whole packet */
1972 +                       /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
1973 +                       lp->stats.rx_errors++;
1974 +                       lp->stats.rx_dropped++;
1975 +               }
1976 +               else if ( (devcs & ETHRX_rok_m)  ) {
1977 +
1978 +                       {
1979 +                               /* must be the (first and) last descriptor then */
1980 +                               pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
1981 +
1982 +                               pktuncrc_len = pkt_len - 4;
1983 +                               /* invalidate the cache */
1984 +                               dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
1985 +
1986 +                               /* Malloc up new buffer. */
1987 +                               skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
1988 +
1989 +                               if (skb_new != NULL){
1990 +                                       /* Make room */
1991 +                                       skb_put(skb, pktuncrc_len);
1992 +
1993 +                                       skb->protocol = eth_type_trans(skb, dev);
1994 +
1995 +                                       /* pass the packet to upper layers */
1996 +#ifdef CONFIG_IDT_USE_NAPI
1997 +                                       netif_receive_skb(skb);
1998 +#else
1999 +                                       netif_rx(skb);
2000 +#endif
2001 +
2002 +                                       dev->last_rx = jiffies;
2003 +                                       lp->stats.rx_packets++;
2004 +                                       lp->stats.rx_bytes += pktuncrc_len;
2005 +
2006 +                                       if (IS_RCV_MP(devcs))
2007 +                                               lp->stats.multicast++;
2008 +
2009 +                                       /* 16 bit align */
2010 +                                       skb_reserve(skb_new, 2);
2011 +
2012 +                                       skb_new->dev = dev;
2013 +                                       lp->rx_skb[lp->rx_next_done] = skb_new;
2014 +                               }
2015 +                               else {
2016 +                                       ERR("no memory, dropping rx packet.\n");
2017 +                                       lp->stats.rx_errors++;
2018 +                                       lp->stats.rx_dropped++;
2019 +                               }
2020 +                       }
2021 +
2022 +               }
2023 +               else {
2024 +                       /* This should only happen if we enable accepting broken packets */
2025 +                       lp->stats.rx_errors++;
2026 +                       lp->stats.rx_dropped++;
2027 +
2028 +                       /* add statistics counters */
2029 +                       if (IS_RCV_CRC_ERR(devcs)) {
2030 +                               DBG(2, "RX CRC error\n");
2031 +                               lp->stats.rx_crc_errors++;
2032 +                       }
2033 +                       else if (IS_RCV_LOR_ERR(devcs)) {
2034 +                               DBG(2, "RX LOR error\n");
2035 +                               lp->stats.rx_length_errors++;
2036 +                       }
2037 +                       else if (IS_RCV_LE_ERR(devcs)) {
2038 +                               DBG(2, "RX LE error\n");
2039 +                               lp->stats.rx_length_errors++;
2040 +                       }
2041 +                       else if (IS_RCV_OVR_ERR(devcs)) {
2042 +                               lp->stats.rx_over_errors++;
2043 +                       }
2044 +                       else if (IS_RCV_CV_ERR(devcs)) {
2045 +                               /* code violation */
2046 +                               DBG(2, "RX CV error\n");
2047 +                               lp->stats.rx_frame_errors++;
2048 +                       }
2049 +                       else if (IS_RCV_CES_ERR(devcs)) {
2050 +                               DBG(2, "RX Preamble error\n");
2051 +                       }
2052 +               }
2053 +
2054 +               rd->devcs = 0;
2055 +
2056 +               /* restore descriptor's curr_addr */
2057 +               if(skb_new)
2058 +                       rd->ca = CPHYSADDR(skb_new->data);
2059 +               else
2060 +                       rd->ca = CPHYSADDR(skb->data);
2061 +
2062 +               rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2063 +               lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &=  ~(DMAD_cod_m);
2064 +
2065 +               lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2066 +               rd = &lp->rd_ring[lp->rx_next_done];
2067 +               rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2068 +       }
2069 +#ifdef CONFIG_IDT_USE_NAPI
2070 +        dev->quota -= received;
2071 +        *budget =- received;
2072 +        if(rx_work_limit < 0)
2073 +                goto not_done;
2074 +#endif
2075 +
2076 +       dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2077 +
2078 +       if(dmas & DMAS_h_m) {
2079 +               rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2080 +#ifdef RC32434_PROC_DEBUG
2081 +               lp->dma_halt_cnt++;
2082 +#endif
2083 +               rd->devcs = 0;
2084 +               skb = lp->rx_skb[lp->rx_next_done];
2085 +               rd->ca = CPHYSADDR(skb->data);
2086 +               rc32434_chain_rx(lp,rd);
2087 +       }
2088 +
2089 +#ifdef CONFIG_IDT_USE_NAPI
2090 +       netif_rx_complete(dev);
2091 +#endif
2092 +       /* Enable D H E bit in Rx DMA */
2093 +       rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2094 +#ifdef CONFIG_IDT_USE_NAPI
2095 +       return 0;
2096 + not_done:
2097 +       return 1;
2098 +#else
2099 +       spin_unlock_irqrestore(&lp->lock, flags);
2100 +       return;
2101 +#endif
2102 +
2103 +
2104 +}
2105 +
2106 +
2107 +
2108 +/* Ethernet Tx DMA interrupt */
2109 +static irqreturn_t
2110 +rc32434_tx_dma_interrupt(int irq, void *dev_id)
2111 +{
2112 +       struct net_device *dev = (struct net_device *)dev_id;
2113 +       struct rc32434_local *lp;
2114 +       volatile u32 dmas,dmasm;
2115 +       irqreturn_t retval;
2116 +
2117 +       ASSERT(dev != NULL);
2118 +
2119 +       lp = (struct rc32434_local *)dev->priv;
2120 +
2121 +       spin_lock(&lp->lock);
2122 +
2123 +       dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2124 +
2125 +       if (dmas & (DMAS_f_m | DMAS_e_m)) {
2126 +               dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2127 +               /* Mask F E bit in Tx DMA */
2128 +               rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2129 +
2130 +               tasklet_hi_schedule(lp->tx_tasklet);
2131 +
2132 +               if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2133 +                       rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2134 +                       lp->tx_chain_status = empty;
2135 +                       lp->tx_chain_head = lp->tx_chain_tail;
2136 +                       dev->trans_start = jiffies;
2137 +               }
2138 +
2139 +               if (dmas & DMAS_e_m)
2140 +                       ERR(": DMA error\n");
2141 +
2142 +               retval = IRQ_HANDLED;
2143 +       }
2144 +       else
2145 +               retval = IRQ_NONE;
2146 +
2147 +       spin_unlock(&lp->lock);
2148 +
2149 +       return retval;
2150 +}
2151 +
2152 +
2153 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2154 +{
2155 +       struct net_device *dev = (struct net_device *)tx_data_dev;
2156 +       struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2157 +       volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2158 +       u32 devcs;
2159 +       unsigned long   flags;
2160 +       volatile u32 dmas;
2161 +
2162 +       spin_lock_irqsave(&lp->lock, flags);
2163 +
2164 +       /* process all desc that are done */
2165 +       while(IS_DMA_FINISHED(td->control)) {
2166 +               if(lp->tx_full == 1) {
2167 +                       netif_wake_queue(dev);
2168 +                       lp->tx_full = 0;
2169 +               }
2170 +
2171 +               devcs = lp->td_ring[lp->tx_next_done].devcs;
2172 +               if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2173 +                       lp->stats.tx_errors++;
2174 +                       lp->stats.tx_dropped++;
2175 +
2176 +                       /* should never happen */
2177 +                       DBG(1, __FUNCTION__ ": split tx ignored\n");
2178 +               }
2179 +               else if (IS_TX_TOK(devcs)) {
2180 +                       lp->stats.tx_packets++;
2181 +               }
2182 +               else {
2183 +                       lp->stats.tx_errors++;
2184 +                       lp->stats.tx_dropped++;
2185 +
2186 +                       /* underflow */
2187 +                       if (IS_TX_UND_ERR(devcs))
2188 +                               lp->stats.tx_fifo_errors++;
2189 +
2190 +                       /* oversized frame */
2191 +                       if (IS_TX_OF_ERR(devcs))
2192 +                               lp->stats.tx_aborted_errors++;
2193 +
2194 +                       /* excessive deferrals */
2195 +                       if (IS_TX_ED_ERR(devcs))
2196 +                               lp->stats.tx_carrier_errors++;
2197 +
2198 +                       /* collisions: medium busy */
2199 +                       if (IS_TX_EC_ERR(devcs))
2200 +                               lp->stats.collisions++;
2201 +
2202 +                       /* late collision */
2203 +                       if (IS_TX_LC_ERR(devcs))
2204 +                               lp->stats.tx_window_errors++;
2205 +
2206 +               }
2207 +
2208 +               /* We must always free the original skb */
2209 +               if (lp->tx_skb[lp->tx_next_done] != NULL) {
2210 +                       dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2211 +                       lp->tx_skb[lp->tx_next_done] = NULL;
2212 +               }
2213 +
2214 +               lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2215 +               lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2216 +               lp->td_ring[lp->tx_next_done].link = 0;
2217 +               lp->td_ring[lp->tx_next_done].ca = 0;
2218 +               lp->tx_count --;
2219 +
2220 +               /* go on to next transmission */
2221 +               lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2222 +               td = &lp->td_ring[lp->tx_next_done];
2223 +
2224 +       }
2225 +
2226 +       dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2227 +       rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2228 +
2229 +       /* Enable F E bit in Tx DMA */
2230 +       rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2231 +       spin_unlock_irqrestore(&lp->lock, flags);
2232 +
2233 +}
2234 +
2235 +
2236 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2237 +{
2238 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2239 +       return &lp->stats;
2240 +}
2241 +
2242 +
2243 +/*
2244 + * Set or clear the multicast filter for this adaptor.
2245 + */
2246 +static void rc32434_multicast_list(struct net_device *dev)
2247 +{
2248 +       /* listen to broadcasts always and to treat     */
2249 +       /*       IFF bits independantly */
2250 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2251 +       unsigned long flags;
2252 +       u32 recognise = ETHARC_ab_m;            /* always accept broadcasts */
2253 +
2254 +       if (dev->flags & IFF_PROMISC)                   /* set promiscuous mode */
2255 +               recognise |= ETHARC_pro_m;
2256 +
2257 +       if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2258 +               recognise |= ETHARC_am_m;               /* all multicast & bcast */
2259 +       else if (dev->mc_count > 0) {
2260 +               DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2261 +               recognise |= ETHARC_am_m;               /* for the time being */
2262 +       }
2263 +
2264 +       spin_lock_irqsave(&lp->lock, flags);
2265 +       rc32434_writel(recognise, &lp->eth_regs->etharc);
2266 +       spin_unlock_irqrestore(&lp->lock, flags);
2267 +}
2268 +
2269 +
2270 +static void rc32434_tx_timeout(struct net_device *dev)
2271 +{
2272 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2273 +       unsigned long flags;
2274 +
2275 +       spin_lock_irqsave(&lp->lock, flags);
2276 +       rc32434_restart(dev);
2277 +       spin_unlock_irqrestore(&lp->lock, flags);
2278 +
2279 +}
2280 +
2281 +
2282 +/*
2283 + * Initialize the RC32434 ethernet controller.
2284 + */
2285 +static int rc32434_init(struct net_device *dev)
2286 +{
2287 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2288 +       int i, j;
2289 +
2290 +       /* Disable DMA */
2291 +       rc32434_abort_tx(dev);
2292 +       rc32434_abort_rx(dev);
2293 +
2294 +       /* reset ethernet logic */
2295 +       rc32434_writel(0, &lp->eth_regs->ethintfc);
2296 +       while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2297 +               dev->trans_start = jiffies;
2298 +
2299 +       /* Enable Ethernet Interface */
2300 +       rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2301 +
2302 +#ifndef CONFIG_IDT_USE_NAPI
2303 +       tasklet_disable(lp->rx_tasklet);
2304 +#endif
2305 +       tasklet_disable(lp->tx_tasklet);
2306 +
2307 +       /* Initialize the transmit Descriptors */
2308 +       for (i = 0; i < RC32434_NUM_TDS; i++) {
2309 +               lp->td_ring[i].control = DMAD_iof_m;
2310 +               lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2311 +               lp->td_ring[i].ca = 0;
2312 +               lp->td_ring[i].link = 0;
2313 +               if (lp->tx_skb[i] != NULL) {
2314 +                       dev_kfree_skb_any(lp->tx_skb[i]);
2315 +                       lp->tx_skb[i] = NULL;
2316 +               }
2317 +       }
2318 +       lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =      lp->tx_full = lp->tx_count = 0;
2319 +       lp->    tx_chain_status = empty;
2320 +
2321 +       /*
2322 +        * Initialize the receive descriptors so that they
2323 +        * become a circular linked list, ie. let the last
2324 +        * descriptor point to the first again.
2325 +        */
2326 +       for (i=0; i<RC32434_NUM_RDS; i++) {
2327 +               struct sk_buff *skb = lp->rx_skb[i];
2328 +
2329 +               if (lp->rx_skb[i] == NULL) {
2330 +                       skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2331 +                       if (skb == NULL) {
2332 +                               ERR("No memory in the system\n");
2333 +                               for (j = 0; j < RC32434_NUM_RDS; j ++)
2334 +                                       if (lp->rx_skb[j] != NULL)
2335 +                                               dev_kfree_skb_any(lp->rx_skb[j]);
2336 +
2337 +                               return 1;
2338 +                       }
2339 +                       else {
2340 +                               skb->dev = dev;
2341 +                               skb_reserve(skb, 2);
2342 +                               lp->rx_skb[i] = skb;
2343 +                               lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2344 +
2345 +                       }
2346 +               }
2347 +               lp->rd_ring[i].control =        DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2348 +               lp->rd_ring[i].devcs = 0;
2349 +               lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2350 +               lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2351 +
2352 +       }
2353 +       /* loop back */
2354 +       lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2355 +       lp->rx_next_done   = 0;
2356 +
2357 +       lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2358 +       lp->rx_chain_head = 0;
2359 +       lp->rx_chain_tail = 0;
2360 +       lp->rx_chain_status = empty;
2361 +
2362 +       rc32434_writel(0, &lp->rx_dma_regs->dmas);
2363 +       /* Start Rx DMA */
2364 +       rc32434_start_rx(lp, &lp->rd_ring[0]);
2365 +
2366 +       /* Enable F E bit in Tx DMA */
2367 +       rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2368 +       /* Enable D H E bit in Rx DMA */
2369 +       rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2370 +
2371 +       /* Accept only packets destined for this Ethernet device address */
2372 +       rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2373 +
2374 +       /* Set all Ether station address registers to their initial values */
2375 +       rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2376 +       rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2377 +
2378 +       rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2379 +       rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2380 +
2381 +       rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2382 +       rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2383 +
2384 +       rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2385 +       rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2386 +
2387 +
2388 +       /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2389 +       rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2390 +       //ETHMAC2_flc_m         ETHMAC2_fd_m    lp->duplex_mode
2391 +
2392 +       /* Back to back inter-packet-gap */
2393 +       rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2394 +       /* Non - Back to back inter-packet-gap */
2395 +       rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2396 +
2397 +       /* Management Clock Prescaler Divisor */
2398 +       /* Clock independent setting */
2399 +       rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2400 +                      &lp->eth_regs->ethmcp);
2401 +
2402 +       /* don't transmit until fifo contains 48b */
2403 +       rc32434_writel(48, &lp->eth_regs->ethfifott);
2404 +
2405 +       rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2406 +
2407 +#ifndef CONFIG_IDT_USE_NAPI
2408 +       tasklet_enable(lp->rx_tasklet);
2409 +#endif
2410 +       tasklet_enable(lp->tx_tasklet);
2411 +
2412 +       netif_start_queue(dev);
2413 +
2414 +
2415 +       return 0;
2416 +
2417 +}
2418 +
2419 +
2420 +#ifndef MODULE
2421 +
2422 +static int __init rc32434_setup(char *options)
2423 +{
2424 +       /* no options yet */
2425 +       return 1;
2426 +}
2427 +
2428 +static int __init rc32434_setup_ethaddr0(char *options)
2429 +{
2430 +       memcpy(mac0, options, 17);
2431 +       mac0[17]= '\0';
2432 +       return 1;
2433 +}
2434 +
2435 +__setup("rc32434eth=", rc32434_setup);
2436 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2437 +
2438 +
2439 +#endif /* MODULE */
2440 +
2441 +module_init(rc32434_init_module);
2442 +module_exit(rc32434_cleanup_module);
2443 +
2444 +
2445 +
2446 +
2447 +
2448 +
2449 +
2450 +
2451 +
2452 +
2453 +
2454 +
2455 +
2456 +
2457 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.h linux-2.6.17-owrt/drivers/net/rc32434_eth.h
2458 --- linux-2.6.17/drivers/net/rc32434_eth.h      1970-01-01 01:00:00.000000000 +0100
2459 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.h 2006-06-18 12:44:28.000000000 +0200
2460 @@ -0,0 +1,187 @@
2461 +/**************************************************************************
2462 + *
2463 + *  BRIEF MODULE DESCRIPTION
2464 + *     Definitions for IDT RC32434 on-chip ethernet controller.
2465 + *
2466 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
2467 + *
2468 + *  This program is free software; you can redistribute  it and/or modify it
2469 + *  under  the terms of  the GNU General  Public License as published by the
2470 + *  Free Software Foundation;  either version 2 of the  License, or (at your
2471 + *  option) any later version.
2472 + *
2473 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
2474 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
2475 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
2476 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
2477 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2478 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
2479 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2480 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
2481 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2482 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2483 + *
2484 + *  You should have received a copy of the  GNU General Public License along
2485 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
2486 + *  675 Mass Ave, Cambridge, MA 02139, USA.
2487 + *
2488 + *
2489 + **************************************************************************
2490 + * May 2004 rkt, neb
2491 + *
2492 + * Initial Release
2493 + *
2494 + * Aug 2004
2495 + *
2496 + * Added NAPI
2497 + *
2498 + **************************************************************************
2499 + */
2500 +
2501 +
2502 +#include  <asm/idt-boards/rc32434/rc32434.h>
2503 +#include  <asm/idt-boards/rc32434/rc32434_dma_v.h>
2504 +#include  <asm/idt-boards/rc32434/rc32434_eth_v.h>
2505 +
2506 +#define RC32434_DEBUG  2
2507 +//#define RC32434_PROC_DEBUG
2508 +#undef RC32434_DEBUG
2509 +
2510 +#ifdef RC32434_DEBUG
2511 +
2512 +/* use 0 for production, 1 for verification, >2 for debug */
2513 +static int rc32434_debug = RC32434_DEBUG;
2514 +#define ASSERT(expr) \
2515 +       if(!(expr)) {   \
2516 +               printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2517 +               #expr,__FILE__,__FUNCTION__,__LINE__);          }
2518 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2519 +#else
2520 +#define ASSERT(expr) do {} while (0)
2521 +#define DBG(lvl, format, arg...) do {} while (0)
2522 +#endif
2523 +
2524 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2525 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2526 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2527 +
2528 +#define ETH0_DMA_RX_IRQ        GROUP1_IRQ_BASE + 0
2529 +#define ETH0_DMA_TX_IRQ        GROUP1_IRQ_BASE + 1
2530 +#define ETH0_RX_OVR_IRQ        GROUP3_IRQ_BASE + 9
2531 +#define ETH0_TX_UND_IRQ        GROUP3_IRQ_BASE + 10
2532 +
2533 +#define ETH0_RX_DMA_ADDR  (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2534 +#define ETH0_TX_DMA_ADDR  (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2535 +
2536 +/* the following must be powers of two */
2537 +#ifdef CONFIG_IDT_USE_NAPI
2538 +#define RC32434_NUM_RDS    64                  /* number of receive descriptors */
2539 +#define RC32434_NUM_TDS    64                  /* number of transmit descriptors */
2540 +#else
2541 +#define RC32434_NUM_RDS    128                 /* number of receive descriptors */
2542 +#define RC32434_NUM_TDS    128                 /* number of transmit descriptors */
2543 +#endif
2544 +
2545 +#define RC32434_RBSIZE     1536                /* size of one resource buffer = Ether MTU */
2546 +#define RC32434_RDS_MASK   (RC32434_NUM_RDS-1)
2547 +#define RC32434_TDS_MASK   (RC32434_NUM_TDS-1)
2548 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2549 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2550 +
2551 +#define RC32434_TX_TIMEOUT HZ * 100
2552 +
2553 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2554 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2555 +
2556 +enum status    { filled,       empty};
2557 +#define IS_DMA_FINISHED(X)   (((X) & (DMAD_f_m)) != 0)
2558 +#define IS_DMA_DONE(X)   (((X) & (DMAD_d_m)) != 0)
2559 +
2560 +
2561 +/* Information that need to be kept for each board. */
2562 +struct rc32434_local {
2563 +       ETH_t  eth_regs;
2564 +       DMA_Chan_t  rx_dma_regs;
2565 +       DMA_Chan_t  tx_dma_regs;
2566 +       volatile DMAD_t   td_ring;                      /* transmit descriptor ring */
2567 +       volatile DMAD_t   rd_ring;                      /* receive descriptor ring  */
2568 +
2569 +       struct sk_buff* tx_skb[RC32434_NUM_TDS];        /* skbuffs for pkt to trans */
2570 +       struct sk_buff* rx_skb[RC32434_NUM_RDS];        /* skbuffs for pkt to trans */
2571 +
2572 +#ifndef CONFIG_IDT_USE_NAPI
2573 +       struct tasklet_struct * rx_tasklet;
2574 +#endif
2575 +       struct tasklet_struct * tx_tasklet;
2576 +
2577 +       int     rx_next_done;
2578 +       int     rx_chain_head;
2579 +       int     rx_chain_tail;
2580 +       enum status     rx_chain_status;
2581 +
2582 +       int     tx_next_done;
2583 +       int     tx_chain_head;
2584 +       int     tx_chain_tail;
2585 +       enum status     tx_chain_status;
2586 +       int tx_count;
2587 +       int     tx_full;
2588 +
2589 +       struct timer_list    mii_phy_timer;
2590 +       unsigned long duplex_mode;
2591 +
2592 +       int     rx_irq;
2593 +       int    tx_irq;
2594 +       int    ovr_irq;
2595 +       int    und_irq;
2596 +
2597 +       struct net_device_stats stats;
2598 +       spinlock_t lock;
2599 +
2600 +       /* debug /proc entry */
2601 +       struct proc_dir_entry *ps;
2602 +       int dma_halt_cnt;  int dma_run_cnt;
2603 +};
2604 +
2605 +extern unsigned int idt_cpu_freq;
2606 +
2607 +/* Index to functions, as function prototypes. */
2608 +static int rc32434_open(struct net_device *dev);
2609 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2610 +static void rc32434_mii_handler(unsigned long data);
2611 +static irqreturn_t  rc32434_und_interrupt(int irq, void *dev_id);
2612 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id);
2613 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id);
2614 +#ifdef RC32434_REVISION
2615 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id);
2616 +#endif
2617 +static int  rc32434_close(struct net_device *dev);
2618 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2619 +static void rc32434_multicast_list(struct net_device *dev);
2620 +static int  rc32434_init(struct net_device *dev);
2621 +static void rc32434_tx_timeout(struct net_device *dev);
2622 +
2623 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2624 +#ifdef CONFIG_IDT_USE_NAPI
2625 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2626 +#else
2627 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2628 +#endif
2629 +static void rc32434_cleanup_module(void);
2630 +static int rc32434_probe(int port_num);
2631 +int rc32434_init_module(void);
2632 +
2633 +
2634 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2635 +{
2636 +       if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2637 +               rc32434_writel(0x10, &ch->dmac);
2638 +
2639 +               while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2640 +                       dev->trans_start = jiffies;
2641 +
2642 +               rc32434_writel(0, &ch->dmas);
2643 +       }
2644 +
2645 +       rc32434_writel(0, &ch->dmadptr);
2646 +       rc32434_writel(0, &ch->dmandptr);
2647 +}
2648 diff -Nur linux-2.6.17/include/asm-mips/bootinfo.h linux-2.6.17-owrt/include/asm-mips/bootinfo.h
2649 --- linux-2.6.17/include/asm-mips/bootinfo.h    2006-06-18 03:49:35.000000000 +0200
2650 +++ linux-2.6.17-owrt/include/asm-mips/bootinfo.h       2006-06-18 12:44:28.000000000 +0200
2651 @@ -218,6 +218,17 @@
2652  #define MACH_GROUP_TITAN       22      /* PMC-Sierra Titan             */
2653  #define  MACH_TITAN_YOSEMITE   1       /* PMC-Sierra Yosemite          */
2654
2655 +
2656 +/*
2657 + * Valid machtype for group ARUBA
2658 + */
2659 +#define MACH_GROUP_ARUBA       23
2660 +#define  MACH_ARUBA_UNKNOWN    0
2661 +#define  MACH_ARUBA_AP60       1
2662 +#define  MACH_ARUBA_AP65       2
2663 +#define  MACH_ARUBA_AP70       3
2664 +#define  MACH_ARUBA_AP40       4
2665 +
2666  #define CL_SIZE                        COMMAND_LINE_SIZE
2667
2668  const char *get_system_type(void);
2669 diff -Nur linux-2.6.17/include/asm-mips/cpu.h linux-2.6.17-owrt/include/asm-mips/cpu.h
2670 --- linux-2.6.17/include/asm-mips/cpu.h 2006-06-18 03:49:35.000000000 +0200
2671 +++ linux-2.6.17-owrt/include/asm-mips/cpu.h    2006-06-18 12:45:56.000000000 +0200
2672 @@ -54,6 +54,9 @@
2673  #define PRID_IMP_R14000                0x0f00
2674  #define PRID_IMP_R8000         0x1000
2675  #define PRID_IMP_PR4450                0x1200
2676 +#define PRID_IMP_RC32334       0x1800
2677 +#define PRID_IMP_RC32355       0x1900
2678 +#define PRID_IMP_RC32365       0x1900
2679  #define PRID_IMP_R4600         0x2000
2680  #define PRID_IMP_R4700         0x2100
2681  #define PRID_IMP_TX39          0x2200
2682 @@ -200,7 +203,8 @@
2683  #define CPU_SB1A               62
2684  #define CPU_74K                        63
2685  #define CPU_R14000             64
2686 -#define CPU_LAST               64
2687 +#define CPU_RC32300            65
2688 +#define CPU_LAST               65
2689
2690  /*
2691   * ISA Level encodings
2692 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2693 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h  1970-01-01 01:00:00.000000000 +0100
2694 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h     2006-06-18 12:44:28.000000000 +0200
2695 @@ -0,0 +1,142 @@
2696 +/**************************************************************************
2697 + *
2698 + *  BRIEF MODULE DESCRIPTION
2699 + *   RC32300 helper routines
2700 + *
2701 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
2702 + *
2703 + *  This program is free software; you can redistribute  it and/or modify it
2704 + *  under  the terms of  the GNU General  Public License as published by the
2705 + *  Free Software Foundation;  either version 2 of the  License, or (at your
2706 + *  option) any later version.
2707 + *
2708 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
2709 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
2710 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
2711 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
2712 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2713 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
2714 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2715 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
2716 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2717 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2718 + *
2719 + *  You should have received a copy of the  GNU General Public License along
2720 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
2721 + *  675 Mass Ave, Cambridge, MA 02139, USA.
2722 + *
2723 + *
2724 + **************************************************************************
2725 + * May 2004 P. Sadik.
2726 + *
2727 + * Initial Release
2728 + *
2729 + *
2730 + *
2731 + **************************************************************************
2732 + */
2733 +
2734 +#ifndef __IDT_RC32300_H__
2735 +#define __IDT_RC32300_H__
2736 +
2737 +#include <linux/delay.h>
2738 +#include <asm/io.h>
2739 +
2740 +
2741 +/* cpu pipeline flush */
2742 +static inline void rc32300_sync(void)
2743 +{
2744 +       __asm__ volatile ("sync");
2745 +}
2746 +
2747 +static inline void rc32300_sync_udelay(int us)
2748 +{
2749 +       __asm__ volatile ("sync");
2750 +       udelay(us);
2751 +}
2752 +
2753 +static inline void rc32300_sync_delay(int ms)
2754 +{
2755 +       __asm__ volatile ("sync");
2756 +       mdelay(ms);
2757 +}
2758 +
2759 +/*
2760 + * Macros to access internal RC32300 registers. No byte
2761 + * swapping should be done when accessing the internal
2762 + * registers.
2763 + */
2764 +
2765 +static inline u8 rc32300_readb(unsigned long pa)
2766 +{
2767 +       return *((volatile u8 *)KSEG1ADDR(pa));
2768 +}
2769 +static inline u16 rc32300_readw(unsigned long pa)
2770 +{
2771 +       return *((volatile u16 *)KSEG1ADDR(pa));
2772 +}
2773 +static inline u32 rc32300_readl(unsigned long pa)
2774 +{
2775 +       return *((volatile u32 *)KSEG1ADDR(pa));
2776 +}
2777 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2778 +{
2779 +       *((volatile u8 *)KSEG1ADDR(pa)) = val;
2780 +}
2781 +static inline void rc32300_writew(u16 val, unsigned long pa)
2782 +{
2783 +       *((volatile u16 *)KSEG1ADDR(pa)) = val;
2784 +}
2785 +static inline void rc32300_writel(u32 val, unsigned long pa)
2786 +{
2787 +       *((volatile u32 *)KSEG1ADDR(pa)) = val;
2788 +}
2789 +
2790 +
2791 +#define local_readb __raw_readb
2792 +#define local_readw __raw_readw
2793 +#define local_readl __raw_readl
2794 +
2795 +#define local_writeb __raw_writeb
2796 +#define local_writew __raw_writew
2797 +#define local_writel __raw_writel
2798 +
2799 +
2800 +/*
2801 + * C access to CLZ and CLO instructions
2802 + * (count leading zeroes/ones).
2803 + */
2804 +static inline int rc32300_clz(unsigned long val)
2805 +{
2806 +       int ret;
2807 +       __asm__ volatile (
2808 +               ".set\tnoreorder\n\t"
2809 +               ".set\tnoat\n\t"
2810 +               ".set\tmips32\n\t"
2811 +               "clz\t%0,%1\n\t"
2812 +               ".set\tmips0\n\t"
2813 +               ".set\tat\n\t"
2814 +               ".set\treorder"
2815 +               : "=r" (ret)
2816 +               : "r" (val));
2817 +
2818 +       return ret;
2819 +}
2820 +static inline int rc32300_clo(unsigned long val)
2821 +{
2822 +       int ret;
2823 +       __asm__ volatile (
2824 +                   ".set\tnoreorder\n\t"
2825 +                   ".set\tnoat\n\t"
2826 +                   ".set\tmips32\n\t"
2827 +                   "clo\t%0,%1\n\t"
2828 +                   ".set\tmips0\n\t"
2829 +                   ".set\tat\n\t"
2830 +                   ".set\treorder"
2831 +                   : "=r" (ret)
2832 +                   : "r" (val));
2833 +
2834 +       return ret;
2835 +}
2836 +
2837 +#endif  // __IDT_RC32300_H__
2838 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2839 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h  1970-01-01 01:00:00.000000000 +0100
2840 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h     2006-06-18 12:44:28.000000000 +0200
2841 @@ -0,0 +1,207 @@
2842 +/**************************************************************************
2843 + *
2844 + *  BRIEF MODULE DESCRIPTION
2845 + *   Definitions for IDT RC32334 CPU.
2846 + *
2847 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
2848 + *
2849 + *  This program is free software; you can redistribute  it and/or modify it
2850 + *  under  the terms of  the GNU General  Public License as published by the
2851 + *  Free Software Foundation;  either version 2 of the  License, or (at your
2852 + *  option) any later version.
2853 + *
2854 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
2855 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
2856 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
2857 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
2858 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2859 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
2860 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2861 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
2862 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2863 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2864 + *
2865 + *  You should have received a copy of the  GNU General Public License along
2866 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
2867 + *  675 Mass Ave, Cambridge, MA 02139, USA.
2868 + *
2869 + *
2870 + **************************************************************************
2871 + * May 2004 P. Sadik.
2872 + *
2873 + * Initial Release
2874 + *
2875 + *
2876 + *
2877 + **************************************************************************
2878 + */
2879 +
2880 +
2881 +#ifndef __IDT_RC32334_H__
2882 +#define __IDT_RC32334_H__
2883 +
2884 +#include <linux/delay.h>
2885 +#include <asm/io.h>
2886 +
2887 +/* Base address of internal registers */
2888 +#define RC32334_REG_BASE   0x18000000
2889 +
2890 +/* CPU and IP Bus Control */
2891 +#define CPU_PORT_WIDTH     0xffffe200 // virtual!
2892 +#define CPU_BTA            0xffffe204 // virtual!
2893 +#define CPU_BUSERR_ADDR    0xffffe208 // virtual!
2894 +#define CPU_IP_BTA         (RC32334_REG_BASE + 0x0000)
2895 +#define CPU_IP_ADDR_LATCH  (RC32334_REG_BASE + 0x0004)
2896 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2897 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2898 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2899 +#define CPU_IP_SYSID       (RC32334_REG_BASE + 0x0018)
2900 +
2901 +/* Memory Controller */
2902 +#define MEM_BASE_BANK0     (RC32334_REG_BASE + 0x0080)
2903 +#define MEM_MASK_BANK0     (RC32334_REG_BASE + 0x0084)
2904 +#define MEM_CNTL_BANK0     (RC32334_REG_BASE + 0x0200)
2905 +#define MEM_BASE_BANK1     (RC32334_REG_BASE + 0x0088)
2906 +#define MEM_MASK_BANK1     (RC32334_REG_BASE + 0x008c)
2907 +#define MEM_CNTL_BANK1     (RC32334_REG_BASE + 0x0204)
2908 +#define MEM_CNTL_BANK2     (RC32334_REG_BASE + 0x0208)
2909 +#define MEM_CNTL_BANK3     (RC32334_REG_BASE + 0x020c)
2910 +#define MEM_CNTL_BANK4     (RC32334_REG_BASE + 0x0210)
2911 +#define MEM_CNTL_BANK5     (RC32334_REG_BASE + 0x0214)
2912 +
2913 +/* PCI Controller */
2914 +#define PCI_INTR_PEND      (RC32334_REG_BASE + 0x05b0)
2915 +#define PCI_INTR_MASK      (RC32334_REG_BASE + 0x05b4)
2916 +#define PCI_INTR_CLEAR     (RC32334_REG_BASE + 0x05b8)
2917 +#define CPU2PCI_INTR_PEND  (RC32334_REG_BASE + 0x05c0)
2918 +#define CPU2PCI_INTR_MASK  (RC32334_REG_BASE + 0x05c4)
2919 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2920 +#define PCI2CPU_INTR_PEND  (RC32334_REG_BASE + 0x05d0)
2921 +#define PCI2CPU_INTR_MASK  (RC32334_REG_BASE + 0x05d4)
2922 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2923 +#define PCI_MEM1_BASE      (RC32334_REG_BASE + 0x20b0)
2924 +#define PCI_MEM2_BASE      (RC32334_REG_BASE + 0x20b8)
2925 +#define PCI_MEM3_BASE      (RC32334_REG_BASE + 0x20c0)
2926 +#define PCI_IO1_BASE       (RC32334_REG_BASE + 0x20c8)
2927 +#define PCI_ARBITRATION    (RC32334_REG_BASE + 0x20e0)
2928 +#define PCI_CPU_MEM1_BASE  (RC32334_REG_BASE + 0x20e8)
2929 +#define PCI_CPU_IO_BASE    (RC32334_REG_BASE + 0x2100)
2930 +#define PCI_CFG_CNTL      (RC32334_REG_BASE + 0x2cf8)
2931 +#define PCI_CFG_DATA      (RC32334_REG_BASE + 0x2cfc)
2932 +
2933 +/* Timers */
2934 +#define TIMER0_CNTL        (RC32334_REG_BASE + 0x0700)
2935 +#define TIMER0_COUNT       (RC32334_REG_BASE + 0x0704)
2936 +#define TIMER0_COMPARE     (RC32334_REG_BASE + 0x0708)
2937 +#define TIMER_REG_OFFSET   0x10
2938 +
2939 +/* Programmable I/O */
2940 +#define PIO_DATA0          (RC32334_REG_BASE + 0x0600)
2941 +#define PIO_DATA1          (RC32334_REG_BASE + 0x0610)
2942 +
2943 +/*
2944 + * DMA
2945 + *
2946 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2947 + *
2948 + * DMA0: 18001400
2949 + * DMA1: 18001440
2950 + * DMA2: 18001900
2951 + * DMA3: 18001940
2952 + * NB: dma number must be immediate value or variable.
2953 + *      It MUST NOT be a function since it would get called twice!
2954 + */
2955 +#define DMA_IO(n)       (((n)>1?0x500:0)+((n)&1?0x40:0))
2956 +
2957 +#define RC32300_IO_DMA(n)       (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2958 +#define RC32300_DMA_CONFREG(n)  RC32300_IO_DMA(n)
2959 +#define RC32300_DMA_BASEREG(n)  (RC32300_IO_DMA(n)+0x4)
2960 +
2961 +#define RC32300_DMA_CURRREG(n)  (RC32300_IO_DMA(n)+0x8)
2962 +#define RC32300_DMA_STATREG(n)  (RC32300_IO_DMA(n)+0x10)
2963 +#define RC32300_DMA_SRCREG(n)   (RC32300_IO_DMA(n)+0x14)
2964 +#define RC32300_DMA_DSTREG(n)   (RC32300_IO_DMA(n)+0x18)
2965 +#define RC32300_DMA_NEXTREG(n)  (RC32300_IO_DMA(n)+0x1c)
2966 +
2967 +#define RC32300_DMA_IRQ(n)  (GROUP7_IRQ_BASE+5*(n))
2968 +
2969 +/* Expansion Interrupt Controller */
2970 +#define IC_GROUP0_PEND     (RC32334_REG_BASE + 0x0500)
2971 +#define IC_GROUP0_MASK     (RC32334_REG_BASE + 0x0504)
2972 +#define IC_GROUP0_CLEAR    (RC32334_REG_BASE + 0x0508)
2973 +#define IC_GROUP_OFFSET    0x10
2974 +
2975 +#define NUM_INTR_GROUPS    15
2976 +/*
2977 + * The IRQ mapping is as follows:
2978 + *
2979 + *    IRQ         Mapped To
2980 + *    ---     -------------------
2981 + *     0      SW0  (IP0) SW0 intr
2982 + *     1      SW1  (IP1) SW1 intr
2983 + *     2      Int0 (IP2) board-specific
2984 + *     3      Int1 (IP3) board-specific
2985 + *     4      Int2 (IP4) board-specific
2986 + *     -      Int3 (IP5) not used, mapped to IRQ's 8 and up
2987 + *     6      Int4 (IP6) board-specific
2988 + *     7      Int5 (IP7) CP0 Timer
2989 + *
2990 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
2991 + * internally on the RC32334 is routed to the Expansion
2992 + * Interrupt Controller.
2993 + */
2994 +#define MIPS_CPU_TIMER_IRQ 7
2995 +
2996 +#define GROUP1_IRQ_BASE  8                       // bus error
2997 +#define GROUP2_IRQ_BASE  (GROUP1_IRQ_BASE + 1)   // PIO active low
2998 +#define GROUP3_IRQ_BASE  (GROUP2_IRQ_BASE + 12)  // PIO active high
2999 +#define GROUP4_IRQ_BASE  (GROUP3_IRQ_BASE + 8)   // Timer Rollovers
3000 +#define GROUP5_IRQ_BASE  (GROUP4_IRQ_BASE + 8)   // UART0
3001 +#define GROUP6_IRQ_BASE  (GROUP5_IRQ_BASE + 3)   // UART1
3002 +#define GROUP7_IRQ_BASE  (GROUP6_IRQ_BASE + 3)   // DMA Ch0
3003 +#define GROUP8_IRQ_BASE  (GROUP7_IRQ_BASE + 5)   // DMA Ch1
3004 +#define GROUP9_IRQ_BASE  (GROUP8_IRQ_BASE + 5)   // DMA Ch2
3005 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5)   // DMA Ch3
3006 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5)  // PCI Ctlr errors
3007 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4)  // PCI Satellite Mode
3008 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
3009 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4)  // SPI
3010 +
3011 +#define RC32334_NR_IRQS  (GROUP14_IRQ_BASE + 1)
3012 +
3013 +/* 16550 UARTs */
3014 +#ifdef __MIPSEB__
3015 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
3016 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
3017 +#else
3018 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
3019 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
3020 +#endif
3021 +
3022 +#define RC32300_UART0_IRQ  GROUP5_IRQ_BASE
3023 +#define RC32300_UART1_IRQ  GROUP6_IRQ_BASE
3024 +
3025 +#define IDT_CLOCK_MULT 2
3026 +
3027 +/* NVRAM */
3028 +#define NVRAM_BASE         0x12000000
3029 +#define NVRAM_ENVSIZE_OFF  4
3030 +#define NVRAM_ENVSTART_OFF 0x40
3031 +
3032 +/* LCD 4-digit display */
3033 +#define LCD_CLEAR          0x14000400
3034 +#define LCD_DIGIT0         0x1400000f
3035 +#define LCD_DIGIT1         0x14000008
3036 +#define LCD_DIGIT2         0x14000007
3037 +#define LCD_DIGIT3         0x14000003
3038 +
3039 +/* Interrupts routed on 79S334A board (see rc32334.h) */
3040 +#define RC32334_SCC8530_IRQ  2
3041 +#define RC32334_PCI_INTA_IRQ 3
3042 +#define RC32334_PCI_INTB_IRQ 4
3043 +#define RC32334_PCI_INTC_IRQ 6
3044 +#define RC32334_PCI_INTD_IRQ 7
3045 +
3046 +#define RAM_SIZE       (32*1024*1024)
3047 +
3048 +#endif // __IDT_RC32334_H__
3049 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3050 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h      1970-01-01 01:00:00.000000000 +0100
3051 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-06-18 12:44:28.000000000 +0200
3052 @@ -0,0 +1,206 @@
3053 +/**************************************************************************
3054 + *
3055 + *  BRIEF MODULE DESCRIPTION
3056 + *     DMA controller defines on IDT RC32355
3057 + *
3058 + *  Copyright 2004 IDT Inc.
3059 + *  Author: Integrated Device Technology Inc. rischelp@idt.com
3060 + *
3061 + *
3062 + *  This program is free software; you can redistribute  it and/or modify it
3063 + *  under  the terms of  the GNU General  Public License as published by the
3064 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3065 + *  option) any later version.
3066 + *
3067 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3068 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3069 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3070 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3071 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3072 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3073 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3074 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3075 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3076 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3077 + *
3078 + *  You should have received a copy of the  GNU General Public License along
3079 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3080 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3081 + *
3082 + *
3083 + *  May 2004 rkt
3084 + *  Initial Release
3085 + *
3086 + **************************************************************************
3087 + */
3088 +
3089 +#ifndef BANYAN_DMA_H
3090 +#define BANYAN_DMA_H
3091 +#include  <asm/idt-boards/rc32300/rc32300.h>
3092 +
3093 +/*
3094 + * An image of one RC32355 dma channel registers
3095 + */
3096 +typedef struct {
3097 +       u32 dmac;
3098 +       u32 dmas;
3099 +       u32 dmasm;
3100 +       u32 dmadptr;
3101 +       u32 dmandptr;
3102 +} rc32355_dma_ch_t;
3103 +
3104 +/*
3105 + * An image of all RC32355 dma channel registers
3106 + */
3107 +typedef struct {
3108 +       rc32355_dma_ch_t ch[16];
3109 +} rc32355_dma_regs_t;
3110 +
3111 +
3112 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3113 +
3114 +
3115 +/* DMAC register layout */
3116 +
3117 +#define DMAC_RUN       0x1     /* Halts processing when cleared        */
3118 +#define DMAC_DM                0x2     /* Done Mask, ignore DMA events         */
3119 +#define DMAC_MODE_MASK 0xC     /* DMA operating mode                   */
3120 +
3121 +#define DMAC_MODE_AUTO 0x0     /* DMA Auto Request Mode                */
3122 +#define DMAC_MODE_BURST        0x4     /* DMA Burst Request Mode               */
3123 +#define DMAC_MODE_TFER 0x8     /* DMA Transfer Request Mode            */
3124 +
3125 +/* DMAS and DMASM register layout */
3126 +
3127 +#define DMAS_F         0x01    /* Finished */
3128 +#define DMAS_D         0x02    /* Done */
3129 +#define DMAS_C         0x04    /* Chain */
3130 +#define DMAS_E         0x08    /* Error */
3131 +#define DMAS_H         0x10    /* Halt */
3132 +
3133 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3134 +#define DMA_HALT_TIMEOUT 500
3135 +
3136 +
3137 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3138 +{
3139 +       int timeout=1;
3140 +
3141 +       if (local_readl(&ch->dmac) & DMAC_RUN) {
3142 +               local_writel(0, &ch->dmac);
3143 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3144 +                       if (local_readl(&ch->dmas) & DMAS_H) {
3145 +                               local_writel(0, &ch->dmas);
3146 +                               break;
3147 +                       }
3148 +               }
3149 +       }
3150 +
3151 +       return timeout ? 0 : 1;
3152 +}
3153 +
3154 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3155 +{
3156 +       local_writel(0, &ch->dmandptr);
3157 +       local_writel(dma_addr, &ch->dmadptr);
3158 +}
3159 +
3160 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3161 +{
3162 +       local_writel(dma_addr, &ch->dmandptr);
3163 +}
3164 +
3165 +
3166 +/* The following can be used to describe DMA channels 0 to 15, and the */
3167 +/* sub device's needed to select them in the DMADESC_DS_MASK field     */
3168 +
3169 +#define DMA_CHAN_ATM01         0            /* ATM interface 0,1 chan  */
3170 +
3171 +#define DMA_CHAN_ATM0IN                0            /* ATM interface 0 input   */
3172 +#define DMA_DEV_ATM0IN         0            /* ATM interface 0 input   */
3173 +
3174 +#define DMA_CHAN_ATM1IN                0            /* ATM interface 1 input   */
3175 +#define DMA_DEV_ATM1IN         1            /* ATM interface 1 input   */
3176 +
3177 +#define DMA_CHAN_ATM0OUT       0            /* ATM interface 0 output  */
3178 +#define DMA_DEV_ATM0OUT                2            /* ATM interface 0 output  */
3179 +
3180 +#define DMA_CHAN_ATM1OUT       0            /* ATM interface 1 output  */
3181 +#define DMA_DEV_ATM1OUT                3            /* ATM interface 1 output  */
3182 +
3183 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3184 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1)  /* ATM VC cache entry      */
3185 +#define DMA_DEV_ATMVCC(entry)  0
3186 +
3187 +#define DMA_CHAN_MEMTOMEM      6            /* Memory to memory DMA    */
3188 +#define DMA_DEV_MEMTOMEM       1            /* Memory to memory DMA    */
3189 +
3190 +#define DMA_CHAN_ATMFMB0       7            /* ATM Frame Mode Buffer 0 */
3191 +#define DMA_DEV_ATMFMB0                1            /* ATM Frame Mode Buffer 0 */
3192 +
3193 +#define DMA_CHAN_ATMFMB1       8            /* ATM Frame Mode Buffer 1 */
3194 +#define DMA_DEV_ATMFMB1                1            /* ATM Frame Mode Buffer 1 */
3195 +
3196 +#define DMA_CHAN_ETHERIN       9            /* Ethernet input          */
3197 +#define DMA_DEV_ETHERIN                0            /* Ethernet input          */
3198 +
3199 +#define DMA_CHAN_ETHEROUT      10           /* Ethernet output         */
3200 +#define DMA_DEV_ETHEROUT       0            /* Ethernet output         */
3201 +
3202 +#define DMA_CHAN_TDMIN         11           /* TDM Bus input           */
3203 +#define DMA_DEV_TDMIN          0            /* TDM Bus input           */
3204 +
3205 +#define DMA_CHAN_TDMOUT                12           /* TDM Bus output          */
3206 +#define DMA_DEV_TDMOUT         0            /* TDM Bus output          */
3207 +
3208 +#define DMA_CHAN_USBIN         13           /* USB input               */
3209 +#define DMA_DEV_USBIN          0            /* USB input               */
3210 +
3211 +#define DMA_CHAN_USBOUT                14           /* USB output              */
3212 +#define DMA_DEV_USBOUT         0            /* USB output              */
3213 +
3214 +#define DMA_CHAN_EXTERN                15           /* External DMA            */
3215 +#define DMA_DEV_EXTERN         0            /* External DMA            */
3216 +
3217 +/*
3218 + * An RC32355 dma descriptor in system memory
3219 + */
3220 +typedef struct {
3221 +       u32 cmdstat;    /* control and status */
3222 +       u32 curr_addr;  /* current address of data */
3223 +       u32 devcs;      /* peripheral-specific control and status */
3224 +       u32 link;       /* link to next descriptor */
3225 +} rc32355_dma_desc_t;
3226 +
3227 +/* Values for the descriptor cmdstat word */
3228 +
3229 +#define DMADESC_F              0x80000000u  /* Finished bit            */
3230 +#define DMADESC_D              0x40000000u  /* Done bit                */
3231 +#define DMADESC_T              0x20000000u  /* Terminated bit          */
3232 +#define DMADESC_IOD            0x10000000u  /* Interrupt On Done       */
3233 +#define DMADESC_IOF            0x08000000u  /* Interrupt On Finished   */
3234 +#define DMADESC_COD            0x04000000u  /* Chain On Done           */
3235 +#define DMADESC_COF            0x02000000u  /* Chain On Finished       */
3236 +
3237 +#define DMADESC_DEVCMD_MASK    0x01C00000u  /* Device Command mask     */
3238 +#define DMADESC_DEVCMD_SHIFT   22           /* Device Command shift    */
3239 +
3240 +#define DMADESC_DS_MASK                0x00300000u  /* Device Select mask      */
3241 +#define DMADESC_DS_SHIFT       20           /* Device Select shift     */
3242 +
3243 +#define DMADESC_COUNT_MASK     0x0003FFFFu  /* Byte Count mask         */
3244 +#define DMADESC_COUNT_SHIFT    0            /* Byte Count shift        */
3245 +
3246 +#define IS_DMA_FINISHED(X)   ( ( (X) & DMADESC_F ) >> 31)   /* F Bit    */
3247 +#define IS_DMA_DONE(X)       ( ( (X) & DMADESC_D ) >> 30)   /* D Bit    */
3248 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29)   /* T Bit    */
3249 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3250 +
3251 +#define DMA_DEVCMD(devcmd) \
3252 +  (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3253 +#define DMA_DS(ds)         \
3254 +  (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3255 +#define DMA_COUNT(count)   \
3256 +  ((count) & DMADESC_COUNT_MASK)
3257 +
3258 +#endif /* RC32355_DMA_H */
3259 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3260 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h      1970-01-01 01:00:00.000000000 +0100
3261 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-06-18 12:44:28.000000000 +0200
3262 @@ -0,0 +1,442 @@
3263 +/**************************************************************************
3264 + *
3265 + *  BRIEF MODULE DESCRIPTION
3266 + *     Ethernet registers on IDT RC32355
3267 + *
3268 + *  Copyright 2004 IDT Inc.
3269 + *  Author: Integrated Device Technology Inc. rischelp@idt.com
3270 + *
3271 + *
3272 + *  This program is free software; you can redistribute  it and/or modify it
3273 + *  under  the terms of  the GNU General  Public License as published by the
3274 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3275 + *  option) any later version.
3276 + *
3277 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3278 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3279 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3280 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3281 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3282 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3283 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3284 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3285 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3286 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3287 + *
3288 + *  You should have received a copy of the  GNU General Public License along
3289 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3290 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3291 + *
3292 + *
3293 + *  May 2004 rkt
3294 + *  Initial Release
3295 + *
3296 + **************************************************************************
3297 + */
3298 +
3299 +
3300 +#ifndef RC32355_ETHER_H
3301 +#define RC32355_ETHER_H
3302 +
3303 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3304 +
3305 +/*
3306 + * A partial image of the RC32355 ethernet registers
3307 + */
3308 +typedef struct {
3309 +       u32 ethintfc;
3310 +       u32 ethfifott;
3311 +       u32 etharc;
3312 +       u32 ethhash0;
3313 +       u32 ethhash1;
3314 +       u32 ethfifost;
3315 +       u32 ethfifos;
3316 +       u32 ethodeops;
3317 +       u32 ethis;
3318 +       u32 ethos;
3319 +       u32 ethmcp;
3320 +       u32 _u1;
3321 +       u32 ethid;
3322 +       u32 _u2;
3323 +       u32 _u3;
3324 +       u32 _u4;
3325 +       u32 ethod;
3326 +       u32 _u5;
3327 +       u32 _u6;
3328 +       u32 _u7;
3329 +       u32 ethodeop;
3330 +       u32 _u8[43];
3331 +       u32 ethsal0;
3332 +       u32 ethsah0;
3333 +       u32 ethsal1;
3334 +       u32 ethsah1;
3335 +       u32 ethsal2;
3336 +       u32 ethsah2;
3337 +       u32 ethsal3;
3338 +       u32 ethsah3;
3339 +       u32 ethrbc;
3340 +       u32 ethrpc;
3341 +       u32 ethrupc;
3342 +       u32 ethrfc;
3343 +       u32 ethtbc;
3344 +       u32 ethgpf;
3345 +       u32 _u9[50];
3346 +       u32 ethmac1;
3347 +       u32 ethmac2;
3348 +       u32 ethipgt;
3349 +       u32 ethipgr;
3350 +       u32 ethclrt;
3351 +       u32 ethmaxf;
3352 +       u32 _u10;
3353 +       u32 ethmtest;
3354 +       u32 miimcfg;
3355 +       u32 miimcmd;
3356 +       u32 miimaddr;
3357 +       u32 miimwtd;
3358 +       u32 miimrdd;
3359 +       u32 miimind;
3360 +       u32 _u11;
3361 +       u32 _u12;
3362 +       u32 ethcfsa0;
3363 +       u32 ethcfsa1;
3364 +       u32 ethcfsa2;
3365 +} rc32355_eth_regs_t;
3366 +
3367 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3368 +
3369 +#define ETH_INTFC   (RC32355_ETH_BASE + 0x000) /* INTerFace Control  */
3370 +#define ETH_FIFOTT  (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold  */
3371 +#define ETH_ARC     (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl  */
3372 +#define ETH_HASH0   (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3373 +#define ETH_HASH1   (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3374 +#define ETH_FIFOST  (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3375 +#define ETH_FIFOS   (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3376 +#define ETH_ODEOPS  (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3377 +#define ETH_IS      (RC32355_ETH_BASE + 0x020) /* Input Status */
3378 +#define ETH_OS      (RC32355_ETH_BASE + 0x024) /* Output Status  */
3379 +#define ETH_MCP     (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3380 +#define ETH_ID      (RC32355_ETH_BASE + 0x030) /* Input Data register */
3381 +#define ETH_OD      (RC32355_ETH_BASE + 0x040) /* Output Data register */
3382 +#define ETH_ODEOP   (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3383 +
3384 +/* for n in { 0, 1, 2, 3 } */
3385 +#define ETH_SAL(n)  (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3386 +#define ETH_SAH(n)  (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3387 +
3388 +#define ETH_RBC     (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3389 +#define ETH_RPC     (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3390 +#define ETH_RUPC    (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3391 +#define ETH_RFC     (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3392 +#define ETH_TBC     (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3393 +#define ETH_GPF     (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3394 +#define ETH_MAC1    (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3395 +#define ETH_MAC2    (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3396 +#define ETH_IPGT    (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3397 +#define ETH_IPGR    (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3398 +#define ETH_CLRT    (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3399 +#define ETH_MAXF    (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3400 +#define ETH_MTEST   (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3401 +
3402 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3403 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command  */
3404 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3405 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3406 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3407 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3408 +
3409 +/* for n in { 0, 1, 2 } */
3410 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4))  /* Station Addr */
3411 +
3412 +
3413 +/*
3414 + * Register Interpretations follow
3415 + */
3416 +
3417 +/******************************************************************************
3418 + * ETHINTFC register
3419 + *****************************************************************************/
3420 +
3421 +#define ETHERINTFC_EN            (1<<0)
3422 +#define ETHERINTFC_ITS           (1<<1)
3423 +#define ETHERINTFC_RES           (1<<2)
3424 +#define ETHERINTFC_RIP           (1<<2)
3425 +#define ETHERINTFC_JAM           (1<<3)
3426 +
3427 +/******************************************************************************
3428 + * ETHFIFOTT register
3429 + *****************************************************************************/
3430 +
3431 +#define ETHERFIFOTT_TTH(v)      (((v)&0x3f)<<0)
3432 +
3433 +/******************************************************************************
3434 + * ETHARC register
3435 + *****************************************************************************/
3436 +
3437 +#define ETHERARC_PRO             (1<<0)
3438 +#define ETHERARC_AM              (1<<1)
3439 +#define ETHERARC_AFM             (1<<2)
3440 +#define ETHERARC_AB              (1<<3)
3441 +
3442 +/******************************************************************************
3443 + * ETHHASH registers
3444 + *****************************************************************************/
3445 +
3446 +#define ETHERHASH0(v)            (((v)&0xffff)<<0)
3447 +#define ETHERHASH1(v)            (((v)&0xffff)<<0)
3448 +
3449 +/******************************************************************************
3450 + * ETHSA registers
3451 + *****************************************************************************/
3452 +
3453 +#define ETHERSAL0(v)             (((v)&0xffff)<<0)
3454 +#define ETHERSAL1(v)             (((v)&0xffff)<<0)
3455 +#define ETHERSAL2(v)             (((v)&0xffff)<<0)
3456 +#define ETHERSAL3(v)             (((v)&0xffff)<<0)
3457 +#define ETHERSAH0(v)             (((v)&0xff)<<0)
3458 +#define ETHERSAH1(v)             (((v)&0xff)<<0)
3459 +#define ETHERSAH2(v)             (((v)&0xff)<<0)
3460 +#define ETHERSAH3(v)             (((v)&0xff)<<0)
3461 +
3462 +/******************************************************************************
3463 + * ETHFIFOST register
3464 + *****************************************************************************/
3465 +
3466 +#define ETHERFIFOST_IRTH(v)      (((v)&0x3f)<<0)
3467 +#define ETHERFIFOST_ORTH(v)      (((v)&0x3f)<<16)
3468 +
3469 +/******************************************************************************
3470 + * ETHFIFOS register
3471 + *****************************************************************************/
3472 +
3473 +#define ETHERFIFOS_IR            (1<<0)
3474 +#define ETHERFIFOS_OR            (1<<1)
3475 +#define ETHERFIFOS_OVR           (1<<2)
3476 +#define ETHERFIFOS_UND           (1<<3)
3477 +
3478 +/******************************************************************************
3479 + * DATA registers
3480 + *****************************************************************************/
3481 +
3482 +#define ETHERID(v)               (((v)&0xffff)<<0)
3483 +#define ETHEROD(v)               (((v)&0xffff)<<0)
3484 +
3485 +/******************************************************************************
3486 + * ETHODEOPS register
3487 + *****************************************************************************/
3488 +
3489 +#define ETHERODEOPS_SIZE(v)      (((v)&0x3)<<0)
3490 +
3491 +/******************************************************************************
3492 + * ETHODEOP register
3493 + *****************************************************************************/
3494 +
3495 +#define ETHERODEOP(v)            (((v)&0xffff)<<0)
3496 +
3497 +/******************************************************************************
3498 + * ETHIS register
3499 + *****************************************************************************/
3500 +
3501 +#define ETHERIS_EOP              (1<<0)
3502 +#define ETHERIS_ROK              (1<<2)
3503 +#define ETHERIS_FM               (1<<3)
3504 +#define ETHERIS_MP               (1<<4)
3505 +#define ETHERIS_BP               (1<<5)
3506 +#define ETHERIS_VLT              (1<<6)
3507 +#define ETHERIS_CF               (1<<7)
3508 +#define ETHERIS_OVR              (1<<8)
3509 +#define ETHERIS_CRC              (1<<9)
3510 +#define ETHERIS_CV               (1<<10)
3511 +#define ETHERIS_DB               (1<<11)
3512 +#define ETHERIS_LE               (1<<12)
3513 +#define ETHERIS_LOR              (1<<13)
3514 +#define ETHERIS_SIZE(v)          (((v)&0x3)<<14)
3515 +#define ETHERIS_LENGTH(v)        (((v)&0xff)<<16)
3516 +
3517 +/******************************************************************************
3518 + * ETHOS register
3519 + *****************************************************************************/
3520 +
3521 +#define ETHEROS_T                (1<<0)
3522 +#define ETHEROS_TOK              (1<<6)
3523 +#define ETHEROS_MP               (1<<7)
3524 +#define ETHEROS_BP               (1<<8)
3525 +#define ETHEROS_UND              (1<<9)
3526 +#define ETHEROS_OF               (1<<10)
3527 +#define ETHEROS_ED               (1<<11)
3528 +#define ETHEROS_EC               (1<<12)
3529 +#define ETHEROS_LC               (1<<13)
3530 +#define ETHEROS_TD               (1<<14)
3531 +#define ETHEROS_CRC              (1<<15)
3532 +#define ETHEROS_LE               (1<<16)
3533 +#define ETHEROS_CC(v)            (((v)&0xf)<<17)
3534 +#define ETHEROS_PFD              (1<<21)
3535 +
3536 +/******************************************************************************
3537 + * Statistics registers
3538 + *****************************************************************************/
3539 +
3540 +#define ETHERRBC(v)              (((v)&0xffff)<<0)
3541 +#define ETHERRPC(v)              (((v)&0xffff)<<0)
3542 +#define ETHERRUPC(v)             (((v)&0xffff)<<0)
3543 +#define ETHERRFC(v)              (((v)&0xffff)<<0)
3544 +#define ETHERTBC(v)              (((v)&0xffff)<<0)
3545 +
3546 +/******************************************************************************
3547 + * ETHGPF register
3548 + *****************************************************************************/
3549 +
3550 +#define ETHERGPF_PTV(v)          (((v)&0xff)<<0)
3551 +
3552 +/******************************************************************************
3553 + * MAC registers
3554 + *****************************************************************************/
3555 +//ETHMAC1
3556 +#define ETHERMAC1_RE             (1<<0)
3557 +#define ETHERMAC1_PAF            (1<<1)
3558 +#define ETHERMAC1_RFC            (1<<2)
3559 +#define ETHERMAC1_TFC            (1<<3)
3560 +#define ETHERMAC1_LB             (1<<4)
3561 +#define ETHERMAC1_MR             (1<<15)
3562 +
3563 +//ETHMAC2
3564 +#define ETHERMAC2_FD             (1<<0)
3565 +#define ETHERMAC2_FLC            (1<<1)
3566 +#define ETHERMAC2_HFE            (1<<2)
3567 +#define ETHERMAC2_DC             (1<<3)
3568 +#define ETHERMAC2_CEN            (1<<4)
3569 +#define ETHERMAC2_PE             (1<<5)
3570 +#define ETHERMAC2_VPE            (1<<6)
3571 +#define ETHERMAC2_APE            (1<<7)
3572 +#define ETHERMAC2_PPE            (1<<8)
3573 +#define ETHERMAC2_LPE            (1<<9)
3574 +#define ETHERMAC2_NB             (1<<12)
3575 +#define ETHERMAC2_BP             (1<<13)
3576 +#define ETHERMAC2_ED             (1<<14)
3577 +
3578 +//ETHIPGT
3579 +#define ETHERIPGT(v)             (((v)&0x3f)<<0)
3580 +
3581 +//ETHIPGR
3582 +#define ETHERIPGR_IPGR1(v)       (((v)&0x3f)<<0)
3583 +#define ETHERIPGR_IPGR2(v)       (((v)&0x3f)<<8)
3584 +
3585 +//ETHCLRT
3586 +#define ETHERCLRT_MAXRET(v)      (((v)&0x3f)<<0)
3587 +#define ETHERCLRT_COLWIN(v)      (((v)&0x3f)<<8)
3588 +
3589 +//ETHMAXF
3590 +#define ETHERMAXF(v)             (((v)&0x3f)<<0)
3591 +
3592 +//ETHMTEST
3593 +#define ETHERMTEST_TB            (1<<2)
3594 +
3595 +//ETHMCP
3596 +#define ETHERMCP_DIV(v)          (((v)&0xff)<<0)
3597 +
3598 +//MIIMCFG
3599 +#define ETHERMIIMCFG_CS(v)          (((v)&0x3)<<2)
3600 +#define ETHERMIIMCFG_R              (1<<15)
3601 +
3602 +//MIIMCMD
3603 +#define ETHERMIIMCMD_RD             (1<<0)
3604 +#define ETHERMIIMCMD_SCN            (1<<1)
3605 +
3606 +//MIIMADDR
3607 +#define ETHERMIIMADDR_REGADDR(v)    (((v)&0x1f)<<0)
3608 +#define ETHERMIIMADDR_PHYADDR(v)    (((v)&0x1f)<<8)
3609 +
3610 +//MIIMWTD
3611 +#define ETHERMIIMWTD(v)             (((v)&0xff)<<0)
3612 +
3613 +//MIIMRDD
3614 +#define ETHERMIIMRDD(v)             (((v)&0xff)<<0)
3615 +
3616 +//MIIMIND
3617 +#define ETHERMIIMIND_BSY            (1<<0)
3618 +#define ETHERMIIMIND_SCN            (1<<1)
3619 +#define ETHERMIIMIND_NV             (1<<2)
3620 +
3621 +//DMA DEVCS IN
3622 +#define ETHERDMA_IN_LENGTH(v)  (((v)&0xffff)<<16)
3623 +#define ETHERDMA_IN_CES                (1<<14)
3624 +#define ETHERDMA_IN_LOR                (1<<13)
3625 +#define ETHERDMA_IN_LE         (1<<12)
3626 +#define ETHERDMA_IN_DB         (1<<11)
3627 +#define ETHERDMA_IN_CV         (1<<10)
3628 +#define ETHERDMA_IN_CRC                (1<<9)
3629 +#define ETHERDMA_IN_OVR                (1<<8)
3630 +#define ETHERDMA_IN_CF         (1<<7)
3631 +#define ETHERDMA_IN_VLT                (1<<6)
3632 +#define ETHERDMA_IN_BP         (1<<5)
3633 +#define ETHERDMA_IN_MP         (1<<4)
3634 +#define ETHERDMA_IN_FM         (1<<3)
3635 +#define ETHERDMA_IN_ROK                (1<<2)
3636 +#define ETHERDMA_IN_LD         (1<<1)
3637 +#define ETHERDMA_IN_FD         (1<<0)
3638 +
3639 +//DMA DEVCS OUT
3640 +#define ETHERDMA_OUT_CC(v)     (((v)&0xf)<<17)
3641 +#define ETHERDMA_OUT_CNT         0x001e0000
3642 +#define ETHERDMA_OUT_SHFT       17
3643 +#define ETHERDMA_OUT_LE                (1<<16)
3644 +
3645 +#define ETHERDMA_OUT_CRC       (1<<15)
3646 +#define ETHERDMA_OUT_TD                (1<<14)
3647 +#define ETHERDMA_OUT_LC                (1<<13)
3648 +#define ETHERDMA_OUT_EC                (1<<12)
3649 +#define ETHERDMA_OUT_ED                (1<<11)
3650 +#define ETHERDMA_OUT_OF                (1<<10)
3651 +#define ETHERDMA_OUT_UND       (1<<9)
3652 +#define ETHERDMA_OUT_BP                (1<<8)
3653 +#define ETHERDMA_OUT_MP                (1<<7)
3654 +#define ETHERDMA_OUT_TOK       (1<<6)
3655 +#define ETHERDMA_OUT_HEN       (1<<5)
3656 +#define ETHERDMA_OUT_CEN       (1<<4)
3657 +#define ETHERDMA_OUT_PEN       (1<<3)
3658 +#define ETHERDMA_OUT_OEN       (1<<2)
3659 +#define ETHERDMA_OUT_LD                (1<<1)
3660 +#define ETHERDMA_OUT_FD                (1<<0)
3661 +
3662 +#define RCV_ERRS \
3663 +  (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
3664 +#define TX_ERRS  \
3665 +  (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
3666 +   ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
3667 +
3668 +#define IS_RCV_ROK(X)        (((X) & (1<<2)) >> 2)       /* Receive Okay     */
3669 +#define IS_RCV_FM(X)         (((X) & (1<<3)) >> 3)       /* Is Filter Match  */
3670 +#define IS_RCV_MP(X)         (((X) & (1<<4)) >> 4)       /* Is it MP         */
3671 +#define IS_RCV_BP(X)         (((X) & (1<<5)) >> 5)       /* Is it BP         */
3672 +#define IS_RCV_VLT(X)        (((X) & (1<<6)) >> 6)       /* VLAN Tag Detect  */
3673 +#define IS_RCV_CF(X)         (((X) & (1<<7)) >> 7)       /* Control Frame    */
3674 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<8)) >> 8)       /* Receive Overflow */
3675 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<9)) >> 9)       /* CRC Error        */
3676 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<10))>>10)       /* Code Violation   */
3677 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<11))>>11)       /* Dribble Bits     */
3678 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<12))>>12)       /* Length error     */
3679 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<13))>>13)       /* Length Out of
3680 +                                                            Range            */
3681 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<14))>>14)       /* Preamble error   */
3682 +#define RCVPKT_LENGTH(X)     (((X) & 0xFFFF0000)>>16)    /* Length of the
3683 +                                                            received packet  */
3684 +
3685 +#define IS_TX_TOK(X)         (((X) & (1<<6) ) >> 6 )     /* Transmit Okay    */
3686 +#define IS_TX_MP(X)          (((X) & (1<<7) ) >> 7 )     /* Multicast        */
3687 +
3688 +#define IS_TX_BP(X)          (((X) & (1<<8) ) >> 8 )     /* Broadcast        */
3689 +#define IS_TX_UND_ERR(X)     (((X) & (1<<9) ) >> 9 )     /* Transmit FIFO
3690 +                                                            Underflow        */
3691 +#define IS_TX_OF_ERR(X)      (((X) & (1<<10)) >>10 )     /* Oversized frame  */
3692 +#define IS_TX_ED_ERR(X)      (((X) & (1<<11)) >>11 )     /* Excessive
3693 +                                                           deferral        */
3694 +#define IS_TX_EC_ERR(X)      (((X) & (1<<12)) >>12 )     /* Excessive
3695 +                                                           collisions      */
3696 +#define IS_TX_LC_ERR(X)      (((X) & (1<<13)) >>13 )     /* Late Collision   */
3697 +#define IS_TX_TD_ERR(X)      (((X) & (1<<14)) >>14 )     /* Transmit deferred*/
3698 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<15)) >>15 )     /* CRC Error        */
3699 +#define IS_TX_LE_ERR(X)      (((X) & (1<<16)) >>16 )     /* Length Error     */
3700 +
3701 +#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17)  /* Collision Count  */
3702 +
3703 +#endif /* RC32355_ETHER_H */
3704 +
3705 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h
3706 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355.h  1970-01-01 01:00:00.000000000 +0100
3707 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h     2006-06-18 12:44:28.000000000 +0200
3708 @@ -0,0 +1,177 @@
3709 +/**************************************************************************
3710 + *
3711 + *  BRIEF MODULE DESCRIPTION
3712 + *     Definitions for IDT RC32355 CPU.
3713 + *
3714 + *  Copyright 2004 IDT Inc.
3715 + *  Author: Integrated Device Technology Inc. rischelp@idt.com
3716 + *
3717 + *
3718 + *  This program is free software; you can redistribute  it and/or modify it
3719 + *  under  the terms of  the GNU General  Public License as published by the
3720 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3721 + *  option) any later version.
3722 + *
3723 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3724 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3725 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3726 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3727 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3728 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3729 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3730 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3731 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3732 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3733 + *
3734 + *  You should have received a copy of the  GNU General Public License along
3735 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3736 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3737 + *
3738 + *
3739 + *  May 2004 rkt
3740 + *  Initial Release
3741 + *
3742 + **************************************************************************
3743 + */
3744 +
3745 +
3746 +#ifndef _RC32355_H_
3747 +#define _RC32355_H_
3748 +
3749 +#include <linux/delay.h>
3750 +#include <asm/io.h>
3751 +
3752 +/* Base address of internal registers */
3753 +#define RC32355_REG_BASE   0x18000000
3754 +
3755 +/* System ID Registers */
3756 +#define CPU_SYSID          (RC32355_REG_BASE + 0x00018)
3757 +#define CPU_BTADDR         (RC32355_REG_BASE + 0x0001c)
3758 +#define CPU_REV            (RC32355_REG_BASE + 0x0002c)
3759 +
3760 +/* Reset Controller */
3761 +#define RESET_CNTL         (RC32355_REG_BASE + 0x08000)
3762 +
3763 +/* Device Controller */
3764 +#define DEV0_BASE          (RC32355_REG_BASE + 0x10000)
3765 +#define DEV0_MASK          (RC32355_REG_BASE + 0x10004)
3766 +#define DEV0_CNTL          (RC32355_REG_BASE + 0x10008)
3767 +#define DEV0_TIMING        (RC32355_REG_BASE + 0x1000c)
3768 +#define DEV_REG_OFFSET     0x10
3769 +
3770 +/* SDRAM Controller */
3771 +#define SDRAM0_BASE        (RC32355_REG_BASE + 0x18000)
3772 +#define SDRAM0_MASK        (RC32355_REG_BASE + 0x18004)
3773 +#define SDRAM1_BASE        (RC32355_REG_BASE + 0x18008)
3774 +#define SDRAM1_MASK        (RC32355_REG_BASE + 0x1800c)
3775 +#define SDRAM_CNTL         (RC32355_REG_BASE + 0x18010)
3776 +
3777 +/* Bus Arbiter */
3778 +#define BUS_ARB_CNTL0      (RC32355_REG_BASE + 0x20000)
3779 +#define BUS_ARB_CNTL1      (RC32355_REG_BASE + 0x20004)
3780 +
3781 +/* Counters/Timers */
3782 +#define TIMER0_COUNT       (RC32355_REG_BASE + 0x28000)
3783 +#define TIMER0_COMPARE     (RC32355_REG_BASE + 0x28004)
3784 +#define TIMER0_CNTL        (RC32355_REG_BASE + 0x28008)
3785 +#define TIMER_REG_OFFSET   0x0C
3786 +
3787 +/* System Integrity */
3788 +
3789 +/* Interrupt Controller */
3790 +#define IC_GROUP0_PEND     (RC32355_REG_BASE + 0x30000)
3791 +#define IC_GROUP0_MASK     (RC32355_REG_BASE + 0x30004)
3792 +#define IC_GROUP_OFFSET    0x08
3793 +
3794 +#define NUM_INTR_GROUPS    5
3795 +/*
3796 + * The IRQ mapping is as follows:
3797 + *
3798 + *    IRQ         Mapped To
3799 + *    ---     -------------------
3800 + *     0      SW0  (IP0) SW0 intr
3801 + *     1      SW1  (IP1) SW1 intr
3802 + *     -      Int0 (IP2) mapped to GROUP0_IRQ_BASE
3803 + *     -      Int1 (IP3) mapped to GROUP1_IRQ_BASE
3804 + *     -      Int2 (IP4) mapped to GROUP2_IRQ_BASE
3805 + *     -      Int3 (IP5) mapped to GROUP3_IRQ_BASE
3806 + *     -      Int4 (IP6) mapped to GROUP4_IRQ_BASE
3807 + *     7      Int5 (IP7) CP0 Timer
3808 + *
3809 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
3810 + * internally on the RC32355 is routed to the Expansion
3811 + * Interrupt Controller.
3812 + */
3813 +#define MIPS_CPU_TIMER_IRQ 7
3814 +
3815 +#define GROUP0_IRQ_BASE  8                      // Counter/Timers, UCW
3816 +#define GROUP1_IRQ_BASE  (GROUP0_IRQ_BASE + 32) // DMA
3817 +#define GROUP2_IRQ_BASE  (GROUP1_IRQ_BASE + 32) // ATM
3818 +#define GROUP3_IRQ_BASE  (GROUP2_IRQ_BASE + 32) // TDM, Eth, USB, UARTs, I2C
3819 +#define GROUP4_IRQ_BASE  (GROUP3_IRQ_BASE + 32) // GPIO
3820 +
3821 +#define RC32355_NR_IRQS  (GROUP4_IRQ_BASE + 32)
3822 +
3823 +/* DMA - see rc32355_dma.h for full list of registers */
3824 +
3825 +#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
3826 +#define DMA_CHAN_OFFSET  0x14
3827 +
3828 +/* GPIO Controller */
3829 +
3830 +/* TDM Bus */
3831 +
3832 +/* 16550 UARTs */
3833 +#ifdef __MIPSEB__
3834 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
3835 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
3836 +#else
3837 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
3838 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
3839 +#endif
3840 +
3841 +#define RC32300_UART0_IRQ  (GROUP3_IRQ_BASE + 14)
3842 +#define RC32300_UART1_IRQ  (GROUP3_IRQ_BASE + 17)
3843 +
3844 +/* ATM */
3845 +
3846 +/* Ethernet - see rc32355_eth.h for full list of registers */
3847 +
3848 +#define RC32355_ETH_BASE   (RC32355_REG_BASE + 0x60000)
3849 +
3850 +
3851 +#define IDT_CLOCK_MULT 2
3852 +
3853 +/* Memory map of 79EB355 board */
3854 +
3855 +/* DRAM */
3856 +#define RAM_BASE        0x00000000
3857 +#define RAM_SIZE       (32*1024*1024)
3858 +
3859 +/* SRAM (device 1) */
3860 +#define SRAM_BASE       0x02000000
3861 +#define SRAM_SIZE       0x00100000
3862 +
3863 +/* FLASH (device 2) */
3864 +#define FLASH_BASE      0x0C000000
3865 +#define FLASH_SIZE      0x00C00000
3866 +
3867 +/* ATM PHY (device 4) */
3868 +#define ATM_PHY_BASE    0x14000000
3869 +
3870 +/* TDM switch (device 3) */
3871 +#define TDM_BASE        0x1A000000
3872 +
3873 +/* LCD panel (device 3) */
3874 +#define LCD_BASE        0x1A002000
3875 +
3876 +/* RTC (DS1511W) (device 3) */
3877 +#define RTC_BASE        0x1A004000
3878 +
3879 +/* NVRAM (256 bytes internal to the DS1511 RTC) */
3880 +#define NVRAM_ADDR      RTC_BASE + 0x10
3881 +#define NVRAM_DATA      RTC_BASE + 0x13
3882 +#define NVRAM_ENVSIZE_OFF  4
3883 +#define NVRAM_ENVSTART_OFF 32
3884 +
3885 +#endif /* _RC32355_H_ */
3886 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h
3887 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma.h      1970-01-01 01:00:00.000000000 +0100
3888 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 2006-06-18 12:44:28.000000000 +0200
3889 @@ -0,0 +1,226 @@
3890 +/**************************************************************************
3891 + *
3892 + *  BRIEF MODULE DESCRIPTION
3893 + *   RC32365/336 DMA hardware abstraction.
3894 + *
3895 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
3896 + *
3897 + *  This program is free software; you can redistribute  it and/or modify it
3898 + *  under  the terms of  the GNU General  Public License as published by the
3899 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3900 + *  option) any later version.
3901 + *
3902 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3903 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3904 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3905 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3906 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3907 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3908 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3909 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3910 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3911 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3912 + *
3913 + *  You should have received a copy of the  GNU General Public License along
3914 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3915 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3916 + *
3917 + *
3918 + **************************************************************************
3919 + * May 2004 P. Sadik.
3920 + *
3921 + * Initial Release
3922 + *
3923 + *
3924 + *
3925 + **************************************************************************
3926 + */
3927 +
3928 +#ifndef __IDT_RC32365_DMA_H__
3929 +#define __IDT_RC32365_DMA_H__
3930 +
3931 +enum
3932 +{
3933 +       DMA0_PhysicalAddress    = 0x18038000,
3934 +       DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
3935 +
3936 +       DMA0_VirtualAddress     = 0xb8038000,
3937 +       DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
3938 +} ;
3939 +
3940 +/*
3941 + * DMA descriptor (in physical memory).
3942 + */
3943 +
3944 +typedef struct DMAD_s
3945 +{
3946 +       u32                     control ;       // Control. use DMAD_*
3947 +       u32                     ca ;            // Current Address.
3948 +       u32                     devcs ;         // Device control and status.
3949 +       u32                     link ;          // Next descriptor in chain.
3950 +} volatile *DMAD_t ;
3951 +
3952 +enum
3953 +{
3954 +       DMAD_size               = sizeof (struct DMAD_s),
3955 +       DMAD_count_b            = 0,            // in DMAD_t -> control
3956 +       DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
3957 +       DMAD_ds_b               = 20,           // in DMAD_t -> control
3958 +       DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
3959 +       DMAD_ds_extToMem0_v     = 0,
3960 +       DMAD_ds_memToExt0_v     = 1,
3961 +       DMAD_ds_extToMem1_v     = 0,
3962 +       DMAD_ds_memToExt1_v     = 1,
3963 +       DMAD_ds_ethRcv0_v       = 0,
3964 +       DMAD_ds_ethXmt0_v       = 0,
3965 +       DMAD_ds_ethRcv1_v       = 0,
3966 +       DMAD_ds_ethXmt2_v       = 0,
3967 +       DMAD_ds_memToFifo_v     = 0,
3968 +       DMAD_ds_fifoToMem_v     = 0,
3969 +       DMAD_ds_rng_de_v           = 1,//randomNumberGenerator on LC/DE
3970 +       DMAD_ds_pciToMem_v      = 0,
3971 +       DMAD_ds_memToPci_v      = 0,
3972 +       DMAD_ds_securityInput_v = 0,
3973 +       DMAD_ds_securityOutput_v = 0,
3974 +       DMAD_ds_rng_se_v        = 0,//randomNumberGenerator on SE
3975 +
3976 +       DMAD_devcmd_b           = 22,           // in DMAD_t -> control
3977 +       DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
3978 +       DMAD_devcmd_byte_v      = 0,    //memory-to-memory
3979 +       DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
3980 +       DMAD_devcmd_word_v      = 2,    //memory-to-memory
3981 +       DMAD_devcmd_2words_v    = 3,    //memory-to-memory
3982 +       DMAD_devcmd_4words_v    = 4,    //memory-to-memory
3983 +       DMAD_devcmd_6words_v    = 5,    //memory-to-memory
3984 +       DMAD_devcmd_8words_v    = 6,    //memory-to-memory
3985 +       DMAD_devcmd_16words_v   = 7,    //memory-to-memory
3986 +       DMAD_cof_b              = 25,           // chain on finished
3987 +       DMAD_cof_m              = 0x02000000,   //
3988 +       DMAD_cod_b              = 26,           // chain on done
3989 +       DMAD_cod_m              = 0x04000000,   //
3990 +       DMAD_iof_b              = 27,           // interrupt on finished
3991 +       DMAD_iof_m              = 0x08000000,   //
3992 +       DMAD_iod_b              = 28,           // interrupt on done
3993 +       DMAD_iod_m              = 0x10000000,   //
3994 +       DMAD_t_b                = 29,           // terminated
3995 +       DMAD_t_m                = 0x20000000,   //
3996 +       DMAD_d_b                = 30,           // done
3997 +       DMAD_d_m                = 0x40000000,   //
3998 +       DMAD_f_b                = 31,           // finished
3999 +       DMAD_f_m                = 0x80000000,   //
4000 +} ;
4001 +
4002 +/*
4003 + * DMA register (within Internal Register Map).
4004 + */
4005 +
4006 +struct DMA_Chan_s
4007 +{
4008 +       u32             dmac ;          // Control.
4009 +       u32             dmas ;          // Status.
4010 +       u32             dmasm ;         // Mask.
4011 +       u32             dmadptr ;       // Descriptor pointer.
4012 +       u32             dmandptr ;      // Next descriptor pointer.
4013 +};
4014 +
4015 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
4016 +
4017 +//DMA_Channels   use DMACH_count instead
4018 +
4019 +enum
4020 +{
4021 +       DMAC_run_b      = 0,            //
4022 +       DMAC_run_m      = 0x00000001,   //
4023 +       DMAC_dm_b       = 1,            // done mask
4024 +       DMAC_dm_m       = 0x00000002,   //
4025 +       DMAC_mode_b     = 2,            //
4026 +       DMAC_mode_m     = 0x0000000c,   //
4027 +       DMAC_mode_auto_v        = 0,
4028 +       DMAC_mode_burst_v       = 1,
4029 +       DMAC_mode_transfer_v    = 2, //usually used
4030 +       DMAC_mode_reserved_v    = 3,
4031 +       DMAC_a_b        = 4,            //
4032 +       DMAC_a_m        = 0x00000010,   //
4033 +
4034 +       DMAS_f_b        = 0,            // finished (sticky)
4035 +       DMAS_f_m        = 0x00000001,   //
4036 +       DMAS_d_b        = 1,            // done (sticky)
4037 +       DMAS_d_m        = 0x00000002,   //
4038 +       DMAS_c_b        = 2,            // chain (sticky)
4039 +       DMAS_c_m        = 0x00000004,   //
4040 +       DMAS_e_b        = 3,            // error (sticky)
4041 +       DMAS_e_m        = 0x00000008,   //
4042 +       DMAS_h_b        = 4,            // halt (sticky)
4043 +       DMAS_h_m        = 0x00000010,   //
4044 +
4045 +       DMASM_f_b       = 0,            // finished (1=mask)
4046 +       DMASM_f_m       = 0x00000001,   //
4047 +       DMASM_d_b       = 1,            // done (1=mask)
4048 +       DMASM_d_m       = 0x00000002,   //
4049 +       DMASM_c_b       = 2,            // chain (1=mask)
4050 +       DMASM_c_m       = 0x00000004,   //
4051 +       DMASM_e_b       = 3,            // error (1=mask)
4052 +       DMASM_e_m       = 0x00000008,   //
4053 +       DMASM_h_b       = 4,            // halt (1=mask)
4054 +       DMASM_h_m       = 0x00000010,   //
4055 +} ;
4056 +
4057 +/*
4058 + * DMA channel definitions
4059 + */
4060 +
4061 +enum
4062 +{
4063 +       DMACH_ethRcv0 = 0,
4064 +       DMACH_ethXmt0 = 1,
4065 +       DMACH_ethRcv1 = 2,
4066 +       DMACH_ethXmt2 = 3,
4067 +       DMACH_pciToMem = 4,
4068 +       DMACH_memToPci = 5,
4069 +       DMACH_securityInput = 6,
4070 +       DMACH_securityOutput = 7,
4071 +       DMACH_rng = 8,
4072 +
4073 +       DMACH_count //must be last
4074 +};
4075 +
4076 +
4077 +typedef struct DMAC_s
4078 +{
4079 +       struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
4080 +} volatile *DMA_t ;
4081 +
4082 +
4083 +/*
4084 + * External DMA parameters
4085 +*/
4086 +
4087 +enum
4088 +{
4089 +       DMADEVCMD_ts_b  = 0,            // ts field in devcmd
4090 +       DMADEVCMD_ts_m  = 0x00000007,   // ts field in devcmd
4091 +       DMADEVCMD_ts_byte_v     = 0,
4092 +       DMADEVCMD_ts_halfword_v = 1,
4093 +       DMADEVCMD_ts_word_v     = 2,
4094 +       DMADEVCMD_ts_2word_v    = 3,
4095 +       DMADEVCMD_ts_4word_v    = 4,
4096 +       DMADEVCMD_ts_6word_v    = 5,
4097 +       DMADEVCMD_ts_8word_v    = 6,
4098 +       DMADEVCMD_ts_16word_v   = 7
4099 +};
4100 +
4101 +
4102 +#if 1  // aws - Compatibility.
4103 +#      define  EXTDMA_ts_b             DMADEVCMD_ts_b
4104 +#      define  EXTDMA_ts_m             DMADEVCMD_ts_m
4105 +#      define  EXTDMA_ts_byte_v        DMADEVCMD_ts_byte_v
4106 +#      define  EXTDMA_ts_halfword_v    DMADEVCMD_ts_halfword_v
4107 +#      define  EXTDMA_ts_word_v        DMADEVCMD_ts_word_v
4108 +#      define  EXTDMA_ts_2word_v       DMADEVCMD_ts_2word_v
4109 +#      define  EXTDMA_ts_4word_v       DMADEVCMD_ts_4word_v
4110 +#      define  EXTDMA_ts_6word_v       DMADEVCMD_ts_6word_v
4111 +#      define  EXTDMA_ts_8word_v       DMADEVCMD_ts_8word_v
4112 +#      define  EXTDMA_ts_16word_v      DMADEVCMD_ts_16word_v
4113 +#endif // aws - Compatibility.
4114 +
4115 +#endif // __IDT_RC32365_DMA_H__
4116 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h
4117 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h    1970-01-01 01:00:00.000000000 +0100
4118 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h       2006-06-18 12:44:28.000000000 +0200
4119 @@ -0,0 +1,86 @@
4120 +/**************************************************************************
4121 + *
4122 + *  BRIEF MODULE DESCRIPTION
4123 + *   RC32365/336 DMA interface routines.
4124 + *
4125 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4126 + *
4127 + *  This program is free software; you can redistribute  it and/or modify it
4128 + *  under  the terms of  the GNU General  Public License as published by the
4129 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4130 + *  option) any later version.
4131 + *
4132 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4133 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4134 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4135 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4136 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4137 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4138 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4139 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4140 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4141 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4142 + *
4143 + *  You should have received a copy of the  GNU General Public License along
4144 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4145 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4146 + *
4147 + *
4148 + **************************************************************************
4149 + * May 2004 P. Sadik.
4150 + *
4151 + * Initial Release
4152 + *
4153 + *
4154 + *
4155 + **************************************************************************
4156 + */
4157 +
4158 +#ifndef __IDT_RC32365_DMA_V_H__
4159 +#define __IDT_RC32365_DMA_V_H__
4160 +
4161 +
4162 +#include  <asm/idt-boards/rc32300/rc32300.h>
4163 +#include  <asm/idt-boards/rc32300/rc32365_dma.h>
4164 +#include  <asm/idt-boards/rc32300/rc32365.h>
4165 +
4166 +#define DMA_CHAN_OFFSET  0x14
4167 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
4168 +#define IS_DMA_FINISHED(X)   (((X) & (DMAD_f_m)) != 0)
4169 +#define IS_DMA_DONE(X)   (((X) & (DMAD_d_m)) != 0)
4170 +
4171 +#define DMA_COUNT(count)   \
4172 +  ((count) & DMAD_count_m)
4173 +
4174 +#define DMA_HALT_TIMEOUT 500
4175 +
4176 +static inline int rc32365_halt_dma(DMA_Chan_t ch)
4177 +{
4178 +       int timeout=1;
4179 +       if (local_readl(&ch->dmac) & DMAC_run_m) {
4180 +               local_writel(0, &ch->dmac);
4181 +
4182 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
4183 +                       if (local_readl(&ch->dmas) & DMAS_h_m) {
4184 +                               local_writel(0, &ch->dmas);
4185 +                               break;
4186 +                       }
4187 +               }
4188 +
4189 +       }
4190 +
4191 +       return timeout ? 0 : 1;
4192 +}
4193 +
4194 +
4195 +static inline void rc32365_start_dma(DMA_Chan_t ch, u32 dma_addr)
4196 +{
4197 +       local_writel(0, &ch->dmandptr);
4198 +       local_writel(dma_addr, &ch->dmadptr);
4199 +}
4200 +
4201 +static inline void rc32365_chain_dma(DMA_Chan_t ch, u32 dma_addr)
4202 +{
4203 +       local_writel(dma_addr, &ch->dmandptr);
4204 +}
4205 +#endif //__IDT_RC32365_DMA_V_H__
4206 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h
4207 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth.h      1970-01-01 01:00:00.000000000 +0100
4208 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 2006-06-18 12:44:28.000000000 +0200
4209 @@ -0,0 +1,344 @@
4210 +/**************************************************************************
4211 + *
4212 + *  BRIEF MODULE DESCRIPTION
4213 + *   RC32365/336 Ethernet hardware abstraction.
4214 + *
4215 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4216 + *
4217 + *  This program is free software; you can redistribute  it and/or modify it
4218 + *  under  the terms of  the GNU General  Public License as published by the
4219 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4220 + *  option) any later version.
4221 + *
4222 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4223 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4224 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4225 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4226 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4227 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4228 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4229 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4230 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4231 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4232 + *
4233 + *  You should have received a copy of the  GNU General Public License along
4234 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4235 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4236 + *
4237 + *
4238 + **************************************************************************
4239 + * May 2004 P. Sadik.
4240 + *
4241 + * Initial Release
4242 + *
4243 + *
4244 + *
4245 + **************************************************************************
4246 + */
4247 +
4248 +#ifndef        __IDT_RC32365_ETH_H__
4249 +#define        __IDT_RC32365_ETH_H__
4250 +
4251 +enum
4252 +{
4253 +       ETH0_PhysicalAddress    = 0x18058000,
4254 +       ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
4255 +       ETH0_VirtualAddress     = 0xb8058000,
4256 +
4257 +       ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
4258 +
4259 +       ETH1_PhysicalAddress    = 0x18060000,
4260 +       ETH1_VirtualAddress     = 0xb8060000,                   // Default
4261 +} ;
4262 +
4263 +typedef struct
4264 +{
4265 +       u32 ethintfc            ;
4266 +       u32 ethfifott           ;
4267 +       u32 etharc              ;
4268 +       u32 ethhash0            ;
4269 +       u32 ethhash1            ;
4270 +       u32 ethu0 [4]           ;       // Reserved.
4271 +       u32 ethpfs              ;
4272 +       u32 ethmcp              ;
4273 +       u32 eth_u1 [10]         ;       // Reserved.
4274 +       u32 ethspare            ;
4275 +       u32 eth_u2 [42]         ;       // Reserved.
4276 +       u32 ethsal0             ;
4277 +       u32 ethsah0             ;
4278 +       u32 ethsal1             ;
4279 +       u32 ethsah1             ;
4280 +       u32 ethsal2             ;
4281 +       u32 ethsah2             ;
4282 +       u32 ethsal3             ;
4283 +       u32 ethsah3             ;
4284 +       u32 ethrbc              ;
4285 +       u32 ethrpc              ;
4286 +       u32 ethrupc             ;
4287 +       u32 ethrfc              ;
4288 +       u32 ethtbc              ;
4289 +       u32 ethgpf              ;
4290 +       u32 eth_u9 [50]         ;       // Reserved.
4291 +       u32 ethmac1             ;
4292 +       u32 ethmac2             ;
4293 +       u32 ethipgt             ;
4294 +       u32 ethipgr             ;
4295 +       u32 ethclrt             ;
4296 +       u32 ethmaxf             ;
4297 +       u32 eth_u10             ;       // Reserved.
4298 +       u32 ethmtest            ;
4299 +       u32 miimcfg             ;
4300 +       u32 miimcmd             ;
4301 +       u32 miimaddr            ;
4302 +       u32 miimwtd             ;
4303 +       u32 miimrdd             ;
4304 +       u32 miimind             ;
4305 +       u32 eth_u11             ;       // Reserved.
4306 +       u32 eth_u12             ;       // Reserved.
4307 +       u32 ethcfsa0            ;
4308 +       u32 ethcfsa1            ;
4309 +       u32 ethcfsa2            ;
4310 +} volatile *ETH_t;
4311 +
4312 +enum
4313 +{
4314 +       ETHINTFC_en_b           = 0,
4315 +       ETHINTFC_en_m           = 0x00000001,
4316 +       ETHINTFC_its_b          = 1,
4317 +       ETHINTFC_its_m          = 0x00000002,
4318 +       ETHINTFC_rip_b          = 2,
4319 +       ETHINTFC_rip_m          = 0x00000004,
4320 +       ETHINTFC_jam_b          = 3,
4321 +       ETHINTFC_jam_m          = 0x00000008,
4322 +       ETHINTFC_ovr_b          = 4,
4323 +       ETHINTFC_ovr_m          = 0x00000010,
4324 +       ETHINTFC_und_b          = 5,
4325 +       ETHINTFC_und_m          = 0x00000020,
4326 +
4327 +       ETHFIFOTT_tth_b         = 0,
4328 +       ETHFIFOTT_tth_m         = 0x0000007f,
4329 +
4330 +       ETHARC_pro_b            = 0,
4331 +       ETHARC_pro_m            = 0x00000001,
4332 +       ETHARC_am_b             = 1,
4333 +       ETHARC_am_m             = 0x00000002,
4334 +       ETHARC_afm_b            = 2,
4335 +       ETHARC_afm_m            = 0x00000004,
4336 +       ETHARC_ab_b             = 3,
4337 +       ETHARC_ab_m             = 0x00000008,
4338 +
4339 +       ETHSAL_byte5_b          = 0,
4340 +       ETHSAL_byte5_m          = 0x000000ff,
4341 +       ETHSAL_byte4_b          = 8,
4342 +       ETHSAL_byte4_m          = 0x0000ff00,
4343 +       ETHSAL_byte3_b          = 16,
4344 +       ETHSAL_byte3_m          = 0x00ff0000,
4345 +       ETHSAL_byte2_b          = 24,
4346 +       ETHSAL_byte2_m          = 0xff000000,
4347 +
4348 +       ETHSAH_byte1_b          = 0,
4349 +       ETHSAH_byte1_m          = 0x000000ff,
4350 +       ETHSAH_byte0_b          = 8,
4351 +       ETHSAH_byte0_m          = 0x0000ff00,
4352 +
4353 +       ETHGPF_ptv_b            = 0,
4354 +       ETHGPF_ptv_m            = 0x0000ffff,
4355 +
4356 +       ETHPFS_pfd_b            = 0,
4357 +       ETHPFS_pfd_m            = 0x00000001,
4358 +
4359 +       ETHCFSA0_cfsa4_b        = 0,
4360 +       ETHCFSA0_cfsa4_m        = 0x000000ff,
4361 +       ETHCFSA0_cfsa5_b        = 8,
4362 +       ETHCFSA0_cfsa5_m        = 0x0000ff00,
4363 +
4364 +       ETHCFSA1_cfsa2_b        = 0,
4365 +       ETHCFSA1_cfsa2_m        = 0x000000ff,
4366 +       ETHCFSA1_cfsa3_b        = 8,
4367 +       ETHCFSA1_cfsa3_m        = 0x0000ff00,
4368 +
4369 +       ETHCFSA2_cfsa0_b        = 0,
4370 +       ETHCFSA2_cfsa0_m        = 0x000000ff,
4371 +       ETHCFSA2_cfsa1_b        = 8,
4372 +       ETHCFSA2_cfsa1_m        = 0x0000ff00,
4373 +
4374 +       ETHMAC1_re_b            = 0,
4375 +       ETHMAC1_re_m            = 0x00000001,
4376 +       ETHMAC1_paf_b           = 1,
4377 +       ETHMAC1_paf_m           = 0x00000002,
4378 +       ETHMAC1_rfc_b           = 2,
4379 +       ETHMAC1_rfc_m           = 0x00000004,
4380 +       ETHMAC1_tfc_b           = 3,
4381 +       ETHMAC1_tfc_m           = 0x00000008,
4382 +       ETHMAC1_lb_b            = 4,
4383 +       ETHMAC1_lb_m            = 0x00000010,
4384 +       ETHMAC1_mr_b            = 31,
4385 +       ETHMAC1_mr_m            = 0x80000000,
4386 +
4387 +       ETHMAC2_fd_b            = 0,
4388 +       ETHMAC2_fd_m            = 0x00000001,
4389 +       ETHMAC2_flc_b           = 1,
4390 +       ETHMAC2_flc_m           = 0x00000002,
4391 +       ETHMAC2_hfe_b           = 2,
4392 +       ETHMAC2_hfe_m           = 0x00000004,
4393 +       ETHMAC2_dc_b            = 3,
4394 +       ETHMAC2_dc_m            = 0x00000008,
4395 +       ETHMAC2_cen_b           = 4,
4396 +       ETHMAC2_cen_m           = 0x00000010,
4397 +       ETHMAC2_pe_b            = 5,
4398 +       ETHMAC2_pe_m            = 0x00000020,
4399 +       ETHMAC2_vpe_b           = 6,
4400 +       ETHMAC2_vpe_m           = 0x00000040,
4401 +       ETHMAC2_ape_b           = 7,
4402 +       ETHMAC2_ape_m           = 0x00000080,
4403 +       ETHMAC2_ppe_b           = 8,
4404 +       ETHMAC2_ppe_m           = 0x00000100,
4405 +       ETHMAC2_lpe_b           = 9,
4406 +       ETHMAC2_lpe_m           = 0x00000200,
4407 +       ETHMAC2_nb_b            = 12,
4408 +       ETHMAC2_nb_m            = 0x00001000,
4409 +       ETHMAC2_bp_b            = 13,
4410 +       ETHMAC2_bp_m            = 0x00002000,
4411 +       ETHMAC2_ed_b            = 14,
4412 +       ETHMAC2_ed_m            = 0x00004000,
4413 +
4414 +       ETHIPGT_ipgt_b          = 0,
4415 +       ETHIPGT_ipgt_m          = 0x0000007f,
4416 +
4417 +       ETHIPGR_ipgr2_b         = 0,
4418 +       ETHIPGR_ipgr2_m         = 0x0000007f,
4419 +       ETHIPGR_ipgr1_b         = 8,
4420 +       ETHIPGR_ipgr1_m         = 0x00007f00,
4421 +
4422 +       ETHCLRT_maxret_b        = 0,
4423 +       ETHCLRT_maxret_m        = 0x0000000f,
4424 +       ETHCLRT_colwin_b        = 8,
4425 +       ETHCLRT_colwin_m        = 0x00003f00,
4426 +
4427 +       ETHMAXF_maxf_b          = 0,
4428 +       ETHMAXF_maxf_m          = 0x0000ffff,
4429 +
4430 +       ETHMTEST_tb_b           = 2,
4431 +       ETHMTEST_tb_m           = 0x00000004,
4432 +
4433 +       ETHMCP_div_b            = 0,
4434 +       ETHMCP_div_m            = 0x000000ff,
4435 +
4436 +       MIIMCFG_rsv_b           = 0,
4437 +       MIIMCFG_rsv_m           = 0x0000000c,
4438 +
4439 +       MIIMCMD_rd_b            = 0,
4440 +       MIIMCMD_rd_m            = 0x00000001,
4441 +       MIIMCMD_scn_b           = 1,
4442 +       MIIMCMD_scn_m           = 0x00000002,
4443 +
4444 +       MIIMADDR_regaddr_b      = 0,
4445 +       MIIMADDR_regaddr_m      = 0x0000001f,
4446 +       MIIMADDR_phyaddr_b      = 8,
4447 +       MIIMADDR_phyaddr_m      = 0x00001f00,
4448 +
4449 +       MIIMWTD_wdata_b         = 0,
4450 +       MIIMWTD_wdata_m         = 0x0000ffff,
4451 +
4452 +       MIIMRDD_rdata_b         = 0,
4453 +       MIIMRDD_rdata_m         = 0x0000ffff,
4454 +
4455 +       MIIMIND_bsy_b           = 0,
4456 +       MIIMIND_bsy_m           = 0x00000001,
4457 +       MIIMIND_scn_b           = 1,
4458 +       MIIMIND_scn_m           = 0x00000002,
4459 +       MIIMIND_nv_b            = 2,
4460 +       MIIMIND_nv_m            = 0x00000004,
4461 +
4462 +} ;
4463 +
4464 +/*
4465 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
4466 + */
4467 +enum
4468 +{
4469 +       ETHRX_fd_b              = 0,
4470 +       ETHRX_fd_m              = 0x00000001,
4471 +       ETHRX_ld_b              = 1,
4472 +       ETHRX_ld_m              = 0x00000002,
4473 +       ETHRX_rok_b             = 2,
4474 +       ETHRX_rok_m             = 0x00000004,
4475 +       ETHRX_fm_b              = 3,
4476 +       ETHRX_fm_m              = 0x00000008,
4477 +       ETHRX_mp_b              = 4,
4478 +       ETHRX_mp_m              = 0x00000010,
4479 +       ETHRX_bp_b              = 5,
4480 +       ETHRX_bp_m              = 0x00000020,
4481 +       ETHRX_vlt_b             = 6,
4482 +       ETHRX_vlt_m             = 0x00000040,
4483 +       ETHRX_cf_b              = 7,
4484 +       ETHRX_cf_m              = 0x00000080,
4485 +       ETHRX_ovr_b             = 8,
4486 +       ETHRX_ovr_m             = 0x00000100,
4487 +       ETHRX_crc_b             = 9,
4488 +       ETHRX_crc_m             = 0x00000200,
4489 +       ETHRX_cv_b              = 10,
4490 +       ETHRX_cv_m              = 0x00000400,
4491 +       ETHRX_db_b              = 11,
4492 +       ETHRX_db_m              = 0x00000800,
4493 +       ETHRX_le_b              = 12,
4494 +       ETHRX_le_m              = 0x00001000,
4495 +       ETHRX_lor_b             = 13,
4496 +       ETHRX_lor_m             = 0x00002000,
4497 +       ETHRX_ces_b             = 14,
4498 +       ETHRX_ces_m             = 0x00004000,
4499 +       ETHRX_length_b          = 16,
4500 +       ETHRX_length_m          = 0xffff0000,
4501 +
4502 +       ETHTX_fd_b              = 0,
4503 +       ETHTX_fd_m              = 0x00000001,
4504 +       ETHTX_ld_b              = 1,
4505 +       ETHTX_ld_m              = 0x00000002,
4506 +       ETHTX_oen_b             = 2,
4507 +       ETHTX_oen_m             = 0x00000004,
4508 +       ETHTX_pen_b             = 3,
4509 +       ETHTX_pen_m             = 0x00000008,
4510 +       ETHTX_cen_b             = 4,
4511 +       ETHTX_cen_m             = 0x00000010,
4512 +       ETHTX_hen_b             = 5,
4513 +       ETHTX_hen_m             = 0x00000020,
4514 +       ETHTX_tok_b             = 6,
4515 +       ETHTX_tok_m             = 0x00000040,
4516 +       ETHTX_mp_b              = 7,
4517 +       ETHTX_mp_m              = 0x00000080,
4518 +       ETHTX_bp_b              = 8,
4519 +       ETHTX_bp_m              = 0x00000100,
4520 +       ETHTX_und_b             = 9,
4521 +       ETHTX_und_m             = 0x00000200,
4522 +       ETHTX_of_b              = 10,
4523 +       ETHTX_of_m              = 0x00000400,
4524 +       ETHTX_ed_b              = 11,
4525 +       ETHTX_ed_m              = 0x00000800,
4526 +       ETHTX_ec_b              = 12,
4527 +       ETHTX_ec_m              = 0x00001000,
4528 +       ETHTX_lc_b              = 13,
4529 +       ETHTX_lc_m              = 0x00002000,
4530 +       ETHTX_td_b              = 14,
4531 +       ETHTX_td_m              = 0x00004000,
4532 +       ETHTX_crc_b             = 15,
4533 +       ETHTX_crc_m             = 0x00008000,
4534 +       ETHTX_le_b              = 16,
4535 +       ETHTX_le_m              = 0x00010000,
4536 +       ETHTX_cc_b              = 17,
4537 +       ETHTX_cc_m              = 0x001E0000,
4538 +} ;
4539 +
4540 +enum
4541 +{
4542 +       ETH0_IPABMC_PhysicalAddress     = 0x18040010,
4543 +       ETH0_IPABMC_VirtualAddress      = 0xb8040000,
4544 +       ETH1_IPABMC_PhysicalAddress     = 0x18040018,
4545 +       ETH1_IPABMC_VirtualAddress      = 0xb8040018,
4546 +} ;
4547 +
4548 +typedef struct
4549 +{
4550 +       u32 ipabmcrx            ;
4551 +       u32 ipabmctx            ;
4552 +}volatile *IPABM_ETH_t;
4553 +#endif //__IDT_RC32365_ETH_H__
4554 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h
4555 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h    1970-01-01 01:00:00.000000000 +0100
4556 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h       2006-06-18 12:44:28.000000000 +0200
4557 @@ -0,0 +1,72 @@
4558 +/**************************************************************************
4559 + *
4560 + *  BRIEF MODULE DESCRIPTION
4561 + *   RC32365/336 Ethernet status checking.
4562 + *
4563 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4564 + *
4565 + *  This program is free software; you can redistribute  it and/or modify it
4566 + *  under  the terms of  the GNU General  Public License as published by the
4567 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4568 + *  option) any later version.
4569 + *
4570 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4571 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4572 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4573 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4574 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4575 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4576 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4577 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4578 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4579 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4580 + *
4581 + *  You should have received a copy of the  GNU General Public License along
4582 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4583 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4584 + *
4585 + *
4586 + **************************************************************************
4587 + * May 2004 P. Sadik.
4588 + *
4589 + * Initial Release
4590 + *
4591 + *
4592 + *
4593 + **************************************************************************
4594 + */
4595 +
4596 +#ifndef __IDT_RC32365_ETH_V_H__
4597 +#define __IDT_RC32365_ETH_V_H__
4598 +#include  <asm/idt-boards/rc32300/rc32365_eth.h>
4599 +
4600 +#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
4601 +#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
4602 +#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
4603 +#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
4604 +#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
4605 +#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
4606 +#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
4607 +#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
4608 +#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
4609 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
4610 +#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
4611 +
4612 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
4613 +
4614 +#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
4615 +#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
4616 +#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
4617 +#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
4618 +#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
4619 +#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
4620 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
4621 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
4622 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
4623 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
4624 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
4625 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
4626 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
4627 +#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
4628 +
4629 +#endif //__IDT_RC32365_ETH_V_H__
4630 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h
4631 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h     1970-01-01 01:00:00.000000000 +0100
4632 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h        2006-06-18 12:44:28.000000000 +0200
4633 @@ -0,0 +1,181 @@
4634 +/**************************************************************************
4635 + *
4636 + *  BRIEF MODULE DESCRIPTION
4637 + *   RC32365/336 GPIO hardware abstraction.
4638 + *
4639 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4640 + *
4641 + *  This program is free software; you can redistribute  it and/or modify it
4642 + *  under  the terms of  the GNU General  Public License as published by the
4643 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4644 + *  option) any later version.
4645 + *
4646 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4647 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4648 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4649 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4650 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4651 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4652 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4653 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4654 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4655 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4656 + *
4657 + *  You should have received a copy of the  GNU General Public License along
4658 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4659 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4660 + *
4661 + *
4662 + **************************************************************************
4663 + * May 2004 P. Sadik.
4664 + *
4665 + * Initial Release
4666 + *
4667 + *
4668 + *
4669 + **************************************************************************
4670 + */
4671 +
4672 +#ifndef        __IDT_RC32365_GPIO_H__
4673 +#define        __IDT_RC32365_GPIO_H__
4674 +
4675 +enum
4676 +{
4677 +       GPIO0_PhysicalAddress   = 0x18048000,
4678 +       GPIO_PhysicalAddress    = GPIO0_PhysicalAddress,        // Default
4679 +
4680 +       GPIO0_VirtualAddress    = 0xb8048000,
4681 +       GPIO_VirtualAddress     = GPIO0_VirtualAddress,         // Default
4682 +} ;
4683 +
4684 +typedef struct
4685 +{
4686 +       u32   gpiofunc;   /* GPIO Function Register
4687 +                          * gpiofunc[x]==0 bit = gpio
4688 +                          * func[x]==1  bit = altfunc
4689 +                          */
4690 +       u32   gpiocfg;    /* GPIO Configuration Register
4691 +                          * gpiocfg[x]==0 bit = input
4692 +                          * gpiocfg[x]==1 bit = output
4693 +                          */
4694 +       u32   gpiod;        /* GPIO Data Register
4695 +                            * gpiod[x] read/write gpio pinX status
4696 +                            */
4697 +       u32   gpioilevel; /* GPIO Interrupt Status Register
4698 +                          * interrupt level (see gpioistat)
4699 +                          */
4700 +       u32   gpioistat;  /* Gpio Interrupt Status Register
4701 +                          * istat[x] = (gpiod[x] == level[x])
4702 +                          * cleared in ISR (STICKY bits)
4703 +                          */
4704 +       u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
4705 +} volatile * GPIO_t ;
4706 +
4707 +typedef enum
4708 +{
4709 +       GPIO_gpio_v         = 0,                // gpiofunc use pin as GPIO.
4710 +       GPIO_alt_v          = 1,                // gpiofunc use pin as alt.
4711 +       GPIO_input_v        = 0,                // gpiocfg use pin as input.
4712 +       GPIO_output_v       = 1,                // gpiocfg use pin as output.
4713 +       GPIO_pin0_b         = 0,
4714 +       GPIO_pin0_m         = 0x00000001,
4715 +       GPIO_pin1_b         = 1,
4716 +       GPIO_pin1_m         = 0x00000002,
4717 +       GPIO_pin2_b         = 2,
4718 +       GPIO_pin2_m         = 0x00000004,
4719 +       GPIO_pin3_b         = 3,
4720 +       GPIO_pin3_m         = 0x00000008,
4721 +       GPIO_pin4_b         = 4,
4722 +       GPIO_pin4_m         = 0x00000010,
4723 +       GPIO_pin5_b         = 5,
4724 +       GPIO_pin5_m         = 0x00000020,
4725 +       GPIO_pin6_b         = 6,
4726 +       GPIO_pin6_m         = 0x00000040,
4727 +       GPIO_pin7_b         = 7,
4728 +       GPIO_pin7_m         = 0x00000080,
4729 +       GPIO_pin8_b         = 8,
4730 +       GPIO_pin8_m         = 0x00000100,
4731 +       GPIO_pin9_b         = 9,
4732 +       GPIO_pin9_m         = 0x00000200,
4733 +       GPIO_pin10_b        = 10,
4734 +       GPIO_pin10_m        = 0x00000400,
4735 +       GPIO_pin11_b        = 11,
4736 +       GPIO_pin11_m        = 0x00000800,
4737 +       GPIO_pin12_b        = 12,
4738 +       GPIO_pin12_m        = 0x00001000,
4739 +       GPIO_pin13_b        = 13,
4740 +       GPIO_pin13_m        = 0x00002000,
4741 +       GPIO_pin14_b        = 14,
4742 +       GPIO_pin14_m        = 0x00004000,
4743 +       GPIO_pin15_b        = 15,
4744 +       GPIO_pin15_m        = 0x00008000,
4745 +
4746 +// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
4747 +
4748 +       GPIO_u0sout_b       = GPIO_pin0_b,              // UART 0 serial out.
4749 +       GPIO_u0sout_m       = GPIO_pin0_m,
4750 +       GPIO_u0sout_cfg_v   = GPIO_output_v,
4751 +
4752 +       GPIO_u0sinp_b       = GPIO_pin1_b,                      // UART 0 serial in.
4753 +       GPIO_u0sinp_m       = GPIO_pin1_m,
4754 +       GPIO_u0sinp_cfg_v   = GPIO_input_v,
4755 +
4756 +       GPIO_maddr22_b      = GPIO_pin2_b,      // M&P bus bit 22.
4757 +       GPIO_maddr22_m      = GPIO_pin2_m,
4758 +       GPIO_maddr22_cfg_v  = GPIO_output_v,
4759 +
4760 +       GPIO_maddr23_b      = GPIO_pin3_b,      // M&P bus bit 23.
4761 +       GPIO_maddr23_m      = GPIO_pin3_m,
4762 +       GPIO_maddr23_cfg_v  = GPIO_output_v,
4763 +
4764 +       GPIO_maddr24_b      = GPIO_pin4_b,      // M&P bus bit 24.
4765 +       GPIO_maddr24_m      = GPIO_pin4_m,
4766 +       GPIO_maddr24_cfg_v  = GPIO_output_v,
4767 +
4768 +       GPIO_maddr25_b      = GPIO_pin5_b,      // M&P bus bit 25.
4769 +       GPIO_maddr25_m      = GPIO_pin5_m,
4770 +       GPIO_maddr25_cfg_v  = GPIO_output_v,
4771 +
4772 +       GPIO_rngclk_b       = GPIO_pin6_b,      // reserved.
4773 +       GPIO_rngclk_m       = GPIO_pin6_m,
4774 +       GPIO_rngclk_cfg_v   = GPIO_input_v,
4775 +
4776 +       GPIO_sdckenp_b      = GPIO_pin7_b,      // reserved.
4777 +       GPIO_sdckenp_m      = GPIO_pin7_m,
4778 +       GPIO_sdckenp_cfg_v  = GPIO_output_v,
4779 +
4780 +       GPIO_cen1_b         = GPIO_pin8_b,      // reserved.
4781 +       GPIO_cen1_m         = GPIO_pin8_m,
4782 +       GPIO_cen1_cfg_v     = GPIO_output_v,
4783 +
4784 +       GPIO_cen2_b         = GPIO_pin9_b,      // reserved.
4785 +       GPIO_cen2_m         = GPIO_pin9_m,
4786 +       GPIO_cen2_cfg_v     = GPIO_output_v,
4787 +
4788 +       GPIO_regn_b         = GPIO_pin10_b,     // reserved.
4789 +       GPIO_regn_m         = GPIO_pin10_m,
4790 +       GPIO_regn_cfg_v     = GPIO_output_v,
4791 +
4792 +       GPIO_iordn_b        = GPIO_pin11_b,     // reserved.
4793 +       GPIO_iordn_m        = GPIO_pin11_m,
4794 +       GPIO_iordn_cfg_v    = GPIO_output_v,
4795 +
4796 +       GPIO_iowrn_b        = GPIO_pin12_b,     // reserved.
4797 +       GPIO_iowrn_m        = GPIO_pin12_m,
4798 +       GPIO_iowrn_cfg_v    = GPIO_output_v,
4799 +
4800 +       GPIO_pcireqn2_b     = GPIO_pin13_b,     // PCI messaging int.
4801 +       GPIO_pcireqn2_m     = GPIO_pin13_m,
4802 +       GPIO_pcireqn2_cfg_v = GPIO_input_v,
4803 +
4804 +       GPIO_pcigntn2_b     = GPIO_pin14_b,     // PCI messaging int.
4805 +       GPIO_pcigntn2_m     = GPIO_pin14_m,
4806 +       GPIO_pcigntn2_cfg_v = GPIO_output_v,
4807 +
4808 +       GPIO_pcimuintn_b    = GPIO_pin15_b,     // PCI messaging int.
4809 +       GPIO_pcimuintn_m    = GPIO_pin15_m,
4810 +       GPIO_pcimuintn_cfg_v= GPIO_output_v,
4811 +
4812 +} GPIO_DEFS_t;
4813 +
4814 +#endif //__IDT_RC32365_GPIO_H__
4815 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h
4816 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h   1970-01-01 01:00:00.000000000 +0100
4817 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h      2006-06-18 12:44:28.000000000 +0200
4818 @@ -0,0 +1,91 @@
4819 +/**************************************************************************
4820 + *
4821 + *  BRIEF MODULE DESCRIPTION
4822 + *   Routines to set/clear/toggle GPIO on RC32365
4823 + *
4824 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4825 + *
4826 + *  This program is free software; you can redistribute  it and/or modify it
4827 + *  under  the terms of  the GNU General  Public License as published by the
4828 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4829 + *  option) any later version.
4830 + *
4831 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4832 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4833 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4834 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4835 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4836 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4837 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4838 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4839 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4840 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4841 + *
4842 + *  You should have received a copy of the  GNU General Public License along
4843 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4844 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4845 + *
4846 + *
4847 + **************************************************************************
4848 + * May 2004 P. Sadik.
4849 + *
4850 + * Initial Release
4851 + *
4852 + *
4853 + *
4854 + **************************************************************************
4855 + */
4856 +#ifndef        __IDT_RC32365_GPIO_V_H__
4857 +#define        __IDT_RC32365_GPIO_V_H__
4858 +
4859 +
4860 +#ifdef _LANGUAGE_ASSEMBLY
4861 +#define SET_GPIO(pin) \
4862 +       lui t5,0xb804 ; \
4863 +       ori t5,t5,0x8000 ; \
4864 +       lw  t4,8(t5) ; \
4865 +       ori t4,t4,pin ; \
4866 +       sw  t4,8(t5) ;
4867 +
4868 +#define CLEAR_GPIO(pin) \
4869 +       lui t5,0xb804 ; \
4870 +       ori t5,t5,0x8000 ; \
4871 +       lw  t4,8(t5) ; \
4872 +        lui t6,0xFFFF; \
4873 +        ori t6,t6,0xFFFF; \
4874 +       xori t6,t6,pin ; \
4875 +        and  t4,t6 ; \
4876 +       sw  t4,8(t5) ;
4877 +
4878 +#define TOGGLE_GPIO(pin) \
4879 +       lui t5,0xb804 ; \
4880 +       ori t5,t5,0x8000 ; \
4881 +       lw  t4,8(t5) ; \
4882 +       xori t4,t4,pin ; \
4883 +       sw  t4,8(t5) ;
4884 +
4885 +#else // !_LANGUAGE_ASSEMBLY
4886 +#include  <asm/rc32300/types.h>
4887 +#include  <asm/rc32300/rc32365_gpio.h>
4888 +#include  <asm/rc32300/rc32365.h>
4889 +
4890 +static inline void set_gpio(unsigned long pin)
4891 +{
4892 +  idt_gpio->gpiod |= pin;
4893 +}
4894 +
4895 +static inline void clear_gpio(unsigned long pin)
4896 +{
4897 +  idt_gpio->gpiod &= ~pin;
4898 +}
4899 +static inline void toggle_gpio(unsigned long pin)
4900 +{
4901 +  idt_gpio->gpiod ^= pin;
4902 +}
4903 +#define SET_GPIO(pin) set_gpio(pin)
4904 +#define CLEAR_GPIO(pin) clear_gpio(pin)
4905 +#define TOGGLE_GPIO(pin) toggle_gpio(pin)
4906 +#endif // _LANGUAGE_ASSEMBLY
4907 +
4908 +#endif //__IDT_RC32365_GPIO_V_H__
4909 +
4910 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h
4911 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365.h  1970-01-01 01:00:00.000000000 +0100
4912 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h     2006-06-18 12:44:28.000000000 +0200
4913 @@ -0,0 +1,160 @@
4914 +/**************************************************************************
4915 + *
4916 + *  BRIEF MODULE DESCRIPTION
4917 + *   Definitions for IDT RC32365 CPU.
4918 + *
4919 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4920 + *
4921 + *  This program is free software; you can redistribute  it and/or modify it
4922 + *  under  the terms of  the GNU General  Public License as published by the
4923 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4924 + *  option) any later version.
4925 + *
4926 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4927 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4928 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4929 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4930 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4931 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4932 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4933 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4934 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4935 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4936 + *
4937 + *  You should have received a copy of the  GNU General Public License along
4938 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4939 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4940 + *
4941 + *
4942 + **************************************************************************
4943 + * May 2004 P. Sadik.
4944 + *
4945 + * Initial Release
4946 + *
4947 + *
4948 + *
4949 + **************************************************************************
4950 + */
4951 +
4952 +#ifndef __IDT_RC32365_H__
4953 +#define __IDT_RC32365_H__
4954 +
4955 +extern unsigned int cedar_za;
4956 +
4957 +/* Base address of internal registers */
4958 +#define RC32365_REG_BASE   0x18000000
4959 +
4960 +/* System ID Registers */
4961 +#define CPU_SYSID          (RC32365_REG_BASE + 0x00018)
4962 +#define CPU_DEVTYPE        (RC32365_REG_BASE + 0x0001c)
4963 +
4964 +/* Reset Controller */
4965 +#define RESET_CNTL         (RC32365_REG_BASE + 0x08000)
4966 +#define BOOT_VECTOR        (RC32365_REG_BASE + 0x08004)
4967 +
4968 +/* Device Controller */
4969 +#define DEV0_BASE          (RC32365_REG_BASE + 0x10000)
4970 +#define DEV0_MASK          (RC32365_REG_BASE + 0x10004)
4971 +#define DEV0_CNTL          (RC32365_REG_BASE + 0x10008)
4972 +#define DEV0_TIMING        (RC32365_REG_BASE + 0x1000c)
4973 +#define DEV_REG_OFFSET     0x10
4974 +
4975 +/* SDRAM Controller */
4976 +#define SDRAM0_BASE        (RC32365_REG_BASE + 0x18000)
4977 +#define SDRAM0_MASK        (RC32365_REG_BASE + 0x18004)
4978 +#define SDRAM1_BASE        (RC32365_REG_BASE + 0x18008)
4979 +#define SDRAM1_MASK        (RC32365_REG_BASE + 0x1800c)
4980 +#define SDRAM_CNTL         (RC32365_REG_BASE + 0x18010)
4981 +
4982 +/* Counters/Timers */
4983 +#define TIMER0_COUNT       (RC32365_REG_BASE + 0x20000)
4984 +#define TIMER0_COMPARE     (RC32365_REG_BASE + 0x20004)
4985 +#define TIMER0_CNTL        (RC32365_REG_BASE + 0x20008)
4986 +#define TIMER0_SELECT      (RC32365_REG_BASE + 0x2000c)
4987 +#define TIMER_REG_OFFSET   0x10
4988 +
4989 +/* System Integrity */
4990 +
4991 +/* Interrupt Controller */
4992 +#define IC_GROUP0_PEND     (RC32365_REG_BASE + 0x30000)
4993 +#define IC_GROUP0_TEST     (RC32365_REG_BASE + 0x30004)
4994 +#define IC_GROUP0_MASK     (RC32365_REG_BASE + 0x30008)
4995 +#define IC_GROUP_OFFSET    0x0c
4996 +
4997 +#define NUM_INTR_GROUPS    5
4998 +/*
4999 + * The IRQ mapping is as follows:
5000 + *
5001 + *    IRQ         Mapped To
5002 + *    ---     -------------------
5003 + *     0      SW0  (IP0) SW0 intr
5004 + *     1      SW1  (IP1) SW1 intr
5005 + *     -      Int0 (IP2) mapped to GROUP0_IRQ_BASE
5006 + *     -      Int1 (IP3) mapped to GROUP1_IRQ_BASE
5007 + *     -      Int2 (IP4) mapped to GROUP2_IRQ_BASE
5008 + *     -      Int3 (IP5) mapped to GROUP3_IRQ_BASE
5009 + *     -      Int4 (IP6) mapped to GROUP4_IRQ_BASE
5010 + *     7      Int5 (IP7) CP0 Timer
5011 + *
5012 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
5013 + * internally on the RC32365 is routed to the Expansion
5014 + * Interrupt Controller.
5015 + */
5016 +#define MIPS_CPU_TIMER_IRQ 7
5017 +
5018 +#define GROUP0_IRQ_BASE  8                      // Counter/Timers, UCW
5019 +#define GROUP1_IRQ_BASE  (GROUP0_IRQ_BASE + 32) // DMA
5020 +#define GROUP2_IRQ_BASE  (GROUP1_IRQ_BASE + 32) // RNG, SEC
5021 +#define GROUP3_IRQ_BASE  (GROUP2_IRQ_BASE + 32) // Eth, PCI, UARTs
5022 +#define GROUP4_IRQ_BASE  (GROUP3_IRQ_BASE + 32) // GPIO
5023 +
5024 +#define RC32365_NR_IRQS  (GROUP4_IRQ_BASE + 32)
5025 +
5026 +/* DMA - see rc32365_dma.h for full list of registers */
5027 +
5028 +#define RC32365_DMA_BASE (RC32365_REG_BASE + 0x38000)
5029 +#define DMA_CHAN_OFFSET  0x14
5030 +
5031 +/* GPIO Controller */
5032 +#define idt_gpio              ((volatile GPIO_t) GPIO0_VirtualAddress)
5033 +
5034 +/* 16550 UARTs */
5035 +#ifdef __MIPSEB__
5036 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50003)
5037 +#else
5038 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50000)
5039 +#endif
5040 +#define RC32300_UART0_IRQ  (GROUP3_IRQ_BASE + 0)
5041 +
5042 +/* Ethernet - see rc32365_eth.h for full list of registers */
5043 +
5044 +#define RC32365_ETH_BASE   (RC32365_REG_BASE + 0x58000)
5045 +
5046 +#define IDT_CLOCK_MULT     2
5047 +
5048 +/* FLASH (device 1) */
5049 +#define FLASH_BASE         0x08000000
5050 +#define FLASH_SIZE         0x00800000
5051 +
5052 +/* LCD 4-digit display (device 2) */
5053 +#define LCD_DIGIT0         0x0C000003
5054 +#define LCD_DIGIT1         0x0C000002
5055 +#define LCD_DIGIT2         0x0C000001
5056 +#define LCD_DIGIT3         0x0C000000
5057 +
5058 +/* RTC (DS1553) (device 2) */
5059 +#define RTC_BASE           0x0c800000
5060 +/* NVRAM */
5061 +#define NVRAM_BASE         RTC_BASE
5062 +#define NVRAM_ENVSIZE_OFF  4
5063 +#define NVRAM_ENVSTART_OFF 32
5064 +
5065 +/* Interrupts routed on 79EB365 board */
5066 +#define RC32365_PCI_INTA_IRQ (GROUP4_IRQ_BASE +  8)
5067 +#define RC32365_PCI_INTB_IRQ (GROUP4_IRQ_BASE +  9)
5068 +#define RC32365_PCI_INTC_IRQ (GROUP4_IRQ_BASE + 10)
5069 +#define RC32365_PCI_INTD_IRQ (GROUP4_IRQ_BASE + 11)
5070 +
5071 +#define RAM_SIZE          (32 * 1024 * 1024)
5072 +
5073 +#endif //__IDT_RC32365_H__
5074 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h
5075 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci.h      1970-01-01 01:00:00.000000000 +0100
5076 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 2006-06-18 12:44:28.000000000 +0200
5077 @@ -0,0 +1,515 @@
5078 +/**************************************************************************
5079 + *
5080 + *  BRIEF MODULE DESCRIPTION
5081 + *   Datatype declaration for IDT 79EB365/336 PCI
5082 + *
5083 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
5084 + *
5085 + *  This program is free software; you can redistribute  it and/or modify it
5086 + *  under  the terms of  the GNU General  Public License as published by the
5087 + *  Free Software Foundation;  either version 2 of the  License, or (at your
5088 + *  option) any later version.
5089 + *
5090 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
5091 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
5092 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
5093 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
5094 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5095 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
5096 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5097 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
5098 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5099 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5100 + *
5101 + *  You should have received a copy of the  GNU General Public License along
5102 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
5103 + *  675 Mass Ave, Cambridge, MA 02139, USA.
5104 + *
5105 + *
5106 + **************************************************************************
5107 + * May 2004 P. Sadik.
5108 + *
5109 + * Initial Release
5110 + *
5111 + *
5112 + *
5113 + **************************************************************************
5114 + */
5115 +
5116 +#ifndef __IDT_RC32365_PCI_H__
5117 +#define __IDT_RC32365_PCI_H__
5118 +
5119 +enum
5120 +{
5121 +       PCI0_PhysicalAddress    = 0x18068000,
5122 +       PCI_PhysicalAddress     = PCI0_PhysicalAddress,
5123 +
5124 +       PCI0_VirtualAddress     = 0xb8068000,
5125 +       PCI_VirtualAddress      = PCI0_VirtualAddress,
5126 +} ;
5127 +
5128 +enum
5129 +{
5130 +       PCI_LbaCount    = 4,            // Local base addresses.
5131 +} ;
5132 +
5133 +typedef struct
5134 +{
5135 +       u32     a ;             // Address.
5136 +       u32     c ;             // Control.
5137 +       u32     m ;             // mapping.
5138 +} PCI_Map_s ;
5139 +
5140 +typedef struct
5141 +{
5142 +       u32             pcic ;
5143 +       u32             pcis ;
5144 +       u32             pcism ;
5145 +       u32             pcicfga ;
5146 +       u32             pcicfgd ;
5147 +       PCI_Map_s       pcilba [PCI_LbaCount] ;
5148 +       u32             pcidac ;
5149 +       u32             pcidas ;
5150 +       u32             pcidasm ;
5151 +       u32             pcidad ;
5152 +       u32             pcidma8c ;
5153 +       u32             pcidma9c ;
5154 +       u32             pcitc ;
5155 +} volatile *PCI_t ;
5156 +
5157 +// PCI messaging unit.
5158 +enum
5159 +{
5160 +       PCIM_Count      = 2,
5161 +} ;
5162 +typedef struct
5163 +{
5164 +       u32             pciim [PCIM_Count] ;
5165 +       u32             pciom [PCIM_Count] ;
5166 +       u32             pciid ;
5167 +       u32             pciiic ;
5168 +       u32             pciiim ;
5169 +       u32             pciiod ;
5170 +       u32             pciioic ;
5171 +       u32             pciioim ;
5172 +} volatile *PCIM_t ;
5173 +
5174 +/*******************************************************************************
5175 + *
5176 + * PCI Control Register
5177 + *
5178 + ******************************************************************************/
5179 +enum
5180 +{
5181 +       PCIC_en_b       = 0,
5182 +       PCIC_en_m       = 0x00000001,
5183 +       PCIC_tnr_b      = 1,
5184 +       PCIC_tnr_m      = 0x00000002,
5185 +       PCIC_sce_b      = 2,
5186 +       PCIC_sce_m      = 0x00000004,
5187 +       PCIC_ien_b      = 3,
5188 +       PCIC_ien_m      = 0x00000008,
5189 +       PCIC_aaa_b      = 4,
5190 +       PCIC_aaa_m      = 0x00000010,
5191 +       PCIC_eap_b      = 5,
5192 +       PCIC_eap_m      = 0x00000020,
5193 +       PCIC_pcim_b     = 6,
5194 +       PCIC_pcim_m     = 0x000001c0,
5195 +               PCIC_pcim_disabled_v    = 0,
5196 +               PCIC_pcim_tnr_v         = 1,    // Satellite - target not ready
5197 +               PCIC_pcim_suspend_v     = 2,    // Satellite - suspended CPU.
5198 +               PCIC_pcim_extern_v      = 3,    // Host - external arbiter.
5199 +               PCIC_pcim_fixed_v       = 4,    // Host - fixed priority arb.
5200 +               PCIC_pcim_roundrobin_v  = 5,    // Host - round robin priority.
5201 +               PCIC_pcim_reserved6_v   = 6,
5202 +               PCIC_pcim_reserved7_v   = 7,
5203 +       PCIC_igm_b      = 9,
5204 +       PCIC_igm_m      = 0x00000200,
5205 +} ;
5206 +
5207 +/*******************************************************************************
5208 + *
5209 + * PCI Status Register
5210 + *
5211 + ******************************************************************************/
5212 +enum {
5213 +       PCIS_eed_b      = 0,
5214 +       PCIS_eed_m      = 0x00000001,
5215 +       PCIS_wr_b       = 1,
5216 +       PCIS_wr_m       = 0x00000002,
5217 +       PCIS_nmi_b      = 2,
5218 +       PCIS_nmi_m      = 0x00000004,
5219 +       PCIS_ii_b       = 3,
5220 +       PCIS_ii_m       = 0x00000008,
5221 +       PCIS_cwe_b      = 4,
5222 +       PCIS_cwe_m      = 0x00000010,
5223 +       PCIS_cre_b      = 5,
5224 +       PCIS_cre_m      = 0x00000020,
5225 +       PCIS_mdpe_b     = 6,
5226 +       PCIS_mdpe_m     = 0x00000040,
5227 +       PCIS_sta_b      = 7,
5228 +       PCIS_sta_m      = 0x00000080,
5229 +       PCIS_rta_b      = 8,
5230 +       PCIS_rta_m      = 0x00000100,
5231 +       PCIS_rma_b      = 9,
5232 +       PCIS_rma_m      = 0x00000200,
5233 +       PCIS_sse_b      = 10,
5234 +       PCIS_sse_m      = 0x00000400,
5235 +       PCIS_ose_b      = 11,
5236 +       PCIS_ose_m      = 0x00000800,
5237 +       PCIS_pe_b       = 12,
5238 +       PCIS_pe_m       = 0x00001000,
5239 +       PCIS_tae_b      = 13,
5240 +       PCIS_tae_m      = 0x00002000,
5241 +       PCIS_rle_b      = 14,
5242 +       PCIS_rle_m      = 0x00004000,
5243 +       PCIS_bme_b      = 15,
5244 +       PCIS_bme_m      = 0x00008000,
5245 +       PCIS_prd_b      = 16,
5246 +       PCIS_prd_m      = 0x00010000,
5247 +       PCIS_rip_b      = 17,
5248 +       PCIS_rip_m      = 0x00020000,
5249 +} ;
5250 +
5251 +/*******************************************************************************
5252 + *
5253 + * PCI Status Mask Register
5254 + *
5255 + ******************************************************************************/
5256 +enum {
5257 +       PCISM_eed_b             = 0,
5258 +       PCISM_eed_m             = 0x00000001,
5259 +       PCISM_wr_b              = 1,
5260 +       PCISM_wr_m              = 0x00000002,
5261 +       PCISM_nmi_b             = 2,
5262 +       PCISM_nmi_m             = 0x00000004,
5263 +       PCISM_ii_b              = 3,
5264 +       PCISM_ii_m              = 0x00000008,
5265 +       PCISM_cwe_b             = 4,
5266 +       PCISM_cwe_m             = 0x00000010,
5267 +       PCISM_cre_b             = 5,
5268 +       PCISM_cre_m             = 0x00000020,
5269 +       PCISM_mdpe_b            = 6,
5270 +       PCISM_mdpe_m            = 0x00000040,
5271 +       PCISM_sta_b             = 7,
5272 +       PCISM_sta_m             = 0x00000080,
5273 +       PCISM_rta_b             = 8,
5274 +       PCISM_rta_m             = 0x00000100,
5275 +       PCISM_rma_b             = 9,
5276 +       PCISM_rma_m             = 0x00000200,
5277 +       PCISM_sse_b             = 10,
5278 +       PCISM_sse_m             = 0x00000400,
5279 +       PCISM_ose_b             = 11,
5280 +       PCISM_ose_m             = 0x00000800,
5281 +       PCISM_pe_b              = 12,
5282 +       PCISM_pe_m              = 0x00001000,
5283 +       PCISM_tae_b             = 13,
5284 +       PCISM_tae_m             = 0x00002000,
5285 +       PCISM_rle_b             = 14,
5286 +       PCISM_rle_m             = 0x00004000,
5287 +       PCISM_bme_b             = 15,
5288 +       PCISM_bme_m             = 0x00008000,
5289 +       PCISM_prd_b             = 16,
5290 +       PCISM_prd_m             = 0x00010000,
5291 +       PCISM_rip_b             = 17,
5292 +       PCISM_rip_m             = 0x00020000,
5293 +} ;
5294 +
5295 +/*******************************************************************************
5296 + *
5297 + * PCI Configuration Address Register
5298 + *
5299 + ******************************************************************************/
5300 +enum {
5301 +       PCICFGA_reg_b           = 2,
5302 +       PCICFGA_reg_m           = 0x000000fc,
5303 +       PCICFGA_reg_id_v        = 0x00>>2, //use PCFGID_
5304 +       PCICFGA_reg_04_v        = 0x04>>2, //use PCFG04_
5305 +       PCICFGA_reg_08_v        = 0x08>>2, //use PCFG08_
5306 +       PCICFGA_reg_0C_v        = 0x0C>>2, //use PCFG0C_
5307 +       PCICFGA_reg_pba0_v      = 0x10>>2, //use PCIPBA_
5308 +       PCICFGA_reg_pba1_v      = 0x14>>2, //use PCIPBA_
5309 +       PCICFGA_reg_pba2_v      = 0x18>>2, //use PCIPBA_
5310 +       PCICFGA_reg_pba3_v      = 0x1c>>2, //use PCIPBA_
5311 +       PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
5312 +       PCICFGA_reg_3C_v        = 0x3C>>2, //use PCFG3C_
5313 +       PCICFGA_reg_pba0c_v     = 0x44>>2, //use PCIPBAC_
5314 +       PCICFGA_reg_pba0m_v     = 0x48>>2,
5315 +       PCICFGA_reg_pba1c_v     = 0x4c>>2, //use PCIPBAC_
5316 +       PCICFGA_reg_pba1m_v     = 0x50>>2,
5317 +       PCICFGA_reg_pba2c_v     = 0x54>>2, //use PCIPBAC_
5318 +       PCICFGA_reg_pba2m_v     = 0x58>>2,
5319 +       PCICFGA_reg_pba3c_v     = 0x5c>>2, //use PCIPBAC_
5320 +       PCICFGA_reg_pba3m_v     = 0x60>>2,
5321 +       PCICFGA_reg_pmgt_v      = 0x64>>2,
5322 +       PCICFGA_func_b          = 8,
5323 +       PCICFGA_func_m          = 0x00000700,
5324 +       PCICFGA_dev_b           = 11,
5325 +       PCICFGA_dev_m           = 0x0000f800,
5326 +       PCICFGA_dev_internal_v  = 0,
5327 +       PCICFGA_bus_b           = 16,
5328 +       PCICFGA_bus_m           = 0x00ff0000,
5329 +       PCICFGA_bus_type0_v     = 0,    //local bus
5330 +       PCICFGA_en_b            = 31,           // read only
5331 +       PCICFGA_en_m            = 0x80000000,
5332 +} ;
5333 +
5334 +enum {
5335 +       PCFGID_vendor_b         = 0,
5336 +       PCFGID_vendor_m         = 0x0000ffff,
5337 +       PCFGID_vendor_IDT_v             = 0x111d,
5338 +       PCFGID_device_b         = 16,
5339 +       PCFGID_device_m         = 0xffff0000,
5340 +       PCFGID_device_Acaciade_v        = 0x0207,
5341 +
5342 +       PCFG04_command_ioena_b          = 1,
5343 +       PCFG04_command_ioena_m          = 0x00000001,
5344 +       PCFG04_command_memena_b         = 2,
5345 +       PCFG04_command_memena_m         = 0x00000002,
5346 +       PCFG04_command_bmena_b          = 3,
5347 +       PCFG04_command_bmena_m          = 0x00000004,
5348 +       PCFG04_command_mwinv_b          = 5,
5349 +       PCFG04_command_mwinv_m          = 0x00000010,
5350 +       PCFG04_command_parena_b         = 7,
5351 +       PCFG04_command_parena_m         = 0x00000040,
5352 +       PCFG04_command_serrena_b        = 9,
5353 +       PCFG04_command_serrena_m        = 0x00000100,
5354 +       PCFG04_command_fastbbena_b      = 10,
5355 +       PCFG04_command_fastbbena_m      = 0x00000200,
5356 +       PCFG04_status_b                 = 16,
5357 +       PCFG04_status_m                 = 0xffff0000,
5358 +       PCFG04_status_66MHz_b           = 21,   // 66 MHz enable
5359 +       PCFG04_status_66MHz_m           = 0x00200000,
5360 +       PCFG04_status_fbb_b             = 23,
5361 +       PCFG04_status_fbb_m             = 0x00800000,
5362 +       PCFG04_status_mdpe_b            = 24,
5363 +       PCFG04_status_mdpe_m            = 0x01000000,
5364 +       PCFG04_status_dst_b             = 25,
5365 +       PCFG04_status_dst_m             = 0x06000000,
5366 +       PCFG04_status_sta_b             = 27,
5367 +       PCFG04_status_sta_m             = 0x08000000,
5368 +       PCFG04_status_rta_b             = 28,
5369 +       PCFG04_status_rta_m             = 0x10000000,
5370 +       PCFG04_status_rma_b             = 29,
5371 +       PCFG04_status_rma_m             = 0x20000000,
5372 +       PCFG04_status_sse_b             = 30,
5373 +       PCFG04_status_sse_m             = 0x40000000,
5374 +       PCFG04_status_pe_b              = 31,
5375 +       PCFG04_status_pe_m              = 0x40000000,
5376 +
5377 +       PCFG08_revId_b                  = 0,
5378 +       PCFG08_revId_m                  = 0x000000ff,
5379 +       PCFG08_classCode_b              = 0,
5380 +       PCFG08_classCode_m              = 0xffffff00,
5381 +       PCFG08_classCode_bridge_v       = 06,
5382 +       PCFG08_classCode_proc_v         = 0x0b3000, // processor-MIPS
5383 +       PCFG0C_cacheline_b              = 0,
5384 +       PCFG0C_cacheline_m              = 0x000000ff,
5385 +       PCFG0C_masterLatency_b          = 8,
5386 +       PCFG0C_masterLatency_m          = 0x0000ff00,
5387 +       PCFG0C_headerType_b             = 16,
5388 +       PCFG0C_headerType_m             = 0x00ff0000,
5389 +       PCFG0C_bist_b                   = 24,
5390 +       PCFG0C_bist_m                   = 0xff000000,
5391 +
5392 +       PCIPBA_msi_b                    = 0,
5393 +       PCIPBA_msi_m                    = 0x00000001,
5394 +       PCIPBA_p_b                      = 3,
5395 +       PCIPBA_p_m                      = 0x00000004,
5396 +       PCIPBA_baddr_b                  = 8,
5397 +       PCIPBA_baddr_m                  = 0xffffff00,
5398 +
5399 +       PCFGSS_vendorId_b               = 0,
5400 +       PCFGSS_vendorId_m               = 0x0000ffff,
5401 +       PCFGSS_id_b                     = 16,
5402 +       PCFGSS_id_m                     = 0xffff0000,
5403 +
5404 +       PCFG3C_interruptLine_b          = 0,
5405 +       PCFG3C_interruptLine_m          = 0x000000ff,
5406 +       PCFG3C_interruptPin_b           = 8,
5407 +       PCFG3C_interruptPin_m           = 0x0000ff00,
5408 +       PCFG3C_minGrant_b               = 16,
5409 +       PCFG3C_minGrant_m               = 0x00ff0000,
5410 +       PCFG3C_maxLat_b                 = 24,
5411 +       PCFG3C_maxLat_m                 = 0xff000000,
5412 +
5413 +       PCIPBAC_msi_b                   = 0,
5414 +       PCIPBAC_msi_m                   = 0x00000001,
5415 +       PCIPBAC_p_b                     = 1,
5416 +       PCIPBAC_p_m                     = 0x00000002,
5417 +       PCIPBAC_size_b                  = 2,
5418 +       PCIPBAC_size_m                  = 0x0000007c,
5419 +       PCIPBAC_sb_b                    = 7,
5420 +       PCIPBAC_sb_m                    = 0x00000080,
5421 +       PCIPBAC_pp_b                    = 8,
5422 +       PCIPBAC_pp_m                    = 0x00000100,
5423 +       PCIPBAC_mr_b                    = 9,
5424 +       PCIPBAC_mr_m                    = 0x00000600,
5425 +       PCIPBAC_mr_read_v       =0,     //no prefetching
5426 +       PCIPBAC_mr_readLine_v   =1,
5427 +       PCIPBAC_mr_readMult_v   =2,
5428 +       PCIPBAC_mrl_b                   = 11,
5429 +       PCIPBAC_mrl_m                   = 0x00000800,
5430 +       PCIPBAC_mrm_b                   = 12,
5431 +       PCIPBAC_mrm_m                   = 0x00001000,
5432 +       PCIPBAC_trp_b                   = 13,
5433 +       PCIPBAC_trp_m                   = 0x00002000,
5434 +
5435 +       PCFG40_trdyTimeout_b            = 0,
5436 +       PCFG40_trdyTimeout_m            = 0x000000ff,
5437 +       PCFG40_retryLim_b               = 8,
5438 +       PCFG40_retryLim_m               = 0x0000ff00,
5439 +};
5440 +
5441 +/*******************************************************************************
5442 + *
5443 + * PCI Local Base Address [0|1|2|3] Register
5444 + *
5445 + ******************************************************************************/
5446 +enum {
5447 +       PCILBA_baddr_b          = 0,            // In PCI_t -> pcilba [] .a
5448 +       PCILBA_baddr_m          = 0xffffff00,
5449 +} ;
5450 +/*******************************************************************************
5451 + *
5452 + * PCI Local Base Address Control Register
5453 + *
5454 + ******************************************************************************/
5455 +enum {
5456 +       PCILBAC_msi_b           = 0,            // In pPci->pcilba[i].c
5457 +       PCILBAC_msi_m           = 0x00000001,
5458 +       PCILBAC_msi_mem_v       = 0,
5459 +       PCILBAC_msi_io_v        = 1,
5460 +       PCILBAC_size_b          = 2,    // In pPci->pcilba[i].c
5461 +       PCILBAC_size_m          = 0x0000007c,
5462 +       PCILBAC_sb_b            = 7,    // In pPci->pcilba[i].c
5463 +       PCILBAC_sb_m            = 0x00000080,
5464 +       PCILBAC_rt_b            = 8,    // In pPci->pcilba[i].c
5465 +       PCILBAC_rt_m            = 0x00000100,
5466 +       PCILBAC_rt_noprefetch_v = 0, // mem read
5467 +       PCILBAC_rt_prefetch_v   = 1, // mem readline
5468 +} ;
5469 +
5470 +/*******************************************************************************
5471 + *
5472 + * PCI Local Base Address [0|1|2|3] Mapping Register
5473 + *
5474 + ******************************************************************************/
5475 +enum {
5476 +       PCILBAM_maddr_b         = 8,
5477 +       PCILBAM_maddr_m         = 0xffffff00,
5478 +} ;
5479 +
5480 +/*******************************************************************************
5481 + *
5482 + * PCI Decoupled Access Control Register
5483 + *
5484 + ******************************************************************************/
5485 +enum {
5486 +       PCIDAC_den_b            = 0,
5487 +       PCIDAC_den_m            = 0x00000001,
5488 +} ;
5489 +
5490 +/*******************************************************************************
5491 + *
5492 + * PCI Decoupled Access Status Register
5493 + *
5494 + ******************************************************************************/
5495 +enum {
5496 +       PCIDAS_d_b      = 0,
5497 +       PCIDAS_d_m      = 0x00000001,
5498 +       PCIDAS_b_b      = 1,
5499 +       PCIDAS_b_m      = 0x00000002,
5500 +       PCIDAS_e_b      = 2,
5501 +       PCIDAS_e_m      = 0x00000004,
5502 +       PCIDAS_ofe_b    = 3,
5503 +       PCIDAS_ofe_m    = 0x00000008,
5504 +       PCIDAS_off_b    = 4,
5505 +       PCIDAS_off_m    = 0x00000010,
5506 +       PCIDAS_ife_b    = 5,
5507 +       PCIDAS_ife_m    = 0x00000020,
5508 +       PCIDAS_iff_b    = 6,
5509 +       PCIDAS_iff_m    = 0x00000040,
5510 +} ;
5511 +
5512 +/*******************************************************************************
5513 + *
5514 + * PCI DMA Channel 8 Configuration Register
5515 + *
5516 + ******************************************************************************/
5517 +enum
5518 +{
5519 +       PCIDMA8C_mbs_b  = 0,            // Maximum Burst Size.
5520 +       PCIDMA8C_mbs_m  = 0x00000fff,   // { pcidma8c }
5521 +       PCIDMA8C_our_b  = 12,           // Optimize Unaligned Burst Reads.
5522 +       PCIDMA8C_our_m  = 0x00001000,   // { pcidma8c }
5523 +} ;
5524 +
5525 +/*******************************************************************************
5526 + *
5527 + * PCI DMA Channel 9 Configuration Register
5528 + *
5529 + ******************************************************************************/
5530 +enum
5531 +{
5532 +       PCIDMA9C_mbs_b  = 0,            // Maximum Burst Size.
5533 +       PCIDMA9C_mbs_m  = 0x00000fff, // { pcidma9c }
5534 +} ;
5535 +
5536 +/*******************************************************************************
5537 + *
5538 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
5539 + *
5540 + ******************************************************************************/
5541 +enum {
5542 +       PCIDMAD_pt_b            = 22,           // in DEVCMD field (descriptor)
5543 +       PCIDMAD_pt_m            = 0x00c00000,   // preferred transaction field
5544 +       // These are for reads (DMA channel 8)
5545 +       PCIDMAD_devcmd_mr_v     = 0,    //memory read
5546 +       PCIDMAD_devcmd_mrl_v    = 1,    //memory read line
5547 +       PCIDMAD_devcmd_mrm_v    = 2,    //memory read multiple
5548 +       PCIDMAD_devcmd_ior_v    = 3,    //I/O read
5549 +       // These are for writes (DMA channel 9)
5550 +       PCIDMAD_devcmd_mw_v     = 0,    //memory write
5551 +       PCIDMAD_devcmd_mwi_v    = 1,    //memory write invalidate
5552 +       PCIDMAD_devcmd_iow_v    = 3,    //I/O write
5553 +
5554 +       // Swap byte field applies to both DMA channel 8 and 9
5555 +       PCIDMAD_sb_b            = 24,           // in DEVCMD field (descriptor)
5556 +       PCIDMAD_sb_m            = 0x01000000,   // swap byte field
5557 +} ;
5558 +
5559 +
5560 +/*******************************************************************************
5561 + *
5562 + * PCI Target Control Register
5563 + *
5564 + ******************************************************************************/
5565 +enum
5566 +{
5567 +       PCITC_rtimer_b          = 0,            // In PCITC_t -> pcitc
5568 +       PCITC_rtimer_m          = 0x000000ff,
5569 +       PCITC_dtimer_b          = 8,            // In PCITC_t -> pcitc
5570 +       PCITC_dtimer_m          = 0x0000ff00,
5571 +       PCITC_rdr_b             = 18,           // In PCITC_t -> pcitc
5572 +       PCITC_rdr_m             = 0x00040000,
5573 +       PCITC_ddt_b             = 19,           // In PCITC_t -> pcitc
5574 +       PCITC_ddt_m             = 0x00080000,
5575 +} ;
5576 +/*******************************************************************************
5577 + *
5578 + * PCI messaging unit [applies to both inbound and outbound registers ]
5579 + *
5580 + ******************************************************************************/
5581 +enum
5582 +{
5583 +       PCIM_m0_b       = 0,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5584 +       PCIM_m0_m       = 0x00000001,   // inbound or outbound message 0
5585 +       PCIM_m1_b       = 1,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5586 +       PCIM_m1_m       = 0x00000002,   // inbound or outbound message 1
5587 +       PCIM_db_b       = 2,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5588 +       PCIM_db_m       = 0x00000004,   // inbound or outbound doorbell
5589 +};
5590 +
5591 +
5592 +#endif // __IDT_RC32365_PCI_H__
5593 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h
5594 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h    1970-01-01 01:00:00.000000000 +0100
5595 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h       2006-06-18 12:44:28.000000000 +0200
5596 @@ -0,0 +1,217 @@
5597 +/**************************************************************************
5598 + *
5599 + *  BRIEF MODULE DESCRIPTION
5600 + *   PCI header values for IDT 79EB365/336
5601 + *
5602 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
5603 + *
5604 + *  This program is free software; you can redistribute  it and/or modify it
5605 + *  under  the terms of  the GNU General  Public License as published by the
5606 + *  Free Software Foundation;  either version 2 of the  License, or (at your
5607 + *  option) any later version.
5608 + *
5609 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
5610 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
5611 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
5612 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
5613 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5614 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
5615 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5616 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
5617 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5618 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5619 + *
5620 + *  You should have received a copy of the  GNU General Public License along
5621 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
5622 + *  675 Mass Ave, Cambridge, MA 02139, USA.
5623 + *
5624 + *
5625 + **************************************************************************
5626 + * May 2004 P. Sadik.
5627 + *
5628 + * Initial Release
5629 + *
5630 + *
5631 + *
5632 + **************************************************************************
5633 + */
5634 +
5635 +#ifndef __IDT_RC32365_PCI_V_H__
5636 +#define __IDT_RC32365_PCI_V_H__
5637 +
5638 +
5639 +#define PCI_MSG_VirtualAddress 0xB806C010
5640 +#define rc32365_pci ((volatile PCI_t) PCI0_VirtualAddress)
5641 +#define rc32365_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
5642 +
5643 +#define PCIM_SHFT              0x6
5644 +#define PCIM_BIT_LEN           0x7
5645 +#define PCIM_H_EA              0x3
5646 +#define PCIM_H_IA_FIX          0x4
5647 +#define PCIM_H_IA_RR           0x5
5648 +
5649 +#define PCI_ADDR_START         0x50000000
5650 +
5651 +#define CPUTOPCI_MEM_WIN       0x02000000
5652 +#define CPUTOPCI_IO_WIN                0x00100000
5653 +#define PCILBA_SIZE_SHFT       2
5654 +#define PCILBA_SIZE_MASK       0x1F
5655 +#define SIZE_256MB             0x1C
5656 +#define SIZE_128MB             0x1B
5657 +#define SIZE_64MB               0x1A
5658 +#define SIZE_32MB              0x19
5659 +#define SIZE_16MB               0x18
5660 +#define SIZE_4MB               0x16
5661 +#define SIZE_2MB               0x15
5662 +#define SIZE_1MB               0x14
5663 +#define CEDAR_CONFIG0_ADDR     0x80000000
5664 +#define CEDAR_CONFIG1_ADDR     0x80000004
5665 +#define CEDAR_CONFIG2_ADDR     0x80000008
5666 +#define CEDAR_CONFIG3_ADDR     0x8000000C
5667 +#define CEDAR_CONFIG4_ADDR     0x80000010
5668 +#define CEDAR_CONFIG5_ADDR     0x80000014
5669 +#define CEDAR_CONFIG6_ADDR     0x80000018
5670 +#define CEDAR_CONFIG7_ADDR     0x8000001C
5671 +#define CEDAR_CONFIG8_ADDR     0x80000020
5672 +#define CEDAR_CONFIG9_ADDR     0x80000024
5673 +#define CEDAR_CONFIG10_ADDR    0x80000028
5674 +#define CEDAR_CONFIG11_ADDR    0x8000002C
5675 +#define CEDAR_CONFIG12_ADDR    0x80000030
5676 +#define CEDAR_CONFIG13_ADDR    0x80000034
5677 +#define CEDAR_CONFIG14_ADDR    0x80000038
5678 +#define CEDAR_CONFIG15_ADDR    0x8000003C
5679 +#define CEDAR_CONFIG16_ADDR    0x80000040
5680 +#define CEDAR_CONFIG17_ADDR    0x80000044
5681 +#define CEDAR_CONFIG18_ADDR    0x80000048
5682 +#define CEDAR_CONFIG19_ADDR    0x8000004C
5683 +#define CEDAR_CONFIG20_ADDR    0x80000050
5684 +#define CEDAR_CONFIG21_ADDR    0x80000054
5685 +#define CEDAR_CONFIG22_ADDR    0x80000058
5686 +#define CEDAR_CONFIG23_ADDR    0x8000005C
5687 +#define CEDAR_CONFIG24_ADDR    0x80000060
5688 +#define CEDAR_CONFIG25_ADDR    0x80000064
5689 +#define CEDAR_CMD             (PCFG04_command_ioena_m  | \
5690 +                               PCFG04_command_memena_m | \
5691 +                               PCFG04_command_bmena_m  | \
5692 +                               PCFG04_command_mwinv_m  | \
5693 +                               PCFG04_command_parena_m | \
5694 +                               PCFG04_command_serrena_m )
5695 +
5696 +#define CEDAR_STAT            (PCFG04_status_mdpe_m | \
5697 +                               PCFG04_status_sta_m  | \
5698 +                               PCFG04_status_rta_m  | \
5699 +                               PCFG04_status_rma_m  | \
5700 +                               PCFG04_status_sse_m  | \
5701 +                               PCFG04_status_pe_m)
5702 +
5703 +#define CEDAR_CNFG1          ((CEDAR_STAT << 16) | \
5704 +                                CEDAR_CMD)
5705 +
5706 +#define CEDAR_REVID            0
5707 +#define CEDAR_CLASS_CODE       0
5708 +#define CEDAR_CNFG2          ((CEDAR_CLASS_CODE << 8) | \
5709 +                               CEDAR_REVID)
5710 +
5711 +#define CEDAR_CACHE_LINE_SIZE  4
5712 +#define CEDAR_MASTER_LAT       0x3c
5713 +#define CEDAR_HEADER_TYPE      0
5714 +#define CEDAR_BIST             0
5715 +
5716 +#define CEDAR_CNFG3           ((CEDAR_BIST        << 24) | \
5717 +                              (CEDAR_HEADER_TYPE << 16) | \
5718 +                              (CEDAR_MASTER_LAT  <<  8) | \
5719 +                               CEDAR_CACHE_LINE_SIZE)
5720 +
5721 +#define CEDAR_BAR0             0x00000008 /* 128 MB Memory */
5722 +#define CEDAR_BAR1             0x18800001 /* 1 MB IO */
5723 +#define CEDAR_BAR2             0x18000001 /* 2 MB IO window for Cedar
5724 +                                             internal Registers */
5725 +#define CEDAR_BAR3             0x48000008 /* Spare 128 MB Memory */
5726 +
5727 +#define CEDAR_CNFG4            CEDAR_BAR0
5728 +#define CEDAR_CNFG5             CEDAR_BAR1
5729 +#define CEDAR_CNFG6            CEDAR_BAR2
5730 +#define CEDAR_CNFG7            CEDAR_BAR3
5731 +
5732 +#define CEDAR_SUBSYS_VENDOR_ID  0
5733 +#define CEDAR_SUBSYSTEM_ID     0
5734 +#define CEDAR_CNFG8            0
5735 +#define CEDAR_CNFG9            0
5736 +#define CEDAR_CNFG10           0
5737 +#define CEDAR_CNFG11         ((CEDAR_SUBSYS_VENDOR_ID << 16) | \
5738 +                               CEDAR_SUBSYSTEM_ID)
5739 +#define CEDAR_INT_LINE         1
5740 +#define CEDAR_INT_PIN          1
5741 +#define CEDAR_MIN_GNT          8
5742 +#define CEDAR_MAX_LAT          0x38
5743 +#define CEDAR_CNFG12           0
5744 +#define CEDAR_CNFG13           0
5745 +#define CEDAR_CNFG14           0
5746 +#define CEDAR_CNFG15         ((CEDAR_MAX_LAT << 24) | \
5747 +                              (CEDAR_MIN_GNT << 16) | \
5748 +                              (CEDAR_INT_PIN <<  8) | \
5749 +                               CEDAR_INT_LINE)
5750 +#define        CEDAR_RETRY_LIMIT       0x80
5751 +#define CEDAR_TRDY_LIMIT       0x80
5752 +#define CEDAR_CNFG16          ((CEDAR_RETRY_LIMIT << 8) | \
5753 +                               CEDAR_TRDY_LIMIT)
5754 +#define PCI_PBAxC_R            0x0
5755 +#define PCI_PBAxC_RL           0x1
5756 +#define PCI_PBAxC_RM           0x2
5757 +#define SIZE_SHFT              2
5758 +#ifdef __MIPSEB__
5759 +#define CEDAR_PBA0C           (((1 & 0x3) << PCIPBAC_mr_b) | \
5760 +                               PCIPBAC_pp_m | \
5761 +                               PCIPBAC_sb_m | \
5762 +                              (SIZE_128MB << SIZE_SHFT) | \
5763 +                               PCIPBAC_p_m)
5764 +#else
5765 +
5766 +#define CEDAR_PBA0C           (((1 & 0x3) << PCIPBAC_mr_b) | \
5767 +                               PCIPBAC_pp_m | \
5768 +                              (SIZE_128MB << SIZE_SHFT) | \
5769 +                               PCIPBAC_p_m)
5770 +#endif
5771 +#define CEDAR_CNFG17           CEDAR_PBA0C
5772 +#define CEDAR_PBA0M            0x0
5773 +#define CEDAR_CNFG18           CEDAR_PBA0M
5774 +
5775 +#ifdef __MIPSEB__
5776 +#define CEDAR_PBA1C          ((SIZE_1MB << SIZE_SHFT) | \
5777 +                               PCIPBAC_sb_m | \
5778 +                               PCIPBAC_msi_m)
5779 +#else
5780 +#define CEDAR_PBA1C          ((SIZE_1MB << SIZE_SHFT) | \
5781 +                               PCIPBAC_msi_m)
5782 +#endif
5783 +#define CEDAR_CNFG19           CEDAR_PBA1C
5784 +#define CEDAR_PBA1M            0x0
5785 +#define CEDAR_CNFG20           CEDAR_PBA1M
5786 +
5787 +#ifdef __MIPSEB__
5788 +#define CEDAR_PBA2C          ((SIZE_2MB << SIZE_SHFT) |  \
5789 +                               PCIPBAC_sb_m | \
5790 +                               PCIPBAC_msi_m)
5791 +#else
5792 +#define CEDAR_PBA2C          ((SIZE_2MB << SIZE_SHFT) |  \
5793 +                               PCIPBAC_msi_m)
5794 +#endif
5795 +
5796 +#define CEDAR_CNFG21           CEDAR_PBA2C
5797 +#define CEDAR_PBA2M            0x18000000
5798 +#define CEDAR_CNFG22           CEDAR_PBA2M
5799 +
5800 +#ifdef __MIPSEB__
5801 +#define CEDAR_PBA3C            PCIPBAC_sb_m
5802 +#else
5803 +#define CEDAR_PBA3C            0
5804 +#endif
5805 +
5806 +#define CEDAR_CNFG23           CEDAR_PBA3C
5807 +#define CEDAR_PBA3M            0
5808 +#define CEDAR_CNFG24           CEDAR_PBA3M
5809 +
5810 +#define        PCITC_DTIMER_VAL        8
5811 +#define PCITC_RTIMER_VAL       0x10
5812 +
5813 +#endif //__IDT_RC32365_PCI_V_H__
5814 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h
5815 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma.h      1970-01-01 01:00:00.000000000 +0100
5816 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 2006-06-18 12:44:28.000000000 +0200
5817 @@ -0,0 +1,205 @@
5818 +/**************************************************************************
5819 + *
5820 + *  BRIEF MODULE DESCRIPTION
5821 + *   DMA register definition
5822 + *
5823 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
5824 + *
5825 + *  This program is free software; you can redistribute  it and/or modify it
5826 + *  under  the terms of  the GNU General  Public License as published by the
5827 + *  Free Software Foundation;  either version 2 of the  License, or (at your
5828 + *  option) any later version.
5829 + *
5830 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
5831 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
5832 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
5833 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
5834 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5835 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
5836 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5837 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
5838 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5839 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5840 + *
5841 + *  You should have received a copy of the  GNU General Public License along
5842 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
5843 + *  675 Mass Ave, Cambridge, MA 02139, USA.
5844 + *
5845 + *
5846 + **************************************************************************
5847 + * May 2004 rkt, neb
5848 + *
5849 + * Initial Release
5850 + *
5851 + *
5852 + *
5853 + **************************************************************************
5854 + */
5855 +
5856 +#ifndef __IDT_DMA_H__
5857 +#define __IDT_DMA_H__
5858 +
5859 +enum
5860 +{
5861 +       DMA0_PhysicalAddress    = 0x18040000,
5862 +       DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
5863 +
5864 +       DMA0_VirtualAddress     = 0xb8040000,
5865 +       DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
5866 +} ;
5867 +
5868 +/*
5869 + * DMA descriptor (in physical memory).
5870 + */
5871 +
5872 +typedef struct DMAD_s
5873 +{
5874 +       u32                     control ;       // Control. use DMAD_*
5875 +       u32                     ca ;            // Current Address.
5876 +       u32                     devcs ;         // Device control and status.
5877 +       u32                     link ;          // Next descriptor in chain.
5878 +} volatile *DMAD_t ;
5879 +
5880 +enum
5881 +{
5882 +       DMAD_size               = sizeof (struct DMAD_s),
5883 +       DMAD_count_b            = 0,            // in DMAD_t -> control
5884 +       DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
5885 +       DMAD_ds_b               = 20,           // in DMAD_t -> control
5886 +       DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
5887 +               DMAD_ds_ethRcv0_v       = 0,
5888 +               DMAD_ds_ethXmt0_v       = 0,
5889 +               DMAD_ds_memToFifo_v     = 0,
5890 +               DMAD_ds_fifoToMem_v     = 0,
5891 +               DMAD_ds_pciToMem_v      = 0,
5892 +               DMAD_ds_memToPci_v      = 0,
5893 +
5894 +       DMAD_devcmd_b           = 22,           // in DMAD_t -> control
5895 +       DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
5896 +               DMAD_devcmd_byte_v      = 0,    //memory-to-memory
5897 +               DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
5898 +               DMAD_devcmd_word_v      = 2,    //memory-to-memory
5899 +               DMAD_devcmd_2words_v    = 3,    //memory-to-memory
5900 +               DMAD_devcmd_4words_v    = 4,    //memory-to-memory
5901 +               DMAD_devcmd_6words_v    = 5,    //memory-to-memory
5902 +               DMAD_devcmd_8words_v    = 6,    //memory-to-memory
5903 +               DMAD_devcmd_16words_v   = 7,    //memory-to-memory
5904 +       DMAD_cof_b              = 25,           // chain on finished
5905 +       DMAD_cof_m              = 0x02000000,   //
5906 +       DMAD_cod_b              = 26,           // chain on done
5907 +       DMAD_cod_m              = 0x04000000,   //
5908 +       DMAD_iof_b              = 27,           // interrupt on finished
5909 +       DMAD_iof_m              = 0x08000000,   //
5910 +       DMAD_iod_b              = 28,           // interrupt on done
5911 +       DMAD_iod_m              = 0x10000000,   //
5912 +       DMAD_t_b                = 29,           // terminated
5913 +       DMAD_t_m                = 0x20000000,   //
5914 +       DMAD_d_b                = 30,           // done
5915 +       DMAD_d_m                = 0x40000000,   //
5916 +       DMAD_f_b                = 31,           // finished
5917 +       DMAD_f_m                = 0x80000000,   //
5918 +} ;
5919 +
5920 +/*
5921 + * DMA register (within Internal Register Map).
5922 + */
5923 +
5924 +struct DMA_Chan_s
5925 +{
5926 +       u32             dmac ;          // Control.
5927 +       u32             dmas ;          // Status.
5928 +       u32             dmasm ;         // Mask.
5929 +       u32             dmadptr ;       // Descriptor pointer.
5930 +       u32             dmandptr ;      // Next descriptor pointer.
5931 +};
5932 +
5933 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
5934 +
5935 +//DMA_Channels   use DMACH_count instead
5936 +
5937 +enum
5938 +{
5939 +       DMAC_run_b      = 0,            //
5940 +       DMAC_run_m      = 0x00000001,   //
5941 +       DMAC_dm_b       = 1,            // done mask
5942 +       DMAC_dm_m       = 0x00000002,   //
5943 +       DMAC_mode_b     = 2,            //
5944 +       DMAC_mode_m     = 0x0000000c,   //
5945 +               DMAC_mode_auto_v        = 0,
5946 +               DMAC_mode_burst_v       = 1,
5947 +               DMAC_mode_transfer_v    = 2, //usually used
5948 +               DMAC_mode_reserved_v    = 3,
5949 +       DMAC_a_b        = 4,            //
5950 +       DMAC_a_m        = 0x00000010,   //
5951 +
5952 +       DMAS_f_b        = 0,            // finished (sticky)
5953 +       DMAS_f_m        = 0x00000001,   //
5954 +       DMAS_d_b        = 1,            // done (sticky)
5955 +       DMAS_d_m        = 0x00000002,   //
5956 +       DMAS_c_b        = 2,            // chain (sticky)
5957 +       DMAS_c_m        = 0x00000004,   //
5958 +       DMAS_e_b        = 3,            // error (sticky)
5959 +       DMAS_e_m        = 0x00000008,   //
5960 +       DMAS_h_b        = 4,            // halt (sticky)
5961 +       DMAS_h_m        = 0x00000010,   //
5962 +
5963 +       DMASM_f_b       = 0,            // finished (1=mask)
5964 +       DMASM_f_m       = 0x00000001,   //
5965 +       DMASM_d_b       = 1,            // done (1=mask)
5966 +       DMASM_d_m       = 0x00000002,   //
5967 +       DMASM_c_b       = 2,            // chain (1=mask)
5968 +       DMASM_c_m       = 0x00000004,   //
5969 +       DMASM_e_b       = 3,            // error (1=mask)
5970 +       DMASM_e_m       = 0x00000008,   //
5971 +       DMASM_h_b       = 4,            // halt (1=mask)
5972 +       DMASM_h_m       = 0x00000010,   //
5973 +} ;
5974 +
5975 +/*
5976 + * DMA channel definitions
5977 + */
5978 +
5979 +enum
5980 +{
5981 +       DMACH_ethRcv0 = 0,
5982 +       DMACH_ethXmt0 = 1,
5983 +       DMACH_memToFifo = 2,
5984 +       DMACH_fifoToMem = 3,
5985 +       DMACH_pciToMem = 4,
5986 +       DMACH_memToPci = 5,
5987 +
5988 +       DMACH_count //must be last
5989 +};
5990 +
5991 +
5992 +typedef struct DMAC_s
5993 +{
5994 +       struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
5995 +} volatile *DMA_t ;
5996 +
5997 +
5998 +/*
5999 + * External DMA parameters
6000 +*/
6001 +
6002 +enum
6003 +{
6004 +       DMADEVCMD_ts_b  = 0,            // ts field in devcmd
6005 +       DMADEVCMD_ts_m  = 0x00000007,   // ts field in devcmd
6006 +               DMADEVCMD_ts_byte_v     = 0,
6007 +               DMADEVCMD_ts_halfword_v = 1,
6008 +               DMADEVCMD_ts_word_v     = 2,
6009 +               DMADEVCMD_ts_2word_v    = 3,
6010 +               DMADEVCMD_ts_4word_v    = 4,
6011 +               DMADEVCMD_ts_6word_v    = 5,
6012 +               DMADEVCMD_ts_8word_v    = 6,
6013 +               DMADEVCMD_ts_16word_v   = 7
6014 +};
6015 +
6016 +
6017 +#endif // __IDT_DMA_H__
6018 +
6019 +
6020 +
6021 +
6022 +
6023 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h
6024 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h    1970-01-01 01:00:00.000000000 +0100
6025 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h       2006-06-18 12:44:28.000000000 +0200
6026 @@ -0,0 +1,89 @@
6027 +/**************************************************************************
6028 + *
6029 + *  BRIEF MODULE DESCRIPTION
6030 + *   Definitions for DMA controller.
6031 + *
6032 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6033 + *
6034 + *  This program is free software; you can redistribute  it and/or modify it
6035 + *  under  the terms of  the GNU General  Public License as published by the
6036 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6037 + *  option) any later version.
6038 + *
6039 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6040 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6041 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6042 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6043 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6044 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6045 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6046 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6047 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6048 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6049 + *
6050 + *  You should have received a copy of the  GNU General Public License along
6051 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6052 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6053 + *
6054 + *
6055 + **************************************************************************
6056 + * May 2004 rkt, neb.
6057 + *
6058 + * Initial Release
6059 + *
6060 + *
6061 + *
6062 + **************************************************************************
6063 + */
6064 +
6065 +#ifndef __IDT_DMA_V_H__
6066 +#define __IDT_DMA_V_H__
6067 +
6068 +#include  <asm/idt-boards/rc32434/rc32434_dma.h>
6069 +#include  <asm/idt-boards/rc32434/rc32434.h>
6070 +
6071 +#define DMA_CHAN_OFFSET  0x14
6072 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
6073 +#define DMA_COUNT(count)   \
6074 +  ((count) & DMAD_count_m)
6075 +
6076 +#define DMA_HALT_TIMEOUT 500
6077 +
6078 +
6079 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
6080 +{
6081 +       int timeout=1;
6082 +       if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
6083 +               rc32434_writel(0, &ch->dmac);
6084 +
6085 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
6086 +                       if (rc32434_readl(&ch->dmas) & DMAS_h_m) {
6087 +                               rc32434_writel(0, &ch->dmas);
6088 +                               break;
6089 +                       }
6090 +               }
6091 +
6092 +       }
6093 +
6094 +       return timeout ? 0 : 1;
6095 +}
6096 +
6097 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
6098 +{
6099 +       rc32434_writel(0, &ch->dmandptr);
6100 +       rc32434_writel(dma_addr, &ch->dmadptr);
6101 +}
6102 +
6103 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
6104 +{
6105 +       rc32434_writel(dma_addr, &ch->dmandptr);
6106 +}
6107 +
6108 +#endif // __IDT_DMA_V_H__
6109 +
6110 +
6111 +
6112 +
6113 +
6114 +
6115 +
6116 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h
6117 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth.h      1970-01-01 01:00:00.000000000 +0100
6118 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 2006-06-18 12:44:28.000000000 +0200
6119 @@ -0,0 +1,333 @@
6120 +/**************************************************************************
6121 + *
6122 + *  BRIEF MODULE DESCRIPTION
6123 + *   Ethernet register definition
6124 + *
6125 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6126 + *
6127 + *  This program is free software; you can redistribute  it and/or modify it
6128 + *  under  the terms of  the GNU General  Public License as published by the
6129 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6130 + *  option) any later version.
6131 + *
6132 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6133 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6134 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6135 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6136 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6137 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6138 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6139 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6140 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6141 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6142 + *
6143 + *  You should have received a copy of the  GNU General Public License along
6144 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6145 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6146 + *
6147 + *
6148 + **************************************************************************
6149 + * May 2004 rkt, neb.
6150 + *
6151 + * Initial Release
6152 + *
6153 + *
6154 + *
6155 + **************************************************************************
6156 + */
6157 +
6158 +#ifndef        __IDT_ETH_H__
6159 +#define        __IDT_ETH_H__
6160 +
6161 +
6162 +enum
6163 +{
6164 +       ETH0_PhysicalAddress    = 0x18060000,
6165 +       ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
6166 +
6167 +       ETH0_VirtualAddress     = 0xb8060000,
6168 +       ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
6169 +} ;
6170 +
6171 +typedef struct
6172 +{
6173 +       u32 ethintfc            ;
6174 +       u32 ethfifott           ;
6175 +       u32 etharc              ;
6176 +       u32 ethhash0            ;
6177 +       u32 ethhash1            ;
6178 +       u32 ethu0 [4]           ;       // Reserved.
6179 +       u32 ethpfs              ;
6180 +       u32 ethmcp              ;
6181 +       u32 eth_u1 [10]         ;       // Reserved.
6182 +       u32 ethspare            ;
6183 +       u32 eth_u2 [42]         ;       // Reserved.
6184 +       u32 ethsal0             ;
6185 +       u32 ethsah0             ;
6186 +       u32 ethsal1             ;
6187 +       u32 ethsah1             ;
6188 +       u32 ethsal2             ;
6189 +       u32 ethsah2             ;
6190 +       u32 ethsal3             ;
6191 +       u32 ethsah3             ;
6192 +       u32 ethrbc              ;
6193 +       u32 ethrpc              ;
6194 +       u32 ethrupc             ;
6195 +       u32 ethrfc              ;
6196 +       u32 ethtbc              ;
6197 +       u32 ethgpf              ;
6198 +       u32 eth_u9 [50]         ;       // Reserved.
6199 +       u32 ethmac1             ;
6200 +       u32 ethmac2             ;
6201 +       u32 ethipgt             ;
6202 +       u32 ethipgr             ;
6203 +       u32 ethclrt             ;
6204 +       u32 ethmaxf             ;
6205 +       u32 eth_u10             ;       // Reserved.
6206 +       u32 ethmtest            ;
6207 +       u32 miimcfg             ;
6208 +       u32 miimcmd             ;
6209 +       u32 miimaddr            ;
6210 +       u32 miimwtd             ;
6211 +       u32 miimrdd             ;
6212 +       u32 miimind             ;
6213 +       u32 eth_u11             ;       // Reserved.
6214 +       u32 eth_u12             ;       // Reserved.
6215 +       u32 ethcfsa0            ;
6216 +       u32 ethcfsa1            ;
6217 +       u32 ethcfsa2            ;
6218 +} volatile *ETH_t;
6219 +
6220 +enum
6221 +{
6222 +       ETHINTFC_en_b           = 0,
6223 +       ETHINTFC_en_m           = 0x00000001,
6224 +       ETHINTFC_its_b          = 1,
6225 +       ETHINTFC_its_m          = 0x00000002,
6226 +       ETHINTFC_rip_b          = 2,
6227 +       ETHINTFC_rip_m          = 0x00000004,
6228 +       ETHINTFC_jam_b          = 3,
6229 +       ETHINTFC_jam_m          = 0x00000008,
6230 +       ETHINTFC_ovr_b          = 4,
6231 +       ETHINTFC_ovr_m          = 0x00000010,
6232 +       ETHINTFC_und_b          = 5,
6233 +       ETHINTFC_und_m          = 0x00000020,
6234 +
6235 +       ETHFIFOTT_tth_b         = 0,
6236 +       ETHFIFOTT_tth_m         = 0x0000007f,
6237 +
6238 +       ETHARC_pro_b            = 0,
6239 +       ETHARC_pro_m            = 0x00000001,
6240 +       ETHARC_am_b             = 1,
6241 +       ETHARC_am_m             = 0x00000002,
6242 +       ETHARC_afm_b            = 2,
6243 +       ETHARC_afm_m            = 0x00000004,
6244 +       ETHARC_ab_b             = 3,
6245 +       ETHARC_ab_m             = 0x00000008,
6246 +
6247 +       ETHSAL_byte5_b          = 0,
6248 +       ETHSAL_byte5_m          = 0x000000ff,
6249 +       ETHSAL_byte4_b          = 8,
6250 +       ETHSAL_byte4_m          = 0x0000ff00,
6251 +       ETHSAL_byte3_b          = 16,
6252 +       ETHSAL_byte3_m          = 0x00ff0000,
6253 +       ETHSAL_byte2_b          = 24,
6254 +       ETHSAL_byte2_m          = 0xff000000,
6255 +
6256 +       ETHSAH_byte1_b          = 0,
6257 +       ETHSAH_byte1_m          = 0x000000ff,
6258 +       ETHSAH_byte0_b          = 8,
6259 +       ETHSAH_byte0_m          = 0x0000ff00,
6260 +
6261 +       ETHGPF_ptv_b            = 0,
6262 +       ETHGPF_ptv_m            = 0x0000ffff,
6263 +
6264 +       ETHPFS_pfd_b            = 0,
6265 +       ETHPFS_pfd_m            = 0x00000001,
6266 +
6267 +       ETHCFSA0_cfsa4_b        = 0,
6268 +       ETHCFSA0_cfsa4_m        = 0x000000ff,
6269 +       ETHCFSA0_cfsa5_b        = 8,
6270 +       ETHCFSA0_cfsa5_m        = 0x0000ff00,
6271 +
6272 +       ETHCFSA1_cfsa2_b        = 0,
6273 +       ETHCFSA1_cfsa2_m        = 0x000000ff,
6274 +       ETHCFSA1_cfsa3_b        = 8,
6275 +       ETHCFSA1_cfsa3_m        = 0x0000ff00,
6276 +
6277 +       ETHCFSA2_cfsa0_b        = 0,
6278 +       ETHCFSA2_cfsa0_m        = 0x000000ff,
6279 +       ETHCFSA2_cfsa1_b        = 8,
6280 +       ETHCFSA2_cfsa1_m        = 0x0000ff00,
6281 +
6282 +       ETHMAC1_re_b            = 0,
6283 +       ETHMAC1_re_m            = 0x00000001,
6284 +       ETHMAC1_paf_b           = 1,
6285 +       ETHMAC1_paf_m           = 0x00000002,
6286 +       ETHMAC1_rfc_b           = 2,
6287 +       ETHMAC1_rfc_m           = 0x00000004,
6288 +       ETHMAC1_tfc_b           = 3,
6289 +       ETHMAC1_tfc_m           = 0x00000008,
6290 +       ETHMAC1_lb_b            = 4,
6291 +       ETHMAC1_lb_m            = 0x00000010,
6292 +       ETHMAC1_mr_b            = 31,
6293 +       ETHMAC1_mr_m            = 0x80000000,
6294 +
6295 +       ETHMAC2_fd_b            = 0,
6296 +       ETHMAC2_fd_m            = 0x00000001,
6297 +       ETHMAC2_flc_b           = 1,
6298 +       ETHMAC2_flc_m           = 0x00000002,
6299 +       ETHMAC2_hfe_b           = 2,
6300 +       ETHMAC2_hfe_m           = 0x00000004,
6301 +       ETHMAC2_dc_b            = 3,
6302 +       ETHMAC2_dc_m            = 0x00000008,
6303 +       ETHMAC2_cen_b           = 4,
6304 +       ETHMAC2_cen_m           = 0x00000010,
6305 +       ETHMAC2_pe_b            = 5,
6306 +       ETHMAC2_pe_m            = 0x00000020,
6307 +       ETHMAC2_vpe_b           = 6,
6308 +       ETHMAC2_vpe_m           = 0x00000040,
6309 +       ETHMAC2_ape_b           = 7,
6310 +       ETHMAC2_ape_m           = 0x00000080,
6311 +       ETHMAC2_ppe_b           = 8,
6312 +       ETHMAC2_ppe_m           = 0x00000100,
6313 +       ETHMAC2_lpe_b           = 9,
6314 +       ETHMAC2_lpe_m           = 0x00000200,
6315 +       ETHMAC2_nb_b            = 12,
6316 +       ETHMAC2_nb_m            = 0x00001000,
6317 +       ETHMAC2_bp_b            = 13,
6318 +       ETHMAC2_bp_m            = 0x00002000,
6319 +       ETHMAC2_ed_b            = 14,
6320 +       ETHMAC2_ed_m            = 0x00004000,
6321 +
6322 +       ETHIPGT_ipgt_b          = 0,
6323 +       ETHIPGT_ipgt_m          = 0x0000007f,
6324 +
6325 +       ETHIPGR_ipgr2_b         = 0,
6326 +       ETHIPGR_ipgr2_m         = 0x0000007f,
6327 +       ETHIPGR_ipgr1_b         = 8,
6328 +       ETHIPGR_ipgr1_m         = 0x00007f00,
6329 +
6330 +       ETHCLRT_maxret_b        = 0,
6331 +       ETHCLRT_maxret_m        = 0x0000000f,
6332 +       ETHCLRT_colwin_b        = 8,
6333 +       ETHCLRT_colwin_m        = 0x00003f00,
6334 +
6335 +       ETHMAXF_maxf_b          = 0,
6336 +       ETHMAXF_maxf_m          = 0x0000ffff,
6337 +
6338 +       ETHMTEST_tb_b           = 2,
6339 +       ETHMTEST_tb_m           = 0x00000004,
6340 +
6341 +       ETHMCP_div_b            = 0,
6342 +       ETHMCP_div_m            = 0x000000ff,
6343 +
6344 +       MIIMCFG_rsv_b           = 0,
6345 +       MIIMCFG_rsv_m           = 0x0000000c,
6346 +
6347 +       MIIMCMD_rd_b            = 0,
6348 +       MIIMCMD_rd_m            = 0x00000001,
6349 +       MIIMCMD_scn_b           = 1,
6350 +       MIIMCMD_scn_m           = 0x00000002,
6351 +
6352 +       MIIMADDR_regaddr_b      = 0,
6353 +       MIIMADDR_regaddr_m      = 0x0000001f,
6354 +       MIIMADDR_phyaddr_b      = 8,
6355 +       MIIMADDR_phyaddr_m      = 0x00001f00,
6356 +
6357 +       MIIMWTD_wdata_b         = 0,
6358 +       MIIMWTD_wdata_m         = 0x0000ffff,
6359 +
6360 +       MIIMRDD_rdata_b         = 0,
6361 +       MIIMRDD_rdata_m         = 0x0000ffff,
6362 +
6363 +       MIIMIND_bsy_b           = 0,
6364 +       MIIMIND_bsy_m           = 0x00000001,
6365 +       MIIMIND_scn_b           = 1,
6366 +       MIIMIND_scn_m           = 0x00000002,
6367 +       MIIMIND_nv_b            = 2,
6368 +       MIIMIND_nv_m            = 0x00000004,
6369 +
6370 +} ;
6371 +
6372 +/*
6373 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
6374 + */
6375 +enum
6376 +{
6377 +       ETHRX_fd_b              = 0,
6378 +       ETHRX_fd_m              = 0x00000001,
6379 +       ETHRX_ld_b              = 1,
6380 +       ETHRX_ld_m              = 0x00000002,
6381 +       ETHRX_rok_b             = 2,
6382 +       ETHRX_rok_m             = 0x00000004,
6383 +       ETHRX_fm_b              = 3,
6384 +       ETHRX_fm_m              = 0x00000008,
6385 +       ETHRX_mp_b              = 4,
6386 +       ETHRX_mp_m              = 0x00000010,
6387 +       ETHRX_bp_b              = 5,
6388 +       ETHRX_bp_m              = 0x00000020,
6389 +       ETHRX_vlt_b             = 6,
6390 +       ETHRX_vlt_m             = 0x00000040,
6391 +       ETHRX_cf_b              = 7,
6392 +       ETHRX_cf_m              = 0x00000080,
6393 +       ETHRX_ovr_b             = 8,
6394 +       ETHRX_ovr_m             = 0x00000100,
6395 +       ETHRX_crc_b             = 9,
6396 +       ETHRX_crc_m             = 0x00000200,
6397 +       ETHRX_cv_b              = 10,
6398 +       ETHRX_cv_m              = 0x00000400,
6399 +       ETHRX_db_b              = 11,
6400 +       ETHRX_db_m              = 0x00000800,
6401 +       ETHRX_le_b              = 12,
6402 +       ETHRX_le_m              = 0x00001000,
6403 +       ETHRX_lor_b             = 13,
6404 +       ETHRX_lor_m             = 0x00002000,
6405 +       ETHRX_ces_b             = 14,
6406 +       ETHRX_ces_m             = 0x00004000,
6407 +       ETHRX_length_b          = 16,
6408 +       ETHRX_length_m          = 0xffff0000,
6409 +
6410 +       ETHTX_fd_b              = 0,
6411 +       ETHTX_fd_m              = 0x00000001,
6412 +       ETHTX_ld_b              = 1,
6413 +       ETHTX_ld_m              = 0x00000002,
6414 +       ETHTX_oen_b             = 2,
6415 +       ETHTX_oen_m             = 0x00000004,
6416 +       ETHTX_pen_b             = 3,
6417 +       ETHTX_pen_m             = 0x00000008,
6418 +       ETHTX_cen_b             = 4,
6419 +       ETHTX_cen_m             = 0x00000010,
6420 +       ETHTX_hen_b             = 5,
6421 +       ETHTX_hen_m             = 0x00000020,
6422 +       ETHTX_tok_b             = 6,
6423 +       ETHTX_tok_m             = 0x00000040,
6424 +       ETHTX_mp_b              = 7,
6425 +       ETHTX_mp_m              = 0x00000080,
6426 +       ETHTX_bp_b              = 8,
6427 +       ETHTX_bp_m              = 0x00000100,
6428 +       ETHTX_und_b             = 9,
6429 +       ETHTX_und_m             = 0x00000200,
6430 +       ETHTX_of_b              = 10,
6431 +       ETHTX_of_m              = 0x00000400,
6432 +       ETHTX_ed_b              = 11,
6433 +       ETHTX_ed_m              = 0x00000800,
6434 +       ETHTX_ec_b              = 12,
6435 +       ETHTX_ec_m              = 0x00001000,
6436 +       ETHTX_lc_b              = 13,
6437 +       ETHTX_lc_m              = 0x00002000,
6438 +       ETHTX_td_b              = 14,
6439 +       ETHTX_td_m              = 0x00004000,
6440 +       ETHTX_crc_b             = 15,
6441 +       ETHTX_crc_m             = 0x00008000,
6442 +       ETHTX_le_b              = 16,
6443 +       ETHTX_le_m              = 0x00010000,
6444 +       ETHTX_cc_b              = 17,
6445 +       ETHTX_cc_m              = 0x001E0000,
6446 +} ;
6447 +
6448 +#endif // __IDT_ETH_H__
6449 +
6450 +
6451 +
6452 +
6453 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h
6454 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h    1970-01-01 01:00:00.000000000 +0100
6455 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h       2006-06-18 12:44:28.000000000 +0200
6456 @@ -0,0 +1,77 @@
6457 +/**************************************************************************
6458 + *
6459 + *  BRIEF MODULE DESCRIPTION
6460 + *   Ethernet register definition
6461 + *
6462 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6463 + *
6464 + *  This program is free software; you can redistribute  it and/or modify it
6465 + *  under  the terms of  the GNU General  Public License as published by the
6466 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6467 + *  option) any later version.
6468 + *
6469 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6470 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6471 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6472 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6473 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6474 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6475 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6476 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6477 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6478 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6479 + *
6480 + *  You should have received a copy of the  GNU General Public License along
6481 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6482 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6483 + *
6484 + *
6485 + **************************************************************************
6486 + * May 2004 rkt, neb.
6487 + *
6488 + * Initial Release
6489 + *
6490 + *
6491 + *
6492 + **************************************************************************
6493 + */
6494 +
6495 +#ifndef        __IDT_ETH_V_H__
6496 +#define        __IDT_ETH_V_H__
6497 +
6498 +#include  <asm/idt-boards/rc32434/rc32434_eth.h>
6499 +
6500 +#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
6501 +#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
6502 +#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
6503 +#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
6504 +#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
6505 +#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
6506 +#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
6507 +#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
6508 +#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
6509 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
6510 +#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
6511 +
6512 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
6513 +
6514 +#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
6515 +#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
6516 +#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
6517 +#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
6518 +#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
6519 +#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
6520 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
6521 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
6522 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
6523 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
6524 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
6525 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
6526 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
6527 +#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
6528 +#endif // __IDT_ETH_V_H__
6529 +
6530 +
6531 +
6532 +
6533 +
6534 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h
6535 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h     1970-01-01 01:00:00.000000000 +0100
6536 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h        2006-06-18 12:44:28.000000000 +0200
6537 @@ -0,0 +1,167 @@
6538 +/**************************************************************************
6539 + *
6540 + *  BRIEF MODULE DESCRIPTION
6541 + *   GPIO register definition
6542 + *
6543 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6544 + *
6545 + *  This program is free software; you can redistribute  it and/or modify it
6546 + *  under  the terms of  the GNU General  Public License as published by the
6547 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6548 + *  option) any later version.
6549 + *
6550 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6551 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6552 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6553 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6554 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6555 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6556 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6557 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6558 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6559 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6560 + *
6561 + *  You should have received a copy of the  GNU General Public License along
6562 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6563 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6564 + *
6565 + *
6566 + **************************************************************************
6567 + * May 2004 rkt, neb.
6568 + *
6569 + * Initial Release
6570 + *
6571 + *
6572 + *
6573 + **************************************************************************
6574 + */
6575 +
6576 +#ifndef __IDT_GPIO_H__
6577 +#define __IDT_GPIO_H__
6578 +
6579 +enum
6580 +{
6581 +       GPIO0_PhysicalAddress   = 0x18050000,
6582 +       GPIO_PhysicalAddress    = GPIO0_PhysicalAddress,        // Default
6583 +
6584 +       GPIO0_VirtualAddress    = 0xb8050000,
6585 +       GPIO_VirtualAddress     = GPIO0_VirtualAddress,         // Default
6586 +} ;
6587 +
6588 +typedef struct
6589 +{
6590 +       u32   gpiofunc;   /* GPIO Function Register
6591 +                          * gpiofunc[x]==0 bit = gpio
6592 +                          * func[x]==1  bit = altfunc
6593 +                          */
6594 +       u32   gpiocfg;    /* GPIO Configuration Register
6595 +                          * gpiocfg[x]==0 bit = input
6596 +                          * gpiocfg[x]==1 bit = output
6597 +                          */
6598 +       u32   gpiod;      /* GPIO Data Register
6599 +                          * gpiod[x] read/write gpio pinX status
6600 +                          */
6601 +       u32   gpioilevel; /* GPIO Interrupt Status Register
6602 +                          * interrupt level (see gpioistat)
6603 +                          */
6604 +       u32   gpioistat;  /* Gpio Interrupt Status Register
6605 +                          * istat[x] = (gpiod[x] == level[x])
6606 +                          * cleared in ISR (STICKY bits)
6607 +                          */
6608 +       u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
6609 +} volatile * GPIO_t ;
6610 +
6611 +typedef enum
6612 +{
6613 +       GPIO_gpio_v             = 0,            // gpiofunc use pin as GPIO.
6614 +       GPIO_alt_v              = 1,            // gpiofunc use pin as alt.
6615 +       GPIO_input_v            = 0,            // gpiocfg use pin as input.
6616 +       GPIO_output_v           = 1,            // gpiocfg use pin as output.
6617 +       GPIO_pin0_b             = 0,
6618 +       GPIO_pin0_m             = 0x00000001,
6619 +       GPIO_pin1_b             = 1,
6620 +       GPIO_pin1_m             = 0x00000002,
6621 +       GPIO_pin2_b             = 2,
6622 +       GPIO_pin2_m             = 0x00000004,
6623 +       GPIO_pin3_b             = 3,
6624 +       GPIO_pin3_m             = 0x00000008,
6625 +       GPIO_pin4_b             = 4,
6626 +       GPIO_pin4_m             = 0x00000010,
6627 +       GPIO_pin5_b             = 5,
6628 +       GPIO_pin5_m             = 0x00000020,
6629 +       GPIO_pin6_b             = 6,
6630 +       GPIO_pin6_m             = 0x00000040,
6631 +       GPIO_pin7_b             = 7,
6632 +       GPIO_pin7_m             = 0x00000080,
6633 +       GPIO_pin8_b             = 8,
6634 +       GPIO_pin8_m             = 0x00000100,
6635 +       GPIO_pin9_b             = 9,
6636 +       GPIO_pin9_m             = 0x00000200,
6637 +       GPIO_pin10_b            = 10,
6638 +       GPIO_pin10_m            = 0x00000400,
6639 +       GPIO_pin11_b            = 11,
6640 +       GPIO_pin11_m            = 0x00000800,
6641 +       GPIO_pin12_b            = 12,
6642 +       GPIO_pin12_m            = 0x00001000,
6643 +       GPIO_pin13_b            = 13,
6644 +       GPIO_pin13_m            = 0x00002000,
6645 +
6646 +// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
6647 +
6648 +       GPIO_u0sout_b           = GPIO_pin0_b,          // UART 0 serial out.
6649 +       GPIO_u0sout_m           = GPIO_pin0_m,
6650 +               GPIO_u0sout_cfg_v       = GPIO_output_v,
6651 +       GPIO_u0sinp_b   = GPIO_pin1_b,                  // UART 0 serial in.
6652 +       GPIO_u0sinp_m   = GPIO_pin1_m,
6653 +               GPIO_u0sinp_cfg_v       = GPIO_input_v,
6654 +       GPIO_u0rtsn_b   = GPIO_pin2_b,                  // UART 0 req. to send.
6655 +       GPIO_u0rtsn_m   = GPIO_pin2_m,
6656 +               GPIO_u0rtsn_cfg_v       = GPIO_output_v,
6657 +       GPIO_u0ctsn_b   = GPIO_pin3_b,                  // UART 0 clear to send.
6658 +       GPIO_u0ctsn_m   = GPIO_pin3_m,
6659 +               GPIO_u0ctsn_cfg_v       = GPIO_input_v,
6660 +
6661 +       GPIO_maddr22_b          = GPIO_pin4_b,  // M&P bus bit 22.
6662 +       GPIO_maddr22_m          = GPIO_pin4_m,
6663 +               GPIO_maddr22_cfg_v      = GPIO_output_v,
6664 +
6665 +       GPIO_maddr23_b          = GPIO_pin5_b,  // M&P bus bit 23.
6666 +       GPIO_maddr23_m          = GPIO_pin5_m,
6667 +               GPIO_maddr23_cfg_v      = GPIO_output_v,
6668 +
6669 +       GPIO_maddr24_b          = GPIO_pin6_b,  // M&P bus bit 24.
6670 +       GPIO_maddr24_m          = GPIO_pin6_m,
6671 +               GPIO_maddr24_cfg_v      = GPIO_output_v,
6672 +
6673 +       GPIO_maddr25_b          = GPIO_pin7_b,  // M&P bus bit 25.
6674 +       GPIO_maddr25_m          = GPIO_pin7_m,
6675 +               GPIO_maddr25_cfg_v      = GPIO_output_v,
6676 +
6677 +       GPIO_cpudmadebug_b      = GPIO_pin8_b,  // CPU or DMA debug pin
6678 +       GPIO_cpudmadebug_m      = GPIO_pin8_m,
6679 +               GPIO_cpudmadebug_cfg_v  = GPIO_output_v,
6680 +
6681 +       GPIO_pcireq4_b  = GPIO_pin9_b,  // PCI Request 4
6682 +       GPIO_pcireq4_m  = GPIO_pin9_m,
6683 +               GPIO_pcireq4_cfg_v      = GPIO_input_v,
6684 +
6685 +       GPIO_pcigrant4_b        = GPIO_pin10_b,         // PCI Grant 4
6686 +       GPIO_pcigrant4_m        = GPIO_pin10_m,
6687 +               GPIO_pcigrant4_cfg_v    = GPIO_output_v,
6688 +
6689 +       GPIO_pcireq5_b  = GPIO_pin11_b,         // PCI Request 5
6690 +       GPIO_pcireq5_m  = GPIO_pin11_m,
6691 +               GPIO_pcireq5_cfg_v      = GPIO_input_v,
6692 +
6693 +       GPIO_pcigrant5_b        = GPIO_pin12_b,         // PCI Grant 5
6694 +       GPIO_pcigrant5_m        = GPIO_pin12_m,
6695 +               GPIO_pcigrant5_cfg_v    = GPIO_output_v,
6696 +
6697 +       GPIO_pcimuintn_b        = GPIO_pin13_b,         // PCI messaging int.
6698 +       GPIO_pcimuintn_m        = GPIO_pin13_m,
6699 +               GPIO_pcimuintn_cfg_v    = GPIO_output_v,
6700 +
6701 +} GPIO_DEFS_t;
6702 +
6703 +#endif // __IDT_GPIO_H__
6704 +
6705 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h
6706 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434.h  1970-01-01 01:00:00.000000000 +0100
6707 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h     2006-06-18 12:44:28.000000000 +0200
6708 @@ -0,0 +1,199 @@
6709 + /**************************************************************************
6710 + *
6711 + *  BRIEF MODULE DESCRIPTION
6712 + *   Definitions for IDT RC32434 CPU
6713 + *
6714 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6715 + *
6716 + *  This program is free software; you can redistribute  it and/or modify it
6717 + *  under  the terms of  the GNU General  Public License as published by the
6718 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6719 + *  option) any later version.
6720 + *
6721 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6722 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6723 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6724 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6725 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6726 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6727 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6728 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6729 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6730 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6731 + *
6732 + *  You should have received a copy of the  GNU General Public License along
6733 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6734 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6735 + *
6736 + *
6737 + **************************************************************************
6738 + * May 2004 rkt, neb.
6739 + *
6740 + * Initial Release
6741 + *
6742 + *
6743 + *
6744 + **************************************************************************
6745 + */
6746 +
6747 +#ifndef _RC32434_H_
6748 +#define _RC32434_H_
6749 +
6750 +#include <linux/autoconf.h>
6751 +#include <linux/delay.h>
6752 +#include <asm/io.h>
6753 +#include <asm/idt-boards/rc32434/rc32434_timer.h>
6754 +
6755 +#define RC32434_REG_BASE   0x18000000
6756 +
6757 +
6758 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
6759 +#define idt_timer     ((volatile TIM_t)  TIM0_VirtualAddress)
6760 +#define idt_gpio         ((volatile GPIO_t) GPIO0_VirtualAddress)
6761 +
6762 +#define IDT_CLOCK_MULT 2
6763 +#define MIPS_CPU_TIMER_IRQ 7
6764 +/* Interrupt Controller */
6765 +#define IC_GROUP0_PEND     (RC32434_REG_BASE + 0x38000)
6766 +#define IC_GROUP0_MASK     (RC32434_REG_BASE + 0x38008)
6767 +#define IC_GROUP_OFFSET    0x0C
6768 +#define RTC_BASE           0xBA001FF0
6769 +
6770 +#define NUM_INTR_GROUPS    5
6771 +/* 16550 UARTs */
6772 +
6773 +#define GROUP0_IRQ_BASE 8              /* GRP2 IRQ numbers start here */
6774 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
6775 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
6776 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
6777 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
6778 +
6779 +#ifdef __MIPSEB__
6780 +
6781 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
6782 +#define EB434_UART1_BASE   (0x19800003)
6783 +
6784 +#else
6785 +
6786 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
6787 +#define EB434_UART1_BASE   (0x19800000)
6788 +
6789 +#endif
6790 +
6791 +#define RC32434_UART0_IRQ  GROUP3_IRQ_BASE + 0
6792 +#define EB434_UART1_IRQ    GROUP4_IRQ_BASE + 11
6793 +
6794 +#define RC32434_NR_IRQS  (GROUP4_IRQ_BASE + 32)
6795 +
6796 +/* cpu pipeline flush */
6797 +static inline void rc32434_sync(void)
6798 +{
6799 +        __asm__ volatile ("sync");
6800 +}
6801 +
6802 +static inline void rc32434_sync_udelay(int us)
6803 +{
6804 +        __asm__ volatile ("sync");
6805 +        udelay(us);
6806 +}
6807 +
6808 +static inline void rc32434_sync_delay(int ms)
6809 +{
6810 +        __asm__ volatile ("sync");
6811 +        mdelay(ms);
6812 +}
6813 +
6814 +
6815 +
6816 +/*
6817 + * Macros to access internal RC32434 registers. No byte
6818 + * swapping should be done when accessing the internal
6819 + * registers.
6820 + */
6821 +
6822 +#define rc32434_readb __raw_readb
6823 +#define rc32434_readw __raw_readw
6824 +#define rc32434_readl __raw_readl
6825 +
6826 +#define rc32434_writeb __raw_writeb
6827 +#define rc32434_writew __raw_writew
6828 +#define rc32434_writel __raw_writel
6829 +
6830 +#if 0
6831 +static inline u8 rc32434_readb(unsigned long pa)
6832 +{
6833 +       return *((volatile u8 *)KSEG1ADDR(pa));
6834 +}
6835 +static inline u16 rc32434_readw(unsigned long pa)
6836 +{
6837 +       return *((volatile u16 *)KSEG1ADDR(pa));
6838 +}
6839 +static inline u32 rc32434_readl(unsigned long pa)
6840 +{
6841 +       return *((volatile u32 *)KSEG1ADDR(pa));
6842 +}
6843 +static inline void rc32434_writeb(u8 val, unsigned long pa)
6844 +{
6845 +       *((volatile u8 *)KSEG1ADDR(pa)) = val;
6846 +}
6847 +static inline void rc32434_writew(u16 val, unsigned long pa)
6848 +{
6849 +       *((volatile u16 *)KSEG1ADDR(pa)) = val;
6850 +}
6851 +static inline void rc32434_writel(u32 val, unsigned long pa)
6852 +{
6853 +       *((volatile u32 *)KSEG1ADDR(pa)) = val;
6854 +}
6855 +
6856 +#endif
6857 +
6858 +
6859 +/*
6860 + * C access to CLZ and CLO instructions
6861 + * (count leading zeroes/ones).
6862 + */
6863 +static inline int rc32434_clz(unsigned long val)
6864 +{
6865 +       int ret;
6866 +        __asm__ volatile (
6867 +               ".set\tnoreorder\n\t"
6868 +               ".set\tnoat\n\t"
6869 +               ".set\tmips32\n\t"
6870 +               "clz\t%0,%1\n\t"
6871 +                ".set\tmips0\n\t"
6872 +                ".set\tat\n\t"
6873 +                ".set\treorder"
6874 +                : "=r" (ret)
6875 +               : "r" (val));
6876 +
6877 +       return ret;
6878 +}
6879 +static inline int rc32434_clo(unsigned long val)
6880 +{
6881 +       int ret;
6882 +        __asm__ volatile (
6883 +               ".set\tnoreorder\n\t"
6884 +               ".set\tnoat\n\t"
6885 +               ".set\tmips32\n\t"
6886 +               "clo\t%0,%1\n\t"
6887 +                ".set\tmips0\n\t"
6888 +                ".set\tat\n\t"
6889 +                ".set\treorder"
6890 +                : "=r" (ret)
6891 +               : "r" (val));
6892 +
6893 +       return ret;
6894 +}
6895 +#endif /* _RC32434_H_ */
6896 +
6897 +
6898 +
6899 +
6900 +
6901 +
6902 +
6903 +
6904 +
6905 +
6906 +
6907 +
6908 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_integ.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h
6909 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_integ.h    1970-01-01 01:00:00.000000000 +0100
6910 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h       2006-06-18 12:44:28.000000000 +0200
6911 @@ -0,0 +1,90 @@
6912 +/**************************************************************************
6913 + *
6914 + *  BRIEF MODULE DESCRIPTION
6915 + *   System Integrity register definition
6916 + *
6917 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6918 + *
6919 + *  This program is free software; you can redistribute  it and/or modify it
6920 + *  under  the terms of  the GNU General  Public License as published by the
6921 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6922 + *  option) any later version.
6923 + *
6924 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6925 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6926 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6927 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6928 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6929 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6930 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6931 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6932 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6933 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6934 + *
6935 + *  You should have received a copy of the  GNU General Public License along
6936 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6937 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6938 + *
6939 + *
6940 + **************************************************************************
6941 + * May 2004 rkt, neb
6942 + *
6943 + * Initial Release
6944 + *
6945 + *
6946 + *
6947 + **************************************************************************
6948 + */
6949 +
6950 +#ifndef __IDT_INTEG_H__
6951 +#define __IDT_INTEG_H__
6952 +
6953 +enum
6954 +{
6955 +       INTEG0_PhysicalAddress  = 0x18030000,
6956 +       INTEG_PhysicalAddress   = INTEG0_PhysicalAddress,       // Default
6957 +
6958 +       INTEG0_VirtualAddress   = 0xB8030000,
6959 +       INTEG_VirtualAddress    = INTEG0_VirtualAddress,        // Default
6960 +} ;
6961 +
6962 +// if you are looking for CEA, try rst.h
6963 +typedef struct
6964 +{
6965 +       u32 filler [0xc] ;              // 0x30 bytes unused.
6966 +       u32 errcs ;                     // sticky use ERRCS_
6967 +       u32 wtcount ;                   // Watchdog timer count reg.
6968 +       u32 wtcompare ;                 // Watchdog timer timeout value.
6969 +       u32 wtc ;                       // Watchdog timer control. use WTC_
6970 +} volatile *INTEG_t ;
6971 +
6972 +enum
6973 +{
6974 +       ERRCS_wto_b             = 0,            // In INTEG_t -> errcs
6975 +       ERRCS_wto_m             = 0x00000001,
6976 +       ERRCS_wne_b             = 1,            // In INTEG_t -> errcs
6977 +       ERRCS_wne_m             = 0x00000002,
6978 +       ERRCS_ucw_b             = 2,            // In INTEG_t -> errcs
6979 +       ERRCS_ucw_m             = 0x00000004,
6980 +       ERRCS_ucr_b             = 3,            // In INTEG_t -> errcs
6981 +       ERRCS_ucr_m             = 0x00000008,
6982 +       ERRCS_upw_b             = 4,            // In INTEG_t -> errcs
6983 +       ERRCS_upw_m             = 0x00000010,
6984 +       ERRCS_upr_b             = 5,            // In INTEG_t -> errcs
6985 +       ERRCS_upr_m             = 0x00000020,
6986 +       ERRCS_udw_b             = 6,            // In INTEG_t -> errcs
6987 +       ERRCS_udw_m             = 0x00000040,
6988 +       ERRCS_udr_b             = 7,            // In INTEG_t -> errcs
6989 +       ERRCS_udr_m             = 0x00000080,
6990 +       ERRCS_sae_b             = 8,            // In INTEG_t -> errcs
6991 +       ERRCS_sae_m             = 0x00000100,
6992 +       ERRCS_wre_b             = 9,            // In INTEG_t -> errcs
6993 +       ERRCS_wre_m             = 0x00000200,
6994 +
6995 +       WTC_en_b                = 0,            // In INTEG_t -> wtc
6996 +       WTC_en_m                = 0x00000001,
6997 +       WTC_to_b                = 1,            // In INTEG_t -> wtc
6998 +       WTC_to_m                = 0x00000002,
6999 +} ;
7000 +
7001 +#endif // __IDT_INTEG_H__
7002 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_int.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h
7003 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_int.h      1970-01-01 01:00:00.000000000 +0100
7004 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h 2006-06-18 12:44:28.000000000 +0200
7005 @@ -0,0 +1,174 @@
7006 +/**************************************************************************
7007 + *
7008 + *  BRIEF MODULE DESCRIPTION
7009 + *   Interrupt Controller register definition.
7010 + *
7011 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
7012 + *
7013 + *  This program is free software; you can redistribute  it and/or modify it
7014 + *  under  the terms of  the GNU General  Public License as published by the
7015 + *  Free Software Foundation;  either version 2 of the  License, or (at your
7016 + *  option) any later version.
7017 + *
7018 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
7019 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
7020 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
7021 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
7022 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7023 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
7024 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7025 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
7026 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7027 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7028 + *
7029 + *  You should have received a copy of the  GNU General Public License along
7030 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
7031 + *  675 Mass Ave, Cambridge, MA 02139, USA.
7032 + *
7033 + *
7034 + **************************************************************************
7035 + * May 2004 rkt, neb.
7036 + *
7037 + * Initial Release
7038 + *
7039 + *
7040 + *
7041 + **************************************************************************
7042 + */
7043 +
7044 +#ifndef __IDT_INT_H__
7045 +#define __IDT_INT_H__
7046 +
7047 +enum
7048 +{
7049 +       INT0_PhysicalAddress    = 0x18038000,
7050 +       INT_PhysicalAddress     = INT0_PhysicalAddress,         // Default
7051 +
7052 +       INT0_VirtualAddress     = 0xB8038000,
7053 +       INT_VirtualAddress      = INT0_VirtualAddress,          // Default
7054 +} ;
7055 +
7056 +struct INT_s
7057 +{
7058 +       u32             ipend ;         //Pending interrupts. use INT?_
7059 +       u32             itest ;         //Test bits.            use INT?_
7060 +       u32             imask ;         //Interrupt disabled when set. use INT?_
7061 +} ;
7062 +
7063 +enum
7064 +{
7065 +       IPEND2  = 0,                    // HW 2 interrupt to core. use INT2_
7066 +       IPEND3  = 1,                    // HW 3 interrupt to core. use INT3_
7067 +       IPEND4  = 2,                    // HW 4 interrupt to core. use INT4_
7068 +       IPEND5  = 3,                    // HW 5 interrupt to core. use INT5_
7069 +       IPEND6  = 4,                    // HW 6 interrupt to core. use INT6_
7070 +
7071 +       IPEND_count,                    // must be last (used in loops)
7072 +       IPEND_min       = IPEND2        // min IPEND (used in loops)
7073 +};
7074 +
7075 +typedef struct INTC_s
7076 +{
7077 +       struct INT_s    i [IPEND_count] ;// use i[IPEND?] = INT?_
7078 +       u32             nmips ;         // use NMIPS_
7079 +} volatile *INT_t ;
7080 +
7081 +enum
7082 +{
7083 +       INT2_timer0_b                   = 0,
7084 +       INT2_timer0_m                   = 0x00000001,
7085 +       INT2_timer1_b                   = 1,
7086 +       INT2_timer1_m                   = 0x00000002,
7087 +       INT2_timer2_b                   = 2,
7088 +       INT2_timer2_m                   = 0x00000004,
7089 +       INT2_refresh_b                  = 3,
7090 +       INT2_refresh_m                  = 0x00000008,
7091 +       INT2_watchdogTimeout_b          = 4,
7092 +       INT2_watchdogTimeout_m          = 0x00000010,
7093 +       INT2_undecodedCpuWrite_b        = 5,
7094 +       INT2_undecodedCpuWrite_m        = 0x00000020,
7095 +       INT2_undecodedCpuRead_b         = 6,
7096 +       INT2_undecodedCpuRead_m         = 0x00000040,
7097 +       INT2_undecodedPciWrite_b        = 7,
7098 +       INT2_undecodedPciWrite_m        = 0x00000080,
7099 +       INT2_undecodedPciRead_b         = 8,
7100 +       INT2_undecodedPciRead_m         = 0x00000100,
7101 +       INT2_undecodedDmaWrite_b        = 9,
7102 +       INT2_undecodedDmaWrite_m        = 0x00000200,
7103 +       INT2_undecodedDmaRead_b         = 10,
7104 +       INT2_undecodedDmaRead_m         = 0x00000400,
7105 +       INT2_ipBusSlaveAckError_b       = 11,
7106 +       INT2_ipBusSlaveAckError_m       = 0x00000800,
7107 +
7108 +       INT3_dmaChannel0_b              = 0,
7109 +       INT3_dmaChannel0_m              = 0x00000001,
7110 +       INT3_dmaChannel1_b              = 1,
7111 +       INT3_dmaChannel1_m              = 0x00000002,
7112 +       INT3_dmaChannel2_b              = 2,
7113 +       INT3_dmaChannel2_m              = 0x00000004,
7114 +       INT3_dmaChannel3_b              = 3,
7115 +       INT3_dmaChannel3_m              = 0x00000008,
7116 +       INT3_dmaChannel4_b              = 4,
7117 +       INT3_dmaChannel4_m              = 0x00000010,
7118 +       INT3_dmaChannel5_b              = 5,
7119 +       INT3_dmaChannel5_m              = 0x00000020,
7120 +
7121 +       INT5_uartGeneral0_b             = 0,
7122 +       INT5_uartGeneral0_m             = 0x00000001,
7123 +       INT5_uartTxrdy0_b               = 1,
7124 +       INT5_uartTxrdy0_m               = 0x00000002,
7125 +       INT5_uartRxrdy0_b               = 2,
7126 +       INT5_uartRxrdy0_m               = 0x00000004,
7127 +       INT5_pci_b                      = 3,
7128 +       INT5_pci_m                      = 0x00000008,
7129 +       INT5_pciDecoupled_b             = 4,
7130 +       INT5_pciDecoupled_m             = 0x00000010,
7131 +       INT5_spi_b                      = 5,
7132 +       INT5_spi_m                      = 0x00000020,
7133 +       INT5_deviceDecoupled_b          = 6,
7134 +       INT5_deviceDecoupled_m          = 0x00000040,
7135 +       INT5_eth0Ovr_b                  = 9,
7136 +       INT5_eth0Ovr_m                  = 0x00000200,
7137 +       INT5_eth0Und_b                  = 10,
7138 +       INT5_eth0Und_m                  = 0x00000400,
7139 +       INT5_eth0Pfd_b                  = 11,
7140 +       INT5_eth0Pfd_m                  = 0x00000800,
7141 +       INT5_nvram_b                    = 12,
7142 +       INT5_nvram_m                    = 0x00001000,
7143 +
7144 +       INT6_gpio0_b                    = 0,
7145 +       INT6_gpio0_m                    = 0x00000001,
7146 +       INT6_gpio1_b                    = 1,
7147 +       INT6_gpio1_m                    = 0x00000002,
7148 +       INT6_gpio2_b                    = 2,
7149 +       INT6_gpio2_m                    = 0x00000004,
7150 +       INT6_gpio3_b                    = 3,
7151 +       INT6_gpio3_m                    = 0x00000008,
7152 +       INT6_gpio4_b                    = 4,
7153 +       INT6_gpio4_m                    = 0x00000010,
7154 +       INT6_gpio5_b                    = 5,
7155 +       INT6_gpio5_m                    = 0x00000020,
7156 +       INT6_gpio6_b                    = 6,
7157 +       INT6_gpio6_m                    = 0x00000040,
7158 +       INT6_gpio7_b                    = 7,
7159 +       INT6_gpio7_m                    = 0x00000080,
7160 +       INT6_gpio8_b                    = 8,
7161 +       INT6_gpio8_m                    = 0x00000100,
7162 +       INT6_gpio9_b                    = 9,
7163 +       INT6_gpio9_m                    = 0x00000200,
7164 +       INT6_gpio10_b                   = 10,
7165 +       INT6_gpio10_m                   = 0x00000400,
7166 +       INT6_gpio11_b                   = 11,
7167 +       INT6_gpio11_m                   = 0x00000800,
7168 +       INT6_gpio12_b                   = 12,
7169 +       INT6_gpio12_m                   = 0x00001000,
7170 +       INT6_gpio13_b                   = 13,
7171 +       INT6_gpio13_m                   = 0x00002000,
7172 +
7173 +       NMIPS_gpio_b                    = 0,
7174 +       NMIPS_gpio_m                    = 0x00000001,
7175 +} ;
7176 +
7177 +#endif // __IDT_INT_H__
7178 +
7179 +
7180 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h
7181 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h    1970-01-01 01:00:00.000000000 +0100
7182 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h       2006-06-18 12:44:28.000000000 +0200
7183 @@ -0,0 +1,111 @@
7184 +/**************************************************************************
7185 + *
7186 + *  BRIEF MODULE DESCRIPTION
7187 + *   IP Arbiter register definitions
7188 + *
7189 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
7190 + *
7191 + *  This program is free software; you can redistribute  it and/or modify it
7192 + *  under  the terms of  the GNU General  Public License as published by the
7193 + *  Free Software Foundation;  either version 2 of the  License, or (at your
7194 + *  option) any later version.
7195 + *
7196 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
7197 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
7198 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
7199 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
7200 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7201 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
7202 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7203 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
7204 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7205 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7206 + *
7207 + *  You should have received a copy of the  GNU General Public License along
7208 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
7209 + *  675 Mass Ave, Cambridge, MA 02139, USA.
7210 + *
7211 + *
7212 + **************************************************************************
7213 + * May 2004 rkt,neb
7214 + *
7215 + * Initial Release
7216 + *
7217 + *
7218 + *
7219 + **************************************************************************
7220 + */
7221 +
7222 +#ifndef __IDT_IPARB_H__
7223 +#define __IDT_IPARB_H__
7224 +
7225 +enum
7226 +{
7227 +       IPARB0_PhysicalAddress  = 0x18048000,
7228 +       IPARB_PhysicalAddress   = IPARB0_PhysicalAddress,       // Default
7229 +
7230 +       IPARB0_VirtualAddress   = 0xB8048000,
7231 +       IPARB_VirtualAddress    = IPARB0_VirtualAddress,        // Default
7232 +} ;
7233 +
7234 +enum
7235 +{
7236 +       IPABMXC_ethernet0Receive        = 0,
7237 +       IPABMXC_ethernet0Transmit       = 1,
7238 +       IPABMXC_memoryToHoldFifo        = 2,
7239 +       IPABMXC_holdFifoToMemory        = 3,
7240 +       IPABMXC_pciToMemory             = 4,
7241 +       IPABMXC_memoryToPci             = 5,
7242 +       IPABMXC_pciTarget               = 6,
7243 +       IPABMXC_pciTargetStart          = 7,
7244 +       IPABMXC_cpuToIpBus              = 8,
7245 +
7246 +       IPABMXC_Count,                          // Must be last in list !
7247 +       IPABMXC_Min                     = IPABMXC_ethernet0Receive,
7248 +
7249 +       IPAPXC_PriorityCount    = 4,            // 3-highest, 0-lowest.
7250 +} ;
7251 +
7252 +typedef struct
7253 +{
7254 +       u32     ipapc [IPAPXC_PriorityCount] ;  // ipapc[IPAPXC_] = IPAPC_
7255 +       u32     ipabmc [IPABMXC_Count] ;        // ipabmc[IPABMXC_] = IPABMC_
7256 +       u32     ipac ;                          // use IPAC_
7257 +       u32     ipaitcc;                        // use IPAITCC_
7258 +       u32     ipaspare ;
7259 +} volatile * IPARB_t ;
7260 +
7261 +enum
7262 +{
7263 +       IPAC_dp_b                       = 0,
7264 +       IPAC_dp_m                       = 0x00000001,
7265 +       IPAC_dep_b                      = 1,
7266 +       IPAC_dep_m                      = 0x00000002,
7267 +       IPAC_drm_b                      = 2,
7268 +       IPAC_drm_m                      = 0x00000004,
7269 +       IPAC_dwm_b                      = 3,
7270 +       IPAC_dwm_m                      = 0x00000008,
7271 +       IPAC_msk_b                      = 4,
7272 +       IPAC_msk_m                      = 0x00000010,
7273 +
7274 +       IPAPC_ptc_b                     = 0,
7275 +       IPAPC_ptc_m                     = 0x00003fff,
7276 +       IPAPC_mf_b                      = 14,
7277 +       IPAPC_mf_m                      = 0x00004000,
7278 +       IPAPC_cptc_b                    = 16,
7279 +       IPAPC_cptc_m                    = 0x3fff0000,
7280 +
7281 +       IPAITCC_itcc                    = 0,
7282 +       IPAITCC_itcc,                   = 0x000001ff,
7283 +
7284 +       IPABMC_mtc_b                    = 0,
7285 +       IPABMC_mtc_m                    = 0x00000fff,
7286 +       IPABMC_p_b                      = 12,
7287 +       IPABMC_p_m                      = 0x00003000,
7288 +       IPABMC_msk_b                    = 14,
7289 +       IPABMC_msk_m                    = 0x00004000,
7290 +       IPABMC_cmtc_b                   = 16,
7291 +       IPABMC_cmtc_m                   = 0x0fff0000,
7292 +};
7293 +
7294 +#endif // __IDT_IPARB_H__
7295 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h
7296 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_pci.h      1970-01-01 01:00:00.000000000 +0100
7297 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 2006-06-18 12:44:28.000000000 +0200
7298 @@ -0,0 +1,695 @@
7299 +/**************************************************************************
7300 + *
7301 + *  BRIEF MODULE DESCRIPTION
7302 + *   PCI register definitio
7303 + *
7304 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
7305 + *
7306 + *  This program is free software; you can redistribute  it and/or modify it
7307 + *  under  the terms of  the GNU General  Public License as published by the
7308 + *  Free Software Foundation;  either version 2 of the  License, or (at your
7309 + *  option) any later version.
7310 + *
7311 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
7312 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
7313 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
7314 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
7315 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7316 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
7317 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7318 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
7319 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7320 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7321 + *
7322 + *  You should have received a copy of the  GNU General Public License along
7323 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
7324 + *  675 Mass Ave, Cambridge, MA 02139, USA.
7325 + *
7326 + *
7327 + **************************************************************************
7328 + * May 2004 rkt, neb.
7329 + *
7330 + * Initial Release
7331 + *
7332 + *
7333 + *
7334 + **************************************************************************
7335 + */
7336 +
7337 +#ifndef __IDT_PCI_H__
7338 +#define __IDT_PCI_H__
7339 +
7340 +enum
7341 +{
7342 +       PCI0_PhysicalAddress    = 0x18080000,
7343 +       PCI_PhysicalAddress     = PCI0_PhysicalAddress,
7344 +
7345 +       PCI0_VirtualAddress     = 0xB8080000,
7346 +       PCI_VirtualAddress      = PCI0_VirtualAddress,
7347 +} ;
7348 +
7349 +enum
7350 +{
7351 +       PCI_LbaCount    = 4,            // Local base addresses.
7352 +} ;
7353 +
7354 +typedef struct
7355 +{
7356 +       u32     a ;             // Address.
7357 +       u32     c ;             // Control.
7358 +       u32     m ;             // mapping.
7359 +} PCI_Map_s ;
7360 +
7361 +typedef struct
7362 +{
7363 +       u32             pcic ;
7364 +       u32             pcis ;
7365 +       u32             pcism ;
7366 +       u32             pcicfga ;
7367 +       u32             pcicfgd ;
7368 +       PCI_Map_s       pcilba [PCI_LbaCount] ;
7369 +       u32             pcidac ;
7370 +       u32             pcidas ;
7371 +       u32             pcidasm ;
7372 +       u32             pcidad ;
7373 +       u32             pcidma8c ;
7374 +       u32             pcidma9c ;
7375 +       u32             pcitc ;
7376 +} volatile *PCI_t ;
7377 +
7378 +// PCI messaging unit.
7379 +enum
7380 +{
7381 +       PCIM_Count      = 2,
7382 +} ;
7383 +typedef struct
7384 +{
7385 +       u32             pciim [PCIM_Count] ;
7386 +       u32             pciom [PCIM_Count] ;
7387 +       u32             pciid ;
7388 +       u32             pciiic ;
7389 +       u32             pciiim ;
7390 +       u32             pciiod ;
7391 +       u32             pciioic ;
7392 +       u32             pciioim ;
7393 +} volatile *PCIM_t ;
7394 +
7395 +/*******************************************************************************
7396 + *
7397 + * PCI Control Register
7398 + *
7399 + ******************************************************************************/
7400 +enum
7401 +{
7402 +       PCIC_en_b       = 0,
7403 +       PCIC_en_m       = 0x00000001,
7404 +       PCIC_tnr_b      = 1,
7405 +       PCIC_tnr_m      = 0x00000002,
7406 +       PCIC_sce_b      = 2,
7407 +       PCIC_sce_m      = 0x00000004,
7408 +       PCIC_ien_b      = 3,
7409 +       PCIC_ien_m      = 0x00000008,
7410 +       PCIC_aaa_b      = 4,
7411 +       PCIC_aaa_m      = 0x00000010,
7412 +       PCIC_eap_b      = 5,
7413 +       PCIC_eap_m      = 0x00000020,
7414 +       PCIC_pcim_b     = 6,
7415 +       PCIC_pcim_m     = 0x000001c0,
7416 +               PCIC_pcim_disabled_v    = 0,
7417 +               PCIC_pcim_tnr_v         = 1,    // Satellite - target not ready
7418 +               PCIC_pcim_suspend_v     = 2,    // Satellite - suspended CPU.
7419 +               PCIC_pcim_extern_v      = 3,    // Host - external arbiter.
7420 +               PCIC_pcim_fixed_v       = 4,    // Host - fixed priority arb.
7421 +               PCIC_pcim_roundrobin_v  = 5,    // Host - round robin priority.
7422 +               PCIC_pcim_reserved6_v   = 6,
7423 +               PCIC_pcim_reserved7_v   = 7,
7424 +       PCIC_igm_b      = 9,
7425 +       PCIC_igm_m      = 0x00000200,
7426 +} ;
7427 +
7428 +/*******************************************************************************
7429 + *
7430 + * PCI Status Register
7431 + *
7432 + ******************************************************************************/
7433 +enum {
7434 +       PCIS_eed_b      = 0,
7435 +       PCIS_eed_m      = 0x00000001,
7436 +       PCIS_wr_b       = 1,
7437 +       PCIS_wr_m       = 0x00000002,
7438 +       PCIS_nmi_b      = 2,
7439 +       PCIS_nmi_m      = 0x00000004,
7440 +       PCIS_ii_b       = 3,
7441 +       PCIS_ii_m       = 0x00000008,
7442 +       PCIS_cwe_b      = 4,
7443 +       PCIS_cwe_m      = 0x00000010,
7444 +       PCIS_cre_b      = 5,
7445 +       PCIS_cre_m      = 0x00000020,
7446 +       PCIS_mdpe_b     = 6,
7447 +       PCIS_mdpe_m     = 0x00000040,
7448 +       PCIS_sta_b      = 7,
7449 +       PCIS_sta_m      = 0x00000080,
7450 +       PCIS_rta_b      = 8,
7451 +       PCIS_rta_m      = 0x00000100,
7452 +       PCIS_rma_b      = 9,
7453 +       PCIS_rma_m      = 0x00000200,
7454 +       PCIS_sse_b      = 10,
7455 +       PCIS_sse_m      = 0x00000400,
7456 +       PCIS_ose_b      = 11,
7457 +       PCIS_ose_m      = 0x00000800,
7458 +       PCIS_pe_b       = 12,
7459 +       PCIS_pe_m       = 0x00001000,
7460 +       PCIS_tae_b      = 13,
7461 +       PCIS_tae_m      = 0x00002000,
7462 +       PCIS_rle_b      = 14,
7463 +       PCIS_rle_m      = 0x00004000,
7464 +       PCIS_bme_b      = 15,
7465 +       PCIS_bme_m      = 0x00008000,
7466 +       PCIS_prd_b      = 16,
7467 +       PCIS_prd_m      = 0x00010000,
7468 +       PCIS_rip_b      = 17,
7469 +       PCIS_rip_m      = 0x00020000,
7470 +} ;
7471 +
7472 +/*******************************************************************************
7473 + *
7474 + * PCI Status Mask Register
7475 + *
7476 + ******************************************************************************/
7477 +enum {
7478 +       PCISM_eed_b             = 0,
7479 +       PCISM_eed_m             = 0x00000001,
7480 +       PCISM_wr_b              = 1,
7481 +       PCISM_wr_m              = 0x00000002,
7482 +       PCISM_nmi_b             = 2,
7483 +       PCISM_nmi_m             = 0x00000004,
7484 +       PCISM_ii_b              = 3,
7485 +       PCISM_ii_m              = 0x00000008,
7486 +       PCISM_cwe_b             = 4,
7487 +       PCISM_cwe_m             = 0x00000010,
7488 +       PCISM_cre_b             = 5,
7489 +       PCISM_cre_m             = 0x00000020,
7490 +       PCISM_mdpe_b            = 6,
7491 +       PCISM_mdpe_m            = 0x00000040,
7492 +       PCISM_sta_b             = 7,
7493 +       PCISM_sta_m             = 0x00000080,
7494 +       PCISM_rta_b             = 8,
7495 +       PCISM_rta_m             = 0x00000100,
7496 +       PCISM_rma_b             = 9,
7497 +       PCISM_rma_m             = 0x00000200,
7498 +       PCISM_sse_b             = 10,
7499 +       PCISM_sse_m             = 0x00000400,
7500 +       PCISM_ose_b             = 11,
7501 +       PCISM_ose_m             = 0x00000800,
7502 +       PCISM_pe_b              = 12,
7503 +       PCISM_pe_m              = 0x00001000,
7504 +       PCISM_tae_b             = 13,
7505 +       PCISM_tae_m             = 0x00002000,
7506 +       PCISM_rle_b             = 14,
7507 +       PCISM_rle_m             = 0x00004000,
7508 +       PCISM_bme_b             = 15,
7509 +       PCISM_bme_m             = 0x00008000,
7510 +       PCISM_prd_b             = 16,
7511 +       PCISM_prd_m             = 0x00010000,
7512 +       PCISM_rip_b             = 17,
7513 +       PCISM_rip_m             = 0x00020000,
7514 +} ;
7515 +
7516 +/*******************************************************************************
7517 + *
7518 + * PCI Configuration Address Register
7519 + *
7520 + ******************************************************************************/
7521 +enum {
7522 +       PCICFGA_reg_b           = 2,
7523 +       PCICFGA_reg_m           = 0x000000fc,
7524 +               PCICFGA_reg_id_v        = 0x00>>2, //use PCFGID_
7525 +               PCICFGA_reg_04_v        = 0x04>>2, //use PCFG04_
7526 +               PCICFGA_reg_08_v        = 0x08>>2, //use PCFG08_
7527 +               PCICFGA_reg_0C_v        = 0x0C>>2, //use PCFG0C_
7528 +               PCICFGA_reg_pba0_v      = 0x10>>2, //use PCIPBA_
7529 +               PCICFGA_reg_pba1_v      = 0x14>>2, //use PCIPBA_
7530 +               PCICFGA_reg_pba2_v      = 0x18>>2, //use PCIPBA_
7531 +               PCICFGA_reg_pba3_v      = 0x1c>>2, //use PCIPBA_
7532 +               PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
7533 +               PCICFGA_reg_3C_v        = 0x3C>>2, //use PCFG3C_
7534 +               PCICFGA_reg_pba0c_v     = 0x44>>2, //use PCIPBAC_
7535 +               PCICFGA_reg_pba0m_v     = 0x48>>2,
7536 +               PCICFGA_reg_pba1c_v     = 0x4c>>2, //use PCIPBAC_
7537 +               PCICFGA_reg_pba1m_v     = 0x50>>2,
7538 +               PCICFGA_reg_pba2c_v     = 0x54>>2, //use PCIPBAC_
7539 +               PCICFGA_reg_pba2m_v     = 0x58>>2,
7540 +               PCICFGA_reg_pba3c_v     = 0x5c>>2, //use PCIPBAC_
7541 +               PCICFGA_reg_pba3m_v     = 0x60>>2,
7542 +               PCICFGA_reg_pmgt_v      = 0x64>>2,
7543 +       PCICFGA_func_b          = 8,
7544 +       PCICFGA_func_m          = 0x00000700,
7545 +       PCICFGA_dev_b           = 11,
7546 +       PCICFGA_dev_m           = 0x0000f800,
7547 +               PCICFGA_dev_internal_v  = 0,
7548 +       PCICFGA_bus_b           = 16,
7549 +       PCICFGA_bus_m           = 0x00ff0000,
7550 +               PCICFGA_bus_type0_v     = 0,    //local bus
7551 +       PCICFGA_en_b            = 31,           // read only
7552 +       PCICFGA_en_m            = 0x80000000,
7553 +} ;
7554 +
7555 +enum {
7556 +       PCFGID_vendor_b         = 0,
7557 +       PCFGID_vendor_m         = 0x0000ffff,
7558 +               PCFGID_vendor_IDT_v             = 0x111d,
7559 +       PCFGID_device_b         = 16,
7560 +       PCFGID_device_m         = 0xffff0000,
7561 +               PCFGID_device_Korinade_v        = 0x0214,
7562 +
7563 +       PCFG04_command_ioena_b          = 1,
7564 +       PCFG04_command_ioena_m          = 0x00000001,
7565 +       PCFG04_command_memena_b         = 2,
7566 +       PCFG04_command_memena_m         = 0x00000002,
7567 +       PCFG04_command_bmena_b          = 3,
7568 +       PCFG04_command_bmena_m          = 0x00000004,
7569 +       PCFG04_command_mwinv_b          = 5,
7570 +       PCFG04_command_mwinv_m          = 0x00000010,
7571 +       PCFG04_command_parena_b         = 7,
7572 +       PCFG04_command_parena_m         = 0x00000040,
7573 +       PCFG04_command_serrena_b        = 9,
7574 +       PCFG04_command_serrena_m        = 0x00000100,
7575 +       PCFG04_command_fastbbena_b      = 10,
7576 +       PCFG04_command_fastbbena_m      = 0x00000200,
7577 +       PCFG04_status_b                 = 16,
7578 +       PCFG04_status_m                 = 0xffff0000,
7579 +       PCFG04_status_66MHz_b           = 21,   // 66 MHz enable
7580 +       PCFG04_status_66MHz_m           = 0x00200000,
7581 +       PCFG04_status_fbb_b             = 23,
7582 +       PCFG04_status_fbb_m             = 0x00800000,
7583 +       PCFG04_status_mdpe_b            = 24,
7584 +       PCFG04_status_mdpe_m            = 0x01000000,
7585 +       PCFG04_status_dst_b             = 25,
7586 +       PCFG04_status_dst_m             = 0x06000000,
7587 +       PCFG04_status_sta_b             = 27,
7588 +       PCFG04_status_sta_m             = 0x08000000,
7589 +       PCFG04_status_rta_b             = 28,
7590 +       PCFG04_status_rta_m             = 0x10000000,
7591 +       PCFG04_status_rma_b             = 29,
7592 +       PCFG04_status_rma_m             = 0x20000000,
7593 +       PCFG04_status_sse_b             = 30,
7594 +       PCFG04_status_sse_m             = 0x40000000,
7595 +       PCFG04_status_pe_b              = 31,
7596 +       PCFG04_status_pe_m              = 0x40000000,
7597 +
7598 +       PCFG08_revId_b                  = 0,
7599 +       PCFG08_revId_m                  = 0x000000ff,
7600 +       PCFG08_classCode_b              = 0,
7601 +       PCFG08_classCode_m              = 0xffffff00,
7602 +               PCFG08_classCode_bridge_v       = 06,
7603 +               PCFG08_classCode_proc_v         = 0x0b3000, // processor-MIPS
7604 +       PCFG0C_cacheline_b              = 0,
7605 +       PCFG0C_cacheline_m              = 0x000000ff,
7606 +       PCFG0C_masterLatency_b          = 8,
7607 +       PCFG0C_masterLatency_m          = 0x0000ff00,
7608 +       PCFG0C_headerType_b             = 16,
7609 +       PCFG0C_headerType_m             = 0x00ff0000,
7610 +       PCFG0C_bist_b                   = 24,
7611 +       PCFG0C_bist_m                   = 0xff000000,
7612 +
7613 +       PCIPBA_msi_b                    = 0,
7614 +       PCIPBA_msi_m                    = 0x00000001,
7615 +       PCIPBA_p_b                      = 3,
7616 +       PCIPBA_p_m                      = 0x00000004,
7617 +       PCIPBA_baddr_b                  = 8,
7618 +       PCIPBA_baddr_m                  = 0xffffff00,
7619 +
7620 +       PCFGSS_vendorId_b               = 0,
7621 +       PCFGSS_vendorId_m               = 0x0000ffff,
7622 +       PCFGSS_id_b                     = 16,
7623 +       PCFGSS_id_m                     = 0xffff0000,
7624 +
7625 +       PCFG3C_interruptLine_b          = 0,
7626 +       PCFG3C_interruptLine_m          = 0x000000ff,
7627 +       PCFG3C_interruptPin_b           = 8,
7628 +       PCFG3C_interruptPin_m           = 0x0000ff00,
7629 +       PCFG3C_minGrant_b               = 16,
7630 +       PCFG3C_minGrant_m               = 0x00ff0000,
7631 +       PCFG3C_maxLat_b                 = 24,
7632 +       PCFG3C_maxLat_m                 = 0xff000000,
7633 +
7634 +       PCIPBAC_msi_b                   = 0,
7635 +       PCIPBAC_msi_m                   = 0x00000001,
7636 +       PCIPBAC_p_b                     = 1,
7637 +       PCIPBAC_p_m                     = 0x00000002,
7638 +       PCIPBAC_size_b                  = 2,
7639 +       PCIPBAC_size_m                  = 0x0000007c,
7640 +       PCIPBAC_sb_b                    = 7,
7641 +       PCIPBAC_sb_m                    = 0x00000080,
7642 +       PCIPBAC_pp_b                    = 8,
7643 +       PCIPBAC_pp_m                    = 0x00000100,
7644 +       PCIPBAC_mr_b                    = 9,
7645 +       PCIPBAC_mr_m                    = 0x00000600,
7646 +               PCIPBAC_mr_read_v       =0,     //no prefetching
7647 +               PCIPBAC_mr_readLine_v   =1,
7648 +               PCIPBAC_mr_readMult_v   =2,
7649 +       PCIPBAC_mrl_b                   = 11,
7650 +       PCIPBAC_mrl_m                   = 0x00000800,
7651 +       PCIPBAC_mrm_b                   = 12,
7652 +       PCIPBAC_mrm_m                   = 0x00001000,
7653 +       PCIPBAC_trp_b                   = 13,
7654 +       PCIPBAC_trp_m                   = 0x00002000,
7655 +
7656 +       PCFG40_trdyTimeout_b            = 0,
7657 +       PCFG40_trdyTimeout_m            = 0x000000ff,
7658 +       PCFG40_retryLim_b               = 8,
7659 +       PCFG40_retryLim_m               = 0x0000ff00,
7660 +};
7661 +
7662 +/*******************************************************************************
7663 + *
7664 + * PCI Local Base Address [0|1|2|3] Register
7665 + *
7666 + ******************************************************************************/
7667 +enum {
7668 +       PCILBA_baddr_b          = 0,            // In PCI_t -> pcilba [] .a
7669 +       PCILBA_baddr_m          = 0xffffff00,
7670 +} ;
7671 +/*******************************************************************************
7672 + *
7673 + * PCI Local Base Address Control Register
7674 + *
7675 + ******************************************************************************/
7676 +enum {
7677 +       PCILBAC_msi_b           = 0,            // In pPci->pcilba[i].c
7678 +       PCILBAC_msi_m           = 0x00000001,
7679 +               PCILBAC_msi_mem_v       = 0,
7680 +               PCILBAC_msi_io_v        = 1,
7681 +       PCILBAC_size_b          = 2,    // In pPci->pcilba[i].c
7682 +       PCILBAC_size_m          = 0x0000007c,
7683 +       PCILBAC_sb_b            = 7,    // In pPci->pcilba[i].c
7684 +       PCILBAC_sb_m            = 0x00000080,
7685 +       PCILBAC_rt_b            = 8,    // In pPci->pcilba[i].c
7686 +       PCILBAC_rt_m            = 0x00000100,
7687 +               PCILBAC_rt_noprefetch_v = 0, // mem read
7688 +               PCILBAC_rt_prefetch_v   = 1, // mem readline
7689 +} ;
7690 +
7691 +/*******************************************************************************
7692 + *
7693 + * PCI Local Base Address [0|1|2|3] Mapping Register
7694 + *
7695 + ******************************************************************************/
7696 +enum {
7697 +       PCILBAM_maddr_b         = 8,
7698 +       PCILBAM_maddr_m         = 0xffffff00,
7699 +} ;
7700 +
7701 +/*******************************************************************************
7702 + *
7703 + * PCI Decoupled Access Control Register
7704 + *
7705 + ******************************************************************************/
7706 +enum {
7707 +       PCIDAC_den_b            = 0,
7708 +       PCIDAC_den_m            = 0x00000001,
7709 +} ;
7710 +
7711 +/*******************************************************************************
7712 + *
7713 + * PCI Decoupled Access Status Register
7714 + *
7715 + ******************************************************************************/
7716 +enum {
7717 +       PCIDAS_d_b      = 0,
7718 +       PCIDAS_d_m      = 0x00000001,
7719 +       PCIDAS_b_b      = 1,
7720 +       PCIDAS_b_m      = 0x00000002,
7721 +       PCIDAS_e_b      = 2,
7722 +       PCIDAS_e_m      = 0x00000004,
7723 +       PCIDAS_ofe_b    = 3,
7724 +       PCIDAS_ofe_m    = 0x00000008,
7725 +       PCIDAS_off_b    = 4,
7726 +       PCIDAS_off_m    = 0x00000010,
7727 +       PCIDAS_ife_b    = 5,
7728 +       PCIDAS_ife_m    = 0x00000020,
7729 +       PCIDAS_iff_b    = 6,
7730 +       PCIDAS_iff_m    = 0x00000040,
7731 +} ;
7732 +
7733 +/*******************************************************************************
7734 + *
7735 + * PCI DMA Channel 8 Configuration Register
7736 + *
7737 + ******************************************************************************/
7738 +enum
7739 +{
7740 +       PCIDMA8C_mbs_b  = 0,            // Maximum Burst Size.
7741 +       PCIDMA8C_mbs_m  = 0x00000fff,   // { pcidma8c }
7742 +       PCIDMA8C_our_b  = 12,           // Optimize Unaligned Burst Reads.
7743 +       PCIDMA8C_our_m  = 0x00001000,   // { pcidma8c }
7744 +} ;
7745 +
7746 +/*******************************************************************************
7747 + *
7748 + * PCI DMA Channel 9 Configuration Register
7749 + *
7750 + ******************************************************************************/
7751 +enum
7752 +{
7753 +       PCIDMA9C_mbs_b  = 0,            // Maximum Burst Size.
7754 +       PCIDMA9C_mbs_m  = 0x00000fff, // { pcidma9c }
7755 +} ;
7756 +
7757 +/*******************************************************************************
7758 + *
7759 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
7760 + *
7761 + ******************************************************************************/
7762 +enum {
7763 +       PCIDMAD_pt_b            = 22,           // in DEVCMD field (descriptor)
7764 +       PCIDMAD_pt_m            = 0x00c00000,   // preferred transaction field
7765 +               // These are for reads (DMA channel 8)
7766 +               PCIDMAD_devcmd_mr_v     = 0,    //memory read
7767 +               PCIDMAD_devcmd_mrl_v    = 1,    //memory read line
7768 +               PCIDMAD_devcmd_mrm_v    = 2,    //memory read multiple
7769 +               PCIDMAD_devcmd_ior_v    = 3,    //I/O read
7770 +               // These are for writes (DMA channel 9)
7771 +               PCIDMAD_devcmd_mw_v     = 0,    //memory write
7772 +               PCIDMAD_devcmd_mwi_v    = 1,    //memory write invalidate
7773 +               PCIDMAD_devcmd_iow_v    = 3,    //I/O write
7774 +
7775 +       // Swap byte field applies to both DMA channel 8 and 9
7776 +       PCIDMAD_sb_b            = 24,           // in DEVCMD field (descriptor)
7777 +       PCIDMAD_sb_m            = 0x01000000,   // swap byte field
7778 +} ;
7779 +
7780 +
7781 +/*******************************************************************************
7782 + *
7783 + * PCI Target Control Register
7784 + *
7785 + ******************************************************************************/
7786 +enum
7787 +{
7788 +       PCITC_rtimer_b          = 0,            // In PCITC_t -> pcitc
7789 +       PCITC_rtimer_m          = 0x000000ff,
7790 +       PCITC_dtimer_b          = 8,            // In PCITC_t -> pcitc
7791 +       PCITC_dtimer_m          = 0x0000ff00,
7792 +       PCITC_rdr_b             = 18,           // In PCITC_t -> pcitc
7793 +       PCITC_rdr_m             = 0x00040000,
7794 +       PCITC_ddt_b             = 19,           // In PCITC_t -> pcitc
7795 +       PCITC_ddt_m             = 0x00080000,
7796 +} ;
7797 +/*******************************************************************************
7798 + *
7799 + * PCI messaging unit [applies to both inbound and outbound registers ]
7800 + *
7801 + ******************************************************************************/
7802 +enum
7803 +{
7804 +       PCIM_m0_b       = 0,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7805 +       PCIM_m0_m       = 0x00000001,   // inbound or outbound message 0
7806 +       PCIM_m1_b       = 1,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7807 +       PCIM_m1_m       = 0x00000002,   // inbound or outbound message 1
7808 +       PCIM_db_b       = 2,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7809 +       PCIM_db_m       = 0x00000004,   // inbound or outbound doorbell
7810 +};
7811 +
7812 +
7813 +
7814 +
7815 +
7816 +
7817 +#define PCI_MSG_VirtualAddress      0xB8088010
7818 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
7819 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
7820 +
7821 +#define PCIM_SHFT              0x6
7822 +#define PCIM_BIT_LEN           0x7
7823 +#define PCIM_H_EA              0x3
7824 +#define PCIM_H_IA_FIX          0x4
7825 +#define PCIM_H_IA_RR           0x5
7826 +#if 0
7827 +#define PCI_ADDR_START         0x13000000
7828 +#endif
7829 +
7830 +#define PCI_ADDR_START         0x50000000
7831 +
7832 +#define CPUTOPCI_MEM_WIN       0x02000000
7833 +#define CPUTOPCI_IO_WIN                0x00100000
7834 +#define PCILBA_SIZE_SHFT       2
7835 +#define PCILBA_SIZE_MASK       0x1F
7836 +#define SIZE_256MB             0x1C
7837 +#define SIZE_128MB             0x1B
7838 +#define SIZE_64MB               0x1A
7839 +#define SIZE_32MB              0x19
7840 +#define SIZE_16MB               0x18
7841 +#define SIZE_4MB               0x16
7842 +#define SIZE_2MB               0x15
7843 +#define SIZE_1MB               0x14
7844 +#define KORINA_CONFIG0_ADDR    0x80000000
7845 +#define KORINA_CONFIG1_ADDR    0x80000004
7846 +#define KORINA_CONFIG2_ADDR    0x80000008
7847 +#define KORINA_CONFIG3_ADDR    0x8000000C
7848 +#define KORINA_CONFIG4_ADDR    0x80000010
7849 +#define KORINA_CONFIG5_ADDR    0x80000014
7850 +#define KORINA_CONFIG6_ADDR    0x80000018
7851 +#define KORINA_CONFIG7_ADDR    0x8000001C
7852 +#define KORINA_CONFIG8_ADDR    0x80000020
7853 +#define KORINA_CONFIG9_ADDR    0x80000024
7854 +#define KORINA_CONFIG10_ADDR   0x80000028
7855 +#define KORINA_CONFIG11_ADDR   0x8000002C
7856 +#define KORINA_CONFIG12_ADDR   0x80000030
7857 +#define KORINA_CONFIG13_ADDR   0x80000034
7858 +#define KORINA_CONFIG14_ADDR   0x80000038
7859 +#define KORINA_CONFIG15_ADDR   0x8000003C
7860 +#define KORINA_CONFIG16_ADDR   0x80000040
7861 +#define KORINA_CONFIG17_ADDR   0x80000044
7862 +#define KORINA_CONFIG18_ADDR   0x80000048
7863 +#define KORINA_CONFIG19_ADDR   0x8000004C
7864 +#define KORINA_CONFIG20_ADDR   0x80000050
7865 +#define KORINA_CONFIG21_ADDR   0x80000054
7866 +#define KORINA_CONFIG22_ADDR   0x80000058
7867 +#define KORINA_CONFIG23_ADDR   0x8000005C
7868 +#define KORINA_CONFIG24_ADDR   0x80000060
7869 +#define KORINA_CONFIG25_ADDR   0x80000064
7870 +#define KORINA_CMD             (PCFG04_command_ioena_m | \
7871 +                                PCFG04_command_memena_m | \
7872 +                                PCFG04_command_bmena_m | \
7873 +                                PCFG04_command_mwinv_m | \
7874 +                                PCFG04_command_parena_m | \
7875 +                                PCFG04_command_serrena_m )
7876 +
7877 +#define KORINA_STAT            (PCFG04_status_mdpe_m | \
7878 +                                PCFG04_status_sta_m  | \
7879 +                                PCFG04_status_rta_m  | \
7880 +                                PCFG04_status_rma_m  | \
7881 +                                PCFG04_status_sse_m  | \
7882 +                                PCFG04_status_pe_m)
7883 +
7884 +#define KORINA_CNFG1           ((KORINA_STAT<<16)|KORINA_CMD)
7885 +
7886 +#define KORINA_REVID           0
7887 +#define KORINA_CLASS_CODE      0
7888 +#define KORINA_CNFG2           ((KORINA_CLASS_CODE<<8) | \
7889 +                                 KORINA_REVID)
7890 +
7891 +#define KORINA_CACHE_LINE_SIZE 4
7892 +#define KORINA_MASTER_LAT      0x3c
7893 +#define KORINA_HEADER_TYPE     0
7894 +#define KORINA_BIST            0
7895 +
7896 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
7897 +                     (KORINA_HEADER_TYPE<<16) | \
7898 +                     (KORINA_MASTER_LAT<<8) | \
7899 +                     KORINA_CACHE_LINE_SIZE )
7900 +
7901 +#define KORINA_BAR0    0x00000008 /* 128 MB Memory */
7902 +#define KORINA_BAR1    0x18800001 /* 1 MB IO */
7903 +#define KORINA_BAR2    0x18000001 /* 2 MB IO window for Korina
7904 +                                       internal Registers */
7905 +#define KORINA_BAR3    0x48000008 /* Spare 128 MB Memory */
7906 +
7907 +#define KORINA_CNFG4   KORINA_BAR0
7908 +#define KORINA_CNFG5    KORINA_BAR1
7909 +#define KORINA_CNFG6   KORINA_BAR2
7910 +#define KORINA_CNFG7   KORINA_BAR3
7911 +
7912 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
7913 +#define KORINA_SUBSYSTEM_ID    0x0214
7914 +#define KORINA_CNFG8           0
7915 +#define KORINA_CNFG9           0
7916 +#define KORINA_CNFG10          0
7917 +#define KORINA_CNFG11  ((KORINA_SUBSYS_VENDOR_ID<<16) | \
7918 +                         KORINA_SUBSYSTEM_ID)
7919 +#define KORINA_INT_LINE                1
7920 +#define KORINA_INT_PIN         1
7921 +#define KORINA_MIN_GNT         8
7922 +#define KORINA_MAX_LAT         0x38
7923 +#define KORINA_CNFG12          0
7924 +#define KORINA_CNFG13          0
7925 +#define KORINA_CNFG14          0
7926 +#define KORINA_CNFG15  ((KORINA_MAX_LAT<<24) | \
7927 +                        (KORINA_MIN_GNT<<16) | \
7928 +                        (KORINA_INT_PIN<<8)  | \
7929 +                         KORINA_INT_LINE)
7930 +#define        KORINA_RETRY_LIMIT      0x80
7931 +#define KORINA_TRDY_LIMIT      0x80
7932 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
7933 +                       KORINA_TRDY_LIMIT)
7934 +#define PCI_PBAxC_R            0x0
7935 +#define PCI_PBAxC_RL           0x1
7936 +#define PCI_PBAxC_RM           0x2
7937 +#define SIZE_SHFT              2
7938 +
7939 +#if defined(__MIPSEB__)
7940 +#define KORINA_PBA0C   ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
7941 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7942 +                         PCIPBAC_pp_m | \
7943 +                         (SIZE_128MB<<SIZE_SHFT) | \
7944 +                          PCIPBAC_p_m)
7945 +#else
7946 +#define KORINA_PBA0C   ( PCIPBAC_mrl_m | \
7947 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7948 +                         PCIPBAC_pp_m | \
7949 +                         (SIZE_128MB<<SIZE_SHFT) | \
7950 +                          PCIPBAC_p_m)
7951 +#endif
7952 +#define KORINA_CNFG17  KORINA_PBA0C
7953 +#define KORINA_PBA0M   0x0
7954 +#define KORINA_CNFG18  KORINA_PBA0M
7955 +
7956 +#if defined(__MIPSEB__)
7957 +#define KORINA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7958 +                         PCIPBAC_msi_m)
7959 +#else
7960 +#define KORINA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | \
7961 +                         PCIPBAC_msi_m)
7962 +#endif
7963 +#define KORINA_CNFG19  KORINA_PBA1C
7964 +#define KORINA_PBA1M   0x0
7965 +#define KORINA_CNFG20  KORINA_PBA1M
7966 +
7967 +#if defined(__MIPSEB__)
7968 +#define KORINA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7969 +                         PCIPBAC_msi_m)
7970 +#else
7971 +#define KORINA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | \
7972 +                         PCIPBAC_msi_m)
7973 +#endif
7974 +#define KORINA_CNFG21  KORINA_PBA2C
7975 +#define KORINA_PBA2M   0x18000000
7976 +#define KORINA_CNFG22  KORINA_PBA2M
7977 +#define KORINA_PBA3C   0
7978 +#define KORINA_CNFG23  KORINA_PBA3C
7979 +#define KORINA_PBA3M   0
7980 +#define KORINA_CNFG24  KORINA_PBA3M
7981 +
7982 +
7983 +
7984 +#define        PCITC_DTIMER_VAL        8
7985 +#define PCITC_RTIMER_VAL       0x10
7986 +
7987 +
7988 +
7989 +
7990 +#endif // __IDT_PCI_H__
7991 +
7992 +
7993 +
7994 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_rst.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h
7995 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_rst.h      1970-01-01 01:00:00.000000000 +0100
7996 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 2006-06-18 12:44:28.000000000 +0200
7997 @@ -0,0 +1,119 @@
7998 +/**************************************************************************
7999 + *
8000 + *  BRIEF MODULE DESCRIPTION
8001 + *   Reset register definitions.
8002 + *
8003 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8004 + *
8005 + *  This program is free software; you can redistribute  it and/or modify it
8006 + *  under  the terms of  the GNU General  Public License as published by the
8007 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8008 + *  option) any later version.
8009 + *
8010 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8011 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8012 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8013 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8014 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8015 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8016 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8017 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8018 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8019 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8020 + *
8021 + *  You should have received a copy of the  GNU General Public License along
8022 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8023 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8024 + *
8025 + *
8026 + **************************************************************************
8027 + * May 2004 rkt, neb.
8028 + *
8029 + * Initial Release
8030 + *
8031 + *
8032 + *
8033 + **************************************************************************
8034 + */
8035 +
8036 +#ifndef __IDT_RST_H__
8037 +#define __IDT_RST_H__
8038 +
8039 +enum
8040 +{
8041 +       RST0_PhysicalAddress    = 0x18000000,
8042 +       RST_PhysicalAddress     = RST0_PhysicalAddress,         // Default
8043 +
8044 +       RST0_VirtualAddress     = 0xb8000000,
8045 +       RST_VirtualAddress      = RST0_VirtualAddress,          // Default
8046 +} ;
8047 +
8048 +typedef struct RST_s
8049 +{
8050 +       u32     filler [0x0006] ;
8051 +       u32     sysid ;
8052 +       u32     filler2 [0x2000-8] ;            // Pad out to offset 0x8000
8053 +       u32     reset ;
8054 +       u32     bcv ;
8055 +       u32     cea ;
8056 +} volatile * RST_t ;
8057 +
8058 +enum
8059 +{
8060 +       SYSID_rev_b             = 0,
8061 +       SYSID_rev_m             = 0x000000ff,
8062 +       SYSID_imp_b             = 8,
8063 +       SYSID_imp_m             = 0x000fff00,
8064 +       SYSID_vendor_b          = 8,
8065 +       SYSID_vendor_m          = 0xfff00000,
8066 +
8067 +       BCV_pll_b               = 0,
8068 +       BCV_pll_m               = 0x0000000f,
8069 +               BCV_pll_PLLBypass_v     = 0x0,  // PCLK=1*CLK.
8070 +               BCV_pll_Mul3_v          = 0x1,  // PCLK=3*CLK.
8071 +               BCV_pll_Mul4_v          = 0x2,  // PCLK=4*CLK.
8072 +               BCV_pll_SlowMul5_v      = 0x3,  // PCLK=5*CLK.
8073 +               BCV_pll_Mul5_v          = 0x4,  // PCLK=5*CLK.
8074 +               BCV_pll_SlowMul6_v      = 0x5,  // PCLK=6*CLK.
8075 +               BCV_pll_Mul6_v          = 0x6,  // PCLK=6*CLK.
8076 +               BCV_pll_Mul8_v          = 0x7,  // PCLK=8*CLK.
8077 +               BCV_pll_Mul10_v         = 0x8,  // PCLK=10*CLK.
8078 +               BCV_pll_Res9_v          = 0x9,
8079 +               BCV_pll_Res10_v         = 0xa,
8080 +               BCV_pll_Res11_v         = 0xb,
8081 +               BCV_pll_Res12_v         = 0xc,
8082 +               BCV_pll_Res13_v         = 0xd,
8083 +               BCV_pll_Res14_v         = 0xe,
8084 +               BCV_pll_Res15_v         = 0xf,
8085 +       BCV_clkDiv_b            = 4,
8086 +       BCV_clkDiv_m            = 0x00000030,
8087 +               BCV_clkDiv_Div1_v       = 0x0,
8088 +               BCV_clkDiv_Div2_v       = 0x1,
8089 +               BCV_clkDiv_Div4_v       = 0x2,
8090 +               BCV_clkDiv_Res3_v       = 0x3,
8091 +       BCV_bigEndian_b         = 6,
8092 +       BCV_bigEndian_m         = 0x00000040,
8093 +       BCV_resetFast_b         = 7,
8094 +       BCV_resetFast_m         = 0x00000080,
8095 +       BCV_pciMode_b           = 8,
8096 +       BCV_pciMode_m           = 0x00000700,
8097 +               BCV_pciMode_disabled_v  = 0,    // PCI is disabled.
8098 +               BCV_pciMode_tnr_v       = 1,    // satellite Target Not Ready.
8099 +               BCV_pciMode_suspended_v = 2,    // satellite with suspended CPU.
8100 +               BCV_pciMode_external_v  = 3,    // host, external arbiter.
8101 +               BCV_pciMode_fixed_v     = 4,    // host, fixed priority arbiter.
8102 +               BCV_pciMode_roundRobin_v= 5,    // host, round robin arbiter.
8103 +               BCV_pciMode_res6_v      = 6,
8104 +               BCV_pciMode_res7_v      = 7,
8105 +       BCV_watchDisable_b      = 11,
8106 +       BCV_watchDisable_m      = 0x00000800,
8107 +       BCV_res12_b             = 12,
8108 +       BCV_res12_m             = 0x00001000,
8109 +       BCV_res13_b             = 13,
8110 +       BCV_res13_m             = 0x00002000,
8111 +       BCV_res14_b             = 14,
8112 +       BCV_res14_m             = 0x00004000,
8113 +       BCV_res15_b             = 15,
8114 +       BCV_res15_m             = 0x00008000,
8115 +} ;
8116 +#endif // __IDT_RST_H__
8117 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_spi.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h
8118 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_spi.h      1970-01-01 01:00:00.000000000 +0100
8119 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 2006-06-18 12:44:28.000000000 +0200
8120 @@ -0,0 +1,120 @@
8121 +/**************************************************************************
8122 + *
8123 + *  BRIEF MODULE DESCRIPTION
8124 + *   Serial Peripheral Interface register definitions.
8125 + *
8126 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8127 + *
8128 + *  This program is free software; you can redistribute  it and/or modify it
8129 + *  under  the terms of  the GNU General  Public License as published by the
8130 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8131 + *  option) any later version.
8132 + *
8133 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8134 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8135 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8136 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8137 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8138 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8139 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8140 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8141 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8142 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8143 + *
8144 + *  You should have received a copy of the  GNU General Public License along
8145 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8146 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8147 + *
8148 + *
8149 + **************************************************************************
8150 + * May 2004 rkt, neb.
8151 + *
8152 + * Initial Release
8153 + *
8154 + *
8155 + *
8156 + **************************************************************************
8157 + */
8158 +
8159 +#ifndef __IDT_SPI_H__
8160 +#define __IDT_SPI_H__
8161 +
8162 +enum
8163 +{
8164 +       SPI0_PhysicalAddress    = 0x18070000,
8165 +       SPI_PhysicalAddress     = SPI0_PhysicalAddress,
8166 +
8167 +       SPI0_VirtualAddress     = 0xB8070000,
8168 +       SPI_VirtualAddress      = SPI0_VirtualAddress,
8169 +} ;
8170 +
8171 +typedef struct
8172 +{
8173 +       u32 spcp ;      // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
8174 +       u32 spc ;       // spi control reg use SPC_
8175 +       u32 sps ;       // spi status reg use SPS_
8176 +       u32 spd ;       // spi data reg use SPD_
8177 +       u32 siofunc ;   // serial IO function use SIOFUNC_
8178 +       u32 siocfg ;    // serial IO config use SIOCFG_
8179 +       u32 siod;       // serial IO data use SIOD_
8180 +} volatile *SPI_t ;
8181 +
8182 +enum
8183 +{
8184 +       SPCP_div_b       = 0,
8185 +       SPCP_div_m       = 0x000000ff,
8186 +       SPC_spr_b       = 0,
8187 +       SPC_spr_m       = 0x00000003,
8188 +            SPC_spr_div2_v  = 0,
8189 +            SPC_spr_div4_v  = 1,
8190 +            SPC_spr_div16_v = 2,
8191 +            SPC_spr_div32_v = 3,
8192 +       SPC_cpha_b      = 2,
8193 +       SPC_cpha_m      = 0x00000004,
8194 +       SPC_cpol_b      = 3,
8195 +       SPC_cpol_m      = 0x00000008,
8196 +       SPC_mstr_b      = 4,
8197 +       SPC_mstr_m      = 0x00000010,
8198 +       SPC_spe_b       = 6,
8199 +       SPC_spe_m       = 0x00000040,
8200 +       SPC_spie_b      = 7,
8201 +       SPC_spie_m      = 0x00000080,
8202 +
8203 +       SPS_modf_b      = 4,
8204 +       SPS_modf_m      = 0x00000010,
8205 +       SPS_wcol_b      = 6,
8206 +       SPS_wcol_m      = 0x00000040,
8207 +       SPS_spif_b      = 7,
8208 +       SPS_spif_m      = 0x00000070,
8209 +
8210 +       SPD_data_b      = 0,
8211 +       SPD_data_m      = 0x000000ff,
8212 +
8213 +       SIOFUNC_sdo_b       = 0,
8214 +       SIOFUNC_sdo_m       = 0x00000001,
8215 +       SIOFUNC_sdi_b       = 1,
8216 +       SIOFUNC_sdi_m       = 0x00000002,
8217 +       SIOFUNC_sck_b       = 2,
8218 +       SIOFUNC_sck_m       = 0x00000004,
8219 +       SIOFUNC_pci_b       = 3,
8220 +       SIOFUNC_pci_m       = 0x00000008,
8221 +
8222 +       SIOCFG_sdo_b       = 0,
8223 +       SIOCFG_sdo_m       = 0x00000001,
8224 +       SIOCFG_sdi_b       = 1,
8225 +       SIOCFG_sdi_m       = 0x00000002,
8226 +       SIOCFG_sck_b       = 2,
8227 +       SIOCFG_sck_m       = 0x00000004,
8228 +       SIOCFG_pci_b       = 3,
8229 +       SIOCFG_pci_m       = 0x00000008,
8230 +
8231 +       SIOD_sdo_b       = 0,
8232 +       SIOD_sdo_m       = 0x00000001,
8233 +       SIOD_sdi_b       = 1,
8234 +       SIOD_sdi_m       = 0x00000002,
8235 +       SIOD_sck_b       = 2,
8236 +       SIOD_sck_m       = 0x00000004,
8237 +       SIOD_pci_b       = 3,
8238 +       SIOD_pci_m       = 0x00000008,
8239 +} ;
8240 +#endif // __IDT_SPI_H__
8241 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_timer.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h
8242 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_timer.h    1970-01-01 01:00:00.000000000 +0100
8243 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h       2006-06-18 12:44:28.000000000 +0200
8244 @@ -0,0 +1,91 @@
8245 +/**************************************************************************
8246 + *
8247 + *  BRIEF MODULE DESCRIPTION
8248 + *   Definitions for timer registers
8249 + *
8250 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8251 + *
8252 + *  This program is free software; you can redistribute  it and/or modify it
8253 + *  under  the terms of  the GNU General  Public License as published by the
8254 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8255 + *  option) any later version.
8256 + *
8257 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8258 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8259 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8260 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8261 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8262 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8263 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8264 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8265 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8266 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8267 + *
8268 + *  You should have received a copy of the  GNU General Public License along
8269 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8270 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8271 + *
8272 + *
8273 + **************************************************************************
8274 + * May 2004 rkt,neb.
8275 + *
8276 + * Initial Release
8277 + *
8278 + *
8279 + *
8280 + **************************************************************************
8281 + */
8282 +
8283 +#ifndef __IDT_TIM_H__
8284 +#define __IDT_TIM_H__
8285 +
8286 +enum
8287 +{
8288 +       TIM0_PhysicalAddress    = 0x18028000,
8289 +       TIM_PhysicalAddress     = TIM0_PhysicalAddress,         // Default
8290 +
8291 +       TIM0_VirtualAddress     = 0xb8028000,
8292 +       TIM_VirtualAddress      = TIM0_VirtualAddress,          // Default
8293 +} ;
8294 +
8295 +enum
8296 +{
8297 +       TIM_Count = 3,
8298 +} ;
8299 +
8300 +struct TIM_CNTR_s
8301 +{
8302 +  u32 count ;
8303 +  u32 compare ;
8304 +  u32 ctc ;    //use CTC_
8305 +} ;
8306 +
8307 +typedef struct TIM_s
8308 +{
8309 +  struct TIM_CNTR_s    tim [TIM_Count] ;
8310 +  u32                  rcount ;        //use RCOUNT_
8311 +  u32                  rcompare ;      //use RCOMPARE_
8312 +  u32                  rtc ;           //use RTC_
8313 +} volatile * TIM_t ;
8314 +
8315 +enum
8316 +{
8317 +  CTC_en_b     = 0,
8318 +  CTC_en_m     = 0x00000001,
8319 +  CTC_to_b     = 1,
8320 +  CTC_to_m     = 0x00000002,
8321 +
8322 +  RCOUNT_count_b               = 0,
8323 +  RCOUNT_count_m               = 0x0000ffff,
8324 +  RCOMPARE_compare_b   = 0,
8325 +  RCOMPARE_compare_m   = 0x0000ffff,
8326 +  RTC_ce_b             = 0,
8327 +  RTC_ce_m             = 0x00000001,
8328 +  RTC_to_b             = 1,
8329 +  RTC_to_m             = 0x00000002,
8330 +  RTC_rqe_b            = 2,
8331 +  RTC_rqe_m            = 0x00000004,
8332 +
8333 +} ;
8334 +#endif // __IDT_TIM_H__
8335 +
8336 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_uart.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h
8337 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_uart.h     1970-01-01 01:00:00.000000000 +0100
8338 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h        2006-06-18 12:44:28.000000000 +0200
8339 @@ -0,0 +1,189 @@
8340 +/**************************************************************************
8341 + *
8342 + *  BRIEF MODULE DESCRIPTION
8343 + *   UART register definitions
8344 + *
8345 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8346 + *
8347 + *  This program is free software; you can redistribute  it and/or modify it
8348 + *  under  the terms of  the GNU General  Public License as published by the
8349 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8350 + *  option) any later version.
8351 + *
8352 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8353 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8354 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8355 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8356 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8357 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8358 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8359 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8360 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8361 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8362 + *
8363 + *  You should have received a copy of the  GNU General Public License along
8364 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8365 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8366 + *
8367 + *
8368 + **************************************************************************
8369 + * May 2004 rkt, neb.
8370 + *
8371 + * Initial Release
8372 + *
8373 + *
8374 + *
8375 + **************************************************************************
8376 + */
8377 +
8378 +#ifndef __IDT_UART_H__
8379 +#define __IDT_UART_H__
8380 +
8381 +enum
8382 +{
8383 +       UART0_PhysicalAddress   = 0x1c000000,
8384 +       UART_PhysicalAddress    = UART0_PhysicalAddress,        // Default
8385 +
8386 +       UART0_VirtualAddress    = 0xbc000000,
8387 +       UART_VirtualAddress     = UART0_VirtualAddress,         // Default
8388 +} ;
8389 +
8390 +/*
8391 + * Register definitions are in bytes so we can handle endian problems.
8392 + */
8393 +
8394 +typedef struct UART_s
8395 +{
8396 +       union
8397 +       {
8398 +               u32 const       uartrb ;        // 0x00 - DLAB=0, read.
8399 +               u32             uartth ;        // 0x00 - DLAB=0, write.
8400 +               u32             uartdll ;       // 0x00 - DLAB=1, read/write.
8401 +       } ;
8402 +
8403 +       union
8404 +       {
8405 +               u32             uartie ;        // 0x04 - DLAB=0, read/write.
8406 +               u32             uartdlh ;       // 0x04 - DLAB=1, read/write.
8407 +       } ;
8408 +       union
8409 +       {
8410 +               u32 const       uartii ;        // 0x08 - DLAB=0, read.
8411 +               u32             uartfc ;        // 0x08 - DLAB=0, write.
8412 +       } ;
8413 +
8414 +       u32             uartlc ;                // 0x0c
8415 +       u32             uartmc ;                // 0x10
8416 +       u32             uartls ;                // 0x14
8417 +       u32             uartms ;                // 0x18
8418 +       u32             uarts ;                 // 0x1c
8419 +} volatile *UART_t ;
8420 +
8421 +// Reset registers.
8422 +typedef u32    volatile *UARTRR_t ;
8423 +
8424 +enum
8425 +{
8426 +       UARTIE_rda_b    = 0,
8427 +       UARTIE_rda_m    = 0x00000001,
8428 +       UARTIE_the_b    = 1,
8429 +       UARTIE_the_m    = 0x00000002,
8430 +       UARTIE_rls_b    = 2,
8431 +       UARTIE_rls_m    = 0x00000004,
8432 +       UARTIE_ems_b    = 3,
8433 +       UARTIE_ems_m    = 0x00000008,
8434 +
8435 +       UARTII_pi_b     = 0,
8436 +       UARTII_pi_m     = 0x00000001,
8437 +       UARTII_iid_b    = 1,
8438 +       UARTII_iid_m    = 0x0000000e,
8439 +               UARTII_iid_ms_v         = 0,    // Modem stat-CTS,DSR,RI or DCD.
8440 +               UARTII_iid_thre_v       = 1,    // Trans. Holding Reg. empty.
8441 +               UARTII_iid_rda_v        = 2,    // Receive data available
8442 +               UARTII_iid_rls_v        = 3,    // Overrun, parity, etc, error.
8443 +               UARTII_iid_res4_v       = 4,    // reserved.
8444 +               UARTII_iid_res5_v       = 5,    // reserved.
8445 +               UARTII_iid_cto_v        = 6,    // Character timeout.
8446 +               UARTII_iid_res7_v       = 7,    // reserved.
8447 +
8448 +       UARTFC_en_b     = 0,
8449 +       UARTFC_en_m     = 0x00000001,
8450 +       UARTFC_rr_b     = 1,
8451 +       UARTFC_rr_m     = 0x00000002,
8452 +       UARTFC_tr_b     = 2,
8453 +       UARTFC_tr_m     = 0x00000004,
8454 +       UARTFC_dms_b    = 3,
8455 +       UARTFC_dms_m    = 0x00000008,
8456 +       UARTFC_rt_b     = 6,
8457 +       UARTFC_rt_m     = 0x000000c0,
8458 +               UARTFC_rt_1Byte_v       = 0,
8459 +               UARTFC_rt_4Byte_v       = 1,
8460 +               UARTFC_rt_8Byte_v       = 2,
8461 +               UARTFC_rt_14Byte_v      = 3,
8462 +
8463 +       UARTLC_wls_b    = 0,
8464 +       UARTLC_wls_m    = 0x00000003,
8465 +               UARTLC_wls_5Bits_v      = 0,
8466 +               UARTLC_wls_6Bits_v      = 1,
8467 +               UARTLC_wls_7Bits_v      = 2,
8468 +               UARTLC_wls_8Bits_v      = 3,
8469 +       UARTLC_stb_b    = 2,
8470 +       UARTLC_stb_m    = 0x00000004,
8471 +       UARTLC_pen_b    = 3,
8472 +       UARTLC_pen_m    = 0x00000008,
8473 +       UARTLC_eps_b    = 4,
8474 +       UARTLC_eps_m    = 0x00000010,
8475 +       UARTLC_sp_b     = 5,
8476 +       UARTLC_sp_m     = 0x00000020,
8477 +       UARTLC_sb_b     = 6,
8478 +       UARTLC_sb_m     = 0x00000040,
8479 +       UARTLC_dlab_b   = 7,
8480 +       UARTLC_dlab_m   = 0x00000080,
8481 +
8482 +       UARTMC_dtr_b    = 0,
8483 +       UARTMC_dtr_m    = 0x00000001,
8484 +       UARTMC_rts_b    = 1,
8485 +       UARTMC_rts_m    = 0x00000002,
8486 +       UARTMC_o1_b     = 2,
8487 +       UARTMC_o1_m     = 0x00000004,
8488 +       UARTMC_o2_b     = 3,
8489 +       UARTMC_o2_m     = 0x00000008,
8490 +       UARTMC_lp_b     = 4,
8491 +       UARTMC_lp_m     = 0x00000010,
8492 +
8493 +       UARTLS_dr_b     = 0,
8494 +       UARTLS_dr_m     = 0x00000001,
8495 +       UARTLS_oe_b     = 1,
8496 +       UARTLS_oe_m     = 0x00000002,
8497 +       UARTLS_pe_b     = 2,
8498 +       UARTLS_pe_m     = 0x00000004,
8499 +       UARTLS_fe_b     = 3,
8500 +       UARTLS_fe_m     = 0x00000008,
8501 +       UARTLS_bi_b     = 4,
8502 +       UARTLS_bi_m     = 0x00000010,
8503 +       UARTLS_thr_b    = 5,
8504 +       UARTLS_thr_m    = 0x00000020,
8505 +       UARTLS_te_b     = 6,
8506 +       UARTLS_te_m     = 0x00000040,
8507 +       UARTLS_rfe_b    = 7,
8508 +       UARTLS_rfe_m    = 0x00000080,
8509 +
8510 +       UARTMS_dcts_b   = 0,
8511 +       UARTMS_dcts_m   = 0x00000001,
8512 +       UARTMS_ddsr_b   = 1,
8513 +       UARTMS_ddsr_m   = 0x00000002,
8514 +       UARTMS_teri_b   = 2,
8515 +       UARTMS_teri_m   = 0x00000004,
8516 +       UARTMS_ddcd_b   = 3,
8517 +       UARTMS_ddcd_m   = 0x00000008,
8518 +       UARTMS_cts_b    = 4,
8519 +       UARTMS_cts_m    = 0x00000010,
8520 +       UARTMS_dsr_b    = 5,
8521 +       UARTMS_dsr_m    = 0x00000020,
8522 +       UARTMS_ri_b     = 6,
8523 +       UARTMS_ri_m     = 0x00000040,
8524 +       UARTMS_dcd_b    = 7,
8525 +       UARTMS_dcd_m    = 0x00000080,
8526 +} ;
8527 +
8528 +#endif // __IDT_UART_H__
8529 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h
8530 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma.h      1970-01-01 01:00:00.000000000 +0100
8531 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 2006-06-18 12:44:28.000000000 +0200
8532 @@ -0,0 +1,231 @@
8533 +/**************************************************************************
8534 + *
8535 + *  BRIEF MODULE DESCRIPTION
8536 + *   Register definitions for  IDT RC32438 DMA.
8537 + *
8538 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8539 + *
8540 + *  This program is free software; you can redistribute  it and/or modify it
8541 + *  under  the terms of  the GNU General  Public License as published by the
8542 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8543 + *  option) any later version.
8544 + *
8545 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8546 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8547 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8548 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8549 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8550 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8551 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8552 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8553 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8554 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8555 + *
8556 + *  You should have received a copy of the  GNU General Public License along
8557 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8558 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8559 + *
8560 + *
8561 + **************************************************************************
8562 + * May 2004 P. Sadik.
8563 + *
8564 + * Initial Release
8565 + *
8566 + *
8567 + *
8568 + **************************************************************************
8569 + */
8570 +#ifndef __IDT_RC32438_DMA_H__
8571 +#define __IDT_RC32438_DMA_H__
8572 +enum
8573 +{
8574 +       DMA0_PhysicalAddress    = 0x18040000,
8575 +       DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
8576 +
8577 +       DMA0_VirtualAddress     = 0xb8040000,
8578 +       DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
8579 +} ;
8580 +
8581 +/*
8582 + * DMA descriptor (in physical memory).
8583 + */
8584 +
8585 +typedef struct DMAD_s
8586 +{
8587 +       u32                     control ;       // Control. use DMAD_*
8588 +       u32                     ca ;            // Current Address.
8589 +       u32                     devcs ;         // Device control and status.
8590 +       u32                     link ;          // Next descriptor in chain.
8591 +} volatile *DMAD_t ;
8592 +
8593 +enum
8594 +{
8595 +       DMAD_size               = sizeof (struct DMAD_s),
8596 +       DMAD_count_b            = 0,            // in DMAD_t -> control
8597 +       DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
8598 +       DMAD_ds_b               = 20,           // in DMAD_t -> control
8599 +       DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
8600 +               DMAD_ds_extToMem0_v     = 0,
8601 +               DMAD_ds_memToExt0_v     = 1,
8602 +               DMAD_ds_extToMem1_v     = 0,
8603 +               DMAD_ds_memToExt1_v     = 1,
8604 +               DMAD_ds_ethRcv0_v       = 0,
8605 +               DMAD_ds_ethXmt0_v       = 0,
8606 +               DMAD_ds_ethRcv1_v       = 0,
8607 +               DMAD_ds_ethXmt2_v       = 0,
8608 +               DMAD_ds_memToFifo_v     = 0,
8609 +               DMAD_ds_fifoToMem_v     = 0,
8610 +               DMAD_ds_rng_de_v           = 1,//randomNumberGenerator on LC/DE
8611 +               DMAD_ds_pciToMem_v      = 0,
8612 +               DMAD_ds_memToPci_v      = 0,
8613 +               DMAD_ds_securityInput_v = 0,
8614 +               DMAD_ds_securityOutput_v = 0,
8615 +               DMAD_ds_rng_se_v        = 0,//randomNumberGenerator on SE
8616 +
8617 +       DMAD_devcmd_b           = 22,           // in DMAD_t -> control
8618 +       DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
8619 +               DMAD_devcmd_byte_v      = 0,    //memory-to-memory
8620 +               DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
8621 +               DMAD_devcmd_word_v      = 2,    //memory-to-memory
8622 +               DMAD_devcmd_2words_v    = 3,    //memory-to-memory
8623 +               DMAD_devcmd_4words_v    = 4,    //memory-to-memory
8624 +               DMAD_devcmd_6words_v    = 5,    //memory-to-memory
8625 +               DMAD_devcmd_8words_v    = 6,    //memory-to-memory
8626 +               DMAD_devcmd_16words_v   = 7,    //memory-to-memory
8627 +       DMAD_cof_b              = 25,           // chain on finished
8628 +       DMAD_cof_m              = 0x02000000,   //
8629 +       DMAD_cod_b              = 26,           // chain on done
8630 +       DMAD_cod_m              = 0x04000000,   //
8631 +       DMAD_iof_b              = 27,           // interrupt on finished
8632 +       DMAD_iof_m              = 0x08000000,   //
8633 +       DMAD_iod_b              = 28,           // interrupt on done
8634 +       DMAD_iod_m              = 0x10000000,   //
8635 +       DMAD_t_b                = 29,           // terminated
8636 +       DMAD_t_m                = 0x20000000,   //
8637 +       DMAD_d_b                = 30,           // done
8638 +       DMAD_d_m                = 0x40000000,   //
8639 +       DMAD_f_b                = 31,           // finished
8640 +       DMAD_f_m                = 0x80000000,   //
8641 +} ;
8642 +
8643 +/*
8644 + * DMA register (within Internal Register Map).
8645 + */
8646 +
8647 +struct DMA_Chan_s
8648 +{
8649 +       u32             dmac ;          // Control.
8650 +       u32             dmas ;          // Status.
8651 +       u32             dmasm ;         // Mask.
8652 +       u32             dmadptr ;       // Descriptor pointer.
8653 +       u32             dmandptr ;      // Next descriptor pointer.
8654 +};
8655 +
8656 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
8657 +
8658 +//DMA_Channels   use DMACH_count instead
8659 +
8660 +enum
8661 +{
8662 +       DMAC_run_b      = 0,            //
8663 +       DMAC_run_m      = 0x00000001,   //
8664 +       DMAC_dm_b       = 1,            // done mask
8665 +       DMAC_dm_m       = 0x00000002,   //
8666 +       DMAC_mode_b     = 2,            //
8667 +       DMAC_mode_m     = 0x0000000c,   //
8668 +               DMAC_mode_auto_v        = 0,
8669 +               DMAC_mode_burst_v       = 1,
8670 +               DMAC_mode_transfer_v    = 2, //usually used
8671 +               DMAC_mode_reserved_v    = 3,
8672 +       DMAC_a_b        = 4,            //
8673 +       DMAC_a_m        = 0x00000010,   //
8674 +
8675 +       DMAS_f_b        = 0,            // finished (sticky)
8676 +       DMAS_f_m        = 0x00000001,   //
8677 +       DMAS_d_b        = 1,            // done (sticky)
8678 +       DMAS_d_m        = 0x00000002,   //
8679 +       DMAS_c_b        = 2,            // chain (sticky)
8680 +       DMAS_c_m        = 0x00000004,   //
8681 +       DMAS_e_b        = 3,            // error (sticky)
8682 +       DMAS_e_m        = 0x00000008,   //
8683 +       DMAS_h_b        = 4,            // halt (sticky)
8684 +       DMAS_h_m        = 0x00000010,   //
8685 +
8686 +       DMASM_f_b       = 0,            // finished (1=mask)
8687 +       DMASM_f_m       = 0x00000001,   //
8688 +       DMASM_d_b       = 1,            // done (1=mask)
8689 +       DMASM_d_m       = 0x00000002,   //
8690 +       DMASM_c_b       = 2,            // chain (1=mask)
8691 +       DMASM_c_m       = 0x00000004,   //
8692 +       DMASM_e_b       = 3,            // error (1=mask)
8693 +       DMASM_e_m       = 0x00000008,   //
8694 +       DMASM_h_b       = 4,            // halt (1=mask)
8695 +       DMASM_h_m       = 0x00000010,   //
8696 +} ;
8697 +
8698 +/*
8699 + * DMA channel definitions
8700 + */
8701 +
8702 +enum
8703 +{
8704 +       DMACH_extToMem0 = 0,
8705 +       DMACH_memToExt0 = 0,
8706 +       DMACH_extToMem1 = 1,
8707 +       DMACH_memToExt1 = 1,
8708 +       DMACH_ethRcv0 = 2,
8709 +       DMACH_ethXmt0 = 3,
8710 +       DMACH_ethRcv1 = 4,
8711 +       DMACH_ethXmt2 = 5,
8712 +       DMACH_memToFifo = 6,
8713 +       DMACH_fifoToMem = 7,
8714 +       DMACH_rng_de = 7,//randomNumberGenerator on LC/DE
8715 +       DMACH_pciToMem = 8,
8716 +       DMACH_memToPci = 9,
8717 +       DMACH_securityInput = 10,
8718 +       DMACH_securityOutput = 11,
8719 +       DMACH_rng_se = 12, //randomNumberGenerator on SE
8720 +
8721 +       DMACH_count //must be last
8722 +};
8723 +
8724 +
8725 +typedef struct DMAC_s
8726 +{
8727 +       struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
8728 +} volatile *DMA_t ;
8729 +
8730 +
8731 +/*
8732 + * External DMA parameters
8733 +*/
8734 +
8735 +enum
8736 +{
8737 +       DMADEVCMD_ts_b  = 0,            // ts field in devcmd
8738 +       DMADEVCMD_ts_m  = 0x00000007,   // ts field in devcmd
8739 +               DMADEVCMD_ts_byte_v     = 0,
8740 +               DMADEVCMD_ts_halfword_v = 1,
8741 +               DMADEVCMD_ts_word_v     = 2,
8742 +               DMADEVCMD_ts_2word_v    = 3,
8743 +               DMADEVCMD_ts_4word_v    = 4,
8744 +               DMADEVCMD_ts_6word_v    = 5,
8745 +               DMADEVCMD_ts_8word_v    = 6,
8746 +               DMADEVCMD_ts_16word_v   = 7
8747 +};
8748 +
8749 +
8750 +#if 1  // aws - Compatibility.
8751 +#      define  EXTDMA_ts_b             DMADEVCMD_ts_b
8752 +#      define  EXTDMA_ts_m             DMADEVCMD_ts_m
8753 +#      define  EXTDMA_ts_byte_v        DMADEVCMD_ts_byte_v
8754 +#      define  EXTDMA_ts_halfword_v    DMADEVCMD_ts_halfword_v
8755 +#      define  EXTDMA_ts_word_v        DMADEVCMD_ts_word_v
8756 +#      define  EXTDMA_ts_2word_v       DMADEVCMD_ts_2word_v
8757 +#      define  EXTDMA_ts_4word_v       DMADEVCMD_ts_4word_v
8758 +#      define  EXTDMA_ts_6word_v       DMADEVCMD_ts_6word_v
8759 +#      define  EXTDMA_ts_8word_v       DMADEVCMD_ts_8word_v
8760 +#      define  EXTDMA_ts_16word_v      DMADEVCMD_ts_16word_v
8761 +#endif // aws - Compatibility.
8762 +
8763 +#endif //__IDT_RC32438_DMA_H__
8764 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h
8765 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h    1970-01-01 01:00:00.000000000 +0100
8766 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h       2006-06-18 12:44:28.000000000 +0200
8767 @@ -0,0 +1,82 @@
8768 +/**************************************************************************
8769 + *
8770 + *  BRIEF MODULE DESCRIPTION
8771 + *   DMA operations for IDT RC32438.
8772 + *
8773 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8774 + *
8775 + *  This program is free software; you can redistribute  it and/or modify it
8776 + *  under  the terms of  the GNU General  Public License as published by the
8777 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8778 + *  option) any later version.
8779 + *
8780 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8781 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8782 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8783 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8784 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8785 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8786 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8787 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8788 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8789 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8790 + *
8791 + *  You should have received a copy of the  GNU General Public License along
8792 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8793 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8794 + *
8795 + *
8796 + **************************************************************************
8797 + * May 2004 P. Sadik.
8798 + *
8799 + * Initial Release
8800 + *
8801 + *
8802 + *
8803 + **************************************************************************
8804 + */
8805 +
8806 +#ifndef __IDT_RC32438_DMA_V_H__
8807 +#define __IDT_RC32438_DMA_V_H__
8808 +#include  <asm/idt-boards/rc32438/rc32438_dma.h>
8809 +
8810 +#define DMA_CHAN_OFFSET  0x14
8811 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
8812 +#define DMA_COUNT(count)   \
8813 +  ((count) & DMAD_count_m)
8814 +
8815 +#define DMA_HALT_TIMEOUT 500
8816 +
8817 +
8818 +static inline int rc32438_halt_dma(DMA_Chan_t ch)
8819 +{
8820 +       int timeout=1;
8821 +       if (rc32438_readl(&ch->dmac) & DMAC_run_m) {
8822 +               rc32438_writel(0, &ch->dmac);
8823 +
8824 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
8825 +                       if (rc32438_readl(&ch->dmas) & DMAS_h_m) {
8826 +                               rc32438_writel(0, &ch->dmas);
8827 +                               break;
8828 +                       }
8829 +               }
8830 +
8831 +       }
8832 +
8833 +       return timeout ? 0 : 1;
8834 +}
8835 +
8836 +
8837 +
8838 +
8839 +static inline void rc32438_start_dma(DMA_Chan_t ch, u32 dma_addr)
8840 +{
8841 +       rc32438_writel(0, &ch->dmandptr);
8842 +       rc32438_writel(dma_addr, &ch->dmadptr);
8843 +}
8844 +
8845 +static inline void rc32438_chain_dma(DMA_Chan_t ch, u32 dma_addr)
8846 +{
8847 +       rc32438_writel(dma_addr, &ch->dmandptr);
8848 +}
8849 +#endif //__IDT_RC32438_DMA_V_H__
8850 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h
8851 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth.h      1970-01-01 01:00:00.000000000 +0100
8852 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 2006-06-18 12:44:28.000000000 +0200
8853 @@ -0,0 +1,328 @@
8854 +/**************************************************************************
8855 + *
8856 + *  BRIEF MODULE DESCRIPTION
8857 + *   Definitions for IDT EB438 ethernet
8858 + *
8859 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8860 + *
8861 + *  This program is free software; you can redistribute  it and/or modify it
8862 + *  under  the terms of  the GNU General  Public License as published by the
8863 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8864 + *  option) any later version.
8865 + *
8866 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8867 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8868 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8869 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8870 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8871 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8872 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8873 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8874 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8875 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8876 + *
8877 + *  You should have received a copy of the  GNU General Public License along
8878 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8879 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8880 + *
8881 + *
8882 + **************************************************************************
8883 + * May 2004 P. Sadik.
8884 + *
8885 + * Initial Release
8886 + *
8887 + *
8888 + *
8889 + **************************************************************************
8890 + */
8891 +
8892 +#ifndef __IDT_RC32438_ETH_H__
8893 +#define __IDT_RC32438_ETH_H__
8894 +enum
8895 +{
8896 +       ETH0_PhysicalAddress    = 0x18058000,
8897 +       ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
8898 +
8899 +       ETH0_VirtualAddress     = 0xb8058000,
8900 +       ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
8901 +       ETH1_PhysicalAddress    = 0x18060000,
8902 +       ETH1_VirtualAddress     = 0xb8060000,                   // Default
8903 +} ;
8904 +
8905 +typedef struct
8906 +{
8907 +       u32 ethintfc            ;
8908 +       u32 ethfifott           ;
8909 +       u32 etharc              ;
8910 +       u32 ethhash0            ;
8911 +       u32 ethhash1            ;
8912 +       u32 ethu0 [4]           ;       // Reserved.
8913 +       u32 ethpfs              ;
8914 +       u32 ethmcp              ;
8915 +       u32 eth_u1 [10]         ;       // Reserved.
8916 +       u32 ethspare            ;
8917 +       u32 eth_u2 [42]         ;       // Reserved.
8918 +       u32 ethsal0             ;
8919 +       u32 ethsah0             ;
8920 +       u32 ethsal1             ;
8921 +       u32 ethsah1             ;
8922 +       u32 ethsal2             ;
8923 +       u32 ethsah2             ;
8924 +       u32 ethsal3             ;
8925 +       u32 ethsah3             ;
8926 +       u32 ethrbc              ;
8927 +       u32 ethrpc              ;
8928 +       u32 ethrupc             ;
8929 +       u32 ethrfc              ;
8930 +       u32 ethtbc              ;
8931 +       u32 ethgpf              ;
8932 +       u32 eth_u9 [50]         ;       // Reserved.
8933 +       u32 ethmac1             ;
8934 +       u32 ethmac2             ;
8935 +       u32 ethipgt             ;
8936 +       u32 ethipgr             ;
8937 +       u32 ethclrt             ;
8938 +       u32 ethmaxf             ;
8939 +       u32 eth_u10             ;       // Reserved.
8940 +       u32 ethmtest            ;
8941 +       u32 miimcfg             ;
8942 +       u32 miimcmd             ;
8943 +       u32 miimaddr            ;
8944 +       u32 miimwtd             ;
8945 +       u32 miimrdd             ;
8946 +       u32 miimind             ;
8947 +       u32 eth_u11             ;       // Reserved.
8948 +       u32 eth_u12             ;       // Reserved.
8949 +       u32 ethcfsa0            ;
8950 +       u32 ethcfsa1            ;
8951 +       u32 ethcfsa2            ;
8952 +} volatile *ETH_t;
8953 +
8954 +enum
8955 +{
8956 +       ETHINTFC_en_b           = 0,
8957 +       ETHINTFC_en_m           = 0x00000001,
8958 +       ETHINTFC_its_b          = 1,
8959 +       ETHINTFC_its_m          = 0x00000002,
8960 +       ETHINTFC_rip_b          = 2,
8961 +       ETHINTFC_rip_m          = 0x00000004,
8962 +       ETHINTFC_jam_b          = 3,
8963 +       ETHINTFC_jam_m          = 0x00000008,
8964 +       ETHINTFC_ovr_b          = 4,
8965 +       ETHINTFC_ovr_m          = 0x00000010,
8966 +       ETHINTFC_und_b          = 5,
8967 +       ETHINTFC_und_m          = 0x00000020,
8968 +
8969 +       ETHFIFOTT_tth_b         = 0,
8970 +       ETHFIFOTT_tth_m         = 0x0000007f,
8971 +
8972 +       ETHARC_pro_b            = 0,
8973 +       ETHARC_pro_m            = 0x00000001,
8974 +       ETHARC_am_b             = 1,
8975 +       ETHARC_am_m             = 0x00000002,
8976 +       ETHARC_afm_b            = 2,
8977 +       ETHARC_afm_m            = 0x00000004,
8978 +       ETHARC_ab_b             = 3,
8979 +       ETHARC_ab_m             = 0x00000008,
8980 +
8981 +       ETHSAL_byte5_b          = 0,
8982 +       ETHSAL_byte5_m          = 0x000000ff,
8983 +       ETHSAL_byte4_b          = 8,
8984 +       ETHSAL_byte4_m          = 0x0000ff00,
8985 +       ETHSAL_byte3_b          = 16,
8986 +       ETHSAL_byte3_m          = 0x00ff0000,
8987 +       ETHSAL_byte2_b          = 24,
8988 +       ETHSAL_byte2_m          = 0xff000000,
8989 +
8990 +       ETHSAH_byte1_b          = 0,
8991 +       ETHSAH_byte1_m          = 0x000000ff,
8992 +       ETHSAH_byte0_b          = 8,
8993 +       ETHSAH_byte0_m          = 0x0000ff00,
8994 +
8995 +       ETHGPF_ptv_b            = 0,
8996 +       ETHGPF_ptv_m            = 0x0000ffff,
8997 +
8998 +       ETHPFS_pfd_b            = 0,
8999 +       ETHPFS_pfd_m            = 0x00000001,
9000 +
9001 +       ETHCFSA0_cfsa4_b        = 0,
9002 +       ETHCFSA0_cfsa4_m        = 0x000000ff,
9003 +       ETHCFSA0_cfsa5_b        = 8,
9004 +       ETHCFSA0_cfsa5_m        = 0x0000ff00,
9005 +
9006 +       ETHCFSA1_cfsa2_b        = 0,
9007 +       ETHCFSA1_cfsa2_m        = 0x000000ff,
9008 +       ETHCFSA1_cfsa3_b        = 8,
9009 +       ETHCFSA1_cfsa3_m        = 0x0000ff00,
9010 +
9011 +       ETHCFSA2_cfsa0_b        = 0,
9012 +       ETHCFSA2_cfsa0_m        = 0x000000ff,
9013 +       ETHCFSA2_cfsa1_b        = 8,
9014 +       ETHCFSA2_cfsa1_m        = 0x0000ff00,
9015 +
9016 +       ETHMAC1_re_b            = 0,
9017 +       ETHMAC1_re_m            = 0x00000001,
9018 +       ETHMAC1_paf_b           = 1,
9019 +       ETHMAC1_paf_m           = 0x00000002,
9020 +       ETHMAC1_rfc_b           = 2,
9021 +       ETHMAC1_rfc_m           = 0x00000004,
9022 +       ETHMAC1_tfc_b           = 3,
9023 +       ETHMAC1_tfc_m           = 0x00000008,
9024 +       ETHMAC1_lb_b            = 4,
9025 +       ETHMAC1_lb_m            = 0x00000010,
9026 +       ETHMAC1_mr_b            = 31,
9027 +       ETHMAC1_mr_m            = 0x80000000,
9028 +
9029 +       ETHMAC2_fd_b            = 0,
9030 +       ETHMAC2_fd_m            = 0x00000001,
9031 +       ETHMAC2_flc_b           = 1,
9032 +       ETHMAC2_flc_m           = 0x00000002,
9033 +       ETHMAC2_hfe_b           = 2,
9034 +       ETHMAC2_hfe_m           = 0x00000004,
9035 +       ETHMAC2_dc_b            = 3,
9036 +       ETHMAC2_dc_m            = 0x00000008,
9037 +       ETHMAC2_cen_b           = 4,
9038 +       ETHMAC2_cen_m           = 0x00000010,
9039 +       ETHMAC2_pe_b            = 5,
9040 +       ETHMAC2_pe_m            = 0x00000020,
9041 +       ETHMAC2_vpe_b           = 6,
9042 +       ETHMAC2_vpe_m           = 0x00000040,
9043 +       ETHMAC2_ape_b           = 7,
9044 +       ETHMAC2_ape_m           = 0x00000080,
9045 +       ETHMAC2_ppe_b           = 8,
9046 +       ETHMAC2_ppe_m           = 0x00000100,
9047 +       ETHMAC2_lpe_b           = 9,
9048 +       ETHMAC2_lpe_m           = 0x00000200,
9049 +       ETHMAC2_nb_b            = 12,
9050 +       ETHMAC2_nb_m            = 0x00001000,
9051 +       ETHMAC2_bp_b            = 13,
9052 +       ETHMAC2_bp_m            = 0x00002000,
9053 +       ETHMAC2_ed_b            = 14,
9054 +       ETHMAC2_ed_m            = 0x00004000,
9055 +
9056 +       ETHIPGT_ipgt_b          = 0,
9057 +       ETHIPGT_ipgt_m          = 0x0000007f,
9058 +
9059 +       ETHIPGR_ipgr2_b         = 0,
9060 +       ETHIPGR_ipgr2_m         = 0x0000007f,
9061 +       ETHIPGR_ipgr1_b         = 8,
9062 +       ETHIPGR_ipgr1_m         = 0x00007f00,
9063 +
9064 +       ETHCLRT_maxret_b        = 0,
9065 +       ETHCLRT_maxret_m        = 0x0000000f,
9066 +       ETHCLRT_colwin_b        = 8,
9067 +       ETHCLRT_colwin_m        = 0x00003f00,
9068 +
9069 +       ETHMAXF_maxf_b          = 0,
9070 +       ETHMAXF_maxf_m          = 0x0000ffff,
9071 +
9072 +       ETHMTEST_tb_b           = 2,
9073 +       ETHMTEST_tb_m           = 0x00000004,
9074 +
9075 +       ETHMCP_div_b            = 0,
9076 +       ETHMCP_div_m            = 0x000000ff,
9077 +
9078 +       MIIMCFG_rsv_b           = 0,
9079 +       MIIMCFG_rsv_m           = 0x0000000c,
9080 +
9081 +       MIIMCMD_rd_b            = 0,
9082 +       MIIMCMD_rd_m            = 0x00000001,
9083 +       MIIMCMD_scn_b           = 1,
9084 +       MIIMCMD_scn_m           = 0x00000002,
9085 +
9086 +       MIIMADDR_regaddr_b      = 0,
9087 +       MIIMADDR_regaddr_m      = 0x0000001f,
9088 +       MIIMADDR_phyaddr_b      = 8,
9089 +       MIIMADDR_phyaddr_m      = 0x00001f00,
9090 +
9091 +       MIIMWTD_wdata_b         = 0,
9092 +       MIIMWTD_wdata_m         = 0x0000ffff,
9093 +
9094 +       MIIMRDD_rdata_b         = 0,
9095 +       MIIMRDD_rdata_m         = 0x0000ffff,
9096 +
9097 +       MIIMIND_bsy_b           = 0,
9098 +       MIIMIND_bsy_m           = 0x00000001,
9099 +       MIIMIND_scn_b           = 1,
9100 +       MIIMIND_scn_m           = 0x00000002,
9101 +       MIIMIND_nv_b            = 2,
9102 +       MIIMIND_nv_m            = 0x00000004,
9103 +
9104 +} ;
9105 +
9106 +/*
9107 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
9108 + */
9109 +enum
9110 +{
9111 +       ETHRX_fd_b              = 0,
9112 +       ETHRX_fd_m              = 0x00000001,
9113 +       ETHRX_ld_b              = 1,
9114 +       ETHRX_ld_m              = 0x00000002,
9115 +       ETHRX_rok_b             = 2,
9116 +       ETHRX_rok_m             = 0x00000004,
9117 +       ETHRX_fm_b              = 3,
9118 +       ETHRX_fm_m              = 0x00000008,
9119 +       ETHRX_mp_b              = 4,
9120 +       ETHRX_mp_m              = 0x00000010,
9121 +       ETHRX_bp_b              = 5,
9122 +       ETHRX_bp_m              = 0x00000020,
9123 +       ETHRX_vlt_b             = 6,
9124 +       ETHRX_vlt_m             = 0x00000040,
9125 +       ETHRX_cf_b              = 7,
9126 +       ETHRX_cf_m              = 0x00000080,
9127 +       ETHRX_ovr_b             = 8,
9128 +       ETHRX_ovr_m             = 0x00000100,
9129 +       ETHRX_crc_b             = 9,
9130 +       ETHRX_crc_m             = 0x00000200,
9131 +       ETHRX_cv_b              = 10,
9132 +       ETHRX_cv_m              = 0x00000400,
9133 +       ETHRX_db_b              = 11,
9134 +       ETHRX_db_m              = 0x00000800,
9135 +       ETHRX_le_b              = 12,
9136 +       ETHRX_le_m              = 0x00001000,
9137 +       ETHRX_lor_b             = 13,
9138 +       ETHRX_lor_m             = 0x00002000,
9139 +       ETHRX_ces_b             = 14,
9140 +       ETHRX_ces_m             = 0x00004000,
9141 +       ETHRX_length_b          = 16,
9142 +       ETHRX_length_m          = 0xffff0000,
9143 +
9144 +       ETHTX_fd_b              = 0,
9145 +       ETHTX_fd_m              = 0x00000001,
9146 +       ETHTX_ld_b              = 1,
9147 +       ETHTX_ld_m              = 0x00000002,
9148 +       ETHTX_oen_b             = 2,
9149 +       ETHTX_oen_m             = 0x00000004,
9150 +       ETHTX_pen_b             = 3,
9151 +       ETHTX_pen_m             = 0x00000008,
9152 +       ETHTX_cen_b             = 4,
9153 +       ETHTX_cen_m             = 0x00000010,
9154 +       ETHTX_hen_b             = 5,
9155 +       ETHTX_hen_m             = 0x00000020,
9156 +       ETHTX_tok_b             = 6,
9157 +       ETHTX_tok_m             = 0x00000040,
9158 +       ETHTX_mp_b              = 7,
9159 +       ETHTX_mp_m              = 0x00000080,
9160 +       ETHTX_bp_b              = 8,
9161 +       ETHTX_bp_m              = 0x00000100,
9162 +       ETHTX_und_b             = 9,
9163 +       ETHTX_und_m             = 0x00000200,
9164 +       ETHTX_of_b              = 10,
9165 +       ETHTX_of_m              = 0x00000400,
9166 +       ETHTX_ed_b              = 11,
9167 +       ETHTX_ed_m              = 0x00000800,
9168 +       ETHTX_ec_b              = 12,
9169 +       ETHTX_ec_m              = 0x00001000,
9170 +       ETHTX_lc_b              = 13,
9171 +       ETHTX_lc_m              = 0x00002000,
9172 +       ETHTX_td_b              = 14,
9173 +       ETHTX_td_m              = 0x00004000,
9174 +       ETHTX_crc_b             = 15,
9175 +       ETHTX_crc_m             = 0x00008000,
9176 +       ETHTX_le_b              = 16,
9177 +       ETHTX_le_m              = 0x00010000,
9178 +       ETHTX_cc_b              = 17,
9179 +       ETHTX_cc_m              = 0x001E0000,
9180 +} ;
9181 +#endif //__IDT_RC32438_ETH_H__
9182 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h
9183 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h    1970-01-01 01:00:00.000000000 +0100
9184 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h       2006-06-18 12:44:28.000000000 +0200
9185 @@ -0,0 +1,72 @@
9186 +/**************************************************************************
9187 + *
9188 + *  BRIEF MODULE DESCRIPTION
9189 + *   macros for IDT EB438 ethernet
9190 + *
9191 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
9192 + *
9193 + *  This program is free software; you can redistribute  it and/or modify it
9194 + *  under  the terms of  the GNU General  Public License as published by the
9195 + *  Free Software Foundation;  either version 2 of the  License, or (at your
9196 + *  option) any later version.
9197 + *
9198 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
9199 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9200 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
9201 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
9202 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9203 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
9204 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9205 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
9206 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9207 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9208 + *
9209 + *  You should have received a copy of the  GNU General Public License along
9210 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
9211 + *  675 Mass Ave, Cambridge, MA 02139, USA.
9212 + *
9213 + *
9214 + **************************************************************************
9215 + * May 2004 P. Sadik.
9216 + *
9217 + * Initial Release
9218 + *
9219 + *
9220 + *
9221 + **************************************************************************
9222 + */
9223 +
9224 +#ifndef __IDT_RC32438_ETH_V_H__
9225 +#define __IDT_RC32438_ETH_V_H__
9226 +#include  <asm/idt-boards/rc32438/rc32438_eth.h>
9227 +
9228 +#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
9229 +#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
9230 +#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
9231 +#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
9232 +#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
9233 +#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
9234 +#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
9235 +#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
9236 +#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
9237 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
9238 +#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
9239 +
9240 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
9241 +
9242 +#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
9243 +#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
9244 +#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
9245 +#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
9246 +#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
9247 +#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
9248 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
9249 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
9250 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
9251 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
9252 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
9253 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
9254 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
9255 +#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
9256 +
9257 +#endif //__IDT_RC32438_ETH_V_H__
9258 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h
9259 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h     1970-01-01 01:00:00.000000000 +0100
9260 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h        2006-06-18 12:44:28.000000000 +0200
9261 @@ -0,0 +1,257 @@
9262 +/**************************************************************************
9263 + *
9264 + *  BRIEF MODULE DESCRIPTION
9265 + *   Definitions for IDT RC32438 GPIO.
9266 + *
9267 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
9268 + *
9269 + *  This program is free software; you can redistribute  it and/or modify it
9270 + *  under  the terms of  the GNU General  Public License as published by the
9271 + *  Free Software Foundation;  either version 2 of the  License, or (at your
9272 + *  option) any later version.
9273 + *
9274 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
9275 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9276 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
9277 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
9278 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9279 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
9280 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9281 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
9282 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9283 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9284 + *
9285 + *  You should have received a copy of the  GNU General Public License along
9286 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
9287 + *  675 Mass Ave, Cambridge, MA 02139, USA.
9288 + *
9289 + *
9290 + **************************************************************************
9291 + * May 2004 P. Sadik.
9292 + *
9293 + * Initial Release
9294 + *
9295 + *
9296 + *
9297 + **************************************************************************
9298 + */
9299 +#ifndef __IDT_RC32438_GPIO_H__
9300 +#define __IDT_RC32438_GPIO_H__
9301 +enum
9302 +{
9303 +       GPIO0_PhysicalAddress   = 0x18048000,
9304 +       GPIO_PhysicalAddress    = GPIO0_PhysicalAddress,        // Default
9305 +
9306 +       GPIO0_VirtualAddress    = 0xb8048000,
9307 +       GPIO_VirtualAddress     = GPIO0_VirtualAddress,         // Default
9308 +} ;
9309 +
9310 +typedef struct
9311 +{
9312 +       u32   gpiofunc;   /* GPIO Function Register
9313 +                          * gpiofunc[x]==0 bit = gpio
9314 +                          * func[x]==1  bit = altfunc
9315 +                          */
9316 +       u32   gpiocfg;    /* GPIO Configuration Register
9317 +                          * gpiocfg[x]==0 bit = input
9318 +                          * gpiocfg[x]==1 bit = output
9319 +                          */
9320 +       u32   gpiod;      /* GPIO Data Register
9321 +                          * gpiod[x] read/write gpio pinX status
9322 +                          */
9323 +       u32   gpioilevel; /* GPIO Interrupt Status Register
9324 +                          * interrupt level (see gpioistat)
9325 +                          */
9326 +       u32   gpioistat;  /* Gpio Interrupt Status Register
9327 +                          * istat[x] = (gpiod[x] == level[x])
9328 +                          * cleared in ISR (STICKY bits)
9329 +                          */
9330 +       u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
9331 +} volatile * GPIO_t ;
9332 +
9333 +typedef enum
9334 +{
9335 +       GPIO_gpio_v             = 0,            // gpiofunc use pin as GPIO.
9336 +       GPIO_alt_v              = 1,            // gpiofunc use pin as alt.
9337 +       GPIO_input_v            = 0,            // gpiocfg use pin as input.
9338 +       GPIO_output_v           = 1,            // gpiocfg use pin as output.
9339 +       GPIO_pin0_b             = 0,
9340 +       GPIO_pin0_m             = 0x00000001,
9341 +       GPIO_pin1_b             = 1,
9342 +       GPIO_pin1_m             = 0x00000002,
9343 +       GPIO_pin2_b             = 2,
9344 +       GPIO_pin2_m             = 0x00000004,
9345 +       GPIO_pin3_b             = 3,
9346 +       GPIO_pin3_m             = 0x00000008,
9347 +       GPIO_pin4_b             = 4,
9348 +       GPIO_pin4_m             = 0x00000010,
9349 +       GPIO_pin5_b             = 5,
9350 +       GPIO_pin5_m             = 0x00000020,
9351 +       GPIO_pin6_b             = 6,
9352 +       GPIO_pin6_m             = 0x00000040,
9353 +       GPIO_pin7_b             = 7,
9354 +       GPIO_pin7_m             = 0x00000080,
9355 +       GPIO_pin8_b             = 8,
9356 +       GPIO_pin8_m             = 0x00000100,
9357 +       GPIO_pin9_b             = 9,
9358 +       GPIO_pin9_m             = 0x00000200,
9359 +       GPIO_pin10_b            = 10,
9360 +       GPIO_pin10_m            = 0x00000400,
9361 +       GPIO_pin11_b            = 11,
9362 +       GPIO_pin11_m            = 0x00000800,
9363 +       GPIO_pin12_b            = 12,
9364 +       GPIO_pin12_m            = 0x00001000,
9365 +       GPIO_pin13_b            = 13,
9366 +       GPIO_pin13_m            = 0x00002000,
9367 +       GPIO_pin14_b            = 14,
9368 +       GPIO_pin14_m            = 0x00004000,
9369 +       GPIO_pin15_b            = 15,
9370 +       GPIO_pin15_m            = 0x00008000,
9371 +       GPIO_pin16_b            = 16,
9372 +       GPIO_pin16_m            = 0x00010000,
9373 +       GPIO_pin17_b            = 17,
9374 +       GPIO_pin17_m            = 0x00020000,
9375 +       GPIO_pin18_b            = 18,
9376 +       GPIO_pin18_m            = 0x00040000,
9377 +       GPIO_pin19_b            = 19,
9378 +       GPIO_pin19_m            = 0x00080000,
9379 +       GPIO_pin20_b            = 20,
9380 +       GPIO_pin20_m            = 0x00100000,
9381 +       GPIO_pin21_b            = 21,
9382 +       GPIO_pin21_m            = 0x00200000,
9383 +       GPIO_pin22_b            = 22,
9384 +       GPIO_pin22_m            = 0x00400000,
9385 +       GPIO_pin23_b            = 23,
9386 +       GPIO_pin23_m            = 0x00800000,
9387 +       GPIO_pin24_b            = 24,
9388 +       GPIO_pin24_m            = 0x01000000,
9389 +       GPIO_pin25_b            = 25,
9390 +       GPIO_pin25_m            = 0x02000000,
9391 +       GPIO_pin26_b            = 26,
9392 +       GPIO_pin26_m            = 0x04000000,
9393 +       GPIO_pin27_b            = 27,
9394 +       GPIO_pin27_m            = 0x08000000,
9395 +       GPIO_pin28_b            = 28,
9396 +       GPIO_pin28_m            = 0x10000000,
9397 +       GPIO_pin29_b            = 29,
9398 +       GPIO_pin29_m            = 0x20000000,
9399 +       GPIO_pin30_b            = 30,
9400 +       GPIO_pin30_m            = 0x40000000,
9401 +       GPIO_pin31_b            = 31,
9402 +       GPIO_pin31_m            = 0x80000000,
9403 +
9404 +// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
9405 +
9406 +       GPIO_u0sout_b           = GPIO_pin0_b,          // UART 0 serial out.
9407 +       GPIO_u0sout_m           = GPIO_pin0_m,
9408 +               GPIO_u0sout_cfg_v       = GPIO_output_v,
9409 +       GPIO_u0sinp_b   = GPIO_pin1_b,                  // UART 0 serial in.
9410 +       GPIO_u0sinp_m   = GPIO_pin1_m,
9411 +               GPIO_u0sinp_cfg_v       = GPIO_input_v,
9412 +       GPIO_u0rin_b    = GPIO_pin2_b,                  // UART 0 ring indic.
9413 +       GPIO_u0rin_m    = GPIO_pin2_m,
9414 +               GPIO_u0rin_cfg_v        = GPIO_input_v,
9415 +       GPIO_u0dcdn_b   = GPIO_pin3_b,                  // UART 0 data carr.det.
9416 +       GPIO_u0dcdn_m   = GPIO_pin3_m,
9417 +               GPIO_u0dcdn_cfg_v       = GPIO_input_v,
9418 +       GPIO_u0dtrn_b   = GPIO_pin4_b,                  // UART 0 data term rdy.
9419 +       GPIO_u0dtrn_m   = GPIO_pin4_m,
9420 +               GPIO_u0dtrn_cfg_v       = GPIO_output_v,
9421 +       GPIO_u0dsrn_b   = GPIO_pin5_b,                  // UART 0 data set rdy.
9422 +       GPIO_u0dsrn_m   = GPIO_pin5_m,
9423 +               GPIO_u0dsrn_cfg_v       = GPIO_input_v,
9424 +       GPIO_u0rtsn_b   = GPIO_pin6_b,                  // UART 0 req. to send.
9425 +       GPIO_u0rtsn_m   = GPIO_pin6_m,
9426 +               GPIO_u0rtsn_cfg_v       = GPIO_output_v,
9427 +       GPIO_u0ctsn_b   = GPIO_pin7_b,                  // UART 0 clear to send.
9428 +       GPIO_u0ctsn_m   = GPIO_pin7_m,
9429 +               GPIO_u0ctsn_cfg_v       = GPIO_input_v,
9430 +
9431 +       GPIO_u1sout_b           = GPIO_pin8_b,          // UART 1 serial out.
9432 +       GPIO_u1sout_m           = GPIO_pin8_m,
9433 +               GPIO_u1sout_cfg_v       = GPIO_output_v,
9434 +       GPIO_u1sinp_b           = GPIO_pin9_b,          // UART 1 serial in.
9435 +       GPIO_u1sinp_m           = GPIO_pin9_m,
9436 +               GPIO_u1sinp_cfg_v       = GPIO_input_v,
9437 +       GPIO_u1dtrn_b           = GPIO_pin10_b,         // UART 1 data term rdy.
9438 +       GPIO_u1dtrn_m           = GPIO_pin10_m,
9439 +               GPIO_u1dtrn_cfg_v       = GPIO_output_v,
9440 +       GPIO_u1dsrn_b           = GPIO_pin11_b,         // UART 1 data set rdy.
9441 +       GPIO_u1dsrn_m           = GPIO_pin11_m,
9442 +               GPIO_u1dsrn_cfg_v       = GPIO_input_v,
9443 +       GPIO_u1rtsn_b           = GPIO_pin12_b,         // UART 1 req. to send.
9444 +       GPIO_u1rtsn_m           = GPIO_pin12_m,
9445 +               GPIO_u1rtsn_cfg_v       = GPIO_output_v,
9446 +       GPIO_u1ctsn_b           = GPIO_pin13_b,         // UART 1 clear to send.
9447 +       GPIO_u1ctsn_m           = GPIO_pin13_m,
9448 +               GPIO_u1ctsn_cfg_v       = GPIO_input_v,
9449 +
9450 +       GPIO_dmareqn0_b         = GPIO_pin14_b,         // Ext. DMA 0 request
9451 +       GPIO_dmareqn0_m         = GPIO_pin14_m,
9452 +               GPIO_dmareqn0_cfg_v     = GPIO_input_v,
9453 +
9454 +       GPIO_dmareqn1_b         = GPIO_pin15_b,         // Ext. DMA 1 request
9455 +       GPIO_dmareqn1_m         = GPIO_pin15_m,
9456 +               GPIO_dmareqn1_cfg_v     = GPIO_input_v,
9457 +
9458 +       GPIO_dmadonen0_b        = GPIO_pin16_b,         // Ext. DMA 0 done
9459 +       GPIO_dmadonen0_m        = GPIO_pin16_m,
9460 +               GPIO_dmadonen0_cfg_v    = GPIO_input_v,
9461 +
9462 +       GPIO_dmadonen1_b        = GPIO_pin17_b,         // Ext. DMA 1 done
9463 +       GPIO_dmadonen1_m        = GPIO_pin17_m,
9464 +               GPIO_dmadonen1_cfg_v    = GPIO_input_v,
9465 +
9466 +       GPIO_dmafinn0_b         = GPIO_pin18_b,         // Ext. DMA 0 finished
9467 +       GPIO_dmafinn0_m         = GPIO_pin18_m,
9468 +               GPIO_dmafinn0_cfg_v     = GPIO_output_v,
9469 +
9470 +       GPIO_dmafinn1_b         = GPIO_pin19_b,         // Ext. DMA 1 finished
9471 +       GPIO_dmafinn1_m         = GPIO_pin19_m,
9472 +               GPIO_dmafinn1_cfg_v     = GPIO_output_v,
9473 +
9474 +       GPIO_maddr22_b          = GPIO_pin20_b,         // M&P bus bit 22.
9475 +       GPIO_maddr22_m          = GPIO_pin20_m,
9476 +               GPIO_maddr22_cfg_v      = GPIO_output_v,
9477 +
9478 +       GPIO_maddr23_b          = GPIO_pin21_b,         // M&P bus bit 23.
9479 +       GPIO_maddr23_m          = GPIO_pin21_m,
9480 +               GPIO_maddr23_cfg_v      = GPIO_output_v,
9481 +
9482 +       GPIO_maddr24_b          = GPIO_pin22_b,         // M&P bus bit 24.
9483 +       GPIO_maddr24_m          = GPIO_pin22_m,
9484 +               GPIO_maddr24_cfg_v      = GPIO_output_v,
9485 +
9486 +       GPIO_maddr25_b          = GPIO_pin23_b,         // M&P bus bit 25.
9487 +       GPIO_maddr25_m          = GPIO_pin23_m,
9488 +               GPIO_maddr25_cfg_v      = GPIO_output_v,
9489 +
9490 +       GPIO_afspare6_b         = GPIO_pin24_b,         // reserved.
9491 +       GPIO_afspare6_m         = GPIO_pin24_m,
9492 +               GPIO_afspare6_cfg_v     = GPIO_input_v,
9493 +       GPIO_afspare5_b         = GPIO_pin25_b,         // reserved.
9494 +       GPIO_afspare5_m         = GPIO_pin25_m,
9495 +               GPIO_afspare5_cfg_v     = GPIO_input_v,
9496 +       GPIO_afspare4_b         = GPIO_pin26_b,         // reserved.
9497 +       GPIO_afspare4_m         = GPIO_pin26_m,
9498 +               GPIO_afspare4_cfg_v     = GPIO_input_v,
9499 +       GPIO_afspare3_b         = GPIO_pin27_b,         // reserved.
9500 +       GPIO_afspare3_m         = GPIO_pin27_m,
9501 +               GPIO_afspare3_cfg_v     = GPIO_input_v,
9502 +       GPIO_afspare2_b         = GPIO_pin28_b,         // reserved.
9503 +       GPIO_afspare2_m         = GPIO_pin28_m,
9504 +               GPIO_afspare2_cfg_v     = GPIO_input_v,
9505 +       GPIO_afspare1_b         = GPIO_pin29_b,         // reserved.
9506 +       GPIO_afspare1_m         = GPIO_pin29_m,
9507 +               GPIO_afspare1_cfg_v     = GPIO_input_v,
9508 +
9509 +       GPIO_pcimuintn_b        = GPIO_pin30_b,         // PCI messaging int.
9510 +       GPIO_pcimuintn_m        = GPIO_pin30_m,
9511 +               GPIO_pcimuintn_cfg_v    = GPIO_output_v,
9512 +
9513 +       GPIO_rngclk_b           = GPIO_pin31_b,         // RNG external clock
9514 +       GPIO_rngclk_m           = GPIO_pin31_m,
9515 +               GPIO_rncclk_cfg_v       = GPIO_input_v,
9516 +} GPIO_DEFS_t;
9517 +
9518 +#endif //__IDT_RC32438_GPIO_H__
9519 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h
9520 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438.h  1970-01-01 01:00:00.000000000 +0100
9521 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h     2006-06-18 12:44:28.000000000 +0200
9522 @@ -0,0 +1,152 @@
9523 +/**************************************************************************
9524 + *
9525 + *  BRIEF MODULE DESCRIPTION
9526 + *   Definitions for IDT RC32438 CPU.
9527 + *
9528 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
9529 + *
9530 + *  This program is free software; you can redistribute  it and/or modify it
9531 + *  under  the terms of  the GNU General  Public License as published by the
9532 + *  Free Software Foundation;  either version 2 of the  License, or (at your
9533 + *  option) any later version.
9534 + *
9535 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
9536 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9537 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
9538 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
9539 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9540 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
9541 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9542 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
9543 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9544 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9545 + *
9546 + *  You should have received a copy of the  GNU General Public License along
9547 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
9548 + *  675 Mass Ave, Cambridge, MA 02139, USA.
9549 + *
9550 + *
9551 + **************************************************************************
9552 + * May 2004 P. Sadik.
9553 + *
9554 + * Initial Release
9555 + *
9556 + *
9557 + *
9558 + **************************************************************************
9559 + */
9560 +
9561 +#ifndef __IDT_RC32438_H__
9562 +#define  __IDT_RC32438_H__
9563 +#include <linux/autoconf.h>
9564 +#include <linux/delay.h>
9565 +#include <asm/io.h>
9566 +#include <asm/idt-boards/rc32438/rc32438_timer.h>
9567 +
9568 +#define RC32438_REG_BASE   0x18000000
9569 +
9570 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
9571 +#define idttimer     ((volatile TIM_t)  TIM0_VirtualAddress)
9572 +#define idt_gpio         ((volatile GPIO_t) GPIO0_VirtualAddress)
9573 +
9574 +#define IDT_CLOCK_MULT 2
9575 +#define MIPS_CPU_TIMER_IRQ 7
9576 +/* Interrupt Controller */
9577 +#define IC_GROUP0_PEND     (RC32438_REG_BASE + 0x38000)
9578 +#define IC_GROUP0_MASK     (RC32438_REG_BASE + 0x38008)
9579 +#define IC_GROUP_OFFSET    0x0C
9580 +#define RTC_BASE           0xAC0801FF0
9581 +
9582 +#define NUM_INTR_GROUPS    5
9583 +/* 16550 UARTs */
9584 +
9585 +#define GROUP0_IRQ_BASE 8              /* GRP2 IRQ numbers start here */
9586 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
9587 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
9588 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
9589 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
9590 +
9591 +#ifdef __MIPSEB__
9592 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50003)
9593 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50023)
9594 +#else
9595 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50000)
9596 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50020)
9597 +#endif
9598 +
9599 +#define RC32438_UART0_IRQ  GROUP3_IRQ_BASE + 0
9600 +#define RC32438_UART1_IRQ  GROUP3_IRQ_BASE + 3
9601 +
9602 +#define RC32438_NR_IRQS  (GROUP4_IRQ_BASE + 32)
9603 +
9604 +
9605 +
9606 +/* cpu pipeline flush */
9607 +static inline void rc32438_sync(void)
9608 +{
9609 +        __asm__ volatile ("sync");
9610 +}
9611 +
9612 +static inline void rc32438_sync_udelay(int us)
9613 +{
9614 +        __asm__ volatile ("sync");
9615 +        udelay(us);
9616 +}
9617 +
9618 +static inline void rc32438_sync_delay(int ms)
9619 +{
9620 +        __asm__ volatile ("sync");
9621 +        mdelay(ms);
9622 +}
9623 +
9624 +/*
9625 + * Macros to access internal RC32438 registers. No byte
9626 + * swapping should be done when accessing the internal
9627 + * registers.
9628 + */
9629 +
9630 +#define rc32438_readb __raw_readb
9631 +#define rc32438_readw __raw_readw
9632 +#define rc32438_readl __raw_readl
9633 +
9634 +#define rc32438_writeb __raw_writeb
9635 +#define rc32438_writew __raw_writew
9636 +#define rc32438_writel __raw_writel
9637 +
9638 +/*
9639 + * C access to CLZ and CLO instructions
9640 + * (count leading zeroes/ones).
9641 + */
9642 +static inline int rc32438_clz(unsigned long val)
9643 +{
9644 +       int ret;
9645 +        __asm__ volatile (
9646 +               ".set\tnoreorder\n\t"
9647 +               ".set\tnoat\n\t"
9648 +               ".set\tmips32\n\t"
9649 +               "clz\t%0,%1\n\t"
9650 +                ".set\tmips0\n\t"
9651 +                ".set\tat\n\t"
9652 +                ".set\treorder"
9653 +                : "=r" (ret)
9654 +               : "r" (val));
9655 +
9656 +       return ret;
9657 +}
9658 +static inline int rc32438_clo(unsigned long val)
9659 +{
9660 +       int ret;
9661 +        __asm__ volatile (
9662 +               ".set\tnoreorder\n\t"
9663 +               ".set\tnoat\n\t"
9664 +               ".set\tmips32\n\t"
9665 +               "clo\t%0,%1\n\t"
9666 +                ".set\tmips0\n\t"
9667 +                ".set\tat\n\t"
9668 +                ".set\treorder"
9669 +                : "=r" (ret)
9670 +               : "r" (val));
9671 +
9672 +       return ret;
9673 +}
9674 +#endif //__IDT_RC32438_H__
9675 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h
9676 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci.h      1970-01-01 01:00:00.000000000 +0100
9677 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 2006-06-18 12:44:28.000000000 +0200
9678 @@ -0,0 +1,510 @@
9679 +/**************************************************************************
9680 + *
9681 + *  BRIEF MODULE DESCRIPTION
9682 + *   Definitions for IDT RC32438 PCI.
9683 + *
9684 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
9685 + *
9686 + *  This program is free software; you can redistribute  it and/or modify it
9687 + *  under  the terms of  the GNU General  Public License as published by the
9688 + *  Free Software Foundation;  either version 2 of the  License, or (at your
9689 + *  option) any later version.
9690 + *
9691 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
9692 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9693 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
9694 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
9695 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9696 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
9697 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9698 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
9699 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9700 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9701 + *
9702 + *  You should have received a copy of the  GNU General Public License along
9703 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
9704 + *  675 Mass Ave, Cambridge, MA 02139, USA.
9705 + *
9706 + *
9707 + **************************************************************************
9708 + * May 2004 P. Sadik
9709 + *
9710 + * Initial Release
9711 + *
9712 + *
9713 + *
9714 + **************************************************************************
9715 + */
9716 +
9717 +enum
9718 +{
9719 +       PCI0_PhysicalAddress    = 0x18080000,
9720 +       PCI_PhysicalAddress     = PCI0_PhysicalAddress,
9721 +
9722 +       PCI0_VirtualAddress     = 0xb8080000,
9723 +       PCI_VirtualAddress      = PCI0_VirtualAddress,
9724 +} ;
9725 +
9726 +enum
9727 +{
9728 +       PCI_LbaCount    = 4,            // Local base addresses.
9729 +} ;
9730 +
9731 +typedef struct
9732 +{
9733 +       u32     a ;             // Address.
9734 +       u32     c ;             // Control.
9735 +       u32     m ;             // mapping.
9736 +} PCI_Map_s ;
9737 +
9738 +typedef struct
9739 +{
9740 +       u32             pcic ;
9741 +       u32             pcis ;
9742 +       u32             pcism ;
9743 +       u32             pcicfga ;
9744 +       u32             pcicfgd ;
9745 +       PCI_Map_s       pcilba [PCI_LbaCount] ;
9746 +       u32             pcidac ;
9747 +       u32             pcidas ;
9748 +       u32             pcidasm ;
9749 +       u32             pcidad ;
9750 +       u32             pcidma8c ;
9751 +       u32             pcidma9c ;
9752 +       u32             pcitc ;
9753 +} volatile *PCI_t ;
9754 +
9755 +// PCI messaging unit.
9756 +enum
9757 +{
9758 +       PCIM_Count      = 2,
9759 +} ;
9760 +typedef struct
9761 +{
9762 +       u32             pciim [PCIM_Count] ;
9763 +       u32             pciom [PCIM_Count] ;
9764 +       u32             pciid ;
9765 +       u32             pciiic ;
9766 +       u32             pciiim ;
9767 +       u32             pciiod ;
9768 +       u32             pciioic ;
9769 +       u32             pciioim ;
9770 +} volatile *PCIM_t ;
9771 +
9772 +/*******************************************************************************
9773 + *
9774 + * PCI Control Register
9775 + *
9776 + ******************************************************************************/
9777 +enum
9778 +{
9779 +       PCIC_en_b       = 0,
9780 +       PCIC_en_m       = 0x00000001,
9781 +       PCIC_tnr_b      = 1,
9782 +       PCIC_tnr_m      = 0x00000002,
9783 +       PCIC_sce_b      = 2,
9784 +       PCIC_sce_m      = 0x00000004,
9785 +       PCIC_ien_b      = 3,
9786 +       PCIC_ien_m      = 0x00000008,
9787 +       PCIC_aaa_b      = 4,
9788 +       PCIC_aaa_m      = 0x00000010,
9789 +       PCIC_eap_b      = 5,
9790 +       PCIC_eap_m      = 0x00000020,
9791 +       PCIC_pcim_b     = 6,
9792 +       PCIC_pcim_m     = 0x000001c0,
9793 +               PCIC_pcim_disabled_v    = 0,
9794 +               PCIC_pcim_tnr_v         = 1,    // Satellite - target not ready
9795 +               PCIC_pcim_suspend_v     = 2,    // Satellite - suspended CPU.
9796 +               PCIC_pcim_extern_v      = 3,    // Host - external arbiter.
9797 +               PCIC_pcim_fixed_v       = 4,    // Host - fixed priority arb.
9798 +               PCIC_pcim_roundrobin_v  = 5,    // Host - round robin priority.
9799 +               PCIC_pcim_reserved6_v   = 6,
9800 +               PCIC_pcim_reserved7_v   = 7,
9801 +       PCIC_igm_b      = 9,
9802 +       PCIC_igm_m      = 0x00000200,
9803 +} ;
9804 +
9805 +/*******************************************************************************
9806 + *
9807 + * PCI Status Register
9808 + *
9809 + ******************************************************************************/
9810 +enum {
9811 +       PCIS_eed_b      = 0,
9812 +       PCIS_eed_m      = 0x00000001,
9813 +       PCIS_wr_b       = 1,
9814 +       PCIS_wr_m       = 0x00000002,
9815 +       PCIS_nmi_b      = 2,
9816 +       PCIS_nmi_m      = 0x00000004,
9817 +       PCIS_ii_b       = 3,
9818 +       PCIS_ii_m       = 0x00000008,
9819 +       PCIS_cwe_b      = 4,
9820 +       PCIS_cwe_m      = 0x00000010,
9821 +       PCIS_cre_b      = 5,
9822 +       PCIS_cre_m      = 0x00000020,
9823 +       PCIS_mdpe_b     = 6,
9824 +       PCIS_mdpe_m     = 0x00000040,
9825 +       PCIS_sta_b      = 7,
9826 +       PCIS_sta_m      = 0x00000080,
9827 +       PCIS_rta_b      = 8,
9828 +       PCIS_rta_m      = 0x00000100,
9829 +       PCIS_rma_b      = 9,
9830 +       PCIS_rma_m      = 0x00000200,
9831 +       PCIS_sse_b      = 10,
9832 +       PCIS_sse_m      = 0x00000400,
9833 +       PCIS_ose_b      = 11,
9834 +       PCIS_ose_m      = 0x00000800,
9835 +       PCIS_pe_b       = 12,
9836 +       PCIS_pe_m       = 0x00001000,
9837 +       PCIS_tae_b      = 13,
9838 +       PCIS_tae_m      = 0x00002000,
9839 +       PCIS_rle_b      = 14,
9840 +       PCIS_rle_m      = 0x00004000,
9841 +       PCIS_bme_b      = 15,
9842 +       PCIS_bme_m      = 0x00008000,
9843 +       PCIS_prd_b      = 16,
9844 +       PCIS_prd_m      = 0x00010000,
9845 +       PCIS_rip_b      = 17,
9846 +       PCIS_rip_m      = 0x00020000,
9847 +} ;
9848 +
9849 +/*******************************************************************************
9850 + *
9851 + * PCI Status Mask Register
9852 + *
9853 + ******************************************************************************/
9854 +enum {
9855 +       PCISM_eed_b             = 0,
9856 +       PCISM_eed_m             = 0x00000001,
9857 +       PCISM_wr_b              = 1,
9858 +       PCISM_wr_m              = 0x00000002,
9859 +       PCISM_nmi_b             = 2,
9860 +       PCISM_nmi_m             = 0x00000004,
9861 +       PCISM_ii_b              = 3,
9862 +       PCISM_ii_m              = 0x00000008,
9863 +       PCISM_cwe_b             = 4,
9864 +       PCISM_cwe_m             = 0x00000010,
9865 +       PCISM_cre_b             = 5,
9866 +       PCISM_cre_m             = 0x00000020,
9867 +       PCISM_mdpe_b            = 6,
9868 +       PCISM_mdpe_m            = 0x00000040,
9869 +       PCISM_sta_b             = 7,
9870 +       PCISM_sta_m             = 0x00000080,
9871 +       PCISM_rta_b             = 8,
9872 +       PCISM_rta_m             = 0x00000100,
9873 +       PCISM_rma_b             = 9,
9874 +       PCISM_rma_m             = 0x00000200,
9875 +       PCISM_sse_b             = 10,
9876 +       PCISM_sse_m             = 0x00000400,
9877 +       PCISM_ose_b             = 11,
9878 +       PCISM_ose_m             = 0x00000800,
9879 +       PCISM_pe_b              = 12,
9880 +       PCISM_pe_m              = 0x00001000,
9881 +       PCISM_tae_b             = 13,
9882 +       PCISM_tae_m             = 0x00002000,
9883 +       PCISM_rle_b             = 14,
9884 +       PCISM_rle_m             = 0x00004000,
9885 +       PCISM_bme_b             = 15,
9886 +       PCISM_bme_m             = 0x00008000,
9887 +       PCISM_prd_b             = 16,
9888 +       PCISM_prd_m             = 0x00010000,
9889 +       PCISM_rip_b             = 17,
9890 +       PCISM_rip_m             = 0x00020000,
9891 +} ;
9892 +
9893 +/*******************************************************************************
9894 + *
9895 + * PCI Configuration Address Register
9896 + *
9897 + ******************************************************************************/
9898 +enum {
9899 +       PCICFGA_reg_b           = 2,
9900 +       PCICFGA_reg_m           = 0x000000fc,
9901 +               PCICFGA_reg_id_v        = 0x00>>2, //use PCFGID_
9902 +               PCICFGA_reg_04_v        = 0x04>>2, //use PCFG04_
9903 +               PCICFGA_reg_08_v        = 0x08>>2, //use PCFG08_
9904 +               PCICFGA_reg_0C_v        = 0x0C>>2, //use PCFG0C_
9905 +               PCICFGA_reg_pba0_v      = 0x10>>2, //use PCIPBA_
9906 +               PCICFGA_reg_pba1_v      = 0x14>>2, //use PCIPBA_
9907 +               PCICFGA_reg_pba2_v      = 0x18>>2, //use PCIPBA_
9908 +               PCICFGA_reg_pba3_v      = 0x1c>>2, //use PCIPBA_
9909 +               PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
9910 +               PCICFGA_reg_3C_v        = 0x3C>>2, //use PCFG3C_
9911 +               PCICFGA_reg_pba0c_v     = 0x44>>2, //use PCIPBAC_
9912 +               PCICFGA_reg_pba0m_v     = 0x48>>2,
9913 +               PCICFGA_reg_pba1c_v     = 0x4c>>2, //use PCIPBAC_
9914 +               PCICFGA_reg_pba1m_v     = 0x50>>2,
9915 +               PCICFGA_reg_pba2c_v     = 0x54>>2, //use PCIPBAC_
9916 +               PCICFGA_reg_pba2m_v     = 0x58>>2,
9917 +               PCICFGA_reg_pba3c_v     = 0x5c>>2, //use PCIPBAC_
9918 +               PCICFGA_reg_pba3m_v     = 0x60>>2,
9919 +               PCICFGA_reg_pmgt_v      = 0x64>>2,
9920 +       PCICFGA_func_b          = 8,
9921 +       PCICFGA_func_m          = 0x00000700,
9922 +       PCICFGA_dev_b           = 11,
9923 +       PCICFGA_dev_m           = 0x0000f800,
9924 +               PCICFGA_dev_internal_v  = 0,
9925 +       PCICFGA_bus_b           = 16,
9926 +       PCICFGA_bus_m           = 0x00ff0000,
9927 +               PCICFGA_bus_type0_v     = 0,    //local bus
9928 +       PCICFGA_en_b            = 31,           // read only
9929 +       PCICFGA_en_m            = 0x80000000,
9930 +} ;
9931 +
9932 +enum {
9933 +       PCFGID_vendor_b         = 0,
9934 +       PCFGID_vendor_m         = 0x0000ffff,
9935 +               PCFGID_vendor_IDT_v             = 0x111d,
9936 +       PCFGID_device_b         = 16,
9937 +       PCFGID_device_m         = 0xffff0000,
9938 +               PCFGID_device_Acaciade_v        = 0x0207,
9939 +
9940 +       PCFG04_command_ioena_b          = 1,
9941 +       PCFG04_command_ioena_m          = 0x00000001,
9942 +       PCFG04_command_memena_b         = 2,
9943 +       PCFG04_command_memena_m         = 0x00000002,
9944 +       PCFG04_command_bmena_b          = 3,
9945 +       PCFG04_command_bmena_m          = 0x00000004,
9946 +       PCFG04_command_mwinv_b          = 5,
9947 +       PCFG04_command_mwinv_m          = 0x00000010,
9948 +       PCFG04_command_parena_b         = 7,
9949 +       PCFG04_command_parena_m         = 0x00000040,
9950 +       PCFG04_command_serrena_b        = 9,
9951 +       PCFG04_command_serrena_m        = 0x00000100,
9952 +       PCFG04_command_fastbbena_b      = 10,
9953 +       PCFG04_command_fastbbena_m      = 0x00000200,
9954 +       PCFG04_status_b                 = 16,
9955 +       PCFG04_status_m                 = 0xffff0000,
9956 +       PCFG04_status_66MHz_b           = 21,   // 66 MHz enable
9957 +       PCFG04_status_66MHz_m           = 0x00200000,
9958 +       PCFG04_status_fbb_b             = 23,
9959 +       PCFG04_status_fbb_m             = 0x00800000,
9960 +       PCFG04_status_mdpe_b            = 24,
9961 +       PCFG04_status_mdpe_m            = 0x01000000,
9962 +       PCFG04_status_dst_b             = 25,
9963 +       PCFG04_status_dst_m             = 0x06000000,
9964 +       PCFG04_status_sta_b             = 27,
9965 +       PCFG04_status_sta_m             = 0x08000000,
9966 +       PCFG04_status_rta_b             = 28,
9967 +       PCFG04_status_rta_m             = 0x10000000,
9968 +       PCFG04_status_rma_b             = 29,
9969 +       PCFG04_status_rma_m             = 0x20000000,
9970 +       PCFG04_status_sse_b             = 30,
9971 +       PCFG04_status_sse_m             = 0x40000000,
9972 +       PCFG04_status_pe_b              = 31,
9973 +       PCFG04_status_pe_m              = 0x40000000,
9974 +
9975 +       PCFG08_revId_b                  = 0,
9976 +       PCFG08_revId_m                  = 0x000000ff,
9977 +       PCFG08_classCode_b              = 0,
9978 +       PCFG08_classCode_m              = 0xffffff00,
9979 +               PCFG08_classCode_bridge_v       = 06,
9980 +               PCFG08_classCode_proc_v         = 0x0b3000, // processor-MIPS
9981 +       PCFG0C_cacheline_b              = 0,
9982 +       PCFG0C_cacheline_m              = 0x000000ff,
9983 +       PCFG0C_masterLatency_b          = 8,
9984 +       PCFG0C_masterLatency_m          = 0x0000ff00,
9985 +       PCFG0C_headerType_b             = 16,
9986 +       PCFG0C_headerType_m             = 0x00ff0000,
9987 +       PCFG0C_bist_b                   = 24,
9988 +       PCFG0C_bist_m                   = 0xff000000,
9989 +
9990 +       PCIPBA_msi_b                    = 0,
9991 +       PCIPBA_msi_m                    = 0x00000001,
9992 +       PCIPBA_p_b                      = 3,
9993 +       PCIPBA_p_m                      = 0x00000004,
9994 +       PCIPBA_baddr_b                  = 8,
9995 +       PCIPBA_baddr_m                  = 0xffffff00,
9996 +
9997 +       PCFGSS_vendorId_b               = 0,
9998 +       PCFGSS_vendorId_m               = 0x0000ffff,
9999 +       PCFGSS_id_b                     = 16,
10000 +       PCFGSS_id_m                     = 0xffff0000,
10001 +
10002 +       PCFG3C_interruptLine_b          = 0,
10003 +       PCFG3C_interruptLine_m          = 0x000000ff,
10004 +       PCFG3C_interruptPin_b           = 8,
10005 +       PCFG3C_interruptPin_m           = 0x0000ff00,
10006 +       PCFG3C_minGrant_b               = 16,
10007 +       PCFG3C_minGrant_m               = 0x00ff0000,
10008 +       PCFG3C_maxLat_b                 = 24,
10009 +       PCFG3C_maxLat_m                 = 0xff000000,
10010 +
10011 +       PCIPBAC_msi_b                   = 0,
10012 +       PCIPBAC_msi_m                   = 0x00000001,
10013 +       PCIPBAC_p_b                     = 1,
10014 +       PCIPBAC_p_m                     = 0x00000002,
10015 +       PCIPBAC_size_b                  = 2,
10016 +       PCIPBAC_size_m                  = 0x0000007c,
10017 +       PCIPBAC_sb_b                    = 7,
10018 +       PCIPBAC_sb_m                    = 0x00000080,
10019 +       PCIPBAC_pp_b                    = 8,
10020 +       PCIPBAC_pp_m                    = 0x00000100,
10021 +       PCIPBAC_mr_b                    = 9,
10022 +       PCIPBAC_mr_m                    = 0x00000600,
10023 +               PCIPBAC_mr_read_v       =0,     //no prefetching
10024 +               PCIPBAC_mr_readLine_v   =1,
10025 +               PCIPBAC_mr_readMult_v   =2,
10026 +       PCIPBAC_mrl_b                   = 11,
10027 +       PCIPBAC_mrl_m                   = 0x00000800,
10028 +       PCIPBAC_mrm_b                   = 12,
10029 +       PCIPBAC_mrm_m                   = 0x00001000,
10030 +       PCIPBAC_trp_b                   = 13,
10031 +       PCIPBAC_trp_m                   = 0x00002000,
10032 +
10033 +       PCFG40_trdyTimeout_b            = 0,
10034 +       PCFG40_trdyTimeout_m            = 0x000000ff,
10035 +       PCFG40_retryLim_b               = 8,
10036 +       PCFG40_retryLim_m               = 0x0000ff00,
10037 +};
10038 +
10039 +/*******************************************************************************
10040 + *
10041 + * PCI Local Base Address [0|1|2|3] Register
10042 + *
10043 + ******************************************************************************/
10044 +enum {
10045 +       PCILBA_baddr_b          = 0,            // In PCI_t -> pcilba [] .a
10046 +       PCILBA_baddr_m          = 0xffffff00,
10047 +} ;
10048 +/*******************************************************************************
10049 + *
10050 + * PCI Local Base Address Control Register
10051 + *
10052 + ******************************************************************************/
10053 +enum {
10054 +       PCILBAC_msi_b           = 0,            // In pPci->pcilba[i].c
10055 +       PCILBAC_msi_m           = 0x00000001,
10056 +               PCILBAC_msi_mem_v       = 0,
10057 +               PCILBAC_msi_io_v        = 1,
10058 +       PCILBAC_size_b          = 2,    // In pPci->pcilba[i].c
10059 +       PCILBAC_size_m          = 0x0000007c,
10060 +       PCILBAC_sb_b            = 7,    // In pPci->pcilba[i].c
10061 +       PCILBAC_sb_m            = 0x00000080,
10062 +       PCILBAC_rt_b            = 8,    // In pPci->pcilba[i].c
10063 +       PCILBAC_rt_m            = 0x00000100,
10064 +               PCILBAC_rt_noprefetch_v = 0, // mem read
10065 +               PCILBAC_rt_prefetch_v   = 1, // mem readline
10066 +} ;
10067 +
10068 +/*******************************************************************************
10069 + *
10070 + * PCI Local Base Address [0|1|2|3] Mapping Register
10071 + *
10072 + ******************************************************************************/
10073 +enum {
10074 +       PCILBAM_maddr_b         = 8,
10075 +       PCILBAM_maddr_m         = 0xffffff00,
10076 +} ;
10077 +
10078 +/*******************************************************************************
10079 + *
10080 + * PCI Decoupled Access Control Register
10081 + *
10082 + ******************************************************************************/
10083 +enum {
10084 +       PCIDAC_den_b            = 0,
10085 +       PCIDAC_den_m            = 0x00000001,
10086 +} ;
10087 +
10088 +/*******************************************************************************
10089 + *
10090 + * PCI Decoupled Access Status Register
10091 + *
10092 + ******************************************************************************/
10093 +enum {
10094 +       PCIDAS_d_b      = 0,
10095 +       PCIDAS_d_m      = 0x00000001,
10096 +       PCIDAS_b_b      = 1,
10097 +       PCIDAS_b_m      = 0x00000002,
10098 +       PCIDAS_e_b      = 2,
10099 +       PCIDAS_e_m      = 0x00000004,
10100 +       PCIDAS_ofe_b    = 3,
10101 +       PCIDAS_ofe_m    = 0x00000008,
10102 +       PCIDAS_off_b    = 4,
10103 +       PCIDAS_off_m    = 0x00000010,
10104 +       PCIDAS_ife_b    = 5,
10105 +       PCIDAS_ife_m    = 0x00000020,
10106 +       PCIDAS_iff_b    = 6,
10107 +       PCIDAS_iff_m    = 0x00000040,
10108 +} ;
10109 +
10110 +/*******************************************************************************
10111 + *
10112 + * PCI DMA Channel 8 Configuration Register
10113 + *
10114 + ******************************************************************************/
10115 +enum
10116 +{
10117 +       PCIDMA8C_mbs_b  = 0,            // Maximum Burst Size.
10118 +       PCIDMA8C_mbs_m  = 0x00000fff,   // { pcidma8c }
10119 +       PCIDMA8C_our_b  = 12,           // Optimize Unaligned Burst Reads.
10120 +       PCIDMA8C_our_m  = 0x00001000,   // { pcidma8c }
10121 +} ;
10122 +
10123 +/*******************************************************************************
10124 + *
10125 + * PCI DMA Channel 9 Configuration Register
10126 + *
10127 + ******************************************************************************/
10128 +enum
10129 +{
10130 +       PCIDMA9C_mbs_b  = 0,            // Maximum Burst Size.
10131 +       PCIDMA9C_mbs_m  = 0x00000fff, // { pcidma9c }
10132 +} ;
10133 +
10134 +/*******************************************************************************
10135 + *
10136 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
10137 + *
10138 + ******************************************************************************/
10139 +enum {
10140 +       PCIDMAD_pt_b            = 22,           // in DEVCMD field (descriptor)
10141 +       PCIDMAD_pt_m            = 0x00c00000,   // preferred transaction field
10142 +               // These are for reads (DMA channel 8)
10143 +               PCIDMAD_devcmd_mr_v     = 0,    //memory read
10144 +               PCIDMAD_devcmd_mrl_v    = 1,    //memory read line
10145 +               PCIDMAD_devcmd_mrm_v    = 2,    //memory read multiple
10146 +               PCIDMAD_devcmd_ior_v    = 3,    //I/O read
10147 +               // These are for writes (DMA channel 9)
10148 +               PCIDMAD_devcmd_mw_v     = 0,    //memory write
10149 +               PCIDMAD_devcmd_mwi_v    = 1,    //memory write invalidate
10150 +               PCIDMAD_devcmd_iow_v    = 3,    //I/O write
10151 +
10152 +       // Swap byte field applies to both DMA channel 8 and 9
10153 +       PCIDMAD_sb_b            = 24,           // in DEVCMD field (descriptor)
10154 +       PCIDMAD_sb_m            = 0x01000000,   // swap byte field
10155 +} ;
10156 +
10157 +
10158 +/*******************************************************************************
10159 + *
10160 + * PCI Target Control Register
10161 + *
10162 + ******************************************************************************/
10163 +enum
10164 +{
10165 +       PCITC_rtimer_b          = 0,            // In PCITC_t -> pcitc
10166 +       PCITC_rtimer_m          = 0x000000ff,
10167 +       PCITC_dtimer_b          = 8,            // In PCITC_t -> pcitc
10168 +       PCITC_dtimer_m          = 0x0000ff00,
10169 +       PCITC_rdr_b             = 18,           // In PCITC_t -> pcitc
10170 +       PCITC_rdr_m             = 0x00040000,
10171 +       PCITC_ddt_b             = 19,           // In PCITC_t -> pcitc
10172 +       PCITC_ddt_m             = 0x00080000,
10173 +} ;
10174 +/*******************************************************************************
10175 + *
10176 + * PCI messaging unit [applies to both inbound and outbound registers ]
10177 + *
10178 + ******************************************************************************/
10179 +enum
10180 +{
10181 +       PCIM_m0_b       = 0,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10182 +       PCIM_m0_m       = 0x00000001,   // inbound or outbound message 0
10183 +       PCIM_m1_b       = 1,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10184 +       PCIM_m1_m       = 0x00000002,   // inbound or outbound message 1
10185 +       PCIM_db_b       = 2,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10186 +       PCIM_db_m       = 0x00000004,   // inbound or outbound doorbell
10187 +};
10188 +
10189 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h
10190 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h    1970-01-01 01:00:00.000000000 +0100
10191 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h       2006-06-18 12:44:28.000000000 +0200
10192 @@ -0,0 +1,190 @@
10193 +/**************************************************************************
10194 + *
10195 + *  BRIEF MODULE DESCRIPTION
10196 + *   Definitions for IDT RC32438 PCI setup.
10197 + *
10198 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
10199 + *
10200 + *  This program is free software; you can redistribute  it and/or modify it
10201 + *  under  the terms of  the GNU General  Public License as published by the
10202 + *  Free Software Foundation;  either version 2 of the  License, or (at your
10203 + *  option) any later version.
10204 + *
10205 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
10206 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
10207 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
10208 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
10209 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10210 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
10211 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10212 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
10213 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10214 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10215 + *
10216 + *  You should have received a copy of the  GNU General Public License along
10217 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
10218 + *  675 Mass Ave, Cambridge, MA 02139, USA.
10219 + *
10220 + *
10221 + **************************************************************************
10222 + * May 2004 P. Sadik
10223 + *
10224 + * Initial Release
10225 + *
10226 + *
10227 + *
10228 + **************************************************************************
10229 + */
10230 +
10231 +#define PCI_MSG_VirtualAddress      0xB8088010
10232 +#define rc32438_pci ((volatile PCI_t) PCI0_VirtualAddress)
10233 +#define rc32438_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
10234 +
10235 +#define PCIM_SHFT              0x6
10236 +#define PCIM_BIT_LEN           0x7
10237 +#define PCIM_H_EA              0x3
10238 +#define PCIM_H_IA_FIX          0x4
10239 +#define PCIM_H_IA_RR           0x5
10240 +
10241 +#define PCI_ADDR_START         0x50000000
10242 +
10243 +#define CPUTOPCI_MEM_WIN       0x02000000
10244 +#define CPUTOPCI_IO_WIN                0x00100000
10245 +#define PCILBA_SIZE_SHFT       2
10246 +#define PCILBA_SIZE_MASK       0x1F
10247 +#define SIZE_256MB             0x1C
10248 +#define SIZE_128MB             0x1B
10249 +#define SIZE_64MB               0x1A
10250 +#define SIZE_32MB              0x19
10251 +#define SIZE_16MB               0x18
10252 +#define SIZE_4MB               0x16
10253 +#define SIZE_2MB               0x15
10254 +#define SIZE_1MB               0x14
10255 +#define ACACIA_CONFIG0_ADDR    0x80000000
10256 +#define ACACIA_CONFIG1_ADDR    0x80000004
10257 +#define ACACIA_CONFIG2_ADDR    0x80000008
10258 +#define ACACIA_CONFIG3_ADDR    0x8000000C
10259 +#define ACACIA_CONFIG4_ADDR    0x80000010
10260 +#define ACACIA_CONFIG5_ADDR    0x80000014
10261 +#define ACACIA_CONFIG6_ADDR    0x80000018
10262 +#define ACACIA_CONFIG7_ADDR    0x8000001C
10263 +#define ACACIA_CONFIG8_ADDR    0x80000020
10264 +#define ACACIA_CONFIG9_ADDR    0x80000024
10265 +#define ACACIA_CONFIG10_ADDR   0x80000028
10266 +#define ACACIA_CONFIG11_ADDR   0x8000002C
10267 +#define ACACIA_CONFIG12_ADDR   0x80000030
10268 +#define ACACIA_CONFIG13_ADDR   0x80000034
10269 +#define ACACIA_CONFIG14_ADDR   0x80000038
10270 +#define ACACIA_CONFIG15_ADDR   0x8000003C
10271 +#define ACACIA_CONFIG16_ADDR   0x80000040
10272 +#define ACACIA_CONFIG17_ADDR   0x80000044
10273 +#define ACACIA_CONFIG18_ADDR   0x80000048
10274 +#define ACACIA_CONFIG19_ADDR   0x8000004C
10275 +#define ACACIA_CONFIG20_ADDR   0x80000050
10276 +#define ACACIA_CONFIG21_ADDR   0x80000054
10277 +#define ACACIA_CONFIG22_ADDR   0x80000058
10278 +#define ACACIA_CONFIG23_ADDR   0x8000005C
10279 +#define ACACIA_CONFIG24_ADDR   0x80000060
10280 +#define ACACIA_CONFIG25_ADDR   0x80000064
10281 +#define ACACIA_CMD             (PCFG04_command_ioena_m | \
10282 +                                PCFG04_command_memena_m | \
10283 +                                PCFG04_command_bmena_m | \
10284 +                                PCFG04_command_mwinv_m | \
10285 +                                PCFG04_command_parena_m | \
10286 +                                PCFG04_command_serrena_m )
10287 +
10288 +#define ACACIA_STAT            (PCFG04_status_mdpe_m | \
10289 +                                PCFG04_status_sta_m  | \
10290 +                                PCFG04_status_rta_m  | \
10291 +                                PCFG04_status_rma_m  | \
10292 +                                PCFG04_status_sse_m  | \
10293 +                                PCFG04_status_pe_m)
10294 +
10295 +#define ACACIA_CNFG1           ((ACACIA_STAT<<16)|ACACIA_CMD)
10296 +
10297 +#define ACACIA_REVID           0
10298 +#define ACACIA_CLASS_CODE      0
10299 +#define ACACIA_CNFG2           ((ACACIA_CLASS_CODE<<8) | \
10300 +                                 ACACIA_REVID)
10301 +
10302 +#define ACACIA_CACHE_LINE_SIZE 4
10303 +#define ACACIA_MASTER_LAT      0x3c
10304 +#define ACACIA_HEADER_TYPE     0
10305 +#define ACACIA_BIST            0
10306 +
10307 +#define ACACIA_CNFG3 ((ACACIA_BIST << 24) | \
10308 +                     (ACACIA_HEADER_TYPE<<16) | \
10309 +                     (ACACIA_MASTER_LAT<<8) | \
10310 +                     ACACIA_CACHE_LINE_SIZE )
10311 +
10312 +#define ACACIA_BAR0    0x00000008 /* 128 MB Memory */
10313 +#define ACACIA_BAR1    0x18800001 /* 1 MB IO */
10314 +#define ACACIA_BAR2    0x18000001 /* 2 MB IO window for Acacia
10315 +                                       internal Registers */
10316 +#define ACACIA_BAR3    0x48000008 /* Spare 128 MB Memory */
10317 +
10318 +#define ACACIA_CNFG4   ACACIA_BAR0
10319 +#define ACACIA_CNFG5    ACACIA_BAR1
10320 +#define ACACIA_CNFG6   ACACIA_BAR2
10321 +#define ACACIA_CNFG7   ACACIA_BAR3
10322 +
10323 +#define ACACIA_SUBSYS_VENDOR_ID 0
10324 +#define ACACIA_SUBSYSTEM_ID    0
10325 +#define ACACIA_CNFG8           0
10326 +#define ACACIA_CNFG9           0
10327 +#define ACACIA_CNFG10          0
10328 +#define ACACIA_CNFG11  ((ACACIA_SUBSYS_VENDOR_ID<<16) | \
10329 +                         ACACIA_SUBSYSTEM_ID)
10330 +#define ACACIA_INT_LINE                1
10331 +#define ACACIA_INT_PIN         1
10332 +#define ACACIA_MIN_GNT         8
10333 +#define ACACIA_MAX_LAT         0x38
10334 +#define ACACIA_CNFG12          0
10335 +#define ACACIA_CNFG13          0
10336 +#define ACACIA_CNFG14          0
10337 +#define ACACIA_CNFG15  ((ACACIA_MAX_LAT<<24) | \
10338 +                        (ACACIA_MIN_GNT<<16) | \
10339 +                        (ACACIA_INT_PIN<<8)  | \
10340 +                         ACACIA_INT_LINE)
10341 +#define        ACACIA_RETRY_LIMIT      0x80
10342 +#define ACACIA_TRDY_LIMIT      0x80
10343 +#define ACACIA_CNFG16 ((ACACIA_RETRY_LIMIT<<8) | \
10344 +                       ACACIA_TRDY_LIMIT)
10345 +#define PCI_PBAxC_R            0x0
10346 +#define PCI_PBAxC_RL           0x1
10347 +#define PCI_PBAxC_RM           0x2
10348 +#define SIZE_SHFT              2
10349 +
10350 +#define ACACIA_PBA0C   ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
10351 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
10352 +                         PCIPBAC_pp_m | \
10353 +                         (SIZE_128MB<<SIZE_SHFT) | \
10354 +                          PCIPBAC_p_m)
10355 +
10356 +#define ACACIA_CNFG17  ACACIA_PBA0C
10357 +#define ACACIA_PBA0M   0x0
10358 +#define ACACIA_CNFG18  ACACIA_PBA0M
10359 +
10360 +#define ACACIA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10361 +                         PCIPBAC_msi_m)
10362 +
10363 +#define ACACIA_CNFG19  ACACIA_PBA1C
10364 +#define ACACIA_PBA1M   0x0
10365 +#define ACACIA_CNFG20  ACACIA_PBA1M
10366 +
10367 +#define ACACIA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10368 +                         PCIPBAC_msi_m)
10369 +
10370 +#define ACACIA_CNFG21  ACACIA_PBA2C
10371 +#define ACACIA_PBA2M   0x18000000
10372 +#define ACACIA_CNFG22  ACACIA_PBA2M
10373 +#define ACACIA_PBA3C   0
10374 +#define ACACIA_CNFG23  ACACIA_PBA3C
10375 +#define ACACIA_PBA3M   0
10376 +#define ACACIA_CNFG24  ACACIA_PBA3M
10377 +
10378 +
10379 +
10380 +#define        PCITC_DTIMER_VAL        8
10381 +#define PCITC_RTIMER_VAL       0x10
10382 +
10383 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_timer.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h
10384 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_timer.h    1970-01-01 01:00:00.000000000 +0100
10385 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h       2006-06-18 12:44:28.000000000 +0200
10386 @@ -0,0 +1,91 @@
10387 +/**************************************************************************
10388 + *
10389 + *  BRIEF MODULE DESCRIPTION
10390 + *    Timer register definition IDT RC32438 CPU.
10391 + *
10392 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
10393 + *
10394 + *  This program is free software; you can redistribute  it and/or modify it
10395 + *  under  the terms of  the GNU General  Public License as published by the
10396 + *  Free Software Foundation;  either version 2 of the  License, or (at your
10397 + *  option) any later version.
10398 + *
10399 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
10400 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
10401 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
10402 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
10403 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10404 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
10405 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10406 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
10407 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10408 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10409 + *
10410 + *  You should have received a copy of the  GNU General Public License along
10411 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
10412 + *  675 Mass Ave, Cambridge, MA 02139, USA.
10413 + *
10414 + *
10415 + **************************************************************************
10416 + * May 2004 P. Sadik.
10417 + *
10418 + * Initial Release
10419 + *
10420 + *
10421 + *
10422 + **************************************************************************
10423 + */
10424 +
10425 +#ifndef __IDT_RC32438_TIM_H__
10426 +#define __IDT_RC32438_TIM_H__
10427 +
10428 +enum
10429 +{
10430 +       TIM0_PhysicalAddress    = 0x18028000,
10431 +       TIM_PhysicalAddress     = TIM0_PhysicalAddress,         // Default
10432 +
10433 +       TIM0_VirtualAddress     = 0xb8028000,
10434 +       TIM_VirtualAddress      = TIM0_VirtualAddress,          // Default
10435 +} ;
10436 +
10437 +enum
10438 +{
10439 +       TIM_Count = 3,
10440 +} ;
10441 +
10442 +struct TIM_CNTR_s
10443 +{
10444 +       u32 count ;
10445 +       u32 compare ;
10446 +       u32 ctc ;       //use CTC_
10447 +} ;
10448 +
10449 +typedef struct TIM_s
10450 +{
10451 +       struct TIM_CNTR_s       tim [TIM_Count] ;
10452 +       u32                     rcount ;        //use RCOUNT_
10453 +       u32                     rcompare ;      //use RCOMPARE_
10454 +       u32                     rtc ;           //use RTC_
10455 +} volatile * TIM_t ;
10456 +
10457 +enum
10458 +{
10459 +       CTC_en_b        = 0,
10460 +       CTC_en_m        = 0x00000001,
10461 +       CTC_to_b        = 1,
10462 +       CTC_to_m        = 0x00000002,
10463 +
10464 +       RCOUNT_count_b          = 0,
10465 +       RCOUNT_count_m          = 0x0000ffff,
10466 +       RCOMPARE_compare_b      = 0,
10467 +       RCOMPARE_compare_m      = 0x0000ffff,
10468 +       RTC_ce_b                = 0,
10469 +       RTC_ce_m                = 0x00000001,
10470 +       RTC_to_b                = 1,
10471 +       RTC_to_m                = 0x00000002,
10472 +       RTC_rqe_b               = 2,
10473 +       RTC_rqe_m               = 0x00000004,
10474 +
10475 +} ;
10476 +#endif //__IDT_RC32438_TIM_H__
10477 +
10478 diff -Nur linux-2.6.17/include/asm-mips/mach-generic/irq.h linux-2.6.17-owrt/include/asm-mips/mach-generic/irq.h
10479 --- linux-2.6.17/include/asm-mips/mach-generic/irq.h    2006-06-18 03:49:35.000000000 +0200
10480 +++ linux-2.6.17-owrt/include/asm-mips/mach-generic/irq.h       2006-06-18 12:44:28.000000000 +0200
10481 @@ -8,6 +8,6 @@
10482  #ifndef __ASM_MACH_GENERIC_IRQ_H
10483  #define __ASM_MACH_GENERIC_IRQ_H
10484
10485 -#define NR_IRQS        128
10486 +#define NR_IRQS        256
10487
10488  #endif /* __ASM_MACH_GENERIC_IRQ_H */
10489 diff -Nur linux-2.6.17/include/linux/kernel.h linux-2.6.17-owrt/include/linux/kernel.h
10490 --- linux-2.6.17/include/linux/kernel.h 2006-06-18 03:49:35.000000000 +0200
10491 +++ linux-2.6.17-owrt/include/linux/kernel.h    2006-06-18 12:44:28.000000000 +0200
10492 @@ -329,6 +329,7 @@
10493  };
10494
10495  /* Force a compilation error if condition is true */
10496 +extern void BUILD_BUG(void);
10497  #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
10498
10499  /* Trap pasters of __FUNCTION__ at compile-time */