ar71xx: use backported PCI patches
[openwrt.git] / target / linux / ar71xx / patches-3.8 / 167-MIPS-ath79-add-USB-controller-registration-code-for-.patch
1 From e4ba5e2bffd1f373f57dd692233aa6b7b46ae76c Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Sun, 24 Jun 2012 13:47:35 +0200
4 Subject: [PATCH 23/34] MIPS: ath79: add USB controller registration code for the QCA955X SoCs
5
6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
7 ---
8  arch/mips/ath79/dev-usb.c                      |   46 ++++++++++++++++++++++++
9  arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    4 ++
10  2 files changed, 50 insertions(+), 0 deletions(-)
11
12 --- a/arch/mips/ath79/dev-usb.c
13 +++ b/arch/mips/ath79/dev-usb.c
14 @@ -73,6 +73,8 @@ static void __init ath79_usb_init_resour
15                                            unsigned long size,
16                                            int irq)
17  {
18 +       memset(res, 0, sizeof(res));
19 +
20         res[0].flags = IORESOURCE_MEM;
21         res[0].start = base;
22         res[0].end = base + size - 1;
23 @@ -217,6 +219,48 @@ static void __init ar934x_usb_setup(void
24         platform_device_register(&ath79_ehci_device);
25  }
26  
27 +static void __init qca955x_usb_setup(void)
28 +{
29 +       struct platform_device *pdev;
30 +
31 +       ath79_usb_init_resource(ath79_ehci_resources,
32 +                               QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
33 +                               ATH79_IP3_IRQ(0));
34 +
35 +       pdev = platform_device_register_resndata(NULL, "ehci-platform", 0,
36 +                                                ath79_ehci_resources,
37 +                                                ARRAY_SIZE(ath79_ehci_resources),
38 +                                                &ath79_ehci_pdata_v2,
39 +                                                sizeof(ath79_ehci_pdata_v2));
40 +       if (IS_ERR(pdev)) {
41 +               pr_err("Unable to register USB %d device, err=%d\n", 0,
42 +                       (int) PTR_ERR(pdev));
43 +               return;
44 +       }
45 +
46 +       pdev->dev.dma_mask = &ath79_ehci_dmamask;
47 +       pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
48 +
49 +       ath79_usb_init_resource(ath79_ehci_resources,
50 +                               QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
51 +                               ATH79_IP3_IRQ(1));
52 +
53 +       pdev = platform_device_register_resndata(NULL, "ehci-platform", 1,
54 +                                                ath79_ehci_resources,
55 +                                                ARRAY_SIZE(ath79_ehci_resources),
56 +                                                &ath79_ehci_pdata_v2,
57 +                                                sizeof(ath79_ehci_pdata_v2));
58 +
59 +       if (IS_ERR(pdev)) {
60 +               pr_err("Unable to register USB %d device, err=%d\n", 1,
61 +                       (int) PTR_ERR(pdev));
62 +               return;
63 +       }
64 +
65 +       pdev->dev.dma_mask = &ath79_ehci_dmamask;
66 +       pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
67 +}
68 +
69  void __init ath79_register_usb(void)
70  {
71         if (soc_is_ar71xx())
72 @@ -231,6 +275,8 @@ void __init ath79_register_usb(void)
73                 ar933x_usb_setup();
74         else if (soc_is_ar934x())
75                 ar934x_usb_setup();
76 +       else if (soc_is_qca955x())
77 +               qca955x_usb_setup();
78         else
79                 BUG();
80  }
81 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
82 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
83 @@ -94,6 +94,10 @@
84  #define AR934X_SRIF_BASE       (AR71XX_APB_BASE + 0x00116000)
85  #define AR934X_SRIF_SIZE       0x1000
86  
87 +#define QCA955X_EHCI0_BASE     0x1b000000
88 +#define QCA955X_EHCI1_BASE     0x1b400000
89 +#define QCA955X_EHCI_SIZE      0x200
90 +
91  /*
92   * DDR_CTRL block
93   */