target/linux/ar71xx/patches-3.8/029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch

   1 From f48780829e9de625cb7fa0850fc31d050da6adeb Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Fri, 15 Feb 2013 13:38:16 +0000
   4 Subject: [PATCH] MIPS: ath79: add SoC detection code for the QCA955X SoCs
   5
   6 commit 2e6c91e392fd7be2ef0ba1e9a20e0ebe8ab79cf3 upstream.
   7
   8 Also add 'soc_is_qca955[68x]' helper functions
   9 and a Kconfig symbol for the SoC family.
  10
  11 Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
  12 Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
  13 Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
  14 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  15 Patchwork: http://patchwork.linux-mips.org/patch/4943/
  16 Signed-off-by: John Crispin <blogic@openwrt.org>
  17 ---
  18  arch/mips/ath79/Kconfig                        |    4 ++++
  19  arch/mips/ath79/setup.c                        |   18 +++++++++++++++++-
  20  arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 ++
  21  arch/mips/include/asm/mach-ath79/ath79.h       |   17 +++++++++++++++++
  22  4 files changed, 40 insertions(+), 1 deletion(-)
  23
  24 --- a/arch/mips/ath79/Kconfig
  25 +++ b/arch/mips/ath79/Kconfig
  26 @@ -88,6 +88,10 @@ config SOC_AR934X
  27         select PCI_AR724X if PCI
  28         def_bool n
  29
  30 +config SOC_QCA955X
  31 +       select USB_ARCH_HAS_EHCI
  32 +       def_bool n
  33 +
  34  config PCI_AR724X
  35         def_bool n
  36
  37 --- a/arch/mips/ath79/setup.c
  38 +++ b/arch/mips/ath79/setup.c
  39 @@ -164,13 +164,29 @@ static void __init ath79_detect_sys_type
  40                 rev = id & AR934X_REV_ID_REVISION_MASK;
  41                 break;
  42
  43 +       case REV_ID_MAJOR_QCA9556:
  44 +               ath79_soc = ATH79_SOC_QCA9556;
  45 +               chip = "9556";
  46 +               rev = id & QCA955X_REV_ID_REVISION_MASK;
  47 +               break;
  48 +
  49 +       case REV_ID_MAJOR_QCA9558:
  50 +               ath79_soc = ATH79_SOC_QCA9558;
  51 +               chip = "9558";
  52 +               rev = id & QCA955X_REV_ID_REVISION_MASK;
  53 +               break;
  54 +
  55         default:
  56                 panic("ath79: unknown SoC, id:0x%08x", id);
  57         }
  58
  59         ath79_soc_rev = rev;
  60
  61 -       sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
  62 +       if (soc_is_qca955x())
  63 +               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
  64 +                       chip, rev);
  65 +       else
  66 +               sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
  67         pr_info("SoC: %s\n", ath79_sys_type);
  68  }
  69
  70 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  71 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  72 @@ -392,6 +392,8 @@
  73
  74  #define AR934X_REV_ID_REVISION_MASK     0xf
  75
  76 +#define QCA955X_REV_ID_REVISION_MASK   0xf
  77 +
  78  /*
  79   * SPI block
  80   */
  81 --- a/arch/mips/include/asm/mach-ath79/ath79.h
  82 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
  83 @@ -32,6 +32,8 @@ enum ath79_soc_type {
  84         ATH79_SOC_AR9341,
  85         ATH79_SOC_AR9342,
  86         ATH79_SOC_AR9344,
  87 +       ATH79_SOC_QCA9556,
  88 +       ATH79_SOC_QCA9558,
  89  };
  90
  91  extern enum ath79_soc_type ath79_soc;
  92 @@ -98,6 +100,21 @@ static inline int soc_is_ar934x(void)
  93         return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
  94  }
  95
  96 +static inline int soc_is_qca9556(void)
  97 +{
  98 +       return ath79_soc == ATH79_SOC_QCA9556;
  99 +}
 100 +
 101 +static inline int soc_is_qca9558(void)
 102 +{
 103 +       return ath79_soc == ATH79_SOC_QCA9558;
 104 +}
 105 +
 106 +static inline int soc_is_qca955x(void)
 107 +{
 108 +       return soc_is_qca9556() || soc_is_qca9558();
 109 +}
 110 +
 111  extern void __iomem *ath79_ddr_base;
 112  extern void __iomem *ath79_pll_base;
 113  extern void __iomem *ath79_reset_base;