target/linux/ar71xx/patches-3.8/013-MIPS-ath79-register-platform-devices-for-the-PCI-con.patch

   1 From 87cdbe4315e4c72c2bc8568d1258e1207e1c772b Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Sat, 2 Feb 2013 11:44:24 +0000
   4 Subject: [PATCH] MIPS: ath79: register platform devices for the PCI
   5  controllers
   6
   7 commit 9fc1ca5b73a82daedffa2d1d5daa48dd2093c39a upstream.
   8
   9 The pci-ar71xx and pci-ar724x drivers were converted
  10 into platform drivers. Register the corresponding
  11 platform devices for the PCI controllers instead
  12 of using the ar7{1x,24}x_pcibios_init functions.
  13
  14 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  15 Patchwork: http://patchwork.linux-mips.org/patch/4908/
  16 Signed-off-by: John Crispin <blogic@openwrt.org>
  17 ---
  18  arch/mips/ath79/pci.c |   87 ++++++++++++++++++++++++++++++++++++++++++++-----
  19  1 file changed, 78 insertions(+), 9 deletions(-)
  20
  21 --- a/arch/mips/ath79/pci.c
  22 +++ b/arch/mips/ath79/pci.c
  23 @@ -14,6 +14,8 @@
  24
  25  #include <linux/init.h>
  26  #include <linux/pci.h>
  27 +#include <linux/resource.h>
  28 +#include <linux/platform_device.h>
  29  #include <asm/mach-ath79/ar71xx_regs.h>
  30  #include <asm/mach-ath79/ath79.h>
  31  #include <asm/mach-ath79/irq.h>
  32 @@ -110,21 +112,88 @@ void __init ath79_pci_set_plat_dev_init(
  33         ath79_pci_plat_dev_init = func;
  34  }
  35
  36 -int __init ath79_register_pci(void)
  37 +static struct platform_device *
  38 +ath79_register_pci_ar71xx(void)
  39  {
  40 -       if (soc_is_ar71xx())
  41 -               return ar71xx_pcibios_init();
  42 +       struct platform_device *pdev;
  43 +       struct resource res[2];
  44 +
  45 +       memset(res, 0, sizeof(res));
  46
  47 -       if (soc_is_ar724x())
  48 -               return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
  49 +       res[0].name = "cfg_base";
  50 +       res[0].flags = IORESOURCE_MEM;
  51 +       res[0].start = AR71XX_PCI_CFG_BASE;
  52 +       res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
  53 +
  54 +       res[1].flags = IORESOURCE_IRQ;
  55 +       res[1].start = ATH79_CPU_IRQ_IP2;
  56 +       res[1].end = ATH79_CPU_IRQ_IP2;
  57 +
  58 +       pdev = platform_device_register_simple("ar71xx-pci", -1,
  59 +                                              res, ARRAY_SIZE(res));
  60 +       return pdev;
  61 +}
  62
  63 -       if (soc_is_ar9342() || soc_is_ar9344()) {
  64 +static struct platform_device *
  65 +ath79_register_pci_ar724x(int id,
  66 +                         unsigned long cfg_base,
  67 +                         unsigned long ctrl_base,
  68 +                         int irq)
  69 +{
  70 +       struct platform_device *pdev;
  71 +       struct resource res[3];
  72 +
  73 +       memset(res, 0, sizeof(res));
  74 +
  75 +       res[0].name = "cfg_base";
  76 +       res[0].flags = IORESOURCE_MEM;
  77 +       res[0].start = cfg_base;
  78 +       res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
  79 +
  80 +       res[1].name = "ctrl_base";
  81 +       res[1].flags = IORESOURCE_MEM;
  82 +       res[1].start = ctrl_base;
  83 +       res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
  84 +
  85 +       res[2].flags = IORESOURCE_IRQ;
  86 +       res[2].start = irq;
  87 +       res[2].end = irq;
  88 +
  89 +       pdev = platform_device_register_simple("ar724x-pci", id,
  90 +                                              res, ARRAY_SIZE(res));
  91 +       return pdev;
  92 +}
  93 +
  94 +int __init ath79_register_pci(void)
  95 +{
  96 +       struct platform_device *pdev = NULL;
  97 +
  98 +       if (soc_is_ar71xx()) {
  99 +               pdev = ath79_register_pci_ar71xx();
 100 +       } else if (soc_is_ar724x()) {
 101 +               pdev = ath79_register_pci_ar724x(-1,
 102 +                                                AR724X_PCI_CFG_BASE,
 103 +                                                AR724X_PCI_CTRL_BASE,
 104 +                                                ATH79_CPU_IRQ_IP2);
 105 +       } else if (soc_is_ar9342() ||
 106 +                  soc_is_ar9344()) {
 107                 u32 bootstrap;
 108
 109                 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
 110 -               if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
 111 -                       return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
 112 +               if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
 113 +                       return -ENODEV;
 114 +
 115 +               pdev = ath79_register_pci_ar724x(-1,
 116 +                                                AR724X_PCI_CFG_BASE,
 117 +                                                AR724X_PCI_CTRL_BASE,
 118 +                                                ATH79_IP2_IRQ(0));
 119 +       } else {
 120 +               /* No PCI support */
 121 +               return -ENODEV;
 122         }
 123
 124 -       return -ENODEV;
 125 +       if (!pdev)
 126 +               pr_err("unable to register PCI controller device\n");
 127 +
 128 +       return pdev ? 0 : -ENODEV;
 129  }