ar71xx: refresh patches
[openwrt.git] / target / linux / ar71xx / patches-3.18 / 609-MIPS-ath79-ap136-fixes.patch
1 --- a/arch/mips/ath79/mach-ap136.c
2 +++ b/arch/mips/ath79/mach-ap136.c
3 @@ -18,23 +18,29 @@
4   *
5   */
6  
7 -#include <linux/pci.h>
8 -#include <linux/ath9k_platform.h>
9 +#include <linux/platform_device.h>
10 +#include <linux/ar8216_platform.h>
11  
12 -#include "machtypes.h"
13 +#include <asm/mach-ath79/ar71xx_regs.h>
14 +
15 +#include "common.h"
16 +#include "pci.h"
17 +#include "dev-ap9x-pci.h"
18  #include "dev-gpio-buttons.h"
19 +#include "dev-eth.h"
20  #include "dev-leds-gpio.h"
21 -#include "dev-spi.h"
22 +#include "dev-m25p80.h"
23 +#include "dev-nfc.h"
24  #include "dev-usb.h"
25  #include "dev-wmac.h"
26 -#include "pci.h"
27 +#include "machtypes.h"
28  
29 -#define AP136_GPIO_LED_STATUS_RED      14
30 -#define AP136_GPIO_LED_STATUS_GREEN    19
31  #define AP136_GPIO_LED_USB             4
32 -#define AP136_GPIO_LED_WLAN_2G         13
33  #define AP136_GPIO_LED_WLAN_5G         12
34 +#define AP136_GPIO_LED_WLAN_2G         13
35 +#define AP136_GPIO_LED_STATUS_RED      14
36  #define AP136_GPIO_LED_WPS_RED         15
37 +#define AP136_GPIO_LED_STATUS_GREEN    19
38  #define AP136_GPIO_LED_WPS_GREEN       20
39  
40  #define AP136_GPIO_BTN_WPS             16
41 @@ -43,37 +49,39 @@
42  #define AP136_KEYS_POLL_INTERVAL       20      /* msecs */
43  #define AP136_KEYS_DEBOUNCE_INTERVAL   (3 * AP136_KEYS_POLL_INTERVAL)
44  
45 -#define AP136_WMAC_CALDATA_OFFSET 0x1000
46 -#define AP136_PCIE_CALDATA_OFFSET 0x5000
47 +#define AP136_MAC0_OFFSET              0
48 +#define AP136_MAC1_OFFSET              6
49 +#define AP136_WMAC_CALDATA_OFFSET      0x1000
50 +#define AP136_PCIE_CALDATA_OFFSET      0x5000
51  
52  static struct gpio_led ap136_leds_gpio[] __initdata = {
53         {
54 -               .name           = "qca:green:status",
55 +               .name           = "ap136:green:status",
56                 .gpio           = AP136_GPIO_LED_STATUS_GREEN,
57                 .active_low     = 1,
58         },
59         {
60 -               .name           = "qca:red:status",
61 +               .name           = "ap136:red:status",
62                 .gpio           = AP136_GPIO_LED_STATUS_RED,
63                 .active_low     = 1,
64         },
65         {
66 -               .name           = "qca:green:wps",
67 +               .name           = "ap136:green:wps",
68                 .gpio           = AP136_GPIO_LED_WPS_GREEN,
69                 .active_low     = 1,
70         },
71         {
72 -               .name           = "qca:red:wps",
73 +               .name           = "ap136:red:wps",
74                 .gpio           = AP136_GPIO_LED_WPS_RED,
75                 .active_low     = 1,
76         },
77         {
78 -               .name           = "qca:red:wlan-2g",
79 +               .name           = "ap136:red:wlan-2g",
80                 .gpio           = AP136_GPIO_LED_WLAN_2G,
81                 .active_low     = 1,
82         },
83         {
84 -               .name           = "qca:red:usb",
85 +               .name           = "ap136:red:usb",
86                 .gpio           = AP136_GPIO_LED_USB,
87                 .active_low     = 1,
88         }
89 @@ -98,65 +106,151 @@ static struct gpio_keys_button ap136_gpi
90         },
91  };
92  
93 -static struct ath79_spi_controller_data ap136_spi0_data = {
94 -       .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
95 -       .cs_line = 0,
96 +static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg;
97 +static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg;
98 +
99 +static struct ar8327_platform_data ap136_ar8327_data = {
100 +       .pad0_cfg = &ap136_ar8327_pad0_cfg,
101 +       .pad6_cfg = &ap136_ar8327_pad6_cfg,
102 +       .port0_cfg = {
103 +               .force_link = 1,
104 +               .speed = AR8327_PORT_SPEED_1000,
105 +               .duplex = 1,
106 +               .txpause = 1,
107 +               .rxpause = 1,
108 +       },
109 +       .port6_cfg = {
110 +               .force_link = 1,
111 +               .speed = AR8327_PORT_SPEED_1000,
112 +               .duplex = 1,
113 +               .txpause = 1,
114 +               .rxpause = 1,
115 +       },
116  };
117  
118 -static struct spi_board_info ap136_spi_info[] = {
119 +static struct mdio_board_info ap136_mdio0_info[] = {
120         {
121 -               .bus_num        = 0,
122 -               .chip_select    = 0,
123 -               .max_speed_hz   = 25000000,
124 -               .modalias       = "mx25l6405d",
125 -               .controller_data = &ap136_spi0_data,
126 -       }
127 +               .bus_id = "ag71xx-mdio.0",
128 +               .phy_addr = 0,
129 +               .platform_data = &ap136_ar8327_data,
130 +       },
131  };
132  
133 -static struct ath79_spi_platform_data ap136_spi_data = {
134 -       .bus_num        = 0,
135 -       .num_chipselect = 1,
136 -};
137 +static void __init ap136_common_setup(void)
138 +{
139 +       u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
140 +
141 +       ath79_register_m25p80(NULL);
142 +
143 +       ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
144 +                                ap136_leds_gpio);
145 +       ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
146 +                                       ARRAY_SIZE(ap136_gpio_keys),
147 +                                       ap136_gpio_keys);
148 +
149 +       ath79_register_usb();
150 +       ath79_register_nfc();
151 +
152 +       ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
153 +
154 +       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
155  
156 -#ifdef CONFIG_PCI
157 -static struct ath9k_platform_data ap136_ath9k_data;
158 +       ath79_register_mdio(0, 0x0);
159 +       ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
160  
161 -static int ap136_pci_plat_dev_init(struct pci_dev *dev)
162 +       mdiobus_register_board_info(ap136_mdio0_info,
163 +                                   ARRAY_SIZE(ap136_mdio0_info));
164 +
165 +       /* GMAC0 is connected to the RMGII interface */
166 +       ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
167 +       ath79_eth0_data.phy_mask = BIT(0);
168 +       ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
169 +
170 +       ath79_register_eth(0);
171 +
172 +       /* GMAC1 is connected tot eh SGMII interface */
173 +       ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
174 +       ath79_eth1_data.speed = SPEED_1000;
175 +       ath79_eth1_data.duplex = DUPLEX_FULL;
176 +
177 +       ath79_register_eth(1);
178 +}
179 +
180 +static void __init ap136_010_setup(void)
181  {
182 -       if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
183 -               dev->dev.platform_data = &ap136_ath9k_data;
184 +       u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
185  
186 -       return 0;
187 +       /* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */
188 +       ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
189 +       ap136_ar8327_pad0_cfg.txclk_delay_en = true;
190 +       ap136_ar8327_pad0_cfg.rxclk_delay_en = true;
191 +       ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
192 +       ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
193 +
194 +       /* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */
195 +       ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
196 +       ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
197 +       ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
198 +
199 +       ath79_eth0_pll_data.pll_1000 = 0xa6000000;
200 +       ath79_eth1_pll_data.pll_1000 = 0x03000101;
201 +
202 +       ap136_common_setup();
203 +       ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
204  }
205  
206 -static void __init ap136_pci_init(u8 *eeprom)
207 +MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
208 +            "Atheros AP136-010 reference board",
209 +            ap136_010_setup);
210 +
211 +static void __init ap136_020_common_setup(void)
212  {
213 -       memcpy(ap136_ath9k_data.eeprom_data, eeprom,
214 -              sizeof(ap136_ath9k_data.eeprom_data));
215 +       /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
216 +       ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
217 +       ap136_ar8327_pad0_cfg.sgmii_delay_en = true;
218 +
219 +       /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */
220 +       ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII;
221 +       ap136_ar8327_pad6_cfg.txclk_delay_en = true;
222 +       ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
223 +       ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
224 +       ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
225  
226 -       ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
227 -       ath79_register_pci();
228 +       ath79_eth0_pll_data.pll_1000 = 0x56000000;
229 +       ath79_eth1_pll_data.pll_1000 = 0x03000101;
230 +
231 +       ap136_common_setup();
232  }
233 -#else
234 -static inline void ap136_pci_init(u8 *eeprom) {}
235 -#endif /* CONFIG_PCI */
236  
237 -static void __init ap136_setup(void)
238 +static void __init ap136_020_setup(void)
239  {
240         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
241  
242 -       ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
243 -                                ap136_leds_gpio);
244 -       ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
245 -                                       ARRAY_SIZE(ap136_gpio_keys),
246 -                                       ap136_gpio_keys);
247 -       ath79_register_spi(&ap136_spi_data, ap136_spi_info,
248 -                          ARRAY_SIZE(ap136_spi_info));
249 -       ath79_register_usb();
250 -       ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
251 -       ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
252 +       ap136_020_common_setup();
253 +       ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
254  }
255  
256 -MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
257 -            "Atheros AP136-010 reference board",
258 -            ap136_setup);
259 +MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020",
260 +            "Atheros AP136-020 reference board",
261 +            ap136_020_setup);
262 +
263 +/*
264 + * AP135-020 is similar to AP136-020, any future AP135 specific init
265 + * code can be added here.
266 + */
267 +static void __init ap135_020_setup(void)
268 +{
269 +       ap136_leds_gpio[0].name = "ap135:green:status";
270 +       ap136_leds_gpio[1].name = "ap135:red:status";
271 +       ap136_leds_gpio[2].name = "ap135:green:wps";
272 +       ap136_leds_gpio[3].name = "ap135:red:wps";
273 +       ap136_leds_gpio[4].name = "ap135:red:wlan-2g";
274 +       ap136_leds_gpio[5].name = "ap135:red:usb";
275 +
276 +       ap136_020_common_setup();
277 +       ath79_register_pci();
278 +}
279 +
280 +MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020",
281 +            "Atheros AP135-020 reference board",
282 +            ap135_020_setup);
283 --- a/arch/mips/ath79/machtypes.h
284 +++ b/arch/mips/ath79/machtypes.h
285 @@ -18,7 +18,9 @@ enum ath79_mach_type {
286         ATH79_MACH_GENERIC = 0,
287         ATH79_MACH_AP121,               /* Atheros AP121 reference board */
288         ATH79_MACH_AP121_MINI,          /* Atheros AP121-MINI reference board */
289 +       ATH79_MACH_AP135_020,           /* Atheros AP135-020 reference board */
290         ATH79_MACH_AP136_010,           /* Atheros AP136-010 reference board */
291 +       ATH79_MACH_AP136_020,           /* Atheros AP136-020 reference board */
292         ATH79_MACH_AP81,                /* Atheros AP81 reference board */
293         ATH79_MACH_DB120,               /* Atheros DB120 reference board */
294         ATH79_MACH_PB44,                /* Atheros PB44 reference board */
295 --- a/arch/mips/ath79/Kconfig
296 +++ b/arch/mips/ath79/Kconfig
297 @@ -16,16 +16,17 @@ config ATH79_MACH_AP121
298           Atheros AP121 reference board.
299  
300  config ATH79_MACH_AP136
301 -       bool "Atheros AP136 reference board"
302 +       bool "Atheros AP136/AP135 reference board"
303         select SOC_QCA955X
304         select ATH79_DEV_GPIO_BUTTONS
305         select ATH79_DEV_LEDS_GPIO
306 +       select ATH79_DEV_NFC
307         select ATH79_DEV_SPI
308         select ATH79_DEV_USB
309         select ATH79_DEV_WMAC
310         help
311           Say 'Y' here if you want your kernel to support the
312 -         Atheros AP136 reference board.
313 +         Atheros AP136 or AP135 reference boards.
314  
315  config ATH79_MACH_AP81
316         bool "Atheros AP81 reference board"