target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include "ag71xx.h"
  15
  16 #define AG71XX_DEFAULT_MSG_ENABLE       \
  17         (NETIF_MSG_DRV                  \
  18         | NETIF_MSG_PROBE               \
  19         | NETIF_MSG_LINK                \
  20         | NETIF_MSG_TIMER               \
  21         | NETIF_MSG_IFDOWN              \
  22         | NETIF_MSG_IFUP                \
  23         | NETIF_MSG_RX_ERR              \
  24         | NETIF_MSG_TX_ERR)
  25
  26 static int ag71xx_msg_level = -1;
  27
  28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
  29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
  30
  31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
  32 {
  33         DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
  34                 ag->dev->name,
  35                 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
  36                 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
  37                 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
  38
  39         DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
  40                 ag->dev->name,
  41                 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
  42                 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
  43                 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
  44 }
  45
  46 static void ag71xx_dump_regs(struct ag71xx *ag)
  47 {
  48         DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
  49                 ag->dev->name,
  50                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
  51                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
  52                 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
  53                 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
  54                 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
  55         DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
  56                 ag->dev->name,
  57                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
  58                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
  59                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
  60         DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
  61                 ag->dev->name,
  62                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
  63                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
  64                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
  65         DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
  66                 ag->dev->name,
  67                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
  68                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
  69                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
  70 }
  71
  72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
  73 {
  74         DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
  75                 ag->dev->name, label, intr,
  76                 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
  77                 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
  78                 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
  79                 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
  80                 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
  81                 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
  82 }
  83
  84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
  85 {
  86         kfree(ring->buf);
  87
  88         if (ring->descs_cpu)
  89                 dma_free_coherent(NULL, ring->size * ring->desc_size,
  90                                   ring->descs_cpu, ring->descs_dma);
  91 }
  92
  93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
  94 {
  95         int err;
  96         int i;
  97
  98         ring->desc_size = sizeof(struct ag71xx_desc);
  99         if (ring->desc_size % cache_line_size()) {
 100                 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
 101                         ring, ring->desc_size,
 102                         roundup(ring->desc_size, cache_line_size()));
 103                 ring->desc_size = roundup(ring->desc_size, cache_line_size());
 104         }
 105
 106         ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
 107                                              &ring->descs_dma, GFP_ATOMIC);
 108         if (!ring->descs_cpu) {
 109                 err = -ENOMEM;
 110                 goto err;
 111         }
 112
 113
 114         ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
 115         if (!ring->buf) {
 116                 err = -ENOMEM;
 117                 goto err;
 118         }
 119
 120         for (i = 0; i < ring->size; i++) {
 121                 int idx = i * ring->desc_size;
 122                 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
 123                 DBG("ag71xx: ring %p, desc %d at %p\n",
 124                         ring, i, ring->buf[i].desc);
 125         }
 126
 127         return 0;
 128
 129 err:
 130         return err;
 131 }
 132
 133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
 134 {
 135         struct ag71xx_ring *ring = &ag->tx_ring;
 136         struct net_device *dev = ag->dev;
 137         u32 bytes_compl = 0, pkts_compl = 0;
 138
 139         while (ring->curr != ring->dirty) {
 140                 u32 i = ring->dirty % ring->size;
 141
 142                 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
 143                         ring->buf[i].desc->ctrl = 0;
 144                         dev->stats.tx_errors++;
 145                 }
 146
 147                 if (ring->buf[i].skb) {
 148                         bytes_compl += ring->buf[i].len;
 149                         pkts_compl++;
 150                         dev_kfree_skb_any(ring->buf[i].skb);
 151                 }
 152                 ring->buf[i].skb = NULL;
 153                 ring->dirty++;
 154         }
 155
 156         /* flush descriptors */
 157         wmb();
 158
 159         netdev_completed_queue(dev, pkts_compl, bytes_compl);
 160 }
 161
 162 static void ag71xx_ring_tx_init(struct ag71xx *ag)
 163 {
 164         struct ag71xx_ring *ring = &ag->tx_ring;
 165         int i;
 166
 167         for (i = 0; i < ring->size; i++) {
 168                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
 169                         ring->desc_size * ((i + 1) % ring->size));
 170
 171                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 172                 ring->buf[i].skb = NULL;
 173         }
 174
 175         /* flush descriptors */
 176         wmb();
 177
 178         ring->curr = 0;
 179         ring->dirty = 0;
 180         netdev_reset_queue(ag->dev);
 181 }
 182
 183 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
 184 {
 185         struct ag71xx_ring *ring = &ag->rx_ring;
 186         int i;
 187
 188         if (!ring->buf)
 189                 return;
 190
 191         for (i = 0; i < ring->size; i++)
 192                 if (ring->buf[i].rx_buf) {
 193                         dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
 194                                          ag->rx_buf_size, DMA_FROM_DEVICE);
 195                         kfree(ring->buf[i].rx_buf);
 196                 }
 197 }
 198
 199 static int ag71xx_buffer_offset(struct ag71xx *ag)
 200 {
 201         int offset = NET_SKB_PAD;
 202
 203         /*
 204          * On AR71xx/AR91xx packets must be 4-byte aligned.
 205          *
 206          * When using builtin AR8216 support, hardware adds a 2-byte header,
 207          * so we don't need any extra alignment in that case.
 208          */
 209         if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
 210                 return offset;
 211
 212         return offset + NET_IP_ALIGN;
 213 }
 214
 215 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
 216                                int offset)
 217 {
 218         void *data;
 219
 220         data = kmalloc(ag->rx_buf_size +
 221                        SKB_DATA_ALIGN(sizeof(struct skb_shared_info)),
 222                        GFP_ATOMIC);
 223         if (!data)
 224                 return false;
 225
 226         buf->rx_buf = data;
 227         buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
 228                                        DMA_FROM_DEVICE);
 229         buf->desc->data = (u32) buf->dma_addr + offset;
 230         return true;
 231 }
 232
 233 static int ag71xx_ring_rx_init(struct ag71xx *ag)
 234 {
 235         struct ag71xx_ring *ring = &ag->rx_ring;
 236         unsigned int i;
 237         int ret;
 238         int offset = ag71xx_buffer_offset(ag);
 239
 240         ret = 0;
 241         for (i = 0; i < ring->size; i++) {
 242                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
 243                         ring->desc_size * ((i + 1) % ring->size));
 244
 245                 DBG("ag71xx: RX desc at %p, next is %08x\n",
 246                         ring->buf[i].desc,
 247                         ring->buf[i].desc->next);
 248         }
 249
 250         for (i = 0; i < ring->size; i++) {
 251                 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset)) {
 252                         ret = -ENOMEM;
 253                         break;
 254                 }
 255
 256                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 257         }
 258
 259         /* flush descriptors */
 260         wmb();
 261
 262         ring->curr = 0;
 263         ring->dirty = 0;
 264
 265         return ret;
 266 }
 267
 268 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
 269 {
 270         struct ag71xx_ring *ring = &ag->rx_ring;
 271         unsigned int count;
 272         int offset = ag71xx_buffer_offset(ag);
 273
 274         count = 0;
 275         for (; ring->curr - ring->dirty > 0; ring->dirty++) {
 276                 unsigned int i;
 277
 278                 i = ring->dirty % ring->size;
 279
 280                 if (!ring->buf[i].rx_buf &&
 281                     !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset))
 282                         break;
 283
 284                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 285                 count++;
 286         }
 287
 288         /* flush descriptors */
 289         wmb();
 290
 291         DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
 292
 293         return count;
 294 }
 295
 296 static int ag71xx_rings_init(struct ag71xx *ag)
 297 {
 298         int ret;
 299
 300         ret = ag71xx_ring_alloc(&ag->tx_ring);
 301         if (ret)
 302                 return ret;
 303
 304         ag71xx_ring_tx_init(ag);
 305
 306         ret = ag71xx_ring_alloc(&ag->rx_ring);
 307         if (ret)
 308                 return ret;
 309
 310         ret = ag71xx_ring_rx_init(ag);
 311         return ret;
 312 }
 313
 314 static void ag71xx_rings_cleanup(struct ag71xx *ag)
 315 {
 316         ag71xx_ring_rx_clean(ag);
 317         ag71xx_ring_free(&ag->rx_ring);
 318
 319         ag71xx_ring_tx_clean(ag);
 320         netdev_reset_queue(ag->dev);
 321         ag71xx_ring_free(&ag->tx_ring);
 322 }
 323
 324 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
 325 {
 326         switch (ag->speed) {
 327         case SPEED_1000:
 328                 return "1000";
 329         case SPEED_100:
 330                 return "100";
 331         case SPEED_10:
 332                 return "10";
 333         }
 334
 335         return "?";
 336 }
 337
 338 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
 339 {
 340         u32 t;
 341
 342         t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
 343           | (((u32) mac[3]) << 8) | ((u32) mac[2]);
 344
 345         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
 346
 347         t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
 348         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
 349 }
 350
 351 static void ag71xx_dma_reset(struct ag71xx *ag)
 352 {
 353         u32 val;
 354         int i;
 355
 356         ag71xx_dump_dma_regs(ag);
 357
 358         /* stop RX and TX */
 359         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
 360         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
 361
 362         /*
 363          * give the hardware some time to really stop all rx/tx activity
 364          * clearing the descriptors too early causes random memory corruption
 365          */
 366         mdelay(1);
 367
 368         /* clear descriptor addresses */
 369         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
 370         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
 371
 372         /* clear pending RX/TX interrupts */
 373         for (i = 0; i < 256; i++) {
 374                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 375                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 376         }
 377
 378         /* clear pending errors */
 379         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
 380         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
 381
 382         val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 383         if (val)
 384                 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
 385                          ag->dev->name, val);
 386
 387         val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 388
 389         /* mask out reserved bits */
 390         val &= ~0xff000000;
 391
 392         if (val)
 393                 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
 394                          ag->dev->name, val);
 395
 396         ag71xx_dump_dma_regs(ag);
 397 }
 398
 399 #define MAC_CFG1_INIT   (MAC_CFG1_RXE | MAC_CFG1_TXE | \
 400                          MAC_CFG1_SRX | MAC_CFG1_STX)
 401
 402 #define FIFO_CFG0_INIT  (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
 403
 404 #define FIFO_CFG4_INIT  (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
 405                          FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
 406                          FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
 407                          FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
 408                          FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
 409                          FIFO_CFG4_VT)
 410
 411 #define FIFO_CFG5_INIT  (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
 412                          FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
 413                          FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
 414                          FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
 415                          FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
 416                          FIFO_CFG5_17 | FIFO_CFG5_SF)
 417
 418 static void ag71xx_hw_stop(struct ag71xx *ag)
 419 {
 420         /* disable all interrupts and stop the rx/tx engine */
 421         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
 422         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
 423         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
 424 }
 425
 426 static void ag71xx_hw_setup(struct ag71xx *ag)
 427 {
 428         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 429
 430         /* setup MAC configuration registers */
 431         ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
 432
 433         ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
 434                   MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
 435
 436         /* setup max frame length */
 437         ag71xx_wr(ag, AG71XX_REG_MAC_MFL, ag->max_frame_len);
 438
 439         /* setup FIFO configuration registers */
 440         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
 441         if (pdata->is_ar724x) {
 442                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
 443                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
 444         } else {
 445                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
 446                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
 447         }
 448         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
 449         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
 450 }
 451
 452 static void ag71xx_hw_init(struct ag71xx *ag)
 453 {
 454         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 455         u32 reset_mask = pdata->reset_bit;
 456
 457         ag71xx_hw_stop(ag);
 458
 459         if (pdata->is_ar724x) {
 460                 u32 reset_phy = reset_mask;
 461
 462                 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
 463                 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
 464
 465                 ath79_device_reset_set(reset_phy);
 466                 mdelay(50);
 467                 ath79_device_reset_clear(reset_phy);
 468                 mdelay(200);
 469         }
 470
 471         ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
 472         udelay(20);
 473
 474         ath79_device_reset_set(reset_mask);
 475         mdelay(100);
 476         ath79_device_reset_clear(reset_mask);
 477         mdelay(200);
 478
 479         ag71xx_hw_setup(ag);
 480
 481         ag71xx_dma_reset(ag);
 482 }
 483
 484 static void ag71xx_fast_reset(struct ag71xx *ag)
 485 {
 486         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 487         struct net_device *dev = ag->dev;
 488         u32 reset_mask = pdata->reset_bit;
 489         u32 rx_ds, tx_ds;
 490         u32 mii_reg;
 491
 492         reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
 493
 494         mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
 495         rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
 496         tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
 497
 498         ath79_device_reset_set(reset_mask);
 499         udelay(10);
 500         ath79_device_reset_clear(reset_mask);
 501         udelay(10);
 502
 503         ag71xx_dma_reset(ag);
 504         ag71xx_hw_setup(ag);
 505
 506         ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
 507         ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
 508         ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
 509
 510         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
 511 }
 512
 513 static void ag71xx_hw_start(struct ag71xx *ag)
 514 {
 515         /* start RX engine */
 516         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 517
 518         /* enable interrupts */
 519         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
 520 }
 521
 522 void ag71xx_link_adjust(struct ag71xx *ag)
 523 {
 524         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 525         u32 cfg2;
 526         u32 ifctl;
 527         u32 fifo5;
 528
 529         if (!ag->link) {
 530                 ag71xx_hw_stop(ag);
 531                 netif_carrier_off(ag->dev);
 532                 if (netif_msg_link(ag))
 533                         pr_info("%s: link down\n", ag->dev->name);
 534                 return;
 535         }
 536
 537         if (pdata->is_ar724x)
 538                 ag71xx_fast_reset(ag);
 539
 540         cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
 541         cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
 542         cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
 543
 544         ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
 545         ifctl &= ~(MAC_IFCTL_SPEED);
 546
 547         fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
 548         fifo5 &= ~FIFO_CFG5_BM;
 549
 550         switch (ag->speed) {
 551         case SPEED_1000:
 552                 cfg2 |= MAC_CFG2_IF_1000;
 553                 fifo5 |= FIFO_CFG5_BM;
 554                 break;
 555         case SPEED_100:
 556                 cfg2 |= MAC_CFG2_IF_10_100;
 557                 ifctl |= MAC_IFCTL_SPEED;
 558                 break;
 559         case SPEED_10:
 560                 cfg2 |= MAC_CFG2_IF_10_100;
 561                 break;
 562         default:
 563                 BUG();
 564                 return;
 565         }
 566
 567         if (pdata->is_ar91xx)
 568                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
 569         else if (pdata->is_ar724x)
 570                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
 571         else
 572                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
 573
 574         if (pdata->set_speed)
 575                 pdata->set_speed(ag->speed);
 576
 577         ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
 578         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
 579         ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
 580         ag71xx_hw_start(ag);
 581
 582         netif_carrier_on(ag->dev);
 583         if (netif_msg_link(ag))
 584                 pr_info("%s: link up (%sMbps/%s duplex)\n",
 585                         ag->dev->name,
 586                         ag71xx_speed_str(ag),
 587                         (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
 588
 589         DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
 590                 ag->dev->name,
 591                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
 592                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
 593                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
 594
 595         DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
 596                 ag->dev->name,
 597                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
 598                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
 599                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
 600
 601         DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
 602                 ag->dev->name,
 603                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
 604                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
 605 }
 606
 607 static int ag71xx_open(struct net_device *dev)
 608 {
 609         struct ag71xx *ag = netdev_priv(dev);
 610         int ret;
 611
 612         ag->rx_buf_size = AG71XX_RX_PKT_SIZE + NET_SKB_PAD + NET_IP_ALIGN;
 613
 614         ret = ag71xx_rings_init(ag);
 615         if (ret)
 616                 goto err;
 617
 618         napi_enable(&ag->napi);
 619
 620         netif_carrier_off(dev);
 621         ag71xx_phy_start(ag);
 622
 623         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
 624         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
 625
 626         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
 627
 628         netif_start_queue(dev);
 629
 630         return 0;
 631
 632 err:
 633         ag71xx_rings_cleanup(ag);
 634         return ret;
 635 }
 636
 637 static int ag71xx_stop(struct net_device *dev)
 638 {
 639         struct ag71xx *ag = netdev_priv(dev);
 640         unsigned long flags;
 641
 642         netif_carrier_off(dev);
 643         ag71xx_phy_stop(ag);
 644
 645         spin_lock_irqsave(&ag->lock, flags);
 646
 647         netif_stop_queue(dev);
 648
 649         ag71xx_hw_stop(ag);
 650         ag71xx_dma_reset(ag);
 651
 652         napi_disable(&ag->napi);
 653         del_timer_sync(&ag->oom_timer);
 654
 655         spin_unlock_irqrestore(&ag->lock, flags);
 656
 657         ag71xx_rings_cleanup(ag);
 658
 659         return 0;
 660 }
 661
 662 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
 663                                           struct net_device *dev)
 664 {
 665         struct ag71xx *ag = netdev_priv(dev);
 666         struct ag71xx_ring *ring = &ag->tx_ring;
 667         struct ag71xx_desc *desc;
 668         dma_addr_t dma_addr;
 669         int i;
 670
 671         i = ring->curr % ring->size;
 672         desc = ring->buf[i].desc;
 673
 674         if (!ag71xx_desc_empty(desc))
 675                 goto err_drop;
 676
 677         if (ag71xx_has_ar8216(ag))
 678                 ag71xx_add_ar8216_header(ag, skb);
 679
 680         if (skb->len <= 0) {
 681                 DBG("%s: packet len is too small\n", ag->dev->name);
 682                 goto err_drop;
 683         }
 684
 685         dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
 686                                   DMA_TO_DEVICE);
 687
 688         netdev_sent_queue(dev, skb->len);
 689         ring->buf[i].len = skb->len;
 690         ring->buf[i].skb = skb;
 691         ring->buf[i].timestamp = jiffies;
 692
 693         /* setup descriptor fields */
 694         desc->data = (u32) dma_addr;
 695         desc->ctrl = (skb->len & DESC_PKTLEN_M);
 696
 697         /* flush descriptor */
 698         wmb();
 699
 700         ring->curr++;
 701         if (ring->curr == (ring->dirty + ring->size)) {
 702                 DBG("%s: tx queue full\n", ag->dev->name);
 703                 netif_stop_queue(dev);
 704         }
 705
 706         DBG("%s: packet injected into TX queue\n", ag->dev->name);
 707
 708         /* enable TX engine */
 709         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
 710
 711         return NETDEV_TX_OK;
 712
 713 err_drop:
 714         dev->stats.tx_dropped++;
 715
 716         dev_kfree_skb(skb);
 717         return NETDEV_TX_OK;
 718 }
 719
 720 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 721 {
 722         struct ag71xx *ag = netdev_priv(dev);
 723         int ret;
 724
 725         switch (cmd) {
 726         case SIOCETHTOOL:
 727                 if (ag->phy_dev == NULL)
 728                         break;
 729
 730                 spin_lock_irq(&ag->lock);
 731                 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
 732                 spin_unlock_irq(&ag->lock);
 733                 return ret;
 734
 735         case SIOCSIFHWADDR:
 736                 if (copy_from_user
 737                         (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
 738                         return -EFAULT;
 739                 return 0;
 740
 741         case SIOCGIFHWADDR:
 742                 if (copy_to_user
 743                         (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
 744                         return -EFAULT;
 745                 return 0;
 746
 747         case SIOCGMIIPHY:
 748         case SIOCGMIIREG:
 749         case SIOCSMIIREG:
 750                 if (ag->phy_dev == NULL)
 751                         break;
 752
 753                 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
 754
 755         default:
 756                 break;
 757         }
 758
 759         return -EOPNOTSUPP;
 760 }
 761
 762 static void ag71xx_oom_timer_handler(unsigned long data)
 763 {
 764         struct net_device *dev = (struct net_device *) data;
 765         struct ag71xx *ag = netdev_priv(dev);
 766
 767         napi_schedule(&ag->napi);
 768 }
 769
 770 static void ag71xx_tx_timeout(struct net_device *dev)
 771 {
 772         struct ag71xx *ag = netdev_priv(dev);
 773
 774         if (netif_msg_tx_err(ag))
 775                 pr_info("%s: tx timeout\n", ag->dev->name);
 776
 777         schedule_work(&ag->restart_work);
 778 }
 779
 780 static void ag71xx_restart_work_func(struct work_struct *work)
 781 {
 782         struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
 783
 784         if (ag71xx_get_pdata(ag)->is_ar724x) {
 785                 ag->link = 0;
 786                 ag71xx_link_adjust(ag);
 787                 return;
 788         }
 789
 790         ag71xx_stop(ag->dev);
 791         ag71xx_open(ag->dev);
 792 }
 793
 794 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
 795 {
 796         u32 rx_sm, tx_sm, rx_fd;
 797
 798         if (likely(time_before(jiffies, timestamp + HZ/10)))
 799                 return false;
 800
 801         if (!netif_carrier_ok(ag->dev))
 802                 return false;
 803
 804         rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
 805         if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
 806                 return true;
 807
 808         tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
 809         rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
 810         if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
 811             ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
 812                 return true;
 813
 814         return false;
 815 }
 816
 817 static int ag71xx_tx_packets(struct ag71xx *ag)
 818 {
 819         struct ag71xx_ring *ring = &ag->tx_ring;
 820         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 821         int sent = 0;
 822         int bytes_compl = 0;
 823
 824         DBG("%s: processing TX ring\n", ag->dev->name);
 825
 826         while (ring->dirty != ring->curr) {
 827                 unsigned int i = ring->dirty % ring->size;
 828                 struct ag71xx_desc *desc = ring->buf[i].desc;
 829                 struct sk_buff *skb = ring->buf[i].skb;
 830                 int len = ring->buf[i].len;
 831
 832                 if (!ag71xx_desc_empty(desc)) {
 833                         if (pdata->is_ar7240 &&
 834                             ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
 835                                 schedule_work(&ag->restart_work);
 836                         break;
 837                 }
 838
 839                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 840
 841                 bytes_compl += len;
 842                 ag->dev->stats.tx_bytes += len;
 843                 ag->dev->stats.tx_packets++;
 844
 845                 dev_kfree_skb_any(skb);
 846                 ring->buf[i].skb = NULL;
 847
 848                 ring->dirty++;
 849                 sent++;
 850         }
 851
 852         DBG("%s: %d packets sent out\n", ag->dev->name, sent);
 853
 854         if (!sent)
 855                 return 0;
 856
 857         netdev_completed_queue(ag->dev, sent, bytes_compl);
 858         if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
 859                 netif_wake_queue(ag->dev);
 860
 861         return sent;
 862 }
 863
 864 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
 865 {
 866         struct net_device *dev = ag->dev;
 867         struct ag71xx_ring *ring = &ag->rx_ring;
 868         int offset = ag71xx_buffer_offset(ag);
 869         int done = 0;
 870
 871         DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
 872                         dev->name, limit, ring->curr, ring->dirty);
 873
 874         while (done < limit) {
 875                 unsigned int i = ring->curr % ring->size;
 876                 struct ag71xx_desc *desc = ring->buf[i].desc;
 877                 struct sk_buff *skb;
 878                 int pktlen;
 879                 int err = 0;
 880
 881                 if (ag71xx_desc_empty(desc))
 882                         break;
 883
 884                 if ((ring->dirty + ring->size) == ring->curr) {
 885                         ag71xx_assert(0);
 886                         break;
 887                 }
 888
 889                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 890
 891                 pktlen = ag71xx_desc_pktlen(desc);
 892                 pktlen -= ETH_FCS_LEN;
 893
 894                 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
 895                                  ag->rx_buf_size, DMA_FROM_DEVICE);
 896
 897                 dev->stats.rx_packets++;
 898                 dev->stats.rx_bytes += pktlen;
 899
 900                 skb = build_skb(ring->buf[i].rx_buf, 0);
 901                 if (!skb) {
 902                         kfree(ring->buf[i].rx_buf);
 903                         goto next;
 904                 }
 905
 906                 skb_reserve(skb, offset);
 907                 skb_put(skb, pktlen);
 908
 909                 if (ag71xx_has_ar8216(ag))
 910                         err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
 911
 912                 if (err) {
 913                         dev->stats.rx_dropped++;
 914                         kfree_skb(skb);
 915                 } else {
 916                         skb->dev = dev;
 917                         skb->ip_summed = CHECKSUM_NONE;
 918                         skb->protocol = eth_type_trans(skb, dev);
 919                         netif_receive_skb(skb);
 920                 }
 921
 922 next:
 923                 ring->buf[i].rx_buf = NULL;
 924                 done++;
 925
 926                 ring->curr++;
 927         }
 928
 929         ag71xx_ring_rx_refill(ag);
 930
 931         DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
 932                 dev->name, ring->curr, ring->dirty, done);
 933
 934         return done;
 935 }
 936
 937 static int ag71xx_poll(struct napi_struct *napi, int limit)
 938 {
 939         struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
 940         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 941         struct net_device *dev = ag->dev;
 942         struct ag71xx_ring *rx_ring;
 943         unsigned long flags;
 944         u32 status;
 945         int tx_done;
 946         int rx_done;
 947
 948         pdata->ddr_flush();
 949         tx_done = ag71xx_tx_packets(ag);
 950
 951         DBG("%s: processing RX ring\n", dev->name);
 952         rx_done = ag71xx_rx_packets(ag, limit);
 953
 954         ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
 955
 956         rx_ring = &ag->rx_ring;
 957         if (rx_ring->buf[rx_ring->dirty % rx_ring->size].rx_buf == NULL)
 958                 goto oom;
 959
 960         status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 961         if (unlikely(status & RX_STATUS_OF)) {
 962                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
 963                 dev->stats.rx_fifo_errors++;
 964
 965                 /* restart RX */
 966                 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 967         }
 968
 969         if (rx_done < limit) {
 970                 if (status & RX_STATUS_PR)
 971                         goto more;
 972
 973                 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 974                 if (status & TX_STATUS_PS)
 975                         goto more;
 976
 977                 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
 978                         dev->name, rx_done, tx_done, limit);
 979
 980                 napi_complete(napi);
 981
 982                 /* enable interrupts */
 983                 spin_lock_irqsave(&ag->lock, flags);
 984                 ag71xx_int_enable(ag, AG71XX_INT_POLL);
 985                 spin_unlock_irqrestore(&ag->lock, flags);
 986                 return rx_done;
 987         }
 988
 989 more:
 990         DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
 991                         dev->name, rx_done, tx_done, limit);
 992         return rx_done;
 993
 994 oom:
 995         if (netif_msg_rx_err(ag))
 996                 pr_info("%s: out of memory\n", dev->name);
 997
 998         mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
 999         napi_complete(napi);
1000         return 0;
1001 }
1002
1003 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1004 {
1005         struct net_device *dev = dev_id;
1006         struct ag71xx *ag = netdev_priv(dev);
1007         u32 status;
1008
1009         status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1010         ag71xx_dump_intr(ag, "raw", status);
1011
1012         if (unlikely(!status))
1013                 return IRQ_NONE;
1014
1015         if (unlikely(status & AG71XX_INT_ERR)) {
1016                 if (status & AG71XX_INT_TX_BE) {
1017                         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1018                         dev_err(&dev->dev, "TX BUS error\n");
1019                 }
1020                 if (status & AG71XX_INT_RX_BE) {
1021                         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1022                         dev_err(&dev->dev, "RX BUS error\n");
1023                 }
1024         }
1025
1026         if (likely(status & AG71XX_INT_POLL)) {
1027                 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1028                 DBG("%s: enable polling mode\n", dev->name);
1029                 napi_schedule(&ag->napi);
1030         }
1031
1032         ag71xx_debugfs_update_int_stats(ag, status);
1033
1034         return IRQ_HANDLED;
1035 }
1036
1037 #ifdef CONFIG_NET_POLL_CONTROLLER
1038 /*
1039  * Polling 'interrupt' - used by things like netconsole to send skbs
1040  * without having to re-enable interrupts. It's not called while
1041  * the interrupt routine is executing.
1042  */
1043 static void ag71xx_netpoll(struct net_device *dev)
1044 {
1045         disable_irq(dev->irq);
1046         ag71xx_interrupt(dev->irq, dev);
1047         enable_irq(dev->irq);
1048 }
1049 #endif
1050
1051 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1052 {
1053         struct ag71xx *ag = netdev_priv(dev);
1054
1055         if (new_mtu < 68 ||
1056             new_mtu > ag->max_frame_len - ETH_HLEN - ETH_FCS_LEN)
1057                 return -EINVAL;
1058
1059         dev->mtu = new_mtu;
1060         return 0;
1061 }
1062
1063 static const struct net_device_ops ag71xx_netdev_ops = {
1064         .ndo_open               = ag71xx_open,
1065         .ndo_stop               = ag71xx_stop,
1066         .ndo_start_xmit         = ag71xx_hard_start_xmit,
1067         .ndo_do_ioctl           = ag71xx_do_ioctl,
1068         .ndo_tx_timeout         = ag71xx_tx_timeout,
1069         .ndo_change_mtu         = ag71xx_change_mtu,
1070         .ndo_set_mac_address    = eth_mac_addr,
1071         .ndo_validate_addr      = eth_validate_addr,
1072 #ifdef CONFIG_NET_POLL_CONTROLLER
1073         .ndo_poll_controller    = ag71xx_netpoll,
1074 #endif
1075 };
1076
1077 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1078 {
1079         switch (mode) {
1080         case PHY_INTERFACE_MODE_MII:
1081                 return "MII";
1082         case PHY_INTERFACE_MODE_GMII:
1083                 return "GMII";
1084         case PHY_INTERFACE_MODE_RMII:
1085                 return "RMII";
1086         case PHY_INTERFACE_MODE_RGMII:
1087                 return "RGMII";
1088         case PHY_INTERFACE_MODE_SGMII:
1089                 return "SGMII";
1090         default:
1091                 break;
1092         }
1093
1094         return "unknown";
1095 }
1096
1097
1098 static int ag71xx_probe(struct platform_device *pdev)
1099 {
1100         struct net_device *dev;
1101         struct resource *res;
1102         struct ag71xx *ag;
1103         struct ag71xx_platform_data *pdata;
1104         int err;
1105
1106         pdata = pdev->dev.platform_data;
1107         if (!pdata) {
1108                 dev_err(&pdev->dev, "no platform data specified\n");
1109                 err = -ENXIO;
1110                 goto err_out;
1111         }
1112
1113         if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
1114                 dev_err(&pdev->dev, "no MII bus device specified\n");
1115                 err = -EINVAL;
1116                 goto err_out;
1117         }
1118
1119         dev = alloc_etherdev(sizeof(*ag));
1120         if (!dev) {
1121                 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1122                 err = -ENOMEM;
1123                 goto err_out;
1124         }
1125
1126         SET_NETDEV_DEV(dev, &pdev->dev);
1127
1128         ag = netdev_priv(dev);
1129         ag->pdev = pdev;
1130         ag->dev = dev;
1131         ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1132                                         AG71XX_DEFAULT_MSG_ENABLE);
1133         spin_lock_init(&ag->lock);
1134
1135         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1136         if (!res) {
1137                 dev_err(&pdev->dev, "no mac_base resource found\n");
1138                 err = -ENXIO;
1139                 goto err_out;
1140         }
1141
1142         ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1143         if (!ag->mac_base) {
1144                 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1145                 err = -ENOMEM;
1146                 goto err_free_dev;
1147         }
1148
1149         dev->irq = platform_get_irq(pdev, 0);
1150         err = request_irq(dev->irq, ag71xx_interrupt,
1151                           IRQF_DISABLED,
1152                           dev->name, dev);
1153         if (err) {
1154                 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1155                 goto err_unmap_base;
1156         }
1157
1158         dev->base_addr = (unsigned long)ag->mac_base;
1159         dev->netdev_ops = &ag71xx_netdev_ops;
1160         dev->ethtool_ops = &ag71xx_ethtool_ops;
1161
1162         INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1163
1164         init_timer(&ag->oom_timer);
1165         ag->oom_timer.data = (unsigned long) dev;
1166         ag->oom_timer.function = ag71xx_oom_timer_handler;
1167
1168         ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1169         ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1170
1171         ag->max_frame_len = AG71XX_TX_MTU_LEN;
1172
1173         ag->stop_desc = dma_alloc_coherent(NULL,
1174                 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1175
1176         if (!ag->stop_desc)
1177                 goto err_free_irq;
1178
1179         ag->stop_desc->data = 0;
1180         ag->stop_desc->ctrl = 0;
1181         ag->stop_desc->next = (u32) ag->stop_desc_dma;
1182
1183         memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1184
1185         netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1186
1187         ag71xx_dump_regs(ag);
1188
1189         ag71xx_hw_init(ag);
1190
1191         ag71xx_dump_regs(ag);
1192
1193         err = ag71xx_phy_connect(ag);
1194         if (err)
1195                 goto err_free_desc;
1196
1197         err = ag71xx_debugfs_init(ag);
1198         if (err)
1199                 goto err_phy_disconnect;
1200
1201         platform_set_drvdata(pdev, dev);
1202
1203         err = register_netdev(dev);
1204         if (err) {
1205                 dev_err(&pdev->dev, "unable to register net device\n");
1206                 goto err_debugfs_exit;
1207         }
1208
1209         pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1210                 dev->name, dev->base_addr, dev->irq,
1211                 ag71xx_get_phy_if_mode_name(pdata->phy_if_mode));
1212
1213         return 0;
1214
1215 err_debugfs_exit:
1216         ag71xx_debugfs_exit(ag);
1217 err_phy_disconnect:
1218         ag71xx_phy_disconnect(ag);
1219 err_free_desc:
1220         dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1221                           ag->stop_desc_dma);
1222 err_free_irq:
1223         free_irq(dev->irq, dev);
1224 err_unmap_base:
1225         iounmap(ag->mac_base);
1226 err_free_dev:
1227         kfree(dev);
1228 err_out:
1229         platform_set_drvdata(pdev, NULL);
1230         return err;
1231 }
1232
1233 static int ag71xx_remove(struct platform_device *pdev)
1234 {
1235         struct net_device *dev = platform_get_drvdata(pdev);
1236
1237         if (dev) {
1238                 struct ag71xx *ag = netdev_priv(dev);
1239
1240                 ag71xx_debugfs_exit(ag);
1241                 ag71xx_phy_disconnect(ag);
1242                 unregister_netdev(dev);
1243                 free_irq(dev->irq, dev);
1244                 iounmap(ag->mac_base);
1245                 kfree(dev);
1246                 platform_set_drvdata(pdev, NULL);
1247         }
1248
1249         return 0;
1250 }
1251
1252 static struct platform_driver ag71xx_driver = {
1253         .probe          = ag71xx_probe,
1254         .remove         = ag71xx_remove,
1255         .driver = {
1256                 .name   = AG71XX_DRV_NAME,
1257         }
1258 };
1259
1260 static int __init ag71xx_module_init(void)
1261 {
1262         int ret;
1263
1264         ret = ag71xx_debugfs_root_init();
1265         if (ret)
1266                 goto err_out;
1267
1268         ret = ag71xx_mdio_driver_init();
1269         if (ret)
1270                 goto err_debugfs_exit;
1271
1272         ret = platform_driver_register(&ag71xx_driver);
1273         if (ret)
1274                 goto err_mdio_exit;
1275
1276         return 0;
1277
1278 err_mdio_exit:
1279         ag71xx_mdio_driver_exit();
1280 err_debugfs_exit:
1281         ag71xx_debugfs_root_exit();
1282 err_out:
1283         return ret;
1284 }
1285
1286 static void __exit ag71xx_module_exit(void)
1287 {
1288         platform_driver_unregister(&ag71xx_driver);
1289         ag71xx_mdio_driver_exit();
1290         ag71xx_debugfs_root_exit();
1291 }
1292
1293 module_init(ag71xx_module_init);
1294 module_exit(ag71xx_module_exit);
1295
1296 MODULE_VERSION(AG71XX_DRV_VERSION);
1297 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1298 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1299 MODULE_LICENSE("GPL v2");
1300 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);