target/linux/ar71xx/files/drivers/mtd/nand/rb4xx_nand.c

   1 /*
   2  *  NAND flash driver for the MikroTik RouterBoard 4xx series
   3  *
   4  *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  This file was based on the driver for Linux 2.6.22 published by
   8  *  MikroTik for their RouterBoard 4xx series devices.
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under the terms of the GNU General Public License version 2 as published
  12  *  by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/mtd/nand.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/partitions.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/delay.h>
  21 #include <linux/io.h>
  22 #include <linux/gpio.h>
  23 #include <linux/slab.h>
  24
  25 #include <asm/mach-ar71xx/ar71xx.h>
  26
  27 #define DRV_NAME        "rb4xx-nand"
  28 #define DRV_VERSION     "0.1.10"
  29 #define DRV_DESC        "NAND flash driver for RouterBoard 4xx series"
  30
  31 #define USE_FAST_READ   1
  32 #define USE_FAST_WRITE  1
  33 #undef RB4XX_NAND_DEBUG
  34
  35 #ifdef RB4XX_NAND_DEBUG
  36 #define DBG(fmt, arg...)        printk(KERN_DEBUG DRV_NAME ": " fmt, ## arg)
  37 #else
  38 #define DBG(fmt, arg...)        do {} while (0)
  39 #endif
  40
  41 #define RB4XX_NAND_GPIO_RDY     5
  42 #define RB4XX_FLASH_HZ          33333334
  43 #define RB4XX_NAND_HZ           33333334
  44
  45 #define SPI_CTRL_FASTEST        0x40
  46 #define SPI_CTRL_SAFE           0x43    /* 25 MHz for AHB 200 MHz */
  47 #define SBIT_IOC_BASE           SPI_IOC_CS1
  48 #define SBIT_IOC_DO_SHIFT       0
  49 #define SBIT_IOC_DO             (1u << SBIT_IOC_DO_SHIFT)
  50 #define SBIT_IOC_DO2_SHIFT      18
  51 #define SBIT_IOC_DO2            (1u << SBIT_IOC_DO2_SHIFT)
  52
  53 #define CPLD_CMD_WRITE_MULT     0x08    /* send cmd, n x send data, read data */
  54 #define CPLD_CMD_WRITE_CFG      0x09    /* send cmd, n x send cfg */
  55 #define CPLD_CMD_READ_MULT      0x0a    /* send cmd, send idle, n x read data */
  56 #define CPLD_CMD_READ_FAST      0x0b    /* send cmd, 4 x idle, n x read data */
  57
  58 #define CFG_BIT_nCE     0x80
  59 #define CFG_BIT_CLE     0x40
  60 #define CFG_BIT_ALE     0x20
  61 #define CFG_BIT_FAN     0x10
  62 #define CFG_BIT_nLED4   0x08
  63 #define CFG_BIT_nLED3   0x04
  64 #define CFG_BIT_nLED2   0x02
  65 #define CFG_BIT_nLED1   0x01
  66
  67 #define CFG_BIT_nLEDS \
  68         (CFG_BIT_nLED1 | CFG_BIT_nLED2 | CFG_BIT_nLED3 | CFG_BIT_nLED4)
  69
  70 struct rb4xx_nand_info {
  71         struct nand_chip        chip;
  72         struct mtd_info         mtd;
  73 };
  74
  75 /*
  76  * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
  77  * will not be able to find the kernel that we load.
  78  */
  79 static struct nand_ecclayout rb4xx_nand_ecclayout = {
  80         .eccbytes       = 6,
  81         .eccpos         = { 8, 9, 10, 13, 14, 15 },
  82         .oobavail       = 9,
  83         .oobfree        = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
  84 };
  85
  86 static struct mtd_partition rb4xx_nand_partitions[] = {
  87         {
  88                 .name   = "booter",
  89                 .offset = 0,
  90                 .size   = (256 * 1024),
  91                 .mask_flags = MTD_WRITEABLE,
  92         },
  93         {
  94                 .name   = "kernel",
  95                 .offset = (256 * 1024),
  96                 .size   = (4 * 1024 * 1024) - (256 * 1024),
  97         },
  98         {
  99                 .name   = "rootfs",
 100                 .offset = MTDPART_OFS_NXTBLK,
 101                 .size   = MTDPART_SIZ_FULL,
 102         },
 103 };
 104
 105 #if USE_FAST_READ
 106 #define SPI_NDATA_BASE  0x00800000
 107 static unsigned spi_ctrl_fread = SPI_CTRL_SAFE;
 108 static unsigned spi_ctrl_flash = SPI_CTRL_SAFE;
 109 extern unsigned mips_hpt_frequency;
 110 #endif
 111
 112 static inline unsigned rb4xx_spi_rreg(unsigned r)
 113 {
 114         return __raw_readl((void * __iomem)(KSEG1ADDR(AR71XX_SPI_BASE) + r));
 115 }
 116
 117 static inline void rb4xx_spi_wreg(unsigned r, unsigned v)
 118 {
 119         __raw_writel(v, (void * __iomem)(KSEG1ADDR(AR71XX_SPI_BASE) + r));
 120 }
 121
 122 static inline void do_spi_clk(int bit)
 123 {
 124         unsigned bval = SBIT_IOC_BASE | (bit & 1);
 125
 126         rb4xx_spi_wreg(SPI_REG_IOC, bval);
 127         rb4xx_spi_wreg(SPI_REG_IOC, bval | SPI_IOC_CLK);
 128 }
 129
 130 static void do_spi_byte(uint8_t byte)
 131 {
 132         do_spi_clk(byte >> 7);
 133         do_spi_clk(byte >> 6);
 134         do_spi_clk(byte >> 5);
 135         do_spi_clk(byte >> 4);
 136         do_spi_clk(byte >> 3);
 137         do_spi_clk(byte >> 2);
 138         do_spi_clk(byte >> 1);
 139         do_spi_clk(byte);
 140
 141         DBG("spi_byte sent 0x%02x got 0x%x\n",
 142                                         byte, rb4xx_spi_rreg(SPI_REG_RDS));
 143 }
 144
 145 #if USE_FAST_WRITE
 146 static inline void do_spi_clk_fast(int bit1, int bit2)
 147 {
 148         unsigned bval = (SBIT_IOC_BASE |
 149                         ((bit1 << SBIT_IOC_DO_SHIFT) & SBIT_IOC_DO) |
 150                         ((bit2 << SBIT_IOC_DO2_SHIFT) & SBIT_IOC_DO2));
 151
 152         rb4xx_spi_wreg(SPI_REG_IOC, bval);
 153         rb4xx_spi_wreg(SPI_REG_IOC, bval | SPI_IOC_CLK);
 154 }
 155
 156 static inline void do_spi_byte_fast(uint8_t byte)
 157 {
 158         do_spi_clk_fast(byte >> 7, byte >> 6);
 159         do_spi_clk_fast(byte >> 5, byte >> 4);
 160         do_spi_clk_fast(byte >> 3, byte >> 2);
 161         do_spi_clk_fast(byte >> 1, byte >> 0);
 162
 163         DBG("spi_byte_fast sent 0x%02x got 0x%x\n",
 164                                         byte, rb4xx_spi_rreg(SPI_REG_RDS));
 165 }
 166 #else
 167 static inline void do_spi_byte_fast(uint8_t byte)
 168 {
 169         do_spi_byte(byte);
 170 }
 171 #endif /* USE_FAST_WRITE */
 172
 173 static int do_spi_cmd(unsigned cmd, unsigned sendCnt, const uint8_t *sendData,
 174                 unsigned recvCnt, uint8_t *recvData,
 175                 const uint8_t *verifyData, int fastWrite)
 176 {
 177         unsigned i;
 178
 179         DBG("SPI cmd 0x%x send %u recv %u\n", cmd, sendCnt, recvCnt);
 180
 181         rb4xx_spi_wreg(SPI_REG_FS, SPI_FS_GPIO);
 182         rb4xx_spi_wreg(SPI_REG_CTRL, SPI_CTRL_FASTEST);
 183
 184         do_spi_byte(cmd);
 185 #if 0
 186         if (cmd == CPLD_CMD_READ_FAST) {
 187                 do_spi_byte(0x80);
 188                 do_spi_byte(0);
 189                 do_spi_byte(0);
 190         }
 191 #endif
 192         for (i = 0; i < sendCnt; ++i) {
 193                 if (fastWrite)
 194                         do_spi_byte_fast(sendData[i]);
 195                 else
 196                         do_spi_byte(sendData[i]);
 197         }
 198
 199         for (i = 0; i < recvCnt; ++i) {
 200                 if (fastWrite)
 201                         do_spi_byte_fast(0);
 202                 else
 203                         do_spi_byte(0);
 204
 205                 if (recvData) {
 206                         recvData[i] = rb4xx_spi_rreg(SPI_REG_RDS) & 0xff;
 207                 } else if (verifyData) {
 208                         if (verifyData[i] != (rb4xx_spi_rreg(SPI_REG_RDS)
 209                                                          & 0xff))
 210                                 break;
 211                 }
 212         }
 213
 214         rb4xx_spi_wreg(SPI_REG_IOC, SBIT_IOC_BASE | SPI_IOC_CS0);
 215         rb4xx_spi_wreg(SPI_REG_CTRL, spi_ctrl_flash);
 216         rb4xx_spi_wreg(SPI_REG_FS, 0);
 217
 218         return i == recvCnt;
 219 }
 220
 221 static int got_write = 1;
 222
 223 static void rb4xx_nand_write_data(const uint8_t *byte, unsigned cnt)
 224 {
 225         do_spi_cmd(CPLD_CMD_WRITE_MULT, cnt, byte, 1, NULL, NULL, 1);
 226         got_write = 1;
 227 }
 228
 229 static void rb4xx_nand_write_byte(uint8_t byte)
 230 {
 231         rb4xx_nand_write_data(&byte, 1);
 232 }
 233
 234 #if USE_FAST_READ
 235 static uint8_t *rb4xx_nand_read_getaddr(unsigned cnt)
 236 {
 237         static unsigned nboffset = 0x100000;
 238         unsigned addr;
 239
 240         if (got_write) {
 241                 nboffset = (nboffset + 31) & ~31;
 242                 if (nboffset >= 0x100000)       /* 1MB */
 243                         nboffset = 0;
 244
 245                 got_write = 0;
 246                 rb4xx_spi_wreg(SPI_REG_FS, SPI_FS_GPIO);
 247                 rb4xx_spi_wreg(SPI_REG_CTRL, spi_ctrl_fread);
 248                 rb4xx_spi_wreg(SPI_REG_FS, 0);
 249         }
 250
 251         addr = KSEG1ADDR(AR71XX_SPI_BASE + SPI_NDATA_BASE) + nboffset;
 252         DBG("rb4xx_nand_read_getaddr 0x%x cnt 0x%x\n", addr, cnt);
 253
 254         nboffset += cnt;
 255         return (uint8_t *)addr;
 256 }
 257
 258 static void rb4xx_nand_read_data(uint8_t *buf, unsigned cnt)
 259 {
 260         unsigned size32 = cnt & ~31;
 261         unsigned remain = cnt & 31;
 262
 263         if (size32) {
 264                 uint8_t *addr = rb4xx_nand_read_getaddr(size32);
 265                 memcpy(buf, (void *)addr, size32);
 266         }
 267
 268         if (remain) {
 269                 do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, remain,
 270                            buf + size32, NULL, 0);
 271         }
 272 }
 273
 274 static int rb4xx_nand_verify_data(const uint8_t *buf, unsigned cnt)
 275 {
 276         unsigned size32 = cnt & ~31;
 277         unsigned remain = cnt & 31;
 278
 279         if (size32) {
 280                 uint8_t *addr = rb4xx_nand_read_getaddr(size32);
 281                 if (memcmp(buf, (void *)addr, size32) != 0)
 282                         return 0;
 283         }
 284
 285         if (remain) {
 286                 return do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, remain,
 287                                   NULL, buf + size32, 0);
 288         }
 289         return 1;
 290 }
 291 #else /* USE_FAST_READ */
 292 static void rb4xx_nand_read_data(uint8_t *buf, unsigned cnt)
 293 {
 294         do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, cnt, buf, NULL, 0);
 295 }
 296
 297 static int rb4xx_nand_verify_data(const uint8_t *buf, unsigned cnt)
 298 {
 299         return do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, cnt, NULL, buf, 0);
 300 }
 301 #endif /* USE_FAST_READ */
 302
 303 static void rb4xx_nand_write_cfg(uint8_t byte)
 304 {
 305         do_spi_cmd(CPLD_CMD_WRITE_CFG, 1, &byte, 0, NULL, NULL, 0);
 306         got_write = 1;
 307 }
 308
 309 static int rb4xx_nand_dev_ready(struct mtd_info *mtd)
 310 {
 311         return gpio_get_value(RB4XX_NAND_GPIO_RDY);
 312 }
 313
 314 static void rb4xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 315                                 unsigned int ctrl)
 316 {
 317         if (ctrl & NAND_CTRL_CHANGE) {
 318                 uint8_t cfg = CFG_BIT_nLEDS;
 319
 320                 cfg |= (ctrl & NAND_CLE) ? CFG_BIT_CLE : 0;
 321                 cfg |= (ctrl & NAND_ALE) ? CFG_BIT_ALE : 0;
 322                 cfg |= (ctrl & NAND_NCE) ? 0 : CFG_BIT_nCE;
 323
 324                 rb4xx_nand_write_cfg(cfg);
 325         }
 326
 327         if (cmd != NAND_CMD_NONE)
 328                 rb4xx_nand_write_byte(cmd);
 329 }
 330
 331 static uint8_t rb4xx_nand_read_byte(struct mtd_info *mtd)
 332 {
 333         uint8_t byte = 0;
 334
 335         rb4xx_nand_read_data(&byte, 1);
 336         return byte;
 337 }
 338
 339 static void rb4xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 340                                 int len)
 341 {
 342         rb4xx_nand_write_data(buf, len);
 343 }
 344
 345 static void rb4xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf,
 346                                 int len)
 347 {
 348         rb4xx_nand_read_data(buf, len);
 349 }
 350
 351 static int rb4xx_nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf,
 352                                 int len)
 353 {
 354         if (!rb4xx_nand_verify_data(buf, len))
 355                 return -EFAULT;
 356
 357         return 0;
 358 }
 359
 360 static unsigned get_spi_ctrl(unsigned hz_max, const char *name)
 361 {
 362         unsigned div;
 363
 364         div = (ar71xx_ahb_freq - 1) / (2 * hz_max);
 365         /*
 366          * CPU has a bug at (div == 0) - first bit read is random
 367          */
 368         if (div == 0)
 369                 ++div;
 370
 371         if (name) {
 372                 unsigned ahb_khz = (ar71xx_ahb_freq + 500) / 1000;
 373                 unsigned div_real = 2 * (div + 1);
 374                 printk(KERN_INFO "%s SPI clock %u kHz (AHB %u kHz / %u)\n",
 375                        name,
 376                        ahb_khz / div_real,
 377                        ahb_khz, div_real);
 378         }
 379
 380         return SPI_CTRL_FASTEST + div;
 381 }
 382
 383 static int __init rb4xx_nand_probe(struct platform_device *pdev)
 384 {
 385         struct rb4xx_nand_info  *info;
 386         int ret;
 387
 388         printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n");
 389
 390         ret = gpio_request(RB4XX_NAND_GPIO_RDY, "NAND RDY");
 391         if (ret) {
 392                 printk(KERN_ERR "rb4xx-nand: gpio request failed\n");
 393                 return ret;
 394         }
 395
 396         ret = gpio_direction_input(RB4XX_NAND_GPIO_RDY);
 397         if (ret) {
 398                 printk(KERN_ERR "rb4xx-nand: unable to set input mode "
 399                                         "on gpio%d\n", RB4XX_NAND_GPIO_RDY);
 400                 goto err_free_gpio;
 401         }
 402
 403         info = kzalloc(sizeof(*info), GFP_KERNEL);
 404         if (!info) {
 405                 printk(KERN_ERR "rb4xx-nand: no memory for private data\n");
 406                 ret = -ENOMEM;
 407                 goto err_free_gpio;
 408         }
 409
 410 #if USE_FAST_READ
 411         spi_ctrl_fread = get_spi_ctrl(RB4XX_NAND_HZ, "NAND");
 412 #endif
 413         spi_ctrl_flash = get_spi_ctrl(RB4XX_FLASH_HZ, "FLASH");
 414
 415         rb4xx_nand_write_cfg(CFG_BIT_nLEDS | CFG_BIT_nCE);
 416
 417         info->chip.priv = &info;
 418         info->mtd.priv  = &info->chip;
 419         info->mtd.owner = THIS_MODULE;
 420
 421         info->chip.cmd_ctrl     = rb4xx_nand_cmd_ctrl;
 422         info->chip.dev_ready    = rb4xx_nand_dev_ready;
 423         info->chip.read_byte    = rb4xx_nand_read_byte;
 424         info->chip.write_buf    = rb4xx_nand_write_buf;
 425         info->chip.read_buf     = rb4xx_nand_read_buf;
 426         info->chip.verify_buf   = rb4xx_nand_verify_buf;
 427
 428         info->chip.chip_delay   = 25;
 429         info->chip.ecc.mode     = NAND_ECC_SOFT;
 430         info->chip.options      |= NAND_NO_AUTOINCR;
 431
 432         platform_set_drvdata(pdev, info);
 433
 434         ret = nand_scan_ident(&info->mtd, 1);
 435         if (ret) {
 436                 ret = -ENXIO;
 437                 goto err_free_info;
 438         }
 439
 440         if (info->mtd.writesize == 512)
 441                 info->chip.ecc.layout = &rb4xx_nand_ecclayout;
 442
 443         ret = nand_scan_tail(&info->mtd);
 444         if (ret) {
 445                 return -ENXIO;
 446                 goto err_set_drvdata;
 447         }
 448
 449 #ifdef CONFIG_MTD_PARTITIONS
 450         ret = add_mtd_partitions(&info->mtd, rb4xx_nand_partitions,
 451                                 ARRAY_SIZE(rb4xx_nand_partitions));
 452 #else
 453         ret = add_mtd_device(&info->mtd);
 454 #endif
 455         if (ret)
 456                 goto err_release_nand;
 457
 458         return 0;
 459
 460 err_release_nand:
 461         nand_release(&info->mtd);
 462 err_set_drvdata:
 463         platform_set_drvdata(pdev, NULL);
 464 err_free_info:
 465         kfree(info);
 466 err_free_gpio:
 467         gpio_free(RB4XX_NAND_GPIO_RDY);
 468         return ret;
 469 }
 470
 471 static int __devexit rb4xx_nand_remove(struct platform_device *pdev)
 472 {
 473         struct rb4xx_nand_info *info = platform_get_drvdata(pdev);
 474
 475         nand_release(&info->mtd);
 476         platform_set_drvdata(pdev, NULL);
 477         kfree(info);
 478
 479         return 0;
 480 }
 481
 482 static struct platform_driver rb4xx_nand_driver = {
 483         .probe  = rb4xx_nand_probe,
 484         .remove = __devexit_p(rb4xx_nand_remove),
 485         .driver = {
 486                 .name   = DRV_NAME,
 487                 .owner  = THIS_MODULE,
 488         },
 489 };
 490
 491 static int __init rb4xx_nand_init(void)
 492 {
 493         return platform_driver_register(&rb4xx_nand_driver);
 494 }
 495
 496 static void __exit rb4xx_nand_exit(void)
 497 {
 498         platform_driver_unregister(&rb4xx_nand_driver);
 499 }
 500
 501 module_init(rb4xx_nand_init);
 502 module_exit(rb4xx_nand_exit);
 503
 504 MODULE_DESCRIPTION(DRV_DESC);
 505 MODULE_VERSION(DRV_VERSION);
 506 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 507 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
 508 MODULE_LICENSE("GPL v2");