2 * Atheros AR724x PCI host controller driver
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
6 * Parts of this file are based on Atheros' 2.6.15 BSP
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
13 #include <linux/resource.h>
14 #include <linux/types.h>
15 #include <linux/delay.h>
16 #include <linux/bitops.h>
17 #include <linux/pci.h>
18 #include <linux/pci_regs.h>
20 #include <asm/mach-ar71xx/ar71xx.h>
21 #include <asm/mach-ar71xx/pci.h>
25 #define DBG(fmt, args...) printk(KERN_INFO fmt, ## args)
27 #define DBG(fmt, args...)
30 static void __iomem *ar724x_pci_localcfg_base;
31 static void __iomem *ar724x_pci_devcfg_base;
32 static int ar724x_pci_fixup_enable;
34 static DEFINE_SPINLOCK(ar724x_pci_lock);
36 static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value)
41 spin_lock_irqsave(&ar724x_pci_lock, flags);
42 data = __raw_readl(base + (where & ~3));
60 spin_unlock_irqrestore(&ar724x_pci_lock, flags);
63 static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value)
69 spin_lock_irqsave(&ar724x_pci_lock, flags);
70 data = __raw_readl(base + (where & ~3));
74 s = ((where & 3) << 3);
76 data |= ((value & 0xFF) << s);
79 s = ((where & 2) << 3);
80 data &= ~(0xFFFF << s);
81 data |= ((value & 0xFFFF) << s);
88 __raw_writel(data, base + (where & ~3));
90 (void)__raw_readl(base + (where & ~3));
91 spin_unlock_irqrestore(&ar724x_pci_lock, flags);
94 static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn,
95 int where, int size, u32 *value)
98 if (bus->number != 0 || devfn != 0)
99 return PCIBIOS_DEVICE_NOT_FOUND;
101 ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value);
103 DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
104 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
105 where, size, *value);
108 * WAR for BAR issue - We are unable to access the PCI device space
109 * if we set the BAR with proper base address
111 if ((where == 0x10) && (size == 4))
112 ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff);
114 return PCIBIOS_SUCCESSFUL;
117 static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn,
118 int where, int size, u32 value)
120 if (bus->number != 0 || devfn != 0)
121 return PCIBIOS_DEVICE_NOT_FOUND;
123 DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
124 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
127 ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value);
129 return PCIBIOS_SUCCESSFUL;
132 static void ar724x_pci_fixup(struct pci_dev *dev)
136 if (!ar724x_pci_fixup_enable)
139 if (dev->bus->number != 0 || dev->devfn != 0)
142 /* setup COMMAND register */
143 pci_read_config_word(dev, PCI_COMMAND, &cmd);
144 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
145 PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
146 PCI_COMMAND_FAST_BACK;
148 pci_write_config_word(dev, PCI_COMMAND, cmd);
150 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup);
152 int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
158 for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
159 struct ar71xx_pci_irq *entry;
160 entry = &ar71xx_pci_irq_map[i];
162 if (entry->slot == slot && entry->pin == pin) {
169 printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
170 pin, pci_name((struct pci_dev *)dev));
172 printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
173 irq, pin, pci_name((struct pci_dev *)dev));
178 static struct pci_ops ar724x_pci_ops = {
179 .read = ar724x_pci_read_config,
180 .write = ar724x_pci_write_config,
183 static struct resource ar724x_pci_io_resource = {
184 .name = "PCI IO space",
187 .flags = IORESOURCE_IO,
190 static struct resource ar724x_pci_mem_resource = {
191 .name = "PCI memory space",
192 .start = AR71XX_PCI_MEM_BASE,
193 .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
194 .flags = IORESOURCE_MEM
197 static struct pci_controller ar724x_pci_controller = {
198 .pci_ops = &ar724x_pci_ops,
199 .mem_resource = &ar724x_pci_mem_resource,
200 .io_resource = &ar724x_pci_io_resource,
203 static void __init ar724x_pci_reset(void)
205 ar71xx_device_stop(AR724X_RESET_PCIE);
206 ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
207 ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
210 ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
212 ar71xx_device_start(AR724X_RESET_PCIE_PHY);
213 ar71xx_device_start(AR724X_RESET_PCIE);
216 static int __init ar724x_pci_setup(void)
220 /* setup COMMAND register */
221 t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
222 PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
224 ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t);
225 ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000);
226 ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000);
228 t = ar724x_pci_rr(AR724X_PCI_REG_RESET);
231 ar724x_pci_wr_nf(AR724X_PCI_REG_RESET, 0);
233 ar724x_pci_wr_nf(AR724X_PCI_REG_RESET, 4);
237 ar724x_pci_wr(AR724X_PCI_REG_APP, AR724X_PCI_APP_LTSSM_ENABLE);
240 t = ar724x_pci_rr(AR724X_PCI_REG_APP);
241 if ((t & AR724X_PCI_APP_LTSSM_ENABLE) == 0x0) {
242 printk(KERN_WARNING "PCI: no PCIe module found\n");
249 int __init ar724x_pcibios_init(void)
253 ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE,
254 AR724X_PCI_CRP_SIZE);
256 ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE,
257 AR724X_PCI_CFG_SIZE);
260 ret = ar724x_pci_setup();
264 ar724x_pci_fixup_enable = 1;
265 register_pci_controller(&ar724x_pci_controller);