target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-c1.c

   1 /*
   2  *  D-Link DIR-825 rev. C1 board support
   3  *
   4  *  Copyright (C) 2013 Alexander Stadler
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License version 2 as published
   8  *  by the Free Software Foundation.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/phy.h>
  13 #include <linux/gpio.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/ath9k_platform.h>
  16 #include <linux/ar8216_platform.h>
  17
  18 #include <asm/mach-ath79/ar71xx_regs.h>
  19
  20 #include "common.h"
  21 #include "dev-ap9x-pci.h"
  22 #include "dev-eth.h"
  23 #include "dev-gpio-buttons.h"
  24 #include "dev-leds-gpio.h"
  25 #include "dev-m25p80.h"
  26 #include "dev-spi.h"
  27 #include "dev-usb.h"
  28 #include "dev-wmac.h"
  29 #include "machtypes.h"
  30
  31 #define DIR825C1_GPIO_LED_BLUE_USB              11
  32 #define DIR825C1_GPIO_LED_ORANGE_POWER          15
  33 #define DIR825C1_GPIO_LED_BLUE_POWER            14
  34 #define DIR825C1_GPIO_LED_ORANGE_PLANET         19
  35 #define DIR825C1_GPIO_LED_BLUE_PLANET           18
  36
  37 #define DIR825C1_GPIO_BTN_RESET                 17
  38 #define DIR825C1_GPIO_BTN_WPS                   16
  39
  40 #define DIR825C1_KEYS_POLL_INTERVAL             20      /* msecs */
  41 #define DIR825C1_KEYS_DEBOUNCE_INTERVAL         (3 * DIR825C1_KEYS_POLL_INTERVAL)
  42
  43 #define DIR825C1_MAC0_OFFSET                    0x4
  44 #define DIR825C1_MAC1_OFFSET                    0x18
  45 #define DIR825C1_WMAC_CALDATA_OFFSET            0x1000
  46 #define DIR825C1_PCIE_CALDATA_OFFSET            0x5000
  47
  48 static struct gpio_led dir825c1_leds_gpio[] __initdata = {
  49         {
  50                 .name           = "d-link:blue:usb",
  51                 .gpio           = DIR825C1_GPIO_LED_BLUE_USB,
  52                 .active_low     = 1,
  53         }, {
  54                 .name           = "d-link:orange:power",
  55                 .gpio           = DIR825C1_GPIO_LED_ORANGE_POWER,
  56                 .active_low     = 1,
  57         }, {
  58                 .name           = "d-link:blue:power",
  59                 .gpio           = DIR825C1_GPIO_LED_BLUE_POWER,
  60                 .active_low     = 1,
  61         }, {
  62                 .name           = "d-link:orange:planet",
  63                 .gpio           = DIR825C1_GPIO_LED_ORANGE_PLANET,
  64                 .active_low     = 1,
  65         }, {
  66                 .name           = "d-link:blue:planet",
  67                 .gpio           = DIR825C1_GPIO_LED_BLUE_PLANET,
  68                 .active_low     = 1,
  69         }
  70 };
  71
  72 static struct gpio_keys_button dir825c1_gpio_keys[] __initdata = {
  73         {
  74                 .desc           = "reset",
  75                 .type           = EV_KEY,
  76                 .code           = KEY_RESTART,
  77                 .debounce_interval = DIR825C1_KEYS_DEBOUNCE_INTERVAL,
  78                 .gpio           = DIR825C1_GPIO_BTN_RESET,
  79                 .active_low     = 1,
  80         }, {
  81                 .desc           = "wps",
  82                 .type           = EV_KEY,
  83                 .code           = KEY_WPS_BUTTON,
  84                 .debounce_interval = DIR825C1_KEYS_DEBOUNCE_INTERVAL,
  85                 .gpio           = DIR825C1_GPIO_BTN_WPS,
  86                 .active_low     = 1,
  87         }
  88 };
  89
  90 static struct ar8327_pad_cfg dir825c1_ar8327_pad0_cfg = {
  91         .mode = AR8327_PAD_MAC_RGMII,
  92         .txclk_delay_en = true,
  93         .rxclk_delay_en = true,
  94         .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  95         .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  96 };
  97
  98 static struct ar8327_led_cfg dir825c1_ar8327_led_cfg = {
  99         .led_ctrl0 = 0xc737c737,
 100         .led_ctrl1 = 0x00000000,
 101         .led_ctrl2 = 0x00000000,
 102         .led_ctrl3 = 0x0030c300,
 103         .open_drain = false,
 104 };
 105
 106 static struct ar8327_platform_data dir825c1_ar8327_data = {
 107         .pad0_cfg = &dir825c1_ar8327_pad0_cfg,
 108         .port0_cfg = {
 109                 .force_link = 1,
 110                 .speed = AR8327_PORT_SPEED_1000,
 111                 .duplex = 1,
 112                 .txpause = 1,
 113                 .rxpause = 1,
 114         },
 115         .led_cfg = &dir825c1_ar8327_led_cfg,
 116 };
 117
 118 static struct mdio_board_info dir825c1_mdio0_info[] = {
 119         {
 120                 .bus_id = "ag71xx-mdio.0",
 121                 .phy_addr = 0,
 122                 .platform_data = &dir825c1_ar8327_data,
 123         },
 124 };
 125
 126 static void dir825c1_read_ascii_mac(u8 *dest, u8 *src)
 127 {
 128         int ret;
 129
 130         ret = sscanf(src, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
 131                      &dest[0], &dest[1], &dest[2],
 132                      &dest[3], &dest[4], &dest[5]);
 133
 134         if (ret != ETH_ALEN)
 135                 memset(dest, 0, ETH_ALEN);
 136 }
 137
 138 static void __init dir825c1_setup(void)
 139 {
 140         u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000);
 141         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 142         u8 tmpmac[ETH_ALEN];
 143         u8 mac1[ETH_ALEN], mac2[ETH_ALEN];
 144
 145         dir825c1_read_ascii_mac(mac1, mac + DIR825C1_MAC0_OFFSET);
 146         dir825c1_read_ascii_mac(mac2, mac + DIR825C1_MAC1_OFFSET);
 147
 148         ath79_gpio_output_select(DIR825C1_GPIO_LED_BLUE_USB, AR934X_GPIO_OUT_GPIO);
 149
 150         ath79_register_m25p80(NULL);
 151
 152         ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825c1_leds_gpio),
 153                                  dir825c1_leds_gpio);
 154         ath79_register_gpio_keys_polled(-1, DIR825C1_KEYS_POLL_INTERVAL,
 155                                         ARRAY_SIZE(dir825c1_gpio_keys),
 156                                         dir825c1_gpio_keys);
 157
 158         ap9x_pci_setup_wmac_led_pin(0, 13);
 159         ap9x_pci_setup_wmac_led_pin(1, 32);
 160
 161         ath79_init_mac(tmpmac, mac1, 0);
 162         ath79_register_wmac(art + DIR825C1_WMAC_CALDATA_OFFSET, tmpmac);
 163
 164         ath79_init_mac(tmpmac, mac2, 0);
 165         ap91_pci_init(art + DIR825C1_PCIE_CALDATA_OFFSET, tmpmac);
 166
 167         ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
 168
 169         mdiobus_register_board_info(dir825c1_mdio0_info,
 170                                     ARRAY_SIZE(dir825c1_mdio0_info));
 171
 172         ath79_register_mdio(0, 0x0);
 173
 174         ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
 175
 176         /* GMAC0 is connected to an AR8327N switch */
 177         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 178         ath79_eth0_data.phy_mask = BIT(0);
 179         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 180         ath79_eth0_pll_data.pll_1000 = 0x06000000;
 181         ath79_register_eth(0);
 182
 183         ath79_register_usb();
 184 }
 185
 186 MIPS_MACHINE(ATH79_MACH_DIR_825_C1, "DIR-825-C1",
 187              "D-Link DIR-825 rev. C1",
 188              dir825c1_setup);