target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb42.c

   1 /*
   2  *  Atheros PB42 board support
   3  *
   4  *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License version 2 as published
   9  *  by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/spi/flash.h>
  16
  17 #include <asm/mips_machine.h>
  18 #include <asm/mach-ar71xx/ar71xx.h>
  19 #include <asm/mach-ar71xx/pci.h>
  20 #include <asm/mach-ar71xx/platform.h>
  21
  22 static struct spi_board_info pb42_spi_info[] = {
  23         {
  24                 .bus_num        = 0,
  25                 .chip_select    = 0,
  26                 .max_speed_hz   = 25000000,
  27                 .modalias       = "m25p80",
  28         }
  29 };
  30
  31 static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = {
  32         {
  33                 .slot   = 0,
  34                 .pin    = 1,
  35                 .irq    = AR71XX_PCI_IRQ_DEV0,
  36         }, {
  37                 .slot   = 1,
  38                 .pin    = 1,
  39                 .irq    = AR71XX_PCI_IRQ_DEV1,
  40         }, {
  41                 .slot   = 2,
  42                 .pin    = 1,
  43                 .irq    = AR71XX_PCI_IRQ_DEV2,
  44         }
  45 };
  46
  47 static void __init pb42_init(void)
  48 {
  49         ar71xx_add_device_spi(NULL, pb42_spi_info,
  50                                 ARRAY_SIZE(pb42_spi_info));
  51
  52         ar71xx_add_device_mdio(0xffe0ffff);
  53
  54         ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  55         ar71xx_eth0_data.phy_mask = 0x000f0000;
  56
  57         ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  58         ar71xx_eth1_data.phy_mask = 0x00100000;
  59
  60         ar71xx_add_device_eth(0);
  61         ar71xx_add_device_eth(1);
  62
  63         ar71xx_add_device_usb();
  64
  65         ar71xx_pci_init(ARRAY_SIZE(pb42_pci_irqs), pb42_pci_irqs);
  66 }
  67
  68 MIPS_MACHINE(AR71XX_MACH_PB42, "Atheros PB42", pb42_init);