target/linux/ar71xx/files/arch/mips/ar71xx/mach-dir-825-b1.c

   1 /*
   2  *  D-Link DIR-825 rev. B1 board support
   3  *
   4  *  Copyright (C) 2009 Lukas Kuna, Evkanet, s.r.o.
   5  *
   6  *  based on mach-wndr3700.c
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License version 2 as published
  10  *  by the Free Software Foundation.
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/mtd/mtd.h>
  15 #include <linux/mtd/partitions.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/spi/flash.h>
  18 #include <linux/input.h>
  19 #include <linux/pci.h>
  20 #include <linux/ath9k_platform.h>
  21 #include <linux/delay.h>
  22 #include <linux/rtl8366_smi.h>
  23
  24 #include <asm/mips_machine.h>
  25 #include <asm/mach-ar71xx/ar71xx.h>
  26 #include <asm/mach-ar71xx/pci.h>
  27
  28 #include "devices.h"
  29
  30 #define DIR825B1_GPIO_LED_BLUE_USB              0
  31 #define DIR825B1_GPIO_LED_ORANGE_POWER          1
  32 #define DIR825B1_GPIO_LED_BLUE_POWER            2
  33 #define DIR825B1_GPIO_LED_BLUE_POWERSAVE        4
  34 #define DIR825B1_GPIO_LED_ORANGE_PLANET         6
  35 #define DIR825B1_GPIO_LED_BLUE_PLANET           11
  36
  37 #define DIR825B1_GPIO_BTN_RESET                 3
  38 #define DIR825B1_GPIO_BTN_POWERSAVE             8
  39
  40 #define DIR825B1_GPIO_RTL8366_SDA               5
  41 #define DIR825B1_GPIO_RTL8366_SCK               7
  42
  43 #define DIR825B1_BUTTONS_POLL_INTERVAL          20
  44
  45 #define DIR825B1_CAL_LOCATION_0                 0x1f661000
  46 #define DIR825B1_CAL_LOCATION_1                 0x1f665000
  47
  48 #define DIR825B1_MAC_LOCATION_0                 0x2ffa81b8
  49 #define DIR825B1_MAC_LOCATION_1                 0x2ffa8370
  50
  51 static struct ath9k_platform_data dir825b1_wmac0_data;
  52 static struct ath9k_platform_data dir825b1_wmac1_data;
  53 static char dir825b1_wmac0_mac[6];
  54 static char dir825b1_wmac1_mac[6];
  55
  56 #ifdef CONFIG_MTD_PARTITIONS
  57 static struct mtd_partition dir825b1_partitions[] = {
  58         {
  59                 .name           = "uboot",
  60                 .offset         = 0,
  61                 .size           = 0x040000,
  62                 .mask_flags     = MTD_WRITEABLE,
  63         } , {
  64                 .name           = "config",
  65                 .offset         = 0x040000,
  66                 .size           = 0x010000,
  67                 .mask_flags     = MTD_WRITEABLE,
  68         } , {
  69                 .name           = "firmware",
  70                 .offset         = 0x050000,
  71                 .size           = 0x610000,
  72         } , {
  73                 .name           = "caldata",
  74                 .offset         = 0x660000,
  75                 .size           = 0x010000,
  76                 .mask_flags     = MTD_WRITEABLE,
  77         }
  78 };
  79 #endif /* CONFIG_MTD_PARTITIONS */
  80
  81 static struct flash_platform_data dir825b1_flash_data = {
  82 #ifdef CONFIG_MTD_PARTITIONS
  83         .parts          = dir825b1_partitions,
  84         .nr_parts       = ARRAY_SIZE(dir825b1_partitions),
  85 #endif
  86 };
  87
  88 static struct spi_board_info dir825b1_spi_info[] = {
  89         {
  90                 .bus_num        = 0,
  91                 .chip_select    = 0,
  92                 .max_speed_hz   = 25000000,
  93                 .modalias       = "m25p80",
  94                 .platform_data  = &dir825b1_flash_data,
  95         }
  96 };
  97
  98 static struct gpio_led dir825b1_leds_gpio[] __initdata = {
  99         {
 100                 .name           = "dir825b1:blue:usb",
 101                 .gpio           = DIR825B1_GPIO_LED_BLUE_USB,
 102                 .active_low     = 1,
 103         }, {
 104                 .name           = "dir825b1:orange:power",
 105                 .gpio           = DIR825B1_GPIO_LED_ORANGE_POWER,
 106                 .active_low     = 1,
 107         }, {
 108                 .name           = "dir825b1:blue:power",
 109                 .gpio           = DIR825B1_GPIO_LED_BLUE_POWER,
 110                 .active_low     = 1,
 111         }, {
 112                 .name           = "dir825b1:blue:powersave",
 113                 .gpio           = DIR825B1_GPIO_LED_BLUE_POWERSAVE,
 114                 .active_low     = 1,
 115         }, {
 116                 .name           = "dir825b1:orange:planet",
 117                 .gpio           = DIR825B1_GPIO_LED_ORANGE_PLANET,
 118                 .active_low     = 1,
 119         }, {
 120                 .name           = "dir825b1:blue:planet",
 121                 .gpio           = DIR825B1_GPIO_LED_BLUE_PLANET,
 122                 .active_low     = 1,
 123         }
 124 };
 125
 126 static struct gpio_button dir825b1_gpio_buttons[] __initdata = {
 127         {
 128                 .desc           = "reset",
 129                 .type           = EV_KEY,
 130                 .code           = BTN_0,
 131                 .threshold      = 5,
 132                 .gpio           = DIR825B1_GPIO_BTN_RESET,
 133                 .active_low     = 1,
 134         } , {
 135                 .desc           = "powersave",
 136                 .type           = EV_KEY,
 137                 .code           = BTN_1,
 138                 .threshold      = 5,
 139                 .gpio           = DIR825B1_GPIO_BTN_POWERSAVE,
 140                 .active_low     = 1,
 141         }
 142 };
 143
 144 static struct rtl8366_smi_platform_data dir825b1_rtl8366_smi_data = {
 145         .gpio_sda        = DIR825B1_GPIO_RTL8366_SDA,
 146         .gpio_sck        = DIR825B1_GPIO_RTL8366_SCK,
 147 };
 148
 149 static struct platform_device dir825b1_rtl8366_smi_device = {
 150         .name           = "rtl8366-smi",
 151         .id             = -1,
 152         .dev = {
 153                 .platform_data  = &dir825b1_rtl8366_smi_data,
 154         }
 155 };
 156
 157 #ifdef CONFIG_PCI
 158 static struct ar71xx_pci_irq dir825b1_pci_irqs[] __initdata = {
 159         {
 160                 .slot   = 0,
 161                 .pin    = 1,
 162                 .irq    = AR71XX_PCI_IRQ_DEV0,
 163         }, {
 164                 .slot   = 1,
 165                 .pin    = 1,
 166                 .irq    = AR71XX_PCI_IRQ_DEV1,
 167         }
 168 };
 169
 170 static int dir825b1_pci_plat_dev_init(struct pci_dev *dev)
 171 {
 172         switch(PCI_SLOT(dev->devfn)) {
 173         case 17:
 174                 dev->dev.platform_data = &dir825b1_wmac0_data;
 175                 break;
 176
 177         case 18:
 178                 dev->dev.platform_data = &dir825b1_wmac1_data;
 179                 break;
 180         }
 181
 182         return 0;
 183 }
 184
 185 static void dir825b1_pci_fixup(struct pci_dev *dev)
 186 {
 187         void __iomem *mem;
 188         u16 *cal_data;
 189         u16 cmd;
 190         u32 bar0;
 191         u32 val;
 192
 193         if (ar71xx_mach != AR71XX_MACH_DIR_825_B1)
 194                 return;
 195
 196         dir825b1_pci_plat_dev_init(dev);
 197         cal_data = dev->dev.platform_data;
 198
 199         if (*cal_data != 0xa55a) {
 200                 printk(KERN_ERR "PCI: no calibration data found for %s\n",
 201                        pci_name(dev));
 202                 return;
 203         }
 204
 205         mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000);
 206         if (!mem) {
 207                 printk(KERN_ERR "PCI: ioremap error for device %s\n",
 208                        pci_name(dev));
 209                 return;
 210         }
 211
 212         printk(KERN_INFO "PCI: fixup device %s\n", pci_name(dev));
 213
 214         pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
 215
 216         /* Setup the PCI device to allow access to the internal registers */
 217         pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, AR71XX_PCI_MEM_BASE);
 218         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 219         cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 220         pci_write_config_word(dev, PCI_COMMAND, cmd);
 221
 222         /* set pointer to first reg address */
 223         cal_data += 3;
 224         while (*cal_data != 0xffff) {
 225                 u32 reg;
 226                 reg = *cal_data++;
 227                 val = *cal_data++;
 228                 val |= (*cal_data++) << 16;
 229
 230                 __raw_writel(val, mem + reg);
 231                 udelay(100);
 232         }
 233
 234         pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
 235         dev->vendor = val & 0xffff;
 236         dev->device = (val >> 16) & 0xffff;
 237
 238         pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
 239         dev->revision = val & 0xff;
 240         dev->class = val >> 8; /* upper 3 bytes */
 241
 242         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 243         cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 244         pci_write_config_word(dev, PCI_COMMAND, cmd);
 245
 246         pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
 247
 248         iounmap(mem);
 249 }
 250 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID,
 251                         dir825b1_pci_fixup);
 252
 253 static void __init dir825b1_pci_init(void)
 254 {
 255         memcpy(dir825b1_wmac0_data.eeprom_data,
 256                (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0),
 257                sizeof(dir825b1_wmac0_data.eeprom_data));
 258
 259         memcpy(dir825b1_wmac1_data.eeprom_data,
 260                (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_1),
 261                sizeof(dir825b1_wmac1_data.eeprom_data));
 262
 263         memcpy(dir825b1_wmac0_mac, (u8 *)KSEG1ADDR(DIR825B1_MAC_LOCATION_0), 6);
 264         dir825b1_wmac0_data.macaddr = dir825b1_wmac0_mac;
 265         memcpy(dir825b1_wmac1_mac, (u8 *)KSEG1ADDR(DIR825B1_MAC_LOCATION_1), 6);
 266         dir825b1_wmac1_data.macaddr = dir825b1_wmac1_mac;
 267
 268         ar71xx_pci_plat_dev_init = dir825b1_pci_plat_dev_init;
 269         ar71xx_pci_init(ARRAY_SIZE(dir825b1_pci_irqs), dir825b1_pci_irqs);
 270 }
 271 #else
 272 static void __init dir825b1_pci_init(void) { }
 273 #endif /* CONFIG_PCI */
 274
 275 static void __init dir825b1_setup(void)
 276 {
 277         u8 mac[6], i;
 278
 279         memcpy(mac, (u8*)KSEG1ADDR(DIR825B1_MAC_LOCATION_1), 6);
 280         for(i = 5; i >= 3; i--)
 281                 if(++mac[i] != 0x00) break;
 282
 283         ar71xx_set_mac_base(mac);
 284
 285         ar71xx_add_device_mdio(0x0);
 286
 287         ar71xx_eth0_data.mii_bus_dev = &dir825b1_rtl8366_smi_device.dev;
 288         ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 289         ar71xx_eth0_data.speed = SPEED_1000;
 290         ar71xx_eth0_data.duplex = DUPLEX_FULL;
 291         ar71xx_eth0_pll_data.pll_1000 = 0x11110000;
 292
 293         ar71xx_eth1_data.mii_bus_dev = &dir825b1_rtl8366_smi_device.dev;
 294         ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 295         ar71xx_eth1_data.phy_mask = 0x10;
 296         ar71xx_eth1_pll_data.pll_1000 = 0x11110000;
 297
 298         ar71xx_add_device_eth(0);
 299         ar71xx_add_device_eth(1);
 300
 301         ar71xx_add_device_spi(NULL, dir825b1_spi_info,
 302                               ARRAY_SIZE(dir825b1_spi_info));
 303
 304         ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio),
 305                                         dir825b1_leds_gpio);
 306
 307         ar71xx_add_device_gpio_buttons(-1, DIR825B1_BUTTONS_POLL_INTERVAL,
 308                                         ARRAY_SIZE(dir825b1_gpio_buttons),
 309                                         dir825b1_gpio_buttons);
 310
 311         ar71xx_add_device_usb();
 312
 313         platform_device_register(&dir825b1_rtl8366_smi_device);
 314         dir825b1_pci_init();
 315 }
 316
 317 MIPS_MACHINE(AR71XX_MACH_DIR_825_B1, "D-Link DIR-825 rev. B1", dir825b1_setup);