2 * Atheros AR71xx SoC specific interrupt handling
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
21 #include <asm/irq_cpu.h>
22 #include <asm/mipsregs.h>
24 #include <asm/mach-ar71xx/ar71xx.h>
26 static void ar71xx_gpio_irq_dispatch(void)
28 void __iomem *base = ar71xx_gpio_base;
31 pending = __raw_readl(base + GPIO_REG_INT_PENDING) &
32 __raw_readl(base + GPIO_REG_INT_ENABLE);
35 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
40 static void ar71xx_gpio_irq_unmask(unsigned int irq)
42 void __iomem *base = ar71xx_gpio_base;
45 irq -= AR71XX_GPIO_IRQ_BASE;
47 t = __raw_readl(base + GPIO_REG_INT_ENABLE);
48 __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE);
51 (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
54 static void ar71xx_gpio_irq_mask(unsigned int irq)
56 void __iomem *base = ar71xx_gpio_base;
59 irq -= AR71XX_GPIO_IRQ_BASE;
61 t = __raw_readl(base + GPIO_REG_INT_ENABLE);
62 __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE);
65 (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
68 static struct irq_chip ar71xx_gpio_irq_chip = {
69 .name = "AR71XX GPIO",
70 .unmask = ar71xx_gpio_irq_unmask,
71 .mask = ar71xx_gpio_irq_mask,
72 .mask_ack = ar71xx_gpio_irq_mask,
75 static struct irqaction ar71xx_gpio_irqaction = {
77 .name = "cascade [AR71XX GPIO]",
80 #define GPIO_INT_ALL 0xffff
82 static void __init ar71xx_gpio_irq_init(void)
84 void __iomem *base = ar71xx_gpio_base;
87 __raw_writel(0, base + GPIO_REG_INT_ENABLE);
88 __raw_writel(0, base + GPIO_REG_INT_PENDING);
90 /* setup type of all GPIO interrupts to level sensitive */
91 __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE);
93 /* setup polarity of all GPIO interrupts to active high */
94 __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY);
96 for (i = AR71XX_GPIO_IRQ_BASE;
97 i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++)
98 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
101 setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
104 static void ar71xx_misc_irq_dispatch(void)
108 pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
109 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
111 if (pending & MISC_INT_UART)
112 do_IRQ(AR71XX_MISC_IRQ_UART);
114 else if (pending & MISC_INT_DMA)
115 do_IRQ(AR71XX_MISC_IRQ_DMA);
117 else if (pending & MISC_INT_PERFC)
118 do_IRQ(AR71XX_MISC_IRQ_PERFC);
120 else if (pending & MISC_INT_TIMER)
121 do_IRQ(AR71XX_MISC_IRQ_TIMER);
123 else if (pending & MISC_INT_OHCI)
124 do_IRQ(AR71XX_MISC_IRQ_OHCI);
126 else if (pending & MISC_INT_ERROR)
127 do_IRQ(AR71XX_MISC_IRQ_ERROR);
129 else if (pending & MISC_INT_GPIO)
130 ar71xx_gpio_irq_dispatch();
132 else if (pending & MISC_INT_WDOG)
133 do_IRQ(AR71XX_MISC_IRQ_WDOG);
135 else if (pending & MISC_INT_TIMER2)
136 do_IRQ(AR71XX_MISC_IRQ_TIMER2);
138 else if (pending & MISC_INT_TIMER3)
139 do_IRQ(AR71XX_MISC_IRQ_TIMER3);
141 else if (pending & MISC_INT_TIMER4)
142 do_IRQ(AR71XX_MISC_IRQ_TIMER4);
144 else if (pending & MISC_INT_DDR_PERF)
145 do_IRQ(AR71XX_MISC_IRQ_DDR_PERF);
147 else if (pending & MISC_INT_ENET_LINK)
148 do_IRQ(AR71XX_MISC_IRQ_ENET_LINK);
151 spurious_interrupt();
154 static void ar71xx_misc_irq_unmask(unsigned int irq)
156 void __iomem *base = ar71xx_reset_base;
159 irq -= AR71XX_MISC_IRQ_BASE;
161 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
162 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
165 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
168 static void ar71xx_misc_irq_mask(unsigned int irq)
170 void __iomem *base = ar71xx_reset_base;
173 irq -= AR71XX_MISC_IRQ_BASE;
175 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
176 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
179 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
182 static void ar724x_misc_irq_ack(unsigned int irq)
184 void __iomem *base = ar71xx_reset_base;
187 irq -= AR71XX_MISC_IRQ_BASE;
189 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
190 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
193 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
196 static struct irq_chip ar71xx_misc_irq_chip = {
197 .name = "AR71XX MISC",
198 .unmask = ar71xx_misc_irq_unmask,
199 .mask = ar71xx_misc_irq_mask,
202 static struct irqaction ar71xx_misc_irqaction = {
203 .handler = no_action,
204 .name = "cascade [AR71XX MISC]",
207 static void __init ar71xx_misc_irq_init(void)
209 void __iomem *base = ar71xx_reset_base;
212 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
213 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
215 switch (ar71xx_soc) {
216 case AR71XX_SOC_AR7240:
217 case AR71XX_SOC_AR7241:
218 case AR71XX_SOC_AR7242:
219 case AR71XX_SOC_AR9330:
220 case AR71XX_SOC_AR9331:
221 case AR71XX_SOC_AR9341:
222 case AR71XX_SOC_AR9342:
223 case AR71XX_SOC_AR9344:
224 ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
227 ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
231 for (i = AR71XX_MISC_IRQ_BASE;
232 i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++)
233 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
236 setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
240 * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
241 * these devices typically allocate coherent DMA memory, however the
242 * DMA controller may still have some unsynchronized data in the FIFO.
243 * Issue a flush in the handlers to ensure that the driver sees
246 static void ar71xx_ip2_handler(void)
248 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_PCI);
249 do_IRQ(AR71XX_CPU_IRQ_IP2);
252 static void ar724x_ip2_handler(void)
254 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE);
255 do_IRQ(AR71XX_CPU_IRQ_IP2);
258 static void ar913x_ip2_handler(void)
260 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
261 do_IRQ(AR71XX_CPU_IRQ_IP2);
264 static void ar933x_ip2_handler(void)
266 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC);
267 do_IRQ(AR71XX_CPU_IRQ_IP2);
270 static void ar934x_ip2_handler(void)
272 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_PCIE);
273 do_IRQ(AR71XX_CPU_IRQ_IP2);
276 static void ar71xx_ip3_handler(void)
278 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_USB);
279 do_IRQ(AR71XX_CPU_IRQ_USB);
282 static void ar724x_ip3_handler(void)
284 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_USB);
285 do_IRQ(AR71XX_CPU_IRQ_USB);
288 static void ar913x_ip3_handler(void)
290 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_USB);
291 do_IRQ(AR71XX_CPU_IRQ_USB);
294 static void ar933x_ip3_handler(void)
296 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_USB);
297 do_IRQ(AR71XX_CPU_IRQ_USB);
300 static void ar934x_ip3_handler(void)
302 do_IRQ(AR71XX_CPU_IRQ_USB);
305 static void (*ip2_handler)(void);
306 static void (*ip3_handler)(void);
308 asmlinkage void plat_irq_dispatch(void)
310 unsigned long pending;
312 pending = read_c0_status() & read_c0_cause() & ST0_IM;
314 if (pending & STATUSF_IP7)
315 do_IRQ(AR71XX_CPU_IRQ_TIMER);
317 else if (pending & STATUSF_IP2)
320 else if (pending & STATUSF_IP4)
321 do_IRQ(AR71XX_CPU_IRQ_GE0);
323 else if (pending & STATUSF_IP5)
324 do_IRQ(AR71XX_CPU_IRQ_GE1);
326 else if (pending & STATUSF_IP3)
329 else if (pending & STATUSF_IP6)
330 ar71xx_misc_irq_dispatch();
332 spurious_interrupt();
335 void __init arch_init_irq(void)
337 switch (ar71xx_soc) {
338 case AR71XX_SOC_AR7130:
339 case AR71XX_SOC_AR7141:
340 case AR71XX_SOC_AR7161:
341 ip2_handler = ar71xx_ip2_handler;
342 ip3_handler = ar71xx_ip3_handler;
345 case AR71XX_SOC_AR7240:
346 case AR71XX_SOC_AR7241:
347 case AR71XX_SOC_AR7242:
348 ip2_handler = ar724x_ip2_handler;
349 ip3_handler = ar724x_ip3_handler;
352 case AR71XX_SOC_AR9130:
353 case AR71XX_SOC_AR9132:
354 ip2_handler = ar913x_ip2_handler;
355 ip3_handler = ar913x_ip3_handler;
358 case AR71XX_SOC_AR9330:
359 case AR71XX_SOC_AR9331:
360 ip2_handler = ar933x_ip2_handler;
361 ip3_handler = ar933x_ip3_handler;
364 case AR71XX_SOC_AR9341:
365 case AR71XX_SOC_AR9342:
366 case AR71XX_SOC_AR9344:
367 ip2_handler = ar934x_ip2_handler;
368 ip3_handler = ar934x_ip3_handler;
377 ar71xx_misc_irq_init();
379 cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
381 ar71xx_gpio_irq_init();