target/linux/ar7-2.4/patches/000-ar7_support.patch

   1 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
   2 --- linux.old/arch/mips/Makefile        2005-10-21 16:43:16.316951500 +0200
   3 +++ linux.dev/arch/mips/Makefile        2005-11-10 01:10:45.775570250 +0100
   4 @@ -369,6 +369,16 @@
   5  endif
   6
   7  #
   8 +# Texas Instruments AR7
   9 +#
  10 +
  11 +ifdef CONFIG_AR7
  12 +LIBS           += arch/mips/ar7/ar7.o
  13 +SUBDIRS                += arch/mips/ar7
  14 +LOADADDR       += 0x94020000
  15 +endif
  16 +
  17 +#
  18  # DECstation family
  19  #
  20  ifdef CONFIG_DECSTATION
  21 diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile
  22 --- linux.old/arch/mips/ar7/Makefile    1970-01-01 01:00:00.000000000 +0100
  23 +++ linux.dev/arch/mips/ar7/Makefile    2005-11-10 01:13:51.443173750 +0100
  24 @@ -0,0 +1,14 @@
  25 +.S.s:
  26 +       $(CPP) $(AFLAGS) $< -o $*.s
  27 +
  28 +.S.o:
  29 +       $(CC) $(AFLAGS) -c $< -o $*.o
  30 +
  31 +EXTRA_CFLAGS := -I$(TOPDIR)/include/asm/ar7 -DLITTLE_ENDIAN -D_LINK_KSEG0_
  32 +O_TARGET := ar7.o
  33 +
  34 +obj-y := tnetd73xx_misc.o misc.o
  35 +export-objs := misc.o irq.o init.o
  36 +obj-y += setup.o irq.o int-handler.o reset.o init.o psp_env.o memory.o promlib.o cmdline.o
  37 +
  38 +include $(TOPDIR)/Rules.make
  39 diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c
  40 --- linux.old/arch/mips/ar7/cmdline.c   1970-01-01 01:00:00.000000000 +0100
  41 +++ linux.dev/arch/mips/ar7/cmdline.c   2005-11-10 01:14:16.372731750 +0100
  42 @@ -0,0 +1,88 @@
  43 +/*
  44 + * Carsten Langgaard, carstenl@mips.com
  45 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
  46 + *
  47 + * This program is free software; you can distribute it and/or modify it
  48 + * under the terms of the GNU General Public License (Version 2) as
  49 + * published by the Free Software Foundation.
  50 + *
  51 + * This program is distributed in the hope it will be useful, but WITHOUT
  52 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  53 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  54 + * for more details.
  55 + *
  56 + * You should have received a copy of the GNU General Public License along
  57 + * with this program; if not, write to the Free Software Foundation, Inc.,
  58 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  59 + *
  60 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
  61 + */
  62 +#include <linux/init.h>
  63 +#include <linux/string.h>
  64 +
  65 +#include <asm/bootinfo.h>
  66 +
  67 +extern int prom_argc;
  68 +extern int *_prom_argv;
  69 +
  70 +/*
  71 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
  72 + * This macro take care of sign extension.
  73 + */
  74 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
  75 +
  76 +char arcs_cmdline[CL_SIZE];
  77 +#ifdef CONFIG_CMDLINE_BOOL
  78 +char __initdata cfg_cmdline[] = CONFIG_CMDLINE;
  79 +#endif
  80 +
  81 +char * __init prom_getcmdline(void)
  82 +{
  83 +       return &(arcs_cmdline[0]);
  84 +}
  85 +
  86 +
  87 +void  __init prom_init_cmdline(void)
  88 +{
  89 +       char *cp, *end;
  90 +       int actr;
  91 +       char *env_cmdline = prom_getenv("kernel_args");
  92 +       size_t len;
  93 +
  94 +       actr = 1; /* Always ignore argv[0] */
  95 +
  96 +       cp = end = &(arcs_cmdline[0]);
  97 +       end += sizeof(arcs_cmdline);
  98 +
  99 +       if (env_cmdline) {
 100 +               len = strlen(env_cmdline);
 101 +               if (len > end - cp - 1)
 102 +                       len = end - cp - 1;
 103 +               strncpy(cp, env_cmdline, len);
 104 +               cp += len;
 105 +               *cp++ = ' ';
 106 +       }
 107 +#ifdef CONFIG_CMDLINE_BOOL
 108 +       else {
 109 +               len = strlen(cfg_cmdline);
 110 +               if (len > end - cp - 1)
 111 +                       len = end - cp - 1;
 112 +               strncpy(cp, cfg_cmdline, len);
 113 +               cp += len;
 114 +               *cp++ = ' ';
 115 +       }
 116 +#endif
 117 +
 118 +       while(actr < prom_argc) {
 119 +               len = strlen(prom_argv(actr));
 120 +               if (len > end - cp - 1)
 121 +                       break;
 122 +               strncpy(cp, prom_argv(actr), len);
 123 +               cp += len;
 124 +               *cp++ = ' ';
 125 +               actr++;
 126 +       }
 127 +       if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
 128 +               --cp;
 129 +       *cp = '\0';
 130 +}
 131 diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c
 132 --- linux.old/arch/mips/ar7/init.c      1970-01-01 01:00:00.000000000 +0100
 133 +++ linux.dev/arch/mips/ar7/init.c      2005-11-10 01:10:45.795571500 +0100
 134 @@ -0,0 +1,199 @@
 135 +/*
 136 + * Carsten Langgaard, carstenl@mips.com
 137 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
 138 + *
 139 + *  This program is free software; you can distribute it and/or modify it
 140 + *  under the terms of the GNU General Public License (Version 2) as
 141 + *  published by the Free Software Foundation.
 142 + *
 143 + *  This program is distributed in the hope it will be useful, but WITHOUT
 144 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 145 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 146 + *  for more details.
 147 + *
 148 + *  You should have received a copy of the GNU General Public License along
 149 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 150 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 151 + *
 152 + * PROM library initialisation code.
 153 + */
 154 +#include <linux/config.h>
 155 +#include <linux/init.h>
 156 +#include <linux/string.h>
 157 +#include <linux/kernel.h>
 158 +#include <linux/module.h>
 159 +
 160 +#include <asm/io.h>
 161 +#include <asm/mips-boards/prom.h>
 162 +#include <asm/mips-boards/generic.h>
 163 +
 164 +#include <asm/ar7/adam2_env.h>
 165 +
 166 +int prom_argc;
 167 +int *_prom_argv, *_prom_envp;
 168 +
 169 +/* max # of Adam2 environment variables */
 170 +#define MAX_ENV_ENTRY 80
 171 +
 172 +static t_env_var local_envp[MAX_ENV_ENTRY];
 173 +static int env_type = 0;
 174 +int init_debug = 0;
 175 +
 176 +unsigned int max_env_entry;
 177 +
 178 +extern char *prom_psp_getenv(char *envname);
 179 +
 180 +static inline char *prom_adam2_getenv(char *envname)
 181 +{
 182 +       /*
 183 +        * Return a pointer to the given environment variable.
 184 +        * In 64-bit mode: we're using 64-bit pointers, but all pointers
 185 +        * in the PROM structures are only 32-bit, so we need some
 186 +        * workarounds, if we are running in 64-bit mode.
 187 +        */
 188 +       int i;
 189 +       t_env_var *env = (t_env_var *) local_envp;
 190 +
 191 +       if (strcmp("bootloader", envname) == 0)
 192 +               return "Adam2";
 193 +
 194 +       i = strlen(envname);
 195 +       while (env->name) {
 196 +               if(strncmp(envname, env->name, i) == 0) {
 197 +                       return(env->val);
 198 +               }
 199 +               env++;
 200 +       }
 201 +
 202 +       return NULL;
 203 +}
 204 +
 205 +/* XXX "bootloader" won't be returned.
 206 + * Better make it an element of local_envp */
 207 +static inline t_env_var *
 208 +prom_adam2_iterenv(t_env_var *env) {
 209 +       if (!env)
 210 +         env = local_envp;
 211 +       else
 212 +         env++;
 213 +       if (env - local_envp > MAX_ENV_ENTRY || !env->name)
 214 +         return 0;
 215 +       return env;
 216 +}
 217 +
 218 +char *prom_getenv(char *envname)
 219 +{
 220 +       if (env_type == 1)
 221 +               return prom_psp_getenv(envname);
 222 +       else
 223 +               return prom_adam2_getenv(envname);
 224 +}
 225 +
 226 +t_env_var *
 227 +prom_iterenv(t_env_var *last)
 228 +{
 229 +       if (env_type == 1)
 230 +         return 0; /* not yet implemented */
 231 +       return prom_adam2_iterenv(last);
 232 +}
 233 +
 234 +static inline unsigned char str2hexnum(unsigned char c)
 235 +{
 236 +       if (c >= '0' && c <= '9')
 237 +               return c - '0';
 238 +       if (c >= 'a' && c <= 'f')
 239 +               return c - 'a' + 10;
 240 +       return 0; /* foo */
 241 +}
 242 +
 243 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
 244 +{
 245 +       int i;
 246 +
 247 +       for (i = 0; i < 6; i++) {
 248 +               unsigned char num;
 249 +
 250 +               if((*str == '.') || (*str == ':'))
 251 +                       str++;
 252 +               num = str2hexnum(*str++) << 4;
 253 +               num |= (str2hexnum(*str++));
 254 +               ea[i] = num;
 255 +       }
 256 +}
 257 +
 258 +int get_ethernet_addr(char *ethernet_addr)
 259 +{
 260 +       char *ethaddr_str;
 261 +
 262 +       ethaddr_str = prom_getenv("ethaddr");
 263 +       if (!ethaddr_str) {
 264 +               printk("ethaddr not set in boot prom\n");
 265 +               return -1;
 266 +       }
 267 +       str2eaddr(ethernet_addr, ethaddr_str);
 268 +
 269 +       if (init_debug > 1) {
 270 +               int i;
 271 +               printk("get_ethernet_addr: ");
 272 +               for (i=0; i<5; i++)
 273 +                       printk("%02x:", (unsigned char)*(ethernet_addr+i));
 274 +               printk("%02x\n", *(ethernet_addr+i));
 275 +       }
 276 +
 277 +       return 0;
 278 +}
 279 +
 280 +struct psbl_rec {
 281 +    unsigned int psbl_size;
 282 +    unsigned int env_base;
 283 +    unsigned int env_size;
 284 +    unsigned int ffs_base;
 285 +    unsigned int ffs_size;
 286 +};
 287 +
 288 +static const char psp_env_version[] = "TIENV0.8";
 289 +
 290 +int __init prom_init(int argc, char **argv, char **envp)
 291 +{
 292 +       int i;
 293 +
 294 +       t_env_var *env = (t_env_var *) envp;
 295 +       struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x94000300));
 296 +       void *psp_env = (void *)KSEG1ADDR(psbl->env_base);
 297 +
 298 +       prom_argc = argc;
 299 +       _prom_argv = (int *)argv;
 300 +       _prom_envp = (int *)envp;
 301 +
 302 +       if(strcmp(psp_env, psp_env_version) == 0) {
 303 +               /* PSPBOOT */
 304 +
 305 +               env_type = 1;
 306 +               _prom_envp = psp_env;
 307 +               max_env_entry = (psbl->env_size / 16) - 1;
 308 +       } else {
 309 +               /* Copy what we need locally so we are not dependent on
 310 +                * bootloader RAM.  In Adam2, the environment parameters
 311 +                * are in flash but the table that references them is in
 312 +                * RAM
 313 +                */
 314 +
 315 +               for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
 316 +                       if (env->name) {
 317 +                               local_envp[i].name = env->name;
 318 +                               local_envp[i].val = env->val;
 319 +                       } else {
 320 +                               local_envp[i].name = NULL;
 321 +                               local_envp[i].val = NULL;
 322 +                       }
 323 +               }
 324 +       }
 325 +
 326 +       set_io_port_base(0);
 327 +
 328 +       prom_printf("\nLINUX started...\n");
 329 +       prom_init_cmdline();
 330 +       prom_meminit();
 331 +
 332 +       return 0;
 333 +}
 334 diff -urN linux.old/arch/mips/ar7/int-handler.S linux.dev/arch/mips/ar7/int-handler.S
 335 --- linux.old/arch/mips/ar7/int-handler.S       1970-01-01 01:00:00.000000000 +0100
 336 +++ linux.dev/arch/mips/ar7/int-handler.S       2005-11-10 01:12:43.938955000 +0100
 337 @@ -0,0 +1,63 @@
 338 +/*
 339 + * Copyright 2004 PMC-Sierra Inc.
 340 + * Author: Manish Lachwani (lachwani@pmc-sierra.com)
 341 + * Adaption for AR7: Enrik Berkhan <enrik@akk.org>
 342 + *
 343 + * First-level interrupt dispatcher for the TI AR7
 344 + *
 345 + * This program is free software; you can redistribute  it and/or modify it
 346 + * under  the terms of  the GNU General  Public License as published by the
 347 + * Free Software Foundation;  either version 2 of the  License, or (at your
 348 + * option) any later version.
 349 + */
 350 +#define __ASSEMBLY__
 351 +#include <linux/config.h>
 352 +#include <asm/asm.h>
 353 +#include <asm/mipsregs.h>
 354 +#include <asm/addrspace.h>
 355 +#include <asm/regdef.h>
 356 +#include <asm/stackframe.h>
 357 +
 358 +/*
 359 + * First level interrupt dispatcher for TI AR7 based boards
 360 + */
 361 +
 362 +               .align  5
 363 +               NESTED(ar7IRQ, PT_SIZE, sp)
 364 +               SAVE_ALL
 365 +               CLI
 366 +               .set    at
 367 +
 368 +               mfc0    t0, CP0_CAUSE
 369 +               mfc0    t2, CP0_STATUS
 370 +
 371 +               and     t0, t2
 372 +
 373 +               andi    t1, t0, STATUSF_IP2     /* hw0 hardware interrupt */
 374 +               bnez    t1, ll_hw0_irq
 375 +
 376 +               andi    t1, t0, STATUSF_IP7     /* R4k CPU timer */
 377 +               bnez    t1, ll_timer_irq
 378 +
 379 +               .set    reorder
 380 +
 381 +               /* wrong alarm or masked ... */
 382 +               j       spurious_interrupt
 383 +               nop
 384 +               END(ar7IRQ)
 385 +
 386 +               .align  5
 387 +
 388 +ll_hw0_irq:
 389 +               li      a0, 2
 390 +               move    a1, sp
 391 +               jal     do_IRQ
 392 +               j       ret_from_irq
 393 +
 394 +ll_timer_irq:
 395 +               li      a0, 7
 396 +               move    a1, sp
 397 +               jal     do_IRQ
 398 +               j       ret_from_irq
 399 +
 400 +
 401 diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c
 402 --- linux.old/arch/mips/ar7/irq.c       1970-01-01 01:00:00.000000000 +0100
 403 +++ linux.dev/arch/mips/ar7/irq.c       2005-11-10 01:12:43.938955000 +0100
 404 @@ -0,0 +1,427 @@
 405 +/*
 406 + * Nitin Dhingra, iamnd@ti.com
 407 + * Copyright (C) 2002 Texas Instruments, Inc.  All rights reserved.
 408 + *
 409 + * ########################################################################
 410 + *
 411 + *  This program is free software; you can distribute it and/or modify it
 412 + *  under the terms of the GNU General Public License (Version 2) as
 413 + *  published by the Free Software Foundation.
 414 + *
 415 + *  This program is distributed in the hope it will be useful, but WITHOUT
 416 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 417 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 418 + *  for more details.
 419 + *
 420 + *  You should have received a copy of the GNU General Public License along
 421 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 422 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 423 + *
 424 + * ########################################################################
 425 + *
 426 + * Routines for generic manipulation of the interrupts found on the Texas
 427 + * Instruments avalanche board
 428 + *
 429 + */
 430 +
 431 +#include <linux/init.h>
 432 +#include <linux/interrupt.h>
 433 +
 434 +#include <asm/irq.h>
 435 +#include <asm/mipsregs.h>
 436 +#include <asm/ar7/ar7.h>
 437 +#include <asm/ar7/avalanche_intc.h>
 438 +
 439 +#define shutdown_avalanche_irq disable_avalanche_irq
 440 +#define mask_and_ack_avalanche_irq   disable_avalanche_irq
 441 +
 442 +static unsigned int startup_avalanche_irq(unsigned int irq);
 443 +static void end_avalanche_irq(unsigned int irq);
 444 +void enable_avalanche_irq(unsigned int irq_nr);
 445 +void disable_avalanche_irq(unsigned int irq_nr);
 446 +void ar7_hw0_interrupt(int interrupt, void *dev, struct pt_regs *regs);
 447 +
 448 +static struct hw_interrupt_type avalanche_irq_type = {
 449 +       "AR7",
 450 +       startup_avalanche_irq,
 451 +       shutdown_avalanche_irq,
 452 +       enable_avalanche_irq,
 453 +       disable_avalanche_irq,
 454 +       mask_and_ack_avalanche_irq,
 455 +       end_avalanche_irq,
 456 +       NULL
 457 +};
 458 +
 459 +static int ar7_irq_base;
 460 +
 461 +static struct irqaction ar7_hw0_action = {
 462 +    ar7_hw0_interrupt, 0, 0, "AR7 on hw0", NULL, NULL
 463 +};
 464 +
 465 +struct avalanche_ictrl_regs         *avalanche_hw0_icregs;  /* Interrupt control regs (primary)   */
 466 +struct avalanche_exctrl_regs        *avalanche_hw0_ecregs;  /* Exception control regs (secondary) */
 467 +struct avalanche_ipace_regs         *avalanche_hw0_ipaceregs;
 468 +struct avalanche_channel_int_number *avalanche_hw0_chregs;  /* Channel control registers          */
 469 +
 470 +/*
 471 +   This remaps interrupts to exist on other channels than the default
 472 +   channels.  essentially we can use the line # as the index for this
 473 +   array
 474 + */
 475 +
 476 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
 477 +unsigned long uni_secondary_interrupt = 0;
 478 +
 479 +static void end_avalanche_irq(unsigned int irq)
 480 +{
 481 +       if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 482 +               enable_avalanche_irq(irq);
 483 +}
 484 +
 485 +void disable_avalanche_irq(unsigned int irq_nr)
 486 +{
 487 +       unsigned long flags;
 488 +       unsigned long chan_nr=0;
 489 +
 490 +       save_and_cli(flags);
 491 +
 492 +       /* irq_nr represents the line number for the interrupt.  We must
 493 +        *  disable the channel number associated with that line number.
 494 +        */
 495 +
 496 +       if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
 497 +               chan_nr = AVINTNUM(irq_nr);                 /*CHECK THIS ALSO*/
 498 +       else
 499 +               chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
 500 +
 501 +       /* disable the interrupt channel bit */
 502 +
 503 +       /* primary interrupt #'s 0-31 */
 504 +
 505 +       if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
 506 +               avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
 507 +
 508 +       /* primary interrupt #'s 32-39 */
 509 +
 510 +       else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
 511 +                       (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
 512 +               avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
 513 +
 514 +       else  /* secondary interrupt #'s 0-31 */
 515 +               avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
 516 +
 517 +       restore_flags(flags);
 518 +}
 519 +
 520 +void enable_avalanche_irq(unsigned int irq_nr)
 521 +{
 522 +       unsigned long flags;
 523 +       unsigned long chan_nr=0;
 524 +
 525 +       save_and_cli(flags);
 526 +
 527 +       /* irq_nr represents the line number for the interrupt.  We must
 528 +        *  disable the channel number associated with that line number.
 529 +        */
 530 +
 531 +       if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
 532 +               chan_nr = AVINTNUM(irq_nr);
 533 +       else
 534 +               chan_nr = line_to_channel[AVINTNUM(irq_nr)];
 535 +
 536 +       /* enable the interrupt channel  bit */
 537 +
 538 +       /* primary interrupt #'s 0-31 */
 539 +       if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
 540 +               avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
 541 +
 542 +       /* primary interrupt #'s 32 throuth 39 */
 543 +       else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
 544 +                       (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
 545 +               avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
 546 +
 547 +       else    /* secondary interrupt #'s 0-31 */
 548 +               avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
 549 +
 550 +       restore_flags(flags);
 551 +}
 552 +
 553 +static unsigned int startup_avalanche_irq(unsigned int irq)
 554 +{
 555 +       enable_avalanche_irq(irq);
 556 +       return 0; /* never anything pending */
 557 +}
 558 +
 559 +void __init ar7_irq_init(int base)
 560 +{
 561 +       int i;
 562 +
 563 +       avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
 564 +       avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
 565 +       avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
 566 +       avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
 567 +
 568 +       /*  Disable interrupts and clear pending
 569 +        */
 570 +
 571 +       avalanche_hw0_icregs->intecr1 = 0xffffffff;    /* disable interrupts 0:31  */
 572 +       avalanche_hw0_icregs->intcr1 = 0xffffffff;     /* clear interrupts 0:31    */
 573 +       avalanche_hw0_icregs->intecr2 = 0xff;          /* disable interrupts 32:39 */
 574 +       avalanche_hw0_icregs->intcr2 = 0xff;           /* clear interrupts 32:39   */
 575 +       avalanche_hw0_ecregs->exiecr = 0xffffffff;     /* disable secondary interrupts 0:31 */
 576 +       avalanche_hw0_ecregs->excr = 0xffffffff;       /* clear secondary interrupts 0:31 */
 577 +
 578 +
 579 +       // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
 580 +       /* hack for speeding up the pacing. */
 581 +       printk("the pacing pre-scalar has been set as 600.\n");
 582 +       avalanche_hw0_ipaceregs->ipacep = 600;
 583 +       /* Channel to line mapping, Line to Channel mapping */
 584 +
 585 +       for(i = 0; i < 40; i++)
 586 +               avalanche_int_set(i,i);
 587 +
 588 +       ar7_irq_base = base;
 589 +       for (i = base; i <= base+40; i++)
 590 +       {
 591 +               irq_desc[i].status      = IRQ_DISABLED;
 592 +               irq_desc[i].action      = 0;
 593 +               irq_desc[i].depth       = 1;
 594 +               irq_desc[i].handler     = &avalanche_irq_type;
 595 +       }
 596 +
 597 +       setup_irq(2, &ar7_hw0_action);
 598 +       set_c0_status(IE_IRQ0);
 599 +
 600 +       return;
 601 +}
 602 +
 603 +void ar7_hw0_interrupt(int interrupt, void *dev, struct pt_regs *regs)
 604 +{
 605 +       int irq;
 606 +       unsigned long int_line_number, status;
 607 +       int i, chan_nr = 0;
 608 +
 609 +       int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
 610 +       chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
 611 +
 612 +       if(chan_nr < 32) /* primary 0-31 */
 613 +       {
 614 +               if( chan_nr != uni_secondary_interrupt)
 615 +                       avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
 616 +
 617 +       }
 618 +
 619 +       if((chan_nr < 40) && (chan_nr > 31)) /* primary 32-39 */
 620 +       {
 621 +               avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-32));
 622 +       }
 623 +
 624 +
 625 +       /* If the Priority Interrupt Index Register returns 40  then no
 626 +        * interrupts are pending
 627 +        */
 628 +
 629 +       if(chan_nr == 40)
 630 +               return;
 631 +
 632 +       if(chan_nr == uni_secondary_interrupt) /* secondary 0-31 */
 633 +       {
 634 +               status = avalanche_hw0_ecregs->exsr;
 635 +               for(i=0; i < 32; i++)
 636 +               {
 637 +                       if (status & 1<<i)
 638 +                       {
 639 +                               /* clear secondary interrupt */
 640 +                               avalanche_hw0_ecregs->excr = 1 << i;
 641 +                               break;
 642 +                       }
 643 +               }
 644 +               irq = i+40;
 645 +
 646 +               /* clear the universal secondary interrupt */
 647 +               avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
 648 +
 649 +       }
 650 +       else
 651 +               irq = chan_nr;
 652 +
 653 +       do_IRQ(irq + ar7_irq_base, regs);
 654 +       return;
 655 +}
 656 +
 657 +void avalanche_int_set(int channel, int line)
 658 +{
 659 +       switch(channel)
 660 +       {
 661 +               case(0):
 662 +                       avalanche_hw0_chregs->cintnr0 =  line;
 663 +                       break;
 664 +               case(1):
 665 +                       avalanche_hw0_chregs->cintnr1 =  line;
 666 +                       break;
 667 +               case(2):
 668 +                       avalanche_hw0_chregs->cintnr2 =  line;
 669 +                       break;
 670 +               case(3):
 671 +                       avalanche_hw0_chregs->cintnr3 =  line;
 672 +                       break;
 673 +               case(4):
 674 +                       avalanche_hw0_chregs->cintnr4 =  line;
 675 +                       break;
 676 +               case(5):
 677 +                       avalanche_hw0_chregs->cintnr5 =  line;
 678 +                       break;
 679 +               case(6):
 680 +                       avalanche_hw0_chregs->cintnr6 =  line;
 681 +                       break;
 682 +               case(7):
 683 +                       avalanche_hw0_chregs->cintnr7 =  line;
 684 +                       break;
 685 +               case(8):
 686 +                       avalanche_hw0_chregs->cintnr8 =  line;
 687 +                       break;
 688 +               case(9):
 689 +                       avalanche_hw0_chregs->cintnr9 =  line;
 690 +                       break;
 691 +               case(10):
 692 +                       avalanche_hw0_chregs->cintnr10 = line;
 693 +                       break;
 694 +               case(11):
 695 +                       avalanche_hw0_chregs->cintnr11 = line;
 696 +                       break;
 697 +               case(12):
 698 +                       avalanche_hw0_chregs->cintnr12 = line;
 699 +                       break;
 700 +               case(13):
 701 +                       avalanche_hw0_chregs->cintnr13 = line;
 702 +                       break;
 703 +               case(14):
 704 +                       avalanche_hw0_chregs->cintnr14 = line;
 705 +                       break;
 706 +               case(15):
 707 +                       avalanche_hw0_chregs->cintnr15 = line;
 708 +                       break;
 709 +               case(16):
 710 +                       avalanche_hw0_chregs->cintnr16 = line;
 711 +                       break;
 712 +               case(17):
 713 +                       avalanche_hw0_chregs->cintnr17 = line;
 714 +                       break;
 715 +               case(18):
 716 +                       avalanche_hw0_chregs->cintnr18 = line;
 717 +                       break;
 718 +               case(19):
 719 +                       avalanche_hw0_chregs->cintnr19 = line;
 720 +                       break;
 721 +               case(20):
 722 +                       avalanche_hw0_chregs->cintnr20 = line;
 723 +                       break;
 724 +               case(21):
 725 +                       avalanche_hw0_chregs->cintnr21 = line;
 726 +                       break;
 727 +               case(22):
 728 +                       avalanche_hw0_chregs->cintnr22 = line;
 729 +                       break;
 730 +               case(23):
 731 +                       avalanche_hw0_chregs->cintnr23 = line;
 732 +                       break;
 733 +               case(24):
 734 +                       avalanche_hw0_chregs->cintnr24 = line;
 735 +                       break;
 736 +               case(25):
 737 +                       avalanche_hw0_chregs->cintnr25 = line;
 738 +                       break;
 739 +               case(26):
 740 +                       avalanche_hw0_chregs->cintnr26 = line;
 741 +                       break;
 742 +               case(27):
 743 +                       avalanche_hw0_chregs->cintnr27 = line;
 744 +                       break;
 745 +               case(28):
 746 +                       avalanche_hw0_chregs->cintnr28 = line;
 747 +                       break;
 748 +               case(29):
 749 +                       avalanche_hw0_chregs->cintnr29 = line;
 750 +                       break;
 751 +               case(30):
 752 +                       avalanche_hw0_chregs->cintnr30 = line;
 753 +                       break;
 754 +               case(31):
 755 +                       avalanche_hw0_chregs->cintnr31 = line;
 756 +                       break;
 757 +               case(32):
 758 +                       avalanche_hw0_chregs->cintnr32 = line;
 759 +                       break;
 760 +               case(33):
 761 +                       avalanche_hw0_chregs->cintnr33 = line;
 762 +                       break;
 763 +               case(34):
 764 +                       avalanche_hw0_chregs->cintnr34 = line;
 765 +                       break;
 766 +               case(35):
 767 +                       avalanche_hw0_chregs->cintnr35 = line;
 768 +                       break;
 769 +               case(36):
 770 +                       avalanche_hw0_chregs->cintnr36 = line;
 771 +                       break;
 772 +               case(37):
 773 +                       avalanche_hw0_chregs->cintnr37 = line;
 774 +                       break;
 775 +               case(38):
 776 +                       avalanche_hw0_chregs->cintnr38 = line;
 777 +                       break;
 778 +               case(39):
 779 +                       avalanche_hw0_chregs->cintnr39 = line;
 780 +                       break;
 781 +               default:
 782 +                       printk("Error: Unknown Avalanche interrupt channel\n");
 783 +       }
 784 +
 785 +       line_to_channel[line] = channel; /* Suraj check */
 786 +
 787 +       if (channel == UNIFIED_SECONDARY_INTERRUPT)
 788 +               uni_secondary_interrupt = line;
 789 +
 790 +}
 791 +
 792 +
 793 +#define AVALANCHE_MAX_PACING_BLK   3
 794 +#define AVALANCHE_PACING_LOW_VAL   2
 795 +#define AVALANCHE_PACING_HIGH_VAL 63
 796 +
 797 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num,
 798 +                            unsigned int pace_value)
 799 +{
 800 +    unsigned int  blk_offset;
 801 +    unsigned long flags;
 802 +
 803 +    if(irq_nr < MIPS_EXCEPTION_OFFSET &&
 804 +       irq_nr >= AVALANCHE_INT_END_PRIMARY)
 805 +        return (0);
 806 +
 807 +    if(blk_num > AVALANCHE_MAX_PACING_BLK)
 808 +        return(-1);
 809 +
 810 +    if(pace_value > AVALANCHE_PACING_HIGH_VAL &&
 811 +       pace_value < AVALANCHE_PACING_LOW_VAL)
 812 +       return(-1);
 813 +
 814 +    blk_offset = blk_num*8;
 815 +
 816 +    save_and_cli(flags);
 817 +
 818 +    /* disable the interrupt pacing, if enabled previously */
 819 +    avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset);
 820 +
 821 +    /* clear the pacing map */
 822 +    avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset);
 823 +
 824 +    /* setup the new values */
 825 +    avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr))   << blk_offset);
 826 +    avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value)  << blk_offset);
 827 +
 828 +    restore_flags(flags);
 829 +
 830 +    return(0);
 831 +}
 832 diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c
 833 --- linux.old/arch/mips/ar7/memory.c    1970-01-01 01:00:00.000000000 +0100
 834 +++ linux.dev/arch/mips/ar7/memory.c    2005-11-10 01:14:16.372731750 +0100
 835 @@ -0,0 +1,103 @@
 836 +/*
 837 + * Carsten Langgaard, carstenl@mips.com
 838 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
 839 + *
 840 + * ########################################################################
 841 + *
 842 + *  This program is free software; you can distribute it and/or modify it
 843 + *  under the terms of the GNU General Public License (Version 2) as
 844 + *  published by the Free Software Foundation.
 845 + *
 846 + *  This program is distributed in the hope it will be useful, but WITHOUT
 847 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 848 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 849 + *  for more details.
 850 + *
 851 + *  You should have received a copy of the GNU General Public License along
 852 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 853 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 854 + *
 855 + * ########################################################################
 856 + *
 857 + */
 858 +
 859 +#include <linux/config.h>
 860 +#include <linux/init.h>
 861 +#include <linux/mm.h>
 862 +#include <linux/bootmem.h>
 863 +
 864 +#include <asm/bootinfo.h>
 865 +#include <asm/page.h>
 866 +#include <asm/mips-boards/prom.h>
 867 +
 868 +extern char _ftext;
 869 +extern int preserve_adam2;
 870 +
 871 +void __init prom_meminit(void)
 872 +{
 873 +       char *memsize_str;
 874 +       unsigned long memsize, adam2size;
 875 +
 876 +       /* assume block before kernel is used by bootloader */
 877 +       adam2size = __pa(&_ftext) - PHYS_OFFSET;
 878 +
 879 +       memsize_str = prom_getenv("memsize");
 880 +       if (!memsize_str) {
 881 +               memsize = 0x02000000;
 882 +       } else {
 883 +               memsize = simple_strtol(memsize_str, NULL, 0);
 884 +       }
 885 +
 886 +#if 0
 887 +       add_memory_region(0x00000000, PHYS_OFFSET, BOOT_MEM_RESERVED);
 888 +#endif
 889 +       add_memory_region(PHYS_OFFSET, adam2size, BOOT_MEM_ROM_DATA);
 890 +       add_memory_region(PHYS_OFFSET+adam2size, memsize-adam2size,
 891 +                         BOOT_MEM_RAM);
 892 +}
 893 +
 894 +unsigned long __init prom_free_prom_memory (void)
 895 +{
 896 +       int i;
 897 +       unsigned long freed = 0;
 898 +       unsigned long addr;
 899 +
 900 +       if (preserve_adam2) {
 901 +               char *firstfree_str = prom_getenv("firstfreeaddress");
 902 +               unsigned long firstfree = 0;
 903 +
 904 +               if (firstfree_str)
 905 +                       firstfree = simple_strtol(firstfree_str, NULL, 0);
 906 +
 907 +               if (firstfree && firstfree < (unsigned long)&_ftext) {
 908 +                       printk("Preserving ADAM2 memory.\n");
 909 +               } else if (firstfree) {
 910 +                       printk("Can't preserve ADAM2 memory, "
 911 +                              "firstfreeaddress = %08lx.\n", firstfree);
 912 +                       preserve_adam2 = 0;
 913 +               } else {
 914 +                       printk("Can't preserve ADAM2 memory, "
 915 +                              "firstfreeaddress unknown!\n");
 916 +                       preserve_adam2 = 0;
 917 +               }
 918 +       }
 919 +
 920 +       if (!preserve_adam2) {
 921 +               for (i = 0; i < boot_mem_map.nr_map; i++) {
 922 +                       if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
 923 +                               continue;
 924 +
 925 +                       addr = boot_mem_map.map[i].addr;
 926 +                       while (addr < boot_mem_map.map[i].addr
 927 +                               + boot_mem_map.map[i].size) {
 928 +                               ClearPageReserved(virt_to_page(__va(addr)));
 929 +                               set_page_count(virt_to_page(__va(addr)), 1);
 930 +                               free_page((unsigned long)__va(addr));
 931 +                               addr += PAGE_SIZE;
 932 +                               freed += PAGE_SIZE;
 933 +                       }
 934 +               }
 935 +               printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
 936 +       }
 937 +       return freed >> PAGE_SHIFT;
 938 +}
 939 diff -urN linux.old/arch/mips/ar7/misc.c linux.dev/arch/mips/ar7/misc.c
 940 --- linux.old/arch/mips/ar7/misc.c      1970-01-01 01:00:00.000000000 +0100
 941 +++ linux.dev/arch/mips/ar7/misc.c      2005-11-10 01:12:43.946955500 +0100
 942 @@ -0,0 +1,322 @@
 943 +#include <asm/ar7/sangam.h>
 944 +#include <asm/ar7/avalanche_misc.h>
 945 +#include <linux/module.h>
 946 +#include <linux/spinlock.h>
 947 +
 948 +#define TRUE 1
 949 +
 950 +static unsigned int avalanche_vbus_freq;
 951 +
 952 +REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL;
 953 +
 954 +/*****************************************************************************
 955 + * Reset Control Module.
 956 + *****************************************************************************/
 957 +void avalanche_reset_ctrl(unsigned int module_reset_bit,
 958 +                          AVALANCHE_RESET_CTRL_T reset_ctrl)
 959 +{
 960 +    volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
 961 +
 962 +    if(module_reset_bit >= 32 && module_reset_bit < 64)
 963 +        return;
 964 +
 965 +    if(module_reset_bit >= 64)
 966 +    {
 967 +        if(p_remote_vlynq_dev_reset_ctrl) {
 968 +            p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl);
 969 +           return;
 970 +       }
 971 +        else
 972 +            return;
 973 +    }
 974 +
 975 +    if(reset_ctrl == OUT_OF_RESET)
 976 +        *reset_reg |= 1 << module_reset_bit;
 977 +    else
 978 +        *reset_reg &= ~(1 << module_reset_bit);
 979 +    return;
 980 +}
 981 +
 982 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit)
 983 +{
 984 +    volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
 985 +
 986 +    return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET );
 987 +}
 988 +
 989 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode)
 990 +{
 991 +    volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR;
 992 +    *sw_reset_reg =  mode;
 993 +}
 994 +
 995 +#define AVALANCHE_RST_CTRL_RSR_MASK 0x3
 996 +
 997 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status()
 998 +{
 999 +    volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR;
1000 +
1001 +    return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) );
1002 +}
1003 +
1004 +
1005 +/*****************************************************************************
1006 + * Power Control Module
1007 + *****************************************************************************/
1008 +#define AVALANCHE_GLOBAL_POWER_DOWN_MASK    0x3FFFFFFF      /* bit 31, 30 masked */
1009 +#define AVALANCHE_GLOBAL_POWER_DOWN_BIT     30              /* shift to bit 30, 31 */
1010 +
1011 +
1012 +void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl)
1013 +{
1014 +    volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1015 +
1016 +    if (power_ctrl == POWER_CTRL_POWER_DOWN)
1017 +        /* power down the module */
1018 +        *power_reg |= (1 << module_power_bit);
1019 +    else
1020 +        /* power on the module */
1021 +        *power_reg &= (~(1 << module_power_bit));
1022 +}
1023 +
1024 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit)
1025 +{
1026 +    volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1027 +
1028 +    return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP);
1029 +}
1030 +
1031 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode)
1032 +{
1033 +    volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1034 +
1035 +    *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK;
1036 +    *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT);
1037 +}
1038 +
1039 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void)
1040 +{
1041 +    volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1042 +
1043 +    return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK))
1044 +                                           >> AVALANCHE_GLOBAL_POWER_DOWN_BIT));
1045 +}
1046 +
1047 +/*****************************************************************************
1048 + * GPIO  Control
1049 + *****************************************************************************/
1050 +
1051 +/****************************************************************************
1052 + * FUNCTION: avalanche_gpio_init
1053 + ***************************************************************************/
1054 +void avalanche_gpio_init(void)
1055 +{
1056 +    spinlock_t closeLock;
1057 +    unsigned int closeFlag;
1058 +    volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
1059 +    spin_lock_irqsave(&closeLock, closeFlag);
1060 +    *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT);
1061 +    spin_unlock_irqrestore(&closeLock, closeFlag);
1062 +}
1063 +
1064 +/****************************************************************************
1065 + * FUNCTION: avalanche_gpio_ctrl
1066 + ***************************************************************************/
1067 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
1068 +                        AVALANCHE_GPIO_PIN_MODE_T pin_mode,
1069 +                        AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction)
1070 +{
1071 +    spinlock_t closeLock;
1072 +    unsigned int closeFlag;
1073 +    volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL;
1074 +
1075 +    if(gpio_pin >= 32)
1076 +        return(-1);
1077 +
1078 +    spin_lock_irqsave(&closeLock, closeFlag);
1079 +
1080 +    if(pin_mode == GPIO_PIN)
1081 +    {
1082 +        *gpio_ctrl |= (1 << gpio_pin);
1083 +
1084 +       gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR;
1085 +
1086 +        if(pin_direction == GPIO_INPUT_PIN)
1087 +            *gpio_ctrl |=  (1 << gpio_pin);
1088 +        else
1089 +            *gpio_ctrl &= ~(1 << gpio_pin);
1090 +    }
1091 +    else /* FUNCTIONAL PIN */
1092 +    {
1093 +        *gpio_ctrl &= ~(1 << gpio_pin);
1094 +    }
1095 +
1096 +    spin_unlock_irqrestore(&closeLock, closeFlag);
1097 +
1098 +    return (0);
1099 +}
1100 +
1101 +/****************************************************************************
1102 + * FUNCTION: avalanche_gpio_out
1103 + ***************************************************************************/
1104 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value)
1105 +{
1106 +    spinlock_t closeLock;
1107 +    unsigned int closeFlag;
1108 +    volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
1109 +
1110 +    if(gpio_pin >= 32)
1111 +        return(-1);
1112 +
1113 +    spin_lock_irqsave(&closeLock, closeFlag);
1114 +    if(value == TRUE)
1115 +        *gpio_out |= 1 << gpio_pin;
1116 +    else
1117 +       *gpio_out &= ~(1 << gpio_pin);
1118 +    spin_unlock_irqrestore(&closeLock, closeFlag);
1119 +
1120 +    return(0);
1121 +}
1122 +
1123 +/****************************************************************************
1124 + * FUNCTION: avalanche_gpio_in
1125 + ***************************************************************************/
1126 +int avalanche_gpio_in_bit(unsigned int gpio_pin)
1127 +{
1128 +    spinlock_t closeLock;
1129 +    unsigned int closeFlag;
1130 +    volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
1131 +    int ret_val = 0;
1132 +
1133 +    if(gpio_pin >= 32)
1134 +        return(-1);
1135 +
1136 +    spin_lock_irqsave(&closeLock, closeFlag);
1137 +    ret_val = ((*gpio_in) & (1 << gpio_pin));
1138 +    spin_unlock_irqrestore(&closeLock, closeFlag);
1139 +
1140 +    return (ret_val);
1141 +}
1142 +
1143 +/****************************************************************************
1144 + * FUNCTION: avalanche_gpio_out_val
1145 + ***************************************************************************/
1146 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask,
1147 +                           unsigned int reg_index)
1148 +{
1149 +    spinlock_t closeLock;
1150 +    unsigned int closeFlag;
1151 +    volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
1152 +
1153 +    if(reg_index > 0)
1154 +        return(-1);
1155 +
1156 +    spin_lock_irqsave(&closeLock, closeFlag);
1157 +    *gpio_out &= ~out_mask;
1158 +    *gpio_out |= out_val;
1159 +    spin_unlock_irqrestore(&closeLock, closeFlag);
1160 +
1161 +    return(0);
1162 +}
1163 +
1164 +/****************************************************************************
1165 + * FUNCTION: avalanche_gpio_in_value
1166 + ***************************************************************************/
1167 +int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index)
1168 +{
1169 +    spinlock_t closeLock;
1170 +    unsigned int closeFlag;
1171 +    volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
1172 +
1173 +    if(reg_index > 0)
1174 +        return(-1);
1175 +
1176 +    spin_lock_irqsave(&closeLock, closeFlag);
1177 +    *in_val = *gpio_in;
1178 +    spin_unlock_irqrestore(&closeLock, closeFlag);
1179 +
1180 +    return (0);
1181 +}
1182 +
1183 +/***********************************************************************
1184 + *
1185 + *    Wakeup Control Module for TNETV1050 Communication Processor
1186 + *
1187 + ***********************************************************************/
1188 +
1189 +#define AVALANCHE_WAKEUP_POLARITY_BIT   16
1190 +
1191 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
1192 +                           AVALANCHE_WAKEUP_CTRL_T      wakeup_ctrl,
1193 +                           AVALANCHE_WAKEUP_POLARITY_T  wakeup_polarity)
1194 +{
1195 +    volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR;
1196 +
1197 +    /* enable/disable */
1198 +    if (wakeup_ctrl == WAKEUP_ENABLED)
1199 +        /* enable wakeup */
1200 +        *wakeup_status_reg |= wakeup_int;
1201 +    else
1202 +        /* disable wakeup */
1203 +        *wakeup_status_reg &= (~wakeup_int);
1204 +
1205 +    /* set polarity */
1206 +    if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
1207 +        *wakeup_status_reg |=  (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
1208 +    else
1209 +        *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
1210 +}
1211 +
1212 +void avalanche_set_vbus_freq(unsigned int new_vbus_freq)
1213 +{
1214 +    avalanche_vbus_freq = new_vbus_freq;
1215 +}
1216 +
1217 +unsigned int avalanche_get_vbus_freq()
1218 +{
1219 +    return(avalanche_vbus_freq);
1220 +}
1221 +
1222 +unsigned int avalanche_get_chip_version_info()
1223 +{
1224 +    return(*(volatile unsigned int*)AVALANCHE_CVR);
1225 +}
1226 +
1227 +SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL;
1228 +
1229 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)
1230 +{
1231 +    if(p_set_mdix_on_chip_fn)
1232 +        return (p_set_mdix_on_chip_fn(base_addr, operation));
1233 +    else
1234 +        return(-1);
1235 +}
1236 +
1237 +unsigned int avalanche_is_mdix_on_chip(void)
1238 +{
1239 +    return(p_set_mdix_on_chip_fn ? 1:0);
1240 +}
1241 +
1242 +EXPORT_SYMBOL(avalanche_reset_ctrl);
1243 +EXPORT_SYMBOL(avalanche_get_reset_status);
1244 +EXPORT_SYMBOL(avalanche_sys_reset);
1245 +EXPORT_SYMBOL(avalanche_get_sys_last_reset_status);
1246 +EXPORT_SYMBOL(avalanche_power_ctrl);
1247 +EXPORT_SYMBOL(avalanche_get_power_status);
1248 +EXPORT_SYMBOL(avalanche_set_global_power_mode);
1249 +EXPORT_SYMBOL(avalanche_get_global_power_mode);
1250 +EXPORT_SYMBOL(avalanche_set_mdix_on_chip);
1251 +EXPORT_SYMBOL(avalanche_is_mdix_on_chip);
1252 +
1253 +EXPORT_SYMBOL(avalanche_gpio_init);
1254 +EXPORT_SYMBOL(avalanche_gpio_ctrl);
1255 +EXPORT_SYMBOL(avalanche_gpio_out_bit);
1256 +EXPORT_SYMBOL(avalanche_gpio_in_bit);
1257 +EXPORT_SYMBOL(avalanche_gpio_out_value);
1258 +EXPORT_SYMBOL(avalanche_gpio_in_value);
1259 +
1260 +EXPORT_SYMBOL(avalanche_set_vbus_freq);
1261 +EXPORT_SYMBOL(avalanche_get_vbus_freq);
1262 +
1263 +EXPORT_SYMBOL(avalanche_get_chip_version_info);
1264 +
1265 diff -urN linux.old/arch/mips/ar7/platform.h linux.dev/arch/mips/ar7/platform.h
1266 --- linux.old/arch/mips/ar7/platform.h  1970-01-01 01:00:00.000000000 +0100
1267 +++ linux.dev/arch/mips/ar7/platform.h  2005-11-10 01:10:45.799571750 +0100
1268 @@ -0,0 +1,65 @@
1269 +#ifndef _PLATFORM_H_
1270 +#define _PLATFORM_H_
1271 +
1272 +#include <linux/config.h>
1273 +
1274 +
1275 +/* Important: The definition of ENV_SPACE_SIZE should match with that in
1276 + * PSPBoot. (/psp_boot/inc/psbl/env.h)
1277 + */
1278 +#ifdef CONFIG_MIPS_AVALANCHE_TICFG
1279 +#define ENV_SPACE_SIZE      (10 * 1024)
1280 +#endif
1281 +
1282 +#ifdef CONFIG_MIPS_TNETV1050SDB
1283 +#define TNETV1050SDB
1284 +#define DUAL_FLASH
1285 +#endif
1286 +
1287 +#ifdef CONFIG_MIPS_AR7DB
1288 +#define TNETD73XX_BOARD
1289 +#define AR7DB
1290 +#endif
1291 +
1292 +#ifdef CONFIG_MIPS_AR7RD
1293 +#define TNETD73XX_BOARD
1294 +#define AR7RD
1295 +#endif
1296 +
1297 +#ifdef CONFIG_AR7WRD
1298 +#define TNETD73XX_BOARD
1299 +#define AR7WRD
1300 +#endif
1301 +
1302 +#ifdef CONFIG_MIPS_AR7VWI
1303 +#define TNETD73XX_BOARD
1304 +#define AR7VWi
1305 +#endif
1306 +
1307 +/* Merging from the DEV_DSL-PSPL4.3.2.7_Patch release. */
1308 +#ifdef CONFIG_MIPS_AR7VW
1309 +#define TNETD73XX_BOARD
1310 +#define AR7WRD
1311 +#endif
1312 +
1313 +#ifdef CONFIG_MIPS_AR7WI
1314 +#define TNETD73XX_BOARD
1315 +#define AR7Wi
1316 +#endif
1317 +
1318 +#ifdef CONFIG_MIPS_AR7V
1319 +#define TNETD73XX_BOARD
1320 +#define AR7V
1321 +#endif
1322 +
1323 +#ifdef CONFIG_MIPS_AR7V
1324 +#define TNETD73XX_BOARD
1325 +#define AR7V
1326 +#endif
1327 +
1328 +#ifdef CONFIG_MIPS_WA1130
1329 +#define AVALANCHE
1330 +#define WLAN
1331 +#endif
1332 +
1333 +#endif
1334 diff -urN linux.old/arch/mips/ar7/promlib.c linux.dev/arch/mips/ar7/promlib.c
1335 --- linux.old/arch/mips/ar7/promlib.c   1970-01-01 01:00:00.000000000 +0100
1336 +++ linux.dev/arch/mips/ar7/promlib.c   2005-11-10 01:14:16.372731750 +0100
1337 @@ -0,0 +1,48 @@
1338 +/*
1339 + * Carsten Langgaard, carstenl@mips.com
1340 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
1341 + *
1342 + *  This program is free software; you can distribute it and/or modify it
1343 + *  under the terms of the GNU General Public License (Version 2) as
1344 + *  published by the Free Software Foundation.
1345 + *
1346 + *  This program is distributed in the hope it will be useful, but WITHOUT
1347 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1348 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1349 + *  for more details.
1350 + *
1351 + *  You should have received a copy of the GNU General Public License along
1352 + *  with this program; if not, write to the Free Software Foundation, Inc.,
1353 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1354 + *
1355 + * Putting things on the screen/serial line using Adam2 facilities.
1356 + */
1357 +
1358 +#include <linux/types.h>
1359 +#include <asm/addrspace.h>
1360 +
1361 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
1362 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR \
1363 +          (AVALANCHE_YAMON_FUNCTION_BASE + 1 * 0x4)
1364 +#define AVALANCHE_YAMON_PROM_EXIT \
1365 +          (AVALANCHE_YAMON_FUNCTION_BASE + 8 * 0x4)
1366 +
1367 +void prom_putchar(char c)
1368 +{
1369 +       static char buf[1];
1370 +       void (*prom_print_str)(unsigned int dummy, char *s, int len) =
1371 +         (void *)(*(uint32_t *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR);
1372 +
1373 +       buf[0] = c;
1374 +       prom_print_str(1, buf, 1);
1375 +       return;
1376 +}
1377 +
1378 +void adam2_exit(int retval)
1379 +{
1380 +       void (*yamon_exit)(int retval) =
1381 +         (void *)(*(uint32_t *)AVALANCHE_YAMON_PROM_EXIT);
1382 +
1383 +       yamon_exit(retval);
1384 +       return;
1385 +}
1386 diff -urN linux.old/arch/mips/ar7/psp_env.c linux.dev/arch/mips/ar7/psp_env.c
1387 --- linux.old/arch/mips/ar7/psp_env.c   1970-01-01 01:00:00.000000000 +0100
1388 +++ linux.dev/arch/mips/ar7/psp_env.c   2005-11-10 01:10:45.799571750 +0100
1389 @@ -0,0 +1,350 @@
1390 +#include <linux/config.h>
1391 +#include <linux/init.h>
1392 +#include <linux/string.h>
1393 +#include <linux/kernel.h>
1394 +#include <linux/module.h>
1395 +#include <asm/io.h>
1396 +
1397 +#include "platform.h"
1398 +
1399 +#define ENV_CELL_SIZE           16
1400 +
1401 +/* control field decode */
1402 +#define ENV_GARBAGE_BIT                 0x01    /* Env is garbage if this bit is off */
1403 +#define ENV_DYNAMIC_BIT                 0x02    /* Env is dynamic if this bit is off */
1404 +
1405 +#define ENV_CTRL_MASK                   0x03
1406 +#define ENV_PREFINED                    (ENV_GARBAGE_BIT | ENV_DYNAMIC_BIT)
1407 +#define ENV_DYNAMIC                     (ENV_GARBAGE_BIT)
1408 +
1409 +struct env_variable {
1410 +    unsigned char   varNum;
1411 +    unsigned char   ctrl;
1412 +    unsigned short  chksum;
1413 +    unsigned char   numCells;
1414 +    unsigned char   data[ENV_CELL_SIZE - 5];    /* The data section starts
1415 +                                                 * here, continues for
1416 +                                                 * numCells.
1417 +                                                 */
1418 +};
1419 +
1420 +extern unsigned int max_env_entry;
1421 +
1422 +/* Internal macros */
1423 +#define get_next_block(var)    ((struct env_variable *)( (char*)(var) + (var)->numCells * ENV_CELL_SIZE))
1424 +
1425 +typedef enum ENV_VARS {
1426 +        env_vars_start = 0,
1427 +        CPUFREQ,
1428 +        MEMSZ,
1429 +        FLASHSZ,
1430 +        MODETTY0,
1431 +        MODETTY1,
1432 +        PROMPT,
1433 +        BOOTCFG,
1434 +        HWA_0,
1435 +#if !defined (AVALANCHE) || defined(TNETC401B)
1436 +        HWA_1,
1437 +#endif
1438 +#if !defined(TNETV1020_BOARD)
1439 +        HWA_RNDIS,
1440 +#endif
1441 +#if defined (TNETD73XX_BOARD)
1442 +        HWA_3,
1443 +#endif
1444 +        IPA,
1445 +        IPA_SVR,
1446 +        BLINE_MAC0,
1447 +#if !defined (AVALANCHE) || defined(TNETC401B)
1448 +        BLINE_MAC1,
1449 +#endif
1450 +#if !defined(TNETV1020_BOARD)
1451 +        BLINE_RNDIS,
1452 +#endif
1453 +#if defined (TNETD73XX_BOARD)
1454 +        BLINE_ATM,
1455 +#endif
1456 +#if !defined(TNETV1020_BOARD)
1457 +        USB_PID,
1458 +        USB_VID,
1459 +        USB_EPPOLLI,
1460 +#endif
1461 +        IPA_GATEWAY,
1462 +        SUBNET_MASK,
1463 +#if defined (TNETV1050_BOARD)
1464 +       BLINE_ESWITCH,
1465 +#endif
1466 +#if !defined(TNETV1020_BOARD)
1467 +       USB_SERIAL,
1468 +       HWA_HRNDIS,      /* Host (PC) side RNDIS address */
1469 +#endif
1470 +       REMOTE_USER,
1471 +       REMOTE_PASS,
1472 +       REMOTE_DIR,
1473 +       SYSFREQ,
1474 +       LINK_TIMEOUT,
1475 +#ifndef AVALANCHE     /* Avalanche boards use only one mac port */
1476 +       MAC_PORT,
1477 +#endif
1478 +       PATH,
1479 +       HOSTNAME,
1480 +#ifdef WLAN
1481 +       HW_REV_MAJOR,
1482 +       HW_REV_MINOR,
1483 +       HW_PATCH,
1484 +       SW_PATCH,
1485 +       SERIAL_NUMBER,
1486 +#endif
1487 +       TFTPCFG,
1488 +#if defined (TNETV1050_BOARD)
1489 +       HWA_ESWITCH,
1490 +#endif
1491 +        /*
1492 +         * Add new env variables here.
1493 +         * NOTE: New environment variables should always be placed at the end, ie
1494 +         *       just before env_vars_end.
1495 +         */
1496 +
1497 +        env_vars_end
1498 +} ENV_VARS;
1499 +
1500 +
1501 +struct env_description {
1502 +        ENV_VARS   idx;
1503 +        char      *nm;
1504 +       char      *alias;
1505 +};
1506 +
1507 +#define ENVSTR(x)         #x
1508 +#define _ENV_ENTRY(x)     {.idx = x, .nm = ENVSTR(x), .alias = NULL}
1509 +
1510 +struct env_description env_ns[] = {
1511 +        _ENV_ENTRY(env_vars_start), /* start. */
1512 +        _ENV_ENTRY(CPUFREQ),
1513 +        _ENV_ENTRY(MEMSZ),
1514 +        _ENV_ENTRY(FLASHSZ),
1515 +        _ENV_ENTRY(MODETTY0),
1516 +        _ENV_ENTRY(MODETTY1),
1517 +        _ENV_ENTRY(PROMPT),
1518 +        _ENV_ENTRY(BOOTCFG),
1519 +        _ENV_ENTRY(HWA_0),
1520 +#if !defined (AVALANCHE) || defined(TNETC401B)
1521 +        _ENV_ENTRY(HWA_1),
1522 +#endif
1523 +#if !defined(TNETV1020_BOARD)
1524 +        _ENV_ENTRY(HWA_RNDIS),
1525 +#endif
1526 +#if defined (TNETD73XX_BOARD)
1527 +        _ENV_ENTRY(HWA_3),
1528 +#endif
1529 +        _ENV_ENTRY(IPA),
1530 +        _ENV_ENTRY(IPA_SVR),
1531 +        _ENV_ENTRY(IPA_GATEWAY),
1532 +        _ENV_ENTRY(SUBNET_MASK),
1533 +        _ENV_ENTRY(BLINE_MAC0),
1534 +#if !defined (AVALANCHE) || defined(TNETC401B)
1535 +        _ENV_ENTRY(BLINE_MAC1),
1536 +#endif
1537 +#if !defined(TNETV1020_BOARD)
1538 +        _ENV_ENTRY(BLINE_RNDIS),
1539 +#endif
1540 +#if defined (TNETD73XX_BOARD)
1541 +        _ENV_ENTRY(BLINE_ATM),
1542 +#endif
1543 +#if !defined(TNETV1020_BOARD)
1544 +        _ENV_ENTRY(USB_PID),
1545 +        _ENV_ENTRY(USB_VID),
1546 +        _ENV_ENTRY(USB_EPPOLLI),
1547 +#endif
1548 +#if defined (TNETV1050_BOARD)
1549 +        _ENV_ENTRY(BLINE_ESWITCH),
1550 +#endif
1551 +#if !defined(TNETV1020_BOARD)
1552 +        _ENV_ENTRY(USB_SERIAL),
1553 +        _ENV_ENTRY(HWA_HRNDIS),
1554 +#endif
1555 +       _ENV_ENTRY(REMOTE_USER),
1556 +       _ENV_ENTRY(REMOTE_PASS),
1557 +       _ENV_ENTRY(REMOTE_DIR),
1558 +       _ENV_ENTRY(SYSFREQ),
1559 +       _ENV_ENTRY(LINK_TIMEOUT),
1560 +#ifndef AVALANCHE       /* Avalanche boards use only one mac port */
1561 +       _ENV_ENTRY(MAC_PORT),
1562 +#endif
1563 +       _ENV_ENTRY(PATH),
1564 +       _ENV_ENTRY(HOSTNAME),
1565 +#ifdef WLAN
1566 +       _ENV_ENTRY(HW_REV_MAJOR),
1567 +       _ENV_ENTRY(HW_REV_MINOR),
1568 +       _ENV_ENTRY(HW_PATCH),
1569 +       _ENV_ENTRY(SW_PATCH),
1570 +       _ENV_ENTRY(SERIAL_NUMBER),
1571 +#endif
1572 +       _ENV_ENTRY(TFTPCFG),
1573 +#if defined (TNETV1050_BOARD)
1574 +       _ENV_ENTRY(HWA_ESWITCH),
1575 +#endif
1576 +        /*
1577 +         * Add new entries below this.
1578 +         */
1579 +       /* Adam2 environment name alias. */
1580 +       { .idx = IPA,      .nm = "my_ipaddress" },
1581 +       { .idx = CPUFREQ,  .nm = "cpufrequency" },
1582 +       { .idx = SYSFREQ,  .nm = "sysfrequency" },
1583 +       { .idx = HWA_0,    .nm = "maca" },
1584 +#ifndef AVALANCHE
1585 +       { .idx = HWA_1,    .nm = "macb" },
1586 +#endif
1587 +        { .idx = MODETTY0, .nm = "modetty0" },
1588 +        { .idx = MODETTY1, .nm = "modetty1" },
1589 +       { .idx = MEMSZ,    .nm = "memsize" },
1590 +
1591 +        _ENV_ENTRY(env_vars_end) /* delimiter. */
1592 +};
1593 +
1594 +static inline int var_to_idx(const char* var)
1595 +{
1596 +       int ii;
1597 +
1598 +       /* go over the list of pre-defined environment variables */
1599 +        for (ii = env_vars_start; env_ns[ii].idx != env_vars_end; ii++){
1600 +               /* check if the env variable is listed */
1601 +                if (strcmp(env_ns[ii].nm, var) == 0) {
1602 +                               return env_ns[ii].idx;
1603 +               }
1604 +
1605 +               /* if an alias is present, check if the alias matches
1606 +                * the description
1607 +                */
1608 +               if (env_ns[ii].alias != NULL) {
1609 +                       if (strcmp(env_ns[ii].alias, var) == 0) {
1610 +                               return env_ns[ii].idx;
1611 +                       }
1612 +               }
1613 +       }
1614 +       return 0;
1615 +}
1616 +
1617 +extern int *_prom_envp;
1618 +
1619 +/* FIXME: reading from the flash is extremly unstable. Sometime a read returns garbage,
1620 + *        the next read some seconds later is ok. It looks like something is hidding or
1621 + *        overlay the flash address at 0xb0000000. Is this possible?
1622 + *
1623 + *        The readb() and while() usage below is a attempt of a workarround - with limited success.
1624 + */
1625 +
1626 +static inline struct env_variable* get_var_by_number(int index)
1627 +{
1628 +       struct env_variable *env_var = (struct env_variable *)_prom_envp;
1629 +       volatile unsigned char nr;
1630 +       int i;
1631 +
1632 +       env_var++;              /* skip signature */
1633 +
1634 +       i = 0;
1635 +       nr = readb(&(env_var->varNum));
1636 +
1637 +       while (i < max_env_entry && nr != 0xFF) {
1638 +               if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_PREFINED) {
1639 +                       if (nr == index) {
1640 +                               return env_var;
1641 +                       }
1642 +               }
1643 +               i++;
1644 +               env_var = get_next_block(env_var);
1645 +               nr = readb(&(env_var->varNum));
1646 +        }
1647 +
1648 +       return NULL;
1649 +}
1650 +
1651 +static inline struct env_variable* get_var_by_name(char *var)
1652 +{
1653 +       struct env_variable *env_var = (struct env_variable *)_prom_envp;
1654 +       volatile unsigned char nr;
1655 +       int i;
1656 +
1657 +       env_var++;              /* skip signature */
1658 +
1659 +       nr = readb(&(env_var->varNum));
1660 +       i = 0;
1661 +
1662 +       while (i < max_env_entry && nr != 0xFF) {
1663 +               if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
1664 +                       if (strcmp(var, env_var->data) == 0)
1665 +                               return env_var;
1666 +               }
1667 +               i++;
1668 +               env_var = get_next_block(env_var);
1669 +               nr = readb(&(env_var->varNum));
1670 +        }
1671 +       return NULL;
1672 +}
1673 +
1674 +static inline struct env_variable* get_var(char *var)
1675 +{
1676 +       int index = var_to_idx(var);
1677 +
1678 +       if (index)
1679 +               return get_var_by_number(index);
1680 +       else
1681 +               return get_var_by_name(var);
1682 +
1683 +       return NULL;
1684 +}
1685 +
1686 +static inline char *get_value(struct env_variable* env_var)
1687 +{
1688 +       unsigned char *name;
1689 +       unsigned char *value;
1690 +       unsigned short chksum;
1691 +       int i;
1692 +
1693 +       chksum = env_var->varNum + env_var->ctrl + env_var->numCells;
1694 +
1695 +       if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
1696 +               name  = env_var->data;
1697 +               value = env_var->data + strlen(name) + 1;
1698 +
1699 +               for(i = 0; i < strlen(name); i++)
1700 +                       chksum += name[i];
1701 +       } else
1702 +               value = env_var->data;
1703 +
1704 +       for (i = 0; i < strlen(value); i++)
1705 +               chksum += value[i];
1706 +
1707 +       chksum += env_var->chksum;
1708 +       chksum = ~(chksum);
1709 +
1710 +       if(chksum != 0) {
1711 +               return NULL;
1712 +       }
1713 +
1714 +       return value;
1715 +}
1716 +
1717 +struct psbl_rec {
1718 +    unsigned int psbl_size;
1719 +    unsigned int env_base;
1720 +    unsigned int env_size;
1721 +    unsigned int ffs_base;
1722 +    unsigned int ffs_size;
1723 +};
1724 +
1725 +char *prom_psp_getenv(char *envname)
1726 +{
1727 +    struct env_variable* env_var;
1728 +    char *value;
1729 +
1730 +    if (strcmp("bootloader", envname) == 0)
1731 +           return "PSPBoot";
1732 +
1733 +    if (!(env_var = get_var(envname)))
1734 +           return NULL;
1735 +
1736 +    value = get_value(env_var);
1737 +
1738 +    return value;
1739 +}
1740 diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c
1741 --- linux.old/arch/mips/ar7/reset.c     1970-01-01 01:00:00.000000000 +0100
1742 +++ linux.dev/arch/mips/ar7/reset.c     2005-11-10 01:14:16.372731750 +0100
1743 @@ -0,0 +1,98 @@
1744 +/*
1745 + * Carsten Langgaard, carstenl@mips.com
1746 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
1747 + *
1748 + * ########################################################################
1749 + *
1750 + *  This program is free software; you can distribute it and/or modify it
1751 + *  under the terms of the GNU General Public License (Version 2) as
1752 + *  published by the Free Software Foundation.
1753 + *
1754 + *  This program is distributed in the hope it will be useful, but WITHOUT
1755 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1756 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1757 + *  for more details.
1758 + *
1759 + *  You should have received a copy of the GNU General Public License along
1760 + *  with this program; if not, write to the Free Software Foundation, Inc.,
1761 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1762 + *
1763 + * ########################################################################
1764 + *
1765 + * Reset the AR7 boards.
1766 + *
1767 + */
1768 +
1769 +#include <linux/init.h>
1770 +#include <linux/kernel.h>
1771 +#include <linux/string.h>
1772 +#include <linux/types.h>
1773 +
1774 +#include <asm/mipsregs.h>
1775 +#include <asm/reboot.h>
1776 +#include <asm/addrspace.h>
1777 +
1778 +int preserve_adam2 = 1;
1779 +
1780 +extern void adam2_exit(int retval);
1781 +
1782 +static void ar7_machine_restart(char *command);
1783 +static void ar7_machine_halt(void);
1784 +static void ar7_machine_power_off(void);
1785 +
1786 +static void ar7_machine_restart(char *command)
1787 +{
1788 +       volatile uint32_t *softres_reg = (void *)(KSEG1ADDR(0x08611600 + 0x4));
1789 +
1790 +       *softres_reg = 1;
1791 +}
1792 +
1793 +static void ar7_machine_halt(void)
1794 +{
1795 +
1796 +       if (preserve_adam2) {
1797 +               set_c0_status(ST0_BEV);
1798 +               adam2_exit(0);
1799 +       } else {
1800 +               /* I'd like to have Alt-SysRq-b work in this state.
1801 +                * What's missing here? The timer interrupt is still running.
1802 +                * Why doesn't the UART work anymore? */
1803 +               while(1) {
1804 +                 __asm__(".set\tmips3\n\t"
1805 +                         "wait\n\t"
1806 +                         ".set\tmips0");
1807 +               }
1808 +       }
1809 +}
1810 +
1811 +static void ar7_machine_power_off(void)
1812 +{
1813 +       volatile uint32_t *power_reg = (void *)(KSEG1ADDR(0x08610A00));
1814 +       uint32_t power_state = *power_reg;
1815 +
1816 +       /* add something to turn LEDs off? */
1817 +
1818 +       power_state &= ~(3 << 30);
1819 +       power_state |=  (3 << 30); /* power down */
1820 +       *power_reg = power_state;
1821 +
1822 +       printk("after power down?\n");
1823 +}
1824 +
1825 +void ar7_reboot_setup(void)
1826 +{
1827 +       _machine_restart = ar7_machine_restart;
1828 +       _machine_halt = ar7_machine_halt;
1829 +       _machine_power_off = ar7_machine_power_off;
1830 +}
1831 +
1832 +static int __init ar7_do_preserve_adam2(char *s)
1833 +{
1834 +       if (!strcmp(s, "no") || !strcmp(s, "0"))
1835 +               preserve_adam2 = 0;
1836 +       else
1837 +               preserve_adam2 = 1;
1838 +        return 1;
1839 +}
1840 +
1841 +__setup("adam2=", ar7_do_preserve_adam2);
1842 diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c
1843 --- linux.old/arch/mips/ar7/setup.c     1970-01-01 01:00:00.000000000 +0100
1844 +++ linux.dev/arch/mips/ar7/setup.c     2005-11-10 01:12:43.946955500 +0100
1845 @@ -0,0 +1,143 @@
1846 +/*
1847 + * Carsten Langgaard, carstenl@mips.com
1848 + * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
1849 + *
1850 + *  This program is free software; you can distribute it and/or modify it
1851 + *  under the terms of the GNU General Public License (Version 2) as
1852 + *  published by the Free Software Foundation.
1853 + *
1854 + *  This program is distributed in the hope it will be useful, but WITHOUT
1855 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1856 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1857 + *  for more details.
1858 + *
1859 + *  You should have received a copy of the GNU General Public License along
1860 + *  with this program; if not, write to the Free Software Foundation, Inc.,
1861 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1862 + */
1863 +
1864 +#include <linux/config.h>
1865 +#include <linux/init.h>
1866 +#include <linux/string.h>
1867 +#include <linux/irq.h>
1868 +
1869 +#include <asm/processor.h>
1870 +#include <asm/irq.h>
1871 +#include <asm/irq_cpu.h>
1872 +#include <asm/time.h>
1873 +#include <asm/mipsregs.h>
1874 +#include <asm/mips-boards/prom.h>
1875 +
1876 +#ifdef CONFIG_KGDB
1877 +extern void rs_kgdb_hook(int);
1878 +extern void breakpoint(void);
1879 +int remote_debug = 0;
1880 +#endif
1881 +
1882 +extern void ar7_reboot_setup(void);
1883 +extern void ar7_irq_init(int);
1884 +extern asmlinkage void ar7IRQ(void);
1885 +
1886 +void ar7_time_init(void)
1887 +{
1888 +  /* XXX runtime */
1889 +  mips_hpt_frequency = CONFIG_AR7_CPU * 500000;
1890 +}
1891 +
1892 +void ar7_timer_setup(struct irqaction *irq)
1893 +{
1894 +  setup_irq(7, irq);
1895 +  set_c0_status(IE_IRQ5);
1896 +}
1897 +
1898 +void __init init_IRQ(void)
1899 +{
1900 +  init_generic_irq();
1901 +  mips_cpu_irq_init(0);
1902 +  ar7_irq_init(8);
1903 +
1904 +  /* Now safe to set the exception vector. */
1905 +  set_except_vector(0, ar7IRQ);
1906 +
1907 +#ifdef CONFIG_KGDB
1908 +  if (remote_debug)
1909 +  {
1910 +    set_debug_traps();
1911 +    breakpoint();
1912 +  }
1913 +#endif
1914 +}
1915 +
1916 +const char *get_system_type(void)
1917 +{
1918 +       return "Texas Instruments AR7";
1919 +}
1920 +
1921 +void __init ar7_setup(void)
1922 +{
1923 +#ifdef CONFIG_KGDB
1924 +       int rs_putDebugChar(char);
1925 +       char rs_getDebugChar(void);
1926 +       extern int (*generic_putDebugChar)(char);
1927 +       extern char (*generic_getDebugChar)(void);
1928 +#endif
1929 +       char *argptr;
1930 +#ifdef CONFIG_SERIAL_CONSOLE
1931 +       argptr = prom_getcmdline();
1932 +       if ((argptr = strstr(argptr, "console=")) == NULL) {
1933 +               char console[20];
1934 +               char *s;
1935 +               int i = 0;
1936 +
1937 +               s = prom_getenv("modetty0");
1938 +               strcpy(console, "38400");
1939 +
1940 +               if (s != NULL) {
1941 +                       while (s[i] >= '0' && s[i] <= '9')
1942 +                               i++;
1943 +
1944 +                       if (i > 0) {
1945 +                               strncpy(console, s, i);
1946 +                               console[i] = 0;
1947 +                       }
1948 +               }
1949 +
1950 +               argptr = prom_getcmdline();
1951 +               strcat(argptr, " console=ttyS0,");
1952 +               strcat(argptr, console);
1953 +       }
1954 +#endif
1955 +
1956 +#ifdef CONFIG_KGDB
1957 +       argptr = prom_getcmdline();
1958 +       if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
1959 +               int line;
1960 +               argptr += strlen("kgdb=ttyS");
1961 +               if (*argptr != '0' && *argptr != '1')
1962 +                       printk("KGDB: Uknown serial line /dev/ttyS%c, "
1963 +                                       "falling back to /dev/ttyS1\n", *argptr);
1964 +               line = *argptr == '0' ? 0 : 1;
1965 +               printk("KGDB: Using serial line /dev/ttyS%d for session\n",
1966 +                               line ? 1 : 0);
1967 +
1968 +               rs_kgdb_hook(line);
1969 +               generic_putDebugChar = rs_putDebugChar;
1970 +               generic_getDebugChar = rs_getDebugChar;
1971 +
1972 +               prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
1973 +                               "please connect your debugger\n", line ? 1 : 0);
1974 +
1975 +               remote_debug = 1;
1976 +               /* Breakpoints are in init_IRQ() */
1977 +       }
1978 +#endif
1979 +
1980 +       argptr = prom_getcmdline();
1981 +       if ((argptr = strstr(argptr, "nofpu")) != NULL)
1982 +               cpu_data[0].options &= ~MIPS_CPU_FPU;
1983 +
1984 +       ar7_reboot_setup();
1985 +
1986 +       board_time_init = ar7_time_init;
1987 +       board_timer_setup = ar7_timer_setup;
1988 +}
1989 diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c
1990 --- linux.old/arch/mips/ar7/tnetd73xx_misc.c    1970-01-01 01:00:00.000000000 +0100
1991 +++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c    2005-11-10 01:12:43.946955500 +0100
1992 @@ -0,0 +1,921 @@
1993 +/******************************************************************************
1994 + * FILE PURPOSE:    TNETD73xx Misc modules API Source
1995 + ******************************************************************************
1996 + * FILE NAME:       tnetd73xx_misc.c
1997 + *
1998 + * DESCRIPTION:     Clock Control, Reset Control, Power Management, GPIO
1999 + *                  FSER Modules API
2000 + *                  As per TNETD73xx specifications
2001 + *
2002 + * REVISION HISTORY:
2003 + * 27 Nov 02 - Sharath Kumar     PSP TII
2004 + * 14 Feb 03 - Anant Gole        PSP TII
2005 + *
2006 + * (C) Copyright 2002, Texas Instruments, Inc
2007 + *******************************************************************************/
2008 +
2009 +#include <linux/types.h>
2010 +#include <asm/ar7/tnetd73xx.h>
2011 +#include <asm/ar7/tnetd73xx_misc.h>
2012 +
2013 +/* TNETD73XX Revision */
2014 +u32 tnetd73xx_get_revision(void)
2015 +{
2016 +       /* Read Chip revision register - This register is from GPIO module */
2017 +       return ( (u32) REG32_DATA(TNETD73XX_CVR));
2018 +}
2019 +
2020 +/*****************************************************************************
2021 + * Reset Control Module
2022 + *****************************************************************************/
2023 +
2024 +
2025 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
2026 +{
2027 +       u32 reset_status;
2028 +
2029 +       /* read current reset register */
2030 +       REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2031 +
2032 +       if (reset_ctrl == OUT_OF_RESET)
2033 +       {
2034 +               /* bring module out of reset */
2035 +               reset_status |= (1 << reset_module);
2036 +       }
2037 +       else
2038 +       {
2039 +               /* put module in reset */
2040 +               reset_status &= (~(1 << reset_module));
2041 +       }
2042 +
2043 +       /* write to the reset register */
2044 +       REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
2045 +}
2046 +
2047 +
2048 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
2049 +{
2050 +       u32 reset_status;
2051 +
2052 +       REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2053 +       return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
2054 +}
2055 +
2056 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
2057 +{
2058 +       REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
2059 +}
2060 +
2061 +#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
2062 +
2063 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
2064 +{
2065 +       u32 sys_reset_status;
2066 +
2067 +       REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
2068 +
2069 +       return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
2070 +}
2071 +
2072 +
2073 +/*****************************************************************************
2074 + * Power Control Module
2075 + *****************************************************************************/
2076 +#define TNETD73XX_GLOBAL_POWER_DOWN_MASK    0x3FFFFFFF      /* bit 31, 30 masked */
2077 +#define TNETD73XX_GLOBAL_POWER_DOWN_BIT     30              /* shift to bit 30, 31 */
2078 +
2079 +
2080 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
2081 +{
2082 +       u32 power_status;
2083 +
2084 +       /* read current power down control register */
2085 +       REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2086 +
2087 +       if (power_ctrl == POWER_CTRL_POWER_DOWN)
2088 +       {
2089 +               /* power down the module */
2090 +               power_status |= (1 << power_module);
2091 +       }
2092 +       else
2093 +       {
2094 +               /* power on the module */
2095 +               power_status &= (~(1 << power_module));
2096 +       }
2097 +
2098 +       /* write to the reset register */
2099 +       REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2100 +}
2101 +
2102 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
2103 +{
2104 +       u32 power_status;
2105 +
2106 +       /* read current power down control register */
2107 +       REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2108 +
2109 +       return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
2110 +}
2111 +
2112 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
2113 +{
2114 +       u32 power_status;
2115 +
2116 +       /* read current power down control register */
2117 +       REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2118 +
2119 +       power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
2120 +       power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2121 +
2122 +       /* write to power down control register */
2123 +       REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2124 +}
2125 +
2126 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
2127 +{
2128 +       u32 power_status;
2129 +
2130 +       /* read current power down control register */
2131 +       REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2132 +
2133 +       power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
2134 +       power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2135 +
2136 +       return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
2137 +}
2138 +
2139 +
2140 +/*****************************************************************************
2141 + * Wakeup Control
2142 + *****************************************************************************/
2143 +
2144 +#define TNETD73XX_WAKEUP_POLARITY_BIT   16
2145 +
2146 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
2147 +               TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
2148 +               TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
2149 +{
2150 +       u32 wakeup_status;
2151 +
2152 +       /* read the wakeup control register */
2153 +       REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2154 +
2155 +       /* enable/disable */
2156 +       if (wakeup_ctrl == WAKEUP_ENABLED)
2157 +       {
2158 +               /* enable wakeup */
2159 +               wakeup_status |= wakeup_int;
2160 +       }
2161 +       else
2162 +       {
2163 +               /* disable wakeup */
2164 +               wakeup_status &= (~wakeup_int);
2165 +       }
2166 +
2167 +       /* set polarity */
2168 +       if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
2169 +       {
2170 +               wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2171 +       }
2172 +       else
2173 +       {
2174 +               wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2175 +       }
2176 +
2177 +       /* write  the wakeup control register */
2178 +       REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2179 +}
2180 +
2181 +
2182 +/*****************************************************************************
2183 + * FSER  Control
2184 + *****************************************************************************/
2185 +
2186 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
2187 +{
2188 +       REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
2189 +}
2190 +
2191 +/*****************************************************************************
2192 + * Clock Control
2193 + *****************************************************************************/
2194 +
2195 +#define MIN(x,y)               ( ((x) <  (y)) ? (x) : (y) )
2196 +#define MAX(x,y)               ( ((x) >  (y)) ? (x) : (y) )
2197 +#define ABS(x)                 ( ((signed)(x) > 0) ? (x) : (-(x)) )
2198 +#define CEIL(x,y)              ( ((x) + (y) / 2) / (y) )
2199 +
2200 +#define CLKC_CLKCR(x)          (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
2201 +#define CLKC_CLKPLLCR(x)       (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
2202 +
2203 +#define CLKC_PRE_DIVIDER        0x0000001F
2204 +#define CLKC_POST_DIVIDER       0x001F0000
2205 +
2206 +#define CLKC_PLL_STATUS         0x1
2207 +#define CLKC_PLL_FACTOR         0x0000F000
2208 +
2209 +#define BOOTCR_PLL_BYPASS       (1 << 5)
2210 +#define BOOTCR_MIPS_ASYNC_MODE  (1 << 25)
2211 +
2212 +#define MIPS_PLL_SELECT         0x00030000
2213 +#define SYSTEM_PLL_SELECT       0x0000C000
2214 +#define USB_PLL_SELECT          0x000C0000
2215 +#define ADSLSS_PLL_SELECT       0x00C00000
2216 +
2217 +#define MIPS_AFECLKI_SELECT     0x00000000
2218 +#define MIPS_REFCLKI_SELECT     0x00010000
2219 +#define MIPS_XTAL3IN_SELECT     0x00020000
2220 +
2221 +#define SYSTEM_AFECLKI_SELECT   0x00000000
2222 +#define SYSTEM_REFCLKI_SELECT   0x00004000
2223 +#define SYSTEM_XTAL3IN_SELECT   0x00008000
2224 +#define SYSTEM_MIPSPLL_SELECT   0x0000C000
2225 +
2226 +#define USB_SYSPLL_SELECT       0x00000000
2227 +#define USB_REFCLKI_SELECT      0x00040000
2228 +#define USB_XTAL3IN_SELECT      0x00080000
2229 +#define USB_MIPSPLL_SELECT      0x000C0000
2230 +
2231 +#define ADSLSS_AFECLKI_SELECT   0x00000000
2232 +#define ADSLSS_REFCLKI_SELECT   0x00400000
2233 +#define ADSLSS_XTAL3IN_SELECT   0x00800000
2234 +#define ADSLSS_MIPSPLL_SELECT   0x00C00000
2235 +
2236 +#define  SYS_MAX                CLK_MHZ(150)
2237 +#define  SYS_MIN                CLK_MHZ(1)
2238 +
2239 +#define  MIPS_SYNC_MAX          SYS_MAX
2240 +#define  MIPS_ASYNC_MAX         CLK_MHZ(160)
2241 +#define  MIPS_MIN               CLK_MHZ(1)
2242 +
2243 +#define  USB_MAX                CLK_MHZ(100)
2244 +#define  USB_MIN                CLK_MHZ(1)
2245 +
2246 +#define  ADSL_MAX               CLK_MHZ(180)
2247 +#define  ADSL_MIN               CLK_MHZ(1)
2248 +
2249 +#define  PLL_MUL_MAXFACTOR      15
2250 +#define  MAX_DIV_VALUE          32
2251 +#define  MIN_DIV_VALUE          1
2252 +
2253 +#define  MIN_PLL_INP_FREQ       CLK_MHZ(8)
2254 +#define  MAX_PLL_INP_FREQ       CLK_MHZ(100)
2255 +
2256 +#define  DIVIDER_LOCK_TIME      10100
2257 +#define  PLL_LOCK_TIME          10100 * 75
2258 +
2259 +
2260 +
2261 +                                                             /****************************************************************************
2262 +                                                              * DATA PURPOSE:    PRIVATE Variables
2263 +                                                              **************************************************************************/
2264 +                                                             static u32 *clk_src[4];
2265 +                                                             static u32 mips_pll_out;
2266 +                                                             static u32 sys_pll_out;
2267 +                                                             static u32 afeclk_inp;
2268 +                                                             static u32 refclk_inp;
2269 +                                                             static u32 xtal_inp;
2270 +                                                             static u32 present_min;
2271 +                                                             static u32 present_max;
2272 +
2273 +                                                             /* Forward References */
2274 +                                                             static u32 find_gcd(u32 min, u32 max);
2275 +                                                             static u32 compute_prediv( u32 divider, u32 min, u32 max);
2276 +                                                             static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
2277 +                                                             static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
2278 +                                                             static void find_approx(u32 *,u32 *,u32);
2279 +
2280 +                                                             /****************************************************************************
2281 +                                                              * FUNCTION: tnetd73xx_clkc_init
2282 +                                                              ****************************************************************************
2283 +                                                              * Description: The routine initializes the internal variables depending on
2284 +                                                              *              on the sources selected for different clocks.
2285 +                                                              ***************************************************************************/
2286 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
2287 +{
2288 +
2289 +       u32 choice;
2290 +
2291 +       afeclk_inp = afeclk;
2292 +       refclk_inp = refclk;
2293 +       xtal_inp = xtal3in;
2294 +
2295 +       choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
2296 +       switch(choice)
2297 +       {
2298 +               case MIPS_AFECLKI_SELECT:
2299 +                       clk_src[CLKC_MIPS] = &afeclk_inp;
2300 +                       break;
2301 +
2302 +               case MIPS_REFCLKI_SELECT:
2303 +                       clk_src[CLKC_MIPS] = &refclk_inp;
2304 +                       break;
2305 +
2306 +               case MIPS_XTAL3IN_SELECT:
2307 +                       clk_src[CLKC_MIPS] = &xtal_inp;
2308 +                       break;
2309 +
2310 +               default :
2311 +                       clk_src[CLKC_MIPS] = 0;
2312 +
2313 +       }
2314 +
2315 +       choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
2316 +       switch(choice)
2317 +       {
2318 +               case SYSTEM_AFECLKI_SELECT:
2319 +                       clk_src[CLKC_SYS] = &afeclk_inp;
2320 +                       break;
2321 +
2322 +               case SYSTEM_REFCLKI_SELECT:
2323 +                       clk_src[CLKC_SYS] = &refclk_inp;
2324 +                       break;
2325 +
2326 +               case SYSTEM_XTAL3IN_SELECT:
2327 +                       clk_src[CLKC_SYS] = &xtal_inp;
2328 +                       break;
2329 +
2330 +               case SYSTEM_MIPSPLL_SELECT:
2331 +                       clk_src[CLKC_SYS] = &mips_pll_out;
2332 +                       break;
2333 +
2334 +               default :
2335 +                       clk_src[CLKC_SYS] = 0;
2336 +
2337 +       }
2338 +
2339 +
2340 +       choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
2341 +       switch(choice)
2342 +       {
2343 +               case ADSLSS_AFECLKI_SELECT:
2344 +                       clk_src[CLKC_ADSLSS] = &afeclk_inp;
2345 +                       break;
2346 +
2347 +               case ADSLSS_REFCLKI_SELECT:
2348 +                       clk_src[CLKC_ADSLSS] = &refclk_inp;
2349 +                       break;
2350 +
2351 +               case ADSLSS_XTAL3IN_SELECT:
2352 +                       clk_src[CLKC_ADSLSS] = &xtal_inp;
2353 +                       break;
2354 +
2355 +               case ADSLSS_MIPSPLL_SELECT:
2356 +                       clk_src[CLKC_ADSLSS] = &mips_pll_out;
2357 +                       break;
2358 +
2359 +               default :
2360 +                       clk_src[CLKC_ADSLSS] = 0;
2361 +
2362 +       }
2363 +
2364 +
2365 +       choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
2366 +       switch(choice)
2367 +       {
2368 +               case USB_SYSPLL_SELECT:
2369 +                       clk_src[CLKC_USB] = &sys_pll_out ;
2370 +                       break;
2371 +
2372 +               case USB_REFCLKI_SELECT:
2373 +                       clk_src[CLKC_USB] = &refclk_inp;
2374 +                       break;
2375 +
2376 +               case USB_XTAL3IN_SELECT:
2377 +                       clk_src[CLKC_USB] = &xtal_inp;
2378 +                       break;
2379 +
2380 +               case USB_MIPSPLL_SELECT:
2381 +                       clk_src[CLKC_USB] = &mips_pll_out;
2382 +                       break;
2383 +
2384 +               default :
2385 +                       clk_src[CLKC_USB] = 0;
2386 +
2387 +       }
2388 +}
2389 +
2390 +
2391 +
2392 +/****************************************************************************
2393 + * FUNCTION: tnetd73xx_clkc_set_freq
2394 + ****************************************************************************
2395 + * Description: The above routine is called to set the output_frequency of the
2396 + *              selected clock(using clk_id) to the  required value given
2397 + *              by the variable output_freq.
2398 + ***************************************************************************/
2399 +TNETD73XX_ERR tnetd73xx_clkc_set_freq
2400 +(
2401 + TNETD73XX_CLKC_ID_T clk_id,
2402 + u32              output_freq
2403 + )
2404 +{
2405 +       u32 base_freq;
2406 +       u32 multiplier;
2407 +       u32 divider;
2408 +       u32 min_prediv;
2409 +       u32 max_prediv;
2410 +       u32 prediv;
2411 +       u32 postdiv;
2412 +       u32 temp;
2413 +
2414 +       /* check if PLLs are bypassed*/
2415 +       if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
2416 +       {
2417 +               return TNETD73XX_ERR_ERROR;
2418 +       }
2419 +
2420 +       /*check if the requested output_frequency is in valid range*/
2421 +       switch( clk_id )
2422 +       {
2423 +               case CLKC_SYS:
2424 +                       if( output_freq < SYS_MIN || output_freq > SYS_MAX)
2425 +                       {
2426 +                               return TNETD73XX_ERR_ERROR;
2427 +                       }
2428 +                       present_min = SYS_MIN;
2429 +                       present_max = SYS_MAX;
2430 +                       break;
2431 +
2432 +               case CLKC_MIPS:
2433 +                       if((output_freq < MIPS_MIN) ||
2434 +                                       (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
2435 +                       {
2436 +                               return TNETD73XX_ERR_ERROR;
2437 +                       }
2438 +                       present_min = MIPS_MIN;
2439 +                       present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
2440 +                       break;
2441 +
2442 +               case CLKC_USB:
2443 +                       if( output_freq < USB_MIN || output_freq > USB_MAX)
2444 +                       {
2445 +                               return TNETD73XX_ERR_ERROR;
2446 +                       }
2447 +                       present_min = USB_MIN;
2448 +                       present_max = USB_MAX;
2449 +                       break;
2450 +
2451 +               case CLKC_ADSLSS:
2452 +                       if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
2453 +                       {
2454 +                               return TNETD73XX_ERR_ERROR;
2455 +                       }
2456 +                       present_min = ADSL_MIN;
2457 +                       present_max = ADSL_MAX;
2458 +                       break;
2459 +       }
2460 +
2461 +
2462 +       base_freq = get_base_frequency(clk_id);
2463 +
2464 +
2465 +       /* check for minimum base frequency value */
2466 +       if( base_freq < MIN_PLL_INP_FREQ)
2467 +       {
2468 +               return TNETD73XX_ERR_ERROR;
2469 +       }
2470 +
2471 +       get_val(output_freq, base_freq, &multiplier, &divider);
2472 +
2473 +       /* check multiplier range  */
2474 +       if( (multiplier  > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
2475 +       {
2476 +               return TNETD73XX_ERR_ERROR;
2477 +       }
2478 +
2479 +       /* check divider value */
2480 +       if( divider == 0 )
2481 +       {
2482 +               return TNETD73XX_ERR_ERROR;
2483 +       }
2484 +
2485 +       /*compute minimum and maximum predivider values */
2486 +       min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
2487 +       max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
2488 +
2489 +       /*adjust  the value of divider so that it not less than minimum predivider value*/
2490 +       if (divider < min_prediv)
2491 +       {
2492 +               temp = CEIL(min_prediv, divider);
2493 +               if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
2494 +               {
2495 +                       return TNETD73XX_ERR_ERROR  ;
2496 +               }
2497 +               else
2498 +               {
2499 +                       multiplier = temp * multiplier;
2500 +                       divider = min_prediv;
2501 +               }
2502 +
2503 +       }
2504 +
2505 +       /* compute predivider  and postdivider values */
2506 +       prediv = compute_prediv (divider, min_prediv, max_prediv);
2507 +       postdiv = CEIL(divider,prediv);
2508 +
2509 +       /*return fail if postdivider value falls out of range */
2510 +       if(postdiv > MAX_DIV_VALUE)
2511 +       {
2512 +               return TNETD73XX_ERR_ERROR;
2513 +       }
2514 +
2515 +
2516 +       /*write predivider and postdivider values*/
2517 +       /* pre-Divider and post-divider are 5 bit N+1 dividers */
2518 +       REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
2519 +
2520 +       /*wait for divider output to stabilise*/
2521 +       for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
2522 +
2523 +       /*write to PLL clock register*/
2524 +
2525 +       if(clk_id == CLKC_SYS)
2526 +       {
2527 +               /* but before writing put DRAM to hold mode */
2528 +               REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
2529 +       }
2530 +       /*Bring PLL into div mode */
2531 +       REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
2532 +
2533 +       /*compute the word to be written to PLLCR
2534 +        *corresponding to multiplier value
2535 +        */
2536 +       multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
2537 +
2538 +       /* wait till PLL enters div mode */
2539 +       while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2540 +               /*nothing*/;
2541 +
2542 +       REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
2543 +
2544 +       while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2545 +               /*nothing*/;
2546 +
2547 +
2548 +       /*wait for External pll to lock*/
2549 +       for(temp =0; temp < PLL_LOCK_TIME; temp++);
2550 +
2551 +       if(clk_id == CLKC_SYS)
2552 +       {
2553 +               /* Bring DRAM out of hold */
2554 +               REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
2555 +       }
2556 +
2557 +       return TNETD73XX_ERR_OK ;
2558 +}
2559 +
2560 +/****************************************************************************
2561 + * FUNCTION: tnetd73xx_clkc_get_freq
2562 + ****************************************************************************
2563 + * Description: The above routine is called to get the output_frequency of the
2564 + *              selected clock( clk_id)
2565 + ***************************************************************************/
2566 +u32 tnetd73xx_clkc_get_freq
2567 +(
2568 + TNETD73XX_CLKC_ID_T clk_id
2569 + )
2570 +{
2571 +
2572 +       u32  clk_ctrl_register;
2573 +       u32  clk_pll_setting;
2574 +       u32  clk_predivider;
2575 +       u32  clk_postdivider;
2576 +       u16  pll_factor;
2577 +       u32  base_freq;
2578 +       u32  divider;
2579 +
2580 +       base_freq = get_base_frequency(clk_id);
2581 +
2582 +       clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
2583 +
2584 +       /* pre-Divider and post-divider are 5 bit N+1 dividers */
2585 +       clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
2586 +       clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
2587 +
2588 +       divider =  clk_predivider * clk_postdivider;
2589 +
2590 +
2591 +       if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
2592 +       {
2593 +               return (CEIL(base_freq, divider));  /* PLLs bypassed.*/
2594 +       }
2595 +
2596 +
2597 +       else
2598 +       {
2599 +               /*  return the current clock speed based upon the PLL setting */
2600 +               clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
2601 +
2602 +               /* Get the PLL multiplication factor */
2603 +               pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
2604 +
2605 +               /* Check if we're in divide mode or multiply mode */
2606 +               if((clk_pll_setting & 0x1)   == 0)
2607 +               {
2608 +                       /* We're in divide mode */
2609 +                       if(pll_factor <  0x10)
2610 +                               return (CEIL(base_freq >> 1, divider));
2611 +                       else
2612 +                               return (CEIL(base_freq >> 2, divider));
2613 +               }
2614 +
2615 +               else     /* We're in PLL mode */
2616 +               {
2617 +                       /* See if PLLNDIV & PLLDIV are set */
2618 +                       if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
2619 +                       {
2620 +                               if(clk_pll_setting & 0x1000)
2621 +                               {
2622 +                                       /* clk = base_freq * k/2  */
2623 +                                       return(CEIL((base_freq * pll_factor) >> 1, divider));
2624 +                               }
2625 +                               else
2626 +                               {
2627 +                                       /* clk = base_freq * (k-1) / 4)*/
2628 +                                       return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
2629 +                               }
2630 +                       }
2631 +                       else
2632 +                       {
2633 +                               if(pll_factor < 0x10)
2634 +                               {
2635 +                                       /* clk = base_freq * k */
2636 +                                       return(CEIL(base_freq * pll_factor, divider));
2637 +                               }
2638 +
2639 +                               else
2640 +                               {
2641 +                                       /* clk = base_freq  */
2642 +                                       return(CEIL(base_freq, divider));
2643 +                               }
2644 +                       }
2645 +               }
2646 +               return(0); /* Should never reach here */
2647 +
2648 +       }
2649 +
2650 +}
2651 +
2652 +
2653 +/* local helper functions */
2654 +
2655 +/****************************************************************************
2656 + * FUNCTION: get_base_frequency
2657 + ****************************************************************************
2658 + * Description: The above routine is called to get base frequency of the clocks.
2659 + ***************************************************************************/
2660 +
2661 +static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
2662 +{
2663 +       /* update the current MIPs PLL output value, if the required
2664 +        * source is MIPS PLL
2665 +        */
2666 +       if ( clk_src[clk_id] == &mips_pll_out)
2667 +       {
2668 +               *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
2669 +       }
2670 +
2671 +
2672 +       /* update the current System PLL output value, if the required
2673 +        * source is system PLL
2674 +        */
2675 +       if ( clk_src[clk_id] == &sys_pll_out)
2676 +       {
2677 +               *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
2678 +       }
2679 +
2680 +       return (*clk_src[clk_id]);
2681 +
2682 +}
2683 +
2684 +
2685 +
2686 +/****************************************************************************
2687 + * FUNCTION: find_gcd
2688 + ****************************************************************************
2689 + * Description: The above routine is called to find gcd of 2 numbers.
2690 + ***************************************************************************/
2691 +static u32 find_gcd
2692 +(
2693 + u32 min,
2694 + u32 max
2695 + )
2696 +{
2697 +       if (max % min == 0)
2698 +       {
2699 +               return min;
2700 +       }
2701 +       else
2702 +       {
2703 +               return find_gcd(max % min, min);
2704 +       }
2705 +}
2706 +
2707 +/****************************************************************************
2708 + * FUNCTION: compute_prediv
2709 + ****************************************************************************
2710 + * Description: The above routine is called to compute predivider value
2711 + ***************************************************************************/
2712 +static u32 compute_prediv(u32 divider, u32 min, u32 max)
2713 +{
2714 +       u16 prediv;
2715 +
2716 +       /* return the divider itself it it falls within the range of predivider*/
2717 +       if (min <= divider && divider <= max)
2718 +       {
2719 +               return divider;
2720 +       }
2721 +
2722 +       /* find a value for prediv such that it is a factor of divider */
2723 +       for (prediv = max; prediv >= min ; prediv--)
2724 +       {
2725 +               if ( (divider % prediv) == 0 )
2726 +               {
2727 +                       return prediv;
2728 +               }
2729 +       }
2730 +
2731 +       /* No such factor exists,  return min as prediv */
2732 +       return min;
2733 +}
2734 +
2735 +/****************************************************************************
2736 + * FUNCTION: get_val
2737 + ****************************************************************************
2738 + * Description: This routine is called to get values of divider and multiplier.
2739 + ***************************************************************************/
2740 +
2741 +static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
2742 +{
2743 +       u32 temp_mul;
2744 +       u32 temp_div;
2745 +       u32 gcd;
2746 +       u32 min_freq;
2747 +       u32 max_freq;
2748 +
2749 +       /* find gcd of base_freq, output_freq */
2750 +       min_freq = (base_freq < output_freq) ? base_freq : output_freq;
2751 +       max_freq = (base_freq > output_freq) ? base_freq : output_freq;
2752 +       gcd = find_gcd(min_freq , max_freq);
2753 +
2754 +       if(gcd == 0)
2755 +               return;  /* ERROR */
2756 +
2757 +       /* compute values of multiplier and divider */
2758 +       temp_mul = output_freq / gcd;
2759 +       temp_div = base_freq / gcd;
2760 +
2761 +
2762 +       /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
2763 +       if( temp_mul > PLL_MUL_MAXFACTOR )
2764 +       {
2765 +               if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
2766 +                       return;
2767 +
2768 +               find_approx(&temp_mul,&temp_div,base_freq);
2769 +       }
2770 +
2771 +       *multiplier = temp_mul;
2772 +       *divider    = temp_div;
2773 +}
2774 +
2775 +/****************************************************************************
2776 + * FUNCTION: find_approx
2777 + ****************************************************************************
2778 + * Description: This function gets the approx value of num/denom.
2779 + ***************************************************************************/
2780 +
2781 +static void find_approx(u32 *num,u32 *denom,u32 base_freq)
2782 +{
2783 +       u32 num1;
2784 +       u32 denom1;
2785 +       u32 num2;
2786 +       u32 denom2;
2787 +       int32_t closest;
2788 +       int32_t prev_closest;
2789 +       u32 temp_num;
2790 +       u32 temp_denom;
2791 +       u32 normalize;
2792 +       u32 gcd;
2793 +       u32 output_freq;
2794 +
2795 +       num1 = *num;
2796 +       denom1 = *denom;
2797 +
2798 +       prev_closest = 0x7fffffff; /* maximum possible value */
2799 +       num2 = num1;
2800 +       denom2 = denom1;
2801 +
2802 +       /* start with  max */
2803 +       for(temp_num = 15; temp_num >=1; temp_num--)
2804 +       {
2805 +
2806 +               temp_denom = CEIL(temp_num * denom1, num1);
2807 +               output_freq = (temp_num * base_freq) / temp_denom;
2808 +
2809 +               if(temp_denom < 1)
2810 +               {
2811 +                       break;
2812 +               }
2813 +               else
2814 +               {
2815 +                       normalize = CEIL(num1,temp_num);
2816 +                       closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1)))  * normalize;
2817 +                       if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
2818 +                       {
2819 +                               prev_closest = closest;
2820 +                               num2 = temp_num;
2821 +                               denom2 = temp_denom;
2822 +                       }
2823 +
2824 +               }
2825 +
2826 +       }
2827 +
2828 +       gcd = find_gcd(num2,denom2);
2829 +       num2 = num2 / gcd;
2830 +       denom2 = denom2 /gcd;
2831 +
2832 +       *num      = num2;
2833 +       *denom    = denom2;
2834 +}
2835 +
2836 +
2837 +/*****************************************************************************
2838 + * GPIO  Control
2839 + *****************************************************************************/
2840 +
2841 +/****************************************************************************
2842 + * FUNCTION: tnetd73xx_gpio_init
2843 + ***************************************************************************/
2844 +void tnetd73xx_gpio_init()
2845 +{
2846 +       /* Bring module out of reset */
2847 +       tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
2848 +       REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
2849 +}
2850 +
2851 +/****************************************************************************
2852 + * FUNCTION: tnetd73xx_gpio_ctrl
2853 + ***************************************************************************/
2854 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
2855 +               TNETD73XX_GPIO_PIN_MODE_T pin_mode,
2856 +               TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
2857 +{
2858 +       u32 pin_status;
2859 +       REG32_READ(TNETD73XX_GPIOENR, pin_status);
2860 +       if (pin_mode == GPIO_PIN)
2861 +       {
2862 +               pin_status |= (1 << gpio_pin);
2863 +               REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2864 +
2865 +               /* Set pin direction */
2866 +               REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
2867 +               if (pin_direction == GPIO_INPUT_PIN)
2868 +               {
2869 +                       pin_status |= (1 << gpio_pin);
2870 +               }
2871 +               else /* GPIO_OUTPUT_PIN */
2872 +               {
2873 +                       pin_status &= (~(1 << gpio_pin));
2874 +               }
2875 +               REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
2876 +       }
2877 +       else /* FUNCTIONAL PIN */
2878 +       {
2879 +               pin_status &= (~(1 << gpio_pin));
2880 +               REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2881 +       }
2882 +
2883 +}
2884 +
2885 +/****************************************************************************
2886 + * FUNCTION: tnetd73xx_gpio_out
2887 + ***************************************************************************/
2888 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
2889 +{
2890 +       u32 pin_value;
2891 +
2892 +       REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
2893 +       if (value == 1)
2894 +       {
2895 +               pin_value |= (1 << gpio_pin);
2896 +       }
2897 +       else
2898 +       {
2899 +               pin_value &= (~(1 << gpio_pin));
2900 +       }
2901 +       REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
2902 +}
2903 +
2904 +/****************************************************************************
2905 + * FUNCTION: tnetd73xx_gpio_in
2906 + ***************************************************************************/
2907 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
2908 +{
2909 +       u32 pin_value;
2910 +       REG32_READ(TNETD73XX_GPIODINR, pin_value);
2911 +       return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
2912 +}
2913 +
2914 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
2915 --- linux.old/arch/mips/config-shared.in        2005-10-21 16:43:18.917114000 +0200
2916 +++ linux.dev/arch/mips/config-shared.in        2005-11-10 01:12:43.950955750 +0100
2917 @@ -20,6 +20,16 @@
2918  mainmenu_option next_comment
2919  comment 'Machine selection'
2920  dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
2921 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
2922 +if [ "$CONFIG_AR7" = "y" ]; then
2923 +   choice 'Texas Instruments Reference Platform' \
2924 +      "AR7DB CONFIG_AR7DB \
2925 +      AR7RD CONFIG_AR7RD \
2926 +      AR7WRD CONFIG_AR7WRD" AR7DB
2927 +   int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_CPU 150
2928 +   int 'Texas Instruments AR7 System Frequency' CONFIG_AR7_SYS 125
2929 +   hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
2930 +fi
2931  dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
2932  dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
2933  dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
2934 @@ -239,6 +249,11 @@
2935     define_bool CONFIG_NONCOHERENT_IO y
2936     define_bool CONFIG_PC_KEYB y
2937  fi
2938 +if [ "$CONFIG_AR7" = "y" ]; then
2939 +   define_bool CONFIG_IRQ_CPU y
2940 +   define_bool CONFIG_NONCOHERENT_IO y
2941 +   define_bool CONFIG_SWAP_IO_SPACE y
2942 +fi
2943  if [ "$CONFIG_CASIO_E55" = "y" ]; then
2944     define_bool CONFIG_IRQ_CPU y
2945     define_bool CONFIG_NONCOHERENT_IO y
2946 @@ -736,6 +751,7 @@
2947  mainmenu_option next_comment
2948  comment 'General setup'
2949  if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2950 +     "$CONFIG_AR7" = "y" -o \
2951       "$CONFIG_CASIO_E55" = "y" -o \
2952       "$CONFIG_DDB5074" = "y" -o \
2953       "$CONFIG_DDB5476" = "y" -o \
2954 @@ -797,6 +813,7 @@
2955  bool 'Networking support' CONFIG_NET
2956
2957  if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2958 +     "$CONFIG_AR7" = "y" -o \
2959       "$CONFIG_CASIO_E55" = "y" -o \
2960       "$CONFIG_DECSTATION" = "y" -o \
2961       "$CONFIG_IBM_WORKPAD" = "y" -o \
2962 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
2963 --- linux.old/arch/mips/kernel/head.S   2005-10-21 16:43:16.396956500 +0200
2964 +++ linux.dev/arch/mips/kernel/head.S   2005-11-10 01:10:45.807572250 +0100
2965 @@ -75,11 +75,11 @@
2966                  * size!
2967                  */
2968                 NESTED(except_vec4, 0, sp)
2969 -               .set    push
2970 -               .set    noreorder
2971 -1:             j       1b                      /* Dummy, will be replaced */
2972 -                nop
2973 -               .set    pop
2974 +               .set    mips2
2975 +               lui     k0, 0x9400
2976 +               ori     k0, 0x200
2977 +               jr      k0
2978 +               nop
2979                 END(except_vec4)
2980
2981                 /*
2982 diff -urN linux.old/arch/mips/kernel/mips_ksyms.c linux.dev/arch/mips/kernel/mips_ksyms.c
2983 --- linux.old/arch/mips/kernel/mips_ksyms.c     2004-02-18 14:36:30.000000000 +0100
2984 +++ linux.dev/arch/mips/kernel/mips_ksyms.c     2005-11-10 01:10:45.811572500 +0100
2985 @@ -40,6 +40,12 @@
2986  extern long __strnlen_user_nocheck_asm(const char *s);
2987  extern long __strnlen_user_asm(const char *s);
2988
2989 +#ifdef CONFIG_AR7
2990 +#include <asm/ar7/adam2_env.h>
2991 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
2992 +#endif
2993 +
2994 +
2995  EXPORT_SYMBOL(mips_machtype);
2996  #ifdef CONFIG_EISA
2997  EXPORT_SYMBOL(EISA_bus);
2998 @@ -103,3 +109,10 @@
2999  #endif
3000
3001  EXPORT_SYMBOL(get_wchan);
3002 +
3003 +#ifdef CONFIG_AR7
3004 +EXPORT_SYMBOL_NOVERS(avalanche_request_pacing);
3005 +EXPORT_SYMBOL_NOVERS(prom_getenv);
3006 +EXPORT_SYMBOL_NOVERS(prom_iterenv);
3007 +#endif
3008 +
3009 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
3010 --- linux.old/arch/mips/kernel/setup.c  2005-10-21 16:43:16.396956500 +0200
3011 +++ linux.dev/arch/mips/kernel/setup.c  2005-11-10 01:14:16.376732000 +0100
3012 @@ -38,6 +38,7 @@
3013  #include <asm/io.h>
3014  #include <asm/ptrace.h>
3015  #include <asm/system.h>
3016 +#include <asm/addrspace.h>
3017
3018  struct cpuinfo_mips cpu_data[NR_CPUS];
3019  EXPORT_SYMBOL(cpu_data);
3020 @@ -88,7 +89,7 @@
3021  struct boot_mem_map boot_mem_map;
3022
3023  unsigned char aux_device_present;
3024 -extern char _ftext, _etext, _fdata, _edata, _end;
3025 +extern char _ftext, _etext, _fdata, _edata, _fbss, _end;
3026
3027  static char command_line[CL_SIZE];
3028         char saved_command_line[CL_SIZE];
3029 @@ -116,6 +117,7 @@
3030
3031  static struct resource code_resource = { "Kernel code" };
3032  static struct resource data_resource = { "Kernel data" };
3033 +static struct resource  bss_resource = { "Kernel bss" };
3034
3035  asmlinkage void __init
3036  init_arch(int argc, char **argv, char **envp, int *prom_vec)
3037 @@ -272,7 +274,7 @@
3038         for (i = 0; i < boot_mem_map.nr_map; i++) {
3039                 unsigned long start, end;
3040
3041 -               if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
3042 +               if (boot_mem_map.map[i].type == BOOT_MEM_RESERVED)
3043                         continue;
3044
3045                 start = PFN_UP(boot_mem_map.map[i].addr);
3046 @@ -320,7 +322,8 @@
3047  #endif
3048
3049         /* Initialize the boot-time allocator with low memory only.  */
3050 -       bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
3051 +       bootmap_size = init_bootmem_node(NODE_DATA(0), first_usable_pfn,
3052 +                                        PFN_UP(PHYS_OFFSET), max_low_pfn);
3053
3054         /*
3055          * Register fully available low RAM pages with the bootmem allocator.
3056 @@ -371,11 +374,12 @@
3057                         continue;
3058
3059                 /* Register lowmem ranges */
3060 -               free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
3061 +               free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
3062 +                                 size<<PAGE_SHIFT);
3063         }
3064
3065         /* Reserve the bootmap memory.  */
3066 -       reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
3067 +       reserve_bootmem_node(NODE_DATA(0), PFN_PHYS(first_usable_pfn), bootmap_size);
3068
3069  #ifdef CONFIG_BLK_DEV_INITRD
3070         /* Board specific code should have set up initrd_start and initrd_end */
3071 @@ -409,6 +413,8 @@
3072         code_resource.end = virt_to_bus(&_etext) - 1;
3073         data_resource.start = virt_to_bus(&_fdata);
3074         data_resource.end = virt_to_bus(&_edata) - 1;
3075 +       bss_resource.start = virt_to_bus(&_fbss);
3076 +       bss_resource.end = virt_to_bus(&_end) - 1;
3077
3078         /*
3079          * Request address space for all standard RAM.
3080 @@ -448,6 +454,7 @@
3081                  */
3082                 request_resource(res, &code_resource);
3083                 request_resource(res, &data_resource);
3084 +               request_resource(res, &bss_resource);
3085         }
3086  }
3087
3088 @@ -494,6 +501,7 @@
3089         void hp_setup(void);
3090         void au1x00_setup(void);
3091         void frame_info_init(void);
3092 +       void ar7_setup(void);
3093
3094         frame_info_init();
3095  #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
3096 @@ -691,6 +699,11 @@
3097                  pmc_yosemite_setup();
3098                  break;
3099  #endif
3100 +#ifdef CONFIG_AR7
3101 +       case MACH_GROUP_UNKNOWN:
3102 +               ar7_setup();
3103 +               break;
3104 +#endif
3105         default:
3106                 panic("Unsupported architecture");
3107         }
3108 diff -urN linux.old/arch/mips/kernel/time.c linux.dev/arch/mips/kernel/time.c
3109 --- linux.old/arch/mips/kernel/time.c   2005-01-19 15:09:29.000000000 +0100
3110 +++ linux.dev/arch/mips/kernel/time.c   2005-11-10 01:12:43.950955750 +0100
3111 @@ -143,7 +143,6 @@
3112         expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
3113         write_c0_count(expirelo - cycles_per_jiffy);
3114         write_c0_compare(expirelo);
3115 -       write_c0_count(count);
3116  }
3117
3118  int (*mips_timer_state)(void);
3119 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
3120 --- linux.old/arch/mips/kernel/traps.c  2005-10-21 16:43:16.400956750 +0200
3121 +++ linux.dev/arch/mips/kernel/traps.c  2005-11-10 01:13:28.301727500 +0100
3122 @@ -869,9 +869,24 @@
3123
3124         exception_handlers[n] = handler;
3125         if (n == 0 && cpu_has_divec) {
3126 +         printk(KERN_DEBUG "%s: using long jump via k0 to reach %08x\n",
3127 +                __FUNCTION__, handler);
3128 +         /* where does the 8 byte limit mentioned in head.S come from??? */
3129 +         if (handler > 0x0fffffff) { /* maximum for single J instruction */
3130 +           /* lui k0, 0x0000 */
3131 +           *(volatile u32 *)(KSEG0+0x200) = 0x3c1a0000 | (handler >> 16);
3132 +           /* ori k0, 0x0000 */
3133 +           *(volatile u32 *)(KSEG0+0x204) = 0x375a0000 | (handler & 0xffff);
3134 +           /* jr k0 */
3135 +           *(volatile u32 *)(KSEG0+0x208) = 0x03400008;
3136 +           /* nop */
3137 +           *(volatile u32 *)(KSEG0+0x20C) = 0x00000000;
3138 +           flush_icache_range(KSEG0+0x200, KSEG0+0x210);
3139 +         } else {
3140                 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
3141                                                  (0x03ffffff & (handler >> 2));
3142 -               flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
3143 +               flush_icache_range(KSEG0+0x200, KSEG0+0x204);
3144 +         }
3145         }
3146         return (void *)old_handler;
3147  }
3148 diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c
3149 --- linux.old/arch/mips/mm/init.c       2004-02-18 14:36:30.000000000 +0100
3150 +++ linux.dev/arch/mips/mm/init.c       2005-11-10 01:14:16.376732000 +0100
3151 @@ -235,10 +235,13 @@
3152  #endif
3153  }
3154
3155 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
3156 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
3157 +
3158  void __init paging_init(void)
3159  {
3160         unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
3161 -       unsigned long max_dma, high, low;
3162 +       unsigned long max_dma, high, low, start;
3163
3164         pagetable_init();
3165
3166 @@ -247,7 +250,8 @@
3167  #endif
3168
3169         max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
3170 -       low = max_low_pfn;
3171 +       start = START_PFN;
3172 +       low = MAX_LOW_PFN - start;
3173         high = highend_pfn;
3174
3175  #ifdef CONFIG_ISA
3176 @@ -270,7 +274,8 @@
3177                 zones_size[ZONE_HIGHMEM] = high - low;
3178  #endif
3179
3180 -       free_area_init(zones_size);
3181 +       free_area_init_node(0, NODE_DATA(0), 0, zones_size,
3182 +                           start << PAGE_SHIFT, 0);
3183  }
3184
3185  #define PFN_UP(x)      (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
3186 @@ -283,7 +288,7 @@
3187         for (i = 0; i < boot_mem_map.nr_map; i++) {
3188                 unsigned long addr, end;
3189
3190 -               if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
3191 +               if (boot_mem_map.map[i].type == BOOT_MEM_RESERVED)
3192                         /* not usable memory */
3193                         continue;
3194
3195 @@ -313,16 +318,17 @@
3196         max_mapnr = num_physpages = highend_pfn;
3197         num_mappedpages = max_low_pfn;
3198  #else
3199 -       max_mapnr = num_mappedpages = num_physpages = max_low_pfn;
3200 +       max_mapnr = num_mappedpages = num_physpages = MAX_LOW_PFN - START_PFN;
3201  #endif
3202 -       high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
3203 -
3204 -       totalram_pages += free_all_bootmem();
3205 +
3206 +       high_memory = (void *) __va(MAX_LOW_PFN * PAGE_SIZE);
3207 +
3208 +       totalram_pages += free_all_bootmem_node(NODE_DATA(0));
3209         totalram_pages -= setup_zero_pages();   /* Setup zeroed pages.  */
3210
3211         reservedpages = ram = 0;
3212 -       for (tmp = 0; tmp < max_low_pfn; tmp++)
3213 -               if (page_is_ram(tmp)) {
3214 +       for (tmp = 0; tmp < max_mapnr; tmp++)
3215 +               if (page_is_ram(START_PFN + tmp)) {
3216                         ram++;
3217                         if (PageReserved(mem_map+tmp))
3218                                 reservedpages++;
3219 @@ -377,13 +383,13 @@
3220  #endif
3221
3222  extern char __init_begin, __init_end;
3223 -extern void prom_free_prom_memory(void) __init;
3224 +extern unsigned long prom_free_prom_memory(void) __init;
3225
3226  void free_initmem(void)
3227  {
3228         unsigned long addr;
3229
3230 -       prom_free_prom_memory ();
3231 +       totalram_pages += prom_free_prom_memory ();
3232
3233         addr = (unsigned long) &__init_begin;
3234         while (addr < (unsigned long) &__init_end) {
3235 diff -urN linux.old/drivers/char/Config.in linux.dev/drivers/char/Config.in
3236 --- linux.old/drivers/char/Config.in    2005-10-21 16:43:16.440959250 +0200
3237 +++ linux.dev/drivers/char/Config.in    2005-11-10 01:10:45.843574500 +0100
3238 @@ -188,6 +188,14 @@
3239     tristate 'Total Impact briQ front panel driver' CONFIG_BRIQ_PANEL
3240  fi
3241
3242 +if [ "$CONFIG_AR7" = "y" ]; then
3243 +   bool 'VLYNQ support for the TI SOC' CONFIG_AR7_VLYNQ
3244 +   dep_bool 'VLYNQ clock source Internal' CONFIG_VLYNQ_CLK_LOCAL $CONFIG_AR7_VLYNQ
3245 +
3246 +   define_int CONFIG_AR7_VLYNQ_PORTS 2
3247 +   tristate 'ADAM2 environment support (read-only)' CONFIG_AR7_ADAM2
3248 +fi
3249 +
3250  source drivers/i2c/Config.in
3251
3252  mainmenu_option next_comment
3253 diff -urN linux.old/drivers/char/Config.in.orig linux.dev/drivers/char/Config.in.orig
3254 --- linux.old/drivers/char/Config.in.orig       1970-01-01 01:00:00.000000000 +0100
3255 +++ linux.dev/drivers/char/Config.in.orig       2005-11-10 01:10:45.863575750 +0100
3256 @@ -0,0 +1,414 @@
3257 +#
3258 +# Character device configuration
3259 +#
3260 +mainmenu_option next_comment
3261 +comment 'Character devices'
3262 +
3263 +bool 'Virtual terminal' CONFIG_VT
3264 +if [ "$CONFIG_VT" = "y" ]; then
3265 +   bool '  Support for console on virtual terminal' CONFIG_VT_CONSOLE
3266 +   if [ "$CONFIG_GSC_LASI" = "y" ]; then
3267 +      bool '    Support for Lasi/Dino PS2 port' CONFIG_GSC_PS2
3268 +   fi
3269 +fi
3270 +tristate 'Standard/generic (8250/16550 and compatible UARTs) serial support' CONFIG_SERIAL
3271 +if [ "$CONFIG_SERIAL" = "y" ]; then
3272 +   bool '  Support for console on serial port' CONFIG_SERIAL_CONSOLE
3273 +   if [ "$CONFIG_GSC_LASI" = "y" ]; then
3274 +      bool '   serial port on GSC support' CONFIG_SERIAL_GSC
3275 +   fi
3276 +   if [ "$CONFIG_IA64" = "y" ]; then
3277 +      bool '  Support for serial port described by EFI HCDP table' CONFIG_SERIAL_HCDP
3278 +   fi
3279 +   if [ "$CONFIG_ARCH_ACORN" = "y" ]; then
3280 +      tristate '   Atomwide serial port support' CONFIG_ATOMWIDE_SERIAL
3281 +      tristate '   Dual serial port support' CONFIG_DUALSP_SERIAL
3282 +   fi
3283 +fi
3284 +dep_mbool 'Extended dumb serial driver options' CONFIG_SERIAL_EXTENDED $CONFIG_SERIAL
3285 +if [ "$CONFIG_SERIAL_EXTENDED" = "y" ]; then
3286 +   bool '  Support more than 4 serial ports' CONFIG_SERIAL_MANY_PORTS
3287 +   bool '  Support for sharing serial interrupts' CONFIG_SERIAL_SHARE_IRQ
3288 +   bool '  Autodetect IRQ on standard ports (unsafe)' CONFIG_SERIAL_DETECT_IRQ
3289 +   bool '  Support special multiport boards' CONFIG_SERIAL_MULTIPORT
3290 +   bool '  Support the Bell Technologies HUB6 card' CONFIG_HUB6
3291 +fi
3292 +bool 'Non-standard serial port support' CONFIG_SERIAL_NONSTANDARD
3293 +if [ "$CONFIG_SERIAL_NONSTANDARD" = "y" ]; then
3294 +   tristate '  Computone IntelliPort Plus serial support' CONFIG_COMPUTONE
3295 +   tristate '  Comtrol Rocketport support' CONFIG_ROCKETPORT
3296 +   tristate '  Cyclades async mux support' CONFIG_CYCLADES
3297 +   if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_CYCLADES" != "n" ]; then
3298 +      bool '    Cyclades-Z interrupt mode operation (EXPERIMENTAL)' CONFIG_CYZ_INTR
3299 +   fi
3300 +   if [ "$CONFIG_X86_64" != "y" ]; then
3301 +      tristate '  Digiboard Intelligent Async Support' CONFIG_DIGIEPCA
3302 +      if [ "$CONFIG_DIGIEPCA" = "n" ]; then
3303 +         tristate '  Digiboard PC/Xx Support' CONFIG_DIGI
3304 +      fi
3305 +   fi
3306 +   dep_tristate '  Hayes ESP serial port support' CONFIG_ESPSERIAL $CONFIG_ISA
3307 +   tristate '  Moxa Intellio support' CONFIG_MOXA_INTELLIO
3308 +   tristate '  Moxa SmartIO support' CONFIG_MOXA_SMARTIO
3309 +   if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
3310 +      dep_tristate '  Multi-Tech multiport card support (EXPERIMENTAL)' CONFIG_ISI m
3311 +   fi
3312 +   tristate '  Microgate SyncLink card support' CONFIG_SYNCLINK
3313 +   tristate '  SyncLink Multiport support' CONFIG_SYNCLINKMP
3314 +   tristate '  HDLC line discipline support' CONFIG_N_HDLC
3315 +   tristate '  SDL RISCom/8 card support' CONFIG_RISCOM8
3316 +   if [ "$CONFIG_X86_64" != "y" ]; then
3317 +      tristate '  Specialix IO8+ card support' CONFIG_SPECIALIX
3318 +      if [ "$CONFIG_SPECIALIX" != "n" ]; then
3319 +         bool '  Specialix DTR/RTS pin is RTS' CONFIG_SPECIALIX_RTSCTS
3320 +      fi
3321 +      tristate '  Specialix SX (and SI) card support' CONFIG_SX
3322 +      tristate '  Specialix RIO system support' CONFIG_RIO
3323 +      if [ "$CONFIG_RIO" != "n" ]; then
3324 +        bool '    Support really old RIO/PCI cards' CONFIG_RIO_OLDPCI
3325 +      fi
3326 +   fi
3327 +   bool '  Stallion multiport serial support' CONFIG_STALDRV
3328 +   if [ "$CONFIG_STALDRV" = "y" ]; then
3329 +     tristate '    Stallion EasyIO or EC8/32 support' CONFIG_STALLION
3330 +     tristate '    Stallion EC8/64, ONboard, Brumby support' CONFIG_ISTALLION
3331 +   fi
3332 +   if [ "$CONFIG_PARISC" = "y" ]; then
3333 +     if [ "$CONFIG_PDC_CONSOLE" != "y" ]; then
3334 +       bool '  Serial MUX support' CONFIG_SERIAL_MUX CONFIG_SERIAL_NONSTANDARD
3335 +     fi
3336 +     if [ "$CONFIG_SERIAL_MUX" != "y" ]; then
3337 +       bool '  PDC software console support' CONFIG_PDC_CONSOLE CONFIG_SERIAL_NONSTANDARD
3338 +     fi
3339 +   fi
3340 +   if [ "$CONFIG_MIPS" = "y" ]; then
3341 +      bool '  TX3912/PR31700 serial port support' CONFIG_SERIAL_TX3912
3342 +      dep_bool '     Console on TX3912/PR31700 serial port' CONFIG_SERIAL_TX3912_CONSOLE $CONFIG_SERIAL_TX3912
3343 +      bool '  TMPTX39XX/49XX serial port support' CONFIG_SERIAL_TXX9
3344 +      dep_bool '     Console on TMPTX39XX/49XX serial port' CONFIG_SERIAL_TXX9_CONSOLE $CONFIG_SERIAL_TXX9
3345 +      if [ "$CONFIG_SOC_AU1X00" = "y" ]; then
3346 +        bool '  Enable Au1x00 UART Support' CONFIG_AU1X00_UART
3347 +        if [ "$CONFIG_AU1X00_UART" = "y" ]; then
3348 +           bool '        Enable Au1x00 serial console' CONFIG_AU1X00_SERIAL_CONSOLE
3349 +         fi
3350 +         dep_tristate '  Au1x00 USB TTY Device support' CONFIG_AU1X00_USB_TTY $CONFIG_SOC_AU1X00
3351 +           if [ "$CONFIG_AU1000_USB_TTY" != "y" ]; then
3352 +              dep_tristate '  Au1x00 USB Raw Device support' CONFIG_AU1X00_USB_RAW $CONFIG_SOC_AU1X00
3353 +           fi
3354 +           if [ "$CONFIG_AU1X00_USB_TTY" != "n" -o \
3355 +                "$CONFIG_AU1X00_USB_RAW" != "n" ]; then
3356 +                define_bool CONFIG_AU1X00_USB_DEVICE y
3357 +           fi
3358 +      fi
3359 +      bool '  TXx927 SIO support' CONFIG_TXX927_SERIAL
3360 +      if [ "$CONFIG_TXX927_SERIAL" = "y" ]; then
3361 +         bool '    TXx927 SIO Console support' CONFIG_TXX927_SERIAL_CONSOLE
3362 +      fi
3363 +      if [ "$CONFIG_SIBYTE_SB1xxx_SOC" = "y" ]; then
3364 +         bool '  Support for BCM1xxx onchip DUART' CONFIG_SIBYTE_SB1250_DUART
3365 +         if [ "$CONFIG_SIBYTE_SB1250_DUART" = "y" ]; then
3366 +            bool '    Console on BCM1xxx DUART' CONFIG_SIBYTE_SB1250_DUART_CONSOLE
3367 +            if [ "$CONFIG_SIBYTE_SB1250_DUART_CONSOLE" = "y" ]; then
3368 +               define_bool CONFIG_SERIAL_CONSOLE y
3369 +            fi
3370 +         fi
3371 +      fi
3372 +   fi
3373 +   if [ "$CONFIG_DECSTATION" = "y" ]; then
3374 +      bool '  DECstation serial support' CONFIG_SERIAL_DEC
3375 +      dep_bool '    Support for console on a DECstation serial port' CONFIG_SERIAL_DEC_CONSOLE $CONFIG_SERIAL_DEC
3376 +      dep_bool '    DZ11 serial support' CONFIG_DZ $CONFIG_SERIAL_DEC $CONFIG_MIPS32
3377 +      dep_bool '    Z85C30 serial support' CONFIG_ZS $CONFIG_SERIAL_DEC $CONFIG_TC
3378 +   fi
3379 +   if [ "$CONFIG_SGI_IP22" = "y" ]; then
3380 +      bool '  SGI Zilog85C30 serial support' CONFIG_IP22_SERIAL
3381 +   fi
3382 +   if [ "$CONFIG_IA64" = "y" ]; then
3383 +      bool '  SGI SN2 l1 serial port support' CONFIG_SGI_L1_SERIAL
3384 +      if [ "$CONFIG_SGI_L1_SERIAL" = "y" ]; then
3385 +        bool '    SGI SN2 l1 Console support' CONFIG_SGI_L1_SERIAL_CONSOLE
3386 +      fi
3387 +      if [ "$CONFIG_IA64_GENERIC" = "y" -o "$CONFIG_IA64_SGI_SN2" = "y" ]; then
3388 +        bool '  SGI SN2 IOC4 serial port support' CONFIG_SGI_IOC4_SERIAL
3389 +      fi
3390 +   fi
3391 +fi
3392 +if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_ZORRO" = "y" ]; then
3393 +   tristate 'Commodore A2232 serial support (EXPERIMENTAL)' CONFIG_A2232
3394 +fi
3395 +if [ "$CONFIG_FOOTBRIDGE" = "y" ]; then
3396 +   bool 'DC21285 serial port support' CONFIG_SERIAL_21285
3397 +   if [ "$CONFIG_SERIAL_21285" = "y" ]; then
3398 +      if [ "$CONFIG_OBSOLETE" = "y" ]; then
3399 +         bool '  Use /dev/ttyS0 device (OBSOLETE)' CONFIG_SERIAL_21285_OLD
3400 +      fi
3401 +      bool '  Console on DC21285 serial port' CONFIG_SERIAL_21285_CONSOLE
3402 +   fi
3403 +   if [ "$CONFIG_PARISC" = "y" ]; then
3404 +     bool '  PDC software console support' CONFIG_PDC_CONSOLE
3405 +   fi
3406 +fi
3407 +if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
3408 +   bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
3409 +   if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
3410 +     define_bool CONFIG_IT8172_CIR y
3411 +   else
3412 +     bool '    Enable PS2 Keyboard Support' CONFIG_PC_KEYB
3413 +   fi
3414 +   bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
3415 +   bool 'Enable Smart Card Reader 1 Support ' CONFIG_IT8172_SCR1
3416 +fi
3417 +if [ "$CONFIG_MIPS_IVR" = "y" ]; then
3418 +   bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
3419 +   if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
3420 +     define_bool CONFIG_IT8172_CIR y
3421 +   fi
3422 +   bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
3423 +fi
3424 +if [ "$CONFIG_CPU_VR41XX" = "y" ]; then
3425 +   bool 'NEC VR4100 series Keyboard Interface Unit Support ' CONFIG_VR41XX_KIU
3426 +fi
3427 +bool 'Unix98 PTY support' CONFIG_UNIX98_PTYS
3428 +if [ "$CONFIG_UNIX98_PTYS" = "y" ]; then
3429 +   int 'Maximum number of Unix98 PTYs in use (0-2048)' CONFIG_UNIX98_PTY_COUNT 256
3430 +fi
3431 +if [ "$CONFIG_PARPORT" != "n" ]; then
3432 +   dep_tristate 'Parallel printer support' CONFIG_PRINTER $CONFIG_PARPORT
3433 +   if [ "$CONFIG_PRINTER" != "n" ]; then
3434 +      bool '  Support for console on line printer' CONFIG_LP_CONSOLE
3435 +   fi
3436 +   dep_tristate 'Support for user-space parallel port device drivers' CONFIG_PPDEV $CONFIG_PARPORT
3437 +   dep_tristate 'Texas Instruments parallel link cable support' CONFIG_TIPAR $CONFIG_PARPORT
3438 +fi
3439 +
3440 +if [ "$CONFIG_PPC64" = "y" ] ; then
3441 +   bool 'pSeries Hypervisor Virtual Console support' CONFIG_HVC_CONSOLE
3442 +fi
3443 +if [ "$CONFIG_ALL_PPC" = "y" ]; then
3444 +   tristate 'Total Impact briQ front panel driver' CONFIG_BRIQ_PANEL
3445 +fi
3446 +
3447 +if [ "$CONFIG_AR7" = "y" ]; then
3448 +   bool 'VLYNQ support for the TI SOC' CONFIG_AR7_VLYNQ
3449 +   dep_bool 'VLYNQ clock source Internal' CONFIG_VLYNQ_CLK_LOCAL $CONFIG_AR7_VLYNQ
3450 +
3451 +   define_int CONFIG_AR7_VLYNQ_PORTS 2
3452 +fi
3453 +
3454 +source drivers/i2c/Config.in
3455 +
3456 +mainmenu_option next_comment
3457 +comment 'Mice'
3458 +tristate 'Bus Mouse Support' CONFIG_BUSMOUSE
3459 +if [ "$CONFIG_BUSMOUSE" != "n" ]; then
3460 +   dep_tristate '  ATIXL busmouse support' CONFIG_ATIXL_BUSMOUSE $CONFIG_BUSMOUSE
3461 +   dep_tristate '  Logitech busmouse support' CONFIG_LOGIBUSMOUSE $CONFIG_BUSMOUSE
3462 +   dep_tristate '  Microsoft busmouse support' CONFIG_MS_BUSMOUSE $CONFIG_BUSMOUSE
3463 +   if [ "$CONFIG_ADB" = "y" -a "$CONFIG_ADB_KEYBOARD" = "y" ]; then
3464 +      dep_tristate '  Apple Desktop Bus mouse support (old driver)' CONFIG_ADBMOUSE $CONFIG_BUSMOUSE
3465 +   fi
3466 +#   if [ "$CONFIG_DECSTATION" = "y" ]; then
3467 +#      dep_bool '  MAXINE Access.Bus mouse (VSXXX-BB/GB) support' CONFIG_DTOP_MOUSE $CONFIG_ACCESSBUS
3468 +#   fi
3469 +fi
3470 +
3471 +tristate 'Mouse Support (not serial and bus mice)' CONFIG_MOUSE
3472 +if [ "$CONFIG_MOUSE" != "n" ]; then
3473 +   bool '  PS/2 mouse (aka "auxiliary device") support' CONFIG_PSMOUSE
3474 +   tristate '  C&T 82C710 mouse port support (as on TI Travelmate)' CONFIG_82C710_MOUSE
3475 +   tristate '  PC110 digitizer pad support' CONFIG_PC110_PAD
3476 +   tristate '  MK712 touch screen support' CONFIG_MK712_MOUSE
3477 +fi
3478 +endmenu
3479 +
3480 +source drivers/char/joystick/Config.in
3481 +
3482 +tristate 'QIC-02 tape support' CONFIG_QIC02_TAPE
3483 +if [ "$CONFIG_QIC02_TAPE" != "n" ]; then
3484 +   bool '  Do you want runtime configuration for QIC-02' CONFIG_QIC02_DYNCONF
3485 +   if [ "$CONFIG_QIC02_DYNCONF" != "y" ]; then
3486 +      comment '  Edit configuration parameters in ./include/linux/tpqic02.h!'
3487 +   else
3488 +      comment '  Setting runtime QIC-02 configuration is done with qic02conf'
3489 +      comment '  from the tpqic02-support package.  It is available at'
3490 +      comment '  metalab.unc.edu or ftp://titus.cfw.com/pub/Linux/util/'
3491 +   fi
3492 +fi
3493 +
3494 +tristate 'IPMI top-level message handler' CONFIG_IPMI_HANDLER
3495 +dep_mbool '  Generate a panic event to all BMCs on a panic' CONFIG_IPMI_PANIC_EVENT $CONFIG_IPMI_HANDLER
3496 +dep_tristate '  Device interface for IPMI' CONFIG_IPMI_DEVICE_INTERFACE $CONFIG_IPMI_HANDLER
3497 +dep_tristate '  IPMI KCS handler' CONFIG_IPMI_KCS $CONFIG_IPMI_HANDLER
3498 +dep_tristate '  IPMI Watchdog Timer' CONFIG_IPMI_WATCHDOG $CONFIG_IPMI_HANDLER
3499 +
3500 +mainmenu_option next_comment
3501 +comment 'Watchdog Cards'
3502 +bool 'Watchdog Timer Support'  CONFIG_WATCHDOG
3503 +if [ "$CONFIG_WATCHDOG" != "n" ]; then
3504 +   bool '  Disable watchdog shutdown on close' CONFIG_WATCHDOG_NOWAYOUT
3505 +   tristate '  Acquire SBC Watchdog Timer' CONFIG_ACQUIRE_WDT
3506 +   tristate '  Advantech SBC Watchdog Timer' CONFIG_ADVANTECH_WDT
3507 +   tristate '  ALi M7101 PMU on ALi 1535D+ Watchdog Timer' CONFIG_ALIM1535_WDT
3508 +   tristate '  ALi M7101 PMU Watchdog Timer' CONFIG_ALIM7101_WDT
3509 +   tristate '  AMD "Elan" SC520 Watchdog Timer' CONFIG_SC520_WDT
3510 +   tristate '  Berkshire Products PC Watchdog' CONFIG_PCWATCHDOG
3511 +   if [ "$CONFIG_FOOTBRIDGE" = "y" ]; then
3512 +      tristate '  DC21285 watchdog' CONFIG_21285_WATCHDOG
3513 +      if [ "$CONFIG_ARCH_NETWINDER" = "y" ]; then
3514 +         tristate '  NetWinder WB83C977 watchdog' CONFIG_977_WATCHDOG
3515 +      fi
3516 +   fi
3517 +   tristate '  Eurotech CPU-1220/1410 Watchdog Timer' CONFIG_EUROTECH_WDT
3518 +   tristate '  IB700 SBC Watchdog Timer' CONFIG_IB700_WDT
3519 +   tristate '  ICP ELectronics Wafer 5823 Watchdog' CONFIG_WAFER_WDT
3520 +   tristate '  Intel i810 TCO timer / Watchdog' CONFIG_I810_TCO
3521 +   tristate '  Mixcom Watchdog' CONFIG_MIXCOMWD
3522 +   tristate '  SBC-60XX Watchdog Timer' CONFIG_60XX_WDT
3523 +   dep_tristate '  SC1200 Watchdog Timer (EXPERIMENTAL)' CONFIG_SC1200_WDT $CONFIG_EXPERIMENTAL
3524 +   tristate '  NatSemi SCx200 Watchdog' CONFIG_SCx200_WDT
3525 +   tristate '  Software Watchdog' CONFIG_SOFT_WATCHDOG
3526 +   tristate '  W83877F (EMACS) Watchdog Timer' CONFIG_W83877F_WDT
3527 +   tristate '  WDT Watchdog timer' CONFIG_WDT
3528 +   tristate '  WDT PCI Watchdog timer' CONFIG_WDTPCI
3529 +   if [ "$CONFIG_WDT" != "n" ]; then
3530 +      bool '    WDT501 features' CONFIG_WDT_501
3531 +      if [ "$CONFIG_WDT_501" = "y" ]; then
3532 +         bool '      Fan Tachometer' CONFIG_WDT_501_FAN
3533 +      fi
3534 +   fi
3535 +   tristate '  ZF MachZ Watchdog' CONFIG_MACHZ_WDT
3536 +   if [ "$CONFIG_SGI_IP22" = "y" ]; then
3537 +      dep_tristate '  Indy/I2 Hardware Watchdog' CONFIG_INDYDOG $CONFIG_SGI_IP22
3538 +   fi
3539 +   if [ "$CONFIG_8xx" = "y" ]; then
3540 +      tristate '  MPC8xx Watchdog Timer' CONFIG_8xx_WDT
3541 +   fi
3542 +fi
3543 +endmenu
3544 +
3545 +if [ "$CONFIG_ARCH_NETWINDER" = "y" ]; then
3546 +   tristate 'NetWinder thermometer support' CONFIG_DS1620
3547 +   tristate 'NetWinder Button' CONFIG_NWBUTTON
3548 +   if [ "$CONFIG_NWBUTTON" != "n" ]; then
3549 +      bool '  Reboot Using Button' CONFIG_NWBUTTON_REBOOT
3550 +   fi
3551 +   tristate 'NetWinder flash support' CONFIG_NWFLASH
3552 +fi
3553 +tristate 'NatSemi SCx200 Support' CONFIG_SCx200
3554 +dep_tristate '  NatSemi SCx200 GPIO Support' CONFIG_SCx200_GPIO $CONFIG_SCx200
3555 +
3556 +if [ "$CONFIG_IA64_GENERIC" = "y" -o "$CONFIG_IA64_SGI_SN2" = "y" ] ; then
3557 +   bool 'SGI SN2 fetchop support' CONFIG_FETCHOP
3558 +fi
3559 +
3560 +if [ "$CONFIG_X86" = "y" -o "$CONFIG_X86_64" = "y" ]; then
3561 +   dep_tristate 'AMD 768/8111 Random Number Generator support' CONFIG_AMD_RNG $CONFIG_PCI
3562 +fi
3563 +if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" ]; then
3564 +   dep_tristate 'Intel i8x0 Random Number Generator support' CONFIG_INTEL_RNG $CONFIG_PCI
3565 +fi
3566 +if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" -o \
3567 +     "$CONFIG_X86_64" = "y" ]; then
3568 +   dep_tristate 'Intel/AMD/VIA HW Random Number Generator support' CONFIG_HW_RANDOM $CONFIG_PCI
3569 +fi
3570 +dep_tristate 'AMD 76x native power management (Experimental)' CONFIG_AMD_PM768 $CONFIG_PCI
3571 +tristate '/dev/nvram support' CONFIG_NVRAM
3572 +tristate 'Enhanced Real Time Clock Support' CONFIG_RTC
3573 +if [ "$CONFIG_IA64" = "y" ]; then
3574 +   bool 'EFI Real Time Clock Services' CONFIG_EFI_RTC
3575 +fi
3576 +if [ "$CONFIG_OBSOLETE" = "y" -a "$CONFIG_ALPHA_BOOK1" = "y" ]; then
3577 +   bool 'Tadpole ANA H8 Support (OBSOLETE)'  CONFIG_H8
3578 +fi
3579 +if [ "$CONFIG_SGI_IP22" = "y" ]; then
3580 +   tristate 'Dallas DS1286 RTC support' CONFIG_DS1286
3581 +fi
3582 +if [ "$CONFIG_SGI_IP27" = "y" ]; then
3583 +   tristate 'SGI M48T35 RTC support' CONFIG_SGI_IP27_RTC
3584 +fi
3585 +if [ "$CONFIG_TOSHIBA_RBTX4927" = "y" -o "$CONFIG_TOSHIBA_JMR3927" = "y" ]; then
3586 +   tristate 'Dallas DS1742 RTC support' CONFIG_DS1742
3587 +fi
3588 +
3589 +tristate 'Double Talk PC internal speech card support' CONFIG_DTLK
3590 +tristate 'Siemens R3964 line discipline' CONFIG_R3964
3591 +tristate 'Applicom intelligent fieldbus card support' CONFIG_APPLICOM
3592 +if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_X86" = "y" -a "$CONFIG_X86_64" != "y" ]; then
3593 +   dep_tristate 'Sony Vaio Programmable I/O Control Device support (EXPERIMENTAL)' CONFIG_SONYPI $CONFIG_PCI
3594 +fi
3595 +
3596 +mainmenu_option next_comment
3597 +comment 'Ftape, the floppy tape device driver'
3598 +tristate 'Ftape (QIC-80/Travan) support' CONFIG_FTAPE
3599 +if [ "$CONFIG_FTAPE" != "n" ]; then
3600 +   source drivers/char/ftape/Config.in
3601 +fi
3602 +
3603 +endmenu
3604 +
3605 +if [ "$CONFIG_GART_IOMMU" = "y" ]; then
3606 +       bool '/dev/agpgart (AGP Support)' CONFIG_AGP
3607 +       define_bool CONFIG_AGP_AMD_K8 y
3608 +else
3609 +       tristate '/dev/agpgart (AGP Support)' CONFIG_AGP
3610 +fi
3611 +if [ "$CONFIG_AGP" != "n" ]; then
3612 +   bool '  Intel 440LX/BX/GX and I815/I820/I830M/I830MP/I840/I845/I850/I860 support' CONFIG_AGP_INTEL
3613 +   bool '  Intel I810/I815/I830M (on-board) support' CONFIG_AGP_I810
3614 +   bool '  VIA chipset support' CONFIG_AGP_VIA
3615 +   bool '  AMD Irongate, 761, and 762 support' CONFIG_AGP_AMD
3616 +   if [ "$CONFIG_GART_IOMMU" != "y" ]; then
3617 +      bool '  AMD Opteron/Athlon64 on-CPU GART support' CONFIG_AGP_AMD_K8
3618 +   fi
3619 +   bool '  Generic SiS support' CONFIG_AGP_SIS
3620 +   bool '  ALI chipset support' CONFIG_AGP_ALI
3621 +   bool '  Serverworks LE/HE support' CONFIG_AGP_SWORKS
3622 +   if [ "$CONFIG_X86" = "y" ]; then
3623 +      bool '  NVIDIA chipset support' CONFIG_AGP_NVIDIA
3624 +   fi
3625 +   if [ "$CONFIG_IA64" = "y" ]; then
3626 +      bool '  Intel 460GX support' CONFIG_AGP_I460
3627 +      bool '  HP ZX1 AGP support' CONFIG_AGP_HP_ZX1
3628 +   fi
3629 +   bool '  ATI IGP chipset support' CONFIG_AGP_ATI
3630 +fi
3631 +
3632 +mainmenu_option next_comment
3633 +comment 'Direct Rendering Manager (XFree86 DRI support)'
3634 +bool 'Direct Rendering Manager (XFree86 DRI support)' CONFIG_DRM
3635 +if [ "$CONFIG_DRM" = "y" ]; then
3636 +   bool '  Build drivers for old (XFree 4.0) DRM' CONFIG_DRM_OLD
3637 +   if [ "$CONFIG_DRM_OLD" = "y" ]; then
3638 +      comment 'DRM 4.0 drivers'
3639 +      source drivers/char/drm-4.0/Config.in
3640 +   else
3641 +      comment 'DRM 4.1 drivers'
3642 +      define_bool CONFIG_DRM_NEW y
3643 +      source drivers/char/drm/Config.in
3644 +   fi
3645 +fi
3646 +
3647 +if [ "$CONFIG_X86" = "y" ]; then
3648 +   tristate 'ACP Modem (Mwave) support' CONFIG_MWAVE
3649 +fi
3650 +
3651 +endmenu
3652 +
3653 +if [ "$CONFIG_HOTPLUG" = "y" -a "$CONFIG_PCMCIA" != "n" ]; then
3654 +   source drivers/char/pcmcia/Config.in
3655 +fi
3656 +if [ "$CONFIG_SOC_AU1X00" = "y" ]; then
3657 +   tristate ' Alchemy Au1x00 GPIO device support' CONFIG_AU1X00_GPIO
3658 +   tristate ' Au1000/ADS7846 touchscreen support' CONFIG_TS_AU1X00_ADS7846
3659 +   #tristate ' Alchemy Au1550 PSC SPI support' CONFIG_AU1550_PSC_SPI
3660 +fi
3661 +if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
3662 +  tristate ' ITE GPIO' CONFIG_ITE_GPIO
3663 +fi
3664 +
3665 +if [ "$CONFIG_X86" = "y" ]; then
3666 +   tristate 'ACP Modem (Mwave) support' CONFIG_MWAVE
3667 +   dep_tristate 'HP OB600 C/CT Pop-up mouse support' CONFIG_OBMOUSE $CONFIG_INPUT_MOUSEDEV
3668 +fi
3669 +
3670 +endmenu
3671 diff -urN linux.old/drivers/char/Makefile linux.dev/drivers/char/Makefile
3672 --- linux.old/drivers/char/Makefile     2005-10-21 16:43:16.460960500 +0200
3673 +++ linux.dev/drivers/char/Makefile     2005-11-10 01:10:45.871576250 +0100
3674 @@ -240,6 +240,13 @@
3675  obj-y += joystick/js.o
3676  endif
3677
3678 +#
3679 +# Texas Intruments VLYNQ driver
3680 +#
3681 +
3682 +subdir-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq
3683 +obj-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq/avalanche_vlynq.o
3684 +
3685  obj-$(CONFIG_FETCHOP) += fetchop.o
3686  obj-$(CONFIG_BUSMOUSE) += busmouse.o
3687  obj-$(CONFIG_DTLK) += dtlk.o
3688 @@ -340,6 +347,11 @@
3689    obj-y += ipmi/ipmi.o
3690  endif
3691
3692 +subdir-$(CONFIG_AR7_ADAM2) += ticfg
3693 +ifeq ($(CONFIG_AR7_ADAM2),y)
3694 +  obj-y += ticfg/ticfg.o
3695 +endif
3696 +
3697  include $(TOPDIR)/Rules.make
3698
3699  fastdep:
3700 diff -urN linux.old/drivers/char/Makefile.orig linux.dev/drivers/char/Makefile.orig
3701 --- linux.old/drivers/char/Makefile.orig        1970-01-01 01:00:00.000000000 +0100
3702 +++ linux.dev/drivers/char/Makefile.orig        2005-11-10 01:10:45.871576250 +0100
3703 @@ -0,0 +1,374 @@
3704 +#
3705 +# Makefile for the kernel character device drivers.
3706 +#
3707 +# Note! Dependencies are done automagically by 'make dep', which also
3708 +# removes any old dependencies. DON'T put your own dependencies here
3709 +# unless it's something special (ie not a .c file).
3710 +#
3711 +# Note 2! The CFLAGS definitions are now inherited from the
3712 +# parent makes..
3713 +#
3714 +
3715 +#
3716 +# This file contains the font map for the default (hardware) font
3717 +#
3718 +FONTMAPFILE = cp437.uni
3719 +
3720 +O_TARGET := char.o
3721 +
3722 +obj-y   += mem.o tty_io.o n_tty.o tty_ioctl.o raw.o pty.o misc.o random.o
3723 +
3724 +# All of the (potential) objects that export symbols.
3725 +# This list comes from 'grep -l EXPORT_SYMBOL *.[hc]'.
3726 +
3727 +export-objs     :=     busmouse.o console.o keyboard.o sysrq.o \
3728 +                       misc.o pty.o random.o selection.o serial.o \
3729 +                       sonypi.o tty_io.o tty_ioctl.o generic_serial.o \
3730 +                       au1000_gpio.o vac-serial.o hp_psaux.o nvram.o \
3731 +                       scx200.o fetchop.o
3732 +
3733 +mod-subdirs    :=      joystick ftape drm drm-4.0 pcmcia
3734 +
3735 +list-multi     :=
3736 +
3737 +KEYMAP   =defkeymap.o
3738 +KEYBD    =pc_keyb.o
3739 +CONSOLE  =console.o
3740 +SERIAL   =serial.o
3741 +
3742 +ifeq ($(ARCH),s390)
3743 +  KEYMAP   =
3744 +  KEYBD    =
3745 +  CONSOLE  =
3746 +  SERIAL   =
3747 +endif
3748 +
3749 +ifeq ($(ARCH),mips)
3750 +  ifneq ($(CONFIG_PC_KEYB),y)
3751 +    KEYBD    =
3752 +  endif
3753 +  ifeq ($(CONFIG_VR41XX_KIU),y)
3754 +    ifeq ($(CONFIG_IBM_WORKPAD),y)
3755 +      KEYMAP = ibm_workpad_keymap.o
3756 +    endif
3757 +    ifeq ($(CONFIG_VICTOR_MPC30X),y)
3758 +      KEYMAP = victor_mpc30x_keymap.o
3759 +    endif
3760 +    KEYBD    = vr41xx_keyb.o
3761 +  endif
3762 +endif
3763 +
3764 +ifeq ($(ARCH),s390x)
3765 +  KEYMAP   =
3766 +  KEYBD    =
3767 +  CONSOLE  =
3768 +  SERIAL   =
3769 +endif
3770 +
3771 +ifeq ($(ARCH),m68k)
3772 +   ifdef CONFIG_AMIGA
3773 +      KEYBD = amikeyb.o
3774 +   else
3775 +      ifndef CONFIG_MAC
3776 +        KEYBD =
3777 +      endif
3778 +   endif
3779 +   SERIAL   =
3780 +endif
3781 +
3782 +ifeq ($(ARCH),parisc)
3783 +   ifdef CONFIG_GSC_PS2
3784 +      KEYBD   = hp_psaux.o hp_keyb.o
3785 +   else
3786 +      KEYBD   =
3787 +   endif
3788 +   ifdef CONFIG_SERIAL_MUX
3789 +      CONSOLE += mux.o
3790 +   endif
3791 +   ifdef CONFIG_PDC_CONSOLE
3792 +      CONSOLE += pdc_console.o
3793 +   endif
3794 +endif
3795 +
3796 +ifdef CONFIG_Q40
3797 +  KEYBD += q40_keyb.o
3798 +  SERIAL = serial.o
3799 +endif
3800 +
3801 +ifdef CONFIG_APOLLO
3802 +  KEYBD += dn_keyb.o
3803 +endif
3804 +
3805 +ifeq ($(ARCH),parisc)
3806 +   ifdef CONFIG_GSC_PS2
3807 +      KEYBD   = hp_psaux.o hp_keyb.o
3808 +   else
3809 +      KEYBD   =
3810 +   endif
3811 +   ifdef CONFIG_PDC_CONSOLE
3812 +      CONSOLE += pdc_console.o
3813 +   endif
3814 +endif
3815 +
3816 +ifeq ($(ARCH),arm)
3817 +  ifneq ($(CONFIG_PC_KEYMAP),y)
3818 +    KEYMAP   =
3819 +  endif
3820 +  ifneq ($(CONFIG_PC_KEYB),y)
3821 +    KEYBD    =
3822 +  endif
3823 +endif
3824 +
3825 +ifeq ($(ARCH),sh)
3826 +  KEYMAP   =
3827 +  KEYBD    =
3828 +  CONSOLE  =
3829 +  ifeq ($(CONFIG_SH_HP600),y)
3830 +  KEYMAP   = defkeymap.o
3831 +  KEYBD    = scan_keyb.o hp600_keyb.o
3832 +  CONSOLE  = console.o
3833 +  endif
3834 +  ifeq ($(CONFIG_SH_DMIDA),y)
3835 +  # DMIDA does not connect the HD64465 PS/2 keyboard port
3836 +  # but we allow for USB keyboards to be plugged in.
3837 +  KEYMAP   = defkeymap.o
3838 +  KEYBD    = # hd64465_keyb.o pc_keyb.o
3839 +  CONSOLE  = console.o
3840 +  endif
3841 +  ifeq ($(CONFIG_SH_EC3104),y)
3842 +  KEYMAP   = defkeymap.o
3843 +  KEYBD    = ec3104_keyb.o
3844 +  CONSOLE  = console.o
3845 +  endif
3846 +  ifeq ($(CONFIG_SH_DREAMCAST),y)
3847 +  KEYMAP   = defkeymap.o
3848 +  KEYBD    =
3849 +  CONSOLE  = console.o
3850 +  endif
3851 +endif
3852 +
3853 +ifeq ($(CONFIG_DECSTATION),y)
3854 +  KEYMAP   =
3855 +  KEYBD    =
3856 +endif
3857 +
3858 +ifeq ($(CONFIG_BAGET_MIPS),y)
3859 +  KEYBD    =
3860 +  SERIAL   = vac-serial.o
3861 +endif
3862 +
3863 +ifeq ($(CONFIG_NINO),y)
3864 +  SERIAL   =
3865 +endif
3866 +
3867 +ifneq ($(CONFIG_SUN_SERIAL),)
3868 +  SERIAL   =
3869 +endif
3870 +
3871 +ifeq ($(CONFIG_QTRONIX_KEYBOARD),y)
3872 +  KEYBD    = qtronix.o
3873 +  KEYMAP   = qtronixmap.o
3874 +endif
3875 +
3876 +ifeq ($(CONFIG_DUMMY_KEYB),y)
3877 +  KEYBD = dummy_keyb.o
3878 +endif
3879 +
3880 +obj-$(CONFIG_VT) += vt.o vc_screen.o consolemap.o consolemap_deftbl.o $(CONSOLE) selection.o
3881 +obj-$(CONFIG_SERIAL) += $(SERIAL)
3882 +obj-$(CONFIG_PARPORT_SERIAL) += parport_serial.o
3883 +obj-$(CONFIG_SERIAL_HCDP) += hcdp_serial.o
3884 +obj-$(CONFIG_SERIAL_21285) += serial_21285.o
3885 +obj-$(CONFIG_SERIAL_SA1100) += serial_sa1100.o
3886 +obj-$(CONFIG_SERIAL_AMBA) += serial_amba.o
3887 +obj-$(CONFIG_TS_AU1X00_ADS7846) += au1000_ts.o
3888 +obj-$(CONFIG_SERIAL_DEC) += decserial.o
3889 +
3890 +ifndef CONFIG_SUN_KEYBOARD
3891 +  obj-$(CONFIG_VT) += keyboard.o $(KEYMAP) $(KEYBD)
3892 +else
3893 +  obj-$(CONFIG_PCI) += keyboard.o $(KEYMAP)
3894 +endif
3895 +
3896 +obj-$(CONFIG_HIL) += hp_keyb.o
3897 +obj-$(CONFIG_MAGIC_SYSRQ) += sysrq.o
3898 +obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o
3899 +obj-$(CONFIG_ROCKETPORT) += rocket.o
3900 +obj-$(CONFIG_MOXA_SMARTIO) += mxser.o
3901 +obj-$(CONFIG_MOXA_INTELLIO) += moxa.o
3902 +obj-$(CONFIG_DIGI) += pcxx.o
3903 +obj-$(CONFIG_DIGIEPCA) += epca.o
3904 +obj-$(CONFIG_CYCLADES) += cyclades.o
3905 +obj-$(CONFIG_STALLION) += stallion.o
3906 +obj-$(CONFIG_ISTALLION) += istallion.o
3907 +obj-$(CONFIG_SIBYTE_SB1250_DUART) += sb1250_duart.o
3908 +obj-$(CONFIG_COMPUTONE) += ip2.o ip2main.o
3909 +obj-$(CONFIG_RISCOM8) += riscom8.o
3910 +obj-$(CONFIG_ISI) += isicom.o
3911 +obj-$(CONFIG_ESPSERIAL) += esp.o
3912 +obj-$(CONFIG_SYNCLINK) += synclink.o
3913 +obj-$(CONFIG_SYNCLINKMP) += synclinkmp.o
3914 +obj-$(CONFIG_N_HDLC) += n_hdlc.o
3915 +obj-$(CONFIG_SPECIALIX) += specialix.o
3916 +obj-$(CONFIG_AMIGA_BUILTIN_SERIAL) += amiserial.o
3917 +obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o
3918 +obj-$(CONFIG_SX) += sx.o generic_serial.o
3919 +obj-$(CONFIG_RIO) += rio/rio.o generic_serial.o
3920 +obj-$(CONFIG_SH_SCI) += sh-sci.o generic_serial.o
3921 +obj-$(CONFIG_SERIAL167) += serial167.o
3922 +obj-$(CONFIG_MVME147_SCC) += generic_serial.o vme_scc.o
3923 +obj-$(CONFIG_MVME162_SCC) += generic_serial.o vme_scc.o
3924 +obj-$(CONFIG_BVME6000_SCC) += generic_serial.o vme_scc.o
3925 +obj-$(CONFIG_HVC_CONSOLE) += hvc_console.o
3926 +obj-$(CONFIG_SERIAL_TX3912) += generic_serial.o serial_tx3912.o
3927 +obj-$(CONFIG_TXX927_SERIAL) += serial_txx927.o
3928 +obj-$(CONFIG_SERIAL_TXX9) += generic_serial.o serial_txx9.o
3929 +obj-$(CONFIG_IP22_SERIAL) += sgiserial.o
3930 +obj-$(CONFIG_AU1X00_UART) += au1x00-serial.o
3931 +obj-$(CONFIG_SGI_L1_SERIAL) += sn_serial.o
3932 +
3933 +subdir-$(CONFIG_RIO) += rio
3934 +subdir-$(CONFIG_INPUT) += joystick
3935 +
3936 +obj-$(CONFIG_ATIXL_BUSMOUSE) += atixlmouse.o
3937 +obj-$(CONFIG_LOGIBUSMOUSE) += logibusmouse.o
3938 +obj-$(CONFIG_PRINTER) += lp.o
3939 +obj-$(CONFIG_TIPAR) += tipar.o
3940 +obj-$(CONFIG_OBMOUSE) += obmouse.o
3941 +
3942 +ifeq ($(CONFIG_INPUT),y)
3943 +obj-y += joystick/js.o
3944 +endif
3945 +
3946 +#
3947 +# Texas Intruments VLYNQ driver
3948 +#
3949 +
3950 +subdir-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq
3951 +obj-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq/avalanche_vlynq.o
3952 +
3953 +obj-$(CONFIG_FETCHOP) += fetchop.o
3954 +obj-$(CONFIG_BUSMOUSE) += busmouse.o
3955 +obj-$(CONFIG_DTLK) += dtlk.o
3956 +obj-$(CONFIG_R3964) += n_r3964.o
3957 +obj-$(CONFIG_APPLICOM) += applicom.o
3958 +obj-$(CONFIG_SONYPI) += sonypi.o
3959 +obj-$(CONFIG_MS_BUSMOUSE) += msbusmouse.o
3960 +obj-$(CONFIG_82C710_MOUSE) += qpmouse.o
3961 +obj-$(CONFIG_AMIGAMOUSE) += amigamouse.o
3962 +obj-$(CONFIG_ATARIMOUSE) += atarimouse.o
3963 +obj-$(CONFIG_ADBMOUSE) += adbmouse.o
3964 +obj-$(CONFIG_PC110_PAD) += pc110pad.o
3965 +obj-$(CONFIG_MK712_MOUSE) += mk712.o
3966 +obj-$(CONFIG_RTC) += rtc.o
3967 +obj-$(CONFIG_GEN_RTC) += genrtc.o
3968 +obj-$(CONFIG_EFI_RTC) += efirtc.o
3969 +obj-$(CONFIG_MIPS_RTC) += mips_rtc.o
3970 +obj-$(CONFIG_SGI_IP27_RTC) += ip27-rtc.o
3971 +ifeq ($(CONFIG_PPC),)
3972 +  obj-$(CONFIG_NVRAM) += nvram.o
3973 +endif
3974 +obj-$(CONFIG_TOSHIBA) += toshiba.o
3975 +obj-$(CONFIG_I8K) += i8k.o
3976 +obj-$(CONFIG_DS1286) += ds1286.o
3977 +obj-$(CONFIG_DS1620) += ds1620.o
3978 +obj-$(CONFIG_DS1742) += ds1742.o
3979 +obj-$(CONFIG_INTEL_RNG) += i810_rng.o
3980 +obj-$(CONFIG_AMD_RNG) += amd768_rng.o
3981 +obj-$(CONFIG_HW_RANDOM) += hw_random.o
3982 +obj-$(CONFIG_AMD_PM768) += amd76x_pm.o
3983 +obj-$(CONFIG_BRIQ_PANEL) += briq_panel.o
3984 +
3985 +obj-$(CONFIG_ITE_GPIO) += ite_gpio.o
3986 +obj-$(CONFIG_AU1X00_GPIO) += au1000_gpio.o
3987 +obj-$(CONFIG_AU1550_PSC_SPI) += au1550_psc_spi.o
3988 +obj-$(CONFIG_AU1X00_USB_TTY) += au1000_usbtty.o
3989 +obj-$(CONFIG_AU1X00_USB_RAW) += au1000_usbraw.o
3990 +obj-$(CONFIG_COBALT_LCD) += lcd.o
3991 +
3992 +obj-$(CONFIG_QIC02_TAPE) += tpqic02.o
3993 +
3994 +subdir-$(CONFIG_FTAPE) += ftape
3995 +subdir-$(CONFIG_DRM_OLD) += drm-4.0
3996 +subdir-$(CONFIG_DRM_NEW) += drm
3997 +subdir-$(CONFIG_PCMCIA) += pcmcia
3998 +subdir-$(CONFIG_AGP) += agp
3999 +
4000 +ifeq ($(CONFIG_FTAPE),y)
4001 +obj-y       += ftape/ftape.o
4002 +endif
4003 +
4004 +obj-$(CONFIG_H8) += h8.o
4005 +obj-$(CONFIG_PPDEV) += ppdev.o
4006 +obj-$(CONFIG_DZ) += dz.o
4007 +obj-$(CONFIG_NWBUTTON) += nwbutton.o
4008 +obj-$(CONFIG_NWFLASH) += nwflash.o
4009 +obj-$(CONFIG_SCx200) += scx200.o
4010 +obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o
4011 +
4012 +# Only one watchdog can succeed. We probe the hardware watchdog
4013 +# drivers first, then the softdog driver.  This means if your hardware
4014 +# watchdog dies or is 'borrowed' for some reason the software watchdog
4015 +# still gives you some cover.
4016 +
4017 +obj-$(CONFIG_PCWATCHDOG) += pcwd.o
4018 +obj-$(CONFIG_ACQUIRE_WDT) += acquirewdt.o
4019 +obj-$(CONFIG_ADVANTECH_WDT) += advantechwdt.o
4020 +obj-$(CONFIG_IB700_WDT) += ib700wdt.o
4021 +obj-$(CONFIG_MIXCOMWD) += mixcomwd.o
4022 +obj-$(CONFIG_60XX_WDT) += sbc60xxwdt.o
4023 +obj-$(CONFIG_W83877F_WDT) += w83877f_wdt.o
4024 +obj-$(CONFIG_SC520_WDT) += sc520_wdt.o
4025 +obj-$(CONFIG_WDT) += wdt.o
4026 +obj-$(CONFIG_WDTPCI) += wdt_pci.o
4027 +obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
4028 +obj-$(CONFIG_977_WATCHDOG) += wdt977.o
4029 +obj-$(CONFIG_I810_TCO) += i810-tco.o
4030 +obj-$(CONFIG_MACHZ_WDT) += machzwd.o
4031 +obj-$(CONFIG_SH_WDT) += shwdt.o
4032 +obj-$(CONFIG_EUROTECH_WDT) += eurotechwdt.o
4033 +obj-$(CONFIG_ALIM7101_WDT) += alim7101_wdt.o
4034 +obj-$(CONFIG_ALIM1535_WDT) += alim1535d_wdt.o
4035 +obj-$(CONFIG_INDYDOG) += indydog.o
4036 +obj-$(CONFIG_SC1200_WDT) += sc1200wdt.o
4037 +obj-$(CONFIG_SCx200_WDT) += scx200_wdt.o
4038 +obj-$(CONFIG_WAFER_WDT) += wafer5823wdt.o
4039 +obj-$(CONFIG_SOFT_WATCHDOG) += softdog.o
4040 +obj-$(CONFIG_INDYDOG) += indydog.o
4041 +obj-$(CONFIG_8xx_WDT) += mpc8xx_wdt.o
4042 +
4043 +subdir-$(CONFIG_MWAVE) += mwave
4044 +ifeq ($(CONFIG_MWAVE),y)
4045 +  obj-y += mwave/mwave.o
4046 +endif
4047 +
4048 +subdir-$(CONFIG_IPMI_HANDLER) += ipmi
4049 +ifeq ($(CONFIG_IPMI_HANDLER),y)
4050 +  obj-y += ipmi/ipmi.o
4051 +endif
4052 +
4053 +include $(TOPDIR)/Rules.make
4054 +
4055 +fastdep:
4056 +
4057 +conmakehash: conmakehash.c
4058 +       $(HOSTCC) $(HOSTCFLAGS) -o conmakehash conmakehash.c
4059 +
4060 +consolemap_deftbl.c: $(FONTMAPFILE) conmakehash
4061 +       ./conmakehash $(FONTMAPFILE) > consolemap_deftbl.c
4062 +
4063 +consolemap_deftbl.o: consolemap_deftbl.c $(TOPDIR)/include/linux/types.h
4064 +
4065 +.DELETE_ON_ERROR:
4066 +
4067 +defkeymap.c: defkeymap.map
4068 +       set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
4069 +
4070 +qtronixmap.c: qtronixmap.map
4071 +       set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
4072 +
4073 +ibm_workpad_keymap.c: ibm_workpad_keymap.map
4074 +       set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
4075 +
4076 +victor_mpc30x_keymap.c: victor_mpc30x_keymap.map
4077 +       set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
4078 diff -urN linux.old/drivers/char/avalanche_vlynq/Makefile linux.dev/drivers/char/avalanche_vlynq/Makefile
4079 --- linux.old/drivers/char/avalanche_vlynq/Makefile     1970-01-01 01:00:00.000000000 +0100
4080 +++ linux.dev/drivers/char/avalanche_vlynq/Makefile     2005-11-10 01:10:45.871576250 +0100
4081 @@ -0,0 +1,16 @@
4082 +#
4083 +# Makefile for the linux kernel.
4084 +#
4085 +# Note! Dependencies are done automagically by 'make dep', which also
4086 +# removes any old dependencies. DON'T put your own dependencies here
4087 +# unless it's something special (ie not a .c file).
4088 +#
4089 +# Note 2! The CFLAGS definitions are now in the main makefile...
4090 +
4091 +O_TARGET := avalanche_vlynq.o
4092 +
4093 +export-objs := vlynq_board.o
4094 +
4095 +obj-y    +=  vlynq_drv.o  vlynq_hal.o  vlynq_board.o
4096 +
4097 +include $(TOPDIR)/Rules.make
4098 diff -urN linux.old/drivers/char/avalanche_vlynq/vlynq_board.c linux.dev/drivers/char/avalanche_vlynq/vlynq_board.c
4099 --- linux.old/drivers/char/avalanche_vlynq/vlynq_board.c        1970-01-01 01:00:00.000000000 +0100
4100 +++ linux.dev/drivers/char/avalanche_vlynq/vlynq_board.c        2005-11-10 01:10:45.871576250 +0100
4101 @@ -0,0 +1,184 @@
4102 +/*
4103 + * Jeff Harrell, jharrell@ti.com
4104 + * Copyright (C) 2001 Texas Instruments, Inc.  All rights reserved.
4105 + *
4106 + *  This program is free software; you can distribute it and/or modify it
4107 + *  under the terms of the GNU General Public License (Version 2) as
4108 + *  published by the Free Software Foundation.
4109 + *
4110 + *  This program is distributed in the hope it will be useful, but WITHOUT
4111 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4112 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
4113 + *  for more details.
4114 + *
4115 + *  You should have received a copy of the GNU General Public License along
4116 + *  with this program; if not, write to the Free Software Foundation, Inc.,
4117 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
4118 + *
4119 + * Texas Instruments Sangam specific setup.
4120 + */
4121 +#include <linux/config.h>
4122 +#include <linux/module.h>
4123 +#include <asm/ar7/sangam.h>
4124 +#include <asm/ar7/avalanche_misc.h>
4125 +#include <asm/ar7/vlynq.h>
4126 +
4127 +#define SYS_VLYNQ_LOCAL_INTERRUPT_VECTOR       30      /* MSB - 1 bit */
4128 +#define SYS_VLYNQ_REMOTE_INTERRUPT_VECTOR      31      /* MSB bit */
4129 +#define SYS_VLYNQ_OPTIONS                      0x7F;   /* all options*/
4130 +
4131 +/* These defines are board specific */
4132 +
4133 +
4134 +#define VLYNQ0_REMOTE_WINDOW1_OFFSET           (0x0C000000)
4135 +#define VLYNQ0_REMOTE_WINDOW1_SIZE             (0x500)
4136 +
4137 +
4138 +#define VLYNQ1_REMOTE_WINDOW1_OFFSET           (0x0C000000)
4139 +#define VLYNQ1_REMOTE_WINDOW1_SIZE             (0x500)
4140 +
4141 +
4142 +extern VLYNQ_DEV vlynqDevice0, vlynqDevice1;
4143 +int    vlynq_init_status[2] = {0, 0};
4144 +EXPORT_SYMBOL(vlynq_init_status);
4145 +static int reset_hack = 1;
4146 +
4147 +void vlynq_ar7wrd_dev_init()
4148 +{
4149 +    *(unsigned long*) AVALANCHE_GPIO_ENBL    |= (1<<18);
4150 +    vlynq_delay(20000);
4151 +    *(unsigned long*) AVALANCHE_GPIO_DIR     &= ~(1<<18);
4152 +    vlynq_delay(20000);
4153 +    *(unsigned long*) AVALANCHE_GPIO_DATA_OUT&= ~(1<<18);
4154 +    vlynq_delay(50000);
4155 +    *(unsigned long*) AVALANCHE_GPIO_DATA_OUT|=  (1<<18);
4156 +    vlynq_delay(50000);
4157 +
4158 +    /* Initialize the MIPS host vlynq driver for a given vlynq interface */
4159 +    vlynqDevice0.dev_idx = 0;                  /* first vlynq module - this parameter is for reference only */
4160 +    vlynqDevice0.module_base = AVALANCHE_LOW_VLYNQ_CONTROL_BASE;       /*  vlynq0 module base address */
4161 +
4162 +#if defined(CONFIG_VLYNQ_CLK_LOCAL)
4163 +    vlynqDevice0.clk_source = VLYNQ_CLK_SOURCE_LOCAL;
4164 +#else
4165 +    vlynqDevice0.clk_source = VLYNQ_CLK_SOURCE_REMOTE;
4166 +#endif
4167 +    vlynqDevice0.clk_div = 0x01;                       /* board/hardware specific */
4168 +    vlynqDevice0.state =  VLYNQ_DRV_STATE_UNINIT;      /* uninitialized module */
4169 +
4170 +    /* Populate vlynqDevice0.local_mem & Vlynq0.remote_mem based on system configuration */
4171 +    /*Local memory configuration */
4172 +
4173 +                /* Demiurg : not good !*/
4174 +#if 0
4175 +    vlynqDevice0.local_mem.Txmap= AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE & ~(0xc0000000) ; /* physical address */
4176 +    vlynqDevice0.remote_mem.RxOffset[0]= VLYNQ0_REMOTE_WINDOW1_OFFSET; /* This is specific to the board on the other end */
4177 +    vlynqDevice0.remote_mem.RxSize[0]=VLYNQ0_REMOTE_WINDOW1_SIZE;
4178 +#endif
4179 +
4180 +                /* Demiurg : This is how it should be ! */
4181 +                vlynqDevice0.local_mem.Txmap = PHYSADDR(AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE);
4182 +#define VLYNQ_ACX111_MEM_OFFSET     0xC0000000  /* Physical address of ACX111 memory */
4183 +#define VLYNQ_ACX111_MEM_SIZE       0x00040000  /* Total size of the ACX111 memory   */
4184 +#define VLYNQ_ACX111_REG_OFFSET     0xF0000000  /* PHYS_ADDR of ACX111 control registers   */
4185 +#define VLYNQ_ACX111_REG_SIZE       0x00022000  /* Size of ACX111 registers area, MAC+PHY  */
4186 +#define ACX111_VL1_REMOTE_SIZE 0x1000000
4187 +                vlynqDevice0.remote_mem.RxOffset[0]  =  VLYNQ_ACX111_MEM_OFFSET;
4188 +                vlynqDevice0.remote_mem.RxSize[0]    =  VLYNQ_ACX111_MEM_SIZE  ;
4189 +                vlynqDevice0.remote_mem.RxOffset[1]  =  VLYNQ_ACX111_REG_OFFSET;
4190 +                vlynqDevice0.remote_mem.RxSize[1]    =  VLYNQ_ACX111_REG_SIZE  ;
4191 +                vlynqDevice0.remote_mem.Txmap        =  0;
4192 +                vlynqDevice0.local_mem.RxOffset[0]   =  AVALANCHE_SDRAM_BASE;
4193 +                vlynqDevice0.local_mem.RxSize[0]     =  ACX111_VL1_REMOTE_SIZE;
4194 +
4195 +
4196 +    /* Local interrupt configuration */
4197 +    vlynqDevice0.local_irq.intLocal = VLYNQ_INT_LOCAL;         /* Host handles vlynq interrupts*/
4198 +    vlynqDevice0.local_irq.intRemote = VLYNQ_INT_ROOT_ISR;     /* vlynq root isr used */
4199 +    vlynqDevice0.local_irq.map_vector = SYS_VLYNQ_LOCAL_INTERRUPT_VECTOR;
4200 +    vlynqDevice0.local_irq.intr_ptr = 0; /* Since remote interrupts part of vlynq root isr this is unused */
4201 +
4202 +    /* Remote interrupt configuration */
4203 +    vlynqDevice0.remote_irq.intLocal = VLYNQ_INT_REMOTE;       /* MIPS handles interrupts */
4204 +    vlynqDevice0.remote_irq.intRemote = VLYNQ_INT_ROOT_ISR;    /* Not significant since MIPS handles interrupts */
4205 +    vlynqDevice0.remote_irq.map_vector = SYS_VLYNQ_REMOTE_INTERRUPT_VECTOR;
4206 +    vlynqDevice0. remote_irq.intr_ptr = AVALANCHE_INTC_BASE; /* Not significant since MIPS handles interrupts */
4207 +
4208 +     if(reset_hack != 1)
4209 +       printk("About to re-init the VLYNQ.\n");
4210 +
4211 +    if(vlynq_init(&vlynqDevice0,VLYNQ_INIT_PERFORM_ALL)== 0)
4212 +    {
4213 +        /* Suraj added the following to keep the 1130 going. */
4214 +        vlynq_interrupt_vector_set(&vlynqDevice0, 0 /* intr vector line running into 1130 vlynq */,
4215 +                                   0 /* intr mapped onto the interrupt register on remote vlynq and this vlynq */,
4216 +                                   VLYNQ_REMOTE_DVC, 0 /* polarity active high */, 0 /* interrupt Level triggered */);
4217 +
4218 +        /* System wide interrupt is 80 for 1130, please note. */
4219 +        vlynq_init_status[0] = 1;
4220 +        reset_hack = 2;
4221 +    }
4222 +    else
4223 +    {
4224 +        if(reset_hack == 1)
4225 +            printk("VLYNQ INIT FAILED: Please try cold reboot. \n");
4226 +        else
4227 +            printk("Failed to initialize the VLYNQ interface at insmod.\n");
4228 +
4229 +    }
4230 +}
4231 +
4232 +void  vlynq_dev_init(void)
4233 +{
4234 +    volatile unsigned int *reset_base = (unsigned int *) AVALANCHE_RESET_CONTROL_BASE;
4235 +
4236 +    *reset_base &= ~((1 << AVALANCHE_LOW_VLYNQ_RESET_BIT)); /* | (1 << AVALANCHE_HIGH_VLYNQ_RESET_BIT)); */
4237 +
4238 +    vlynq_delay(20000);
4239 +
4240 +    /* Bring vlynq out of reset if not already done */
4241 +    *reset_base |= (1 << AVALANCHE_LOW_VLYNQ_RESET_BIT); /* | (1 << AVALANCHE_HIGH_VLYNQ_RESET_BIT); */
4242 +    vlynq_delay(20000); /* Allowing sufficient time to VLYNQ to settle down.*/
4243 +
4244 +    vlynq_ar7wrd_dev_init( );
4245 +
4246 +}
4247 +
4248 +/* This function is board specific and should be ported for each board. */
4249 +void remote_vlynq_dev_reset_ctrl(unsigned int module_reset_bit,
4250 +                                 AVALANCHE_RESET_CTRL_T reset_ctrl)
4251 +{
4252 +    if(module_reset_bit >= 32)
4253 +        return;
4254 +
4255 +    switch(module_reset_bit)
4256 +    {
4257 +        case 0:
4258 +            if(OUT_OF_RESET == reset_ctrl)
4259 +            {
4260 +                if(reset_hack) return;
4261 +
4262 +                vlynq_delay(20000);
4263 +                printk("Un-resetting the remote device.\n");
4264 +                vlynq_dev_init();
4265 +                printk("Re-initialized the VLYNQ.\n");
4266 +                reset_hack = 2;
4267 +            }
4268 +            else if(IN_RESET == reset_ctrl)
4269 +            {
4270 +                *(unsigned long*) AVALANCHE_GPIO_DATA_OUT &= ~(1<<18);
4271 +
4272 +                vlynq_delay(20000);
4273 +                printk("Resetting the remote device.\n");
4274 +                reset_hack = 0;
4275 +            }
4276 +            else
4277 +                ;
4278 +        break;
4279 +
4280 +        default:
4281 +        break;
4282 +
4283 +    }
4284 +}
4285 +
4286 diff -urN linux.old/drivers/char/avalanche_vlynq/vlynq_drv.c linux.dev/drivers/char/avalanche_vlynq/vlynq_drv.c
4287 --- linux.old/drivers/char/avalanche_vlynq/vlynq_drv.c  1970-01-01 01:00:00.000000000 +0100
4288 +++ linux.dev/drivers/char/avalanche_vlynq/vlynq_drv.c  2005-11-10 01:10:45.891577500 +0100
4289 @@ -0,0 +1,243 @@
4290 +/******************************************************************************
4291 + * FILE PURPOSE:    Vlynq Linux Device Driver Source
4292 + ******************************************************************************
4293 + * FILE NAME:       vlynq_drv.c
4294 + *
4295 + * DESCRIPTION:     Vlynq Linux Device Driver Source
4296 + *
4297 + * REVISION HISTORY:
4298 + *
4299 + * Date           Description                       Author
4300 + *-----------------------------------------------------------------------------
4301 + * 17 July 2003   Initial Creation                  Anant Gole
4302 + * 17 Dec  2003   Updates                           Sharath Kumar
4303 + *
4304 + * (C) Copyright 2003, Texas Instruments, Inc
4305 + *******************************************************************************/
4306 +
4307 +#include <linux/config.h>
4308 +#include <linux/init.h>
4309 +#include <linux/module.h>
4310 +#include <linux/sched.h>
4311 +#include <linux/miscdevice.h>
4312 +#include <linux/smp_lock.h>
4313 +#include <linux/delay.h>
4314 +#include <linux/proc_fs.h>
4315 +#include <linux/capability.h>
4316 +#include <asm/ar7/avalanche_intc.h>
4317 +#include <asm/ar7/sangam.h>
4318 +#include <asm/ar7/vlynq.h>
4319 +
4320 +
4321 +#define    TI_VLYNQ_VERSION                 "0.2"
4322 +
4323 +/* debug on ? */
4324 +#define VLYNQ_DEBUG
4325 +
4326 +/* Macro for debug and error printf's */
4327 +#ifdef VLYNQ_DEBUG
4328 +#define DBGPRINT  printk
4329 +#else
4330 +#define DBGPRINT(x)
4331 +#endif
4332 +
4333 +#define ERRPRINT  printk
4334 +
4335 +/* Define the max vlynq ports this driver will support.
4336 +   Device name strings are statically added here */
4337 +#define MAX_VLYNQ_PORTS 2
4338 +
4339 +
4340 +/* Type define for VLYNQ private structure */
4341 +typedef struct vlynqPriv{
4342 +    int irq;
4343 +    VLYNQ_DEV *vlynqDevice;
4344 +}VLYNQ_PRIV;
4345 +
4346 +extern int vlynq_init_status[2];
4347 +
4348 +/* Extern Global variable for vlynq devices used in initialization of the vlynq device
4349 + * These variables need to be populated/initialized by the system as part of initialization
4350 + * process. The vlynq enumerator can run at initialization and populate these globals
4351 + */
4352 +
4353 +VLYNQ_DEV vlynqDevice0;
4354 +VLYNQ_DEV vlynqDevice1;
4355 +
4356 +/* Defining dummy macro AVALANCHE_HIGH_VLYNQ_INT to take
4357 + * care of compilation in case of single vlynq device
4358 + */
4359 +
4360 +#ifndef AVALANCHE_HIGH_VLYNQ_INT
4361 +#define  AVALANCHE_HIGH_VLYNQ_INT 0
4362 +#endif
4363 +
4364 +
4365 +
4366 +/* vlynq private object */
4367 +VLYNQ_PRIV vlynq_priv[CONFIG_AR7_VLYNQ_PORTS] = {
4368 +    { LNXINTNUM(AVALANCHE_LOW_VLYNQ_INT),&vlynqDevice0},
4369 +    { LNXINTNUM(AVALANCHE_HIGH_VLYNQ_INT),&vlynqDevice1},
4370 +};
4371 +
4372 +extern void vlynq_dev_init(void);
4373 +
4374 +
4375 +/* =================================== all the operations */
4376 +
4377 +static int
4378 +vlynq_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
4379 +{
4380 +    return 0;
4381 +}
4382 +
4383 +static struct file_operations vlynq_fops = {
4384 +    owner:      THIS_MODULE,
4385 +    ioctl:      vlynq_ioctl,
4386 +};
4387 +
4388 +/* Vlynq device object */
4389 +static struct miscdevice vlynq_dev [MAX_VLYNQ_PORTS] = {
4390 +    { MISC_DYNAMIC_MINOR , "vlynq0", &vlynq_fops },
4391 +    { MISC_DYNAMIC_MINOR , "vlynq1", &vlynq_fops },
4392 +};
4393 +
4394 +
4395 +/* Proc read function */
4396 +static int
4397 +vlynq_read_link_proc(char *buf, char **start, off_t offset, int count, int *eof, void *unused)
4398 +{
4399 +    int instance;
4400 +    int len = 0;
4401 +
4402 +    len += sprintf(buf +len,"VLYNQ Devices : %d\n",CONFIG_AR7_VLYNQ_PORTS);
4403 +
4404 +    for(instance =0;instance < CONFIG_AR7_VLYNQ_PORTS;instance++)
4405 +    {
4406 +        int link_state;
4407 +        char *link_msg[] = {" DOWN "," UP "};
4408 +
4409 +        if(vlynq_init_status[instance] == 0)
4410 +            link_state = 0;
4411 +
4412 +        else if (vlynq_link_check(vlynq_priv[instance].vlynqDevice))
4413 +            link_state = 1;
4414 +
4415 +        else
4416 +            link_state = 0;
4417 +
4418 +        len += sprintf(buf + len, "VLYNQ %d: Link state: %s\n",instance,link_msg[link_state]);
4419 +
4420 +    }
4421 +    /* Print info about vlynq device 1 */
4422 +
4423 +    return len;
4424 +}
4425 +
4426 +
4427 +/* Proc function to display driver version */
4428 +static int
4429 +vlynq_read_ver_proc(char *buf, char **start, off_t offset, int count, int *eof, void *data)
4430 +{
4431 +       int instance;
4432 +       int len=0;
4433 +
4434 +       len += sprintf(buf +len,"\nTI Linux VLYNQ Driver Version %s\n",TI_VLYNQ_VERSION);
4435 +       return len;
4436 +}
4437 +
4438 +
4439 +
4440 +
4441 +/* Wrapper for vlynq ISR */
4442 +static void lnx_vlynq_root_isr(int irq, void * arg, struct pt_regs *regs)
4443 +{
4444 +   vlynq_root_isr(arg);
4445 +}
4446 +
4447 +/* =================================== init and cleanup */
4448 +
4449 +int vlynq_init_module(void)
4450 +{
4451 +    int ret;
4452 +    int unit = 0;
4453 +    int instance_count = CONFIG_AR7_VLYNQ_PORTS;
4454 +    volatile int *ptr;
4455 +
4456 +    vlynq_dev_init();
4457 +
4458 +    DBGPRINT("Vlynq CONFIG_AR7_VLYNQ_PORTS=%d\n", CONFIG_AR7_VLYNQ_PORTS);
4459 +    /* If num of configured vlynq ports > supported by driver return error */
4460 +    if (instance_count > MAX_VLYNQ_PORTS)
4461 +    {
4462 +        ERRPRINT("ERROR: vlynq_init_module(): Max %d supported\n", MAX_VLYNQ_PORTS);
4463 +        return (-1);
4464 +    }
4465 +
4466 +    /* register the misc device */
4467 +    for (unit = 0; unit < CONFIG_AR7_VLYNQ_PORTS; unit++)
4468 +    {
4469 +        ret = misc_register(&vlynq_dev[unit]);
4470 +
4471 +        if(ret < 0)
4472 +        {
4473 +            ERRPRINT("ERROR:Could not register vlynq device:%d\n",unit);
4474 +            continue;
4475 +        }
4476 +        else
4477 +            DBGPRINT("Vlynq Device %s registered with minor no %d as misc device. Result=%d\n",
4478 +                vlynq_dev[unit].name, vlynq_dev[unit].minor, ret);
4479 +#if 0
4480 +
4481 +        DBGPRINT("Calling vlynq init\n");
4482 +
4483 +        /* Read the global variable for VLYNQ device structure and initialize vlynq driver */
4484 +        ret = vlynq_init(vlynq_priv[unit].vlynqDevice,VLYNQ_INIT_PERFORM_ALL );
4485 +#endif
4486 +
4487 +        if(vlynq_init_status[unit] == 0)
4488 +        {
4489 +            printk("VLYNQ %d : init failed\n",unit);
4490 +            continue;
4491 +        }
4492 +
4493 +        /* Check link before proceeding */
4494 +        if (!vlynq_link_check(vlynq_priv[unit].vlynqDevice))
4495 +        {
4496 +           DBGPRINT("\nError: Vlynq link not available.trying once before  Exiting");
4497 +        }
4498 +        else
4499 +        {
4500 +            DBGPRINT("Vlynq instance:%d Link UP\n",unit);
4501 +
4502 +            /* Install the vlynq local root ISR */
4503 +           request_irq(vlynq_priv[unit].irq,lnx_vlynq_root_isr,0,vlynq_dev[unit].name,vlynq_priv[unit].vlynqDevice);
4504 +        }
4505 +    }
4506 +
4507 +    proc_mkdir("avalanche", NULL);
4508 +    /* Creating proc entry for the devices */
4509 +    create_proc_read_entry("avalanche/vlynq_link", 0, NULL, vlynq_read_link_proc, NULL);
4510 +    create_proc_read_entry("avalanche/vlynq_ver", 0, NULL, vlynq_read_ver_proc, NULL);
4511 +
4512 +    return 0;
4513 +}
4514 +
4515 +void vlynq_cleanup_module(void)
4516 +{
4517 +    int unit = 0;
4518 +
4519 +    for (unit = 0; unit < CONFIG_AR7_VLYNQ_PORTS; unit++)
4520 +    {
4521 +        DBGPRINT("vlynq_cleanup_module(): Unregistring misc device %s\n",vlynq_dev[unit].name);
4522 +        misc_deregister(&vlynq_dev[unit]);
4523 +    }
4524 +
4525 +    remove_proc_entry("avalanche/vlynq_link", NULL);
4526 +    remove_proc_entry("avalanche/vlynq_ver", NULL);
4527 +}
4528 +
4529 +
4530 +module_init(vlynq_init_module);
4531 +module_exit(vlynq_cleanup_module);
4532 +
4533 diff -urN linux.old/drivers/char/avalanche_vlynq/vlynq_hal.c linux.dev/drivers/char/avalanche_vlynq/vlynq_hal.c
4534 --- linux.old/drivers/char/avalanche_vlynq/vlynq_hal.c  1970-01-01 01:00:00.000000000 +0100
4535 +++ linux.dev/drivers/char/avalanche_vlynq/vlynq_hal.c  2005-11-10 01:10:45.975582750 +0100
4536 @@ -0,0 +1,1214 @@
4537 +/***************************************************************************
4538 +**+----------------------------------------------------------------------+**
4539 +**|                                ****                                  |**
4540 +**|                                ****                                  |**
4541 +**|                                ******o***                            |**
4542 +**|                          ********_///_****                           |**
4543 +**|                           ***** /_//_/ ****                          |**
4544 +**|                            ** ** (__/ ****                           |**
4545 +**|                                *********                             |**
4546 +**|                                 ****                                 |**
4547 +**|                                  ***                                 |**
4548 +**|                                                                      |**
4549 +**|     Copyright (c) 2003 Texas Instruments Incorporated                |**
4550 +**|                        ALL RIGHTS RESERVED                           |**
4551 +**|                                                                      |**
4552 +**| Permission is hereby granted to licensees of Texas Instruments       |**
4553 +**| Incorporated (TI) products to use this computer program for the sole |**
4554 +**| purpose of implementing a licensee product based on TI products.     |**
4555 +**| No other rights to reproduce, use, or disseminate this computer      |**
4556 +**| program, whether in part or in whole, are granted.                   |**
4557 +**|                                                                      |**
4558 +**| TI makes no representation or warranties with respect to the         |**
4559 +**| performance of this computer program, and specifically disclaims     |**
4560 +**| any responsibility for any damages, special or consequential,        |**
4561 +**| connected with the use of this program.                              |**
4562 +**|                                                                      |**
4563 +**+----------------------------------------------------------------------+**
4564 +***************************************************************************/
4565 +
4566 +/***************************************************************************
4567 + *  ------------------------------------------------------------------------------
4568 + *   Module      : vlynq_hal.c
4569 + *   Description : This file implements VLYNQ HAL API.
4570 + *  ------------------------------------------------------------------------------
4571 + ***************************************************************************/
4572 +
4573 +#include <linux/stddef.h>
4574 +#include <linux/types.h>
4575 +#include <asm/ar7/vlynq.h>
4576 +
4577 +/**** Local Function prototypes *******/
4578 +static int vlynqInterruptInit(VLYNQ_DEV *pdev);
4579 +static void  vlynq_configClock(VLYNQ_DEV  *pdev);
4580 +
4581 +/*** Second argument must be explicitly type casted to
4582 + * (VLYNQ_DEV*) inside the following functions */
4583 +static void vlynq_local_module_isr(void *arg1, void *arg2, void *arg3);
4584 +static void vlynq_remote_module_isr(void *arg1, void *arg2, void *arg3);
4585 +
4586 +
4587 +volatile int vlynq_delay_value = 0;
4588 +
4589 +/* Code adopted from original vlynq driver */
4590 +void vlynq_delay(unsigned int clktime)
4591 +{
4592 +    int i = 0;
4593 +    volatile int    *ptr = &vlynq_delay_value;
4594 +    *ptr = 0;
4595 +
4596 +    /* We are assuming that the each cycle takes about
4597 +     * 23 assembly instructions. */
4598 +    for(i = 0; i < (clktime + 23)/23; i++)
4599 +    {
4600 +        *ptr = *ptr + 1;
4601 +    }
4602 +}
4603 +
4604 +
4605 +/* ----------------------------------------------------------------------------
4606 + *  Function : vlynq_configClock()
4607 + *  Description: Configures clock settings based on input parameters
4608 + *  Adapted from original vlyna driver from Cable
4609 + */
4610 +static void vlynq_configClock(VLYNQ_DEV * pdev)
4611 +{
4612 +    unsigned int tmp;
4613 +
4614 +    switch( pdev->clk_source)
4615 +    {
4616 +        case VLYNQ_CLK_SOURCE_LOCAL:  /* we output the clock, clk_div in range [1..8]. */
4617 +            tmp = ((pdev->clk_div - 1) << 16) |  VLYNQ_CTL_CLKDIR_MASK ;
4618 +            VLYNQ_CTRL_REG = tmp;
4619 +            VLYNQ_R_CTRL_REG = 0ul;
4620 +            break;
4621 +        case VLYNQ_CLK_SOURCE_REMOTE: /* we need to set the clock pin as input */
4622 +            VLYNQ_CTRL_REG = 0ul;
4623 +            tmp = ((pdev->clk_div - 1) << 16) |  VLYNQ_CTL_CLKDIR_MASK ;
4624 +            VLYNQ_R_CTRL_REG = tmp;
4625 +            break;
4626 +        default:   /* do nothing about the clock, but clear other bits. */
4627 +            tmp = ~(VLYNQ_CTL_CLKDIR_MASK | VLYNQ_CTL_CLKDIV_MASK);
4628 +            VLYNQ_CTRL_REG &= tmp;
4629 +            break;
4630 +   }
4631 +}
4632 +
4633 + /* ----------------------------------------------------------------------------
4634 + *  Function : vlynq_link_check()
4635 + *  Description: This function checks the current VLYNQ for a link.
4636 + *  An arbitrary amount of time is allowed for the link to come up .
4637 + *  Returns 0 for "no link / failure " and 1 for "link available".
4638 + * -----------------------------------------------------------------------------
4639 + */
4640 +unsigned int vlynq_link_check( VLYNQ_DEV * pdev)
4641 +{
4642 +    /*sleep for 64 cycles, allow link to come up*/
4643 +    vlynq_delay(64);
4644 +
4645 +    /* check status register return OK if link is found. */
4646 +    if (VLYNQ_STATUS_REG & VLYNQ_STS_LINK_MASK)
4647 +    {
4648 +        return 1;   /* Link Available */
4649 +    }
4650 +    else
4651 +    {
4652 +        return 0;   /* Link Failure */
4653 +    }
4654 +}
4655 +
4656 +/* ----------------------------------------------------------------------------
4657 + *  Function : vlynq_init()
4658 + *  Description: Initialization function accepting paramaters for VLYNQ module
4659 + *  initialization. The Options bitmap decides what operations are performed
4660 + *  as a part of initialization. The Input parameters  are obtained through the
4661 + *  sub fields of VLYNQ_DEV structure.
4662 + */
4663 +
4664 +int vlynq_init(VLYNQ_DEV *pdev, VLYNQ_INIT_OPTIONS options)
4665 +{
4666 +    unsigned int map;
4667 +    unsigned int val=0,cnt,tmp;
4668 +    unsigned int counter=0;
4669 +    VLYNQ_INTERRUPT_CNTRL *intSetting=NULL;
4670 +
4671 +    /* validate arguments */
4672 +    if( VLYNQ_OUTRANGE(pdev->clk_source, VLYNQ_CLK_SOURCE_REMOTE, VLYNQ_CLK_SOURCE_NONE) ||
4673 +        VLYNQ_OUTRANGE(pdev->clk_div, 8, 1) )
4674 +    {
4675 +      return VLYNQ_INVALID_ARG;
4676 +    }
4677 +
4678 +    /** perform all sanity checks first **/
4679 +    if(pdev->state != VLYNQ_DRV_STATE_UNINIT)
4680 +        return VLYNQ_INVALID_DRV_STATE;
4681 +
4682 +    /** Initialize local and remote register set addresses- additional
4683 +     * provision to access the registers directly if need be */
4684 +    pdev->local = (VLYNQ_REG_SET*)pdev->module_base;
4685 +    pdev->remote = (VLYNQ_REG_SET*) (pdev->module_base + VLYNQ_REMOTE_REGS_OFFSET);
4686 +
4687 +    /* Detect faulty int configuration that might induce int pkt looping */
4688 +    if ( (options  & VLYNQ_INIT_LOCAL_INTERRUPTS) && (options & VLYNQ_INIT_REMOTE_INTERRUPTS) )
4689 +    {
4690 +        /* case when both local and remote are configured */
4691 +        if((pdev->local_irq.intLocal== VLYNQ_INT_REMOTE )  /* interrupts transfered to remote from local */
4692 +        && (pdev->remote_irq.intLocal== VLYNQ_INT_REMOTE)  /* interrupts transfered from remote to local */
4693 +        && ((pdev->local_irq.intRemote == VLYNQ_INT_ROOT_ISR) || (pdev->remote_irq.intRemote == VLYNQ_INT_ROOT_ISR)) )
4694 +        {
4695 +            return (VLYNQ_INT_CONFIG_ERR);
4696 +        }
4697 +    }
4698 +
4699 +    pdev->state = VLYNQ_DRV_STATE_ININIT;
4700 +    pdev->intCount = 0;
4701 +    pdev->isrCount = 0;
4702 +
4703 +    /*** Its assumed that the vlynq module  has been brought out of reset
4704 +     * before invocation of vlynq_init. Since, this operation is board specific
4705 +     * it must be handled outside this generic driver */
4706 +
4707 +    /* Assert reset the remote device, call reset_cb,
4708 +     * reset CB holds Reset according to the device needs. */
4709 +    VLYNQ_RESETCB(VLYNQ_RESET_ASSERT);
4710 +
4711 +    /* Handle VLYNQ clock, HW default (Sense On Reset) is
4712 +     * usually input for all the devices. */
4713 +    if (options & VLYNQ_INIT_CONFIG_CLOCK)
4714 +    {
4715 +        vlynq_configClock(pdev);
4716 +    }
4717 +
4718 +    /* Call reset_cb again. It will release the remote device
4719 +     * from reset, and wait for a while. */
4720 +    VLYNQ_RESETCB(VLYNQ_RESET_DEASSERT);
4721 +
4722 +    if(options & VLYNQ_INIT_CHECK_LINK )
4723 +    {
4724 +        /* Check for link up during initialization*/
4725 +       while( counter < 25 )
4726 +       {
4727 +       /* loop around giving a chance for link status to settle down */
4728 +       counter++;
4729 +        if(vlynq_link_check(pdev))
4730 +        {
4731 +           /* Link is up exit loop*/
4732 +          break;
4733 +        }
4734 +
4735 +       vlynq_delay(4000);
4736 +       }/*end of while counter loop */
4737 +
4738 +        if(!vlynq_link_check(pdev))
4739 +        {
4740 +            /* Handle this case as abort */
4741 +            pdev->state = VLYNQ_DRV_STATE_ERROR;
4742 +            VLYNQ_RESETCB( VLYNQ_RESET_INITFAIL);
4743 +            return VLYNQ_LINK_DOWN;
4744 +        }/* end of if not vlynq_link_check conditional block */
4745 +
4746 +    }/*end of if options & VLYNQ_INIT_CHECK_LINK conditional block */
4747 +
4748 +
4749 +    if (options & VLYNQ_INIT_LOCAL_MEM_REGIONS)
4750 +    {
4751 +        /* Initialise local memory regions . This initialization lets
4752 +         * the local host access remote device memory regions*/
4753 +        int i;
4754 +
4755 +        /* configure the VLYNQ portal window to a PHYSICAL
4756 +         * address of the local CPU */
4757 +        VLYNQ_ALIGN4(pdev->local_mem.Txmap);
4758 +        VLYNQ_TXMAP_REG = (pdev->local_mem.Txmap);
4759 +
4760 +        /*This code assumes input parameter is itself a physical address */
4761 +        for(i=0; i < VLYNQ_MAX_MEMORY_REGIONS ; i++)
4762 +        {
4763 +            /* Physical address on the remote */
4764 +            map = i+1;
4765 +            VLYNQ_R_RXMAP_SIZE_REG(map) =  0;
4766 +            if( pdev->remote_mem.RxSize[i])
4767 +            {
4768 +                VLYNQ_ALIGN4(pdev->remote_mem.RxOffset[i]);
4769 +                VLYNQ_ALIGN4(pdev->remote_mem.RxSize[i]);
4770 +                VLYNQ_R_RXMAP_OFFSET_REG(map) = pdev->remote_mem.RxOffset[i];
4771 +                VLYNQ_R_RXMAP_SIZE_REG(map) = pdev->remote_mem.RxSize[i];
4772 +            }
4773 +        }
4774 +    }
4775 +
4776 +    if(options & VLYNQ_INIT_REMOTE_MEM_REGIONS )
4777 +    {
4778 +        int i;
4779 +
4780 +        /* Initialise remote memory regions. This initialization lets remote
4781 +         * device access local host memory regions. It configures the VLYNQ portal
4782 +         * window to a PHYSICAL address of the remote */
4783 +        VLYNQ_ALIGN4(pdev->remote_mem.Txmap);
4784 +        VLYNQ_R_TXMAP_REG = pdev->remote_mem.Txmap;
4785 +
4786 +        for( i=0; i<VLYNQ_MAX_MEMORY_REGIONS; i++)
4787 +        {
4788 +            /* Physical address on the local */
4789 +            map = i+1;
4790 +            VLYNQ_RXMAP_SIZE_REG(map) =  0;
4791 +            if( pdev->local_mem.RxSize[i])
4792 +            {
4793 +                VLYNQ_ALIGN4(pdev->local_mem.RxOffset[i]);
4794 +                VLYNQ_ALIGN4(pdev->local_mem.RxSize[i]);
4795 +                VLYNQ_RXMAP_OFFSET_REG(map) =  (pdev->local_mem.RxOffset[i]);
4796 +                VLYNQ_RXMAP_SIZE_REG(map) =  (pdev->local_mem.RxSize[i]);
4797 +            }
4798 +        }
4799 +    }
4800 +
4801 +    /* Adapted from original vlynq driver from cable - Calculate VLYNQ bus width */
4802 +    pdev->width = 3 +  VLYNQ_STATUS_FLD_WIDTH(VLYNQ_STATUS_REG)
4803 +                  + VLYNQ_STATUS_FLD_WIDTH(VLYNQ_R_STATUS_REG);
4804 +
4805 +    /* chance to initialize the device, e.g. to boost VLYNQ
4806 +     * clock by modifying pdev->clk_div or and verify the width. */
4807 +    VLYNQ_RESETCB(VLYNQ_RESET_LINKESTABLISH);
4808 +
4809 +    /* Handle VLYNQ clock, HW default (Sense On Reset) is
4810 +     * usually input for all the devices. */
4811 +    if(options & VLYNQ_INIT_CONFIG_CLOCK )
4812 +    {
4813 +        vlynq_configClock(pdev);
4814 +    }
4815 +
4816 +    /* last check for link*/
4817 +    if(options & VLYNQ_INIT_CHECK_LINK )
4818 +    {
4819 +     /* Final Check for link during initialization*/
4820 +       while( counter < 25 )
4821 +       {
4822 +       /* loop around giving a chance for link status to settle down */
4823 +       counter++;
4824 +        if(vlynq_link_check(pdev))
4825 +        {
4826 +           /* Link is up exit loop*/
4827 +          break;
4828 +        }
4829 +
4830 +       vlynq_delay(4000);
4831 +       }/*end of while counter loop */
4832 +
4833 +        if(!vlynq_link_check(pdev))
4834 +        {
4835 +            /* Handle this case as abort */
4836 +            pdev->state = VLYNQ_DRV_STATE_ERROR;
4837 +            VLYNQ_RESETCB( VLYNQ_RESET_INITFAIL);
4838 +            return VLYNQ_LINK_DOWN;
4839 +        }/* end of if not vlynq_link_check conditional block */
4840 +
4841 +    } /* end of if options & VLYNQ_INIT_CHECK_LINK */
4842 +
4843 +    if(options & VLYNQ_INIT_LOCAL_INTERRUPTS )
4844 +    {
4845 +        /* Configure local interrupt settings */
4846 +        intSetting = &(pdev->local_irq);
4847 +
4848 +        /* Map local module status interrupts to interrupt vector*/
4849 +        val = intSetting->map_vector << VLYNQ_CTL_INTVEC_SHIFT ;
4850 +
4851 +        /* enable local module status interrupts */
4852 +        val |= 0x01 << VLYNQ_CTL_INTEN_SHIFT;
4853 +
4854 +        if ( intSetting->intLocal == VLYNQ_INT_LOCAL )
4855 +        {
4856 +            /*set the intLocal bit*/
4857 +            val |= 0x01 << VLYNQ_CTL_INTLOCAL_SHIFT;
4858 +        }
4859 +
4860 +        /* Irrespective of whether interrupts are handled locally, program
4861 +         * int2Cfg. Error checking for accidental loop(when intLocal=0 and int2Cfg=1
4862 +         * i.e remote packets are set intPending register->which will result in
4863 +         * same packet being sent out) has been done already
4864 +         */
4865 +
4866 +        if (intSetting->intRemote == VLYNQ_INT_ROOT_ISR)
4867 +        {
4868 +            /* Set the int2Cfg register, so that remote interrupt
4869 +             * packets are written to intPending register */
4870 +            val |= 0x01 << VLYNQ_CTL_INT2CFG_SHIFT;
4871 +
4872 +            /* Set intPtr register to point to intPending register */
4873 +            VLYNQ_INT_PTR_REG = VLYNQ_INT_PENDING_REG_PTR ;
4874 +        }
4875 +        else
4876 +        {
4877 +            /*set the interrupt pointer register*/
4878 +            VLYNQ_INT_PTR_REG = intSetting->intr_ptr;
4879 +            /* Dont bother to modify int2Cfg as it would be zero */
4880 +        }
4881 +
4882 +        /** Clear bits related to INT settings in control register **/
4883 +        VLYNQ_CTRL_REG = VLYNQ_CTRL_REG & (~VLYNQ_CTL_INTFIELDS_CLEAR_MASK);
4884 +
4885 +        /** Or the bits to be set with Control register **/
4886 +        VLYNQ_CTRL_REG = VLYNQ_CTRL_REG | val;
4887 +
4888 +        /* initialise local ICB */
4889 +        if(vlynqInterruptInit(pdev)==VLYNQ_MEMALLOC_FAIL)
4890 +            return VLYNQ_MEMALLOC_FAIL;
4891 +
4892 +        /* Install handler for local module status interrupts. By default when
4893 +         * local interrupt setting is initialised, the local module status are
4894 +         * enabled and handler hooked up */
4895 +        if(vlynq_install_isr(pdev, intSetting->map_vector, vlynq_local_module_isr,
4896 +                             pdev, NULL, NULL) == VLYNQ_INVALID_ARG)
4897 +            return VLYNQ_INVALID_ARG;
4898 +    } /* end of init local interrupts */
4899 +
4900 +    if(options & VLYNQ_INIT_REMOTE_INTERRUPTS )
4901 +    {
4902 +        /* Configure remote interrupt settings from configuration */
4903 +        intSetting = &(pdev->remote_irq);
4904 +
4905 +        /* Map remote module status interrupts to remote interrupt vector*/
4906 +        val = intSetting->map_vector << VLYNQ_CTL_INTVEC_SHIFT ;
4907 +        /* enable remote module status interrupts */
4908 +        val |= 0x01 << VLYNQ_CTL_INTEN_SHIFT;
4909 +
4910 +        if ( intSetting->intLocal == VLYNQ_INT_LOCAL )
4911 +        {
4912 +            /*set the intLocal bit*/
4913 +            val |= 0x01 << VLYNQ_CTL_INTLOCAL_SHIFT;
4914 +        }
4915 +
4916 +        /* Irrespective of whether interrupts are handled locally, program
4917 +         * int2Cfg. Error checking for accidental loop(when intLocal=0 and int2Cfg=1
4918 +         * i.e remote packets are set intPending register->which will result in
4919 +         * same packet being sent out) has been done already
4920 +        */
4921 +
4922 +        if (intSetting->intRemote == VLYNQ_INT_ROOT_ISR)
4923 +        {
4924 +            /* Set the int2Cfg register, so that remote interrupt
4925 +             * packets are written to intPending register */
4926 +            val |= 0x01 << VLYNQ_CTL_INT2CFG_SHIFT;
4927 +            /* Set intPtr register to point to intPending register */
4928 +            VLYNQ_R_INT_PTR_REG = VLYNQ_R_INT_PENDING_REG_PTR ;
4929 +        }
4930 +        else
4931 +        {
4932 +            /*set the interrupt pointer register*/
4933 +            VLYNQ_R_INT_PTR_REG = intSetting->intr_ptr;
4934 +            /* Dont bother to modify int2Cfg as it would be zero */
4935 +        }
4936 +
4937 +        if( (intSetting->intLocal == VLYNQ_INT_REMOTE) &&
4938 +            (options & VLYNQ_INIT_LOCAL_INTERRUPTS) &&
4939 +            (pdev->local_irq.intRemote == VLYNQ_INT_ROOT_ISR) )
4940 +        {
4941 +            /* Install handler for remote module status interrupts. By default when
4942 +             * remote interrupts are forwarded to local root_isr then remote_module_isr is
4943 +             * enabled and handler hooked up */
4944 +            if(vlynq_install_isr(pdev,intSetting->map_vector,vlynq_remote_module_isr,
4945 +                                 pdev, NULL, NULL) == VLYNQ_INVALID_ARG)
4946 +                return VLYNQ_INVALID_ARG;
4947 +        }
4948 +
4949 +
4950 +        /** Clear bits related to INT settings in control register **/
4951 +        VLYNQ_R_CTRL_REG = VLYNQ_R_CTRL_REG & (~VLYNQ_CTL_INTFIELDS_CLEAR_MASK);
4952 +
4953 +        /** Or the bits to be set with the remote Control register **/
4954 +        VLYNQ_R_CTRL_REG = VLYNQ_R_CTRL_REG | val;
4955 +
4956 +    } /* init remote interrupt settings*/
4957 +
4958 +    if(options & VLYNQ_INIT_CLEAR_ERRORS )
4959 +    {
4960 +        /* Clear errors during initialization */
4961 +        tmp = VLYNQ_STATUS_REG  & (VLYNQ_STS_RERROR_MASK | VLYNQ_STS_LERROR_MASK);
4962 +        VLYNQ_STATUS_REG = tmp;
4963 +        tmp = VLYNQ_R_STATUS_REG & (VLYNQ_STS_RERROR_MASK | VLYNQ_STS_LERROR_MASK);
4964 +        VLYNQ_R_STATUS_REG = tmp;
4965 +    }
4966 +
4967 +    /* clear int status */
4968 +    val = VLYNQ_INT_STAT_REG;
4969 +    VLYNQ_INT_STAT_REG = val;
4970 +
4971 +    /* finish initialization */
4972 +    pdev->state = VLYNQ_DRV_STATE_RUN;
4973 +    VLYNQ_RESETCB( VLYNQ_RESET_INITOK);
4974 +    return VLYNQ_SUCCESS;
4975 +
4976 +}
4977 +
4978 +
4979 +/* ----------------------------------------------------------------------------
4980 + *  Function : vlynqInterruptInit()
4981 + *  Description: This local function is used to set up the ICB table for the
4982 + *  VLYNQ_STATUS_REG vlynq module. The input parameter "pdev" points the vlynq
4983 + *  device instance whose ICB is allocated.
4984 + *  Return : returns VLYNQ_SUCCESS or vlynq error for failure
4985 + * -----------------------------------------------------------------------------
4986 + */
4987 +static int vlynqInterruptInit(VLYNQ_DEV *pdev)
4988 +{
4989 +    int i, numslots;
4990 +
4991 +    /* Memory allocated statically.
4992 +     * Initialise ICB,free list.Indicate primary slot empty.
4993 +     * Intialise intVector <==> map_vector translation table*/
4994 +    for(i=0; i < VLYNQ_NUM_INT_BITS; i++)
4995 +    {
4996 +        pdev->pIntrCB[i].isr = NULL;
4997 +        pdev->pIntrCB[i].next = NULL; /*nothing chained */
4998 +        pdev->vector_map[i] = -1;   /* indicates unmapped  */
4999 +    }
5000 +
5001 +    /* In the ICB slots, [VLYNQ_NUM_INT_BITS i.e 32 to ICB array size) are expansion slots
5002 +     * required only when interrupt chaining/sharing is supported. In case
5003 +     * of chained interrupts the list starts from primary slot and the
5004 +     * additional slots are obtained from the common free area */
5005 +
5006 +    /* Initialise freelist */
5007 +
5008 +    numslots = VLYNQ_NUM_INT_BITS + VLYNQ_IVR_CHAIN_SLOTS;
5009 +
5010 +    if (numslots > VLYNQ_NUM_INT_BITS)
5011 +    {
5012 +        pdev->freelist = &(pdev->pIntrCB[VLYNQ_NUM_INT_BITS]);
5013 +
5014 +        for(i = VLYNQ_NUM_INT_BITS; i < (numslots-1) ; i++)
5015 +        {
5016 +            pdev->pIntrCB[i].next = &(pdev->pIntrCB[i+1]);
5017 +            pdev->pIntrCB[i].isr = NULL;
5018 +        }
5019 +        pdev->pIntrCB[i].next=NULL; /* Indicate end of freelist*/
5020 +        pdev->pIntrCB[i].isr=NULL;
5021 +    }
5022 +    else
5023 +    {
5024 +        pdev->freelist = NULL;
5025 +    }
5026 +
5027 +    /** Reset mapping for IV 0-7 **/
5028 +    VLYNQ_IVR_03TO00_REG = 0;
5029 +    VLYNQ_IVR_07TO04_REG = 0;
5030 +
5031 +    return VLYNQ_SUCCESS;
5032 +}
5033 +
5034 +/** remember that hooking up of root ISR handler with the interrupt controller
5035 + *  is not done as a part of this driver. Typically, it must be done after
5036 + *  invoking vlynq_init*/
5037 +
5038 +
5039 + /* ----------------------------------------------------------------------------
5040 + *  ISR with the SOC interrupt controller. This ISR typically scans
5041 + *  the Int PENDING/SET register in the VLYNQ module and calls the
5042 + *  appropriate ISR associated with the correponding vector number.
5043 + * -----------------------------------------------------------------------------
5044 + */
5045 +void vlynq_root_isr(void *arg)
5046 +{
5047 +    int    source;  /* Bit position of pending interrupt, start from 0 */
5048 +    unsigned int interrupts, clrInterrupts;
5049 +    VLYNQ_DEV * pdev;
5050 +    VLYNQ_INTR_CNTRL_ICB *entry;
5051 +
5052 +    pdev=(VLYNQ_DEV*)(arg);          /*obtain the vlynq device pointer*/
5053 +
5054 +    interrupts =  VLYNQ_INT_STAT_REG; /* Get the list of pending interrupts */
5055 +    VLYNQ_INT_STAT_REG = interrupts; /* clear the int CR register */
5056 +    clrInterrupts = interrupts;      /* save them for further analysis */
5057 +
5058 +    debugPrint("vlynq_root_isr: dev %u. INTCR = 0x%08lx\n", pdev->dev_idx, clrInterrupts,0,0,0,0);
5059 +
5060 +    /* Scan interrupt bits */
5061 +    source =0;
5062 +    while( clrInterrupts != 0)
5063 +    {
5064 +        /* test if bit is set? */
5065 +        if( 0x1ul & clrInterrupts)
5066 +        {
5067 +            entry = &(pdev->pIntrCB[source]);   /* Get the ISR entry */
5068 +            pdev->intCount++;                   /* update interrupt count */
5069 +            if(entry->isr != NULL)
5070 +            {
5071 +                do
5072 +                {
5073 +                    pdev->isrCount++;   /* update isr invocation count */
5074 +                    /* Call the user ISR and update the count for ISR */
5075 +                   entry->isrCount++;
5076 +                    entry->isr(entry->arg1, entry->arg2, entry->arg3);
5077 +                    if (entry->next == NULL) break;
5078 +                    entry = entry->next;
5079 +
5080 +                } while (entry->isr != NULL);
5081 +            }
5082 +            else
5083 +            {
5084 +                debugPrint(" ISR not installed for vlynq vector:%d\n",source,0,0,0,0,0);
5085 +            }
5086 +        }
5087 +        clrInterrupts >>= 1;    /* Next source bit */
5088 +        ++source;
5089 +    } /* endWhile clrInterrupts != 0 */
5090 +}
5091 +
5092 +
5093 + /* ----------------------------------------------------------------------------
5094 + *  Function : vlynq_local__module_isr()
5095 + *  Description: This ISR is attached to the local VLYNQ interrupt vector
5096 + *  by the Vlynq Driver when local interrupts are being handled. i.e.
5097 + *  intLocal=1. This ISR handles local Vlynq module status interrupts only
5098 + *  AS a part of this ISR, user callback in VLYNQ_DEV structure
5099 + *  is invoked.
5100 + *  VLYNQ_DEV is passed as arg1. arg2 and arg3 are unused.
5101 + * -----------------------------------------------------------------------------
5102 + */
5103 +static void vlynq_local_module_isr(void *arg1,void *arg2, void *arg3)
5104 +{
5105 +    VLYNQ_REPORT_CB func;
5106 +    unsigned int dwStatRegVal;
5107 +    VLYNQ_DEV * pdev;
5108 +
5109 +    pdev = (VLYNQ_DEV*) arg1;
5110 +    /* Callback function is read from the device pointer that is passed as an argument */
5111 +    func = pdev->report_cb;
5112 +
5113 +    /* read local status register */
5114 +    dwStatRegVal = VLYNQ_STATUS_REG;
5115 +
5116 +    /* clear pending events */
5117 +    VLYNQ_STATUS_REG = dwStatRegVal;
5118 +
5119 +    /* invoke user callback */
5120 +    if( func != NULL)
5121 +        func( pdev, VLYNQ_LOCAL_DVC, dwStatRegVal);
5122 +
5123 +}
5124 +
5125 + /* ----------------------------------------------------------------------------
5126 + *  Function : vlynq_remote_module_isr()
5127 + *  Description: This ISR is attached to the remote VLYNQ interrupt vector
5128 + *  by the Vlynq Driver when remote interrupts are being handled locally. i.e.
5129 + *  intLocal=1. This ISR handles local Vlynq module status interrupts only
5130 + *  AS a part of this ISR, user callback in VLYNQ_DEV structure
5131 + *  is invoked.
5132 + *  The parameters  irq,regs ar unused.
5133 + * -----------------------------------------------------------------------------
5134 + */
5135 +static void vlynq_remote_module_isr(void *arg1,void *arg2, void *arg3)
5136 +{
5137 +    VLYNQ_REPORT_CB func;
5138 +    unsigned int dwStatRegVal;
5139 +    VLYNQ_DEV * pdev;
5140 +
5141 +
5142 +    pdev = (VLYNQ_DEV*) arg1;
5143 +
5144 +    /* Callback function is read from the device pointer that is passed as an argument */
5145 +   func = pdev->report_cb;
5146 +
5147 +    /* read local status register */
5148 +    dwStatRegVal = VLYNQ_R_STATUS_REG;
5149 +
5150 +    /* clear pending events */
5151 +    VLYNQ_R_STATUS_REG = dwStatRegVal;
5152 +
5153 +    /* invoke user callback */
5154 +    if( func != NULL)
5155 +        func( pdev, VLYNQ_REMOTE_DVC, dwStatRegVal);
5156 +
5157 +}
5158 +
5159 +/* ----------------------------------------------------------------------------
5160 + *  Function : vlynq_interrupt_get_count()
5161 + *  Description: This function returns the number of times a particular intr
5162 + *  has been invoked.
5163 + *
5164 + *  It returns 0, if erroneous map_vector is specified or if the corres isr
5165 + *  has not been registered with VLYNQ.
5166 + */
5167 +unsigned int vlynq_interrupt_get_count(VLYNQ_DEV *pdev,
5168 +                                       unsigned int map_vector)
5169 +{
5170 +    VLYNQ_INTR_CNTRL_ICB *entry;
5171 +    unsigned int count = 0;
5172 +
5173 +    if (map_vector > (VLYNQ_NUM_INT_BITS-1))
5174 +        return count;
5175 +
5176 +    entry = &(pdev->pIntrCB[map_vector]);
5177 +
5178 +    if (entry)
5179 +        count = entry->isrCount;
5180 +
5181 +    return (count);
5182 +}
5183 +
5184 +
5185 +/* ----------------------------------------------------------------------------
5186 + *  Function : vlynq_install_isr()
5187 + *  Description: This function installs ISR for Vlynq interrupt vector
5188 + *  bits(in IntPending register). This function should be used only when
5189 + *  Vlynq interrupts are being handled locally(remote may be programmed to send
5190 + *  interrupt packets).Also, the int2cfg should be 1 and the least significant
5191 + *  8 bits of the Interrupt Pointer Register must point to Interrupt
5192 + *  Pending/Set Register).
5193 + *  If host int2cfg=0 and the Interrupt Pointer register contains
5194 + *  the address of the interrupt set register in the interrupt controller
5195 + *  module of the local device , then the ISR for the remote interrupt must be
5196 + *  directly registered with the Interrupt controller and must not use this API
5197 + *  Note: this function simply installs the ISR in ICB It doesnt modify
5198 + *  any register settings
5199 + */
5200 +int
5201 +vlynq_install_isr(VLYNQ_DEV *pdev,
5202 +                  unsigned int map_vector,
5203 +                  VLYNQ_INTR_CNTRL_ISR isr,
5204 +                  void *arg1, void *arg2, void *arg3)
5205 +{
5206 +    VLYNQ_INTR_CNTRL_ICB *entry;
5207 +
5208 +    if ( (map_vector > (VLYNQ_NUM_INT_BITS-1)) || (isr == NULL) )
5209 +        return VLYNQ_INVALID_ARG;
5210 +
5211 +    entry = &(pdev->pIntrCB[map_vector]);
5212 +
5213 +    if(entry->isr == NULL)
5214 +    {
5215 +        entry->isr = isr;
5216 +        entry->arg1 = arg1;
5217 +        entry->arg2 = arg2;
5218 +        entry->arg3 = arg3;
5219 +        entry->next = NULL;
5220 +    }
5221 +    else
5222 +    {
5223 +        /** No more empty slots,return error */
5224 +        if(pdev->freelist == NULL)
5225 +            return VLYNQ_MEMALLOC_FAIL;
5226 +
5227 +        while(entry->next != NULL)
5228 +        {
5229 +            entry = entry->next;
5230 +        }
5231 +
5232 +        /* Append new node to the chain */
5233 +        entry->next = pdev->freelist;
5234 +        /* Remove the appended node from freelist */
5235 +        pdev->freelist = pdev->freelist->next;
5236 +        entry= entry->next;
5237 +
5238 +        /*** Set the ICB fields ***/
5239 +        entry->isr = isr;
5240 +        entry->arg1 = arg1;
5241 +        entry->arg2 = arg2;
5242 +        entry->arg3 = arg3;
5243 +        entry->next = NULL;
5244 +    }
5245 +
5246 +    return VLYNQ_SUCCESS;
5247 +}
5248 +
5249 +
5250 +
5251 +/* ----------------------------------------------------------------------------
5252 + *  Function : vlynq_uninstall_isr
5253 + *  Description: This function is used to uninstall a previously
5254 + *  registered ISR. In case of shared/chained interrupts, the
5255 + *  void * arg parameter must uniquely identify the ISR to be
5256 + *  uninstalled.
5257 + *  Note: this function simply uninstalls the ISR in ICB
5258 + *  It doesnt modify any register settings
5259 + */
5260 +int
5261 +vlynq_uninstall_isr(VLYNQ_DEV *pdev,
5262 +                    unsigned int map_vector,
5263 +                    void *arg1, void *arg2, void *arg3)
5264 +{
5265 +    VLYNQ_INTR_CNTRL_ICB *entry,*temp;
5266 +
5267 +    if (map_vector > (VLYNQ_NUM_INT_BITS-1))
5268 +        return VLYNQ_INVALID_ARG;
5269 +
5270 +    entry = &(pdev->pIntrCB[map_vector]);
5271 +
5272 +    if(entry->isr == NULL )
5273 +        return VLYNQ_ISR_NON_EXISTENT;
5274 +
5275 +    if ( (entry->arg1 == arg1) && (entry->arg2 == arg2) && (entry->arg3 == arg3) )
5276 +    {
5277 +        if(entry->next == NULL)
5278 +        {
5279 +            entry->isr=NULL;
5280 +            return VLYNQ_SUCCESS;
5281 +        }
5282 +        else
5283 +        {
5284 +            temp =  entry->next;
5285 +            /* Copy next node in the chain to prim.slot */
5286 +            entry->isr = temp->isr;
5287 +            entry->arg1 = temp->arg1;
5288 +            entry->arg2 = temp->arg2;
5289 +            entry->arg3 = temp->arg3;
5290 +            entry->next = temp->next;
5291 +            /* Free the just copied node */
5292 +            temp->isr = NULL;
5293 +            temp->arg1 = NULL;
5294 +            temp->arg2 = NULL;
5295 +            temp->arg3 = NULL;
5296 +            temp->next = pdev->freelist;
5297 +            pdev->freelist = temp;
5298 +            return VLYNQ_SUCCESS;
5299 +        }
5300 +    }
5301 +    else
5302 +    {
5303 +        temp = entry;
5304 +        while ( (entry = temp->next) != NULL)
5305 +        {
5306 +            if ( (entry->arg1 == arg1) && (entry->arg2 == arg2) && (entry->arg3 == arg3) )
5307 +            {
5308 +                /* remove node from chain */
5309 +                temp->next = entry->next;
5310 +                /* Add the removed node to freelist */
5311 +                entry->isr = NULL;
5312 +                entry->arg1 = NULL;
5313 +                entry->arg2 = NULL;
5314 +                entry->arg3 = NULL;
5315 +                entry->next = pdev->freelist;
5316 +                entry->isrCount = 0;
5317 +                pdev->freelist  = entry;
5318 +                return VLYNQ_SUCCESS;
5319 +            }
5320 +            temp = entry;
5321 +        }
5322 +
5323 +        return VLYNQ_ISR_NON_EXISTENT;
5324 +    }
5325 +}
5326 +
5327 +
5328 +
5329 +
5330 +/* ----------------------------------------------------------------------------
5331 + *  function : vlynq_interrupt_vector_set()
5332 + *  description:configures interrupt vector mapping,interrupt type
5333 + *  polarity -all in one go.
5334 + */
5335 +int
5336 +vlynq_interrupt_vector_set(VLYNQ_DEV *pdev,                 /* vlynq device */
5337 +                           unsigned int int_vector,               /* int vector on vlynq device */
5338 +                           unsigned int map_vector,               /* bit for this interrupt */
5339 +                           VLYNQ_DEV_TYPE dev_type,         /* local or remote device */
5340 +                           VLYNQ_INTR_POLARITY pol,         /* polarity of interrupt */
5341 +                           VLYNQ_INTR_TYPE type)            /* pulsed/level interrupt */
5342 +{
5343 +    volatile unsigned int * vecreg;
5344 +    unsigned int val=0;
5345 +    unsigned int bytemask=0XFF;
5346 +
5347 +    /* use the lower 8 bits of val to set the value , shift it to
5348 +     * appropriate byte position in the ivr and write it to the
5349 +     * corresponding register */
5350 +
5351 +    /* validate the number of interrupts supported */
5352 +    if (int_vector >= VLYNQ_IVR_MAXIVR)
5353 +        return VLYNQ_INVALID_ARG;
5354 +
5355 +    if(map_vector > (VLYNQ_NUM_INT_BITS - 1) )
5356 +        return VLYNQ_INVALID_ARG;
5357 +
5358 +    if (dev_type == VLYNQ_LOCAL_DVC)
5359 +    {
5360 +        vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5361 +    }
5362 +    else
5363 +    {
5364 +        vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5365 +    }
5366 +
5367 +    /* Update the intVector<==> bit position translation table */
5368 +    pdev->vector_map[map_vector] = int_vector;
5369 +
5370 +    /* val has been initialised to zero. we only have to turn on appropriate bits*/
5371 +    if(type == VLYNQ_INTR_PULSED)
5372 +        val |= VLYNQ_IVR_INTTYPE_MASK;
5373 +
5374 +    if(pol == VLYNQ_INTR_ACTIVE_LOW)
5375 +        val |= VLYNQ_IVR_INTPOL_MASK;
5376 +
5377 +    val |= map_vector;
5378 +
5379 +    /** clear the correct byte position and then or val **/
5380 +    *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5381 +
5382 +    /** write to correct byte position in vecreg*/
5383 +    *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
5384 +
5385 +    /* Setting a interrupt vector, leaves the interrupt disabled
5386 +     * which  must be enabled subsequently */
5387 +
5388 +    return VLYNQ_SUCCESS;
5389 +}
5390 +
5391 +
5392 +/* ----------------------------------------------------------------------------
5393 + *  Function : vlynq_interrupt_vector_cntl()
5394 + *  Description:enables/disable interrupt
5395 + */
5396 +int vlynq_interrupt_vector_cntl( VLYNQ_DEV *pdev,
5397 +                                          unsigned int int_vector,
5398 +                                          VLYNQ_DEV_TYPE dev_type,
5399 +                                          unsigned int enable)
5400 +{
5401 +    volatile unsigned int *vecReg;
5402 +    unsigned int val=0;
5403 +    unsigned int intenMask=0x80;
5404 +
5405 +    /* validate the number of interrupts supported */
5406 +    if (int_vector >= VLYNQ_IVR_MAXIVR)
5407 +        return VLYNQ_INVALID_ARG;
5408 +
5409 +    if (dev_type == VLYNQ_LOCAL_DVC)
5410 +    {
5411 +        vecReg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5412 +    }
5413 +    else
5414 +    {
5415 +        vecReg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5416 +    }
5417 +
5418 +    /** Clear the correct byte position and then or val **/
5419 +    *vecReg = (*vecReg) & ( ~(intenMask << ( (int_vector %4)*8) ) );
5420 +
5421 +    if(enable)
5422 +    {
5423 +        val |= VLYNQ_IVR_INTEN_MASK;
5424 +        /** Write to correct byte position in vecReg*/
5425 +        *vecReg = (*vecReg) | (val << ( (int_vector % 4)*8) ) ;
5426 +    }
5427 +
5428 +    return VLYNQ_SUCCESS;
5429 +
5430 +}/* end of function vlynq_interrupt_vector_cntl */
5431 +
5432 +
5433 +
5434 +/* ----------------------------------------------------------------------------
5435 + *  Function : vlynq_interrupt_vector_map()
5436 + *  Description:Configures interrupt vector mapping alone
5437 + */
5438 +int
5439 +vlynq_interrupt_vector_map( VLYNQ_DEV *pdev,
5440 +                            VLYNQ_DEV_TYPE dev_type,
5441 +                            unsigned int int_vector,
5442 +                            unsigned int map_vector)
5443 +{
5444 +    volatile unsigned int * vecreg;
5445 +    unsigned int val=0;
5446 +    unsigned int bytemask=0x1f;   /* mask to turn off bits corresponding to int vector */
5447 +
5448 +    /* use the lower 8 bits of val to set the value , shift it to
5449 +     * appropriate byte position in the ivr and write it to the
5450 +     * corresponding register */
5451 +
5452 +    /* validate the number of interrupts supported */
5453 +    if (int_vector >= VLYNQ_IVR_MAXIVR)
5454 +        return VLYNQ_INVALID_ARG;
5455 +
5456 +    if(map_vector > (VLYNQ_NUM_INT_BITS - 1) )
5457 +        return VLYNQ_INVALID_ARG;
5458 +
5459 +    if (dev_type == VLYNQ_LOCAL_DVC)
5460 +    {
5461 +        vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5462 +    }
5463 +    else
5464 +    {
5465 +        vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5466 +    }
5467 +
5468 +    /* Update the intVector<==> bit position translation table */
5469 +    pdev->vector_map[map_vector] = int_vector;
5470 +
5471 +    /** val has been initialised to zero. we only have to turn on
5472 +     * appropriate bits*/
5473 +    val |= map_vector;
5474 +
5475 +    /** clear the correct byte position and then or val **/
5476 +    *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5477 +
5478 +    /** write to correct byte position in vecreg*/
5479 +    *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
5480 +
5481 +    return VLYNQ_SUCCESS;
5482 +}
5483 +
5484 +
5485 +/* ----------------------------------------------------------------------------
5486 + *  function : vlynq_interrupt_set_polarity()
5487 + *  description:configures interrupt polarity .
5488 + */
5489 +int
5490 +vlynq_interrupt_set_polarity( VLYNQ_DEV *pdev ,
5491 +                              VLYNQ_DEV_TYPE dev_type,
5492 +                              unsigned int map_vector,
5493 +                              VLYNQ_INTR_POLARITY pol)
5494 +{
5495 +    volatile unsigned int * vecreg;
5496 +    int int_vector;
5497 +    unsigned int val=0;
5498 +    unsigned int bytemask=0x20; /** mask to turn off bits corresponding to int polarity */
5499 +
5500 +    /* get the int_vector from map_vector */
5501 +    int_vector = pdev->vector_map[map_vector];
5502 +
5503 +    if(int_vector == -1)
5504 +        return VLYNQ_INTVEC_MAP_NOT_FOUND;
5505 +
5506 +    /* use the lower 8 bits of val to set the value , shift it to
5507 +     * appropriate byte position in the ivr and write it to the
5508 +     * corresponding register */
5509 +
5510 +    if (dev_type == VLYNQ_LOCAL_DVC)
5511 +    {
5512 +        vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5513 +    }
5514 +    else
5515 +    {
5516 +        vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5517 +    }
5518 +
5519 +    /* val has been initialised to zero. we only have to turn on
5520 +     * appropriate bits, if need be*/
5521 +
5522 +    /** clear the correct byte position and then or val **/
5523 +    *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5524 +
5525 +    if( pol == VLYNQ_INTR_ACTIVE_LOW)
5526 +    {
5527 +        val |= VLYNQ_IVR_INTPOL_MASK;
5528 +        /** write to correct byte position in vecreg*/
5529 +        *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
5530 +    }
5531 +
5532 +    return VLYNQ_SUCCESS;
5533 +}
5534 +
5535 +int vlynq_interrupt_get_polarity( VLYNQ_DEV *pdev ,
5536 +                                           VLYNQ_DEV_TYPE dev_type,
5537 +                                           unsigned int map_vector)
5538 +{
5539 +    volatile unsigned int * vecreg;
5540 +    int int_vector;
5541 +    unsigned int val=0;
5542 +
5543 +    /* get the int_vector from map_vector */
5544 +    int_vector = pdev->vector_map[map_vector];
5545 +
5546 +    if (map_vector > (VLYNQ_NUM_INT_BITS-1))
5547 +        return(-1);
5548 +
5549 +    if(int_vector == -1)
5550 +        return VLYNQ_INTVEC_MAP_NOT_FOUND;
5551 +
5552 +    /* use the lower 8 bits of val to set the value , shift it to
5553 +     * appropriate byte position in the ivr and write it to the
5554 +     * corresponding register */
5555 +
5556 +    if (dev_type == VLYNQ_LOCAL_DVC)
5557 +    {
5558 +        vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5559 +    }
5560 +    else
5561 +    {
5562 +        vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5563 +    }
5564 +
5565 +    /** read the information into val **/
5566 +    val = (*vecreg) & ((VLYNQ_IVR_INTPOL_MASK << ( (int_vector %4)*8) ) );
5567 +
5568 +    return (val ? (VLYNQ_INTR_ACTIVE_LOW) : (VLYNQ_INTR_ACTIVE_HIGH));
5569 +}
5570 +
5571 +
5572 +/* ----------------------------------------------------------------------------
5573 + *  function : vlynq_interrupt_set_type()
5574 + *  description:configures interrupt type .
5575 + */
5576 +int vlynq_interrupt_set_type( VLYNQ_DEV *pdev,
5577 +                                       VLYNQ_DEV_TYPE dev_type,
5578 +                                       unsigned int map_vector,
5579 +                                       VLYNQ_INTR_TYPE type)
5580 +{
5581 +    volatile unsigned int * vecreg;
5582 +    unsigned int val=0;
5583 +    int int_vector;
5584 +
5585 +    /** mask to turn off bits corresponding to interrupt type */
5586 +    unsigned int bytemask=0x40;
5587 +
5588 +    /* get the int_vector from map_vector */
5589 +    int_vector = pdev->vector_map[map_vector];
5590 +    if(int_vector == -1)
5591 +        return VLYNQ_INTVEC_MAP_NOT_FOUND;
5592 +
5593 +    /* use the lower 8 bits of val to set the value , shift it to
5594 +     * appropriate byte position in the ivr and write it to the
5595 +     * corresponding register */
5596 +    if (dev_type == VLYNQ_LOCAL_DVC)
5597 +    {
5598 +        vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5599 +    }
5600 +    else
5601 +    {
5602 +        vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5603 +    }
5604 +
5605 +    /** val has been initialised to zero. we only have to turn on
5606 +     * appropriate bits if need be*/
5607 +
5608 +     /** clear the correct byte position and then or val **/
5609 +    *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5610 +
5611 +    if( type == VLYNQ_INTR_PULSED)
5612 +    {
5613 +        val |= VLYNQ_IVR_INTTYPE_MASK;
5614 +        /** write to correct byte position in vecreg*/
5615 +        *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
5616 +    }
5617 +
5618 +    return VLYNQ_SUCCESS;
5619 +}
5620 +
5621 +/* ----------------------------------------------------------------------------
5622 + *  function : vlynq_interrupt_get_type()
5623 + *  description:returns interrupt type .
5624 + */
5625 +int vlynq_interrupt_get_type( VLYNQ_DEV *pdev, VLYNQ_DEV_TYPE dev_type,
5626 +                                       unsigned int map_vector)
5627 +{
5628 +    volatile unsigned int * vecreg;
5629 +    unsigned int val=0;
5630 +    int int_vector;
5631 +
5632 +    if (map_vector > (VLYNQ_NUM_INT_BITS-1))
5633 +        return(-1);
5634 +
5635 +    /* get the int_vector from map_vector */
5636 +    int_vector = pdev->vector_map[map_vector];
5637 +    if(int_vector == -1)
5638 +        return VLYNQ_INTVEC_MAP_NOT_FOUND;
5639 +
5640 +    /* use the lower 8 bits of val to set the value , shift it to
5641 +     * appropriate byte position in the ivr and write it to the
5642 +     * corresponding register */
5643 +    if (dev_type == VLYNQ_LOCAL_DVC)
5644 +    {
5645 +        vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5646 +    }
5647 +    else
5648 +    {
5649 +        vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5650 +    }
5651 +
5652 +    /** Read the correct bit position into val **/
5653 +    val = (*vecreg) & ((VLYNQ_IVR_INTTYPE_MASK << ( (int_vector %4)*8) ) );
5654 +
5655 +    return (val ? (VLYNQ_INTR_PULSED) : (VLYNQ_INTR_LEVEL));
5656 +}
5657 +
5658 +/* ----------------------------------------------------------------------------
5659 + *  function : vlynq_interrupt_enable()
5660 + *  description:Enable interrupt by writing to IVR register.
5661 + */
5662 +int vlynq_interrupt_enable( VLYNQ_DEV *pdev,
5663 +                                     VLYNQ_DEV_TYPE dev_type,
5664 +                                     unsigned int map_vector)
5665 +{
5666 +    volatile unsigned int * vecreg;
5667 +    unsigned int val=0;
5668 +    int int_vector;
5669 +
5670 +    /** mask to turn off bits corresponding to interrupt enable */
5671 +    unsigned int bytemask=0x80;
5672 +
5673 +    /* get the int_vector from map_vector */
5674 +    int_vector = pdev->vector_map[map_vector];
5675 +    if(int_vector == -1)
5676 +        return VLYNQ_INTVEC_MAP_NOT_FOUND;
5677 +
5678 +    /* use the lower 8 bits of val to set the value , shift it to
5679 +     * appropriate byte position in the ivr and write it to the
5680 +     * corresponding register */
5681 +
5682 +    if (dev_type == VLYNQ_LOCAL_DVC)
5683 +    {
5684 +        vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5685 +    }
5686 +    else
5687 +    {
5688 +        vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5689 +    }
5690 +
5691 +    /** val has been initialised to zero. we only have to turn on
5692 +    *  bit corresponding to interrupt enable*/
5693 +    val |= VLYNQ_IVR_INTEN_MASK;
5694 +
5695 +    /** clear the correct byte position and then or val **/
5696 +    *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5697 +
5698 +    /** write to correct byte position in vecreg*/
5699 +    *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
5700 +
5701 +    return VLYNQ_SUCCESS;
5702 +}
5703 +
5704 +
5705 +/* ----------------------------------------------------------------------------
5706 + *  function : vlynq_interrupt_disable()
5707 + *  description:Disable interrupt by writing to IVR register.
5708 + */
5709 +int
5710 +vlynq_interrupt_disable( VLYNQ_DEV *pdev,
5711 +                         VLYNQ_DEV_TYPE dev_type,
5712 +                         unsigned int map_vector)
5713 +{
5714 +    volatile unsigned int * vecreg;
5715 +    int int_vector;
5716 +
5717 +    /** mask to turn off bits corresponding to interrupt enable */
5718 +    unsigned int bytemask=0x80;
5719 +
5720 +    /* get the int_vector from map_vector */
5721 +    int_vector = pdev->vector_map[map_vector];
5722 +    if(int_vector == -1)
5723 +        return VLYNQ_INTVEC_MAP_NOT_FOUND;
5724 +
5725 +    /* use the lower 8 bits of val to set the value , shift it to
5726 +     * appropriate byte position in the ivr and write it to the
5727 +     * corresponding register */
5728 +    if (dev_type == VLYNQ_LOCAL_DVC)
5729 +    {
5730 +        vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5731 +    }
5732 +    else
5733 +    {
5734 +        vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5735 +    }
5736 +
5737 +    /* We disable the interrupt by simply turning off the bit
5738 +     * corresponding to Interrupt enable.
5739 +     * Clear the interrupt enable bit in the correct byte position **/
5740 +    *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5741 +
5742 +    /* Dont have to set any bit positions */
5743 +
5744 +    return VLYNQ_SUCCESS;
5745 +
5746 +}
5747 +
5748 +
5749 +
5750 +
5751 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
5752 --- linux.old/drivers/char/serial.c     2005-10-21 16:43:20.709226000 +0200
5753 +++ linux.dev/drivers/char/serial.c     2005-11-10 01:10:46.015585250 +0100
5754 @@ -419,7 +419,40 @@
5755         return 0;
5756  }
5757
5758 -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
5759 +#if defined(CONFIG_AR7)
5760 +
5761 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
5762 +{
5763 +       return (inb(info->port + (offset * 4)) & 0xff);
5764 +}
5765 +
5766 +
5767 +static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
5768 +{
5769 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
5770 +       return (inb(info->port + (offset * 4)) & 0xff);
5771 +#else
5772 +       return (inb_p(info->port + (offset * 4)) & 0xff);
5773 +#endif
5774 +}
5775 +
5776 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
5777 +{
5778 +       outb(value, info->port + (offset * 4));
5779 +}
5780 +
5781 +
5782 +static _INLINE_ void serial_outp(struct async_struct *info, int offset,
5783 +               int value)
5784 +{
5785 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
5786 +       outb(value, info->port + (offset * 4));
5787 +#else
5788 +       outb_p(value, info->port + (offset * 4));
5789 +#endif
5790 +}
5791 +
5792 +#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
5793
5794  #include <asm/mips-boards/atlas.h>
5795
5796 @@ -478,8 +511,10 @@
5797   * needed for certain old 386 machines, I've left these #define's
5798   * in....
5799   */
5800 +#ifndef CONFIG_AR7
5801  #define serial_inp(info, offset)               serial_in(info, offset)
5802  #define serial_outp(info, offset, value)       serial_out(info, offset, value)
5803 +#endif
5804
5805
5806  /*
5807 @@ -1728,7 +1763,15 @@
5808                         /* Special case since 134 is really 134.5 */
5809                         quot = (2*baud_base / 269);
5810                 else if (baud)
5811 +#ifdef CONFIG_AR7
5812 +                       quot = (CONFIG_AR7_SYS*500000) / baud;
5813 +
5814 +               if ((quot%16)>7)
5815 +                       quot += 8;
5816 +               quot /=16;
5817 +#else
5818                         quot = baud_base / baud;
5819 +#endif
5820         }
5821         /* If the quotient is zero refuse the change */
5822         if (!quot && old_termios) {
5823 @@ -5540,8 +5583,10 @@
5824                 state->irq = irq_cannonicalize(state->irq);
5825                 if (state->hub6)
5826                         state->io_type = SERIAL_IO_HUB6;
5827 +#ifndef CONFIG_AR7
5828                 if (state->port && check_region(state->port,8))
5829                         continue;
5830 +#endif
5831  #ifdef CONFIG_MCA
5832                 if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
5833                         continue;
5834 @@ -5997,7 +6042,15 @@
5835         info->io_type = state->io_type;
5836         info->iomem_base = state->iomem_base;
5837         info->iomem_reg_shift = state->iomem_reg_shift;
5838 +#ifdef CONFIG_AR7
5839 +       quot = (CONFIG_AR7_SYS*500000) / baud;
5840 +
5841 +       if ((quot%16)>7)
5842 +               quot += 8;
5843 +       quot /=16;
5844 +#else
5845         quot = state->baud_base / baud;
5846 +#endif
5847         cval = cflag & (CSIZE | CSTOPB);
5848  #if defined(__powerpc__) || defined(__alpha__)
5849         cval >>= 8;
5850 diff -urN linux.old/drivers/char/ticfg/Makefile linux.dev/drivers/char/ticfg/Makefile
5851 --- linux.old/drivers/char/ticfg/Makefile       1970-01-01 01:00:00.000000000 +0100
5852 +++ linux.dev/drivers/char/ticfg/Makefile       2005-11-10 01:10:46.051587500 +0100
5853 @@ -0,0 +1,6 @@
5854 +
5855 +O_TARGET := ticfg.o
5856 +
5857 +obj-$(CONFIG_AR7_ADAM2) := adam2_env.o
5858 +
5859 +include $(TOPDIR)/Rules.make
5860 diff -urN linux.old/drivers/char/ticfg/adam2_env.c linux.dev/drivers/char/ticfg/adam2_env.c
5861 --- linux.old/drivers/char/ticfg/adam2_env.c    1970-01-01 01:00:00.000000000 +0100
5862 +++ linux.dev/drivers/char/ticfg/adam2_env.c    2005-11-10 01:10:46.051587500 +0100
5863 @@ -0,0 +1,85 @@
5864 +#include <linux/types.h>
5865 +#include <linux/errno.h>
5866 +#include <linux/module.h>
5867 +#include <linux/kernel.h>
5868 +#include <linux/proc_fs.h>
5869 +#include <linux/fcntl.h>
5870 +#include <linux/init.h>
5871 +
5872 +#include <asm/ar7/adam2_env.h>
5873 +
5874 +#undef ADAM2_ENV_DEBUG
5875 +
5876 +#ifdef ADAM2_ENV_DEBUG
5877 +#define DPRINTK(args...) do { printk(args); } while(0);
5878 +#else
5879 +#define DPRINTK(args...) do { } while(0);
5880 +#endif
5881 +
5882 +#define ADAM2_ENV_DIR  "ticfg"
5883 +#define ADAM2_ENV_NAME "env"
5884 +
5885 +static struct proc_dir_entry *adam2_env_proc_dir;
5886 +static struct proc_dir_entry *adam2_env_proc_ent;
5887 +
5888 +static int
5889 +adam2_proc_read_env(char *page, char **start, off_t pos, int count,
5890 +                   int *eof, void *data)
5891 +{
5892 +       int len;
5893 +       t_env_var *env;
5894 +
5895 +       if (pos > 0)
5896 +               return 0;
5897 +
5898 +       len=0;
5899 +       for (env = prom_iterenv(0); env; env = prom_iterenv(env)) {
5900 +               if (env->val) {
5901 +                       /* XXX check for page len */
5902 +                       len += sprintf(page + len, "%s\t%s\n",
5903 +                                      env->name, env->val);
5904 +               }
5905 +       }
5906 +
5907 +       *eof=1;
5908 +       return len;
5909 +}
5910 +
5911 +static int __init
5912 +adam2_env_init(void)
5913 +{
5914 +
5915 +       DPRINTK("%s\n", __FUNCTION__);
5916 +
5917 +       adam2_env_proc_dir = proc_mkdir(ADAM2_ENV_DIR, NULL);
5918 +       if (!adam2_env_proc_dir) {
5919 +               printk(KERN_ERR "%s: Unable to create /proc/%s entry\n",
5920 +                      __FUNCTION__, ADAM2_ENV_DIR);
5921 +               return -ENOMEM;
5922 +       }
5923 +
5924 +       adam2_env_proc_ent =
5925 +               create_proc_entry(ADAM2_ENV_NAME, 0444, adam2_env_proc_dir);
5926 +       if (!adam2_env_proc_ent) {
5927 +               printk(KERN_ERR "%s: Unable to create /proc/%s/%s entry\n",
5928 +                      __FUNCTION__, ADAM2_ENV_DIR, ADAM2_ENV_NAME);
5929 +               remove_proc_entry(ADAM2_ENV_DIR, NULL);
5930 +               return -ENOMEM;
5931 +       }
5932 +       adam2_env_proc_ent->read_proc = adam2_proc_read_env;
5933 +
5934 +       return 0;
5935 +}
5936 +
5937 +static
5938 +void __exit
5939 +adam2_env_cleanup(void)
5940 +{
5941 +       remove_proc_entry(ADAM2_ENV_NAME, adam2_env_proc_dir);
5942 +       remove_proc_entry(ADAM2_ENV_DIR, NULL);
5943 +}
5944 +
5945 +module_init(adam2_env_init);
5946 +module_exit(adam2_env_cleanup);
5947 +
5948 +MODULE_LICENSE("GPL");
5949 diff -urN linux.old/include/asm-mips/addrspace.h linux.dev/include/asm-mips/addrspace.h
5950 --- linux.old/include/asm-mips/addrspace.h      2002-11-29 00:53:15.000000000 +0100
5951 +++ linux.dev/include/asm-mips/addrspace.h      2005-11-10 01:14:16.400733500 +0100
5952 @@ -11,6 +11,8 @@
5953  #ifndef __ASM_MIPS_ADDRSPACE_H
5954  #define __ASM_MIPS_ADDRSPACE_H
5955
5956 +#include <linux/config.h>
5957 +
5958  /*
5959   *  Configure language
5960   */
5961 @@ -102,4 +104,11 @@
5962  #define XKPHYS_TO_PHYS(p)              ((p) & TO_PHYS_MASK)
5963  #define PHYS_TO_XKPHYS(cm,a)           (0x8000000000000000 | ((cm)<<59) | (a))
5964
5965 +#ifdef CONFIG_AR7_MEMORY
5966 +#define PHYS_OFFSET    ((unsigned long)(CONFIG_AR7_MEMORY))
5967 +#else
5968 +#define PHYS_OFFSET    (0)
5969 +#endif
5970 +#define PHYS_PFN_OFFSET        (PHYS_OFFSET >> PAGE_SHIFT)
5971 +
5972  #endif /* __ASM_MIPS_ADDRSPACE_H */
5973 diff -urN linux.old/include/asm-mips/ar7/adam2_env.h linux.dev/include/asm-mips/ar7/adam2_env.h
5974 --- linux.old/include/asm-mips/ar7/adam2_env.h  1970-01-01 01:00:00.000000000 +0100
5975 +++ linux.dev/include/asm-mips/ar7/adam2_env.h  2005-11-10 01:10:46.067588500 +0100
5976 @@ -0,0 +1,13 @@
5977 +#ifndef _INCLUDE_ASM_AR7_ADAM2_ENV_H_
5978 +#define        _INCLUDE_ASM_AR7_ADAM2_ENV_H_
5979 +
5980 +/* Environment variable */
5981 +typedef struct {
5982 +       char *name;
5983 +       char *val;
5984 +} t_env_var;
5985 +
5986 +char *prom_getenv(char *);
5987 +t_env_var *prom_iterenv(t_env_var *);
5988 +
5989 +#endif /* _INCLUDE_ASM_AR7_ADAM2_ENV_H_ */
5990 diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar7.h
5991 --- linux.old/include/asm-mips/ar7/ar7.h        1970-01-01 01:00:00.000000000 +0100
5992 +++ linux.dev/include/asm-mips/ar7/ar7.h        2005-11-10 01:10:46.067588500 +0100
5993 @@ -0,0 +1,33 @@
5994 +/*
5995 + * $Id$
5996 + * Copyright (C) $Date$  $Author$
5997 + *
5998 + * This program is free software; you can redistribute it and/or modify
5999 + * it under the terms of the GNU General Public License as published by
6000 + * the Free Software Foundation; either version 2 of the License, or
6001 + * (at your option) any later version.
6002 + *
6003 + * This program is distributed in the hope that it will be useful,
6004 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6005 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6006 + * GNU General Public License for more details.
6007 + *
6008 + * You should have received a copy of the GNU General Public License
6009 + * along with this program; if not, write to the Free Software
6010 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
6011 + *
6012 + */
6013 +
6014 +#ifndef _AR7_H
6015 +#define _AR7_H
6016 +
6017 +#include <asm/addrspace.h>
6018 +#include <linux/config.h>
6019 +
6020 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(CONFIG_AR7_MEMORY))
6021 +
6022 +#define AR7_UART0_REGS_BASE (KSEG1ADDR(0x08610E00))
6023 +#define AR7_UART1_REGS_BASE (KSEG1ADDR(0x08610F00))
6024 +#define AR7_BASE_BAUD ( 3686400 / 16 )
6025 +
6026 +#endif
6027 diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm-mips/ar7/avalanche_intc.h
6028 --- linux.old/include/asm-mips/ar7/avalanche_intc.h     1970-01-01 01:00:00.000000000 +0100
6029 +++ linux.dev/include/asm-mips/ar7/avalanche_intc.h     2005-11-10 01:10:46.067588500 +0100
6030 @@ -0,0 +1,292 @@
6031 + /*
6032 + * Nitin Dhingra, iamnd@ti.com
6033 + * Copyright (C) 2000 Texas Instruments Inc.
6034 + *
6035 + *
6036 + * ########################################################################
6037 + *
6038 + *  This program is free software; you can distribute it and/or modify it
6039 + *  under the terms of the GNU General Public License (Version 2) as
6040 + *  published by the Free Software Foundation.
6041 + *
6042 + *  This program is distributed in the hope it will be useful, but WITHOUT
6043 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6044 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
6045 + *  for more details.
6046 + *
6047 + *  You should have received a copy of the GNU General Public License along
6048 + *  with this program; if not, write to the Free Software Foundation, Inc.,
6049 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
6050 + *
6051 + * ########################################################################
6052 + *
6053 + * Defines of the Sead board specific address-MAP, registers, etc.
6054 + *
6055 + */
6056 +#ifndef _AVALANCHE_INTC_H
6057 +#define _AVALANCHE_INTC_H
6058 +
6059 +#include <linux/config.h>
6060 +
6061 +/* ----- */
6062 +
6063 +#define KSEG1_BASE                  0xA0000000
6064 +#define KSEG_INV_MASK               0x1FFFFFFF /* Inverted mask for kseg address */
6065 +#define PHYS_ADDR(addr)             ((addr) & KSEG_INV_MASK)
6066 +#define PHYS_TO_K1(addr)            (PHYS_ADDR(addr)|KSEG1_BASE)
6067 +#define AVALANCHE_INTC_BASE PHYS_TO_K1(0x08612400)
6068 +
6069 +/* ----- */
6070 +
6071 +#define MIPS_EXCEPTION_OFFSET 8
6072 +
6073 +/******************************************************************************
6074 + Avalanche Interrupt number
6075 +******************************************************************************/
6076 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
6077 +
6078 +/*******************************************************************************
6079 +*Linux Interrupt number
6080 +*******************************************************************************/
6081 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
6082 +
6083 +
6084 +
6085 +#define AVALANCHE_INT_END_PRIMARY      (40 + MIPS_EXCEPTION_OFFSET)
6086 +#define AVALANCHE_INT_END_SECONDARY    (32 + MIPS_EXCEPTION_OFFSET)
6087 +
6088 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
6089 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
6090 +
6091 +#define AVALANCHE_INTC_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
6092 +                           AVINTNUM(AVALANCHE_INT_END_SECONDARY) + \
6093 +                           MIPS_EXCEPTION_OFFSET)
6094 +
6095 +#if defined(CONFIG_AR7_VLYNQ)
6096 +#define AVALANCHE_INT_END_LOW_VLYNQ  (AVALANCHE_INTC_END + 32)
6097 +#define AVALANCHE_INT_END_VLYNQ      (AVALANCHE_INTC_END + 32 * CONFIG_AR7_VLYNQ_PORTS)
6098 +#define AVALANCHE_INT_END             AVALANCHE_INT_END_VLYNQ
6099 +#else
6100 +#define AVALANCHE_INT_END             AVALANCHE_INTC_END
6101 +#endif
6102 +
6103 +
6104 +/*
6105 + * Avalanche interrupt controller register base (primary)
6106 + */
6107 +#define AVALANCHE_ICTRL_REGS_BASE  AVALANCHE_INTC_BASE
6108 +
6109 +/******************************************************************************
6110 + * Avalanche exception controller register base (secondary)
6111 + ******************************************************************************/
6112 +#define AVALANCHE_ECTRL_REGS_BASE  (AVALANCHE_ICTRL_REGS_BASE + 0x80)
6113 +
6114 +
6115 +/******************************************************************************
6116 + *  Avalanche Interrupt pacing register base (secondary)
6117 + ******************************************************************************/
6118 +#define AVALANCHE_IPACE_REGS_BASE  (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
6119 +
6120 +
6121 +
6122 +/******************************************************************************
6123 + * Avalanche Interrupt Channel Control register base
6124 + *****************************************************************************/
6125 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
6126 +
6127 +
6128 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
6129 +{
6130 +  volatile unsigned long intsr1;    /* Interrupt Status/Set Register 1   0x00 */
6131 +  volatile unsigned long intsr2;    /* Interrupt Status/Set Register 2   0x04 */
6132 +  volatile unsigned long unused1;                                      /*0x08 */
6133 +  volatile unsigned long unused2;                                      /*0x0C */
6134 +  volatile unsigned long intcr1;    /* Interrupt Clear Register 1        0x10 */
6135 +  volatile unsigned long intcr2;    /* Interrupt Clear Register 2        0x14 */
6136 +  volatile unsigned long unused3;                                      /*0x18 */
6137 +  volatile unsigned long unused4;                                      /*0x1C */
6138 +  volatile unsigned long intesr1;   /* Interrupt Enable (Set) Register 1 0x20 */
6139 +  volatile unsigned long intesr2;   /* Interrupt Enable (Set) Register 2 0x24 */
6140 +  volatile unsigned long unused5;                                      /*0x28 */
6141 +  volatile unsigned long unused6;                                      /*0x2C */
6142 +  volatile unsigned long intecr1;   /* Interrupt Enable Clear Register 1 0x30 */
6143 +  volatile unsigned long intecr2;   /* Interrupt Enable Clear Register 2 0x34 */
6144 +  volatile unsigned long unused7;                                     /* 0x38 */
6145 +  volatile unsigned long unused8;                                     /* 0x3c */
6146 +  volatile unsigned long pintir;    /* Priority Interrupt Index Register 0x40 */
6147 +  volatile unsigned long intmsr;    /* Priority Interrupt Mask Index Reg 0x44 */
6148 +  volatile unsigned long unused9;                                     /* 0x48 */
6149 +  volatile unsigned long unused10;                                    /* 0x4C */
6150 +  volatile unsigned long intpolr1;  /* Interrupt Polarity Mask register 10x50 */
6151 +  volatile unsigned long intpolr2;  /* Interrupt Polarity Mask register 20x54 */
6152 +  volatile unsigned long unused11;                                    /* 0x58 */
6153 +  volatile unsigned long unused12;                                   /*0x5C */
6154 +  volatile unsigned long inttypr1;  /* Interrupt Type     Mask register 10x60 */
6155 +  volatile unsigned long inttypr2;  /* Interrupt Type     Mask register 20x64 */
6156 +};
6157 +
6158 +struct avalanche_exctrl_regs   /* Avalanche Exception control registers */
6159 +{
6160 +  volatile unsigned long exsr;      /* Exceptions Status/Set register    0x80 */
6161 +  volatile unsigned long reserved;                                     /*0x84 */
6162 +  volatile unsigned long excr;      /* Exceptions Clear Register         0x88 */
6163 +  volatile unsigned long reserved1;                                    /*0x8c */
6164 +  volatile unsigned long exiesr;    /* Exceptions Interrupt Enable (set) 0x90 */
6165 +  volatile unsigned long reserved2;                                    /*0x94 */
6166 +  volatile unsigned long exiecr;    /* Exceptions Interrupt Enable(clear)0x98 */
6167 +};
6168 +struct avalanche_ipace_regs
6169 +{
6170 +
6171 +  volatile unsigned long ipacep;    /* Interrupt pacing register         0xa0 */
6172 +  volatile unsigned long ipacemap;  /*Interrupt Pacing Map Register      0xa4 */
6173 +  volatile unsigned long ipacemax;  /*Interrupt Pacing Max Register      0xa8 */
6174 +};
6175 +struct avalanche_channel_int_number
6176 +{
6177 +  volatile unsigned long cintnr0;   /* Channel Interrupt Number Register0x200 */
6178 +  volatile unsigned long cintnr1;   /* Channel Interrupt Number Register0x204 */
6179 +  volatile unsigned long cintnr2;   /* Channel Interrupt Number Register0x208 */
6180 +  volatile unsigned long cintnr3;   /* Channel Interrupt Number Register0x20C */
6181 +  volatile unsigned long cintnr4;   /* Channel Interrupt Number Register0x210 */
6182 +  volatile unsigned long cintnr5;   /* Channel Interrupt Number Register0x214 */
6183 +  volatile unsigned long cintnr6;   /* Channel Interrupt Number Register0x218 */
6184 +  volatile unsigned long cintnr7;   /* Channel Interrupt Number Register0x21C */
6185 +  volatile unsigned long cintnr8;   /* Channel Interrupt Number Register0x220 */
6186 +  volatile unsigned long cintnr9;   /* Channel Interrupt Number Register0x224 */
6187 +  volatile unsigned long cintnr10;  /* Channel Interrupt Number Register0x228 */
6188 +  volatile unsigned long cintnr11;  /* Channel Interrupt Number Register0x22C */
6189 +  volatile unsigned long cintnr12;  /* Channel Interrupt Number Register0x230 */
6190 +  volatile unsigned long cintnr13;  /* Channel Interrupt Number Register0x234 */
6191 +  volatile unsigned long cintnr14;  /* Channel Interrupt Number Register0x238 */
6192 +  volatile unsigned long cintnr15;  /* Channel Interrupt Number Register0x23C */
6193 +  volatile unsigned long cintnr16;  /* Channel Interrupt Number Register0x240 */
6194 +  volatile unsigned long cintnr17;  /* Channel Interrupt Number Register0x244 */
6195 +  volatile unsigned long cintnr18;  /* Channel Interrupt Number Register0x248 */
6196 +  volatile unsigned long cintnr19;  /* Channel Interrupt Number Register0x24C */
6197 +  volatile unsigned long cintnr20;  /* Channel Interrupt Number Register0x250 */
6198 +  volatile unsigned long cintnr21;  /* Channel Interrupt Number Register0x254 */
6199 +  volatile unsigned long cintnr22;  /* Channel Interrupt Number Register0x358 */
6200 +  volatile unsigned long cintnr23;  /* Channel Interrupt Number Register0x35C */
6201 +  volatile unsigned long cintnr24;  /* Channel Interrupt Number Register0x260 */
6202 +  volatile unsigned long cintnr25;  /* Channel Interrupt Number Register0x264 */
6203 +  volatile unsigned long cintnr26;  /* Channel Interrupt Number Register0x268 */
6204 +  volatile unsigned long cintnr27;  /* Channel Interrupt Number Register0x26C */
6205 +  volatile unsigned long cintnr28;  /* Channel Interrupt Number Register0x270 */
6206 +  volatile unsigned long cintnr29;  /* Channel Interrupt Number Register0x274 */
6207 +  volatile unsigned long cintnr30;  /* Channel Interrupt Number Register0x278 */
6208 +  volatile unsigned long cintnr31;  /* Channel Interrupt Number Register0x27C */
6209 +  volatile unsigned long cintnr32;  /* Channel Interrupt Number Register0x280 */
6210 +  volatile unsigned long cintnr33;  /* Channel Interrupt Number Register0x284 */
6211 +  volatile unsigned long cintnr34;  /* Channel Interrupt Number Register0x288 */
6212 +  volatile unsigned long cintnr35;  /* Channel Interrupt Number Register0x28C */
6213 +  volatile unsigned long cintnr36;  /* Channel Interrupt Number Register0x290 */
6214 +  volatile unsigned long cintnr37;  /* Channel Interrupt Number Register0x294 */
6215 +  volatile unsigned long cintnr38;  /* Channel Interrupt Number Register0x298 */
6216 +  volatile unsigned long cintnr39;  /* Channel Interrupt Number Register0x29C */
6217 +};
6218 +
6219 +struct avalanche_interrupt_line_to_channel
6220 +{
6221 +  unsigned long int_line0;    /* Start of primary interrupts */
6222 +  unsigned long int_line1;
6223 +  unsigned long int_line2;
6224 +  unsigned long int_line3;
6225 +  unsigned long int_line4;
6226 +  unsigned long int_line5;
6227 +  unsigned long int_line6;
6228 +  unsigned long int_line7;
6229 +  unsigned long int_line8;
6230 +  unsigned long int_line9;
6231 +  unsigned long int_line10;
6232 +  unsigned long int_line11;
6233 +  unsigned long int_line12;
6234 +  unsigned long int_line13;
6235 +  unsigned long int_line14;
6236 +  unsigned long int_line15;
6237 +  unsigned long int_line16;
6238 +  unsigned long int_line17;
6239 +  unsigned long int_line18;
6240 +  unsigned long int_line19;
6241 +  unsigned long int_line20;
6242 +  unsigned long int_line21;
6243 +  unsigned long int_line22;
6244 +  unsigned long int_line23;
6245 +  unsigned long int_line24;
6246 +  unsigned long int_line25;
6247 +  unsigned long int_line26;
6248 +  unsigned long int_line27;
6249 +  unsigned long int_line28;
6250 +  unsigned long int_line29;
6251 +  unsigned long int_line30;
6252 +  unsigned long int_line31;
6253 +  unsigned long int_line32;
6254 +  unsigned long int_line33;
6255 +  unsigned long int_line34;
6256 +  unsigned long int_line35;
6257 +  unsigned long int_line36;
6258 +  unsigned long int_line37;
6259 +  unsigned long int_line38;
6260 +  unsigned long int_line39;
6261 +};
6262 +
6263 +
6264 +/* Interrupt Line #'s  (Sangam peripherals) */
6265 +
6266 +/*------------------------------*/
6267 +/* Sangam primary interrupts */
6268 +/*------------------------------*/
6269 +
6270 +#define UNIFIED_SECONDARY_INTERRUPT  0
6271 +#define AVALANCHE_EXT_INT_0          1
6272 +#define AVALANCHE_EXT_INT_1          2
6273 +/*  Line #3  Reserved               */
6274 +/*  Line #4  Reserved               */
6275 +#define AVALANCHE_TIMER_0_INT        5
6276 +#define AVALANCHE_TIMER_1_INT        6
6277 +#define AVALANCHE_UART0_INT          7
6278 +#define AVALANCHE_UART1_INT          8
6279 +#define AVALANCHE_PDMA_INT0          9
6280 +#define AVALANCHE_PDMA_INT1          10
6281 +/*  Line #11  Reserved               */
6282 +/*  Line #12  Reserved               */
6283 +/*  Line #13  Reserved               */
6284 +/*  Line #14  Reserved               */
6285 +#define AVALANCHE_ATM_SAR_INT        15
6286 +/*  Line #16  Reserved               */
6287 +/*  Line #17  Reserved               */
6288 +/*  Line #18  Reserved               */
6289 +#define AVALANCHE_MAC0_INT           19
6290 +/*  Line #20  Reserved               */
6291 +#define AVALANCHE_VLYNQ0_INT         21
6292 +#define AVALANCHE_CODEC_WAKE_INT     22
6293 +/*  Line #23  Reserved               */
6294 +#define AVALANCHE_USB_INT            24
6295 +#define AVALANCHE_VLYNQ1_INT         25
6296 +/*  Line #26  Reserved               */
6297 +/*  Line #27  Reserved               */
6298 +#define AVALANCHE_MAC1_INT           28
6299 +#define AVALANCHE_I2CM_INT           29
6300 +#define AVALANCHE_PDMA_INT2          30
6301 +#define AVALANCHE_PDMA_INT3          31
6302 +/*  Line #32  Reserved               */
6303 +/*  Line #33  Reserved               */
6304 +/*  Line #34  Reserved               */
6305 +/*  Line #35  Reserved               */
6306 +/*  Line #36  Reserved               */
6307 +#define AVALANCHE_VDMA_VT_RX_INT     37
6308 +#define AVALANCHE_VDMA_VT_TX_INT     38
6309 +#define AVALANCHE_ADSLSS_INT         39
6310 +
6311 +/*-----------------------------------*/
6312 +/* Sangam Secondary Interrupts    */
6313 +/*-----------------------------------*/
6314 +#define PRIMARY_INTS                 40
6315 +
6316 +#define EMIF_INT                    (7 + PRIMARY_INTS)
6317 +
6318 +
6319 +extern void avalanche_int_set(int channel, int line);
6320 +
6321 +
6322 +#endif /* _AVALANCHE_INTC_H */
6323 diff -urN linux.old/include/asm-mips/ar7/avalanche_misc.h linux.dev/include/asm-mips/ar7/avalanche_misc.h
6324 --- linux.old/include/asm-mips/ar7/avalanche_misc.h     1970-01-01 01:00:00.000000000 +0100
6325 +++ linux.dev/include/asm-mips/ar7/avalanche_misc.h     2005-11-10 01:10:46.067588500 +0100
6326 @@ -0,0 +1,174 @@
6327 +#ifndef _AVALANCHE_MISC_H_
6328 +#define _AVALANCHE_MISC_H_
6329 +
6330 +typedef enum AVALANCHE_ERR_t
6331 +{
6332 +    AVALANCHE_ERR_OK        = 0,    /* OK or SUCCESS */
6333 +    AVALANCHE_ERR_ERROR     = -1,   /* Unspecified/Generic ERROR */
6334 +
6335 +    /* Pointers and args */
6336 +    AVALANCHE_ERR_INVARG        = -2,   /* Invaild argument to the call */
6337 +    AVALANCHE_ERR_NULLPTR       = -3,   /* NULL pointer */
6338 +    AVALANCHE_ERR_BADPTR        = -4,   /* Bad (out of mem) pointer */
6339 +
6340 +    /* Memory issues */
6341 +    AVALANCHE_ERR_ALLOC_FAIL    = -10,  /* allocation failed */
6342 +    AVALANCHE_ERR_FREE_FAIL     = -11,  /* free failed */
6343 +    AVALANCHE_ERR_MEM_CORRUPT   = -12,  /* corrupted memory */
6344 +    AVALANCHE_ERR_BUF_LINK      = -13,  /* buffer linking failed */
6345 +
6346 +    /* Device issues */
6347 +    AVALANCHE_ERR_DEVICE_TIMEOUT    = -20,  /* device timeout on read/write */
6348 +    AVALANCHE_ERR_DEVICE_MALFUNC    = -21,  /* device malfunction */
6349 +
6350 +    AVALANCHE_ERR_INVID     = -30   /* Invalid ID */
6351 +
6352 +} AVALANCHE_ERR;
6353 +
6354 +/*****************************************************************************
6355 + * Reset Control Module
6356 + *****************************************************************************/
6357 +
6358 +typedef enum AVALANCHE_RESET_MODULE_tag
6359 +{
6360 +    RESET_MODULE_UART0      = 0,
6361 +    RESET_MODULE_UART1      = 1,
6362 +    RESET_MODULE_I2C        = 2,
6363 +    RESET_MODULE_TIMER0     = 3,
6364 +    RESET_MODULE_TIMER1     = 4,
6365 +    RESET_MODULE_GPIO       = 6,
6366 +    RESET_MODULE_ADSLSS     = 7,
6367 +    RESET_MODULE_USBS       = 8,
6368 +    RESET_MODULE_SAR        = 9,
6369 +    RESET_MODULE_VDMA_VT    = 11,
6370 +    RESET_MODULE_FSER       = 12,
6371 +    RESET_MODULE_VLYNQ1     = 16,
6372 +    RESET_MODULE_EMAC0      = 17,
6373 +    RESET_MODULE_DMA        = 18,
6374 +    RESET_MODULE_BIST       = 19,
6375 +    RESET_MODULE_VLYNQ0     = 20,
6376 +    RESET_MODULE_EMAC1      = 21,
6377 +    RESET_MODULE_MDIO       = 22,
6378 +    RESET_MODULE_ADSLSS_DSP = 23,
6379 +    RESET_MODULE_EPHY       = 26
6380 +} AVALANCHE_RESET_MODULE_T;
6381 +
6382 +typedef enum AVALANCHE_RESET_CTRL_tag
6383 +{
6384 +    IN_RESET        = 0,
6385 +    OUT_OF_RESET
6386 +} AVALANCHE_RESET_CTRL_T;
6387 +
6388 +typedef enum AVALANCHE_SYS_RST_MODE_tag
6389 +{
6390 +    RESET_SOC_WITH_MEMCTRL      = 1,    /* SW0 bit in SWRCR register */
6391 +    RESET_SOC_WITHOUT_MEMCTRL   = 2     /* SW1 bit in SWRCR register */
6392 +} AVALANCHE_SYS_RST_MODE_T;
6393 +
6394 +typedef enum AVALANCHE_SYS_RESET_STATUS_tag
6395 +{
6396 +    HARDWARE_RESET = 0,
6397 +    SOFTWARE_RESET0,            /* Caused by writing 1 to SW0 bit in SWRCR register */
6398 +    WATCHDOG_RESET,
6399 +    SOFTWARE_RESET1             /* Caused by writing 1 to SW1 bit in SWRCR register */
6400 +} AVALANCHE_SYS_RESET_STATUS_T;
6401 +
6402 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(AVALANCHE_RESET_MODULE_T reset_module);
6403 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode);
6404 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status(void);
6405 +
6406 +typedef int (*REMOTE_VLYNQ_DEV_RESET_CTRL_FN)(unsigned int reset_module, AVALANCHE_RESET_CTRL_T reset_ctrl);
6407 +
6408 +/*****************************************************************************
6409 + * Power Control Module
6410 + *****************************************************************************/
6411 +
6412 +typedef enum AVALANCHE_POWER_CTRL_tag
6413 +{
6414 +    POWER_CTRL_POWER_UP = 0,
6415 +    POWER_CTRL_POWER_DOWN
6416 +} AVALANCHE_POWER_CTRL_T;
6417 +
6418 +typedef enum AVALANCHE_SYS_POWER_MODE_tag
6419 +{
6420 +    GLOBAL_POWER_MODE_RUN       = 0,    /* All system is up */
6421 +    GLOBAL_POWER_MODE_IDLE,             /* MIPS is power down, all peripherals working */
6422 +    GLOBAL_POWER_MODE_STANDBY,          /* Chip in power down, but clock to ADSKL subsystem is running */
6423 +    GLOBAL_POWER_MODE_POWER_DOWN        /* Total chip is powered down */
6424 +} AVALANCHE_SYS_POWER_MODE_T;
6425 +
6426 +void avalanche_power_ctrl(unsigned int power_module,  AVALANCHE_POWER_CTRL_T power_ctrl);
6427 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int power_module);
6428 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode);
6429 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void);
6430 +
6431 +/*****************************************************************************
6432 + * Wakeup Control
6433 + *****************************************************************************/
6434 +
6435 +typedef enum AVALANCHE_WAKEUP_INTERRUPT_tag
6436 +{
6437 +    WAKEUP_INT0 = 1,
6438 +    WAKEUP_INT1 = 2,
6439 +    WAKEUP_INT2 = 4,
6440 +    WAKEUP_INT3 = 8
6441 +} AVALANCHE_WAKEUP_INTERRUPT_T;
6442 +
6443 +typedef enum TNETV1050_WAKEUP_CTRL_tag
6444 +{
6445 +    WAKEUP_DISABLED = 0,
6446 +    WAKEUP_ENABLED
6447 +} AVALANCHE_WAKEUP_CTRL_T;
6448 +
6449 +typedef enum TNETV1050_WAKEUP_POLARITY_tag
6450 +{
6451 +    WAKEUP_ACTIVE_HIGH = 0,
6452 +    WAKEUP_ACTIVE_LOW
6453 +} AVALANCHE_WAKEUP_POLARITY_T;
6454 +
6455 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
6456 +                           AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
6457 +                           AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity);
6458 +
6459 +/*****************************************************************************
6460 + * GPIO Control
6461 + *****************************************************************************/
6462 +
6463 +typedef enum AVALANCHE_GPIO_PIN_MODE_tag
6464 +{
6465 +    FUNCTIONAL_PIN = 0,
6466 +    GPIO_PIN = 1
6467 +} AVALANCHE_GPIO_PIN_MODE_T;
6468 +
6469 +typedef enum AVALANCHE_GPIO_PIN_DIRECTION_tag
6470 +{
6471 +    GPIO_OUTPUT_PIN = 0,
6472 +    GPIO_INPUT_PIN = 1
6473 +} AVALANCHE_GPIO_PIN_DIRECTION_T;
6474 +
6475 +typedef enum { GPIO_FALSE, GPIO_TRUE } AVALANCHE_GPIO_BOOL_T;
6476 +
6477 +void avalanche_gpio_init(void);
6478 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
6479 +                         AVALANCHE_GPIO_PIN_MODE_T pin_mode,
6480 +                         AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
6481 +int avalanche_gpio_ctrl_with_link_count(unsigned int gpio_pin,
6482 +                         AVALANCHE_GPIO_PIN_MODE_T pin_mode,
6483 +                         AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
6484 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value);
6485 +int avalanche_gpio_in_bit(unsigned int gpio_pin);
6486 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
6487 +int avalanche_gpio_out_value_with_link_count(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
6488 +int avalanche_gpio_in_value(unsigned int *in_val, unsigned int reg_index);
6489 +
6490 +unsigned int avalanche_get_chip_version_info(void);
6491 +
6492 +unsigned int avalanche_get_vbus_freq(void);
6493 +void         avalanche_set_vbus_freq(unsigned int);
6494 +
6495 +
6496 +typedef int (*SET_MDIX_ON_CHIP_FN_T)(unsigned int base_addr, unsigned int operation);
6497 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation);
6498 +unsigned int avalanche_is_mdix_on_chip(void);
6499 +
6500 +#endif
6501 diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm-mips/ar7/avalanche_regs.h
6502 --- linux.old/include/asm-mips/ar7/avalanche_regs.h     1970-01-01 01:00:00.000000000 +0100
6503 +++ linux.dev/include/asm-mips/ar7/avalanche_regs.h     2005-11-10 01:10:46.071588750 +0100
6504 @@ -0,0 +1,567 @@
6505 +/*
6506 + *  $Id$
6507 + *  Avalanche Register Descriptions
6508 + *
6509 + *  Jeff Harrell, jharrell@ti.com
6510 + *  2000 (c) Texas Instruments Inc.
6511 + */
6512 +
6513 +#ifndef __AVALANCHE_REGS_H
6514 +#define __AVALANCHE_REGS_H
6515 +
6516 +#include <asm/addrspace.h>
6517 +#include <linux/config.h>
6518 +
6519 +/*----------------------------------------*/
6520 +/* Base offsets within the Avalanche ASIC */
6521 +/*----------------------------------------*/
6522 +
6523 +#define BBIF_SPACE0     (KSEG1ADDR(0x01000000))
6524 +#define BBIF_SPACE1     (KSEG1ADDR(0x01800000))
6525 +#define BBIF_CONTROL    (KSEG1ADDR(0x02000000))
6526 +#define ATM_SAR_BASE    (KSEG1ADDR(0x03000000))
6527 +#define USB_MCU_BASE    (KSEG1ADDR(0x03400000))
6528 +#define DES_BASE        (KSEG1ADDR(0x08600000))
6529 +#define ETH_MACA_BASE   (KSEG1ADDR(0x08610000))
6530 +#define ETH_MACB_BASE   (KSEG1ADDR(0x08612800))
6531 +#define MEM_CTRLR_BASE  (KSEG1ADDR(0x08610800))
6532 +#define GPIO_BASE       (KSEG1ADDR(0x08610900))
6533 +#define CLK_CTRL_BASE   (KSEG1ADDR(0x08610A00))
6534 +#define WATCH_DOG_BASE  (KSEG1ADDR(0x08610B00))
6535 +#define TMR1_BASE       (KSEG1ADDR(0x08610C00))
6536 +#define TRM2_BASE       (KSEG1ADDR(0x08610D00))
6537 +#define UARTA_BASE      (KSEG1ADDR(0x08610E00))
6538 +#define UARTB_BASE      (KSEG1ADDR(0x08610F00))
6539 +#define I2C_BASE        (KSEG1ADDR(0x08611000))
6540 +#define DEV_ID_BASE     (KSEG1ADDR(0x08611100))
6541 +#define USB_BASE        (KSEG1ADDR(0x08611200))
6542 +#define PCI_CONFIG_BASE (KSEG1ADDR(0x08611300))
6543 +#define DMA_BASE        (KSEG1ADDR(0x08611400))
6544 +#define RESET_CTRL_BASE (KSEG1ADDR(0x08611600))
6545 +#define DSL_IF_BASE     (KSEG1ADDR(0x08611B00))
6546 +#define INT_CTL_BASE    (KSEG1ADDR(0x08612400))
6547 +#define PHY_BASE        (KSEG1ADDR(0x1E000000))
6548 +
6549 +/*---------------------------------*/
6550 +/* Device ID, chip version number  */
6551 +/*---------------------------------*/
6552 +
6553 +#define AVALANCHE_CHVN  (*(volatile unsigned int *)(DEV_ID_BASE+0x14))
6554 +#define AVALANCHE_DEVID1 (*(volatile unsigned int *)(DEV_ID_BASE+0x18))
6555 +#define AVALANCHE_DEVID2 (*(volatile unsigned int *)(DEV_ID_BASE+0x1C))
6556 +
6557 +/*----------------------------------*/
6558 +/* Reset Control VW changed to ptrs */
6559 +/*----------------------------------*/
6560 +
6561 +#define AVALANCHE_PRCR  (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x0))  /* Peripheral reset control */
6562 +#define AVALANCHE_SWRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x4))  /* Software reset control   */
6563 +#define AVALANCHE_RSR   (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x8))  /* Reset status register    */
6564 +
6565 +/* reset control bits */
6566 +
6567 +#define AV_RST_UART0    (1<<0)    /* Brings UART0 out of reset              */
6568 +#define AV_RST_UART1    (1<<1)    /* Brings UART1 out of reset              */
6569 +#define AV_RST_IICM     (1<<2)    /* Brings the I2CM out of reset           */
6570 +#define AV_RST_TIMER0   (1<<3)    /* Brings Timer 0 out of reset            */
6571 +#define AV_RST_TIMER1   (1<<4)    /* Brings Timer 1 out of reset            */
6572 +#define AV_RST_DES      (1<<5)    /* Brings the DES module out of reset     */
6573 +#define AV_RST_GPIO     (1<<6)    /* Brings the GPIO module out of reset (see note below) */
6574 +/*
6575 +  JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
6576 +       If you reset the GPIO interface all of the directions (i/o) of the UART B
6577 +       interface pins are inputs and must be reconfigured so as not to lose the
6578 +       serial console interface
6579 +  JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
6580 +*/
6581 +#define AV_RST_BBIF     (1<<7)    /* Brings the Broadband interface out of reset */
6582 +#define AV_RST_USB      (1<<8)    /* Brings the USB module out of reset     */
6583 +#define AV_RST_SAR      (1<<9)    /* Brings the SAR out of reset            */
6584 +#define AV_RST_HDLC     (1<<10)   /* Brings the HDLC module out of reset    */
6585 +#define AV_RST_PCI      (1<<16)   /* Brings the PCI module out of reset     */
6586 +#define AV_RST_ETH_MAC0 (1<<17)   /* Brings the Ethernet MAC0 out of reset  */
6587 +#define AV_RST_PICO_DMA (1<<18)   /* Brings the PICO DMA module out of reset */
6588 +#define AV_RST_BIST     (1<<19)   /* Brings the BIST module out of reset    */
6589 +#define AV_RST_DSP      (1<<20)   /* Brings the DSP sub system out of reset */
6590 +#define AV_RST_ETH_MAC1 (1<<21)   /* Brings the Ethernet MAC1 out of reset  */
6591 +
6592 +/*----------------------*/
6593 +/* Physical interfaces  */
6594 +/*----------------------*/
6595 +
6596 +/* Phy loopback */
6597 +#define PHY_LOOPBACK    1
6598 +
6599 +
6600 +/* Phy 0 */
6601 +#define PHY0BASE        (PHY_BASE)
6602 +#define PHY0RST         (*(volatile unsigned char *) (PHY0BASE))      /* reset   */
6603 +#define PHY0CTRL        (*(volatile unsigned char *) (PHY0BASE+0x5))  /* control */
6604 +#define PHY0RACPCTRL    (*(volatile unsigned char *) (PHY0BASE+0x50)) /* RACP control/status */
6605 +#define PHY0TACPCTRL    (*(volatile unsigned char *) (PHY0BASE+0x60)) /* TACP idle/unassigned cell hdr */
6606 +#define PHY0RACPINT     (*(volatile unsigned char *) (PHY0BASE+0x51)) /* RACP interrupt enable/Status */
6607 +
6608 +
6609 +/* Phy 1 */
6610 +
6611 +#define PHY1BASE        (PHY_BASE + 0x100000)
6612 +#define PHY1RST         (*(volatile unsigned char *) (PHY1BASE))      /* reset   */
6613 +#define PHY1CTRL        (*(volatile unsigned char *) (PHY1BASE+0x5))  /* control */
6614 +#define PHY1RACPCTRL    (*(volatile unsigned char *) (PHY1BASE+0x50))
6615 +#define PHY1TACPCTRL    (*(volatile unsigned char *) (PHY1BASE+0x60))
6616 +#define PHY1RACPINT     (*(volatile unsigned char *) (PHY1BASE+0x51))
6617 +
6618 +/* Phy 2 */
6619 +
6620 +#define PHY2BASE        (PHY_BASE + 0x200000)
6621 +#define PHY2RST         (*(volatile unsigned char *) (PHY2BASE))      /* reset   */
6622 +#define PHY2CTRL        (*(volatile unsigned char *) (PHY2BASE+0x5))  /* control */
6623 +#define PHY2RACPCTRL    (*(volatile unsigned char *) (PHY2BASE+0x50))
6624 +#define PHY2TACPCTRL    (*(volatile unsigned char *) (PHY2BASE+0x60))
6625 +#define PHY2RACPINT     (*(volatile unsigned char *) (PHY2BASE+0x51))
6626 +
6627 +/*-------------------*/
6628 +/* Avalanche ATM SAR */
6629 +/*-------------------*/
6630 +
6631 +#define AVSAR_SYSCONFIG    (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000000)) /* SAR system config register    */
6632 +#define AVSAR_SYSSTATUS    (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000004)) /* SAR system status register    */
6633 +#define AVSAR_INT_ENABLE   (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000008)) /* SAR interrupt enable register */
6634 +#define AVSAR_CONN_VPI_VCI (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000000c)) /* VPI/VCI connection config     */
6635 +#define AVSAR_CONN_CONFIG  (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000010)) /* Connection config register    */
6636 +#define AVSAR_OAM_CONFIG   (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018)) /* OAM configuration register    */
6637 +
6638 +/* Transmit completion ring registers */
6639 +
6640 +#define AVSAR_TCRAPTR       (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000100))
6641 +#define AVSAR_TCRASIZE      (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000104))
6642 +#define AVSAR_TCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000108))
6643 +#define AVSAR_TCRATOTENT    (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000010c))
6644 +#define AVSAR_TCRAFREEENT   (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000110))
6645 +#define AVSAR_TCRAPENDENT   (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000114))
6646 +#define AVSAR_TCRAENTINC    (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000118))
6647 +#define AVSAR_TCRBPTR       (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000011c))
6648 +#define AVSAR_TCRBSIZE      (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000120))
6649 +#define AVSAR_TCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000124))
6650 +#define AVSAR_TCRBTOTENT    (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000128))
6651 +#define AVSAR_TCRBFREEENT   (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000012c))
6652 +#define AVSAR_TCRBPENDENT   (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000130))
6653 +#define AVSAR_TCRBENTINC    (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000134))
6654 +
6655 +/* Transmit Queue Packet registers */
6656 +#define AVSAR_TXQUEUE_PKT0  (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000140))
6657 +#define AVSAR_TXQUEUE_PKT1  (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000144))
6658 +#define AVSAR_TXQUEUE_PKT2  (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000148))
6659 +#define AVSAR_TX_FLUSH      (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000014C))
6660 +/* Receive completion ring registers */
6661 +
6662 +#define AVSAR_RCRAPTR       (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000200))
6663 +#define AVSAR_RCRASIZE      (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000204))
6664 +#define AVSAR_RCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000208))
6665 +#define AVSAR_RCRATOTENT    (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000020c))
6666 +#define AVSAR_RCRAFREEENT   (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000210))
6667 +#define AVSAR_RCRAPENDENT   (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000214))
6668 +#define AVSAR_RCRAENTINC    (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000218))
6669 +#define AVSAR_RCRBPTR       (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000021c))
6670 +#define AVSAR_RCRBSIZE      (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000220))
6671 +#define AVSAR_RCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000224))
6672 +#define AVSAR_RCRBTOTENT    (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000228))
6673 +#define AVSAR_RCRBFREEENT   (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000022c))
6674 +#define AVSAR_RCRBPENDENT   (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000230))
6675 +#define AVSAR_RCRBENTINC    (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000234))
6676 +
6677 +#define AVSAR_RXFBL_ADD0    (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000240)) /* Rx Free buffer list add 0  */
6678 +#define AVSAR_RXFBL_ADD1    (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000244)) /* Rx Free buffer list add 1  */
6679 +#define AVSAR_RXFBL_ADD2    (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000248)) /* Rx Free buffer list add 2  */
6680 +#define AVSAR_RXFBLSIZE_0   (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000028c)) /* Rx Free buffer list size 0 */
6681 +#define AVSAR_RXFBLSIZE_1   (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000029c)) /* Rx Free buffer list size 1 */
6682 +#define AVSAR_RXFBLSIZE_2   (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002ac)) /* Rx Free buffer list size 2 */
6683 +#define AVSAR_RXFBLSIZE_3   (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002bc)) /* Rx Free buffer list size 3 */
6684 +
6685 +
6686 +#if defined(CONFIG_MIPS_EVM3D) || defined(CONFIG_MIPS_AR5D01) || defined(CONFIG_MIPS_AR5W01)
6687 +
6688 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010480))
6689 +#define AVSAR_OAM_CC_SINK   (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010484))
6690 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010488))
6691 +#define AVSAR_OAM_CPID0      (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E0))
6692 +#define AVSAR_OAM_LLID0      (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F0))
6693 +#define AVSAR_OAM_CPID1      (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E4))
6694 +#define AVSAR_OAM_LLID1      (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F4))
6695 +#define AVSAR_OAM_CPID2      (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E8))
6696 +#define AVSAR_OAM_LLID2      (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F8))
6697 +#define AVSAR_OAM_CPID3      (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104EC))
6698 +#define AVSAR_OAM_LLID3      (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104FC))
6699 +#define AVSAR_OAM_CORR_TAG      (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010500))
6700 +#define AVSAR_OAM_FAR_COUNT      (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010520))
6701 +#define AVSAR_OAM_NEAR_COUNT      (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010540))
6702 +#define AVSAR_OAM_CONFIG_REG      (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018))
6703 +#define AVSAR_FAIRNESS_REG   (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104B8))
6704 +#define AVSAR_UBR_PCR_REG   (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010490))
6705 +
6706 +
6707 +/*
6708 +
6709 +#define OAM_CPID_ADD  0xa30104e0
6710 +
6711 +#define OAM_LLID_ADD  0xa30104f0
6712 +
6713 +#define OAM_LLID_VAL  0xffffffff
6714 +
6715 +#define OAM_CORR_TAG  0xa3010500
6716 +
6717 +#define OAM_FAR_COUNT_ADD 0xa3010520
6718 +
6719 +#define OAM_NEAR_COUNT_ADD 0xa3010540
6720 +
6721 +#define OAM_CONFIG_REG_ADD 0xa3000018
6722 +*/
6723 +
6724 +
6725 +#else /* CONFIG_MIPS_EVM3 || CONFIG_MIPS_ACPEP */
6726 +
6727 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012000))
6728 +#define AVSAR_OAM_CC_SINK   (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012004))
6729 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012008))
6730 +#define AVSAR_OAM_CPID      (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012300))
6731 +
6732 +#endif /* CONFIG_MIPS_EVM3D || CONFIG_MIPS_AR5D01 || CONFIG_MIPS_AR5W01 */
6733 +
6734 +
6735 +#define AVSAR_STATE_RAM     (ATM_SAR_BASE + 0x010000) /* SAR state RAM */
6736 +#define AVSAR_PDSP_BASE     (ATM_SAR_BASE + 0x020000) /* SAR PDSP base address   */
6737 +#define AVSAR_TXDMA_BASE    (ATM_SAR_BASE + 0x030000) /* Transmit DMA state base */
6738 +#define AVSAR_TDMASTATE6    0x18                      /* Transmit DMA state word 6 */
6739 +#define AVSAR_RXDMA_BASE    (ATM_SAR_BASE + 0x040000) /* Receive  DMA state base */
6740 +#define AVSAR_RDMASTATE0    0x0                       /* Receive  DMA state word 0 */
6741 +
6742 +/*------------------------------------------*/
6743 +/* DSL Interface                            */
6744 +/*------------------------------------------*/
6745 +
6746 +#define AVDSL_TX_EN          (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000000))
6747 +#define AVDSL_RX_EN          (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000004))
6748 +#define AVDSL_POLL           (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000008))
6749 +
6750 +/* Fast */
6751 +
6752 +#define AVDSL_TX_FIFO_ADDR0  (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000000C))
6753 +#define AVDSL_TX_FIFO_BASE0  (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000010))
6754 +#define AVDSL_TX_FIFO_LEN0   (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000014))
6755 +#define AVDSL_TX_FIFO_PR0    (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000018))
6756 +#define AVDSL_RX_FIFO_ADDR0  (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000001C))
6757 +#define AVDSL_RX_FIFO_BASE0  (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000020))
6758 +#define AVDSL_RX_FIFO_LEN0   (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000024))
6759 +#define AVDSL_RX_FIFO_PR0    (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000028))
6760 +
6761 +/* Interleaved */
6762 +
6763 +#define AVDSL_TX_FIFO_ADDR1  (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000002C))
6764 +#define AVDSL_TX_FIFO_BASE1  (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000030))
6765 +#define AVDSL_TX_FIFO_LEN1   (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000034))
6766 +#define AVDSL_TX_FIFO_PR1    (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000038))
6767 +#define AVDSL_RX_FIFO_ADDR1  (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000003C))
6768 +#define AVDSL_RX_FIFO_BASE1  (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000040))
6769 +#define AVDSL_RX_FIFO_LEN1   (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000044))
6770 +#define AVDSL_RX_FIFO_PR1    (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000048))
6771 +
6772 +/*------------------------------------------*/
6773 +/* Broadband I/F                            */
6774 +/*------------------------------------------*/
6775 +
6776 +#define AVBBIF_BBIF_CNTRL    (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000000))
6777 +#define AVBBIF_ADDR_TRANS_0  (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000004))
6778 +#define AVBBIF_ADDR_TRANS_1  (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000008))
6779 +#define AVBBIF_ADDR_XB_MX_BL (*(volatile unsigned int *)(BBIF_CONTROL + 0x0000000C))
6780 +#define AVBBIF_INFIFO_LVL    (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000010))
6781 +#define AVBBIF_OUTFIFO_LVL   (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000014))
6782 +
6783 +#define AVBBIF_DISABLED    0x0
6784 +#define AVBBIF_LBT4040_INT 0x1
6785 +#define AVBBIF_XBUS        0x2
6786 +#define AVBBIF_LBT4040_EXT 0x4
6787 +
6788 +#define AVBBIF_ADDR_MASK0   0xff000000 /* handles upper bits of BBIF 0 address */
6789 +#define AVBBIF_ADDR_MASK1   0xff800000 /* handles upper bits of BBIF 1 address */
6790 +#define AVBBIF_TRANS_MASK   0xff000000
6791 +/*------------------------------------------*/
6792 +/* GPIO I/F                                 */
6793 +/*------------------------------------------*/
6794 +
6795 +#define GPIO_DATA_INPUT      (*(volatile unsigned int *)(GPIO_BASE + 0x00000000))
6796 +#define GPIO_DATA_OUTPUT     (*(volatile unsigned int *)(GPIO_BASE + 0x00000004))
6797 +#define GPIO_DATA_DIR        (*(volatile unsigned int *)(GPIO_BASE + 0x00000008)) /* 0=output 1=input  */
6798 +#define GPIO_DATA_ENABLE     (*(volatile unsigned int *)(GPIO_BASE + 0x0000000C)) /* 0=GPIO Mux 1=GPIO */
6799 +
6800 +#define GPIO_0 (1<<21)
6801 +#define GPIO_1 (1<<22)
6802 +#define GPIO_2 (1<<23)
6803 +#define GPIO_3 (1<<24)
6804 +#define EINT_1 (1<<18)
6805 +
6806 +/*
6807 +  JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
6808 +       If you reset the GPIO interface all of the directions (i/o) of the UART B
6809 +       interface pins are inputs and must be reconfigured so as not to lose the
6810 +       serial console interface
6811 +  JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
6812 +*/
6813 +
6814 +/*------------------------------------------*/
6815 +/* CLK_CTRL                                 */
6816 +/*------------------------------------------*/
6817 +#define PERIPH_CLK_CTL       (*(volatile unsigned int *)(CLK_CTRL_BASE + 0x00000004))
6818 +
6819 +#define PCLK_0_HALF_VBUS     (0<<16)
6820 +#define PCLK_EQ_INPUT        (1<<16)
6821 +#define BBIF_CLK_HALF_VBUS   (0<<17)
6822 +#define BBIF_CLK_EQ_VBUS     (1<<17)
6823 +#define BBIF_CLK_EQ_BBCLK    (3<<17)
6824 +#define DSP_MODCLK_DSPCLKI   (0<<20)
6825 +#define DSP_MODCLK_REFCLKI   (1<<20)
6826 +#define USB_CLK_EQ_USBCLKI   (0<<21)
6827 +#define USB_CLK_EQ_REFCLKI   (1<<21)
6828 +
6829 +/*------------------------------------------*/
6830 +/* PCI Control Registers                    */
6831 +/*------------------------------------------*/
6832 +#define        PCIC_CONTROL            (*(volatile unsigned int *)(PCI_CONFIG_BASE))
6833 +#define                PCIC_CONTROL_CFG_DONE                           (1<<0)
6834 +#define                PCIC_CONTROL_DIS_SLAVE_TO                       (1<<1)
6835 +#define                PCIC_CONTROL_FORCE_DELAY_READ           (1<<2)
6836 +#define                PCIC_CONTROL_FORCE_DELAY_READ_LINE      (1<<3)
6837 +#define                PCIC_CONTROL_FORCE_DELAY_READ_MULT      (1<<4)
6838 +#define                PCIC_CONTROL_MEM_SPACE_EN                       (1<<5)
6839 +#define                PCIC_CONTROL_MEM_MASK                           (1<<6)
6840 +#define                PCIC_CONTROL_IO_SPACE_EN                        (1<<7)
6841 +#define                PCIC_CONTROL_IO_MASK                            (1<<8)
6842 +/*                     PCIC_CONTROL_RESERVED                           (1<<9)  */
6843 +#define                PCIC_CONTROL_BASE0_EN                           (1<<10)
6844 +#define                PCIC_CONTROL_BASE1_EN                           (1<<11)
6845 +#define                PCIC_CONTROL_BASE2_EN                           (1<<12)
6846 +#define                PCIC_CONTROL_HOLD_MASTER_WRITE          (1<<13)
6847 +#define                PCIC_CONTROL_ARBITER_EN                         (1<<14)
6848 +#define        PCIC_INT_SOURCE         (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000004))
6849 +#define                PCIC_INT_SOURCE_PWR_MGMT                        (1<<0)
6850 +#define                PCIC_INT_SOURCE_PCI_TARGET                      (1<<1)
6851 +#define                PCIC_INT_SOURCE_PCI_MASTER                      (1<<2)
6852 +#define                PCIC_INT_SOURCE_POWER_WAKEUP            (1<<3)
6853 +#define                PCIC_INT_SOURCE_PMEIN                           (1<<4)
6854 +/*                     PCIC_INT_SOURCE_RESERVED                        (1<<5) */
6855 +/*                     PCIC_INT_SOURCE_RESERVED                        (1<<6) */
6856 +#define                PCIC_INT_SOURCE_PIC_INTA                        (1<<7)
6857 +#define                PCIC_INT_SOURCE_PIC_INTB                        (1<<8)
6858 +#define                PCIC_INT_SOURCE_PIC_INTC                        (1<<9)
6859 +#define                PCIC_INT_SOURCE_PIC_INTD                        (1<<10)
6860 +#define                PCIC_INT_SOURCE_SOFT_INT0                       (1<<11)
6861 +#define                PCIC_INT_SOURCE_SOFT_INT1                       (1<<12)
6862 +#define                PCIC_INT_SOURCE_SOFT_INT2                       (1<<13)
6863 +#define                PCIC_INT_SOURCE_SOFT_INT3                       (1<<14)
6864 +#define        PCIC_INT_CLEAR          (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000008))
6865 +#define                PCIC_INT_CLEAR_PM                                       (1<<0)
6866 +#define                PCIC_INT_CLEAR_PCI_TARGET                       (1<<1)
6867 +#define                PCIC_INT_CLEAR_PCI_MASTER                       (1<<2)
6868 +/*                     PCIC_INT_CLEAR_RESERVED                         (1<<3)  */
6869 +#define                PCIC_INT_CLEAR_PMEIN                            (1<<4)
6870 +/*                     PCIC_INT_CLEAR_RESERVED                         (1<<5)  */
6871 +/*                     PCIC_INT_CLEAR_RESERVED                         (1<<6)  */
6872 +#define                PCIC_INT_CLEAR_PCI_INTA                         (1<<7)
6873 +#define                PCIC_INT_CLEAR_PCI_INTB                         (1<<8)
6874 +#define                PCIC_INT_CLEAR_PCI_INTC                         (1<<9)
6875 +#define                PCIC_INT_CLEAR_PCI_INTD                         (1<<10)
6876 +#define                PCIC_INT_CLEAR_SOFT_INT0                        (1<<11)
6877 +#define                PCIC_INT_CLEAR_SOFT_INT1                        (1<<12)
6878 +#define                PCIC_INT_CLEAR_SOFT_INT2                        (1<<13)
6879 +#define                PCIC_INT_CLEAR_SOFT_INT3                        (1<<14)
6880 +#define        PCIC_INT_EN_AVAL        (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000000c))
6881 +#define                PCIC_INT_EN_AVAL_PM                                     (1<<0)
6882 +#define                PCIC_INT_EN_AVAL_PCI_TARGET                     (1<<1)
6883 +#define                PCIC_INT_EN_AVAL_PCI_MASTER                     (1<<2)
6884 +/*                     PCIC_INT_EN_AVAL_RESERVED                       (1<<3)  */
6885 +#define                PCIC_INT_EN_AVAL_PMEIN                          (1<<4)
6886 +/*                     PCIC_INT_EN_AVAL_RESERVED                       (1<<5)  */
6887 +/*                     PCIC_INT_EN_AVAL_RESERVED                       (1<<6)  */
6888 +#define                PCIC_INT_EN_AVAL_PCI_INTA                       (1<<7)
6889 +#define                PCIC_INT_EN_AVAL_PCI_INTB                       (1<<8)
6890 +#define                PCIC_INT_EN_AVAL_PCI_INTC                       (1<<9)
6891 +#define                PCIC_INT_EN_AVAL_PCI_INTD                       (1<<10)
6892 +#define                PCIC_INT_EN_AVAL_SOFT_INT0                      (1<<11)
6893 +#define                PCIC_INT_EN_AVAL_SOFT_INT1                      (1<<12)
6894 +#define                PCIC_INT_EN_AVAL_SOFT_INT2                      (1<<13)
6895 +#define                PCIC_INT_EN_AVAL_SOFT_INT3                      (1<<14)
6896 +#define        PCIC_INT_EN_PCI                 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000010))
6897 +#define                PCIC_INT_EN_PCI_PM                                      (1<<0)
6898 +#define                PCIC_INT_EN_PCI_PCI_TARGET                      (1<<1)
6899 +#define                PCIC_INT_EN_PCI_PCI_MASTER                      (1<<2)
6900 +/*                     PCIC_INT_EN_PCI_RESERVED                        (1<<3)  */
6901 +#define                PCIC_INT_EN_PCI_PMEIN                           (1<<4)
6902 +/*                     PCIC_INT_EN_PCI_RESERVED                        (1<<5)  */
6903 +/*                     PCIC_INT_EN_PCI_RESERVED                        (1<<6)  */
6904 +#define                PCIC_INT_EN_PCI_PCI_INTA                        (1<<7)
6905 +#define                PCIC_INT_EN_PCI_PCI_INTB                        (1<<8)
6906 +#define                PCIC_INT_EN_PCI_PCI_INTC                        (1<<9)
6907 +#define                PCIC_INT_EN_PCI_PCI_INTD                        (1<<10)
6908 +#define                PCIC_INT_EN_PCI_SOFT_INT0                       (1<<11)
6909 +#define                PCIC_INT_EN_PCI_SOFT_INT1                       (1<<12)
6910 +#define                PCIC_INT_EN_PCI_SOFT_INT2                       (1<<13)
6911 +#define                PCIC_INT_EN_PCI_SOFT_INT3                       (1<<14)
6912 +#define        PCIC_INT_SWSET          (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000014))
6913 +#define                PCIC_INT_SWSET_SOFT_INT0                        (1<<0)
6914 +#define                PCIC_INT_SWSET_SOFT_INT1                        (1<<1)
6915 +#define                PCIC_INT_SWSET_SOFT_INT2                        (1<<2)
6916 +#define                PCIC_INT_SWSET_SOFT_INT3                        (1<<3)
6917 +#define        PCIC_PM_CTL                     (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000018))
6918 +#define                PCIC_PM_CTL_PWR_STATE_MASK                      (0x02)
6919 +/*                     PCIC_PM_CTL_RESERVED                            (1<<2) */
6920 +/*                     PCIC_PM_CTL_RESERVED                            (1<<3) */
6921 +/*                     PCIC_PM_CTL_RESERVED                            (1<<4) */
6922 +/*                     PCIC_PM_CTL_RESERVED                            (1<<5) */
6923 +/*                     PCIC_PM_CTL_RESERVED                            (1<<6) */
6924 +/*                     PCIC_PM_CTL_RESERVED                            (1<<7) */
6925 +/*                     PCIC_PM_CTL_RESERVED                            (1<<8) */
6926 +/*                     PCIC_PM_CTL_RESERVED                            (1<<9) */
6927 +#define                PCIC_PM_CTL_PWR_SUPPORT                         (1<<10)
6928 +#define                PCIC_PM_CTL_PMEIN                                       (1<<11)
6929 +#define                PCIC_PM_CTL_CAP_MASK    (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x0000001a))
6930 +#define        PCIC_PM_CONSUME         (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000001c))
6931 +#define                PCIC_PM_CONSUME_D0              (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001c))
6932 +#define                PCIC_PM_CONSUME_D1              (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001d))
6933 +#define                PCIC_PM_CONSUME_D2              (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001e))
6934 +#define                PCIC_PM_CONSUME_D3              (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001f))
6935 +#define        PCIC_PM_DISSAPATED      (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000020))
6936 +#define                PCIC_PM_DISSAPATED_D0   (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000020))
6937 +#define                PCIC_PM_DISSAPATED_D1   (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000021))
6938 +#define                PCIC_PM_DISSAPATED_D2   (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000022))
6939 +#define                PCIC_PM_DISSAPATED_D3   (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000023))
6940 +#define        PCIC_PM_DATA_SCALE      (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x00000024))
6941 +#define        PCIC_VEND_DEV_ID        (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000028))
6942 +#define        PCIC_SUB_VEND_DEV_ID    (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000002c))
6943 +#define        PCIC_CLASS_REV_ID       (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000030))
6944 +#define        PCIC_MAX_MIN            (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000034))
6945 +#define        PCIC_MAST_MEM_AT0       (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000003c))
6946 +#define        PCIC_MAST_MEM_AT1       (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000040))
6947 +#define        PCIC_MAST_MEM_AT2       (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000044))
6948 +#define        PCIC_SLAVE_MASK0        (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000004c))
6949 +#define        PCIC_SLAVE_MASK1        (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000050))
6950 +#define        PCIC_SLAVE_MASK2        (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000054))
6951 +#define        PCIC_SLAVE_BASE_AT0     (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000058))
6952 +#define        PCIC_SLAVE_BASE_AT1     (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000005c))
6953 +#define        PCIC_SLAVE_BASE_AT2     (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000060))
6954 +#define        PCIC_CONF_COMMAND       (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000090))
6955 +#define        PCIC_CONF_ADDR          (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000094))
6956 +#define        PCIC_CONF_DATA          (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000098))
6957 +
6958 +/*------------------------------------------*/
6959 +/* IIC_INTERFACE                            */
6960 +/*------------------------------------------*/
6961 +#define I2C_DATA_HI          (*(volatile unsigned int *)(I2C_BASE + 0x0))
6962 +#define I2C_DATA_LOW         (*(volatile unsigned int *)(I2C_BASE + 0x4))
6963 +#define I2C_CONFIG           (*(volatile unsigned int *)(I2C_BASE + 0x8))
6964 +#define I2C_DATA_READ        (*(volatile unsigned int *)(I2C_BASE + 0xC))
6965 +#define I2C_CLOCK_DIV        (*(volatile unsigned int *)(I2C_BASE + 0x10))
6966 +
6967 +#define I2CWRITE      0x200
6968 +#define I2CREAD       0x300
6969 +#define I2C_END_BURST 0x400
6970 +
6971 +/* read bits */
6972 +#define I2C_READ_ERROR    0x8000
6973 +#define I2C_READ_COMPLETE 0x4000
6974 +#define I2C_READ_BUSY     0x2000
6975 +
6976 +/* device types */
6977 +#define I2C_IO_EXPANDER      0x2
6978 +#define I2C_RTC              0xd
6979 +
6980 +/* device Addresses on I2C bus (EVM3) */
6981 +#define SEVEN_SEGMENT_DISP    0x23   /* Device type = 0x2, Addr = 3 */
6982 +#define EVM3_RTC              0xd0   /* Device type = 0xd, Addr = 0 */
6983 +#define EVM3_RTC_I2C_ADDR      0x0
6984 +
6985 +/*------------------------------------------*/
6986 +/* Ethernet MAC register offset definitions */
6987 +/*------------------------------------------*/
6988 +#define VMAC_DMACONFIG(X)      (*(volatile unsigned int *)(X + 0x00000000))
6989 +#define VMAC_INTSTS(X)         (*(volatile unsigned int *)(X + 0x00000004))
6990 +#define VMAC_INTMASK(X)        (*(volatile unsigned int *)(X + 0x00000008))
6991 +
6992 +#define VMAC_WRAPCLK(X)        (*(volatile unsigned int *)(X + 0x00000340))
6993 +#define VMAC_STATSBASE(X)      (*(volatile unsigned int *)(X + 0x00000400))
6994 +
6995 +#define VMAC_TCRPTR(X)         (*(volatile unsigned int *)(X + 0x00000100))
6996 +#define VMAC_TCRSIZE(X)        (*(volatile unsigned int *)(X + 0x00000104))
6997 +#define VMAC_TCRINTTHRESH(X)   (*(volatile unsigned int *)(X + 0x00000108))
6998 +#define VMAC_TCRTOTENT(X)      (*(volatile unsigned int *)(X + 0x0000010C))
6999 +#define VMAC_TCRFREEENT(X)     (*(volatile unsigned int *)(X + 0x00000110))
7000 +#define VMAC_TCRPENDENT(X)     (*(volatile unsigned int *)(X + 0x00000114))
7001 +#define VMAC_TCRENTINC(X)      (*(volatile unsigned int *)(X + 0x00000118))
7002 +#define VMAC_TXISRPACE(X)      (*(volatile unsigned int *)(X + 0x0000011c))
7003 +
7004 +
7005 +#define VMAC_TDMASTATE0(X)     (*(volatile unsigned int *)(X + 0x00000120))
7006 +#define VMAC_TDMASTATE1(X)     (*(volatile unsigned int *)(X + 0x00000124))
7007 +#define VMAC_TDMASTATE2(X)     (*(volatile unsigned int *)(X + 0x00000128))
7008 +#define VMAC_TDMASTATE3(X)     (*(volatile unsigned int *)(X + 0x0000012C))
7009 +#define VMAC_TDMASTATE4(X)     (*(volatile unsigned int *)(X + 0x00000130))
7010 +#define VMAC_TDMASTATE5(X)     (*(volatile unsigned int *)(X + 0x00000134))
7011 +#define VMAC_TDMASTATE6(X)     (*(volatile unsigned int *)(X + 0x00000138))
7012 +#define VMAC_TDMASTATE7(X)     (*(volatile unsigned int *)(X + 0x0000013C))
7013 +#define VMAC_TXPADDCNT(X)      (*(volatile unsigned int *)(X + 0x00000140))
7014 +#define VMAC_TXPADDSTART(X)    (*(volatile unsigned int *)(X + 0x00000144))
7015 +#define VMAC_TXPADDEND(X)      (*(volatile unsigned int *)(X + 0x00000148))
7016 +#define VMAC_TXQFLUSH(X)       (*(volatile unsigned int *)(X + 0x0000014C))
7017 +
7018 +#define VMAC_RCRPTR(X)         (*(volatile unsigned int *)(X + 0x00000200))
7019 +#define VMAC_RCRSIZE(X)        (*(volatile unsigned int *)(X + 0x00000204))
7020 +#define VMAC_RCRINTTHRESH(X)   (*(volatile unsigned int *)(X + 0x00000208))
7021 +#define VMAC_RCRTOTENT(X)      (*(volatile unsigned int *)(X + 0x0000020C))
7022 +#define VMAC_RCRFREEENT(X)     (*(volatile unsigned int *)(X + 0x00000210))
7023 +#define VMAC_RCRPENDENT(X)     (*(volatile unsigned int *)(X + 0x00000214))
7024 +#define VMAC_RCRENTINC(X)      (*(volatile unsigned int *)(X + 0x00000218))
7025 +#define VMAC_RXISRPACE(X)      (*(volatile unsigned int *)(X + 0x0000021c))
7026 +
7027 +#define VMAC_RDMASTATE0(X)     (*(volatile unsigned int *)(X + 0x00000220))
7028 +#define VMAC_RDMASTATE1(X)     (*(volatile unsigned int *)(X + 0x00000224))
7029 +#define VMAC_RDMASTATE2(X)     (*(volatile unsigned int *)(X + 0x00000228))
7030 +#define VMAC_RDMASTATE3(X)     (*(volatile unsigned int *)(X + 0x0000022C))
7031 +#define VMAC_RDMASTATE4(X)     (*(volatile unsigned int *)(X + 0x00000230))
7032 +#define VMAC_RDMASTATE5(X)     (*(volatile unsigned int *)(X + 0x00000234))
7033 +#define VMAC_RDMASTATE6(X)     (*(volatile unsigned int *)(X + 0x00000238))
7034 +#define VMAC_RDMASTATE7(X)     (*(volatile unsigned int *)(X + 0x0000023C))
7035 +#define VMAC_FBLADDCNT(X)      (*(volatile unsigned int *)(X + 0x00000240))
7036 +#define VMAC_FBLADDSTART(X)    (*(volatile unsigned int *)(X + 0x00000244))
7037 +#define VMAC_FBLADDEND(X)      (*(volatile unsigned int *)(X + 0x00000248))
7038 +#define VMAC_RXONOFF(X)        (*(volatile unsigned int *)(X + 0x0000024C))
7039 +
7040 +#define VMAC_FBL0NEXTD(X)      (*(volatile unsigned int *)(X + 0x00000280))
7041 +#define VMAC_FBL0LASTD(X)      (*(volatile unsigned int *)(X + 0x00000284))
7042 +#define VMAC_FBL0COUNTD(X)     (*(volatile unsigned int *)(X + 0x00000288))
7043 +#define VMAC_FBL0BUFSIZE(X)    (*(volatile unsigned int *)(X + 0x0000028C))
7044 +
7045 +#define VMAC_MACCONTROL(X)     (*(volatile unsigned int *)(X + 0x00000300))
7046 +#define VMAC_MACSTATUS(X)      (*(volatile unsigned int *)(X + 0x00000304))
7047 +#define VMAC_MACADDRHI(X)      (*(volatile unsigned int *)(X + 0x00000308))
7048 +#define VMAC_MACADDRLO(X)      (*(volatile unsigned int *)(X + 0x0000030C))
7049 +#define VMAC_MACHASH1(X)       (*(volatile unsigned int *)(X + 0x00000310))
7050 +#define VMAC_MACHASH2(X)       (*(volatile unsigned int *)(X + 0x00000314))
7051 +
7052 +#define VMAC_WRAPCLK(X)        (*(volatile unsigned int *)(X + 0x00000340))
7053 +#define VMAC_BOFTEST(X)        (*(volatile unsigned int *)(X + 0x00000344))
7054 +#define VMAC_PACTEST(X)        (*(volatile unsigned int *)(X + 0x00000348))
7055 +#define VMAC_PAUSEOP(X)        (*(volatile unsigned int *)(X + 0x0000034C))
7056 +
7057 +#define VMAC_MDIOCONTROL(X)    (*(volatile unsigned int *)(X + 0x00000380))
7058 +#define VMAC_MDIOUSERACCESS(X) (*(volatile unsigned int *)(X +0x00000384))
7059 +#define VMAC_MDIOACK(X)        (*(volatile unsigned int *)(X + 0x00000388))
7060 +#define VMAC_MDIOLINK(X)       (*(volatile unsigned int *)(X + 0x0000038C))
7061 +#define VMAC_MDIOMACPHY(X)     (*(volatile unsigned int *)(X + 0x00000390))
7062 +
7063 +#define VMAC_STATS_BASE(X)     (X + 0x00000400)
7064 +
7065 +#endif __AVALANCHE_REGS_H
7066 +
7067 +
7068 +
7069 +
7070 +
7071 +
7072 diff -urN linux.old/include/asm-mips/ar7/avalanche_types.h linux.dev/include/asm-mips/ar7/avalanche_types.h
7073 --- linux.old/include/asm-mips/ar7/avalanche_types.h    1970-01-01 01:00:00.000000000 +0100
7074 +++ linux.dev/include/asm-mips/ar7/avalanche_types.h    2005-11-10 01:10:46.071588750 +0100
7075 @@ -0,0 +1,126 @@
7076 +/*------------------------------------------------------------------------------------------*\
7077 +\*------------------------------------------------------------------------------------------*/
7078 +#ifndef _avalanche_types_h_
7079 +#define _avalanche_types_h_
7080 +
7081 +/*--- #include <asm/avalanche/generic/hal_modules/haltypes.h> ---*/
7082 +#ifndef TRUE
7083 +#define TRUE 1
7084 +#endif
7085 +#ifndef FALSE
7086 +#define FALSE 0
7087 +#endif
7088 +#ifndef NULL
7089 +#define NULL (void *)0
7090 +#endif
7091 +
7092 +/*------------------------------------------------------------------------------------------*\
7093 + * Typen für Texas GPL Module
7094 +\*------------------------------------------------------------------------------------------*/
7095 +#ifndef __UINT8_T__
7096 +typedef unsigned char   UINT8;
7097 +#define __UINT8_T__
7098 +#endif
7099 +
7100 +#ifndef __UCHAR_T__
7101 +typedef unsigned char   UCHAR;
7102 +#define __UCHAR_T__
7103 +#endif
7104 +
7105 +#ifndef __INT8_T__
7106 +typedef signed char     INT8;
7107 +#define __INT8_T__
7108 +#endif
7109 +
7110 +#ifndef __UINT16_T__
7111 +typedef unsigned short  UINT16;
7112 +#define __UINT16_T__
7113 +#endif
7114 +
7115 +#ifndef __USHORT_T__
7116 +typedef unsigned short  USHORT;
7117 +#define __USHORT_T__
7118 +#endif
7119 +
7120 +#ifndef __INT16_T__
7121 +typedef signed short    INT16;
7122 +#define __INT16_T__
7123 +#endif
7124 +
7125 +#ifndef __UINT32_T__
7126 +typedef unsigned int    UINT32;
7127 +#define __UINT32_T__
7128 +#endif
7129 +
7130 +#ifndef __UINT_T__
7131 +typedef unsigned int    UINT;
7132 +#define __UINT_T__
7133 +#endif
7134 +
7135 +#ifndef __INT32_T__
7136 +typedef signed int      INT32;
7137 +#define __INT32_T__
7138 +#endif
7139 +
7140 +#ifndef __ULONG_T__
7141 +typedef unsigned long   ULONG;
7142 +#define __ULONG_T__
7143 +#endif
7144 +
7145 +#ifndef __BOOL_T__
7146 +typedef int             BOOL;
7147 +#define __BOOL_T__
7148 +#endif
7149 +
7150 +#ifndef __STATUS_T__
7151 +typedef int             STATUS;
7152 +#define __STATUS_T__
7153 +#endif
7154 +
7155 +/*------------------------------------------------------------------------------------------*\
7156 +\*------------------------------------------------------------------------------------------*/
7157 +typedef void (*p_vlynq_intr_cntrl_isr_t)(void *,void *,void *);
7158 +typedef INT32 (*p_vlynq_interrupt_vector_set_t)(void *, UINT32, UINT32, INT32, INT32, INT32);
7159 +typedef INT32 (*p_vlynq_interrupt_vector_cntl_t)(void *, UINT32, INT32, UINT32);
7160 +typedef UINT32 (*p_vlynq_interrupt_get_count_t)(void *, UINT32);
7161 +typedef INT32 (*p_vlynq_install_isr_t)(void *, UINT32, p_vlynq_intr_cntrl_isr_t, void *, void *, void *);
7162 +typedef INT32 (*p_vlynq_uninstall_isr_t)(void *, UINT32, void *, void *, void *);
7163 +typedef void (*p_vlynq_root_isr_t)(void *);
7164 +typedef void (*p_vlynq_delay_t)(UINT32);
7165 +typedef INT32 (*p_vlynq_interrupt_vector_map_t)(void *, INT32, UINT32, UINT32);
7166 +typedef INT32 (*p_vlynq_interrupt_set_polarity_t)(void *, INT32, UINT32, INT32);
7167 +typedef INT32 (*p_vlynq_interrupt_get_polarity_t)(void *, INT32, UINT32);
7168 +typedef INT32 (*p_vlynq_interrupt_set_type_t)(void *, INT32, UINT32, INT32);
7169 +typedef INT32 (*p_vlynq_interrupt_get_type_t)(void *, INT32, UINT32);
7170 +typedef INT32 (*p_vlynq_interrupt_enable_t)(void *, INT32, UINT32);
7171 +typedef INT32 (*p_vlynq_interrupt_disable_t)(void *, INT32, UINT32);
7172 +
7173 +/*------------------------------------------------------------------------------------------*\
7174 +\*------------------------------------------------------------------------------------------*/
7175 +extern p_vlynq_interrupt_vector_set_t p_vlynq_interrupt_vector_set;
7176 +extern p_vlynq_interrupt_vector_cntl_t p_vlynq_interrupt_vector_cntl;
7177 +extern p_vlynq_interrupt_get_count_t p_vlynq_interrupt_get_count;
7178 +extern p_vlynq_install_isr_t p_vlynq_install_isr;
7179 +extern p_vlynq_uninstall_isr_t p_vlynq_uninstall_isr;
7180 +extern p_vlynq_root_isr_t p_vlynq_root_isr;
7181 +extern p_vlynq_delay_t p_vlynq_delay;
7182 +extern p_vlynq_interrupt_vector_map_t p_vlynq_interrupt_vector_map;
7183 +extern p_vlynq_interrupt_set_polarity_t p_vlynq_interrupt_set_polarity;
7184 +extern p_vlynq_interrupt_get_polarity_t p_vlynq_interrupt_get_polarity;
7185 +extern p_vlynq_interrupt_set_type_t p_vlynq_interrupt_set_type;
7186 +extern p_vlynq_interrupt_get_type_t p_vlynq_interrupt_get_type;
7187 +extern p_vlynq_interrupt_enable_t p_vlynq_interrupt_enable;
7188 +extern p_vlynq_interrupt_disable_t p_vlynq_interrupt_disable;
7189 +extern void *p_vlynqDevice0;
7190 +extern void *p_vlynqDevice1;
7191 +
7192 +/*------------------------------------------------------------------------------------------*\
7193 +\*------------------------------------------------------------------------------------------*/
7194 +enum _avalanche_need_ {
7195 +    avalanche_need_vlynq,
7196 +    avalanche_need_auto_mdix
7197 +};
7198 +
7199 +int avalanche_need(enum _avalanche_need_);
7200 +
7201 +#endif /*--- #ifndef _avalanche_types_h_ ---*/
7202 diff -urN linux.old/include/asm-mips/ar7/if_port.h linux.dev/include/asm-mips/ar7/if_port.h
7203 --- linux.old/include/asm-mips/ar7/if_port.h    1970-01-01 01:00:00.000000000 +0100
7204 +++ linux.dev/include/asm-mips/ar7/if_port.h    2005-11-10 01:10:46.071588750 +0100
7205 @@ -0,0 +1,26 @@
7206 +/*******************************************************************************
7207 + * FILE PURPOSE:    Interface port id Header file
7208 + *******************************************************************************
7209 + * FILE NAME:       if_port.h
7210 + *
7211 + * DESCRIPTION:     Header file carrying information about port ids of interfaces
7212 + *
7213 + *
7214 + * (C) Copyright 2003, Texas Instruments, Inc
7215 + ******************************************************************************/
7216 +#ifndef _IF_PORT_H_
7217 +#define _IF_PORT_H_
7218 +
7219 +#define AVALANCHE_CPMAC_LOW_PORT_ID         0
7220 +#define AVALANCHE_CPMAC_HIGH_PORT_ID        1
7221 +#define AVALANCHE_USB_PORT_ID               2
7222 +#define AVALANCHE_WLAN_PORT_ID              3
7223 +
7224 +
7225 +#define AVALANCHE_MARVELL_BASE_PORT_ID      4
7226 +
7227 +/* The marvell ports occupy port ids from  4 to 8 */
7228 +/* so the next port id number should start at 9   */
7229 +
7230 +
7231 +#endif /* _IF_PORT_H_ */
7232 diff -urN linux.old/include/asm-mips/ar7/sangam.h linux.dev/include/asm-mips/ar7/sangam.h
7233 --- linux.old/include/asm-mips/ar7/sangam.h     1970-01-01 01:00:00.000000000 +0100
7234 +++ linux.dev/include/asm-mips/ar7/sangam.h     2005-11-10 01:10:46.071588750 +0100
7235 @@ -0,0 +1,180 @@
7236 +#ifndef _SANGAM_H_
7237 +#define _SANGAM_H_
7238 +
7239 +#include <linux/config.h>
7240 +#include <asm/addrspace.h>
7241 +
7242 +/*----------------------------------------------------
7243 + * Sangam's Module Base Addresses
7244 + *--------------------------------------------------*/
7245 +#define AVALANCHE_ADSL_SUB_SYS_MEM_BASE       (KSEG1ADDR(0x01000000)) /* AVALANCHE ADSL Mem Base */
7246 +#define AVALANCHE_BROADBAND_INTERFACE__BASE   (KSEG1ADDR(0x02000000)) /* AVALANCHE BBIF */
7247 +#define AVALANCHE_ATM_SAR_BASE                (KSEG1ADDR(0x03000000)) /* AVALANCHE ATM SAR */
7248 +#define AVALANCHE_USB_SLAVE_BASE              (KSEG1ADDR(0x03400000)) /* AVALANCHE USB SLAVE */
7249 +#define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE      (KSEG1ADDR(0x04000000)) /* AVALANCHE VLYNQ 0 Mem map */
7250 +#define AVALANCHE_LOW_CPMAC_BASE              (KSEG1ADDR(0x08610000)) /* AVALANCHE CPMAC 0 */
7251 +#define AVALANCHE_EMIF_CONTROL_BASE           (KSEG1ADDR(0x08610800)) /* AVALANCHE EMIF */
7252 +#define AVALANCHE_GPIO_BASE                   (KSEG1ADDR(0x08610900)) /* AVALANCHE GPIO */
7253 +#define AVALANCHE_CLOCK_CONTROL_BASE          (KSEG1ADDR(0x08610A00)) /* AVALANCHE Clock Control */
7254 +#define AVALANCHE_WATCHDOG_TIMER_BASE         (KSEG1ADDR(0x08610B00)) /* AVALANCHE Watch Dog Timer */
7255 +#define AVALANCHE_TIMER0_BASE                 (KSEG1ADDR(0x08610C00)) /* AVALANCHE Timer 1 */
7256 +#define AVALANCHE_TIMER1_BASE                 (KSEG1ADDR(0x08610D00)) /* AVALANCHE Timer 2 */
7257 +#define AVALANCHE_UART0_REGS_BASE             (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
7258 +#define AVALANCHE_UART1_REGS_BASE             (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 0 */
7259 +#define AVALANCHE_I2C_BASE                    (KSEG1ADDR(0x08611000)) /* AVALANCHE I2C */
7260 +#define AVALANCHE_USB_SLAVE_CONTROL_BASE      (KSEG1ADDR(0x08611200)) /* AVALANCHE USB DMA */
7261 +#define AVALANCHE_MCDMA0_CTRL_BASE            (KSEG1ADDR(0x08611400)) /* AVALANCHE MC DMA 0 (channels 0-3) */
7262 +#define AVALANCHE_RESET_CONTROL_BASE          (KSEG1ADDR(0x08611600)) /* AVALANCHE Reset Control */
7263 +#define AVALANCHE_BIST_CONTROL_BASE           (KSEG1ADDR(0x08611700)) /* AVALANCHE BIST Control */
7264 +#define AVALANCHE_LOW_VLYNQ_CONTROL_BASE      (KSEG1ADDR(0x08611800)) /* AVALANCHE VLYNQ0 Control */
7265 +#define AVALANCHE_DEVICE_CONFIG_LATCH_BASE    (KSEG1ADDR(0x08611A00)) /* AVALANCHE Device Config Latch */
7266 +#define AVALANCHE_HIGH_VLYNQ_CONTROL_BASE     (KSEG1ADDR(0x08611C00)) /* AVALANCHE VLYNQ1 Control */
7267 +#define AVALANCHE_MDIO_BASE                   (KSEG1ADDR(0x08611E00)) /* AVALANCHE MDIO    */
7268 +#define AVALANCHE_FSER_BASE                   (KSEG1ADDR(0x08612000)) /* AVALANCHE FSER base */
7269 +#define AVALANCHE_INTC_BASE                   (KSEG1ADDR(0x08612400)) /* AVALANCHE INTC  */
7270 +#define AVALANCHE_HIGH_CPMAC_BASE             (KSEG1ADDR(0x08612800)) /* AVALANCHE CPMAC 1 */
7271 +#define AVALANCHE_HIGH_VLYNQ_MEM_MAP_BASE     (KSEG1ADDR(0x0C000000)) /* AVALANCHE VLYNQ 1 Mem map */
7272 +
7273 +#define AVALANCHE_SDRAM_BASE                  0x14000000UL
7274 +
7275 +
7276 +/*----------------------------------------------------
7277 + * Sangam Interrupt Map (Primary Interrupts)
7278 + *--------------------------------------------------*/
7279 +
7280 +#define AVALANCHE_UNIFIED_SECONDARY_INT            0
7281 +#define AVALANCHE_EXT_INT_0                        1
7282 +#define AVALANCHE_EXT_INT_1                        2
7283 +/* Line#  3 to 4 are reserved                            */
7284 +#define AVALANCHE_TIMER_0_INT                      5
7285 +#define AVALANCHE_TIMER_1_INT                      6
7286 +#define AVALANCHE_UART0_INT                        7
7287 +#define AVALANCHE_UART1_INT                        8
7288 +#define AVALANCHE_DMA_INT0                         9
7289 +#define AVALANCHE_DMA_INT1                        10
7290 +/* Line# 11 to 14 are reserved                    */
7291 +#define AVALANCHE_ATM_SAR_INT                     15
7292 +/* Line# 16 to 18 are reserved                    */
7293 +#define AVALANCHE_LOW_CPMAC_INT                   19
7294 +/* Line# 20 is reserved                           */
7295 +#define AVALANCHE_LOW_VLYNQ_INT                   21
7296 +#define AVALANCHE_CODEC_WAKEUP_INT                22
7297 +/* Line# 23 is reserved                           */
7298 +#define AVALANCHE_USB_SLAVE_INT                   24
7299 +#define AVALANCHE_HIGH_VLYNQ_INT                  25
7300 +/* Line# 26 to 27 are reserved                    */
7301 +#define AVALANCHE_UNIFIED_PHY_INT                 28
7302 +#define AVALANCHE_I2C_INT                         29
7303 +#define AVALANCHE_DMA_INT2                        30
7304 +#define AVALANCHE_DMA_INT3                        31
7305 +/* Line# 32 is reserved                           */
7306 +#define AVALANCHE_HIGH_CPMAC_INT                  33
7307 +/* Line# 34 to 36 is reserved                     */
7308 +#define AVALANCHE_VDMA_VT_RX_INT                  37
7309 +#define AVALANCHE_VDMA_VT_TX_INT                  38
7310 +#define AVALANCHE_ADSL_SUB_SYSTEM_INT             39
7311 +
7312 +
7313 +#define AVALANCHE_EMIF_INT                        47
7314 +
7315 +
7316 +
7317 +/*-----------------------------------------------------------
7318 + * Sangam's Reset Bits
7319 + *---------------------------------------------------------*/
7320 +
7321 +#define AVALANCHE_UART0_RESET_BIT                  0
7322 +#define AVALANCHE_UART1_RESET_BIT                  1
7323 +#define AVALANCHE_I2C_RESET_BIT                    2
7324 +#define AVALANCHE_TIMER0_RESET_BIT                 3
7325 +#define AVALANCHE_TIMER1_RESET_BIT                 4
7326 +/* Reset bit  5 is reserved.                       */
7327 +#define AVALANCHE_GPIO_RESET_BIT                   6
7328 +#define AVALANCHE_ADSL_SUB_SYS_RESET_BIT           7
7329 +#define AVALANCHE_USB_SLAVE_RESET_BIT              8
7330 +#define AVALANCHE_ATM_SAR_RESET_BIT                9
7331 +/* Reset bit 10 is reserved.                      */
7332 +#define AVALANCHE_VDMA_VT_RESET_BIT               11
7333 +#define AVALANCHE_FSER_RESET_BIT                  12
7334 +/* Reset bit 13 to 15 are reserved                */
7335 +#define AVALANCHE_HIGH_VLYNQ_RESET_BIT            16
7336 +#define AVALANCHE_LOW_CPMAC_RESET_BIT             17
7337 +#define AVALANCHE_MCDMA_RESET_BIT                 18
7338 +#define AVALANCHE_BIST_RESET_BIT                  19
7339 +#define AVALANCHE_LOW_VLYNQ_RESET_BIT             20
7340 +#define AVALANCHE_HIGH_CPMAC_RESET_BIT            21
7341 +#define AVALANCHE_MDIO_RESET_BIT                  22
7342 +#define AVALANCHE_ADSL_SUB_SYS_DSP_RESET_BIT      23
7343 +/* Reset bit 24 to 25 are reserved                */
7344 +#define AVALANCHE_LOW_EPHY_RESET_BIT              26
7345 +/* Reset bit 27 to 31 are reserved                */
7346 +
7347 +
7348 +#define AVALANCHE_POWER_MODULE_USBSP               0
7349 +#define AVALANCHE_POWER_MODULE_WDTP                1
7350 +#define AVALANCHE_POWER_MODULE_UT0P                2
7351 +#define AVALANCHE_POWER_MODULE_UT1P                3
7352 +#define AVALANCHE_POWER_MODULE_IICP                4
7353 +#define AVALANCHE_POWER_MODULE_VDMAP               5
7354 +#define AVALANCHE_POWER_MODULE_GPIOP               6
7355 +#define AVALANCHE_POWER_MODULE_VLYNQ1P             7
7356 +#define AVALANCHE_POWER_MODULE_SARP                8
7357 +#define AVALANCHE_POWER_MODULE_ADSLP               9
7358 +#define AVALANCHE_POWER_MODULE_EMIFP              10
7359 +#define AVALANCHE_POWER_MODULE_ADSPP              12
7360 +#define AVALANCHE_POWER_MODULE_RAMP               13
7361 +#define AVALANCHE_POWER_MODULE_ROMP               14
7362 +#define AVALANCHE_POWER_MODULE_DMAP               15
7363 +#define AVALANCHE_POWER_MODULE_BISTP              16
7364 +#define AVALANCHE_POWER_MODULE_TIMER0P            18
7365 +#define AVALANCHE_POWER_MODULE_TIMER1P            19
7366 +#define AVALANCHE_POWER_MODULE_EMAC0P             20
7367 +#define AVALANCHE_POWER_MODULE_EMAC1P             22
7368 +#define AVALANCHE_POWER_MODULE_EPHYP              24
7369 +#define AVALANCHE_POWER_MODULE_VLYNQ0P            27
7370 +
7371 +
7372 +
7373 +
7374 +
7375 +/*
7376 + * Sangam board vectors
7377 + */
7378 +
7379 +#define AVALANCHE_VECS       (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
7380 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
7381 +
7382 +/*-----------------------------------------------------------------------------
7383 + * Sangam's system register.
7384 + *
7385 + *---------------------------------------------------------------------------*/
7386 +#define AVALANCHE_DCL_BOOTCR          (KSEG1ADDR(0x08611A00))
7387 +#define AVALANCHE_EMIF_SDRAM_CFG      (AVALANCHE_EMIF_CONTROL_BASE + 0x8)
7388 +#define AVALANCHE_RST_CTRL_PRCR       (KSEG1ADDR(0x08611600))
7389 +#define AVALANCHE_RST_CTRL_SWRCR      (KSEG1ADDR(0x08611604))
7390 +#define AVALANCHE_RST_CTRL_RSR        (KSEG1ADDR(0x08611600))
7391 +
7392 +#define AVALANCHE_POWER_CTRL_PDCR     (KSEG1ADDR(0x08610A00))
7393 +#define AVALANCHE_WAKEUP_CTRL_WKCR    (KSEG1ADDR(0x08610A0C))
7394 +
7395 +#define AVALANCHE_GPIO_DATA_IN        (AVALANCHE_GPIO_BASE +  0x0)
7396 +#define AVALANCHE_GPIO_DATA_OUT       (AVALANCHE_GPIO_BASE +  0x4)
7397 +#define AVALANCHE_GPIO_DIR            (AVALANCHE_GPIO_BASE +  0x8)
7398 +#define AVALANCHE_GPIO_ENBL           (AVALANCHE_GPIO_BASE +  0xC)
7399 +#define AVALANCHE_CVR                 (AVALANCHE_GPIO_BASE +  0x14)
7400 +
7401 +/*
7402 + * Yamon Prom print address.
7403 + */
7404 +#define AVALANCHE_YAMON_FUNCTION_BASE             (KSEG1ADDR(0x10000500))
7405 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR     (AVALANCHE_YAMON_FUNCTION_BASE + 0x4)  /* print_count function */
7406 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR           (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
7407 +
7408 +#define AVALANCHE_BASE_BAUD       ( 3686400 / 16 )
7409 +
7410 +#define  AVALANCHE_GPIO_PIN_COUNT         32
7411 +#define  AVALANCHE_GPIO_OFF_MAP           {0xF34FFFC0}
7412 +
7413 +#include "sangam_boards.h"
7414 +
7415 +#endif /*_SANGAM_H_ */
7416 diff -urN linux.old/include/asm-mips/ar7/sangam_boards.h linux.dev/include/asm-mips/ar7/sangam_boards.h
7417 --- linux.old/include/asm-mips/ar7/sangam_boards.h      1970-01-01 01:00:00.000000000 +0100
7418 +++ linux.dev/include/asm-mips/ar7/sangam_boards.h      2005-11-10 01:10:46.071588750 +0100
7419 @@ -0,0 +1,77 @@
7420 +#ifndef _SANGAM_BOARDS_H
7421 +#define _SANGAM_BOARDS_H
7422 +
7423 +// Let us define board specific information here.
7424 +
7425 +
7426 +#if defined(CONFIG_AR7DB)
7427 +
7428 +#define AFECLK_FREQ                                 35328000
7429 +#define REFCLK_FREQ                                 25000000
7430 +#define OSC3_FREQ                                   24000000
7431 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
7432 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x55555555
7433 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
7434 +
7435 +#endif
7436 +
7437 +
7438 +#if defined(CONFIG_AR7RD)
7439 +#define AFECLK_FREQ                                 35328000
7440 +#define REFCLK_FREQ                                 25000000
7441 +#define OSC3_FREQ                                   24000000
7442 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
7443 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x2
7444 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
7445 +#endif
7446 +
7447 +
7448 +#if defined(CONFIG_AR7WI)
7449 +#define AFECLK_FREQ                                 35328000
7450 +#define REFCLK_FREQ                                 25000000
7451 +#define OSC3_FREQ                                   24000000
7452 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
7453 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x2
7454 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
7455 +#endif
7456 +
7457 +
7458 +#if defined(CONFIG_AR7V)
7459 +#define AFECLK_FREQ                                 35328000
7460 +#define REFCLK_FREQ                                 25000000
7461 +#define OSC3_FREQ                                   24000000
7462 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
7463 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x2
7464 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
7465 +#endif
7466 +
7467 +
7468 +#if defined(CONFIG_AR7WRD)
7469 +#define AFECLK_FREQ                                 35328000
7470 +#define REFCLK_FREQ                                 25000000
7471 +#define OSC3_FREQ                                   24000000
7472 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
7473 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x00010000
7474 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
7475 +#endif
7476 +
7477 +
7478 +#if defined(CONFIG_AR7VWI)
7479 +#define AFECLK_FREQ                                 35328000
7480 +#define REFCLK_FREQ                                 25000000
7481 +#define OSC3_FREQ                                   24000000
7482 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
7483 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x00010000
7484 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
7485 +#endif
7486 +
7487 +
7488 +#if defined CONFIG_SEAD2
7489 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0xAAAAAAAA
7490 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x55555555
7491 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0
7492 +#include <asm/mips-boards/sead.h>
7493 +#endif
7494 +
7495 +
7496 +#endif
7497 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx.h linux.dev/include/asm-mips/ar7/tnetd73xx.h
7498 --- linux.old/include/asm-mips/ar7/tnetd73xx.h  1970-01-01 01:00:00.000000000 +0100
7499 +++ linux.dev/include/asm-mips/ar7/tnetd73xx.h  2005-11-10 01:10:46.075589000 +0100
7500 @@ -0,0 +1,338 @@
7501 +/******************************************************************************
7502 + * FILE PURPOSE:    TNETD73xx Common Header File
7503 + ******************************************************************************
7504 + * FILE NAME:       tnetd73xx.h
7505 + *
7506 + * DESCRIPTION:     shared typedef's, constants and API for TNETD73xx
7507 + *
7508 + * REVISION HISTORY:
7509 + * 27 Nov 02 - PSP TII
7510 + *
7511 + * (C) Copyright 2002, Texas Instruments, Inc
7512 + *******************************************************************************/
7513 +
7514 +/*
7515 + *
7516 + *
7517 + *   These are const, typedef, and api definitions for tnetd73xx.
7518 + *
7519 + *   NOTES:
7520 + *   1. This file may be included into both C and Assembly files.
7521 + *       - for .s files, please do #define _ASMLANGUAGE in your ASM file to
7522 + *           avoid C data types (typedefs) below;
7523 + *       - for .c files, you don't have to do anything special.
7524 + *
7525 + *   2. This file has a number of sections for each SOC subsystem. When adding
7526 + *       a new constant, find the subsystem you are working on and follow the
7527 + *       name pattern. If you are adding another typedef for your interface, please,
7528 + *       place it with other typedefs and function prototypes.
7529 + *
7530 + *   3. Please, DO NOT add any macros or types that are local to a subsystem to avoid
7531 + *       cluttering. Include such items directly into the module's .c file or have a
7532 + *       local .h file to pass data between smaller modules. This file defines only
7533 + *       shared items.
7534 + */
7535 +
7536 +#ifndef __TNETD73XX_H__
7537 +#define __TNETD73XX_H__
7538 +
7539 +#ifndef _ASMLANGUAGE        /* This part not for assembly language */
7540 +
7541 +extern unsigned int tnetd73xx_mips_freq;
7542 +extern unsigned int tnetd73xx_vbus_freq;
7543 +
7544 +#include "tnetd73xx_err.h"
7545 +
7546 +#endif /* _ASMLANGUAGE */
7547 +
7548 +
7549 +/*******************************************************************************************
7550 +*   Emerald core specific
7551 +******************************************************************************************** */
7552 +
7553 +#ifdef  BIG_ENDIAN
7554 +#elif defined(LITTLE_ENDIAN)
7555 +#else
7556 +#error Need to define endianism
7557 +#endif
7558 +
7559 +#ifndef KSEG_MSK
7560 +#define KSEG_MSK                    0xE0000000 /* Most significant 3 bits denote kseg choice */
7561 +#endif
7562 +
7563 +#ifndef KSEG_INV_MASK
7564 +#define KSEG_INV_MASK               0x1FFFFFFF /* Inverted mask for kseg address */
7565 +#endif
7566 +
7567 +#ifndef KSEG0_BASE
7568 +#define KSEG0_BASE                  0x80000000
7569 +#endif
7570 +
7571 +#ifndef KSEG1_BASE
7572 +#define KSEG1_BASE                  0xA0000000
7573 +#endif
7574 +
7575 +#ifndef KSEG0
7576 +#define KSEG0(addr)                 (((__u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
7577 +#endif
7578 +
7579 +#ifndef KSEG1
7580 +#define KSEG1(addr)                 (((__u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
7581 +#endif
7582 +
7583 +#ifndef KUSEG
7584 +#define KUSEG(addr)                 ((__u32)(addr) & ~KSEG_MSK)
7585 +#endif
7586 +
7587 +#ifndef PHYS_ADDR
7588 +#define PHYS_ADDR(addr)             ((addr) & KSEG_INV_MASK)
7589 +#endif
7590 +
7591 +#ifndef PHYS_TO_K0
7592 +#define PHYS_TO_K0(addr)            (PHYS_ADDR(addr)|KSEG0_BASE)
7593 +#endif
7594 +
7595 +#ifndef PHYS_TO_K1
7596 +#define PHYS_TO_K1(addr)            (PHYS_ADDR(addr)|KSEG1_BASE)
7597 +#endif
7598 +
7599 +#ifndef REG8_ADDR
7600 +#define REG8_ADDR(addr)             (volatile __u8 *)(PHYS_TO_K1(addr))
7601 +#define REG8_DATA(addr)             (*(volatile __u8 *)(PHYS_TO_K1(addr)))
7602 +#define REG8_WRITE(addr, data)      REG8_DATA(addr) = data;
7603 +#define REG8_READ(addr, data)       data = (__u8) REG8_DATA(addr);
7604 +#endif
7605 +
7606 +#ifndef REG16_ADDR
7607 +#define REG16_ADDR(addr)            (volatile __u16 *)(PHYS_TO_K1(addr))
7608 +#define REG16_DATA(addr)            (*(volatile __u16 *)(PHYS_TO_K1(addr)))
7609 +#define REG16_WRITE(addr, data)     REG16_DATA(addr) = data;
7610 +#define REG16_READ(addr, data)      data = (__u16) REG16_DATA(addr);
7611 +#endif
7612 +
7613 +#ifndef REG32_ADDR
7614 +#define REG32_ADDR(addr)            (volatile __u32 *)(PHYS_TO_K1(addr))
7615 +#define REG32_DATA(addr)            (*(volatile __u32 *)(PHYS_TO_K1(addr)))
7616 +#define REG32_WRITE(addr, data)     REG32_DATA(addr) = data;
7617 +#define REG32_READ(addr, data)      data = (__u32) REG32_DATA(addr);
7618 +#endif
7619 +
7620 +#ifdef  _LINK_KSEG0_                /* Application is linked into KSEG0 space */
7621 +#define VIRT_ADDR(addr)             PHYS_TO_K0(PHYS_ADDR(addr))
7622 +#endif
7623 +
7624 +#ifdef  _LINK_KSEG1_                /* Application is linked into KSEG1 space */
7625 +#define VIRT_ADDR(addr)             PHYS_TO_K1(PHYS_ADDR(addr))
7626 +#endif
7627 +
7628 +#if !defined(_LINK_KSEG0_) && !defined(_LINK_KSEG1_)
7629 +#error  You must define _LINK_KSEG0_ or _LINK_KSEG1_ to compile the code.
7630 +#endif
7631 +
7632 +/* TNETD73XX chip definations */
7633 +
7634 +#define FREQ_1MHZ                       1000000
7635 +#define TNETD73XX_MIPS_FREQ             tnetd73xx_mips_freq /* CPU clock frequency */
7636 +#define TNETD73XX_VBUS_FREQ             tnetd73xx_vbus_freq /* originally (TNETD73XX_MIPS_FREQ/2) */
7637 +
7638 +#ifdef AR7SEAD2
7639 +#define TNETD73XX_MIPS_FREQ_DEFAULT     25000000       /* 25 Mhz for sead2 board crystal */
7640 +#else
7641 +#define TNETD73XX_MIPS_FREQ_DEFAULT     125000000      /* 125 Mhz */
7642 +#endif
7643 +#define TNETD73XX_VBUS_FREQ_DEFAULT     (TNETD73XX_MIPS_FREQ_DEFAULT / 2) /* Sync mode */
7644 +
7645 +
7646 +
7647 +/* Module base addresses */
7648 +#define TNETD73XX_ADSLSS_BASE               PHYS_TO_K1(0x01000000)      /* ADSLSS Module */
7649 +#define TNETD73XX_BBIF_CTRL_BASE            PHYS_TO_K1(0x02000000)      /* BBIF Control */
7650 +#define TNETD73XX_ATMSAR_BASE               PHYS_TO_K1(0x03000000)      /* ATM SAR */
7651 +#define TNETD73XX_USB_BASE                  PHYS_TO_K1(0x03400000)      /* USB Module */
7652 +#define TNETD73XX_VLYNQ0_BASE               PHYS_TO_K1(0x04000000)      /* VLYNQ0 Module */
7653 +#define TNETD73xx_EMAC0_BASE                PHYS_TO_K1(0x08610000)      /* EMAC0 Module*/
7654 +#define TNETD73XX_EMIF_BASE                 PHYS_TO_K1(0x08610800)      /* EMIF Module */
7655 +#define TNETD73XX_GPIO_BASE                 PHYS_TO_K1(0x08610900)      /* GPIO control */
7656 +#define TNETD73XX_CLOCK_CTRL_BASE           PHYS_TO_K1(0x08610A00)      /* Clock Control */
7657 +#define TNETD73XX_WDTIMER_BASE              PHYS_TO_K1(0x08610B00)      /* WDTIMER Module */
7658 +#define TNETD73XX_TIMER0_BASE               PHYS_TO_K1(0x08610C00)      /* TIMER0 Module */
7659 +#define TNETD73XX_TIMER1_BASE               PHYS_TO_K1(0x08610D00)      /* TIMER1 Module */
7660 +#define TNETD73XX_UARTA_BASE                PHYS_TO_K1(0x08610E00)      /* UART A */
7661 +#define TNETD73XX_UARTB_BASE                PHYS_TO_K1(0x08610F00)      /* UART B */
7662 +#define TNETD73XX_I2C_BASE                  PHYS_TO_K1(0x08611000)      /* I2C Module */
7663 +#define TNETD73XX_USB_DMA_BASE              PHYS_TO_K1(0x08611200)      /* USB Module */
7664 +#define TNETD73XX_MCDMA_BASE                PHYS_TO_K1(0x08611400)      /* MC-DMA */
7665 +#define TNETD73xx_VDMAVT_BASE               PHYS_TO_K1(0x08611500)      /* VDMAVT Control */
7666 +#define TNETD73XX_RST_CTRL_BASE             PHYS_TO_K1(0x08611600)      /* Reset Control */
7667 +#define TNETD73xx_BIST_CTRL_BASE            PHYS_TO_K1(0x08611700)      /* BIST Control */
7668 +#define TNETD73xx_VLYNQ0_CTRL_BASE          PHYS_TO_K1(0x08611800)      /* VLYNQ0 Control */
7669 +#define TNETD73XX_DCL_BASE                  PHYS_TO_K1(0x08611A00)      /* Device Configuration Latch */
7670 +#define TNETD73xx_VLYNQ1_CTRL_BASE          PHYS_TO_K1(0x08611C00)      /* VLYNQ1 Control */
7671 +#define TNETD73xx_MDIO_BASE                 PHYS_TO_K1(0x08611E00)      /* MDIO Control */
7672 +#define TNETD73XX_FSER_BASE                 PHYS_TO_K1(0x08612000)      /* FSER Control */
7673 +#define TNETD73XX_INTC_BASE                 PHYS_TO_K1(0x08612400)      /* Interrupt Controller */
7674 +#define TNETD73xx_EMAC1_BASE                PHYS_TO_K1(0x08612800)      /* EMAC1 Module*/
7675 +#define TNETD73XX_VLYNQ1_BASE               PHYS_TO_K1(0x0C000000)      /* VLYNQ1 Module */
7676 +
7677 +/* BBIF Registers */
7678 +#define TNETD73XX_BBIF_ADSLADR              (TNETD73XX_BBIF_CTRL_BASE + 0x0)
7679 +
7680 +/* Device Configuration Latch Registers */
7681 +#define TNETD73XX_DCL_BOOTCR                (TNETD73XX_DCL_BASE + 0x0)
7682 +#define TNETD73XX_DCL_DPLLSELR              (TNETD73XX_DCL_BASE + 0x10)
7683 +#define TNETD73XX_DCL_SPEEDCTLR             (TNETD73XX_DCL_BASE + 0x14)
7684 +#define TNETD73XX_DCL_SPEEDPWDR             (TNETD73XX_DCL_BASE + 0x18)
7685 +#define TNETD73XX_DCL_SPEEDCAPR             (TNETD73XX_DCL_BASE + 0x1C)
7686 +
7687 +/* GPIO Control */
7688 +#define TNETD73XX_GPIODINR                  (TNETD73XX_GPIO_BASE + 0x0)
7689 +#define TNETD73XX_GPIODOUTR                 (TNETD73XX_GPIO_BASE + 0x4)
7690 +#define TNETD73XX_GPIOPDIRR                 (TNETD73XX_GPIO_BASE + 0x8)
7691 +#define TNETD73XX_GPIOENR                   (TNETD73XX_GPIO_BASE + 0xC)
7692 +#define TNETD73XX_CVR                       (TNETD73XX_GPIO_BASE + 0x14)
7693 +#define TNETD73XX_DIDR1                     (TNETD73XX_GPIO_BASE + 0x18)
7694 +#define TNETD73XX_DIDR2                     (TNETD73XX_GPIO_BASE + 0x1C)
7695 +
7696 +/* Reset Control  */
7697 +#define TNETD73XX_RST_CTRL_PRCR             (TNETD73XX_RST_CTRL_BASE + 0x0)
7698 +#define TNETD73XX_RST_CTRL_SWRCR            (TNETD73XX_RST_CTRL_BASE + 0x4)
7699 +#define TNETD73XX_RST_CTRL_RSR              (TNETD73XX_RST_CTRL_BASE + 0x8)
7700 +
7701 +/* Power Control  */
7702 +#define TNETD73XX_POWER_CTRL_PDCR           (TNETD73XX_CLOCK_CTRL_BASE + 0x0)
7703 +#define TNETD73XX_POWER_CTRL_PCLKCR         (TNETD73XX_CLOCK_CTRL_BASE + 0x4)
7704 +#define TNETD73XX_POWER_CTRL_PDUCR          (TNETD73XX_CLOCK_CTRL_BASE + 0x8)
7705 +#define TNETD73XX_POWER_CTRL_WKCR           (TNETD73XX_CLOCK_CTRL_BASE + 0xC)
7706 +
7707 +/* Clock Control */
7708 +#define TNETD73XX_CLK_CTRL_SCLKCR           (TNETD73XX_CLOCK_CTRL_BASE + 0x20)
7709 +#define TNETD73XX_CLK_CTRL_SCLKPLLCR        (TNETD73XX_CLOCK_CTRL_BASE + 0x30)
7710 +#define TNETD73XX_CLK_CTRL_MCLKCR           (TNETD73XX_CLOCK_CTRL_BASE + 0x40)
7711 +#define TNETD73XX_CLK_CTRL_MCLKPLLCR        (TNETD73XX_CLOCK_CTRL_BASE + 0x50)
7712 +#define TNETD73XX_CLK_CTRL_UCLKCR           (TNETD73XX_CLOCK_CTRL_BASE + 0x60)
7713 +#define TNETD73XX_CLK_CTRL_UCLKPLLCR        (TNETD73XX_CLOCK_CTRL_BASE + 0x70)
7714 +#define TNETD73XX_CLK_CTRL_ACLKCR0          (TNETD73XX_CLOCK_CTRL_BASE + 0x80)
7715 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR0       (TNETD73XX_CLOCK_CTRL_BASE + 0x90)
7716 +#define TNETD73XX_CLK_CTRL_ACLKCR1          (TNETD73XX_CLOCK_CTRL_BASE + 0xA0)
7717 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR1       (TNETD73XX_CLOCK_CTRL_BASE + 0xB0)
7718 +
7719 +/* EMIF control */
7720 +#define TNETD73XX_EMIF_SDRAM_CFG              ( TNETD73XX_EMIF_BASE + 0x08 )
7721 +
7722 +/* UART */
7723 +#ifdef AR7SEAD2
7724 +#define TNETD73XX_UART_FREQ                 3686400
7725 +#else
7726 +#define TNETD73XX_UART_FREQ                 TNETD73XX_VBUS_FREQ
7727 +#endif
7728 +
7729 +/* Interrupt Controller */
7730 +
7731 +/* Primary interrupts */
7732 +#define TNETD73XX_INTC_UNIFIED_SECONDARY    0   /* Unified secondary interrupt */
7733 +#define TNETD73XX_INTC_EXTERNAL0            1   /* External Interrupt Line 0 */
7734 +#define TNETD73XX_INTC_EXTERNAL1            2   /* External Interrupt Line 1 */
7735 +#define TNETD73XX_INTC_RESERVED3            3   /* Reserved */
7736 +#define TNETD73XX_INTC_RESERVED4            4   /* Reserved */
7737 +#define TNETD73XX_INTC_TIMER0               5   /* TIMER 0 int */
7738 +#define TNETD73XX_INTC_TIMER1               6   /* TIMER 1 int */
7739 +#define TNETD73XX_INTC_UART0                7   /* UART 0 int */
7740 +#define TNETD73XX_INTC_UART1                8   /* UART 1 int */
7741 +#define TNETD73XX_INTC_MCDMA0               9   /* MCDMA 0 int */
7742 +#define TNETD73XX_INTC_MCDMA1               10  /* MCDMA 1 int */
7743 +#define TNETD73XX_INTC_RESERVED11           11  /* Reserved */
7744 +#define TNETD73XX_INTC_RESERVED12           12  /* Reserved */
7745 +#define TNETD73XX_INTC_RESERVED13           13  /* Reserved */
7746 +#define TNETD73XX_INTC_RESERVED14           14  /* Reserved */
7747 +#define TNETD73XX_INTC_ATMSAR               15  /* ATM SAR int */
7748 +#define TNETD73XX_INTC_RESERVED16           16  /* Reserved */
7749 +#define TNETD73XX_INTC_RESERVED17           17  /* Reserved */
7750 +#define TNETD73XX_INTC_RESERVED18           18  /* Reserved */
7751 +#define TNETD73XX_INTC_EMAC0                19  /* EMAC 0 int */
7752 +#define TNETD73XX_INTC_RESERVED20           20  /* Reserved */
7753 +#define TNETD73XX_INTC_VLYNQ0               21  /* VLYNQ 0 int */
7754 +#define TNETD73XX_INTC_CODEC                22  /* CODEC int */
7755 +#define TNETD73XX_INTC_RESERVED23           23  /* Reserved */
7756 +#define TNETD73XX_INTC_USBSLAVE             24  /* USB Slave int */
7757 +#define TNETD73XX_INTC_VLYNQ1               25  /* VLYNQ 1 int */
7758 +#define TNETD73XX_INTC_RESERVED26           26  /* Reserved */
7759 +#define TNETD73XX_INTC_RESERVED27           27  /* Reserved */
7760 +#define TNETD73XX_INTC_ETH_PHY              28  /* Ethernet PHY   */
7761 +#define TNETD73XX_INTC_I2C                  29  /* I2C int */
7762 +#define TNETD73XX_INTC_MCDMA2               30  /* MCDMA 2 int */
7763 +#define TNETD73XX_INTC_MCDMA3               31  /* MCDMA 3 int */
7764 +#define TNETD73XX_INTC_RESERVED32           32  /* Reserved */
7765 +#define TNETD73XX_INTC_EMAC1                33  /* EMAC 1 int */
7766 +#define TNETD73XX_INTC_RESERVED34           34  /* Reserved */
7767 +#define TNETD73XX_INTC_RESERVED35           35  /* Reserved */
7768 +#define TNETD73XX_INTC_RESERVED36           36  /* Reserved */
7769 +#define TNETD73XX_INTC_VDMAVTRX             37  /* VDMAVTRX */
7770 +#define TNETD73XX_INTC_VDMAVTTX             38  /* VDMAVTTX */
7771 +#define TNETD73XX_INTC_ADSLSS               39  /* ADSLSS */
7772 +
7773 +/* Secondary interrupts */
7774 +#define TNETD73XX_INTC_SEC0                 40  /* Secondary */
7775 +#define TNETD73XX_INTC_SEC1                 41  /* Secondary */
7776 +#define TNETD73XX_INTC_SEC2                 42  /* Secondary */
7777 +#define TNETD73XX_INTC_SEC3                 43  /* Secondary */
7778 +#define TNETD73XX_INTC_SEC4                 44  /* Secondary */
7779 +#define TNETD73XX_INTC_SEC5                 45  /* Secondary */
7780 +#define TNETD73XX_INTC_SEC6                 46  /* Secondary */
7781 +#define TNETD73XX_INTC_EMIF                 47  /* EMIF */
7782 +#define TNETD73XX_INTC_SEC8                 48  /* Secondary */
7783 +#define TNETD73XX_INTC_SEC9                 49  /* Secondary */
7784 +#define TNETD73XX_INTC_SEC10                50  /* Secondary */
7785 +#define TNETD73XX_INTC_SEC11                51  /* Secondary */
7786 +#define TNETD73XX_INTC_SEC12                52  /* Secondary */
7787 +#define TNETD73XX_INTC_SEC13                53  /* Secondary */
7788 +#define TNETD73XX_INTC_SEC14                54  /* Secondary */
7789 +#define TNETD73XX_INTC_SEC15                55  /* Secondary */
7790 +#define TNETD73XX_INTC_SEC16                56  /* Secondary */
7791 +#define TNETD73XX_INTC_SEC17                57  /* Secondary */
7792 +#define TNETD73XX_INTC_SEC18                58  /* Secondary */
7793 +#define TNETD73XX_INTC_SEC19                59  /* Secondary */
7794 +#define TNETD73XX_INTC_SEC20                60  /* Secondary */
7795 +#define TNETD73XX_INTC_SEC21                61  /* Secondary */
7796 +#define TNETD73XX_INTC_SEC22                62  /* Secondary */
7797 +#define TNETD73XX_INTC_SEC23                63  /* Secondary */
7798 +#define TNETD73XX_INTC_SEC24                64  /* Secondary */
7799 +#define TNETD73XX_INTC_SEC25                65  /* Secondary */
7800 +#define TNETD73XX_INTC_SEC26                66  /* Secondary */
7801 +#define TNETD73XX_INTC_SEC27                67  /* Secondary */
7802 +#define TNETD73XX_INTC_SEC28                68  /* Secondary */
7803 +#define TNETD73XX_INTC_SEC29                69  /* Secondary */
7804 +#define TNETD73XX_INTC_SEC30                70  /* Secondary */
7805 +#define TNETD73XX_INTC_SEC31                71  /* Secondary */
7806 +
7807 +/* These ugly macros are to access the -1 registers, like config1 */
7808 +#define MFC0_SEL1_OPCODE(dst, src)\
7809 +        .word (0x40000000 | ((dst)<<16) | ((src)<<11) | 1);\
7810 +        nop; \
7811 +        nop; \
7812 +        nop
7813 +
7814 +#define MTC0_SEL1_OPCODE(dst, src)\
7815 +        .word (0x40800000 | ((dst)<<16) | ((src)<<11) | 1);\
7816 +        nop; \
7817 +        nop; \
7818 +        nop
7819 +
7820 +
7821 +/* Below are Jade core specific */
7822 +#define CFG0_4K_IL_MASK         0x00380000
7823 +#define CFG0_4K_IL_SHIFT        19
7824 +#define CFG0_4K_IA_MASK         0x00070000
7825 +#define CFG0_4K_IA_SHIFT        16
7826 +#define CFG0_4K_IS_MASK         0x01c00000
7827 +#define CFG0_4K_IS_SHIFT        22
7828 +
7829 +#define CFG0_4K_DL_MASK         0x00001c00
7830 +#define CFG0_4K_DL_SHIFT        10
7831 +#define CFG0_4K_DA_MASK         0x00000380
7832 +#define CFG0_4K_DA_SHIFT        7
7833 +#define CFG0_4K_DS_MASK         0x0000E000
7834 +#define CFG0_4K_DS_SHIFT        13
7835 +
7836 +
7837 +
7838 +#endif /* __TNETD73XX_H_ */
7839 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_err.h linux.dev/include/asm-mips/ar7/tnetd73xx_err.h
7840 --- linux.old/include/asm-mips/ar7/tnetd73xx_err.h      1970-01-01 01:00:00.000000000 +0100
7841 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h      2005-11-10 01:10:46.075589000 +0100
7842 @@ -0,0 +1,42 @@
7843 +/******************************************************************************
7844 + * FILE PURPOSE:    TNETD73xx Error Definations Header File
7845 + ******************************************************************************
7846 + * FILE NAME:       tnetd73xx_err.h
7847 + *
7848 + * DESCRIPTION:     Error definations for TNETD73XX
7849 + *
7850 + * REVISION HISTORY:
7851 + * 27 Nov 02 - PSP TII
7852 + *
7853 + * (C) Copyright 2002, Texas Instruments, Inc
7854 + *******************************************************************************/
7855 +
7856 +
7857 +#ifndef __TNETD73XX_ERR_H__
7858 +#define __TNETD73XX_ERR_H__
7859 +
7860 +typedef enum TNETD73XX_ERR_t
7861 +{
7862 +    TNETD73XX_ERR_OK        = 0,    /* OK or SUCCESS */
7863 +    TNETD73XX_ERR_ERROR     = -1,   /* Unspecified/Generic ERROR */
7864 +
7865 +    /* Pointers and args */
7866 +    TNETD73XX_ERR_INVARG        = -2,   /* Invaild argument to the call */
7867 +    TNETD73XX_ERR_NULLPTR       = -3,   /* NULL pointer */
7868 +    TNETD73XX_ERR_BADPTR        = -4,   /* Bad (out of mem) pointer */
7869 +
7870 +    /* Memory issues */
7871 +    TNETD73XX_ERR_ALLOC_FAIL    = -10,  /* allocation failed */
7872 +    TNETD73XX_ERR_FREE_FAIL     = -11,  /* free failed */
7873 +    TNETD73XX_ERR_MEM_CORRUPT   = -12,  /* corrupted memory */
7874 +    TNETD73XX_ERR_BUF_LINK      = -13,  /* buffer linking failed */
7875 +
7876 +    /* Device issues */
7877 +    TNETD73XX_ERR_DEVICE_TIMEOUT    = -20,  /* device timeout on read/write */
7878 +    TNETD73XX_ERR_DEVICE_MALFUNC    = -21,  /* device malfunction */
7879 +
7880 +    TNETD73XX_ERR_INVID     = -30   /* Invalid ID */
7881 +
7882 +} TNETD73XX_ERR;
7883 +
7884 +#endif /* __TNETD73XX_ERR_H__ */
7885 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_misc.h linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h
7886 --- linux.old/include/asm-mips/ar7/tnetd73xx_misc.h     1970-01-01 01:00:00.000000000 +0100
7887 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h     2005-11-10 01:10:46.075589000 +0100
7888 @@ -0,0 +1,239 @@
7889 +/******************************************************************************
7890 + * FILE PURPOSE:    TNETD73xx Misc modules API Header
7891 + ******************************************************************************
7892 + * FILE NAME:       tnetd73xx_misc.h
7893 + *
7894 + * DESCRIPTION:     Clock Control, Reset Control, Power Management, GPIO
7895 + *                  FSER Modules API
7896 + *                  As per TNETD73xx specifications
7897 + *
7898 + * REVISION HISTORY:
7899 + * 27 Nov 02 - Sharath Kumar     PSP TII
7900 + * 14 Feb 03 - Anant Gole        PSP TII
7901 + *
7902 + * (C) Copyright 2002, Texas Instruments, Inc
7903 + *******************************************************************************/
7904 +
7905 +#ifndef __TNETD73XX_MISC_H__
7906 +#define __TNETD73XX_MISC_H__
7907 +
7908 +/*****************************************************************************
7909 + * Reset Control Module
7910 + *****************************************************************************/
7911 +
7912 +typedef enum TNETD73XX_RESET_MODULE_tag
7913 +{
7914 +    RESET_MODULE_UART0      = 0,
7915 +    RESET_MODULE_UART1      = 1,
7916 +    RESET_MODULE_I2C        = 2,
7917 +    RESET_MODULE_TIMER0     = 3,
7918 +    RESET_MODULE_TIMER1     = 4,
7919 +    RESET_MODULE_GPIO       = 6,
7920 +    RESET_MODULE_ADSLSS     = 7,
7921 +    RESET_MODULE_USBS       = 8,
7922 +    RESET_MODULE_SAR        = 9,
7923 +    RESET_MODULE_VDMA_VT    = 11,
7924 +    RESET_MODULE_FSER       = 12,
7925 +    RESET_MODULE_VLYNQ1     = 16,
7926 +    RESET_MODULE_EMAC0      = 17,
7927 +    RESET_MODULE_DMA        = 18,
7928 +    RESET_MODULE_BIST       = 19,
7929 +    RESET_MODULE_VLYNQ0     = 20,
7930 +    RESET_MODULE_EMAC1      = 21,
7931 +    RESET_MODULE_MDIO       = 22,
7932 +    RESET_MODULE_ADSLSS_DSP = 23,
7933 +    RESET_MODULE_EPHY       = 26
7934 +} TNETD73XX_RESET_MODULE_T;
7935 +
7936 +typedef enum TNETD73XX_RESET_CTRL_tag
7937 +{
7938 +    IN_RESET        = 0,
7939 +    OUT_OF_RESET
7940 +} TNETD73XX_RESET_CTRL_T;
7941 +
7942 +typedef enum TNETD73XX_SYS_RST_MODE_tag
7943 +{
7944 +    RESET_SOC_WITH_MEMCTRL      = 1,    /* SW0 bit in SWRCR register */
7945 +    RESET_SOC_WITHOUT_MEMCTRL   = 2     /* SW1 bit in SWRCR register */
7946 +} TNETD73XX_SYS_RST_MODE_T;
7947 +
7948 +typedef enum TNETD73XX_SYS_RESET_STATUS_tag
7949 +{
7950 +    HARDWARE_RESET = 0,
7951 +    SOFTWARE_RESET0,            /* Caused by writing 1 to SW0 bit in SWRCR register */
7952 +    WATCHDOG_RESET,
7953 +    SOFTWARE_RESET1             /* Caused by writing 1 to SW1 bit in SWRCR register */
7954 +} TNETD73XX_SYS_RESET_STATUS_T;
7955 +
7956 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module,
7957 +                                TNETD73XX_RESET_CTRL_T reset_ctrl);
7958 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status(TNETD73XX_RESET_MODULE_T reset_module);
7959 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode);
7960 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status(void);
7961 +
7962 +/*****************************************************************************
7963 + * Power Control Module
7964 + *****************************************************************************/
7965 +
7966 +typedef enum TNETD73XX_POWER_MODULE_tag
7967 +{
7968 +    POWER_MODULE_USBSP      = 0,
7969 +    POWER_MODULE_WDTP       = 1,
7970 +    POWER_MODULE_UT0P       = 2,
7971 +    POWER_MODULE_UT1P       = 3,
7972 +    POWER_MODULE_IICP       = 4,
7973 +    POWER_MODULE_VDMAP      = 5,
7974 +    POWER_MODULE_GPIOP      = 6,
7975 +    POWER_MODULE_VLYNQ1P    = 7,
7976 +    POWER_MODULE_SARP       = 8,
7977 +    POWER_MODULE_ADSLP      = 9,
7978 +    POWER_MODULE_EMIFP      = 10,
7979 +    POWER_MODULE_ADSPP      = 12,
7980 +    POWER_MODULE_RAMP       = 13,
7981 +    POWER_MODULE_ROMP       = 14,
7982 +    POWER_MODULE_DMAP       = 15,
7983 +    POWER_MODULE_BISTP      = 16,
7984 +    POWER_MODULE_TIMER0P    = 18,
7985 +    POWER_MODULE_TIMER1P    = 19,
7986 +    POWER_MODULE_EMAC0P     = 20,
7987 +    POWER_MODULE_EMAC1P     = 22,
7988 +    POWER_MODULE_EPHYP      = 24,
7989 +    POWER_MODULE_VLYNQ0P    = 27,
7990 +} TNETD73XX_POWER_MODULE_T;
7991 +
7992 +typedef enum TNETD73XX_POWER_CTRL_tag
7993 +{
7994 +    POWER_CTRL_POWER_UP = 0,
7995 +    POWER_CTRL_POWER_DOWN
7996 +} TNETD73XX_POWER_CTRL_T;
7997 +
7998 +typedef enum TNETD73XX_SYS_POWER_MODE_tag
7999 +{
8000 +    GLOBAL_POWER_MODE_RUN       = 0,    /* All system is up */
8001 +    GLOBAL_POWER_MODE_IDLE,             /* MIPS is power down, all peripherals working */
8002 +    GLOBAL_POWER_MODE_STANDBY,          /* Chip in power down, but clock to ADSKL subsystem is running */
8003 +    GLOBAL_POWER_MODE_POWER_DOWN        /* Total chip is powered down */
8004 +} TNETD73XX_SYS_POWER_MODE_T;
8005 +
8006 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module,  TNETD73XX_POWER_CTRL_T power_ctrl);
8007 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module);
8008 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode);
8009 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode(void);
8010 +
8011 +/*****************************************************************************
8012 + * Wakeup Control
8013 + *****************************************************************************/
8014 +
8015 +typedef enum TNETD73XX_WAKEUP_INTERRUPT_tag
8016 +{
8017 +    WAKEUP_INT0 = 1,
8018 +    WAKEUP_INT1 = 2,
8019 +    WAKEUP_INT2 = 4,
8020 +    WAKEUP_INT3 = 8
8021 +} TNETD73XX_WAKEUP_INTERRUPT_T;
8022 +
8023 +typedef enum TNETD73XX_WAKEUP_CTRL_tag
8024 +{
8025 +    WAKEUP_DISABLED = 0,
8026 +    WAKEUP_ENABLED
8027 +} TNETD73XX_WAKEUP_CTRL_T;
8028 +
8029 +typedef enum TNETD73XX_WAKEUP_POLARITY_tag
8030 +{
8031 +    WAKEUP_ACTIVE_HIGH = 0,
8032 +    WAKEUP_ACTIVE_LOW
8033 +} TNETD73XX_WAKEUP_POLARITY_T;
8034 +
8035 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
8036 +                           TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
8037 +                           TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity);
8038 +
8039 +/*****************************************************************************
8040 + * FSER  Control
8041 + *****************************************************************************/
8042 +
8043 +typedef enum TNETD73XX_FSER_MODE_tag
8044 +{
8045 +    FSER_I2C    = 0,
8046 +    FSER_UART   = 1
8047 +} TNETD73XX_FSER_MODE_T;
8048 +
8049 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode);
8050 +
8051 +/*****************************************************************************
8052 + * Clock Control
8053 + *****************************************************************************/
8054 +
8055 +#define CLK_MHZ(x)    ( (x) * 1000000 )
8056 +
8057 +typedef enum TNETD73XX_CLKC_ID_tag
8058 +{
8059 +    CLKC_SYS = 0,
8060 +    CLKC_MIPS,
8061 +    CLKC_USB,
8062 +    CLKC_ADSLSS
8063 +} TNETD73XX_CLKC_ID_T;
8064 +
8065 +void tnetd73xx_clkc_init(__u32 afeclk, __u32 refclk, __u32 xtal3in);
8066 +TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, __u32 output_freq);
8067 +__u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
8068 +
8069 +/*****************************************************************************
8070 + * GPIO Control
8071 + *****************************************************************************/
8072 +
8073 +typedef enum TNETD73XX_GPIO_PIN_tag
8074 +{
8075 +    GPIO_UART0_RD           = 0,
8076 +    GPIO_UART0_TD           = 1,
8077 +    GPIO_UART0_RTS          = 2,
8078 +    GPIO_UART0_CTS          = 3,
8079 +    GPIO_FSER_CLK           = 4,
8080 +    GPIO_FSER_D             = 5,
8081 +    GPIO_EXT_AFE_SCLK       = 6,
8082 +    GPIO_EXT_AFE_TX_FS      = 7,
8083 +    GPIO_EXT_AFE_TXD        = 8,
8084 +    GPIO_EXT_AFE_RS_FS      = 9,
8085 +    GPIO_EXT_AFE_RXD1       = 10,
8086 +    GPIO_EXT_AFE_RXD0       = 11,
8087 +    GPIO_EXT_AFE_CDIN       = 12,
8088 +    GPIO_EXT_AFE_CDOUT      = 13,
8089 +    GPIO_EPHY_SPEED100      = 14,
8090 +    GPIO_EPHY_LINKON        = 15,
8091 +    GPIO_EPHY_ACTIVITY      = 16,
8092 +    GPIO_EPHY_FDUPLEX       = 17,
8093 +    GPIO_EINT0              = 18,
8094 +    GPIO_EINT1              = 19,
8095 +    GPIO_MBSP0_TCLK         = 20,
8096 +    GPIO_MBSP0_RCLK         = 21,
8097 +    GPIO_MBSP0_RD           = 22,
8098 +    GPIO_MBSP0_TD           = 23,
8099 +    GPIO_MBSP0_RFS          = 24,
8100 +    GPIO_MBSP0_TFS          = 25,
8101 +    GPIO_MII_DIO            = 26,
8102 +    GPIO_MII_DCLK           = 27,
8103 +} TNETD73XX_GPIO_PIN_T;
8104 +
8105 +typedef enum TNETD73XX_GPIO_PIN_MODE_tag
8106 +{
8107 +    FUNCTIONAL_PIN = 0,
8108 +    GPIO_PIN = 1
8109 +} TNETD73XX_GPIO_PIN_MODE_T;
8110 +
8111 +typedef enum TNETD73XX_GPIO_PIN_DIRECTION_tag
8112 +{
8113 +    GPIO_OUTPUT_PIN = 0,
8114 +    GPIO_INPUT_PIN = 1
8115 +} TNETD73XX_GPIO_PIN_DIRECTION_T;
8116 +
8117 +void tnetd73xx_gpio_init(void);
8118 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
8119 +                         TNETD73XX_GPIO_PIN_MODE_T pin_mode,
8120 +                         TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction);
8121 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value);
8122 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
8123 +
8124 +/* TNETD73XX Revision */
8125 +__u32 tnetd73xx_get_revision(void);
8126 +
8127 +#endif /* __TNETD73XX_MISC_H__ */
8128 diff -urN linux.old/include/asm-mips/ar7/vlynq.h linux.dev/include/asm-mips/ar7/vlynq.h
8129 --- linux.old/include/asm-mips/ar7/vlynq.h      1970-01-01 01:00:00.000000000 +0100
8130 +++ linux.dev/include/asm-mips/ar7/vlynq.h      2005-11-10 01:10:46.095590250 +0100
8131 @@ -0,0 +1,610 @@
8132 +/***************************************************************************
8133 +**+----------------------------------------------------------------------+**
8134 +**|                                ****                                  |**
8135 +**|                                ****                                  |**
8136 +**|                                ******o***                            |**
8137 +**|                          ********_///_****                           |**
8138 +**|                           ***** /_//_/ ****                          |**
8139 +**|                            ** ** (__/ ****                           |**
8140 +**|                                *********                             |**
8141 +**|                                 ****                                 |**
8142 +**|                                  ***                                 |**
8143 +**|                                                                      |**
8144 +**|     Copyright (c) 2003 Texas Instruments Incorporated                |**
8145 +**|                        ALL RIGHTS RESERVED                           |**
8146 +**|                                                                      |**
8147 +**| Permission is hereby granted to licensees of Texas Instruments       |**
8148 +**| Incorporated (TI) products to use this computer program for the sole |**
8149 +**| purpose of implementing a licensee product based on TI products.     |**
8150 +**| No other rights to reproduce, use, or disseminate this computer      |**
8151 +**| program, whether in part or in whole, are granted.                   |**
8152 +**|                                                                      |**
8153 +**| TI makes no representation or warranties with respect to the         |**
8154 +**| performance of this computer program, and specifically disclaims     |**
8155 +**| any responsibility for any damages, special or consequential,        |**
8156 +**| connected with the use of this program.                              |**
8157 +**|                                                                      |**
8158 +**+----------------------------------------------------------------------+**
8159 +***************************************************************************/
8160 +
8161 +/*********************************************************************************
8162 + *  ------------------------------------------------------------------------------
8163 + *   Module      : vlynq_hal.h
8164 + *   Description :
8165 + *   This header file provides the set of functions exported by the
8166 + *   VLYNQ HAL. This file is included from the SOC specific VLYNQ driver wrapper.
8167 + *  ------------------------------------------------------------------------------
8168 + *********************************************************************************/
8169 +
8170 +#ifndef _VLYNQ_HAL_H_
8171 +#define _VLYNQ_HAL_H_
8172 +
8173 +/* Enable/Disable debug feature */
8174 +#undef VLYNQ_DEBUG
8175 +
8176 +#ifdef VLYNQ_DEBUG  /* This needs to be OS abstracted - for testing use vxworks/linux calls */
8177 +#define debugPrint(format,args...)
8178 +#else
8179 +#define debugPrint(format,args...)
8180 +#endif
8181 +
8182 + /* number of VLYNQ memory regions supported */
8183 +#define VLYNQ_MAX_MEMORY_REGIONS 0x04
8184 +
8185 + /* Max.number of external interrupt inputs supported by VLYNQ module */
8186 +#define VLYNQ_IVR_MAXIVR         0x08
8187 +
8188 +#define VLYNQ_CLK_DIV_MAX  0x08
8189 +#define VLYNQ_CLK_DIV_MIN  0x01
8190 +
8191 +
8192 +/*** the total number of entries allocated for ICB would be
8193 + * 32(for 32 bits in IntPending register) + VLYNQ_IVR_CHAIN_SLOTS*/
8194 +#define VLYNQ_IVR_CHAIN_SLOTS 10
8195 +
8196 +
8197 +/* Error defines */
8198 +#define VLYNQ_SUCCESS               0
8199 +
8200 +#define VLYNQ_ERRCODE_BASE          0 /* Chosen by system */
8201 +#define VLYNQ_INVALID_ARG          -(VLYNQ_ERRCODE_BASE+1)
8202 +#define VLYNQ_INVALID_DRV_STATE    -(VLYNQ_ERRCODE_BASE+2)
8203 +#define VLYNQ_INT_CONFIG_ERR       -(VLYNQ_ERRCODE_BASE+3)
8204 +#define VLYNQ_LINK_DOWN            -(VLYNQ_ERRCODE_BASE+4)
8205 +#define VLYNQ_MEMALLOC_FAIL        -(VLYNQ_ERRCODE_BASE+5)
8206 +#define VLYNQ_ISR_NON_EXISTENT     -(VLYNQ_ERRCODE_BASE+6)
8207 +#define VLYNQ_INTVEC_MAP_NOT_FOUND -(VLYNQ_ERRCODE_BASE+7)
8208 +
8209 +/* Vlynq Defines and Macros */
8210 +
8211 +#define VLYNQ_NUM_INT_BITS              32 /* 32 bit interrupt staus register */
8212 +
8213 +/* Base address of module */
8214 +#define VLYNQ_BASE                      (pdev->module_base)
8215 +
8216 +#define VLYNQ_REMOTE_REGS_OFFSET        0x0080
8217 +
8218 +#define VLYNQ_REV_OFFSET                0x0000
8219 +#define VLYNQ_CTRL_OFFSET               0x0004
8220 +#define VLYNQ_STATUS_OFFSET             0x0008
8221 +#define VLYNQ_INT_STAT_OFFSET           0x0010
8222 +#define VLYNQ_INT_PEND_OFFSET           0x0014
8223 +#define VLYNQ_INT_PTR_OFFSET            0x0018
8224 +#define VLYNQ_TXMAP_OFFSET              0x001c
8225 +
8226 +#define VLYNQ_RX0MAP_SIZE_REG_OFFSET    0x0020
8227 +#define VLYNQ_RX0MAP_OFFSET_REG_OFFSET  0x0024
8228 +
8229 +#define VLYNQ_CHIP_VER_OFFSET           0x0040
8230 +#define VLYNQ_IVR_REGS_OFFSET           0x0060
8231 +
8232 +#define VLYNQ_INT_PENDING_REG_PTR       0x14
8233 +#define VLYNQ_R_INT_PENDING_REG_PTR     VLYNQ_REMOTE_REGS_OFFSET + 0x14
8234 +
8235 +#define VLYNQ_REV_REG       *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_REV_OFFSET))
8236 +#define VLYNQ_CTRL_REG      *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_CTRL_OFFSET))
8237 +#define VLYNQ_STATUS_REG    *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_STATUS_OFFSET))
8238 +#define VLYNQ_INT_STAT_REG  *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_INT_STAT_OFFSET))
8239 +#define VLYNQ_INT_PEND_REG  *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_INT_PEND_OFFSET))
8240 +#define VLYNQ_INT_PTR_REG   *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_INT_PTR_OFFSET))
8241 +#define VLYNQ_TXMAP_REG     *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_TXMAP_OFFSET))
8242 +
8243 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
8244 +#define VLYNQ_RXMAP_SIZE_REG(map) \
8245 +    *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_RX0MAP_SIZE_REG_OFFSET+( (map-1)<<3)))
8246 +
8247 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
8248 +#define VLYNQ_RXMAP_OFFSET_REG(map) \
8249 +    *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_RX0MAP_OFFSET_REG_OFFSET+( (map-1)<<3)))
8250 +
8251 +#define VLYNQ_CHIP_VER_REG  *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_CHIP_VER_OFFSET))
8252 +
8253 +/* 0 =< ivr <= 31; currently ivr < VLYNQ_IVR_MAXIVR=8) */
8254 +#define VLYNQ_IVR_OFFSET(ivr)  \
8255 +    (VLYNQ_BASE + VLYNQ_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3) )
8256 +
8257 +#define VLYNQ_IVR_03TO00_REG  *((volatile unsigned int*) (VLYNQ_IVR_OFFSET(0)) )
8258 +#define VLYNQ_IVR_07TO04_REG  *((volatile unsigned int*) (VLYNQ_IVR_OFFSET(4)) )
8259 +/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
8260 +
8261 +#define VLYNQ_IVR_INTEN(ivr)    (((unsigned int)(0x80)) << ((((unsigned)(ivr)) % 4) * 8))
8262 +#define VLYNQ_IVR_INTTYPE(ivr)  (((unsigned int)(0x40)) << ((((unsigned)(ivr)) % 4) * 8))
8263 +#define VLYNQ_IVR_INTPOL(ivr)   (((unsigned int)(0x20)) << ((((unsigned)(ivr)) % 4) * 8))
8264 +#define VLYNQ_IVR_INTVEC(ivr)   (((unsigned int)(0x1F)) << ((((unsigned)(ivr)) % 4) * 8))
8265 +#define VLYNQ_IVR_INTALL(ivr)   (((unsigned int)(0xFF)) << ((((unsigned)(ivr)) % 4) * 8))
8266 +
8267 +
8268 +
8269 +/*********************************
8270 + * Remote VLYNQ register set     *
8271 + *********************************/
8272 +
8273 +#define VLYNQ_R_REV_OFFSET              0x0080
8274 +#define VLYNQ_R_CTRL_OFFSET             0x0084
8275 +#define VLYNQ_R_STATUS_OFFSET           0x0088
8276 +#define VLYNQ_R_INT_STAT_OFFSET         0x0090
8277 +#define VLYNQ_R_INT_PEND_OFFSET         0x0094
8278 +#define VLYNQ_R_INT_PTR_OFFSET          0x0098
8279 +#define VLYNQ_R_TXMAP_OFFSET            0x009c
8280 +
8281 +#define VLYNQ_R_RX0MAP_SIZE_REG_OFFSET  0x00A0
8282 +#define VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET 0x00A4
8283 +
8284 +#define VLYNQ_R_CHIP_VER_OFFSET         0x00C0
8285 +#define VLYNQ_R_IVR_REGS_OFFSET         0x00E0
8286 +
8287 +#define VLYNQ_R_REV_REG       *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_REV_OFFSET))
8288 +#define VLYNQ_R_CTRL_REG      *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_CTRL_OFFSET))
8289 +#define VLYNQ_R_STATUS_REG    *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_STATUS_OFFSET))
8290 +#define VLYNQ_R_INT_STAT_REG  *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_INT_STAT_OFFSET))
8291 +#define VLYNQ_R_INT_PEND_REG  *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_INT_PEND_OFFSET))
8292 +#define VLYNQ_R_INT_PTR_REG   *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_INT_PTR_OFFSET))
8293 +#define VLYNQ_R_TXMAP_REG     *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_TXMAP_OFFSET))
8294 +
8295 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
8296 +#define VLYNQ_R_RXMAP_SIZE_REG(map) \
8297 +    *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_SIZE_REG_OFFSET + ((map-1)<<3)))
8298 +
8299 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
8300 +#define VLYNQ_R_RXMAP_OFFSET_REG(map) \
8301 +    *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET + ((map-1)<<3)))
8302 +
8303 +#define VLYNQ_R_CHIP_VER_REG  *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_CHIP_VER_OFFSET)
8304 +
8305 +#define VLYNQ_R_IVR_OFFSET(ivr)  \
8306 +    (VLYNQ_BASE + VLYNQ_R_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3))
8307 +
8308 +
8309 +/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
8310 +#define VLYNQ_R_IVR_03TO00_REG  *((volatile unsigned int*) (VLYNQ_R_IVR_OFFSET(0)) )
8311 +#define VLYNQ_R_IVR_07TO04_REG  *((volatile unsigned int*) (VLYNQ_R_IVR_OFFSET(4)) )
8312 +
8313 +
8314 +/****End of remote register set definition******/
8315 +
8316 +
8317 +/*** Masks for individual register fields ***/
8318 +
8319 +#define VLYNQ_MODULE_ID_MASK        0xffff0000
8320 +#define VLYNQ_MAJOR_REV_MASK        0x0000ff00
8321 +#define VLYNQ_MINOR_REV_MASK        0x000000ff
8322 +
8323 +
8324 +#define VLYNQ_CTL_ILOOP_MASK        0x00000002
8325 +#define VLYNQ_CTL_INT2CFG_MASK      0x00000080
8326 +#define VLYNQ_CTL_INTVEC_MASK       0x00001f00
8327 +#define VLYNQ_CTL_INTEN_MASK        0x00002000
8328 +#define VLYNQ_CTL_INTLOCAL_MASK     0x00004000
8329 +#define VLYNQ_CTL_CLKDIR_MASK       0x00008000
8330 +#define VLYNQ_CTL_CLKDIV_MASK       0x00070000
8331 +#define VLYNQ_CTL_MODE_MASK         0x00e00000
8332 +
8333 +
8334 +#define VLYNQ_STS_LINK_MASK         0x00000001  /* Link is active */
8335 +#define VLYNQ_STS_MPEND_MASK        0x00000002  /* Pending master requests */
8336 +#define VLYNQ_STS_SPEND_MASK        0x00000004  /* Pending slave requests */
8337 +#define VLYNQ_STS_NFEMPTY0_MASK     0x00000008  /* Master data FIFO not empty */
8338 +#define VLYNQ_STS_NFEMPTY1_MASK     0x00000010  /* Master command FIFO not empty */
8339 +#define VLYNQ_STS_NFEMPTY2_MASK     0x00000020  /* Slave data FIFO not empty */
8340 +#define VLYNQ_STS_NFEMPTY3_MASK     0x00000040  /* Slave command FIFO not empty */
8341 +#define VLYNQ_STS_LERROR_MASK       0x00000080  /* Local error, w/c */
8342 +#define VLYNQ_STS_RERROR_MASK       0x00000100  /* remote error w/c */
8343 +#define VLYNQ_STS_OFLOW_MASK        0x00000200
8344 +#define VLYNQ_STS_IFLOW_MASK        0x00000400
8345 +#define VLYNQ_STS_MODESUP_MASK      0x00E00000  /* Highest mode supported */
8346 +#define VLYNQ_STS_SWIDTH_MASK       0x07000000  /* Used for reading the width of VLYNQ bus */
8347 +#define VLYNQ_STS_DEBUG_MASK        0xE0000000
8348 +
8349 +#define VLYNQ_CTL_INTVEC_SHIFT      0x08
8350 +#define VLYNQ_CTL_INTEN_SHIFT       0x0D
8351 +#define VLYNQ_CTL_INT2CFG_SHIFT     0x07
8352 +#define VLYNQ_CTL_INTLOCAL_SHIFT    0x0E
8353 +
8354 +#define VLYNQ_CTL_INTFIELDS_CLEAR_MASK  0x7F80
8355 +
8356 +#define VLYNQ_CHIPVER_DEVREV_MASK   0xffff0000
8357 +#define VLYNQ_CHIPVER_DEVID_MASK    0x0000ffff
8358 +
8359 +#define VLYNQ_IVR_INTEN_MASK        0x80
8360 +#define VLYNQ_IVR_INTTYPE_MASK      0x40
8361 +#define VLYNQ_IVR_INTPOL_MASK       0x20
8362 +
8363 +
8364 +/**** Helper macros ****/
8365 +
8366 +#define VLYNQ_RESETCB(arg) \
8367 +   if( pdev->reset_cb != NULL)   \
8368 +   {                             \
8369 +      (pdev->reset_cb)(pdev, (arg));  \
8370 +   }
8371 +
8372 +#define VLYNQ_STATUS_FLD_WIDTH(sts) (((sts) & VLYNQ_STS_SWIDTH_MASK) >> 24 )
8373 +#define VLYNQ_CTL_INTVEC(x)         (((x) & 31) << 8 )
8374 +
8375 +#define VLYNQ_INRANGE(x,hi,lo)      (((x) <= (hi)) && ((x) >= (lo)))
8376 +#define VLYNQ_OUTRANGE(x,hi,lo)     (((x) > (hi)) || ((x) < (lo)))
8377 +
8378 +#define VLYNQ_ALIGN4(x)             (x)=(x)&(~3)
8379 +
8380 +
8381 +/*************************************
8382 + *             Enums                 *
8383 + *************************************/
8384 +
8385 +/* Initialization options define what operations are
8386 + * undertaken during vlynq module initialization */
8387 +typedef enum
8388 +{
8389 +    /* Init host local memory regions.This allows
8390 +     * local host access remote memory regions */
8391 +    VLYNQ_INIT_LOCAL_MEM_REGIONS = 0x01,
8392 +    /* Init host remote memory regions.This allows
8393 +     * remote device access local memory regions */
8394 +    VLYNQ_INIT_REMOTE_MEM_REGIONS =0x02,
8395 +    /* Init local interrupt config*/
8396 +    VLYNQ_INIT_LOCAL_INTERRUPTS   =0x04,
8397 +    /* Init remote interrupt config*/
8398 +    VLYNQ_INIT_REMOTE_INTERRUPTS  =0x08,
8399 +    /* Check link during initialization*/
8400 +    VLYNQ_INIT_CHECK_LINK         =0x10,
8401 +    /* configure clock during init */
8402 +    VLYNQ_INIT_CONFIG_CLOCK       =0x20,
8403 +    /* Clear errors during init */
8404 +    VLYNQ_INIT_CLEAR_ERRORS       =0x40,
8405 +    /* All options */
8406 +    VLYNQ_INIT_PERFORM_ALL        =0x7F
8407 +}VLYNQ_INIT_OPTIONS;
8408 +
8409 +
8410 +/* VLYNQ_DEV_TYPE identifies local or remote device */
8411 +typedef enum
8412 +{
8413 +    VLYNQ_LOCAL_DVC  = 0,           /* vlynq local device (SOC's vlynq module) */
8414 +    VLYNQ_REMOTE_DVC = 1            /* vlynq remote device (remote vlynq module) */
8415 +}VLYNQ_DEV_TYPE;
8416 +
8417 +
8418 +/* VLYNQ_CLK_SOURCE identifies the vlynq module clock source */
8419 +typedef enum
8420 +{
8421 +    VLYNQ_CLK_SOURCE_NONE   = 0,    /* do not initialize clock generator*/
8422 +    VLYNQ_CLK_SOURCE_LOCAL  = 1,    /* clock is generated by local machine  */
8423 +    VLYNQ_CLK_SOURCE_REMOTE = 2     /* clock is generated by remote machine */
8424 +}VLYNQ_CLK_SOURCE;
8425 +
8426 +
8427 +/* VLYNQ_DRV_STATE indicates the current driver state */
8428 +typedef enum
8429 +{
8430 +    VLYNQ_DRV_STATE_UNINIT = 0,     /* driver is uninitialized  */
8431 +    VLYNQ_DRV_STATE_ININIT = 1,     /* VLYNQ is being initialized */
8432 +    VLYNQ_DRV_STATE_RUN    = 2,     /* VLYNQ is running properly  */
8433 +    VLYNQ_DRV_STATE_HOLD   = 3,     /* driver stopped temporarily */
8434 +    VLYNQ_DRV_STATE_ERROR  = 4      /* driver stopped on unrecoverable error */
8435 +}VLYNQ_DRV_STATE;
8436 +
8437 +
8438 +/* VLYNQ_BUS_WIDTH identifies the vlynq module bus width */
8439 +typedef enum
8440 +{
8441 +   VLYNQ_BUS_WIDTH_3 =  3,
8442 +   VLYNQ_BUS_WIDTH_5 =  5,
8443 +   VLYNQ_BUS_WIDTH_7 =  7,
8444 +   VLYNQ_BUS_WIDTH_9 =  9
8445 +}VLYNQ_BUS_WIDTH;
8446 +
8447 +
8448 +/* VLYNQ_LOCAL_INT_CONFIG indicates whether the local vlynq
8449 + * interrupts are processed by the host or passed on to the
8450 + * remote device.
8451 + */
8452 +typedef enum
8453 +{
8454 +    VLYNQ_INT_REMOTE = 0,   /* Interrupt packets sent to remote, intlocal=0 */
8455 +    VLYNQ_INT_LOCAL  = 1    /* Interrupts are handled locally, intlocal=1 */
8456 +}VLYNQ_LOCAL_INT_CONFIG;
8457 +
8458 +
8459 +/* VLYNQ_REMOTE_INT_CONFIG indicates whether the remote
8460 + * interrupts are to be handled by the SOC system ISR
8461 + * or via the vlynq root ISR
8462 + */
8463 +typedef enum
8464 +{
8465 +    VLYNQ_INT_ROOT_ISR   = 0,   /* remote ints handled via vlynq root ISR */
8466 +    VLYNQ_INT_SYSTEM_ISR = 1    /* remote ints handled via system ISR */
8467 +}VLYNQ_REMOTE_INT_CONFIG;
8468 +
8469 +
8470 +/* VLYNQ_INTR_POLARITY - vlynq interrupt polarity setting */
8471 +typedef enum
8472 +{
8473 +    VLYNQ_INTR_ACTIVE_HIGH = 0,
8474 +    VLYNQ_INTR_ACTIVE_LOW  = 1
8475 +}VLYNQ_INTR_POLARITY;
8476 +
8477 +
8478 +/* VLYNQ_INTR_TYPE  - vlynq interrupt type */
8479 +typedef enum
8480 +{
8481 +    VLYNQ_INTR_LEVEL  = 0,
8482 +    VLYNQ_INTR_PULSED = 1
8483 +}VLYNQ_INTR_TYPE;
8484 +
8485 +
8486 +/* VLYNQ_RESET_MODE - vlynq reset mode */
8487 +typedef enum
8488 +{
8489 +   VLYNQ_RESET_ASSERT,      /* hold device in reset state */
8490 +   VLYNQ_RESET_DEASSERT,    /* release device from reset state */
8491 +   VLYNQ_RESET_INITFAIL,    /* handle the device in case driver initialization fails */
8492 +   VLYNQ_RESET_LINKESTABLISH,  /* handle the device in case driver established link */
8493 +   VLYNQ_RESET_INITFAIL2,   /* Driver initialization failed but VLYNQ link exist. */
8494 +   VLYNQ_RESET_INITOK       /* Driver initialization finished OK. */
8495 +}VLYNQ_RESET_MODE;
8496 +
8497 +
8498 +
8499 +/*************************************
8500 + *             Typedefs              *
8501 + *************************************/
8502 +
8503 +struct VLYNQ_DEV_t; /*forward declaration*/
8504 +
8505 +/*--------Function Pointers defintions -----------*/
8506 +
8507 +/* prototype for interrupt handler definition */
8508 +typedef void (*VLYNQ_INTR_CNTRL_ISR)(void *arg1,void *arg2,void *arg3);
8509 +
8510 +typedef void
8511 +(*VLYNQ_RESET_REMOTE)(struct VLYNQ_DEV_t *pDev, VLYNQ_RESET_MODE mode);
8512 +
8513 +typedef void
8514 +(*VLYNQ_REPORT_CB)( struct VLYNQ_DEV_t *pDev,   /* This VLYNQ */
8515 +                    VLYNQ_DEV_TYPE  aSrcDvc,    /* Event Cause -local/remote? */
8516 +                    unsigned int  dwStatRegVal);      /* Value of the relevant status register */
8517 +
8518 +
8519 +/*-------Structure Definitions------------*/
8520 +
8521 +typedef struct VLYNQ_MEMORY_MAP_t
8522 +{
8523 +    unsigned int Txmap;
8524 +    unsigned int RxOffset[VLYNQ_MAX_MEMORY_REGIONS];
8525 +    unsigned int RxSize[VLYNQ_MAX_MEMORY_REGIONS];
8526 +}VLYNQ_MEMORY_MAP;
8527 +
8528 +
8529 +/**VLYNQ_INTERRUPT_CNTRL - defines the vlynq module interrupt
8530 + * settings in vlynq Control register  */
8531 +typedef struct VLYNQ_INTERRUPT_CNTRL_t
8532 +{
8533 +    /* vlynq interrupts handled by host or remote - maps to
8534 +     * intLocal bit in vlynq control register */
8535 +    VLYNQ_LOCAL_INT_CONFIG intLocal;
8536 +
8537 +    /* remote interrupts handled by vlynq isr or host system
8538 +     * interrupt controller - maps to the int2Cfg in vlynq
8539 +     * control register */
8540 +    VLYNQ_REMOTE_INT_CONFIG intRemote;
8541 +
8542 +    /* bit in pending/set register used for module interrupts*/
8543 +    unsigned int map_vector;
8544 +
8545 +    /* used only if remote interrupts are to be handled by system ISR*/
8546 +    unsigned int intr_ptr;
8547 +
8548 +}VLYNQ_INTERRUPT_CNTRL;
8549 +
8550 +
8551 +/* VLYNQ_INTR_CNTRL_ICB - defines the Interrupt control block which hold
8552 + * the interrupt dispatch table. The vlynq_root_isr() indexes into this
8553 + * table to identify the ISR to be invoked
8554 + */
8555 +typedef struct VLYNQ_INTR_CNTRL_ICB_t
8556 +{
8557 +    VLYNQ_INTR_CNTRL_ISR            isr;    /* Clear errors during initialization */
8558 +    void                            *arg1 ; /* Arg 1 for the ISR */
8559 +    void                            *arg2 ; /* Arg 2 for the ISR */
8560 +    void                            *arg3 ; /* Arg 3 for the ISR */
8561 +    unsigned int  isrCount; /* number of ISR invocations so far */
8562 +    struct VLYNQ_INTR_CNTRL_ICB_t   *next;
8563 +}VLYNQ_INTR_CNTRL_ICB;
8564 +
8565 +/* overlay of vlynq register set */
8566 +typedef struct VLYNQ_REG_SET_t
8567 +{
8568 +    unsigned int revision; /*offset : 0x00 */
8569 +    unsigned int control;  /* 0x04*/
8570 +    unsigned int status;   /* 0x08*/
8571 +    unsigned int pad1;     /* 0x0c*/
8572 +    unsigned int intStatus;   /*0x10*/
8573 +    unsigned int intPending;  /*0x14*/
8574 +    unsigned int intPtr;      /*0x18*/
8575 +    unsigned int txMap;       /*0x1C*/
8576 +    unsigned int rxSize1;     /*0x20*/
8577 +    unsigned int rxOffset1;   /*0x24*/
8578 +    unsigned int rxSize2;     /*0x28*/
8579 +    unsigned int rxOffset2;   /*0x2C*/
8580 +    unsigned int rxSize3;     /*0x30*/
8581 +    unsigned int rxOffset3;   /*0x34*/
8582 +    unsigned int rxSize4;     /*0x38*/
8583 +    unsigned int rxOffset4;   /*0x3C*/
8584 +    unsigned int chipVersion; /*0x40*/
8585 +    unsigned int pad2[8];
8586 +    unsigned int ivr30;       /*0x60*/
8587 +    unsigned int ivr74;       /*0x64*/
8588 +    unsigned int pad3[7];
8589 +}VLYNQ_REG_SET;
8590 +
8591 +
8592 +typedef struct VLYNQ_DEV_t
8593 +{
8594 +    /** module index:1,2,3... used for debugging purposes */
8595 +    unsigned int dev_idx;
8596 +
8597 +    /*VLYNQ module base address */
8598 +    unsigned int module_base;
8599 +
8600 +    /* clock source selection */
8601 +    VLYNQ_CLK_SOURCE clk_source;
8602 +
8603 +    /* Clock Divider.Val=1 to 8. VLYNQ_clk = VBUSCLK/clk_div */
8604 +    unsigned int  clk_div;
8605 +
8606 +    /* State of the VLYNQ driver, set to VLYNQ_DRV_STATE_UNINIT, when initializing */
8607 +    VLYNQ_DRV_STATE state;
8608 +
8609 +    /* Valid VLYNQ bus width, filled by driver  */
8610 +    VLYNQ_BUS_WIDTH width;
8611 +
8612 +    /* local memory mapping   */
8613 +    VLYNQ_MEMORY_MAP local_mem;
8614 +
8615 +    /* remote memory mapping   */
8616 +    VLYNQ_MEMORY_MAP remote_mem;
8617 +
8618 +    /* Local module interrupt params */
8619 +    VLYNQ_INTERRUPT_CNTRL  local_irq;
8620 +
8621 +    /* remote module interrupt params */
8622 +    VLYNQ_INTERRUPT_CNTRL  remote_irq;
8623 +
8624 +    /*** ICB related fields **/
8625 +
8626 +    /* Sizeof of ICB = VLYNQ_NUM_INT_BITS(for 32 bits in IntPending) +
8627 +     * expansion slots for shared interrupts*/
8628 +    VLYNQ_INTR_CNTRL_ICB  pIntrCB[VLYNQ_NUM_INT_BITS + VLYNQ_IVR_CHAIN_SLOTS];
8629 +    VLYNQ_INTR_CNTRL_ICB  *freelist;
8630 +
8631 +   /* table holding mapping between intVector and the bit position the interrupt
8632 +    * is mapped to(mapVector)*/
8633 +    char vector_map[32];
8634 +
8635 +    /* user callback for vlynq events, NULL if unused */
8636 +    VLYNQ_REPORT_CB        report_cb;
8637 +
8638 +   /* user callback for resetting/realeasing remote device */
8639 +    VLYNQ_RESET_REMOTE     reset_cb;
8640 +
8641 +    /*** Handles provided for direct access to register set if need be
8642 +     * Must be intialized to point to appropriate address during
8643 +     * vlynq_init */
8644 +    volatile VLYNQ_REG_SET * local;
8645 +    volatile VLYNQ_REG_SET * remote;
8646 +
8647 +    unsigned int  intCount; /* number of interrupts generated so far */
8648 +    unsigned int  isrCount; /* number of ISR invocations so far */
8649 +}VLYNQ_DEV;
8650 +
8651 +
8652 +typedef struct VLYNQ_ISR_ARGS_t
8653 +{
8654 +    int irq;
8655 +    void * arg;
8656 +    void * regset;
8657 +}VLYNQ_ISR_ARGS;
8658 +
8659 +
8660 +/****************************************
8661 + *        Function Prototypes           *
8662 + * API exported by generic vlynq driver *
8663 + ****************************************/
8664 +/* Initialization function */
8665 +int vlynq_init( VLYNQ_DEV *pdev, VLYNQ_INIT_OPTIONS options);
8666 +
8667 +/* Check vlynq link */
8668 +unsigned int vlynq_link_check( VLYNQ_DEV * pdev);
8669 +
8670 +/* Set interrupt vector in local or remote device */
8671 +int vlynq_interrupt_vector_set( VLYNQ_DEV *pdev,
8672 +                                         unsigned int int_vector,
8673 +                                         unsigned int map_vector,
8674 +                                         VLYNQ_DEV_TYPE dev,
8675 +                                         VLYNQ_INTR_POLARITY pol,
8676 +                                         VLYNQ_INTR_TYPE type);
8677 +
8678 +
8679 +int vlynq_interrupt_vector_cntl( VLYNQ_DEV *pdev,
8680 +                                          unsigned int int_vector,
8681 +                                          VLYNQ_DEV_TYPE dev,
8682 +                                          unsigned int enable);
8683 +
8684 +unsigned int vlynq_interrupt_get_count( VLYNQ_DEV *pdev,
8685 +                                         unsigned int map_vector);
8686 +
8687 +int vlynq_install_isr( VLYNQ_DEV *pdev,
8688 +                                unsigned int map_vector,
8689 +                                VLYNQ_INTR_CNTRL_ISR isr,
8690 +                                void *arg1, void *arg2, void *arg3);
8691 +
8692 +int vlynq_uninstall_isr( VLYNQ_DEV *pdev,
8693 +                                  unsigned int map_vector,
8694 +                                  void *arg1, void *arg2, void *arg3);
8695 +
8696 +
8697 +void vlynq_root_isr(void *arg);
8698 +
8699 +void vlynq_delay(unsigned int clktime);
8700 +
8701 +/* The following functions, provide better granularity in setting
8702 + * interrupt parameters. (for better support of linux INT Controller)
8703 + * Note: The interrupt source is identified by "map_vector"- the bit
8704 + * position in interrupt status register*/
8705 +
8706 +int vlynq_interrupt_vector_map(VLYNQ_DEV * pdev,
8707 +                                        VLYNQ_DEV_TYPE dev,
8708 +                                        unsigned int int_vector,
8709 +                                        unsigned int map_vector);
8710 +
8711 +int vlynq_interrupt_set_polarity(VLYNQ_DEV * pdev,
8712 +                                          VLYNQ_DEV_TYPE dev,
8713 +                                          unsigned int map_vector,
8714 +                                          VLYNQ_INTR_POLARITY pol);
8715 +
8716 +int vlynq_interrupt_get_polarity( VLYNQ_DEV *pdev ,
8717 +                                           VLYNQ_DEV_TYPE dev_type,
8718 +                                           unsigned int map_vector);
8719 +
8720 +int vlynq_interrupt_set_type(VLYNQ_DEV * pdev,
8721 +                                      VLYNQ_DEV_TYPE dev,
8722 +                                      unsigned int map_vector,
8723 +                                      VLYNQ_INTR_TYPE type);
8724 +
8725 +int vlynq_interrupt_get_type( VLYNQ_DEV *pdev,
8726 +                                       VLYNQ_DEV_TYPE dev_type,
8727 +                                       unsigned int map_vector);
8728 +
8729 +int vlynq_interrupt_enable(VLYNQ_DEV* pdev,
8730 +                                    VLYNQ_DEV_TYPE dev,
8731 +                                    unsigned int map_vector);
8732 +
8733 +int vlynq_interrupt_disable(VLYNQ_DEV * pdev,
8734 +                                     VLYNQ_DEV_TYPE dev,
8735 +                                     unsigned int map_vector);
8736 +
8737 +
8738 +
8739 +
8740 +
8741 +#endif /* _VLYNQ_HAL_H_ */
8742 diff -urN linux.old/include/asm-mips/ar7/vlynq_hal.h linux.dev/include/asm-mips/ar7/vlynq_hal.h
8743 --- linux.old/include/asm-mips/ar7/vlynq_hal.h  1970-01-01 01:00:00.000000000 +0100
8744 +++ linux.dev/include/asm-mips/ar7/vlynq_hal.h  2005-11-10 01:10:46.095590250 +0100
8745 @@ -0,0 +1,606 @@
8746 +/***************************************************************************
8747 +**+----------------------------------------------------------------------+**
8748 +**|                                ****                                  |**
8749 +**|                                ****                                  |**
8750 +**|                                ******o***                            |**
8751 +**|                          ********_///_****                           |**
8752 +**|                           ***** /_//_/ ****                          |**
8753 +**|                            ** ** (__/ ****                           |**
8754 +**|                                *********                             |**
8755 +**|                                 ****                                 |**
8756 +**|                                  ***                                 |**
8757 +**|                                                                      |**
8758 +**|     Copyright (c) 2003 Texas Instruments Incorporated                |**
8759 +**|                        ALL RIGHTS RESERVED                           |**
8760 +**|                                                                      |**
8761 +**| Permission is hereby granted to licensees of Texas Instruments       |**
8762 +**| Incorporated (TI) products to use this computer program for the sole |**
8763 +**| purpose of implementing a licensee product based on TI products.     |**
8764 +**| No other rights to reproduce, use, or disseminate this computer      |**
8765 +**| program, whether in part or in whole, are granted.                   |**
8766 +**|                                                                      |**
8767 +**| TI makes no representation or warranties with respect to the         |**
8768 +**| performance of this computer program, and specifically disclaims     |**
8769 +**| any responsibility for any damages, special or consequential,        |**
8770 +**| connected with the use of this program.                              |**
8771 +**|                                                                      |**
8772 +**+----------------------------------------------------------------------+**
8773 +***************************************************************************/
8774 +
8775 +/*********************************************************************************
8776 + *  ------------------------------------------------------------------------------
8777 + *   Module      : vlynq_hal.h
8778 + *   Description :
8779 + *   This header file provides the set of functions exported by the
8780 + *   VLYNQ HAL. This file is included from the SOC specific VLYNQ driver wrapper.
8781 + *  ------------------------------------------------------------------------------
8782 + *********************************************************************************/
8783 +
8784 +#ifndef _VLYNQ_HAL_H_
8785 +#define _VLYNQ_HAL_H_
8786 +
8787 +#include <asm/ar7/avalanche_types.h>
8788 +#include <asm/ar7/vlynq_hal_params.h>
8789 +
8790 +#ifndef PRIVATE
8791 +#define PRIVATE static
8792 +#endif
8793 +
8794 +#ifndef GLOBAL
8795 +#define GLOBAL
8796 +#endif
8797 +
8798 +/* Enable/Disable debug feature */
8799 +#undef VLYNQ_DEBUG
8800 +
8801 +#ifdef VLYNQ_DEBUG  /* This needs to be OS abstracted - for testing use vxworks/linux calls */
8802 +#define debugPrint(format,args...)
8803 +#else
8804 +#define debugPrint(format,args...)
8805 +#endif
8806 +
8807 +/* Error defines */
8808 +#define VLYNQ_SUCCESS               0
8809 +
8810 +#define VLYNQ_ERRCODE_BASE          0 /* Chosen by system */
8811 +#define VLYNQ_INVALID_ARG          -(VLYNQ_ERRCODE_BASE+1)
8812 +#define VLYNQ_INVALID_DRV_STATE    -(VLYNQ_ERRCODE_BASE+2)
8813 +#define VLYNQ_INT_CONFIG_ERR       -(VLYNQ_ERRCODE_BASE+3)
8814 +#define VLYNQ_LINK_DOWN            -(VLYNQ_ERRCODE_BASE+4)
8815 +#define VLYNQ_MEMALLOC_FAIL        -(VLYNQ_ERRCODE_BASE+5)
8816 +#define VLYNQ_ISR_NON_EXISTENT     -(VLYNQ_ERRCODE_BASE+6)
8817 +#define VLYNQ_INTVEC_MAP_NOT_FOUND -(VLYNQ_ERRCODE_BASE+7)
8818 +
8819 +/* Vlynq Defines and Macros */
8820 +
8821 +#define VLYNQ_NUM_INT_BITS              32 /* 32 bit interrupt staus register */
8822 +
8823 +/* Base address of module */
8824 +#define VLYNQ_BASE                      (pdev->module_base)
8825 +
8826 +#define VLYNQ_REMOTE_REGS_OFFSET        0x0080
8827 +
8828 +#define VLYNQ_REV_OFFSET                0x0000
8829 +#define VLYNQ_CTRL_OFFSET               0x0004
8830 +#define VLYNQ_STATUS_OFFSET             0x0008
8831 +#define VLYNQ_INT_STAT_OFFSET           0x0010
8832 +#define VLYNQ_INT_PEND_OFFSET           0x0014
8833 +#define VLYNQ_INT_PTR_OFFSET            0x0018
8834 +#define VLYNQ_TXMAP_OFFSET              0x001c
8835 +
8836 +#define VLYNQ_RX0MAP_SIZE_REG_OFFSET    0x0020
8837 +#define VLYNQ_RX0MAP_OFFSET_REG_OFFSET  0x0024
8838 +
8839 +#define VLYNQ_CHIP_VER_OFFSET           0x0040
8840 +#define VLYNQ_IVR_REGS_OFFSET           0x0060
8841 +
8842 +#define VLYNQ_INT_PENDING_REG_PTR       0x14
8843 +#define VLYNQ_R_INT_PENDING_REG_PTR     VLYNQ_REMOTE_REGS_OFFSET + 0x14
8844 +
8845 +#define VLYNQ_REV_REG       *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_REV_OFFSET))
8846 +#define VLYNQ_CTRL_REG      *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_CTRL_OFFSET))
8847 +#define VLYNQ_STATUS_REG    *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_STATUS_OFFSET))
8848 +#define VLYNQ_INT_STAT_REG  *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_INT_STAT_OFFSET))
8849 +#define VLYNQ_INT_PEND_REG  *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_INT_PEND_OFFSET))
8850 +#define VLYNQ_INT_PTR_REG   *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_INT_PTR_OFFSET))
8851 +#define VLYNQ_TXMAP_REG     *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_TXMAP_OFFSET))
8852 +
8853 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
8854 +#define VLYNQ_RXMAP_SIZE_REG(map) \
8855 +    *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_RX0MAP_SIZE_REG_OFFSET+( (map-1)<<3)))
8856 +
8857 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
8858 +#define VLYNQ_RXMAP_OFFSET_REG(map) \
8859 +    *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_RX0MAP_OFFSET_REG_OFFSET+( (map-1)<<3)))
8860 +
8861 +#define VLYNQ_CHIP_VER_REG  *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_CHIP_VER_OFFSET))
8862 +
8863 +/* 0 =< ivr <= 31; currently ivr < VLYNQ_IVR_MAXIVR=8) */
8864 +#define VLYNQ_IVR_OFFSET(ivr)  \
8865 +    (VLYNQ_BASE + VLYNQ_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3) )
8866 +
8867 +#define VLYNQ_IVR_03TO00_REG  *((volatile UINT32*) (VLYNQ_IVR_OFFSET(0)) )
8868 +#define VLYNQ_IVR_07TO04_REG  *((volatile UINT32*) (VLYNQ_IVR_OFFSET(4)) )
8869 +/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
8870 +
8871 +#define VLYNQ_IVR_INTEN(ivr)    (((UINT32)(0x80)) << ((((unsigned)(ivr)) % 4) * 8))
8872 +#define VLYNQ_IVR_INTTYPE(ivr)  (((UINT32)(0x40)) << ((((unsigned)(ivr)) % 4) * 8))
8873 +#define VLYNQ_IVR_INTPOL(ivr)   (((UINT32)(0x20)) << ((((unsigned)(ivr)) % 4) * 8))
8874 +#define VLYNQ_IVR_INTVEC(ivr)   (((UINT32)(0x1F)) << ((((unsigned)(ivr)) % 4) * 8))
8875 +#define VLYNQ_IVR_INTALL(ivr)   (((UINT32)(0xFF)) << ((((unsigned)(ivr)) % 4) * 8))
8876 +
8877 +
8878 +
8879 +/*********************************
8880 + * Remote VLYNQ register set     *
8881 + *********************************/
8882 +
8883 +#define VLYNQ_R_REV_OFFSET              0x0080
8884 +#define VLYNQ_R_CTRL_OFFSET             0x0084
8885 +#define VLYNQ_R_STATUS_OFFSET           0x0088
8886 +#define VLYNQ_R_INT_STAT_OFFSET         0x0090
8887 +#define VLYNQ_R_INT_PEND_OFFSET         0x0094
8888 +#define VLYNQ_R_INT_PTR_OFFSET          0x0098
8889 +#define VLYNQ_R_TXMAP_OFFSET            0x009c
8890 +
8891 +#define VLYNQ_R_RX0MAP_SIZE_REG_OFFSET  0x00A0
8892 +#define VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET 0x00A4
8893 +
8894 +#define VLYNQ_R_CHIP_VER_OFFSET         0x00C0
8895 +#define VLYNQ_R_IVR_REGS_OFFSET         0x00E0
8896 +
8897 +#define VLYNQ_R_REV_REG       *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_REV_OFFSET))
8898 +#define VLYNQ_R_CTRL_REG      *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_CTRL_OFFSET))
8899 +#define VLYNQ_R_STATUS_REG    *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_STATUS_OFFSET))
8900 +#define VLYNQ_R_INT_STAT_REG  *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_INT_STAT_OFFSET))
8901 +#define VLYNQ_R_INT_PEND_REG  *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_INT_PEND_OFFSET))
8902 +#define VLYNQ_R_INT_PTR_REG   *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_INT_PTR_OFFSET))
8903 +#define VLYNQ_R_TXMAP_REG     *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_TXMAP_OFFSET))
8904 +
8905 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
8906 +#define VLYNQ_R_RXMAP_SIZE_REG(map) \
8907 +    *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_SIZE_REG_OFFSET + ((map-1)<<3)))
8908 +
8909 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
8910 +#define VLYNQ_R_RXMAP_OFFSET_REG(map) \
8911 +    *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET + ((map-1)<<3)))
8912 +
8913 +#define VLYNQ_R_CHIP_VER_REG  *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_CHIP_VER_OFFSET)
8914 +
8915 +#define VLYNQ_R_IVR_OFFSET(ivr)  \
8916 +    (VLYNQ_BASE + VLYNQ_R_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3))
8917 +
8918 +
8919 +/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
8920 +#define VLYNQ_R_IVR_03TO00_REG  *((volatile UINT32*) (VLYNQ_R_IVR_OFFSET(0)) )
8921 +#define VLYNQ_R_IVR_07TO04_REG  *((volatile UINT32*) (VLYNQ_R_IVR_OFFSET(4)) )
8922 +
8923 +
8924 +/****End of remote register set definition******/
8925 +
8926 +
8927 +/*** Masks for individual register fields ***/
8928 +
8929 +#define VLYNQ_MODULE_ID_MASK        0xffff0000
8930 +#define VLYNQ_MAJOR_REV_MASK        0x0000ff00
8931 +#define VLYNQ_MINOR_REV_MASK        0x000000ff
8932 +
8933 +
8934 +#define VLYNQ_CTL_ILOOP_MASK        0x00000002
8935 +#define VLYNQ_CTL_INT2CFG_MASK      0x00000080
8936 +#define VLYNQ_CTL_INTVEC_MASK       0x00001f00
8937 +#define VLYNQ_CTL_INTEN_MASK        0x00002000
8938 +#define VLYNQ_CTL_INTLOCAL_MASK     0x00004000
8939 +#define VLYNQ_CTL_CLKDIR_MASK       0x00008000
8940 +#define VLYNQ_CTL_CLKDIV_MASK       0x00070000
8941 +#define VLYNQ_CTL_MODE_MASK         0x00e00000
8942 +
8943 +
8944 +#define VLYNQ_STS_LINK_MASK         0x00000001  /* Link is active */
8945 +#define VLYNQ_STS_MPEND_MASK        0x00000002  /* Pending master requests */
8946 +#define VLYNQ_STS_SPEND_MASK        0x00000004  /* Pending slave requests */
8947 +#define VLYNQ_STS_NFEMPTY0_MASK     0x00000008  /* Master data FIFO not empty */
8948 +#define VLYNQ_STS_NFEMPTY1_MASK     0x00000010  /* Master command FIFO not empty */
8949 +#define VLYNQ_STS_NFEMPTY2_MASK     0x00000020  /* Slave data FIFO not empty */
8950 +#define VLYNQ_STS_NFEMPTY3_MASK     0x00000040  /* Slave command FIFO not empty */
8951 +#define VLYNQ_STS_LERROR_MASK       0x00000080  /* Local error, w/c */
8952 +#define VLYNQ_STS_RERROR_MASK       0x00000100  /* remote error w/c */
8953 +#define VLYNQ_STS_OFLOW_MASK        0x00000200
8954 +#define VLYNQ_STS_IFLOW_MASK        0x00000400
8955 +#define VLYNQ_STS_MODESUP_MASK      0x00E00000  /* Highest mode supported */
8956 +#define VLYNQ_STS_SWIDTH_MASK       0x07000000  /* Used for reading the width of VLYNQ bus */
8957 +#define VLYNQ_STS_DEBUG_MASK        0xE0000000
8958 +
8959 +#define VLYNQ_CTL_INTVEC_SHIFT      0x08
8960 +#define VLYNQ_CTL_INTEN_SHIFT       0x0D
8961 +#define VLYNQ_CTL_INT2CFG_SHIFT     0x07
8962 +#define VLYNQ_CTL_INTLOCAL_SHIFT    0x0E
8963 +
8964 +#define VLYNQ_CTL_INTFIELDS_CLEAR_MASK  0x7F80
8965 +
8966 +#define VLYNQ_CHIPVER_DEVREV_MASK   0xffff0000
8967 +#define VLYNQ_CHIPVER_DEVID_MASK    0x0000ffff
8968 +
8969 +#define VLYNQ_IVR_INTEN_MASK        0x80
8970 +#define VLYNQ_IVR_INTTYPE_MASK      0x40
8971 +#define VLYNQ_IVR_INTPOL_MASK       0x20
8972 +
8973 +
8974 +/**** Helper macros ****/
8975 +
8976 +#define VLYNQ_RESETCB(arg) \
8977 +   if( pdev->reset_cb != NULL)   \
8978 +   {                             \
8979 +      (pdev->reset_cb)(pdev, (arg));  \
8980 +   }
8981 +
8982 +#define VLYNQ_STATUS_FLD_WIDTH(sts) (((sts) & VLYNQ_STS_SWIDTH_MASK) >> 24 )
8983 +#define VLYNQ_CTL_INTVEC(x)         (((x) & 31) << 8 )
8984 +
8985 +#define VLYNQ_INRANGE(x,hi,lo)      (((x) <= (hi)) && ((x) >= (lo)))
8986 +#define VLYNQ_OUTRANGE(x,hi,lo)     (((x) > (hi)) || ((x) < (lo)))
8987 +
8988 +#define VLYNQ_ALIGN4(x)             (x)=(x)&(~3)
8989 +
8990 +
8991 +/*************************************
8992 + *             Enums                 *
8993 + *************************************/
8994 +
8995 +/* Initialization options define what operations are
8996 + * undertaken during vlynq module initialization */
8997 +typedef enum
8998 +{
8999 +    /* Init host local memory regions.This allows
9000 +     * local host access remote memory regions */
9001 +    VLYNQ_INIT_LOCAL_MEM_REGIONS = 0x01,
9002 +    /* Init host remote memory regions.This allows
9003 +     * remote device access local memory regions */
9004 +    VLYNQ_INIT_REMOTE_MEM_REGIONS =0x02,
9005 +    /* Init local interrupt config*/
9006 +    VLYNQ_INIT_LOCAL_INTERRUPTS   =0x04,
9007 +    /* Init remote interrupt config*/
9008 +    VLYNQ_INIT_REMOTE_INTERRUPTS  =0x08,
9009 +    /* Check link during initialization*/
9010 +    VLYNQ_INIT_CHECK_LINK         =0x10,
9011 +    /* configure clock during init */
9012 +    VLYNQ_INIT_CONFIG_CLOCK       =0x20,
9013 +    /* Clear errors during init */
9014 +    VLYNQ_INIT_CLEAR_ERRORS       =0x40,
9015 +    /* All options */
9016 +    VLYNQ_INIT_PERFORM_ALL        =0x7F
9017 +}VLYNQ_INIT_OPTIONS;
9018 +
9019 +
9020 +/* VLYNQ_DEV_TYPE identifies local or remote device */
9021 +typedef enum
9022 +{
9023 +    VLYNQ_LOCAL_DVC  = 0,           /* vlynq local device (SOC's vlynq module) */
9024 +    VLYNQ_REMOTE_DVC = 1            /* vlynq remote device (remote vlynq module) */
9025 +}VLYNQ_DEV_TYPE;
9026 +
9027 +
9028 +/* VLYNQ_CLK_SOURCE identifies the vlynq module clock source */
9029 +typedef enum
9030 +{
9031 +    VLYNQ_CLK_SOURCE_NONE   = 0,    /* do not initialize clock generator*/
9032 +    VLYNQ_CLK_SOURCE_LOCAL  = 1,    /* clock is generated by local machine  */
9033 +    VLYNQ_CLK_SOURCE_REMOTE = 2     /* clock is generated by remote machine */
9034 +}VLYNQ_CLK_SOURCE;
9035 +
9036 +
9037 +/* VLYNQ_DRV_STATE indicates the current driver state */
9038 +typedef enum
9039 +{
9040 +    VLYNQ_DRV_STATE_UNINIT = 0,     /* driver is uninitialized  */
9041 +    VLYNQ_DRV_STATE_ININIT = 1,     /* VLYNQ is being initialized */
9042 +    VLYNQ_DRV_STATE_RUN    = 2,     /* VLYNQ is running properly  */
9043 +    VLYNQ_DRV_STATE_HOLD   = 3,     /* driver stopped temporarily */
9044 +    VLYNQ_DRV_STATE_ERROR  = 4      /* driver stopped on unrecoverable error */
9045 +}VLYNQ_DRV_STATE;
9046 +
9047 +
9048 +/* VLYNQ_BUS_WIDTH identifies the vlynq module bus width */
9049 +typedef enum
9050 +{
9051 +   VLYNQ_BUS_WIDTH_3 =  3,
9052 +   VLYNQ_BUS_WIDTH_5 =  5,
9053 +   VLYNQ_BUS_WIDTH_7 =  7,
9054 +   VLYNQ_BUS_WIDTH_9 =  9
9055 +}VLYNQ_BUS_WIDTH;
9056 +
9057 +
9058 +/* VLYNQ_LOCAL_INT_CONFIG indicates whether the local vlynq
9059 + * interrupts are processed by the host or passed on to the
9060 + * remote device.
9061 + */
9062 +typedef enum
9063 +{
9064 +    VLYNQ_INT_REMOTE = 0,   /* Interrupt packets sent to remote, intlocal=0 */
9065 +    VLYNQ_INT_LOCAL  = 1    /* Interrupts are handled locally, intlocal=1 */
9066 +}VLYNQ_LOCAL_INT_CONFIG;
9067 +
9068 +
9069 +/* VLYNQ_REMOTE_INT_CONFIG indicates whether the remote
9070 + * interrupts are to be handled by the SOC system ISR
9071 + * or via the vlynq root ISR
9072 + */
9073 +typedef enum
9074 +{
9075 +    VLYNQ_INT_ROOT_ISR   = 0,   /* remote ints handled via vlynq root ISR */
9076 +    VLYNQ_INT_SYSTEM_ISR = 1    /* remote ints handled via system ISR */
9077 +}VLYNQ_REMOTE_INT_CONFIG;
9078 +
9079 +
9080 +/* VLYNQ_INTR_POLARITY - vlynq interrupt polarity setting */
9081 +typedef enum
9082 +{
9083 +    VLYNQ_INTR_ACTIVE_HIGH = 0,
9084 +    VLYNQ_INTR_ACTIVE_LOW  = 1
9085 +}VLYNQ_INTR_POLARITY;
9086 +
9087 +
9088 +/* VLYNQ_INTR_TYPE  - vlynq interrupt type */
9089 +typedef enum
9090 +{
9091 +    VLYNQ_INTR_LEVEL  = 0,
9092 +    VLYNQ_INTR_PULSED = 1
9093 +}VLYNQ_INTR_TYPE;
9094 +
9095 +
9096 +/* VLYNQ_RESET_MODE - vlynq reset mode */
9097 +typedef enum
9098 +{
9099 +   VLYNQ_RESET_ASSERT,      /* hold device in reset state */
9100 +   VLYNQ_RESET_DEASSERT,    /* release device from reset state */
9101 +   VLYNQ_RESET_INITFAIL,    /* handle the device in case driver initialization fails */
9102 +   VLYNQ_RESET_LINKESTABLISH,  /* handle the device in case driver established link */
9103 +   VLYNQ_RESET_INITFAIL2,   /* Driver initialization failed but VLYNQ link exist. */
9104 +   VLYNQ_RESET_INITOK       /* Driver initialization finished OK. */
9105 +}VLYNQ_RESET_MODE;
9106 +
9107 +
9108 +
9109 +/*************************************
9110 + *             Typedefs              *
9111 + *************************************/
9112 +
9113 +struct VLYNQ_DEV_t; /*forward declaration*/
9114 +
9115 +/*--------Function Pointers defintions -----------*/
9116 +
9117 +/* prototype for interrupt handler definition */
9118 +typedef void (*VLYNQ_INTR_CNTRL_ISR)(void *arg1,void *arg2,void *arg3);
9119 +
9120 +typedef void
9121 +(*VLYNQ_RESET_REMOTE)(struct VLYNQ_DEV_t *pDev, VLYNQ_RESET_MODE mode);
9122 +
9123 +typedef void
9124 +(*VLYNQ_REPORT_CB)( struct VLYNQ_DEV_t *pDev,   /* This VLYNQ */
9125 +                    VLYNQ_DEV_TYPE  aSrcDvc,    /* Event Cause -local/remote? */
9126 +                    UINT32  dwStatRegVal);      /* Value of the relevant status register */
9127 +
9128 +
9129 +/*-------Structure Definitions------------*/
9130 +
9131 +typedef struct VLYNQ_MEMORY_MAP_t
9132 +{
9133 +    UINT32 Txmap;
9134 +    UINT32 RxOffset[VLYNQ_MAX_MEMORY_REGIONS];
9135 +    UINT32 RxSize[VLYNQ_MAX_MEMORY_REGIONS];
9136 +}VLYNQ_MEMORY_MAP;
9137 +
9138 +
9139 +/**VLYNQ_INTERRUPT_CNTRL - defines the vlynq module interrupt
9140 + * settings in vlynq Control register  */
9141 +typedef struct VLYNQ_INTERRUPT_CNTRL_t
9142 +{
9143 +    /* vlynq interrupts handled by host or remote - maps to
9144 +     * intLocal bit in vlynq control register */
9145 +    VLYNQ_LOCAL_INT_CONFIG intLocal;
9146 +
9147 +    /* remote interrupts handled by vlynq isr or host system
9148 +     * interrupt controller - maps to the int2Cfg in vlynq
9149 +     * control register */
9150 +    VLYNQ_REMOTE_INT_CONFIG intRemote;
9151 +
9152 +    /* bit in pending/set register used for module interrupts*/
9153 +    UINT32 map_vector;
9154 +
9155 +    /* used only if remote interrupts are to be handled by system ISR*/
9156 +    UINT32 intr_ptr;
9157 +
9158 +}VLYNQ_INTERRUPT_CNTRL;
9159 +
9160 +
9161 +/* VLYNQ_INTR_CNTRL_ICB - defines the Interrupt control block which hold
9162 + * the interrupt dispatch table. The vlynq_root_isr() indexes into this
9163 + * table to identify the ISR to be invoked
9164 + */
9165 +typedef struct VLYNQ_INTR_CNTRL_ICB_t
9166 +{
9167 +    VLYNQ_INTR_CNTRL_ISR            isr;    /* Clear errors during initialization */
9168 +    void                            *arg1 ; /* Arg 1 for the ISR */
9169 +    void                            *arg2 ; /* Arg 2 for the ISR */
9170 +    void                            *arg3 ; /* Arg 3 for the ISR */
9171 +    UINT32  isrCount; /* number of ISR invocations so far */
9172 +    struct VLYNQ_INTR_CNTRL_ICB_t   *next;
9173 +}VLYNQ_INTR_CNTRL_ICB;
9174 +
9175 +/* overlay of vlynq register set */
9176 +typedef struct VLYNQ_REG_SET_t
9177 +{
9178 +    UINT32 revision; /*offset : 0x00 */
9179 +    UINT32 control;  /* 0x04*/
9180 +    UINT32 status;   /* 0x08*/
9181 +    UINT32 pad1;     /* 0x0c*/
9182 +    UINT32 intStatus;   /*0x10*/
9183 +    UINT32 intPending;  /*0x14*/
9184 +    UINT32 intPtr;      /*0x18*/
9185 +    UINT32 txMap;       /*0x1C*/
9186 +    UINT32 rxSize1;     /*0x20*/
9187 +    UINT32 rxOffset1;   /*0x24*/
9188 +    UINT32 rxSize2;     /*0x28*/
9189 +    UINT32 rxOffset2;   /*0x2C*/
9190 +    UINT32 rxSize3;     /*0x30*/
9191 +    UINT32 rxOffset3;   /*0x34*/
9192 +    UINT32 rxSize4;     /*0x38*/
9193 +    UINT32 rxOffset4;   /*0x3C*/
9194 +    UINT32 chipVersion; /*0x40*/
9195 +    UINT32 pad2[8];
9196 +    UINT32 ivr30;       /*0x60*/
9197 +    UINT32 ivr74;       /*0x64*/
9198 +    UINT32 pad3[7];
9199 +}VLYNQ_REG_SET;
9200 +
9201 +
9202 +typedef struct VLYNQ_DEV_t
9203 +{
9204 +    /** module index:1,2,3... used for debugging purposes */
9205 +    UINT32 dev_idx;
9206 +
9207 +    /*VLYNQ module base address */
9208 +    UINT32 module_base;
9209 +
9210 +    /* clock source selection */
9211 +    VLYNQ_CLK_SOURCE clk_source;
9212 +
9213 +    /* Clock Divider.Val=1 to 8. VLYNQ_clk = VBUSCLK/clk_div */
9214 +    UINT32  clk_div;
9215 +
9216 +    /* State of the VLYNQ driver, set to VLYNQ_DRV_STATE_UNINIT, when initializing */
9217 +    VLYNQ_DRV_STATE state;
9218 +
9219 +    /* Valid VLYNQ bus width, filled by driver  */
9220 +    VLYNQ_BUS_WIDTH width;
9221 +
9222 +    /* local memory mapping   */
9223 +    VLYNQ_MEMORY_MAP local_mem;
9224 +
9225 +    /* remote memory mapping   */
9226 +    VLYNQ_MEMORY_MAP remote_mem;
9227 +
9228 +    /* Local module interrupt params */
9229 +    VLYNQ_INTERRUPT_CNTRL  local_irq;
9230 +
9231 +    /* remote module interrupt params */
9232 +    VLYNQ_INTERRUPT_CNTRL  remote_irq;
9233 +
9234 +    /*** ICB related fields **/
9235 +
9236 +    /* Sizeof of ICB = VLYNQ_NUM_INT_BITS(for 32 bits in IntPending) +
9237 +     * expansion slots for shared interrupts*/
9238 +    VLYNQ_INTR_CNTRL_ICB  pIntrCB[VLYNQ_NUM_INT_BITS + VLYNQ_IVR_CHAIN_SLOTS];
9239 +    VLYNQ_INTR_CNTRL_ICB  *freelist;
9240 +
9241 +   /* table holding mapping between intVector and the bit position the interrupt
9242 +    * is mapped to(mapVector)*/
9243 +    INT8 vector_map[32];
9244 +
9245 +    /* user callback for vlynq events, NULL if unused */
9246 +    VLYNQ_REPORT_CB        report_cb;
9247 +
9248 +   /* user callback for resetting/realeasing remote device */
9249 +    VLYNQ_RESET_REMOTE     reset_cb;
9250 +
9251 +    /*** Handles provided for direct access to register set if need be
9252 +     * Must be intialized to point to appropriate address during
9253 +     * vlynq_init */
9254 +    volatile VLYNQ_REG_SET * local;
9255 +    volatile VLYNQ_REG_SET * remote;
9256 +
9257 +    UINT32  intCount; /* number of interrupts generated so far */
9258 +    UINT32  isrCount; /* number of ISR invocations so far */
9259 +}VLYNQ_DEV;
9260 +
9261 +
9262 +typedef struct VLYNQ_ISR_ARGS_t
9263 +{
9264 +    int irq;
9265 +    void * arg;
9266 +    void * regset;
9267 +}VLYNQ_ISR_ARGS;
9268 +
9269 +
9270 +/****************************************
9271 + *        Function Prototypes           *
9272 + * API exported by generic vlynq driver *
9273 + ****************************************/
9274 +/* Initialization function */
9275 +GLOBAL INT32 vlynq_init( VLYNQ_DEV *pdev, VLYNQ_INIT_OPTIONS options);
9276 +
9277 +/* Check vlynq link */
9278 +GLOBAL UINT32 vlynq_link_check( VLYNQ_DEV * pdev);
9279 +
9280 +/* Set interrupt vector in local or remote device */
9281 +GLOBAL INT32 vlynq_interrupt_vector_set( VLYNQ_DEV *pdev,
9282 +                                         UINT32 int_vector,
9283 +                                         UINT32 map_vector,
9284 +                                         VLYNQ_DEV_TYPE dev,
9285 +                                         VLYNQ_INTR_POLARITY pol,
9286 +                                         VLYNQ_INTR_TYPE type);
9287 +
9288 +
9289 +GLOBAL INT32 vlynq_interrupt_vector_cntl( VLYNQ_DEV *pdev,
9290 +                                          UINT32 int_vector,
9291 +                                          VLYNQ_DEV_TYPE dev,
9292 +                                          UINT32 enable);
9293 +
9294 +GLOBAL UINT32 vlynq_interrupt_get_count( VLYNQ_DEV *pdev,
9295 +                                         UINT32 map_vector);
9296 +
9297 +GLOBAL INT32 vlynq_install_isr( VLYNQ_DEV *pdev,
9298 +                                UINT32 map_vector,
9299 +                                VLYNQ_INTR_CNTRL_ISR isr,
9300 +                                void *arg1, void *arg2, void *arg3);
9301 +
9302 +GLOBAL INT32 vlynq_uninstall_isr( VLYNQ_DEV *pdev,
9303 +                                  UINT32 map_vector,
9304 +                                  void *arg1, void *arg2, void *arg3);
9305 +
9306 +
9307 +GLOBAL void vlynq_root_isr(void *arg);
9308 +
9309 +GLOBAL void vlynq_delay(UINT32 clktime);
9310 +
9311 +/* The following functions, provide better granularity in setting
9312 + * interrupt parameters. (for better support of linux INT Controller)
9313 + * Note: The interrupt source is identified by "map_vector"- the bit
9314 + * position in interrupt status register*/
9315 +
9316 +GLOBAL INT32 vlynq_interrupt_vector_map(VLYNQ_DEV * pdev,
9317 +                                        VLYNQ_DEV_TYPE dev,
9318 +                                        UINT32 int_vector,
9319 +                                        UINT32 map_vector);
9320 +
9321 +GLOBAL INT32 vlynq_interrupt_set_polarity(VLYNQ_DEV * pdev,
9322 +                                          VLYNQ_DEV_TYPE dev,
9323 +                                          UINT32 map_vector,
9324 +                                          VLYNQ_INTR_POLARITY pol);
9325 +
9326 +GLOBAL INT32 vlynq_interrupt_get_polarity( VLYNQ_DEV *pdev ,
9327 +                                           VLYNQ_DEV_TYPE dev_type,
9328 +                                           UINT32 map_vector);
9329 +
9330 +GLOBAL INT32 vlynq_interrupt_set_type(VLYNQ_DEV * pdev,
9331 +                                      VLYNQ_DEV_TYPE dev,
9332 +                                      UINT32 map_vector,
9333 +                                      VLYNQ_INTR_TYPE type);
9334 +
9335 +GLOBAL INT32 vlynq_interrupt_get_type( VLYNQ_DEV *pdev,
9336 +                                       VLYNQ_DEV_TYPE dev_type,
9337 +                                       UINT32 map_vector);
9338 +
9339 +GLOBAL INT32 vlynq_interrupt_enable(VLYNQ_DEV* pdev,
9340 +                                    VLYNQ_DEV_TYPE dev,
9341 +                                    UINT32 map_vector);
9342 +
9343 +GLOBAL INT32 vlynq_interrupt_disable(VLYNQ_DEV * pdev,
9344 +                                     VLYNQ_DEV_TYPE dev,
9345 +                                     UINT32 map_vector);
9346 +
9347 +
9348 +
9349 +
9350 +
9351 +#endif /* _VLYNQ_HAL_H_ */
9352 diff -urN linux.old/include/asm-mips/ar7/vlynq_hal_params.h linux.dev/include/asm-mips/ar7/vlynq_hal_params.h
9353 --- linux.old/include/asm-mips/ar7/vlynq_hal_params.h   1970-01-01 01:00:00.000000000 +0100
9354 +++ linux.dev/include/asm-mips/ar7/vlynq_hal_params.h   2005-11-10 01:10:46.095590250 +0100
9355 @@ -0,0 +1,50 @@
9356 +/***************************************************************************
9357 +**+----------------------------------------------------------------------+**
9358 +**|                                ****                                  |**
9359 +**|                                ****                                  |**
9360 +**|                                ******o***                            |**
9361 +**|                          ********_///_****                           |**
9362 +**|                           ***** /_//_/ ****                          |**
9363 +**|                            ** ** (__/ ****                           |**
9364 +**|                                *********                             |**
9365 +**|                                 ****                                 |**
9366 +**|                                  ***                                 |**
9367 +**|                                                                      |**
9368 +**|     Copyright (c) 2003 Texas Instruments Incorporated                |**
9369 +**|                        ALL RIGHTS RESERVED                           |**
9370 +**|                                                                      |**
9371 +**| Permission is hereby granted to licensees of Texas Instruments       |**
9372 +**| Incorporated (TI) products to use this computer program for the sole |**
9373 +**| purpose of implementing a licensee product based on TI products.     |**
9374 +**| No other rights to reproduce, use, or disseminate this computer      |**
9375 +**| program, whether in part or in whole, are granted.                   |**
9376 +**|                                                                      |**
9377 +**| TI makes no representation or warranties with respect to the         |**
9378 +**| performance of this computer program, and specifically disclaims     |**
9379 +**| any responsibility for any damages, special or consequential,        |**
9380 +**| connected with the use of this program.                              |**
9381 +**|                                                                      |**
9382 +**+----------------------------------------------------------------------+**
9383 +***************************************************************************/
9384 +
9385 +/* This file defines Vlynq module parameters*/
9386 +
9387 +#ifndef _VLYNQ_HAL_PARAMS_H
9388 +#define _VLYNQ_HAL_PARAMS_H
9389 +
9390 + /* number of VLYNQ memory regions supported */
9391 +#define VLYNQ_MAX_MEMORY_REGIONS 0x04
9392 +
9393 + /* Max.number of external interrupt inputs supported by VLYNQ module */
9394 +#define VLYNQ_IVR_MAXIVR         0x08
9395 +
9396 +#define VLYNQ_CLK_DIV_MAX  0x08
9397 +#define VLYNQ_CLK_DIV_MIN  0x01
9398 +
9399 +
9400 +/*** the total number of entries allocated for ICB would be
9401 + * 32(for 32 bits in IntPending register) + VLYNQ_IVR_CHAIN_SLOTS*/
9402 +#define VLYNQ_IVR_CHAIN_SLOTS 10
9403 +
9404 +
9405 +#endif /* _VLYNQ_HAL_PARAMS_H */
9406 diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h
9407 --- linux.old/include/asm-mips/io.h     2003-08-25 13:44:43.000000000 +0200
9408 +++ linux.dev/include/asm-mips/io.h     2005-11-10 01:14:16.400733500 +0100
9409 @@ -61,9 +61,9 @@
9410   * Change "struct page" to physical address.
9411   */
9412  #ifdef CONFIG_64BIT_PHYS_ADDR
9413 -#define page_to_phys(page)     ((u64)(page - mem_map) << PAGE_SHIFT)
9414 +#define page_to_phys(page)     (((u64)(page - mem_map) << PAGE_SHIFT) + PHYS_OFFSET)
9415  #else
9416 -#define page_to_phys(page)     ((page - mem_map) << PAGE_SHIFT)
9417 +#define page_to_phys(page)     (((page - mem_map) << PAGE_SHIFT) + PHYS_OFFSET)
9418  #endif
9419
9420  #define IO_SPACE_LIMIT 0xffff
9421 diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h
9422 --- linux.old/include/asm-mips/irq.h    2003-08-25 13:44:43.000000000 +0200
9423 +++ linux.dev/include/asm-mips/irq.h    2005-11-10 01:12:43.950955750 +0100
9424 @@ -14,7 +14,20 @@
9425  #include <linux/config.h>
9426  #include <linux/linkage.h>
9427
9428 +#ifdef CONFIG_AR7
9429 +/* MIPS   has 8 irqs
9430 + * AR7    has 40 primary and 32 secondary irqs
9431 + * vlynq0 has 32 irqs
9432 + * vlynq1 has 32 irqs
9433 + */
9434 +#ifdef CONFIG_AR7_VLYNQ
9435 +#define NR_IRQS (80 + 32 * CONFIG_AR7_VLYNQ_PORTS)
9436 +#else
9437 +#define NR_IRQS 80
9438 +#endif
9439 +#else
9440  #define NR_IRQS 128            /* Largest number of ints of all machines.  */
9441 +#endif
9442
9443  #ifdef CONFIG_I8259
9444  static inline int irq_cannonicalize(int irq)
9445 diff -urN linux.old/include/asm-mips/mips-boards/prom.h linux.dev/include/asm-mips/mips-boards/prom.h
9446 --- linux.old/include/asm-mips/mips-boards/prom.h       2001-09-09 19:43:02.000000000 +0200
9447 +++ linux.dev/include/asm-mips/mips-boards/prom.h       2005-11-10 01:14:16.436735750 +0100
9448 @@ -33,7 +33,7 @@
9449  extern void prom_init_cmdline(void);
9450  extern void prom_meminit(void);
9451  extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
9452 -extern void prom_free_prom_memory (void);
9453 +extern unsigned long prom_free_prom_memory (void);
9454  extern void mips_display_message(const char *str);
9455  extern void mips_display_word(unsigned int num);
9456  extern int get_ethernet_addr(char *ethernet_addr);
9457 diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h
9458 --- linux.old/include/asm-mips/page.h   2004-02-18 14:36:32.000000000 +0100
9459 +++ linux.dev/include/asm-mips/page.h   2005-11-10 01:14:16.436735750 +0100
9460 @@ -12,6 +12,7 @@
9461
9462  #include <linux/config.h>
9463  #include <asm/break.h>
9464 +#include <asm/addrspace.h>
9465
9466  #ifdef __KERNEL__
9467
9468 @@ -129,7 +130,7 @@
9469
9470  #define __pa(x)                ((unsigned long) (x) - PAGE_OFFSET)
9471  #define __va(x)                ((void *)((unsigned long) (x) + PAGE_OFFSET))
9472 -#define virt_to_page(kaddr)    (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
9473 +#define virt_to_page(kaddr)    (mem_map + ((__pa(kaddr)-PHYS_OFFSET) >> PAGE_SHIFT))
9474  #define VALID_PAGE(page)       ((page - mem_map) < max_mapnr)
9475
9476  #define VM_DATA_DEFAULT_FLAGS  (VM_READ | VM_WRITE | VM_EXEC | \
9477 diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgtable-32.h
9478 --- linux.old/include/asm-mips/pgtable-32.h     2004-02-18 14:36:32.000000000 +0100
9479 +++ linux.dev/include/asm-mips/pgtable-32.h     2005-11-10 01:14:16.436735750 +0100
9480 @@ -108,7 +108,7 @@
9481   * and a page entry and page directory to the page they refer to.
9482   */
9483
9484 -#ifdef CONFIG_CPU_VR41XX
9485 +#if defined(CONFIG_CPU_VR41XX)
9486  #define mk_pte(page, pgprot)                                            \
9487  ({                                                                      \
9488          pte_t   __pte;                                                  \
9489 @@ -123,13 +123,14 @@
9490  ({                                                                     \
9491         pte_t   __pte;                                                  \
9492                                                                         \
9493 -       pte_val(__pte) = ((phys_t)(page - mem_map) << PAGE_SHIFT) | \
9494 -                        pgprot_val(pgprot);                            \
9495 +       pte_val(__pte) = (((phys_t)(page - mem_map) << PAGE_SHIFT) +    \
9496 +                         PHYS_OFFSET) | pgprot_val(pgprot);            \
9497                                                                         \
9498         __pte;                                                          \
9499  })
9500  #endif
9501
9502 +
9503  static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot)
9504  {
9505  #ifdef CONFIG_CPU_VR41XX
9506 @@ -175,12 +176,12 @@
9507                 set_pte(ptep, __pte(0));
9508  }
9509
9510 -#ifdef CONFIG_CPU_VR41XX
9511 +#if defined(CONFIG_CPU_VR41XX)
9512  #define pte_page(x)  (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
9513  #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
9514  #else
9515 -#define pte_page(x)  (mem_map+((unsigned long)(((x).pte_low >> PAGE_SHIFT))))
9516 -#define __mk_pte(page_nr,pgprot) __pte(((page_nr) << PAGE_SHIFT) | pgprot_val(pgprot))
9517 +#define pte_page(x)  (mem_map+((unsigned long)((((x).pte_low-PHYS_OFFSET) >> PAGE_SHIFT))))
9518 +#define __mk_pte(page_nr,pgprot) __pte((((page_nr) << PAGE_SHIFT)+PHYS_OFFSET)|pgprot_val(pgprot))
9519  #endif
9520
9521  #endif
9522 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
9523 --- linux.old/include/asm-mips/serial.h 2005-01-19 15:10:12.000000000 +0100
9524 +++ linux.dev/include/asm-mips/serial.h 2005-11-10 01:14:16.436735750 +0100
9525 @@ -65,6 +65,16 @@
9526
9527  #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
9528
9529 +#ifdef CONFIG_AR7
9530 +#include <asm/ar7/ar7.h>
9531 +#include <asm/ar7/avalanche_intc.h>
9532 +#define AR7_SERIAL_PORT_DEFNS  \
9533 +       { 0, AR7_BASE_BAUD, AR7_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
9534 +       { 0, AR7_BASE_BAUD, AR7_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
9535 +#else
9536 +#define AR7_SERIAL_PORT_DEFNS
9537 +#endif
9538 +
9539  #ifdef CONFIG_MIPS_JAZZ
9540  #define _JAZZ_SERIAL_INIT(int, base)                                   \
9541         { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,      \
9542 @@ -468,6 +478,7 @@
9543  #endif
9544
9545  #define SERIAL_PORT_DFNS                       \
9546 +       AR7_SERIAL_PORT_DEFNS                   \
9547         ATLAS_SERIAL_PORT_DEFNS                 \
9548         AU1000_SERIAL_PORT_DEFNS                \
9549         COBALT_SERIAL_PORT_DEFNS                \