target/linux/amazon-2.6/files/include/asm-mips/amazon/amazon_mei_ioctl.h

   1 //509221:tc.chen 2005/09/22 Reset DFE added when MEI_TO_ARC_CS_DONE not cleared by ARC and Added AMAZON_MEI_DEBUG_MODE ioctl
   2 #ifndef         _AMAZON_MEI_IOCTL_H
   3 #define         _AMAZON_MEI_IOCTL_H
   4
   5 /////////////////////////////////////////////////////////////////////////////////////////////////////
   6 #define PCM_BUFF_SIZE           1024 //bytes
   7 //  interrupt numbers
   8
   9 #ifndef         _AMAZON_ADSL_APP
  10
  11 typedef struct pcm_data_struct{
  12         u16 S;
  13         u16 temp;
  14         u16 LSW;
  15         u16 MSW;
  16         u16 len;
  17         u16 rdindex;
  18         u16 wrindex;
  19         u16 flow;
  20
  21         int finish;
  22         u8 buff[PCM_BUFF_SIZE];
  23         int point;
  24 }pcm_data_struct;
  25
  26 typedef struct amazon_clreoc_pkt{
  27         struct list_head list;
  28         u8 * command;           //point to clreoc command data
  29         int len;                //command length
  30 }amazon_clreoc_pkt;
  31
  32 // Number of intervals
  33 #define INTERVAL_NUM                                    192 //two days
  34 typedef struct amazon_mei_mib{
  35         struct list_head list;
  36         struct timeval start_time;      //start of current interval
  37
  38         int AtucPerfLof;
  39         int AtucPerfLos;
  40         int AtucPerfEs;
  41         int AtucPerfInit;
  42
  43         int AturPerfLof;
  44         int AturPerfLos;
  45         int AturPerfLpr;
  46         int AturPerfEs;
  47
  48         int AturChanPerfRxBlk;
  49         int AturChanPerfTxBlk;
  50         int AturChanPerfCorrBlk;
  51         int AturChanPerfUncorrBlk;
  52
  53         //RFC-3440
  54         int AtucPerfStatFastR;
  55         int AtucPerfStatFailedFastR;
  56         int AtucPerfStatSesL;
  57         int AtucPerfStatUasL;
  58         int AturPerfStatSesL;
  59         int AturPerfStatUasL;
  60 }amazon_mei_mib;
  61
  62 typedef struct adslChanPrevTxRate{
  63         u32 adslAtucChanPrevTxRate;
  64         u32 adslAturChanPrevTxRate;
  65 }adslChanPrevTxRate;
  66
  67 typedef struct adslPhysCurrStatus{
  68         u32 adslAtucCurrStatus;
  69         u32 adslAturCurrStatus;
  70 }adslPhysCurrStatus;
  71
  72 typedef struct ChanType{
  73         int interleave;
  74         int fast;
  75 // 603221:tc.chen start
  76         int bearchannel0;
  77         int bearchannel1;
  78 // 603221:tc.chen end
  79 }ChanType;
  80
  81 typedef struct mib_previous_read{
  82         u16 ATUC_PERF_ESS;
  83         u16 ATUR_PERF_ESS;
  84         u32 ATUR_CHAN_RECV_BLK;
  85         u16 ATUR_CHAN_CORR_BLK_INTL;
  86         u16 ATUR_CHAN_CORR_BLK_FAST;
  87         u16 ATUR_CHAN_UNCORR_BLK_INTL;
  88         u16 ATUR_CHAN_UNCORR_BLK_FAST;
  89         u16 ATUC_PERF_STAT_FASTR;
  90         u16 ATUC_PERF_STAT_FAILED_FASTR;
  91         u16 ATUC_PERF_STAT_SESL;
  92         u16 ATUC_PERF_STAT_UASL;
  93         u16 ATUR_PERF_STAT_SESL;
  94 }mib_previous_read;
  95
  96 typedef struct mib_flags_pretime{
  97         struct timeval ATUC_PERF_LOSS_PTIME;
  98         struct timeval ATUC_PERF_LOFS_PTIME;
  99         struct timeval ATUR_PERF_LOSS_PTIME;
 100         struct timeval ATUR_PERF_LOFS_PTIME;
 101         struct timeval ATUR_PERF_LPR_PTIME;
 102 }mib_flags_pretime;
 103
 104                 //  cmv message structures
 105 #define MP_PAYLOAD_SIZE                                 12
 106 typedef struct mpmessage{
 107         u16     iFunction;
 108         u16     iGroup;
 109         u16     iAddress;
 110         u16     iIndex;
 111         u16     iPayload[MP_PAYLOAD_SIZE];
 112 }MPMessage;
 113 #endif
 114
 115
 116 typedef struct meireg{
 117         u32 iAddress;
 118         u32 iData;
 119 }meireg;
 120
 121 #define MEIDEBUG_BUFFER_SIZES 50
 122 typedef struct meidebug{
 123         u32 iAddress;
 124         u32 iCount;
 125         u32 buffer[MEIDEBUG_BUFFER_SIZES];
 126 }meidebug;
 127
 128 //==============================================================================
 129 // Group definitions
 130 //==============================================================================
 131 #define OPTN                    5
 132 #define CNFG                    8
 133 #define CNTL                    1
 134 #define STAT                    2
 135 #define RATE                    6
 136 #define PLAM                    7
 137 #define INFO                    3
 138 #define TEST                    4
 139 //==============================================================================
 140 // Opcode definitions
 141 //==============================================================================
 142 #define H2D_CMV_READ                            0x00
 143 #define H2D_CMV_WRITE                           0x04
 144 #define H2D_CMV_INDICATE_REPLY                  0x10
 145 #define H2D_ERROR_OPCODE_UNKNOWN                0x20
 146 #define H2D_ERROR_CMV_UNKNOWN                   0x30
 147
 148 #define D2H_CMV_READ_REPLY                      0x01
 149 #define D2H_CMV_WRITE_REPLY                     0x05
 150 #define D2H_CMV_INDICATE                        0x11
 151 #define D2H_ERROR_OPCODE_UNKNOWN                0x21
 152 #define D2H_ERROR_CMV_UNKNOWN                   0x31
 153 #define D2H_ERROR_CMV_READ_NOT_AVAILABLE        0x41
 154 #define D2H_ERROR_CMV_WRITE_ONLY                0x51
 155 #define D2H_ERROR_CMV_READ_ONLY                 0x61
 156
 157 #define H2D_DEBUG_READ_DM                       0x02
 158 #define H2D_DEBUG_READ_PM                       0x06
 159 #define H2D_DEBUG_WRITE_DM                      0x0a
 160 #define H2D_DEBUG_WRITE_PM                      0x0e
 161
 162 #define D2H_DEBUG_READ_DM_REPLY                 0x03
 163 #define D2H_DEBUG_READ_FM_REPLY                 0x07
 164 #define D2H_DEBUG_WRITE_DM_REPLY                0x0b
 165 #define D2H_DEBUG_WRITE_FM_REPLY                0x0f
 166 #define D2H_ERROR_ADDR_UNKNOWN                  0x33
 167
 168 #define D2H_AUTONOMOUS_MODEM_READY_MSG          0xf1
 169 //==============================================================================
 170 // INFO register address field definitions
 171 //==============================================================================
 172
 173 #define INFO_TxState                                    0
 174 #define INFO_RxState                                    1
 175 #define INFO_TxNextState                                2
 176 #define INFO_RxNextState                                3
 177 #define INFO_TxStateJumpFrom                            4
 178 #define INFO_RxStateJumpFrom                            5
 179
 180 #define INFO_ReverbSnrBuf                               8
 181 #define INFO_ReverbEchoSnrBuf                           9
 182 #define INFO_MedleySnrBuf                               10
 183 #define INFO_RxShowtimeSnrBuf                           11
 184 #define INFO_DECdelay                                   12
 185 #define INFO_DECExponent                                13
 186 #define INFO_DECTaps                                    14
 187 #define INFO_AECdelay                                   15
 188 #define INFO_AECExponent                                16
 189 #define INFO_AECTaps                                    17
 190 #define INFO_TDQExponent                                18
 191 #define INFO_TDQTaps                                    19
 192 #define INFO_FDQExponent                                20
 193 #define INFO_FDQTaps                                    21
 194 #define INFO_USBat                                      22
 195 #define INFO_DSBat                                      23
 196 #define INFO_USFineGains                                24
 197 #define INFO_DSFineGains                                25
 198 #define INFO_BitloadFirstChannel                        26
 199 #define INFO_BitloadLastChannel                         27
 200 #define INFO_PollEOCData                                28              // CO specific
 201 #define INFO_CSNRMargin                                 29              // CO specific
 202 #define INFO_RCMsgs1                                    30
 203 #define INFO_RMsgs1                                     31
 204 #define INFO_RMsgRA                                     32
 205 #define INFO_RCMsgRA                                    33
 206 #define INFO_RMsg2                                      34
 207 #define INFO_RCMsg2                                     35
 208 #define INFO_BitLoadOK                                  36
 209 #define INFO_RCRates1                                   37
 210 #define INFO_RRates1Tab                                 38
 211 #define INFO_RMsgs1Tab                                  39
 212 #define INFO_RMsgRATab                                  40
 213 #define INFO_RRatesRA                                   41
 214 #define INFO_RCRatesRA                                  42
 215 #define INFO_RRates2                                    43
 216 #define INFO_RCRates2                                   44
 217 #define INFO_PackedRMsg2                                45
 218 #define INFO_RxBitSwapFlag                              46
 219 #define INFO_TxBitSwapFlag                              47
 220 #define INFO_ShowtimeSNRUpdateCount                     48
 221 #define INFO_ShowtimeFDQUpdateCount                     49
 222 #define INFO_ShowtimeDECUpdateCount                     50
 223 #define INFO_CopyRxBuffer                               51
 224 #define INFO_RxToneBuf                                  52
 225 #define INFO_TxToneBuf                                  53
 226 #define INFO_Version                                    54
 227 #define INFO_TimeStamp                                  55
 228 #define INFO_feVendorID                                 56
 229 #define INFO_feSerialNum                                57
 230 #define INFO_feVersionNum                               58
 231 #define INFO_BulkMemory                                 59      //Points to start of bulk memory
 232 #define INFO_neVendorID                                 60
 233 #define INFO_neVersionNum                               61
 234 #define INFO_neSerialNum                                62
 235
 236 //==============================================================================
 237 // RATE register address field definitions
 238 //==============================================================================
 239
 240
 241 #define RATE_UsRate                                     0
 242 #define RATE_DsRate                                     1
 243
 244
 245 //==============================================================================
 246 // PLAM (Physical Layer Management) register address field definitions
 247 //      (See G997.1 for reference)
 248 //==============================================================================
 249
 250
 251         //                                      ///
 252         // Failure Flags        ///
 253         //                                      ///
 254
 255 #define PLAM_NearEndFailureFlags                0
 256 #define PLAM_FarEndFailureFlags                 1
 257
 258         //                                                                      ///
 259         // Near End Failure Flags Bit Definitions       ///
 260         //                                                                      ///
 261
 262 // ADSL Failures ///
 263 #define PLAM_LOS_FailureBit                             0x0001
 264 #define PLAM_LOF_FailureBit                             0x0002
 265 #define PLAM_LPR_FailureBit                             0x0004
 266 #define PLAM_RFI_FailureBit                             0x0008
 267
 268 // ATM Failures ///
 269 #define PLAM_NCD_LP0_FailureBit                         0x0010
 270 #define PLAM_NCD_LP1_FailureBit                         0x0020
 271 #define PLAM_LCD_LP0_FailureBit                         0x0040
 272 #define PLAM_LCD_LP1_FailureBit                         0x0080
 273
 274 #define PLAM_NCD_BC0_FailureBit                         0x0100
 275 #define PLAM_NCD_BC1_FailureBit                         0x0200
 276 #define PLAM_LCD_BC0_FailureBit                         0x0400
 277 #define PLAM_LCD_BC1_FailureBit                         0x0800
 278         //                                              ///
 279         // Performance Counts   ///
 280         //                                              ///
 281
 282 #define PLAM_NearEndCrcCnt                              2
 283 #define PLAM_CorrectedRSErrors                          3
 284
 285 #define PLAM_NearEndECSCnt                              6
 286 #define PLAM_NearEndESCnt                               7
 287 #define PLAM_NearEndSESCnt                              8
 288 #define PLAM_NearEndLOSSCnt                             9
 289 #define PLAM_NearEndUASLCnt                             10
 290
 291 #define PLAM_NearEndHECErrCnt                           11
 292
 293 #define PLAM_NearEndHECTotCnt                           16
 294 #define PLAM_NearEndCellTotCnt                          18
 295 #define PLAM_NearEndSfCntLSW                            20
 296 #define PLAM_NearEndSfCntMSW                            21
 297
 298 #define PLAM_FarEndFebeCnt                              24
 299
 300 #define PLAM_FarEndFecCnt                               28
 301
 302 #define PLAM_FarEndFECSCnt                              32
 303 #define PLAM_FarEndESCnt                                33
 304 #define PLAM_FarEndSESCnt                               34
 305 #define PLAM_FarEndLOSSCnt                              35
 306 #define PLAM_FarEndUASLCnt                              36
 307
 308 #define PLAM_FarEndHECErrCnt                            37
 309
 310 #define PLAM_FarEndHECTotCnt                            41
 311
 312 #define PLAM_FarEndCellTotCnt                           43
 313
 314 #define PLAM_LineAttn                                   45
 315 #define PLAM_SNRMargin                                  46
 316
 317
 318 //==============================================================================
 319 // CNTL register address and bit field definitions
 320 //==============================================================================
 321
 322
 323 #define CNTL_ModemControl                               0
 324
 325 #define CNTL_ModemReset                                 0x0
 326 #define CNTL_ModemStart                                 0x2
 327
 328
 329 //==============================================================================
 330 // STAT register address and bit field definitions
 331 //==============================================================================
 332
 333 #define STAT_MacroState                                 0
 334 #define STAT_Mode                                       1
 335 #define STAT_DMTFramingMode                             2
 336 #define STAT_SleepState                                 3
 337 #define STAT_Misc                                       4
 338 #define STAT_FailureState                               5
 339
 340 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 341  // STAT_OLRStatus provides status of OLR
 342  //16-bit STAT_OLRStatus_DS
 343  //  [1:0]      :       OLR status 00=IDLE,  01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted
 344  //  [3:2]:             Reserved
 345  //  [5:4]:             OLR_Type (1:bitswap; 2: DRR; 3: SRA)
 346  //  [7:6]:             Reserved
 347  //  [10:8]:            >0=Request. 0=not.   For DS, # of request transmissions/retransmissions (3 bits).
 348  //  [11]:              1=Receive Response, 0=not
 349  //  [15:12]:   Reserved
 350  //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 351  ///
 352 #define STAT_OLRStatus_DS                               6
 353
 354 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 355  // STAT_OLRStatus provides status of OLR
 356  // 16-bit STAT_OLRStatus_US CMV
 357  //  [1:0]      :       OLR status 00=IDLE,  01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted
 358  //  [3:2]:             Reserved
 359  //  [5:4]:             OLR_Type (1:bitswap; 2: DRR; 3: SRA)
 360  //  [7:6]:             Reserved
 361  //  [8]:               1=Request Received. 0=not.
 362  //  [10:9]:     Reserved
 363  //  [11]:              1=Response Sent, 0=not
 364  //  [15:12]:   Reserved
 365  //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 366 ///
 367 #define STAT_OLRStatus_US                               7
 368
 369 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 370  // STAT_PMStatus provides status of PM
 371  // 16-bit STAT_PMStatus CMV
 372  //  [1:0]      :       PM Status 00=IDLE,  01=PM_IN_PROGRESS, 10=PM_Completed, 11=PM_Aborted
 373  //  [2] :              0=ATU_R initiated PM; 1 = ATU_C initiated PM
 374  //  [3]:               Reserved
 375  //  [5:4]:             PM_Type (1:Simple Request; 2: L2 request; 3: L2 trim)
 376  //  [7:6]:             Reserved
 377  //  [10:8]:            >0=Request. 0=not.   # of request transmissions/retransmissions (3 bits).
 378  //  [11]:              1=Response, 0=not
 379  //  [15:12]:   Reserved
 380  //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 381  ///
 382 #define STAT_PMStatus                                   8
 383
 384 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 385  // 16-bit STAT_OLRError_DS, STAT_OLRError_US, STAT_PMError
 386  // [3:0]:          OLR/PM response reason code
 387  // [7:4]:             OLR/PM Internal error code
 388  // [15:8]:         OLR/PM Reserved for future
 389  //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 390  ///
 391 #define STAT_OLRError_DS                                9
 392 #define STAT_OLRError_US                                10
 393 #define STAT_PMError                                    11
 394
 395
 396 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 397 // STAT_MacroState
 398 // MacroState reflects the high level state of the modem
 399
 400 #define STAT_InitState                          0x0000
 401 #define STAT_ReadyState                         0x0001
 402 #define STAT_FailState                          0x0002
 403 #define STAT_IdleState                          0x0003
 404 #define STAT_QuietState                         0x0004
 405 #define STAT_GhsState                           0x0005
 406 #define STAT_FullInitState                      0x0006
 407 #define STAT_ShowTimeState                      0x0007
 408 #define STAT_FastRetrainState                   0x0008
 409 #define STAT_LoopDiagMode                       0x0009
 410 #define STAT_ShortInit                          0x000A     // Bis short initialization ///
 411
 412 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 413 // STAT_Mode
 414 // ConfigurationMode indicates the mode of the current ADSL Link. In general, a modem may use
 415 // G.Hs or some other mechanism to negotiate the specific mode of operation.
 416 // The OPTN_modeControl CMV is used to select a set of desired modes.
 417 // The STAT_Mode CMV indicates which mode was actually selected.
 418
 419 #define STAT_ConfigMode_T1413                   0x0001
 420 #define STAT_ConfigMode_G992_2_AB               0x0002
 421 #define STAT_ConfigMode_G992_1_A                0x0004
 422 #define STAT_ConfigMode_G992_1_B                0x0008
 423 #define STAT_ConfigMode_G992_1_C                0x0010
 424 #define STAT_ConfigMode_G992_2_C                0x0020
 425
 426 #define STAT_ConfigMode_G992_3_A                0x0100
 427 #define STAT_ConfigMode_G992_3_B                0x0200
 428 #define STAT_ConfigMode_G992_3_I                0x0400
 429 #define STAT_ConfigMode_G992_3_J                0x0800
 430 #define STAT_ConfigMode_G992_3_L                0x1000
 431
 432 #define STAT_ConfigMode_G992_4_A                0x2000
 433 #define STAT_ConfigMode_G992_4_I                0x4000
 434
 435 #define STAT_ConfigMode_G992_5                  0x8000
 436
 437
 438 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 439 // STAT_DMTFramingMode
 440 // FramingMode indicates the DMT framing mde negotiated during initialization. The framing mode
 441 // status is not applicable in BIS mode and its value is undefined
 442 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 443
 444 #define STAT_FramingModeMask                    0x0003
 445
 446
 447 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 448 // STAT_Misc
 449 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 450
 451 #define STAT_OverlappedSpectrum         0x0008
 452 #define STAT_TCM                        0x0010
 453 #define STAT_TDQ_at_1104                0x0020
 454 #define STAT_T1413_Signal_Detected      0x0040
 455 #define STAT_AnnexL_US_Mask1_PSD        0x1000  //indicate we actually selected G992.3 AnnexL US PSD mask1
 456 #define STAT_AnnexL_US_Mask2_PSD        0x2000  //indicate we actually selected G992.3 AnnexL US PSD mask2
 457
 458 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 459 // STAT_FailureState
 460 // when the MacroSTate indicates the fail state, FailureState provides a failure code
 461 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 462
 463
 464 #define E_CODE_NO_ERROR                                                         0
 465 #define E_CODE_BAT_TX                                                           1               // TX BAT table is incorrect */
 466 #define E_CODE_BAT_RX                                                           2               //  RX BAT table is incorrect */
 467 #define E_CODE_PROFILE                                                          3               //  profile is not selected in fast retrain */
 468 #define E_CODE_TX_AOC_FIFO_OVERFLOW                                             4
 469 #define E_CODE_TRUNCATE_FR                                                      5               //Fast Retrain truncated due to no stored profiles*/
 470 #define E_CODE_BITLOAD                                                          6               //  bit loading fails */
 471 #define E_CODE_ST_ERROR                                                         7               //  showtime CRC error */
 472 #define E_CODE_RESERVED                                                         8       //  using parameters reserved by the ITU-T */
 473 #define E_CODE_C_TONES                                                          9               //  detected C_TONES */
 474 #define E_CODE_CODESWAP_ERR                                                     10      //  codeswap not finished in time */
 475 #define E_CODE_FIFO_OVERFLOW                                                    11      // we have run out of fifo space */
 476 #define E_CODE_C_BG_DECODE_ERR                                                  12      // error in decoding C-BG message */
 477 #define E_CODE_C_RATES2_DECODE_ERR                                              13      // error in decoding C-MSGS2 and C-RATES2 */
 478 #define E_CODE_RCMedleyRx_C_SEGUE2_Failure                                      14              //  Timeout after RCMedleyRx waiting for C_SEGUE2 */
 479 #define E_CODE_RReverbRATx_C_SEGUE2_Failure                                     15              //  Timeout after RReverbRATx waiting for C_SEGUE2 */
 480 #define E_CODE_RReverb3Tx_C_SEGUE1_Failure                                      16              //  Timeout after RReverb3Tx waiting for C_SEGUE1 */
 481 #define E_CODE_RCCRC2Rx_C_RATES1_DECOD_ERR                                      17              //  Received CRC not equal to computed CRC */
 482 #define E_CODE_RCCRC1Rx_C_RATES1_DECOD_ERR                                      18              //  Received CRC not equal to computed CRC */
 483 #define E_CODE_RReverb5Tx_C_SEGUE2_Failure                                      19              //  Timeout after RReverb5Tx waiting for C_SEGUE2 */
 484 #define E_CODE_RReverb6Tx_C_SEGUE3_Failure                                      20              //  Timeout after RReverb6Tx waiting for C_SEGUE3 */
 485 #define E_CODE_RSegue5Tx_C_SEGUE3_Failure                                       21              //  Timeout after RSegue5Tx waiting for C_SEGUE3 */
 486 #define E_CODE_RCReverb5Rx_C_SEGUE_Failure                                      22              //  Timeout after RCReverb5Rx waiting for C_SEGUE */
 487 #define E_CODE_RCReverbRARx_C_SEGUE2_Failure                                    23              //  Timeout after RCReverbRARx waiting for C_SEGUE2 */
 488 #define E_CODE_RCCRC4Rx_CMSGS2_DECOD_ERR                                        24              //  Received CRC not equal to computed CRC */
 489 #define E_CODE_RCCRC5Rx_C_BG_DECOD_ERR                                          25              //  Received CRC not equal to computed CRC */
 490 #define E_CODE_RCCRC3Rx_DECOD_ERR                                               26              //  Received CRC not equal to computed CRC */
 491 #define E_CODE_RCPilot3_DEC_PATH_DEL_TIMEOUT                                    27              //  DEC Path Delay timeout */
 492 #define E_CODE_RCPilot3_DEC_TRAINING_TIMEOUT                                    28              //  DEC Training timeout */
 493 #define E_CODE_RCReverb3Rx_C_SEGUE1_Failure                                     29              //  Timeout after RCReverb3Rx waiting for C_SEGUE1 */
 494 #define E_CODE_RCReverb2Rx_SignalEnd_Failure                                    30              //  Timeout waiting for the end of RCReverb2Rx signal */
 495 #define E_CODE_RQuiet2_SignalEnd_Failure                                        31              //  Timeout waiting for the end of RQuiet2 signal */
 496 #define E_CODE_RCReverbFR1Rx_Failure                                            32              //  Timeout waiting for the end of RCReverbFR1Rx signal */
 497 #define E_CODE_RCPilotFR1Rx_SignalEnd_Failure                                   33              //  Timeout waiting for the end of RCPilotFR1Rx signal */
 498 #define E_CODE_RCReverbFR2Rx_C_Segue_Failure                                    34              //  Timeout after RCReverbFR2Rx waiting for C_SEGUE */
 499 #define E_CODE_RCReverbFR5Rx_SignalEnd_TIMEOUT                                  35              //  Timeout waiting for the end of RCReverbFR5Rx signal */
 500 #define E_CODE_RCReverbFR6Rx_C_SEGUE_Failure                                    36              //  Timeout after RCReverbFR6Rx waiting for C_SEGUE */
 501 #define E_CODE_RCReverbFR8Rx_C_SEGUE_FR4_Failure                                37              //  Timeout after RCReverbFR8Rx waiting for C_SEGUE_FR4 */
 502 #define E_CODE_RCReverbFR8Rx_No_PROFILE                                         38              //  Timeout since no profile was selected */
 503 #define E_CODE_RCReverbFR8Rx_SignalEnd_TIMEOUT                                  39              //  Timeout waiting for the end of RCReverbFR8Rx signal */
 504 #define E_CODE_RCCRCFR1_DECOD_ERR                                               40              //  Received CRC not equal to computed CRC */
 505 #define E_CODE_RCRecovRx_SingnalEnd_TIMEOUT                                     41              //  Timeout waiting for the end of RCRecovRx signal */
 506 #define E_CODE_RSegueFR5Tx_TX_Not_Ready_TIMEOUT                                 42              //  Timeout after RSegueFR5Tx waiting for C_SEGUE2 */
 507 #define E_CODE_RRecovTx_SignalEnd_TIMEOUT                                       43              //  Timeout waiting for the end of RRecovTx signal */
 508 #define E_CODE_RCMedleyFRRx_C_SEGUE2_Failure                                    44              //  Timeout after RCMedleyFRRx waiting for C_SEGUE2 */
 509 #define E_CODE_CONFIGURATION_PARAMETERS_ERROR                                   45              // one of the configuration parameters do not meet the standard */
 510 #define E_CODE_BAD_MEM_ACCESS                                                   46
 511 #define E_CODE_BAD_INSTRUCTION_ACCESS                                           47
 512 #define E_CODE_TX_EOC_FIFO_OVERFLOW                                             48
 513 #define E_CODE_RX_EOC_FIFO_OVERFLOW                                             49
 514 #define E_CODE_GHS_CD_FLAG_TIME_OUT                                             50      // Timeout when transmitting Flag in handshake cleardown */
 515
 516
 517 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 518 //STAT_OLRStatus:
 519 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 520
 521 #define STAT_OLRPM_IDLE                                 0x0000
 522 #define STAT_OLRPM_IN_PROGRESS                          0x0001
 523 #define STAT_OLRPM_COMPLETE                             0x0002
 524 #define STAT_OLRPM_ABORTED                              0x0003
 525 #define STAT_OLRPM_RESPONSE                             0x0800
 526
 527 #define STAT_OLR_BITSWAP                                0x0010
 528 #define STAT_OLR_DRR                                    0x0020
 529 #define STAT_OLR_SRA                                    0x0030
 530
 531 //STAT_PMStatus_US:
 532 #define STAT_PM_CO_REQ                                  0x0004
 533 #define STAT_PM_SIMPLE_REQ                              0x0010
 534 #define STAT_PM_L2_REQ                                  0x0020
 535 #define STAT_PM_L2_TRIM_REQ                             0x0030
 536
 537 // STAT_OLRError_DS, STAT_OLRError_US
 538 //4 bit response reason code:
 539 #define RESP_BUSY                                       0x01
 540 #define RESP_INVALID_PARAMETERS                         0x02
 541 #define RESP_NOT_ENABLED                                0x03
 542 #define RESP_NOT_SUPPORTED                              0x04
 543
 544 //4 bit internal error code (common for OLR and PM)
 545 #define REQ_INVALID_BiGi                                0x10
 546 #define REQ_INVALID_Lp                                  0x20
 547 #define REQ_INVALID_Bpn                                 0x30
 548 #define REQ_INVALID_FRAMING_CONSTRAINT                  0x40
 549 #define REQ_NOT_IN_L0_STATE                             0x50
 550 #define REQ_NOT_IN_L2_STATE                             0x60
 551 #define REQ_INVALID_PCB                                 0x70
 552 #define REQ_VIOLATES_MARGIN                             0x80
 553
 554 //STAT_PMError
 555 //4 bit response reason code:
 556 #define RESP_STATE_NOT_DESIRED                          0x03
 557 #define RESP_INFEASIBLE_PARAMETERS                      0x04
 558
 559
 560
 561 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 562 // OPTN register address and bit field definitions
 563 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 564
 565 #define OPTN_ModeControl                                0
 566 #define OPTN_DMTLnkCtl                                  1
 567 // Reserved                                             2
 568 #define OPTN_GhsControl                                 3
 569 // Reserved                                             4
 570 #define OPTN_PwrManControl                              5
 571 #define OPTN_AnnexControl                               6
 572 #define OPTN_ModeControl1                               7
 573 // Reserved                                             8
 574 #define OPTN_StateMachineCtrl                           9
 575 // Reserved                                             10
 576 // Reserved                                             11
 577 #define OPTN_BisLinkControl                             12
 578 #define OPTN_ATMAddrConfig                              13
 579 #define OPTN_ATMNumCellConfig                           14
 580
 581 // Mode control defines the allowable operating modes of an ADSL link. In general, a modem may ///
 582 // use G.Hs or some other mechanism to negotiate the specific mode of operation. ///
 583 // The OPTN_ModeControl CMV is used to select a set of desired modes ///
 584 // The STAT_ModeControl CMV indicates which mode was actually selected ///
 585
 586 // OPTN_ModeControl
 587 #define OPTN_ConfigMode_T1413                   0x0001
 588 #define OPTN_ConfigMode_G992_2_AB               0x0002
 589 #define OPTN_ConfigMode_G992_1_A                0x0004
 590 #define OPTN_ConfigMode_G992_1_B                0x0008
 591 #define OPTN_ConfigMode_G992_1_C                0x0010
 592 #define OPTN_ConfigMode_G992_2_C                0x0020
 593
 594 #define OPTN_ConfigMode_G992_3_A                0x0100
 595 #define OPTN_ConfigMode_G992_3_B                0x0200
 596 #define OPTN_ConfigMode_G992_3_I                0x0400
 597 #define OPTN_ConfigMode_G992_3_J                0x0800
 598 #define OPTN_ConfigMode_G992_3_L                0x1000
 599
 600 #define OPTN_ConfigMode_G992_4_A                0x2000
 601 #define OPTN_ConfigMode_G992_4_I                0x4000
 602
 603 #define OPTN_ConfigMode_G992_5                  0x8000
 604
 605 // OPTN_PwrManControl
 606 #define OPTN_PwrManWakeUpGhs                    0x1
 607 #define OPTN_PwrManWakeUpFR                     0x2
 608
 609 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 610 // OPTN_DMT Link Control
 611 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 612 #define OPTN_DMT_DualLatency_Dis                0x200
 613 #define OPTN_DMT_S_Dis                          0x100
 614 #define OPTN_DMT_FRAMINGMODE                    0x1
 615 #define OPTN_DMT_FRAMINGMODE_MASK               0x7
 616
 617 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 618 // OPTN_BIS Link Control
 619 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 620 #define OPTN_BisLinkContrl_LineProbeDis         0x1
 621 #define OPTN_BisLinkContrl_DSBlackBitsEn        0x2
 622 #define OPTN_BisLinkContrl_DiagnosticModeEn     0x4
 623 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 624 // OPTN_GhsControl
 625 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 626 //
 627 // for OPTN_GhsControl, we will assign 16bit word as follows
 628 // bit 0~3: set the control over which start(initial) message CPE will send:
 629 //
 630 //              BIT: 2  1  0
 631 //                       0  0  1  CLR
 632 //                       0  1  0  MR
 633 //                       0  1  1  MS
 634 //                       1  0  0  MP
 635 //
 636 //  // bit 4~6: set the control over which message will be sent when we get at lease one CL/CLR exchange
 637 //        BIT: 5  4
 638 //                   0  1  MS
 639 //                       1  0  MR
 640 //                       1  1  MP
 641 //
 642 //  // bit 15: RT initiated G.hs sample sessions one through eight.  Session one is default.
 643 //        BIT: 15
 644 //                        1  means session one
 645 //
 646 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 647
 648 #define OPTN_GHS_ST_GHS                                 0x8000
 649 #define OPTN_GHS_INIT_MASK                              0x000F
 650 #define OPTN_GHS_RESP_MASK                              0x00F0
 651
 652 #define OPTN_RTInitTxMsg_CLR                            0x0001
 653 #define OPTN_RTInitTxMsg_MR                             0x0002
 654 #define OPTN_RTInitTxMsg_MS                             0x0003
 655 #define OPTN_RTInitTxMsg_MP                             0x0004
 656
 657 #define OPTN_RTRespTxMsg_MS                             0x0010
 658 #define OPTN_RTRespTxMsg_MR                             0x0020
 659 #define OPTN_RTRespTxMsg_MP                             0x0030
 660
 661 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 662 //      OPTN_AnnexControl
 663 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 664
 665
 666 // G.992.3 Annex A/L1/L2 US PSD Mask preferred
 667
 668 #define OPTN_G992_3_AnnexA_PreferredModeMask            0x3000
 669 #define OPTN_G992_3_AnnexA_PreferredModeA               0x0000         // default AnnexA PSD mask ///
 670 #define OPTN_G992_3_AnnexA_PreferredModeL1              0x1000             // AnnexL wide spectrum upstream PSD mask ///
 671 #define OPTN_G992_3_AnnexA_PreferredModeL2              0x2000             // AnnexL narrow spectrum upstream PSD mask ///
 672
 673
 674 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 675 //OPTN_ATMAddrConfig
 676 // Bits 4:0             are Utopia address for BC1
 677 // Bits 9:5             are Utopia address for BC0
 678 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 679
 680 #define OPTN_UTPADDR_BC1                                0x001F
 681 #define OPTN_UTPADDR_BC0                                0x03E0
 682
 683 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 684 //OPTN_ATMNumCellConfig
 685 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 686
 687 #define OPTN_BC1_NUM_CELL_PAGES                         0x000F // Bits 0:3 ///
 688 #define OPTN_BC0_NUM_CELL_PAGES                         0x00F0 // Bits 4:7 ///
 689
 690
 691 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 692 // CNFG register address field ///
 693 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 694
 695 ///////////////////////////////////////////
 696 // these cmvs are used by bis handshake ///
 697 ///////////////////////////////////////////
 698
 699 // Each of the CNFG_TPS entries points to a structure of type (TPS_TC_BearerChannel_t)
 700 #define CNFG_TPS_TC_DS0                                 0
 701 #define CNFG_TPS_TC_DS1                                 1
 702 #define CNFG_TPS_TC_US0                                 2
 703 #define CNFG_TPS_TC_US1                                 3
 704
 705 #define CNFG_HDLC_Overhead_Requirements                 4
 706
 707 // Each of the CNFG_PMS entries points to a structure of type (PMS_TC_LatencyPath_t)
 708 #define CNFG_PMS_TC_DS0                                 5
 709 #define CNFG_PMS_TC_DS1                                 6
 710 #define CNFG_PMS_TC_US0                                 7
 711 #define CNFG_PMS_TC_US1                                 8
 712
 713 // CNFG_PMD_PARAMETERS points to a structure of type (PMD_params_t)
 714 #define CNFG_PMD_PARAMETERS                             9
 715
 716 ////////////////////////////////////////////////////////////
 717 // these cmvs are used by bis training and showtime code ///
 718 ////////////////////////////////////////////////////////////
 719
 720 ////////////////
 721 // Tx Config ///
 722 ////////////////
 723 #define CNFG_tx_Cnfg_Nbc                                10
 724 #define CNFG_tx_Cnfg_Nlp                                11
 725 #define CNFG_tx_Cnfg_Rp                                 12
 726 #define CNFG_tx_Cnfg_Mp                                 13
 727 #define CNFG_tx_Cnfg_Lp                                 14
 728 #define CNFG_tx_Cnfg_Tp                                 15
 729 #define CNFG_tx_Cnfg_Dp                                 16
 730 #define CNFG_tx_Cnfg_Bpn                                17
 731 #define CNFG_tx_Cnfg_FramingMode                        18
 732 #define CNFG_tx_Cnfg_MSGLp                              19
 733 #define CNFG_tx_Cnfg_MSGc                               20
 734
 735
 736 ////////////////
 737 // Rx Config ///
 738 ////////////////
 739 #define CNFG_rx_Cnfg_Nbc                                21
 740 #define CNFG_rx_Cnfg_Nlp                                22
 741 #define CNFG_rx_Cnfg_Rp                                 23
 742 #define CNFG_rx_Cnfg_Mp                                 24
 743 #define CNFG_rx_Cnfg_Lp                                 25
 744 #define CNFG_rx_Cnfg_Tp                                 26
 745 #define CNFG_rx_Cnfg_Dp                                 27
 746 #define CNFG_rx_Cnfg_Bpn                                28
 747 #define CNFG_rx_Cnfg_FramingMode                        29
 748 #define CNFG_rx_Cnfg_MSGLp                              30
 749 #define CNFG_rx_Cnfg_MSGc                               31
 750
 751 #define CNFG_tx_Cnfg_BCnToLPp                           32
 752 #define CNFG_rx_Cnfg_BCnToLPp                           33
 753
 754
 755
 756 #endif
 757