1 /* Settings for Denali DDR SDRAM controller */
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2 /* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
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4 #define MC_DC0_VALUE 0x1B1B
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5 #define MC_DC1_VALUE 0x0
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6 #define MC_DC2_VALUE 0x0
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7 #define MC_DC3_VALUE 0x0
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8 #define MC_DC4_VALUE 0x0
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9 #define MC_DC5_VALUE 0x200
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10 #define MC_DC6_VALUE 0x306
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11 #define MC_DC7_VALUE 0x303
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12 #define MC_DC8_VALUE 0x102
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13 #define MC_DC9_VALUE 0x80B
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14 #define MC_DC10_VALUE 0x203
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15 #define MC_DC11_VALUE 0xD02
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16 #define MC_DC12_VALUE 0x1C8
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17 #define MC_DC13_VALUE 0x1
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18 #define MC_DC14_VALUE 0x0
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19 #define MC_DC15_VALUE 0x144 /* WDQS tuning for clk_wr*/
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20 #define MC_DC16_VALUE 0xC800
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21 #define MC_DC17_VALUE 0xF
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22 #define MC_DC18_VALUE 0x301
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23 #define MC_DC19_VALUE 0x200
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24 #define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
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25 #define MC_DC21_VALUE 0x1200
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26 #define MC_DC22_VALUE 0x1212
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27 #define MC_DC23_VALUE 0x0
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28 #define MC_DC24_VALUE 0x66 /* WDQS Tuning for DQS */
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29 #define MC_DC25_VALUE 0x0
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30 #define MC_DC26_VALUE 0x0
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31 #define MC_DC27_VALUE 0x0
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32 #define MC_DC28_VALUE 0x5FB
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33 #define MC_DC29_VALUE 0x35DF
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34 #define MC_DC30_VALUE 0x99E9
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35 #define MC_DC31_VALUE 0x0
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36 #define MC_DC32_VALUE 0x0
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37 #define MC_DC33_VALUE 0x0
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38 #define MC_DC34_VALUE 0x0
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39 #define MC_DC35_VALUE 0x0
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40 #define MC_DC36_VALUE 0x0
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41 #define MC_DC37_VALUE 0x0
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42 #define MC_DC38_VALUE 0x0
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43 #define MC_DC39_VALUE 0x0
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44 #define MC_DC40_VALUE 0x0
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45 #define MC_DC41_VALUE 0x0
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46 #define MC_DC42_VALUE 0x0
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47 #define MC_DC43_VALUE 0x0
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48 #define MC_DC44_VALUE 0x0
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49 #define MC_DC45_VALUE 0x600
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50 //#define MC_DC45_VALUE 0x400
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51 #define MC_DC46_VALUE 0x0
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projects / openwrt.git / blob